FSTAT - Flash Status Register
#define	FTFE_FSTAT_MGSTAT0_MASK (0x1U)

#define	FTFE_FSTAT_MGSTAT0_SHIFT (0U)

#define	FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)

#define	FTFE_FSTAT_FPVIOL_MASK (0x10U)

#define	FTFE_FSTAT_FPVIOL_SHIFT (4U)

#define	FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)

#define	FTFE_FSTAT_ACCERR_MASK (0x20U)

#define	FTFE_FSTAT_ACCERR_SHIFT (5U)

#define	FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)

#define	FTFE_FSTAT_RDCOLERR_MASK (0x40U)

#define	FTFE_FSTAT_RDCOLERR_SHIFT (6U)

#define	FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)

#define	FTFE_FSTAT_CCIF_MASK (0x80U)

#define	FTFE_FSTAT_CCIF_SHIFT (7U)

#define	FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)

#define	FTFE_FSTAT_MGSTAT0_MASK (0x1U)

#define	FTFE_FSTAT_MGSTAT0_SHIFT (0U)

#define	FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)

#define	FTFE_FSTAT_FPVIOL_MASK (0x10U)

#define	FTFE_FSTAT_FPVIOL_SHIFT (4U)

#define	FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)

#define	FTFE_FSTAT_ACCERR_MASK (0x20U)

#define	FTFE_FSTAT_ACCERR_SHIFT (5U)

#define	FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)

#define	FTFE_FSTAT_RDCOLERR_MASK (0x40U)

#define	FTFE_FSTAT_RDCOLERR_SHIFT (6U)

#define	FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)

#define	FTFE_FSTAT_CCIF_MASK (0x80U)

#define	FTFE_FSTAT_CCIF_SHIFT (7U)

#define	FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)

#define	FTFE_FSTAT_MGSTAT0_MASK (0x1U)

#define	FTFE_FSTAT_MGSTAT0_SHIFT (0U)

#define	FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)

#define	FTFE_FSTAT_FPVIOL_MASK (0x10U)

#define	FTFE_FSTAT_FPVIOL_SHIFT (4U)

#define	FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)

#define	FTFE_FSTAT_ACCERR_MASK (0x20U)

#define	FTFE_FSTAT_ACCERR_SHIFT (5U)

#define	FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)

#define	FTFE_FSTAT_RDCOLERR_MASK (0x40U)

#define	FTFE_FSTAT_RDCOLERR_SHIFT (6U)

#define	FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)

#define	FTFE_FSTAT_CCIF_MASK (0x80U)

#define	FTFE_FSTAT_CCIF_SHIFT (7U)

#define	FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)

#define	FTFE_FSTAT_MGSTAT0_MASK (0x1U)

#define	FTFE_FSTAT_MGSTAT0_SHIFT (0U)

#define	FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)

#define	FTFE_FSTAT_FPVIOL_MASK (0x10U)

#define	FTFE_FSTAT_FPVIOL_SHIFT (4U)

#define	FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)

#define	FTFE_FSTAT_ACCERR_MASK (0x20U)

#define	FTFE_FSTAT_ACCERR_SHIFT (5U)

#define	FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)

#define	FTFE_FSTAT_RDCOLERR_MASK (0x40U)

#define	FTFE_FSTAT_RDCOLERR_SHIFT (6U)

#define	FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)

#define	FTFE_FSTAT_CCIF_MASK (0x80U)

#define	FTFE_FSTAT_CCIF_SHIFT (7U)

#define	FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)

FCNFG - Flash Configuration Register
#define	FTFE_FCNFG_EEERDY_MASK (0x1U)

#define	FTFE_FCNFG_EEERDY_SHIFT (0U)

#define	FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)

#define	FTFE_FCNFG_RAMRDY_MASK (0x2U)

#define	FTFE_FCNFG_RAMRDY_SHIFT (1U)

#define	FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)

#define	FTFE_FCNFG_PFLSH_MASK (0x4U)

#define	FTFE_FCNFG_PFLSH_SHIFT (2U)

#define	FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)

#define	FTFE_FCNFG_ERSSUSP_MASK (0x10U)

#define	FTFE_FCNFG_ERSSUSP_SHIFT (4U)

#define	FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)

#define	FTFE_FCNFG_ERSAREQ_MASK (0x20U)

#define	FTFE_FCNFG_ERSAREQ_SHIFT (5U)

#define	FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)

#define	FTFE_FCNFG_RDCOLLIE_MASK (0x40U)

#define	FTFE_FCNFG_RDCOLLIE_SHIFT (6U)

#define	FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)

#define	FTFE_FCNFG_CCIE_MASK (0x80U)

#define	FTFE_FCNFG_CCIE_SHIFT (7U)

#define	FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)

#define	FTFE_FCNFG_EEERDY_MASK (0x1U)

#define	FTFE_FCNFG_EEERDY_SHIFT (0U)

#define	FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)

#define	FTFE_FCNFG_RAMRDY_MASK (0x2U)

#define	FTFE_FCNFG_RAMRDY_SHIFT (1U)

#define	FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)

#define	FTFE_FCNFG_PFLSH_MASK (0x4U)

#define	FTFE_FCNFG_PFLSH_SHIFT (2U)

#define	FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)

#define	FTFE_FCNFG_ERSSUSP_MASK (0x10U)

#define	FTFE_FCNFG_ERSSUSP_SHIFT (4U)

#define	FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)

#define	FTFE_FCNFG_ERSAREQ_MASK (0x20U)

#define	FTFE_FCNFG_ERSAREQ_SHIFT (5U)

#define	FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)

#define	FTFE_FCNFG_RDCOLLIE_MASK (0x40U)

#define	FTFE_FCNFG_RDCOLLIE_SHIFT (6U)

#define	FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)

#define	FTFE_FCNFG_CCIE_MASK (0x80U)

#define	FTFE_FCNFG_CCIE_SHIFT (7U)

#define	FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)

#define	FTFE_FCNFG_EEERDY_MASK (0x1U)

#define	FTFE_FCNFG_EEERDY_SHIFT (0U)

#define	FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)

#define	FTFE_FCNFG_RAMRDY_MASK (0x2U)

#define	FTFE_FCNFG_RAMRDY_SHIFT (1U)

#define	FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)

#define	FTFE_FCNFG_PFLSH_MASK (0x4U)

#define	FTFE_FCNFG_PFLSH_SHIFT (2U)

#define	FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)

#define	FTFE_FCNFG_ERSSUSP_MASK (0x10U)

#define	FTFE_FCNFG_ERSSUSP_SHIFT (4U)

#define	FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)

#define	FTFE_FCNFG_ERSAREQ_MASK (0x20U)

#define	FTFE_FCNFG_ERSAREQ_SHIFT (5U)

#define	FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)

#define	FTFE_FCNFG_RDCOLLIE_MASK (0x40U)

#define	FTFE_FCNFG_RDCOLLIE_SHIFT (6U)

#define	FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)

#define	FTFE_FCNFG_CCIE_MASK (0x80U)

#define	FTFE_FCNFG_CCIE_SHIFT (7U)

#define	FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)

#define	FTFE_FCNFG_EEERDY_MASK (0x1U)

#define	FTFE_FCNFG_EEERDY_SHIFT (0U)

#define	FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)

#define	FTFE_FCNFG_RAMRDY_MASK (0x2U)

#define	FTFE_FCNFG_RAMRDY_SHIFT (1U)

#define	FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)

#define	FTFE_FCNFG_PFLSH_MASK (0x4U)

#define	FTFE_FCNFG_PFLSH_SHIFT (2U)

#define	FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)

#define	FTFE_FCNFG_ERSSUSP_MASK (0x10U)

#define	FTFE_FCNFG_ERSSUSP_SHIFT (4U)

#define	FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)

#define	FTFE_FCNFG_ERSAREQ_MASK (0x20U)

#define	FTFE_FCNFG_ERSAREQ_SHIFT (5U)

#define	FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)

#define	FTFE_FCNFG_RDCOLLIE_MASK (0x40U)

#define	FTFE_FCNFG_RDCOLLIE_SHIFT (6U)

#define	FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)

#define	FTFE_FCNFG_CCIE_MASK (0x80U)

#define	FTFE_FCNFG_CCIE_SHIFT (7U)

#define	FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)

FCNFG - Flash Configuration Register
#define	FTFE_FCNFG_SWAP_MASK (0x8U)

#define	FTFE_FCNFG_SWAP_SHIFT (3U)

#define	FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)

#define	FTFE_FCNFG_SWAP_MASK (0x8U)

#define	FTFE_FCNFG_SWAP_SHIFT (3U)

#define	FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)

#define	FTFE_FCNFG_SWAP_MASK (0x8U)

#define	FTFE_FCNFG_SWAP_SHIFT (3U)

#define	FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)

FSEC - Flash Security Register
#define	FTFE_FSEC_SEC_MASK (0x3U)

#define	FTFE_FSEC_SEC_SHIFT (0U)

#define	FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)

#define	FTFE_FSEC_FSLACC_MASK (0xCU)

#define	FTFE_FSEC_FSLACC_SHIFT (2U)

#define	FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)

#define	FTFE_FSEC_MEEN_MASK (0x30U)

#define	FTFE_FSEC_MEEN_SHIFT (4U)

#define	FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)

#define	FTFE_FSEC_KEYEN_MASK (0xC0U)

#define	FTFE_FSEC_KEYEN_SHIFT (6U)

#define	FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)

#define	FTFE_FSEC_SEC_MASK (0x3U)

#define	FTFE_FSEC_SEC_SHIFT (0U)

#define	FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)

#define	FTFE_FSEC_FSLACC_MASK (0xCU)

#define	FTFE_FSEC_FSLACC_SHIFT (2U)

#define	FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)

#define	FTFE_FSEC_MEEN_MASK (0x30U)

#define	FTFE_FSEC_MEEN_SHIFT (4U)

#define	FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)

#define	FTFE_FSEC_KEYEN_MASK (0xC0U)

#define	FTFE_FSEC_KEYEN_SHIFT (6U)

#define	FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)

#define	FTFE_FSEC_SEC_MASK (0x3U)

#define	FTFE_FSEC_SEC_SHIFT (0U)

#define	FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)

#define	FTFE_FSEC_FSLACC_MASK (0xCU)

#define	FTFE_FSEC_FSLACC_SHIFT (2U)

#define	FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)

#define	FTFE_FSEC_MEEN_MASK (0x30U)

#define	FTFE_FSEC_MEEN_SHIFT (4U)

#define	FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)

#define	FTFE_FSEC_KEYEN_MASK (0xC0U)

#define	FTFE_FSEC_KEYEN_SHIFT (6U)

#define	FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)

#define	FTFE_FSEC_SEC_MASK (0x3U)

#define	FTFE_FSEC_SEC_SHIFT (0U)

#define	FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)

#define	FTFE_FSEC_FSLACC_MASK (0xCU)

#define	FTFE_FSEC_FSLACC_SHIFT (2U)

#define	FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)

#define	FTFE_FSEC_MEEN_MASK (0x30U)

#define	FTFE_FSEC_MEEN_SHIFT (4U)

#define	FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)

#define	FTFE_FSEC_KEYEN_MASK (0xC0U)

#define	FTFE_FSEC_KEYEN_SHIFT (6U)

#define	FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)

FOPT - Flash Option Register
#define	FTFE_FOPT_OPT_MASK (0xFFU)

#define	FTFE_FOPT_OPT_SHIFT (0U)

#define	FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)

#define	FTFE_FOPT_OPT_MASK (0xFFU)

#define	FTFE_FOPT_OPT_SHIFT (0U)

#define	FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)

#define	FTFE_FOPT_OPT_MASK (0xFFU)

#define	FTFE_FOPT_OPT_SHIFT (0U)

#define	FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)

#define	FTFE_FOPT_OPT_MASK (0xFFU)

#define	FTFE_FOPT_OPT_SHIFT (0U)

#define	FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)

FCCOB3 - Flash Common Command Object Registers
#define	FTFE_FCCOB3_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB3_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)

#define	FTFE_FCCOB3_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB3_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)

#define	FTFE_FCCOB3_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB3_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)

#define	FTFE_FCCOB3_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB3_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)

FCCOB2 - Flash Common Command Object Registers
#define	FTFE_FCCOB2_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB2_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)

#define	FTFE_FCCOB2_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB2_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)

#define	FTFE_FCCOB2_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB2_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)

#define	FTFE_FCCOB2_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB2_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)

FCCOB1 - Flash Common Command Object Registers
#define	FTFE_FCCOB1_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB1_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)

#define	FTFE_FCCOB1_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB1_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)

#define	FTFE_FCCOB1_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB1_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)

#define	FTFE_FCCOB1_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB1_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)

FCCOB0 - Flash Common Command Object Registers
#define	FTFE_FCCOB0_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB0_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)

#define	FTFE_FCCOB0_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB0_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)

#define	FTFE_FCCOB0_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB0_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)

#define	FTFE_FCCOB0_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB0_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)

FCCOB7 - Flash Common Command Object Registers
#define	FTFE_FCCOB7_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB7_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)

#define	FTFE_FCCOB7_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB7_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)

#define	FTFE_FCCOB7_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB7_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)

#define	FTFE_FCCOB7_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB7_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)

FCCOB6 - Flash Common Command Object Registers
#define	FTFE_FCCOB6_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB6_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)

#define	FTFE_FCCOB6_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB6_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)

#define	FTFE_FCCOB6_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB6_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)

#define	FTFE_FCCOB6_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB6_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)

FCCOB5 - Flash Common Command Object Registers
#define	FTFE_FCCOB5_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB5_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)

#define	FTFE_FCCOB5_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB5_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)

#define	FTFE_FCCOB5_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB5_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)

#define	FTFE_FCCOB5_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB5_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)

FCCOB4 - Flash Common Command Object Registers
#define	FTFE_FCCOB4_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB4_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)

#define	FTFE_FCCOB4_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB4_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)

#define	FTFE_FCCOB4_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB4_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)

#define	FTFE_FCCOB4_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB4_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)

FCCOBB - Flash Common Command Object Registers
#define	FTFE_FCCOBB_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOBB_CCOBn_SHIFT (0U)

#define	FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)

#define	FTFE_FCCOBB_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOBB_CCOBn_SHIFT (0U)

#define	FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)

#define	FTFE_FCCOBB_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOBB_CCOBn_SHIFT (0U)

#define	FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)

#define	FTFE_FCCOBB_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOBB_CCOBn_SHIFT (0U)

#define	FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)

FCCOBA - Flash Common Command Object Registers
#define	FTFE_FCCOBA_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOBA_CCOBn_SHIFT (0U)

#define	FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)

#define	FTFE_FCCOBA_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOBA_CCOBn_SHIFT (0U)

#define	FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)

#define	FTFE_FCCOBA_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOBA_CCOBn_SHIFT (0U)

#define	FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)

#define	FTFE_FCCOBA_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOBA_CCOBn_SHIFT (0U)

#define	FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)

FCCOB9 - Flash Common Command Object Registers
#define	FTFE_FCCOB9_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB9_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)

#define	FTFE_FCCOB9_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB9_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)

#define	FTFE_FCCOB9_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB9_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)

#define	FTFE_FCCOB9_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB9_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)

FCCOB8 - Flash Common Command Object Registers
#define	FTFE_FCCOB8_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB8_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)

#define	FTFE_FCCOB8_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB8_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)

#define	FTFE_FCCOB8_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB8_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)

#define	FTFE_FCCOB8_CCOBn_MASK (0xFFU)

#define	FTFE_FCCOB8_CCOBn_SHIFT (0U)

#define	FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)

FPROT3 - Program Flash Protection Registers
#define	FTFE_FPROT3_PROT_MASK (0xFFU)

#define	FTFE_FPROT3_PROT_SHIFT (0U)

#define	FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)

#define	FTFE_FPROT3_PROT_MASK (0xFFU)

#define	FTFE_FPROT3_PROT_SHIFT (0U)

#define	FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)

#define	FTFE_FPROT3_PROT_MASK (0xFFU)

#define	FTFE_FPROT3_PROT_SHIFT (0U)

#define	FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)

#define	FTFE_FPROT3_PROT_MASK (0xFFU)

#define	FTFE_FPROT3_PROT_SHIFT (0U)

#define	FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)

FPROT2 - Program Flash Protection Registers
#define	FTFE_FPROT2_PROT_MASK (0xFFU)

#define	FTFE_FPROT2_PROT_SHIFT (0U)

#define	FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)

#define	FTFE_FPROT2_PROT_MASK (0xFFU)

#define	FTFE_FPROT2_PROT_SHIFT (0U)

#define	FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)

#define	FTFE_FPROT2_PROT_MASK (0xFFU)

#define	FTFE_FPROT2_PROT_SHIFT (0U)

#define	FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)

#define	FTFE_FPROT2_PROT_MASK (0xFFU)

#define	FTFE_FPROT2_PROT_SHIFT (0U)

#define	FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)

FPROT1 - Program Flash Protection Registers
#define	FTFE_FPROT1_PROT_MASK (0xFFU)

#define	FTFE_FPROT1_PROT_SHIFT (0U)

#define	FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)

#define	FTFE_FPROT1_PROT_MASK (0xFFU)

#define	FTFE_FPROT1_PROT_SHIFT (0U)

#define	FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)

#define	FTFE_FPROT1_PROT_MASK (0xFFU)

#define	FTFE_FPROT1_PROT_SHIFT (0U)

#define	FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)

#define	FTFE_FPROT1_PROT_MASK (0xFFU)

#define	FTFE_FPROT1_PROT_SHIFT (0U)

#define	FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)

FPROT0 - Program Flash Protection Registers
#define	FTFE_FPROT0_PROT_MASK (0xFFU)

#define	FTFE_FPROT0_PROT_SHIFT (0U)

#define	FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)

#define	FTFE_FPROT0_PROT_MASK (0xFFU)

#define	FTFE_FPROT0_PROT_SHIFT (0U)

#define	FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)

#define	FTFE_FPROT0_PROT_MASK (0xFFU)

#define	FTFE_FPROT0_PROT_SHIFT (0U)

#define	FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)

#define	FTFE_FPROT0_PROT_MASK (0xFFU)

#define	FTFE_FPROT0_PROT_SHIFT (0U)

#define	FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)

FEPROT - EEPROM Protection Register
#define	FTFE_FEPROT_EPROT_MASK (0xFFU)

#define	FTFE_FEPROT_EPROT_SHIFT (0U)

#define	FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)

#define	FTFE_FEPROT_EPROT_MASK (0xFFU)

#define	FTFE_FEPROT_EPROT_SHIFT (0U)

#define	FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)

#define	FTFE_FEPROT_EPROT_MASK (0xFFU)

#define	FTFE_FEPROT_EPROT_SHIFT (0U)

#define	FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)

FDPROT - Data Flash Protection Register
#define	FTFE_FDPROT_DPROT_MASK (0xFFU)

#define	FTFE_FDPROT_DPROT_SHIFT (0U)

#define	FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)

#define	FTFE_FDPROT_DPROT_MASK (0xFFU)

#define	FTFE_FDPROT_DPROT_SHIFT (0U)

#define	FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)

#define	FTFE_FDPROT_DPROT_MASK (0xFFU)

#define	FTFE_FDPROT_DPROT_SHIFT (0U)

#define	FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)

XACCH3 - Execute-only Access Registers
#define	FTFE_XACCH3_XA_MASK (0xFFU)

#define	FTFE_XACCH3_XA_SHIFT (0U)

#define	FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)

#define	FTFE_XACCH3_XA_MASK (0xFFU)

#define	FTFE_XACCH3_XA_SHIFT (0U)

#define	FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)

XACCH2 - Execute-only Access Registers
#define	FTFE_XACCH2_XA_MASK (0xFFU)

#define	FTFE_XACCH2_XA_SHIFT (0U)

#define	FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)

#define	FTFE_XACCH2_XA_MASK (0xFFU)

#define	FTFE_XACCH2_XA_SHIFT (0U)

#define	FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)

XACCH1 - Execute-only Access Registers
#define	FTFE_XACCH1_XA_MASK (0xFFU)

#define	FTFE_XACCH1_XA_SHIFT (0U)

#define	FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)

#define	FTFE_XACCH1_XA_MASK (0xFFU)

#define	FTFE_XACCH1_XA_SHIFT (0U)

#define	FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)

XACCH0 - Execute-only Access Registers
#define	FTFE_XACCH0_XA_MASK (0xFFU)

#define	FTFE_XACCH0_XA_SHIFT (0U)

#define	FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)

#define	FTFE_XACCH0_XA_MASK (0xFFU)

#define	FTFE_XACCH0_XA_SHIFT (0U)

#define	FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)

XACCL3 - Execute-only Access Registers
#define	FTFE_XACCL3_XA_MASK (0xFFU)

#define	FTFE_XACCL3_XA_SHIFT (0U)

#define	FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)

#define	FTFE_XACCL3_XA_MASK (0xFFU)

#define	FTFE_XACCL3_XA_SHIFT (0U)

#define	FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)

XACCL2 - Execute-only Access Registers
#define	FTFE_XACCL2_XA_MASK (0xFFU)

#define	FTFE_XACCL2_XA_SHIFT (0U)

#define	FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)

#define	FTFE_XACCL2_XA_MASK (0xFFU)

#define	FTFE_XACCL2_XA_SHIFT (0U)

#define	FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)

XACCL1 - Execute-only Access Registers
#define	FTFE_XACCL1_XA_MASK (0xFFU)

#define	FTFE_XACCL1_XA_SHIFT (0U)

#define	FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)

#define	FTFE_XACCL1_XA_MASK (0xFFU)

#define	FTFE_XACCL1_XA_SHIFT (0U)

#define	FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)

XACCL0 - Execute-only Access Registers
#define	FTFE_XACCL0_XA_MASK (0xFFU)

#define	FTFE_XACCL0_XA_SHIFT (0U)

#define	FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)

#define	FTFE_XACCL0_XA_MASK (0xFFU)

#define	FTFE_XACCL0_XA_SHIFT (0U)

#define	FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)

SACCH3 - Supervisor-only Access Registers
#define	FTFE_SACCH3_SA_MASK (0xFFU)

#define	FTFE_SACCH3_SA_SHIFT (0U)

#define	FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)

#define	FTFE_SACCH3_SA_MASK (0xFFU)

#define	FTFE_SACCH3_SA_SHIFT (0U)

#define	FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)

SACCH2 - Supervisor-only Access Registers
#define	FTFE_SACCH2_SA_MASK (0xFFU)

#define	FTFE_SACCH2_SA_SHIFT (0U)

#define	FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)

#define	FTFE_SACCH2_SA_MASK (0xFFU)

#define	FTFE_SACCH2_SA_SHIFT (0U)

#define	FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)

SACCH1 - Supervisor-only Access Registers
#define	FTFE_SACCH1_SA_MASK (0xFFU)

#define	FTFE_SACCH1_SA_SHIFT (0U)

#define	FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)

#define	FTFE_SACCH1_SA_MASK (0xFFU)

#define	FTFE_SACCH1_SA_SHIFT (0U)

#define	FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)

SACCH0 - Supervisor-only Access Registers
#define	FTFE_SACCH0_SA_MASK (0xFFU)

#define	FTFE_SACCH0_SA_SHIFT (0U)

#define	FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)

#define	FTFE_SACCH0_SA_MASK (0xFFU)

#define	FTFE_SACCH0_SA_SHIFT (0U)

#define	FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)

SACCL3 - Supervisor-only Access Registers
#define	FTFE_SACCL3_SA_MASK (0xFFU)

#define	FTFE_SACCL3_SA_SHIFT (0U)

#define	FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)

#define	FTFE_SACCL3_SA_MASK (0xFFU)

#define	FTFE_SACCL3_SA_SHIFT (0U)

#define	FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)

SACCL2 - Supervisor-only Access Registers
#define	FTFE_SACCL2_SA_MASK (0xFFU)

#define	FTFE_SACCL2_SA_SHIFT (0U)

#define	FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)

#define	FTFE_SACCL2_SA_MASK (0xFFU)

#define	FTFE_SACCL2_SA_SHIFT (0U)

#define	FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)

SACCL1 - Supervisor-only Access Registers
#define	FTFE_SACCL1_SA_MASK (0xFFU)

#define	FTFE_SACCL1_SA_SHIFT (0U)

#define	FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)

#define	FTFE_SACCL1_SA_MASK (0xFFU)

#define	FTFE_SACCL1_SA_SHIFT (0U)

#define	FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)

SACCL0 - Supervisor-only Access Registers
#define	FTFE_SACCL0_SA_MASK (0xFFU)

#define	FTFE_SACCL0_SA_SHIFT (0U)

#define	FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)

#define	FTFE_SACCL0_SA_MASK (0xFFU)

#define	FTFE_SACCL0_SA_SHIFT (0U)

#define	FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)

FACSS - Flash Access Segment Size Register
#define	FTFE_FACSS_SGSIZE_MASK (0xFFU)

#define	FTFE_FACSS_SGSIZE_SHIFT (0U)

#define	FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)

#define	FTFE_FACSS_SGSIZE_MASK (0xFFU)

#define	FTFE_FACSS_SGSIZE_SHIFT (0U)

#define	FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)

FACSN - Flash Access Segment Number Register
#define	FTFE_FACSN_NUMSG_MASK (0xFFU)

#define	FTFE_FACSN_NUMSG_SHIFT (0U)

#define	FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)

#define	FTFE_FACSN_NUMSG_MASK (0xFFU)

#define	FTFE_FACSN_NUMSG_SHIFT (0U)

#define	FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)

Macro Definition Documentation

◆ FTFE_FACSN_NUMSG [1/2]

#define FTFE_FACSN_NUMSG ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)

NUMSG - Number of Segments Indicator 0b00110000..Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes) 0b01000000..Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes)

◆ FTFE_FACSN_NUMSG [2/2]

#define FTFE_FACSN_NUMSG ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)

NUMSG - Number of Segments Indicator 0b00110000..Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes) 0b01000000..Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes)

◆ FTFE_FCNFG_CCIE [1/4]

#define FTFE_FCNFG_CCIE ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)

CCIE - Command Complete Interrupt Enable 0b0..Command complete interrupt disabled 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.

◆ FTFE_FCNFG_CCIE [2/4]

#define FTFE_FCNFG_CCIE ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)

CCIE - Command Complete Interrupt Enable 0b0..Command complete interrupt disabled 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.

◆ FTFE_FCNFG_CCIE [3/4]

#define FTFE_FCNFG_CCIE ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)

CCIE - Command Complete Interrupt Enable 0b0..Command complete interrupt disabled 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.

◆ FTFE_FCNFG_CCIE [4/4]

#define FTFE_FCNFG_CCIE ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)

CCIE - Command Complete Interrupt Enable 0b0..Command complete interrupt disabled 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.

◆ FTFE_FCNFG_EEERDY [1/4]

#define FTFE_FCNFG_EEERDY ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)

EEERDY 0b0..For devices with FlexNVM: FlexRAM is not available for EEPROM operation. 0b1..For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup.

EEERDY 0b0..For devices with FlexNVM: FlexRAM is not available for EEPROM operation For devices without FlexNVM: See RAMRDY for availability of programming acceleration RAM 0b1..For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup For devices without FlexNVM: Reserved

EEERDY 0b0..See RAMRDY for availability of programming acceleration RAM 0b1..Reserved

◆ FTFE_FCNFG_EEERDY [2/4]

#define FTFE_FCNFG_EEERDY ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)

EEERDY 0b0..For devices with FlexNVM: FlexRAM is not available for EEPROM operation For devices without FlexNVM: See RAMRDY for availability of programming acceleration RAM 0b1..For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup For devices without FlexNVM: Reserved

EEERDY 0b0..See RAMRDY for availability of programming acceleration RAM 0b1..Reserved

◆ FTFE_FCNFG_EEERDY [3/4]

#define FTFE_FCNFG_EEERDY ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)

EEERDY 0b0..For devices with FlexNVM: FlexRAM is not available for EEPROM operation For devices without FlexNVM: See RAMRDY for availability of programming acceleration RAM 0b1..For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup For devices without FlexNVM: Reserved

EEERDY 0b0..See RAMRDY for availability of programming acceleration RAM 0b1..Reserved

◆ FTFE_FCNFG_EEERDY [4/4]

#define FTFE_FCNFG_EEERDY ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)

EEERDY 0b0..See RAMRDY for availability of programming acceleration RAM 0b1..Reserved

◆ FTFE_FCNFG_ERSAREQ [1/4]

#define FTFE_FCNFG_ERSAREQ ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)

ERSAREQ - Erase All Request 0b0..No request or request complete 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.

ERSAREQ - Erase All Request 0b0..No request or request complete 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state

◆ FTFE_FCNFG_ERSAREQ [2/4]

#define FTFE_FCNFG_ERSAREQ ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)

ERSAREQ - Erase All Request 0b0..No request or request complete 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state

◆ FTFE_FCNFG_ERSAREQ [3/4]

#define FTFE_FCNFG_ERSAREQ ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)

ERSAREQ - Erase All Request 0b0..No request or request complete 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state

◆ FTFE_FCNFG_ERSAREQ [4/4]

#define FTFE_FCNFG_ERSAREQ ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)

ERSAREQ - Erase All Request 0b0..No request or request complete 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state

◆ FTFE_FCNFG_ERSSUSP [1/4]

#define FTFE_FCNFG_ERSSUSP ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)

ERSSUSP - Erase Suspend 0b0..No suspend requested 0b1..Suspend the current Erase Flash Sector command execution.

ERSSUSP - Erase Suspend 0b0..No suspend requested 0b1..Suspend the current Erase Flash Sector command execution

◆ FTFE_FCNFG_ERSSUSP [2/4]

#define FTFE_FCNFG_ERSSUSP ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)

ERSSUSP - Erase Suspend 0b0..No suspend requested 0b1..Suspend the current Erase Flash Sector command execution

◆ FTFE_FCNFG_ERSSUSP [3/4]

#define FTFE_FCNFG_ERSSUSP ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)

ERSSUSP - Erase Suspend 0b0..No suspend requested 0b1..Suspend the current Erase Flash Sector command execution

◆ FTFE_FCNFG_ERSSUSP [4/4]

#define FTFE_FCNFG_ERSSUSP ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)

ERSSUSP - Erase Suspend 0b0..No suspend requested 0b1..Suspend the current Erase Flash Sector command execution

◆ FTFE_FCNFG_PFLSH [1/3]

#define FTFE_FCNFG_PFLSH ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)

PFLSH - FTFE configuration 0b0..For devices with FlexNVM: FTFE configuration supports two program flash blocks and two FlexNVM blocks For devices with program flash only: Reserved 0b1..For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports four program flash blocks

PFLSH - FTFE configuration 0b0..For devices with FlexNVM: FTFE configuration supports two or three program flash blocks and two FlexNVM blocks For devices with program flash only: Reserved 0b1..For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports four program flash blocks

◆ FTFE_FCNFG_PFLSH [2/3]

#define FTFE_FCNFG_PFLSH ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)

PFLSH - FTFE configuration 0b0..For devices with FlexNVM: FTFE configuration supports two or three program flash blocks and two FlexNVM blocks For devices with program flash only: Reserved 0b1..For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports four program flash blocks

◆ FTFE_FCNFG_PFLSH [3/3]

#define FTFE_FCNFG_PFLSH ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)

PFLSH - FTFE configuration 0b0..For devices with FlexNVM: FTFE configuration supports two or three program flash blocks and two FlexNVM blocks For devices with program flash only: Reserved 0b1..For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports four program flash blocks

◆ FTFE_FCNFG_RAMRDY [1/4]

#define FTFE_FCNFG_RAMRDY ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)

RAMRDY - RAM Ready 0b0..For devices with FlexNVM: FlexRAM is not available for traditional RAM access. For devices without FlexNVM: Programming acceleration RAM is not available. 0b1..For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations. For devices without FlexNVM: Programming acceleration RAM is available.

RAMRDY - RAM Ready 0b0..For devices with FlexNVM: FlexRAM is not available for traditional RAM access For devices without FlexNVM: Programming acceleration RAM is not available 0b1..For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations For devices without FlexNVM: Programming acceleration RAM is available

RAMRDY - RAM Ready 0b0..Programming acceleration RAM is not available 0b1..Programming acceleration RAM is available

◆ FTFE_FCNFG_RAMRDY [2/4]

#define FTFE_FCNFG_RAMRDY ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)

RAMRDY - RAM Ready 0b0..For devices with FlexNVM: FlexRAM is not available for traditional RAM access For devices without FlexNVM: Programming acceleration RAM is not available 0b1..For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations For devices without FlexNVM: Programming acceleration RAM is available

RAMRDY - RAM Ready 0b0..Programming acceleration RAM is not available 0b1..Programming acceleration RAM is available

◆ FTFE_FCNFG_RAMRDY [3/4]

#define FTFE_FCNFG_RAMRDY ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)

RAMRDY - RAM Ready 0b0..For devices with FlexNVM: FlexRAM is not available for traditional RAM access For devices without FlexNVM: Programming acceleration RAM is not available 0b1..For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations For devices without FlexNVM: Programming acceleration RAM is available

RAMRDY - RAM Ready 0b0..Programming acceleration RAM is not available 0b1..Programming acceleration RAM is available

◆ FTFE_FCNFG_RAMRDY [4/4]

#define FTFE_FCNFG_RAMRDY ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)

RAMRDY - RAM Ready 0b0..Programming acceleration RAM is not available 0b1..Programming acceleration RAM is available

◆ FTFE_FCNFG_RDCOLLIE [1/4]

#define FTFE_FCNFG_RDCOLLIE ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)

RDCOLLIE - Read Collision Error Interrupt Enable 0b0..Read collision error interrupt disabled 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]).

◆ FTFE_FCNFG_RDCOLLIE [2/4]

#define FTFE_FCNFG_RDCOLLIE ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)

RDCOLLIE - Read Collision Error Interrupt Enable 0b0..Read collision error interrupt disabled 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]).

◆ FTFE_FCNFG_RDCOLLIE [3/4]

#define FTFE_FCNFG_RDCOLLIE ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)

RDCOLLIE - Read Collision Error Interrupt Enable 0b0..Read collision error interrupt disabled 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]).

◆ FTFE_FCNFG_RDCOLLIE [4/4]

#define FTFE_FCNFG_RDCOLLIE ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)

RDCOLLIE - Read Collision Error Interrupt Enable 0b0..Read collision error interrupt disabled 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]).

◆ FTFE_FCNFG_SWAP [1/3]

#define FTFE_FCNFG_SWAP ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)

SWAP - Swap 0b0..For devices with FlexNVM: Program flash 0 block is located at relative address 0x0000 For devices with program flash only: Program flash 0 block is located at relative address 0x0000 0b1..For devices with FlexNVM: Reserved For devices with program flash only: Program flash 1 block is located at relative address 0x0000

SWAP - Swap 0b0..For devices with FlexNVM: Program flash 0 block is located at relative address 0x0000 For devices with program flash only: Program flash 0/1 blocks are located at relative address 0x0000 0b1..For devices with FlexNVM: Reserved For devices with program flash only: Program flash 2/3 blocks are located at relative address 0x0000

◆ FTFE_FCNFG_SWAP [2/3]

#define FTFE_FCNFG_SWAP ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)

SWAP - Swap 0b0..For devices with FlexNVM: Program flash 0 block is located at relative address 0x0000 For devices with program flash only: Program flash 0/1 blocks are located at relative address 0x0000 0b1..For devices with FlexNVM: Reserved For devices with program flash only: Program flash 2/3 blocks are located at relative address 0x0000

◆ FTFE_FCNFG_SWAP [3/3]

#define FTFE_FCNFG_SWAP ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)

SWAP - Swap 0b0..For devices with FlexNVM: Program flash 0 block is located at relative address 0x0000 For devices with program flash only: Program flash 0/1 blocks are located at relative address 0x0000 0b1..For devices with FlexNVM: Reserved For devices with program flash only: Program flash 2/3 blocks are located at relative address 0x0000

◆ FTFE_FDPROT_DPROT [1/3]

#define FTFE_FDPROT_DPROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)

DPROT - Data Flash Region Protect 0b00000000..Data Flash region is protected 0b00000001..Data Flash region is not protected

◆ FTFE_FDPROT_DPROT [2/3]

#define FTFE_FDPROT_DPROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)

DPROT - Data Flash Region Protect 0b00000000..Data Flash region is protected 0b00000001..Data Flash region is not protected

◆ FTFE_FDPROT_DPROT [3/3]

#define FTFE_FDPROT_DPROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)

DPROT - Data Flash Region Protect 0b00000000..Data Flash region is protected 0b00000001..Data Flash region is not protected

◆ FTFE_FEPROT_EPROT [1/3]

#define FTFE_FEPROT_EPROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)

EPROT - EEPROM Region Protect 0b00000000..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected 0b00000001..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected

◆ FTFE_FEPROT_EPROT [2/3]

#define FTFE_FEPROT_EPROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)

EPROT - EEPROM Region Protect 0b00000000..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected 0b00000001..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected

◆ FTFE_FEPROT_EPROT [3/3]

#define FTFE_FEPROT_EPROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)

EPROT - EEPROM Region Protect 0b00000000..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected 0b00000001..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected

◆ FTFE_FPROT0_PROT [1/4]

#define FTFE_FPROT0_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT0_PROT [2/4]

#define FTFE_FPROT0_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT0_PROT [3/4]

#define FTFE_FPROT0_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT0_PROT [4/4]

#define FTFE_FPROT0_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT1_PROT [1/4]

#define FTFE_FPROT1_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT1_PROT [2/4]

#define FTFE_FPROT1_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT1_PROT [3/4]

#define FTFE_FPROT1_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT1_PROT [4/4]

#define FTFE_FPROT1_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT2_PROT [1/4]

#define FTFE_FPROT2_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT2_PROT [2/4]

#define FTFE_FPROT2_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT2_PROT [3/4]

#define FTFE_FPROT2_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT2_PROT [4/4]

#define FTFE_FPROT2_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT3_PROT [1/4]

#define FTFE_FPROT3_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT3_PROT [2/4]

#define FTFE_FPROT3_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT3_PROT [3/4]

#define FTFE_FPROT3_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FPROT3_PROT [4/4]

#define FTFE_FPROT3_PROT ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)

PROT - Program Flash Region Protect 0b00000000..Program flash region is protected. 0b00000001..Program flash region is not protected

◆ FTFE_FSEC_FSLACC [1/4]

#define FTFE_FSEC_FSLACC ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)

FSLACC - Freescale Failure Analysis Access Code 0b00..Freescale factory access granted 0b01..Freescale factory access denied 0b10..Freescale factory access denied 0b11..Freescale factory access granted

FSLACC - Factory Security Level Access Code 0b00..Factory access granted 0b01..Factory access denied 0b10..Factory access denied 0b11..Factory access granted

◆ FTFE_FSEC_FSLACC [2/4]

#define FTFE_FSEC_FSLACC ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)

FSLACC - Freescale Failure Analysis Access Code 0b00..Freescale factory access granted 0b01..Freescale factory access denied 0b10..Freescale factory access denied 0b11..Freescale factory access granted

FSLACC - Factory Security Level Access Code 0b00..Factory access granted 0b01..Factory access denied 0b10..Factory access denied 0b11..Factory access granted

◆ FTFE_FSEC_FSLACC [3/4]

#define FTFE_FSEC_FSLACC ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)

FSLACC - Freescale Failure Analysis Access Code 0b00..Freescale factory access granted 0b01..Freescale factory access denied 0b10..Freescale factory access denied 0b11..Freescale factory access granted

FSLACC - Factory Security Level Access Code 0b00..Factory access granted 0b01..Factory access denied 0b10..Factory access denied 0b11..Factory access granted

◆ FTFE_FSEC_FSLACC [4/4]

#define FTFE_FSEC_FSLACC ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)

FSLACC - Factory Security Level Access Code 0b00..Factory access granted 0b01..Factory access denied 0b10..Factory access denied 0b11..Factory access granted

◆ FTFE_FSEC_KEYEN [1/4]

#define FTFE_FSEC_KEYEN ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)

KEYEN - Backdoor Key Security Enable 0b00..Backdoor key access disabled 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 0b10..Backdoor key access enabled 0b11..Backdoor key access disabled

◆ FTFE_FSEC_KEYEN [2/4]

#define FTFE_FSEC_KEYEN ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)

KEYEN - Backdoor Key Security Enable 0b00..Backdoor key access disabled 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 0b10..Backdoor key access enabled 0b11..Backdoor key access disabled

◆ FTFE_FSEC_KEYEN [3/4]

#define FTFE_FSEC_KEYEN ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)

KEYEN - Backdoor Key Security Enable 0b00..Backdoor key access disabled 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 0b10..Backdoor key access enabled 0b11..Backdoor key access disabled

◆ FTFE_FSEC_KEYEN [4/4]

#define FTFE_FSEC_KEYEN ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)

KEYEN - Backdoor Key Security Enable 0b00..Backdoor key access disabled 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 0b10..Backdoor key access enabled 0b11..Backdoor key access disabled

◆ FTFE_FSEC_MEEN [1/4]

#define FTFE_FSEC_MEEN ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)

MEEN - Mass Erase Enable Bits 0b00..Mass erase is enabled 0b01..Mass erase is enabled 0b10..Mass erase is disabled 0b11..Mass erase is enabled

◆ FTFE_FSEC_MEEN [2/4]

#define FTFE_FSEC_MEEN ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)

MEEN - Mass Erase Enable Bits 0b00..Mass erase is enabled 0b01..Mass erase is enabled 0b10..Mass erase is disabled 0b11..Mass erase is enabled

◆ FTFE_FSEC_MEEN [3/4]

#define FTFE_FSEC_MEEN ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)

MEEN - Mass Erase Enable Bits 0b00..Mass erase is enabled 0b01..Mass erase is enabled 0b10..Mass erase is disabled 0b11..Mass erase is enabled

◆ FTFE_FSEC_MEEN [4/4]

#define FTFE_FSEC_MEEN ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)

MEEN - Mass Erase Enable Bits 0b00..Mass erase is enabled 0b01..Mass erase is enabled 0b10..Mass erase is disabled 0b11..Mass erase is enabled

◆ FTFE_FSEC_SEC [1/4]

#define FTFE_FSEC_SEC ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)

SEC - Flash Security 0b00..MCU security status is secure 0b01..MCU security status is secure 0b10..MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.) 0b11..MCU security status is secure

◆ FTFE_FSEC_SEC [2/4]

#define FTFE_FSEC_SEC ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)

SEC - Flash Security 0b00..MCU security status is secure 0b01..MCU security status is secure 0b10..MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.) 0b11..MCU security status is secure

◆ FTFE_FSEC_SEC [3/4]

#define FTFE_FSEC_SEC ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)

SEC - Flash Security 0b00..MCU security status is secure 0b01..MCU security status is secure 0b10..MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.) 0b11..MCU security status is secure

◆ FTFE_FSEC_SEC [4/4]

#define FTFE_FSEC_SEC ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)

SEC - Flash Security 0b00..MCU security status is secure 0b01..MCU security status is secure 0b10..MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.) 0b11..MCU security status is secure

◆ FTFE_FSTAT_ACCERR [1/4]

#define FTFE_FSTAT_ACCERR ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)

ACCERR - Flash Access Error Flag 0b0..No access error detected 0b1..Access error detected

◆ FTFE_FSTAT_ACCERR [2/4]

#define FTFE_FSTAT_ACCERR ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)

ACCERR - Flash Access Error Flag 0b0..No access error detected 0b1..Access error detected

◆ FTFE_FSTAT_ACCERR [3/4]

#define FTFE_FSTAT_ACCERR ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)

ACCERR - Flash Access Error Flag 0b0..No access error detected 0b1..Access error detected

◆ FTFE_FSTAT_ACCERR [4/4]

#define FTFE_FSTAT_ACCERR ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)

ACCERR - Flash Access Error Flag 0b0..No access error detected 0b1..Access error detected

◆ FTFE_FSTAT_CCIF [1/4]

#define FTFE_FSTAT_CCIF ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)

CCIF - Command Complete Interrupt Flag 0b0..FTFE command or EEPROM file system operation in progress 0b1..FTFE command or EEPROM file system operation has completed

CCIF - Command Complete Interrupt Flag 0b0..FTFE command in progress 0b1..FTFE command has completed

◆ FTFE_FSTAT_CCIF [2/4]

#define FTFE_FSTAT_CCIF ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)

CCIF - Command Complete Interrupt Flag 0b0..FTFE command or EEPROM file system operation in progress 0b1..FTFE command or EEPROM file system operation has completed

CCIF - Command Complete Interrupt Flag 0b0..FTFE command in progress 0b1..FTFE command has completed

◆ FTFE_FSTAT_CCIF [3/4]

#define FTFE_FSTAT_CCIF ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)

CCIF - Command Complete Interrupt Flag 0b0..FTFE command or EEPROM file system operation in progress 0b1..FTFE command or EEPROM file system operation has completed

CCIF - Command Complete Interrupt Flag 0b0..FTFE command in progress 0b1..FTFE command has completed

◆ FTFE_FSTAT_CCIF [4/4]

#define FTFE_FSTAT_CCIF ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)

CCIF - Command Complete Interrupt Flag 0b0..FTFE command in progress 0b1..FTFE command has completed

◆ FTFE_FSTAT_FPVIOL [1/4]

#define FTFE_FSTAT_FPVIOL ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)

FPVIOL - Flash Protection Violation Flag 0b0..No protection violation detected 0b1..Protection violation detected

◆ FTFE_FSTAT_FPVIOL [2/4]

#define FTFE_FSTAT_FPVIOL ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)

FPVIOL - Flash Protection Violation Flag 0b0..No protection violation detected 0b1..Protection violation detected

◆ FTFE_FSTAT_FPVIOL [3/4]

#define FTFE_FSTAT_FPVIOL ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)

FPVIOL - Flash Protection Violation Flag 0b0..No protection violation detected 0b1..Protection violation detected

◆ FTFE_FSTAT_FPVIOL [4/4]

#define FTFE_FSTAT_FPVIOL ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)

FPVIOL - Flash Protection Violation Flag 0b0..No protection violation detected 0b1..Protection violation detected

◆ FTFE_FSTAT_RDCOLERR [1/4]

#define FTFE_FSTAT_RDCOLERR ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)

RDCOLERR - FTFE Read Collision Error Flag 0b0..No collision error detected 0b1..Collision error detected

◆ FTFE_FSTAT_RDCOLERR [2/4]

#define FTFE_FSTAT_RDCOLERR ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)

RDCOLERR - FTFE Read Collision Error Flag 0b0..No collision error detected 0b1..Collision error detected

◆ FTFE_FSTAT_RDCOLERR [3/4]

#define FTFE_FSTAT_RDCOLERR ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)

RDCOLERR - FTFE Read Collision Error Flag 0b0..No collision error detected 0b1..Collision error detected

◆ FTFE_FSTAT_RDCOLERR [4/4]

#define FTFE_FSTAT_RDCOLERR ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)

RDCOLERR - FTFE Read Collision Error Flag 0b0..No collision error detected 0b1..Collision error detected

◆ FTFE_SACCH0_SA [1/2]

#define FTFE_SACCH0_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCH0_SA [2/2]

#define FTFE_SACCH0_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCH1_SA [1/2]

#define FTFE_SACCH1_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCH1_SA [2/2]

#define FTFE_SACCH1_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCH2_SA [1/2]

#define FTFE_SACCH2_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCH2_SA [2/2]

#define FTFE_SACCH2_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCH3_SA [1/2]

#define FTFE_SACCH3_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCH3_SA [2/2]

#define FTFE_SACCH3_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCL0_SA [1/2]

#define FTFE_SACCL0_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCL0_SA [2/2]

#define FTFE_SACCL0_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCL1_SA [1/2]

#define FTFE_SACCL1_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCL1_SA [2/2]

#define FTFE_SACCL1_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCL2_SA [1/2]

#define FTFE_SACCL2_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCL2_SA [2/2]

#define FTFE_SACCL2_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCL3_SA [1/2]

#define FTFE_SACCL3_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_SACCL3_SA [2/2]

#define FTFE_SACCL3_SA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)

SA - Supervisor-only access control 0b00000000..Associated segment is accessible in supervisor mode only 0b00000001..Associated segment is accessible in user or supervisor mode

◆ FTFE_XACCH0_XA [1/2]

#define FTFE_XACCH0_XA ( x ) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)