mikroSDK Reference Manual
Macros
HSADC Register Masks
Mapping Information » Device Peripheral Access Layer » HSADC Peripheral Access Layer

Macros

#define HSADC_RSLT_COUNT   (16U)
 
#define HSADC_LOLIM_COUNT   (16U)
 
#define HSADC_HILIM_COUNT   (16U)
 
#define HSADC_OFFST_COUNT   (16U)
 

CTRL1 - HSADC Control Register 1

#define HSADC_CTRL1_SMODE_MASK   (0x7U)
 
#define HSADC_CTRL1_SMODE_SHIFT   (0U)
 
#define HSADC_CTRL1_SMODE(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_SMODE_SHIFT)) & HSADC_CTRL1_SMODE_MASK)
 
#define HSADC_CTRL1_CHNCFG_L_MASK   (0xF0U)
 
#define HSADC_CTRL1_CHNCFG_L_SHIFT   (4U)
 
#define HSADC_CTRL1_CHNCFG_L(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_CHNCFG_L_SHIFT)) & HSADC_CTRL1_CHNCFG_L_MASK)
 
#define HSADC_CTRL1_HLMTIE_MASK   (0x100U)
 
#define HSADC_CTRL1_HLMTIE_SHIFT   (8U)
 
#define HSADC_CTRL1_HLMTIE(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_HLMTIE_SHIFT)) & HSADC_CTRL1_HLMTIE_MASK)
 
#define HSADC_CTRL1_LLMTIE_MASK   (0x200U)
 
#define HSADC_CTRL1_LLMTIE_SHIFT   (9U)
 
#define HSADC_CTRL1_LLMTIE(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_LLMTIE_SHIFT)) & HSADC_CTRL1_LLMTIE_MASK)
 
#define HSADC_CTRL1_ZCIE_MASK   (0x400U)
 
#define HSADC_CTRL1_ZCIE_SHIFT   (10U)
 
#define HSADC_CTRL1_ZCIE(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_ZCIE_SHIFT)) & HSADC_CTRL1_ZCIE_MASK)
 
#define HSADC_CTRL1_EOSIEA_MASK   (0x800U)
 
#define HSADC_CTRL1_EOSIEA_SHIFT   (11U)
 
#define HSADC_CTRL1_EOSIEA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_EOSIEA_SHIFT)) & HSADC_CTRL1_EOSIEA_MASK)
 
#define HSADC_CTRL1_SYNCA_MASK   (0x1000U)
 
#define HSADC_CTRL1_SYNCA_SHIFT   (12U)
 
#define HSADC_CTRL1_SYNCA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_SYNCA_SHIFT)) & HSADC_CTRL1_SYNCA_MASK)
 
#define HSADC_CTRL1_STARTA_MASK   (0x2000U)
 
#define HSADC_CTRL1_STARTA_SHIFT   (13U)
 
#define HSADC_CTRL1_STARTA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_STARTA_SHIFT)) & HSADC_CTRL1_STARTA_MASK)
 
#define HSADC_CTRL1_STOPA_MASK   (0x4000U)
 
#define HSADC_CTRL1_STOPA_SHIFT   (14U)
 
#define HSADC_CTRL1_STOPA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_STOPA_SHIFT)) & HSADC_CTRL1_STOPA_MASK)
 
#define HSADC_CTRL1_DMAENA_MASK   (0x8000U)
 
#define HSADC_CTRL1_DMAENA_SHIFT   (15U)
 
#define HSADC_CTRL1_DMAENA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_DMAENA_SHIFT)) & HSADC_CTRL1_DMAENA_MASK)
 

CTRL2 - HSADC Control Register 2

#define HSADC_CTRL2_DIVA_MASK   (0x3FU)
 
#define HSADC_CTRL2_DIVA_SHIFT   (0U)
 
#define HSADC_CTRL2_DIVA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_DIVA_SHIFT)) & HSADC_CTRL2_DIVA_MASK)
 
#define HSADC_CTRL2_SIMULT_MASK   (0x40U)
 
#define HSADC_CTRL2_SIMULT_SHIFT   (6U)
 
#define HSADC_CTRL2_SIMULT(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_SIMULT_SHIFT)) & HSADC_CTRL2_SIMULT_MASK)
 
#define HSADC_CTRL2_CHNCFG_H_MASK   (0x780U)
 
#define HSADC_CTRL2_CHNCFG_H_SHIFT   (7U)
 
#define HSADC_CTRL2_CHNCFG_H(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_CHNCFG_H_SHIFT)) & HSADC_CTRL2_CHNCFG_H_MASK)
 
#define HSADC_CTRL2_EOSIEB_MASK   (0x800U)
 
#define HSADC_CTRL2_EOSIEB_SHIFT   (11U)
 
#define HSADC_CTRL2_EOSIEB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_EOSIEB_SHIFT)) & HSADC_CTRL2_EOSIEB_MASK)
 
#define HSADC_CTRL2_SYNCB_MASK   (0x1000U)
 
#define HSADC_CTRL2_SYNCB_SHIFT   (12U)
 
#define HSADC_CTRL2_SYNCB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_SYNCB_SHIFT)) & HSADC_CTRL2_SYNCB_MASK)
 
#define HSADC_CTRL2_STARTB_MASK   (0x2000U)
 
#define HSADC_CTRL2_STARTB_SHIFT   (13U)
 
#define HSADC_CTRL2_STARTB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_STARTB_SHIFT)) & HSADC_CTRL2_STARTB_MASK)
 
#define HSADC_CTRL2_STOPB_MASK   (0x4000U)
 
#define HSADC_CTRL2_STOPB_SHIFT   (14U)
 
#define HSADC_CTRL2_STOPB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_STOPB_SHIFT)) & HSADC_CTRL2_STOPB_MASK)
 
#define HSADC_CTRL2_DMAENB_MASK   (0x8000U)
 
#define HSADC_CTRL2_DMAENB_SHIFT   (15U)
 
#define HSADC_CTRL2_DMAENB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_DMAENB_SHIFT)) & HSADC_CTRL2_DMAENB_MASK)
 

ZXCTRL1 - HSADC Zero Crossing Control 1 Register

#define HSADC_ZXCTRL1_ZCE0_MASK   (0x3U)
 
#define HSADC_ZXCTRL1_ZCE0_SHIFT   (0U)
 
#define HSADC_ZXCTRL1_ZCE0(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE0_SHIFT)) & HSADC_ZXCTRL1_ZCE0_MASK)
 
#define HSADC_ZXCTRL1_ZCE1_MASK   (0xCU)
 
#define HSADC_ZXCTRL1_ZCE1_SHIFT   (2U)
 
#define HSADC_ZXCTRL1_ZCE1(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE1_SHIFT)) & HSADC_ZXCTRL1_ZCE1_MASK)
 
#define HSADC_ZXCTRL1_ZCE2_MASK   (0x30U)
 
#define HSADC_ZXCTRL1_ZCE2_SHIFT   (4U)
 
#define HSADC_ZXCTRL1_ZCE2(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE2_SHIFT)) & HSADC_ZXCTRL1_ZCE2_MASK)
 
#define HSADC_ZXCTRL1_ZCE3_MASK   (0xC0U)
 
#define HSADC_ZXCTRL1_ZCE3_SHIFT   (6U)
 
#define HSADC_ZXCTRL1_ZCE3(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE3_SHIFT)) & HSADC_ZXCTRL1_ZCE3_MASK)
 
#define HSADC_ZXCTRL1_ZCE4_MASK   (0x300U)
 
#define HSADC_ZXCTRL1_ZCE4_SHIFT   (8U)
 
#define HSADC_ZXCTRL1_ZCE4(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE4_SHIFT)) & HSADC_ZXCTRL1_ZCE4_MASK)
 
#define HSADC_ZXCTRL1_ZCE5_MASK   (0xC00U)
 
#define HSADC_ZXCTRL1_ZCE5_SHIFT   (10U)
 
#define HSADC_ZXCTRL1_ZCE5(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE5_SHIFT)) & HSADC_ZXCTRL1_ZCE5_MASK)
 
#define HSADC_ZXCTRL1_ZCE6_MASK   (0x3000U)
 
#define HSADC_ZXCTRL1_ZCE6_SHIFT   (12U)
 
#define HSADC_ZXCTRL1_ZCE6(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE6_SHIFT)) & HSADC_ZXCTRL1_ZCE6_MASK)
 
#define HSADC_ZXCTRL1_ZCE7_MASK   (0xC000U)
 
#define HSADC_ZXCTRL1_ZCE7_SHIFT   (14U)
 
#define HSADC_ZXCTRL1_ZCE7(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE7_SHIFT)) & HSADC_ZXCTRL1_ZCE7_MASK)
 

ZXCTRL2 - HSADC Zero Crossing Control 2 Register

#define HSADC_ZXCTRL2_ZCE8_MASK   (0x3U)
 
#define HSADC_ZXCTRL2_ZCE8_SHIFT   (0U)
 
#define HSADC_ZXCTRL2_ZCE8(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE8_SHIFT)) & HSADC_ZXCTRL2_ZCE8_MASK)
 
#define HSADC_ZXCTRL2_ZCE9_MASK   (0xCU)
 
#define HSADC_ZXCTRL2_ZCE9_SHIFT   (2U)
 
#define HSADC_ZXCTRL2_ZCE9(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE9_SHIFT)) & HSADC_ZXCTRL2_ZCE9_MASK)
 
#define HSADC_ZXCTRL2_ZCE10_MASK   (0x30U)
 
#define HSADC_ZXCTRL2_ZCE10_SHIFT   (4U)
 
#define HSADC_ZXCTRL2_ZCE10(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE10_SHIFT)) & HSADC_ZXCTRL2_ZCE10_MASK)
 
#define HSADC_ZXCTRL2_ZCE11_MASK   (0xC0U)
 
#define HSADC_ZXCTRL2_ZCE11_SHIFT   (6U)
 
#define HSADC_ZXCTRL2_ZCE11(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE11_SHIFT)) & HSADC_ZXCTRL2_ZCE11_MASK)
 
#define HSADC_ZXCTRL2_ZCE12_MASK   (0x300U)
 
#define HSADC_ZXCTRL2_ZCE12_SHIFT   (8U)
 
#define HSADC_ZXCTRL2_ZCE12(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE12_SHIFT)) & HSADC_ZXCTRL2_ZCE12_MASK)
 
#define HSADC_ZXCTRL2_ZCE13_MASK   (0xC00U)
 
#define HSADC_ZXCTRL2_ZCE13_SHIFT   (10U)
 
#define HSADC_ZXCTRL2_ZCE13(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE13_SHIFT)) & HSADC_ZXCTRL2_ZCE13_MASK)
 
#define HSADC_ZXCTRL2_ZCE14_MASK   (0x3000U)
 
#define HSADC_ZXCTRL2_ZCE14_SHIFT   (12U)
 
#define HSADC_ZXCTRL2_ZCE14(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE14_SHIFT)) & HSADC_ZXCTRL2_ZCE14_MASK)
 
#define HSADC_ZXCTRL2_ZCE15_MASK   (0xC000U)
 
#define HSADC_ZXCTRL2_ZCE15_SHIFT   (14U)
 
#define HSADC_ZXCTRL2_ZCE15(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE15_SHIFT)) & HSADC_ZXCTRL2_ZCE15_MASK)
 

CLIST1 - HSADC Channel List Register 1

#define HSADC_CLIST1_SAMPLE0_MASK   (0xFU)
 
#define HSADC_CLIST1_SAMPLE0_SHIFT   (0U)
 
#define HSADC_CLIST1_SAMPLE0(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE0_SHIFT)) & HSADC_CLIST1_SAMPLE0_MASK)
 
#define HSADC_CLIST1_SAMPLE1_MASK   (0xF0U)
 
#define HSADC_CLIST1_SAMPLE1_SHIFT   (4U)
 
#define HSADC_CLIST1_SAMPLE1(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE1_SHIFT)) & HSADC_CLIST1_SAMPLE1_MASK)
 
#define HSADC_CLIST1_SAMPLE2_MASK   (0xF00U)
 
#define HSADC_CLIST1_SAMPLE2_SHIFT   (8U)
 
#define HSADC_CLIST1_SAMPLE2(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE2_SHIFT)) & HSADC_CLIST1_SAMPLE2_MASK)
 
#define HSADC_CLIST1_SAMPLE3_MASK   (0xF000U)
 
#define HSADC_CLIST1_SAMPLE3_SHIFT   (12U)
 
#define HSADC_CLIST1_SAMPLE3(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE3_SHIFT)) & HSADC_CLIST1_SAMPLE3_MASK)
 

CLIST2 - HSADC Channel List Register 2

#define HSADC_CLIST2_SAMPLE4_MASK   (0xFU)
 
#define HSADC_CLIST2_SAMPLE4_SHIFT   (0U)
 
#define HSADC_CLIST2_SAMPLE4(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE4_SHIFT)) & HSADC_CLIST2_SAMPLE4_MASK)
 
#define HSADC_CLIST2_SAMPLE5_MASK   (0xF0U)
 
#define HSADC_CLIST2_SAMPLE5_SHIFT   (4U)
 
#define HSADC_CLIST2_SAMPLE5(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE5_SHIFT)) & HSADC_CLIST2_SAMPLE5_MASK)
 
#define HSADC_CLIST2_SAMPLE6_MASK   (0xF00U)
 
#define HSADC_CLIST2_SAMPLE6_SHIFT   (8U)
 
#define HSADC_CLIST2_SAMPLE6(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE6_SHIFT)) & HSADC_CLIST2_SAMPLE6_MASK)
 
#define HSADC_CLIST2_SAMPLE7_MASK   (0xF000U)
 
#define HSADC_CLIST2_SAMPLE7_SHIFT   (12U)
 
#define HSADC_CLIST2_SAMPLE7(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE7_SHIFT)) & HSADC_CLIST2_SAMPLE7_MASK)
 

CLIST3 - HSADC Channel List Register 3

#define HSADC_CLIST3_SAMPLE8_MASK   (0xFU)
 
#define HSADC_CLIST3_SAMPLE8_SHIFT   (0U)
 
#define HSADC_CLIST3_SAMPLE8(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE8_SHIFT)) & HSADC_CLIST3_SAMPLE8_MASK)
 
#define HSADC_CLIST3_SAMPLE9_MASK   (0xF0U)
 
#define HSADC_CLIST3_SAMPLE9_SHIFT   (4U)
 
#define HSADC_CLIST3_SAMPLE9(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE9_SHIFT)) & HSADC_CLIST3_SAMPLE9_MASK)
 
#define HSADC_CLIST3_SAMPLE10_MASK   (0xF00U)
 
#define HSADC_CLIST3_SAMPLE10_SHIFT   (8U)
 
#define HSADC_CLIST3_SAMPLE10(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE10_SHIFT)) & HSADC_CLIST3_SAMPLE10_MASK)
 
#define HSADC_CLIST3_SAMPLE11_MASK   (0xF000U)
 
#define HSADC_CLIST3_SAMPLE11_SHIFT   (12U)
 
#define HSADC_CLIST3_SAMPLE11(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE11_SHIFT)) & HSADC_CLIST3_SAMPLE11_MASK)
 

CLIST4 - HSADC Channel List Register 4

#define HSADC_CLIST4_SAMPLE12_MASK   (0xFU)
 
#define HSADC_CLIST4_SAMPLE12_SHIFT   (0U)
 
#define HSADC_CLIST4_SAMPLE12(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE12_SHIFT)) & HSADC_CLIST4_SAMPLE12_MASK)
 
#define HSADC_CLIST4_SAMPLE13_MASK   (0xF0U)
 
#define HSADC_CLIST4_SAMPLE13_SHIFT   (4U)
 
#define HSADC_CLIST4_SAMPLE13(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE13_SHIFT)) & HSADC_CLIST4_SAMPLE13_MASK)
 
#define HSADC_CLIST4_SAMPLE14_MASK   (0xF00U)
 
#define HSADC_CLIST4_SAMPLE14_SHIFT   (8U)
 
#define HSADC_CLIST4_SAMPLE14(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE14_SHIFT)) & HSADC_CLIST4_SAMPLE14_MASK)
 
#define HSADC_CLIST4_SAMPLE15_MASK   (0xF000U)
 
#define HSADC_CLIST4_SAMPLE15_SHIFT   (12U)
 
#define HSADC_CLIST4_SAMPLE15(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE15_SHIFT)) & HSADC_CLIST4_SAMPLE15_MASK)
 

SDIS - HSADC Sample Disable Register

#define HSADC_SDIS_DS_MASK   (0xFFFFU)
 
#define HSADC_SDIS_DS_SHIFT   (0U)
 
#define HSADC_SDIS_DS(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_SDIS_DS_SHIFT)) & HSADC_SDIS_DS_MASK)
 

STAT - HSADC Status Register

#define HSADC_STAT_CALONA_MASK   (0x1U)
 
#define HSADC_STAT_CALONA_SHIFT   (0U)
 
#define HSADC_STAT_CALONA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CALONA_SHIFT)) & HSADC_STAT_CALONA_MASK)
 
#define HSADC_STAT_CALONB_MASK   (0x2U)
 
#define HSADC_STAT_CALONB_SHIFT   (1U)
 
#define HSADC_STAT_CALONB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CALONB_SHIFT)) & HSADC_STAT_CALONB_MASK)
 
#define HSADC_STAT_DUMMYA_MASK   (0x4U)
 
#define HSADC_STAT_DUMMYA_SHIFT   (2U)
 
#define HSADC_STAT_DUMMYA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_DUMMYA_SHIFT)) & HSADC_STAT_DUMMYA_MASK)
 
#define HSADC_STAT_DUMMYB_MASK   (0x8U)
 
#define HSADC_STAT_DUMMYB_SHIFT   (3U)
 
#define HSADC_STAT_DUMMYB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_DUMMYB_SHIFT)) & HSADC_STAT_DUMMYB_MASK)
 
#define HSADC_STAT_EOCALIA_MASK   (0x10U)
 
#define HSADC_STAT_EOCALIA_SHIFT   (4U)
 
#define HSADC_STAT_EOCALIA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOCALIA_SHIFT)) & HSADC_STAT_EOCALIA_MASK)
 
#define HSADC_STAT_EOCALIB_MASK   (0x20U)
 
#define HSADC_STAT_EOCALIB_SHIFT   (5U)
 
#define HSADC_STAT_EOCALIB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOCALIB_SHIFT)) & HSADC_STAT_EOCALIB_MASK)
 
#define HSADC_STAT_HLMTI_MASK   (0x100U)
 
#define HSADC_STAT_HLMTI_SHIFT   (8U)
 
#define HSADC_STAT_HLMTI(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_HLMTI_SHIFT)) & HSADC_STAT_HLMTI_MASK)
 
#define HSADC_STAT_LLMTI_MASK   (0x200U)
 
#define HSADC_STAT_LLMTI_SHIFT   (9U)
 
#define HSADC_STAT_LLMTI(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_LLMTI_SHIFT)) & HSADC_STAT_LLMTI_MASK)
 
#define HSADC_STAT_ZCI_MASK   (0x400U)
 
#define HSADC_STAT_ZCI_SHIFT   (10U)
 
#define HSADC_STAT_ZCI(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_ZCI_SHIFT)) & HSADC_STAT_ZCI_MASK)
 
#define HSADC_STAT_EOSIA_MASK   (0x800U)
 
#define HSADC_STAT_EOSIA_SHIFT   (11U)
 
#define HSADC_STAT_EOSIA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOSIA_SHIFT)) & HSADC_STAT_EOSIA_MASK)
 
#define HSADC_STAT_EOSIB_MASK   (0x1000U)
 
#define HSADC_STAT_EOSIB_SHIFT   (12U)
 
#define HSADC_STAT_EOSIB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOSIB_SHIFT)) & HSADC_STAT_EOSIB_MASK)
 
#define HSADC_STAT_CIPB_MASK   (0x4000U)
 
#define HSADC_STAT_CIPB_SHIFT   (14U)
 
#define HSADC_STAT_CIPB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CIPB_SHIFT)) & HSADC_STAT_CIPB_MASK)
 
#define HSADC_STAT_CIPA_MASK   (0x8000U)
 
#define HSADC_STAT_CIPA_SHIFT   (15U)
 
#define HSADC_STAT_CIPA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CIPA_SHIFT)) & HSADC_STAT_CIPA_MASK)
 

RDY - HSADC Ready Register

#define HSADC_RDY_RDY_MASK   (0xFFFFU)
 
#define HSADC_RDY_RDY_SHIFT   (0U)
 
#define HSADC_RDY_RDY(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_RDY_RDY_SHIFT)) & HSADC_RDY_RDY_MASK)
 

LOLIMSTAT - HSADC Low Limit Status Register

#define HSADC_LOLIMSTAT_LLS_MASK   (0xFFFFU)
 
#define HSADC_LOLIMSTAT_LLS_SHIFT   (0U)
 
#define HSADC_LOLIMSTAT_LLS(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_LOLIMSTAT_LLS_SHIFT)) & HSADC_LOLIMSTAT_LLS_MASK)
 

HILIMSTAT - HSADC High Limit Status Register

#define HSADC_HILIMSTAT_HLS_MASK   (0xFFFFU)
 
#define HSADC_HILIMSTAT_HLS_SHIFT   (0U)
 
#define HSADC_HILIMSTAT_HLS(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_HILIMSTAT_HLS_SHIFT)) & HSADC_HILIMSTAT_HLS_MASK)
 

ZXSTAT - HSADC Zero Crossing Status Register

#define HSADC_ZXSTAT_ZCS_MASK   (0xFFFFU)
 
#define HSADC_ZXSTAT_ZCS_SHIFT   (0U)
 
#define HSADC_ZXSTAT_ZCS(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_ZXSTAT_ZCS_SHIFT)) & HSADC_ZXSTAT_ZCS_MASK)
 

RSLT - HSADC Result Registers with sign extension

#define HSADC_RSLT_RSLT_MASK   (0x7FF8U)
 
#define HSADC_RSLT_RSLT_SHIFT   (3U)
 
#define HSADC_RSLT_RSLT(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_RSLT_RSLT_SHIFT)) & HSADC_RSLT_RSLT_MASK)
 
#define HSADC_RSLT_SEXT_MASK   (0x8000U)
 
#define HSADC_RSLT_SEXT_SHIFT   (15U)
 
#define HSADC_RSLT_SEXT(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_RSLT_SEXT_SHIFT)) & HSADC_RSLT_SEXT_MASK)
 

LOLIM - HSADC Low Limit Registers

#define HSADC_LOLIM_LLMT_MASK   (0x7FF8U)
 
#define HSADC_LOLIM_LLMT_SHIFT   (3U)
 
#define HSADC_LOLIM_LLMT(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_LOLIM_LLMT_SHIFT)) & HSADC_LOLIM_LLMT_MASK)
 

HILIM - HSADC High Limit Registers

#define HSADC_HILIM_HLMT_MASK   (0x7FF8U)
 
#define HSADC_HILIM_HLMT_SHIFT   (3U)
 
#define HSADC_HILIM_HLMT(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_HILIM_HLMT_SHIFT)) & HSADC_HILIM_HLMT_MASK)
 

OFFST - HSADC Offset Register

#define HSADC_OFFST_OFFSET_MASK   (0x7FF8U)
 
#define HSADC_OFFST_OFFSET_SHIFT   (3U)
 
#define HSADC_OFFST_OFFSET(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_OFFST_OFFSET_SHIFT)) & HSADC_OFFST_OFFSET_MASK)
 

PWR - HSADC Power Control Register

#define HSADC_PWR_PDA_MASK   (0x1U)
 
#define HSADC_PWR_PDA_SHIFT   (0U)
 
#define HSADC_PWR_PDA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PDA_SHIFT)) & HSADC_PWR_PDA_MASK)
 
#define HSADC_PWR_PDB_MASK   (0x2U)
 
#define HSADC_PWR_PDB_SHIFT   (1U)
 
#define HSADC_PWR_PDB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PDB_SHIFT)) & HSADC_PWR_PDB_MASK)
 
#define HSADC_PWR_APD_MASK   (0x8U)
 
#define HSADC_PWR_APD_SHIFT   (3U)
 
#define HSADC_PWR_APD(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_APD_SHIFT)) & HSADC_PWR_APD_MASK)
 
#define HSADC_PWR_PUDELAY_MASK   (0x3F0U)
 
#define HSADC_PWR_PUDELAY_SHIFT   (4U)
 
#define HSADC_PWR_PUDELAY(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PUDELAY_SHIFT)) & HSADC_PWR_PUDELAY_MASK)
 
#define HSADC_PWR_PSTSA_MASK   (0x400U)
 
#define HSADC_PWR_PSTSA_SHIFT   (10U)
 
#define HSADC_PWR_PSTSA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PSTSA_SHIFT)) & HSADC_PWR_PSTSA_MASK)
 
#define HSADC_PWR_PSTSB_MASK   (0x800U)
 
#define HSADC_PWR_PSTSB_SHIFT   (11U)
 
#define HSADC_PWR_PSTSB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PSTSB_SHIFT)) & HSADC_PWR_PSTSB_MASK)
 
#define HSADC_PWR_ASB_MASK   (0x8000U)
 
#define HSADC_PWR_ASB_SHIFT   (15U)
 
#define HSADC_PWR_ASB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_ASB_SHIFT)) & HSADC_PWR_ASB_MASK)
 

SCTRL - HSADC Scan Control Register

#define HSADC_SCTRL_SC_MASK   (0xFFFFU)
 
#define HSADC_SCTRL_SC_SHIFT   (0U)
 
#define HSADC_SCTRL_SC(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_SCTRL_SC_SHIFT)) & HSADC_SCTRL_SC_MASK)
 

PWR2 - HSADC Power Control Register 2

#define HSADC_PWR2_DIVB_MASK   (0x3F00U)
 
#define HSADC_PWR2_DIVB_SHIFT   (8U)
 
#define HSADC_PWR2_DIVB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_PWR2_DIVB_SHIFT)) & HSADC_PWR2_DIVB_MASK)
 

CTRL3 - HSADC Control Register 3

#define HSADC_CTRL3_DMASRC_MASK   (0x40U)
 
#define HSADC_CTRL3_DMASRC_SHIFT   (6U)
 
#define HSADC_CTRL3_DMASRC(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL3_DMASRC_SHIFT)) & HSADC_CTRL3_DMASRC_MASK)
 
#define HSADC_CTRL3_ADCRES_MASK   (0x300U)
 
#define HSADC_CTRL3_ADCRES_SHIFT   (8U)
 
#define HSADC_CTRL3_ADCRES(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL3_ADCRES_SHIFT)) & HSADC_CTRL3_ADCRES_MASK)
 

SCINTEN - HSADC Scan Interrupt Enable Register

#define HSADC_SCINTEN_SCINTEN_MASK   (0xFFFFU)
 
#define HSADC_SCINTEN_SCINTEN_SHIFT   (0U)
 
#define HSADC_SCINTEN_SCINTEN(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_SCINTEN_SCINTEN_SHIFT)) & HSADC_SCINTEN_SCINTEN_MASK)
 

SAMPTIM - HSADC Sampling Time Configuration Register

#define HSADC_SAMPTIM_SAMPT_A_MASK   (0xFFU)
 
#define HSADC_SAMPTIM_SAMPT_A_SHIFT   (0U)
 
#define HSADC_SAMPTIM_SAMPT_A(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_SAMPTIM_SAMPT_A_SHIFT)) & HSADC_SAMPTIM_SAMPT_A_MASK)
 
#define HSADC_SAMPTIM_SAMPT_B_MASK   (0xFF00U)
 
#define HSADC_SAMPTIM_SAMPT_B_SHIFT   (8U)
 
#define HSADC_SAMPTIM_SAMPT_B(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_SAMPTIM_SAMPT_B_SHIFT)) & HSADC_SAMPTIM_SAMPT_B_MASK)
 

CALIB - HSADCs Calibration Configuration

#define HSADC_CALIB_REQSINGA_MASK   (0x1U)
 
#define HSADC_CALIB_REQSINGA_SHIFT   (0U)
 
#define HSADC_CALIB_REQSINGA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQSINGA_SHIFT)) & HSADC_CALIB_REQSINGA_MASK)
 
#define HSADC_CALIB_REQDIFA_MASK   (0x2U)
 
#define HSADC_CALIB_REQDIFA_SHIFT   (1U)
 
#define HSADC_CALIB_REQDIFA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQDIFA_SHIFT)) & HSADC_CALIB_REQDIFA_MASK)
 
#define HSADC_CALIB_BYPA_MASK   (0x4U)
 
#define HSADC_CALIB_BYPA_SHIFT   (2U)
 
#define HSADC_CALIB_BYPA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_BYPA_SHIFT)) & HSADC_CALIB_BYPA_MASK)
 
#define HSADC_CALIB_CAL_REQA_MASK   (0x8U)
 
#define HSADC_CALIB_CAL_REQA_SHIFT   (3U)
 
#define HSADC_CALIB_CAL_REQA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_CAL_REQA_SHIFT)) & HSADC_CALIB_CAL_REQA_MASK)
 
#define HSADC_CALIB_REQSINGB_MASK   (0x10U)
 
#define HSADC_CALIB_REQSINGB_SHIFT   (4U)
 
#define HSADC_CALIB_REQSINGB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQSINGB_SHIFT)) & HSADC_CALIB_REQSINGB_MASK)
 
#define HSADC_CALIB_REQDIFB_MASK   (0x20U)
 
#define HSADC_CALIB_REQDIFB_SHIFT   (5U)
 
#define HSADC_CALIB_REQDIFB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQDIFB_SHIFT)) & HSADC_CALIB_REQDIFB_MASK)
 
#define HSADC_CALIB_BYPB_MASK   (0x40U)
 
#define HSADC_CALIB_BYPB_SHIFT   (6U)
 
#define HSADC_CALIB_BYPB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_BYPB_SHIFT)) & HSADC_CALIB_BYPB_MASK)
 
#define HSADC_CALIB_CAL_REQB_MASK   (0x80U)
 
#define HSADC_CALIB_CAL_REQB_SHIFT   (7U)
 
#define HSADC_CALIB_CAL_REQB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_CAL_REQB_SHIFT)) & HSADC_CALIB_CAL_REQB_MASK)
 
#define HSADC_CALIB_EOCALIEA_MASK   (0x100U)
 
#define HSADC_CALIB_EOCALIEA_SHIFT   (8U)
 
#define HSADC_CALIB_EOCALIEA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_EOCALIEA_SHIFT)) & HSADC_CALIB_EOCALIEA_MASK)
 
#define HSADC_CALIB_EOCALIEB_MASK   (0x200U)
 
#define HSADC_CALIB_EOCALIEB_SHIFT   (9U)
 
#define HSADC_CALIB_EOCALIEB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_EOCALIEB_SHIFT)) & HSADC_CALIB_EOCALIEB_MASK)
 

CALVAL_A - Calibration Values for ADCA Register

#define HSADC_CALVAL_A_CALVSING_MASK   (0x7FU)
 
#define HSADC_CALVAL_A_CALVSING_SHIFT   (0U)
 
#define HSADC_CALVAL_A_CALVSING(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALVAL_A_CALVSING_SHIFT)) & HSADC_CALVAL_A_CALVSING_MASK)
 
#define HSADC_CALVAL_A_CALVDIF_MASK   (0x7F00U)
 
#define HSADC_CALVAL_A_CALVDIF_SHIFT   (8U)
 
#define HSADC_CALVAL_A_CALVDIF(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALVAL_A_CALVDIF_SHIFT)) & HSADC_CALVAL_A_CALVDIF_MASK)
 

CALVAL_B - Calibration Values for ADCB Register

#define HSADC_CALVAL_B_CALVSING_MASK   (0x7FU)
 
#define HSADC_CALVAL_B_CALVSING_SHIFT   (0U)
 
#define HSADC_CALVAL_B_CALVSING(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALVAL_B_CALVSING_SHIFT)) & HSADC_CALVAL_B_CALVSING_MASK)
 
#define HSADC_CALVAL_B_CALVDIF_MASK   (0x7F00U)
 
#define HSADC_CALVAL_B_CALVDIF_SHIFT   (8U)
 
#define HSADC_CALVAL_B_CALVDIF(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_CALVAL_B_CALVDIF_SHIFT)) & HSADC_CALVAL_B_CALVDIF_MASK)
 

MUX67_SEL - MUX6_7 Selection Controls Register

#define HSADC_MUX67_SEL_CH6_SELA_MASK   (0x7U)
 
#define HSADC_MUX67_SEL_CH6_SELA_SHIFT   (0U)
 
#define HSADC_MUX67_SEL_CH6_SELA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_MUX67_SEL_CH6_SELA_SHIFT)) & HSADC_MUX67_SEL_CH6_SELA_MASK)
 
#define HSADC_MUX67_SEL_CH7_SELA_MASK   (0x70U)
 
#define HSADC_MUX67_SEL_CH7_SELA_SHIFT   (4U)
 
#define HSADC_MUX67_SEL_CH7_SELA(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_MUX67_SEL_CH7_SELA_SHIFT)) & HSADC_MUX67_SEL_CH7_SELA_MASK)
 
#define HSADC_MUX67_SEL_CH6_SELB_MASK   (0x700U)
 
#define HSADC_MUX67_SEL_CH6_SELB_SHIFT   (8U)
 
#define HSADC_MUX67_SEL_CH6_SELB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_MUX67_SEL_CH6_SELB_SHIFT)) & HSADC_MUX67_SEL_CH6_SELB_MASK)
 
#define HSADC_MUX67_SEL_CH7_SELB_MASK   (0x7000U)
 
#define HSADC_MUX67_SEL_CH7_SELB_SHIFT   (12U)
 
#define HSADC_MUX67_SEL_CH7_SELB(x)   (((uint16_t)(((uint16_t)(x)) << HSADC_MUX67_SEL_CH7_SELB_SHIFT)) & HSADC_MUX67_SEL_CH7_SELB_MASK)
 

Macro Definition Documentation

◆ HSADC_CALIB_BYPA

#define HSADC_CALIB_BYPA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_BYPA_SHIFT)) & HSADC_CALIB_BYPA_MASK)

BYPA - ADCA calibration bypass 0b0..ADCA block uses the calibration values to obtain the final conversion result (differential or single-ended mode) 0b1..Calibration operation is bypassed on ADCA.

◆ HSADC_CALIB_BYPB

#define HSADC_CALIB_BYPB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_BYPB_SHIFT)) & HSADC_CALIB_BYPB_MASK)

BYPB - ADCB calibration bypass 0b0..ADCB block uses the calibration values to obtain the final conversion result (differential or single-ended mode) 0b1..Calibration operation is bypassed on ADCB.

◆ HSADC_CALIB_CAL_REQA

#define HSADC_CALIB_CAL_REQA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_CAL_REQA_SHIFT)) & HSADC_CALIB_CAL_REQA_MASK)

CAL_REQA - Calibration Request for ADCA 0b0..None. 0b1..Calibration request for ADCA.

◆ HSADC_CALIB_CAL_REQB

#define HSADC_CALIB_CAL_REQB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_CAL_REQB_SHIFT)) & HSADC_CALIB_CAL_REQB_MASK)

CAL_REQB - Calibration Request for ADCB 0b0..Calibration is not requested. 0b1..Calibration is requested for ADCB.

◆ HSADC_CALIB_EOCALIEA

#define HSADC_CALIB_EOCALIEA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_EOCALIEA_SHIFT)) & HSADC_CALIB_EOCALIEA_MASK)

EOCALIEA - Interrupt Enable for End of Calibration on ADCA 0b0..Interrupt is not enabled. 0b1..Interrupt is enabled.

◆ HSADC_CALIB_EOCALIEB

#define HSADC_CALIB_EOCALIEB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_EOCALIEB_SHIFT)) & HSADC_CALIB_EOCALIEB_MASK)

EOCALIEB - Interrupt Enable for End of Calibration on ADCB 0b0..Interrupt is not enabled. 0b1..Interrupt is enabled.

◆ HSADC_CALIB_REQDIFA

#define HSADC_CALIB_REQDIFA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQDIFA_SHIFT)) & HSADC_CALIB_REQDIFA_MASK)

REQDIFA - ADCA Calibration request for differential mode 0b0..Calibration value calculation is not requested to ADCA. 0b1..Calibration value calculation for differential input mode is requested to be run on ADCA.

◆ HSADC_CALIB_REQDIFB

#define HSADC_CALIB_REQDIFB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQDIFB_SHIFT)) & HSADC_CALIB_REQDIFB_MASK)

REQDIFB - ADCB Calibration request for differential mode 0b0..Calibration value calculation is not requested to be run on ADCB. 0b1..Calibration value calculation for differential input mode is requested to be run onr ADCB

◆ HSADC_CALIB_REQSINGA

#define HSADC_CALIB_REQSINGA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQSINGA_SHIFT)) & HSADC_CALIB_REQSINGA_MASK)

REQSINGA - ADCA Calibration request for single ended mode 0b0..Calibration value calculation is not requested to be run on ADCA. 0b1..Calibration value calculation for single-ended input mode is requested to be run on ADCA.

◆ HSADC_CALIB_REQSINGB

#define HSADC_CALIB_REQSINGB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CALIB_REQSINGB_SHIFT)) & HSADC_CALIB_REQSINGB_MASK)

REQSINGB - ADCB Calibration request for single ended mode 0b0..Calibration value calculation is not requested to be run on ADCB. 0b1..Calibration value calculation for single-ended input mode is requested to be run on ADCB.

◆ HSADC_CLIST1_SAMPLE0

#define HSADC_CLIST1_SAMPLE0 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE0_SHIFT)) & HSADC_CLIST1_SAMPLE0_MASK)

SAMPLE0 - Sample Field 0 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST1_SAMPLE1

#define HSADC_CLIST1_SAMPLE1 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE1_SHIFT)) & HSADC_CLIST1_SAMPLE1_MASK)

SAMPLE1 - Sample Field 1 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST1_SAMPLE2

#define HSADC_CLIST1_SAMPLE2 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE2_SHIFT)) & HSADC_CLIST1_SAMPLE2_MASK)

SAMPLE2 - Sample Field 2 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST1_SAMPLE3

#define HSADC_CLIST1_SAMPLE3 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST1_SAMPLE3_SHIFT)) & HSADC_CLIST1_SAMPLE3_MASK)

SAMPLE3 - Sample Field 3 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST2_SAMPLE4

#define HSADC_CLIST2_SAMPLE4 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE4_SHIFT)) & HSADC_CLIST2_SAMPLE4_MASK)

SAMPLE4 - Sample Field 4 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST2_SAMPLE5

#define HSADC_CLIST2_SAMPLE5 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE5_SHIFT)) & HSADC_CLIST2_SAMPLE5_MASK)

SAMPLE5 - Sample Field 5 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST2_SAMPLE6

#define HSADC_CLIST2_SAMPLE6 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE6_SHIFT)) & HSADC_CLIST2_SAMPLE6_MASK)

SAMPLE6 - Sample Field 6 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST2_SAMPLE7

#define HSADC_CLIST2_SAMPLE7 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST2_SAMPLE7_SHIFT)) & HSADC_CLIST2_SAMPLE7_MASK)

SAMPLE7 - Sample Field 7 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST3_SAMPLE10

#define HSADC_CLIST3_SAMPLE10 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE10_SHIFT)) & HSADC_CLIST3_SAMPLE10_MASK)

SAMPLE10 - Sample Field 10 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST3_SAMPLE11

#define HSADC_CLIST3_SAMPLE11 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE11_SHIFT)) & HSADC_CLIST3_SAMPLE11_MASK)

SAMPLE11 - Sample Field 11 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST3_SAMPLE8

#define HSADC_CLIST3_SAMPLE8 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE8_SHIFT)) & HSADC_CLIST3_SAMPLE8_MASK)

SAMPLE8 - Sample Field 8 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST3_SAMPLE9

#define HSADC_CLIST3_SAMPLE9 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST3_SAMPLE9_SHIFT)) & HSADC_CLIST3_SAMPLE9_MASK)

SAMPLE9 - Sample Field 9 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST4_SAMPLE12

#define HSADC_CLIST4_SAMPLE12 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE12_SHIFT)) & HSADC_CLIST4_SAMPLE12_MASK)

SAMPLE12 - Sample Field 12 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST4_SAMPLE13

#define HSADC_CLIST4_SAMPLE13 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE13_SHIFT)) & HSADC_CLIST4_SAMPLE13_MASK)

SAMPLE13 - Sample Field 13 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST4_SAMPLE14

#define HSADC_CLIST4_SAMPLE14 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE14_SHIFT)) & HSADC_CLIST4_SAMPLE14_MASK)

SAMPLE14 - Sample Field 14 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7- 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CLIST4_SAMPLE15

#define HSADC_CLIST4_SAMPLE15 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CLIST4_SAMPLE15_SHIFT)) & HSADC_CLIST4_SAMPLE15_MASK)

SAMPLE15 - Sample Field 15 0b0000..Single Ended: ANA0, Differential: ANA0+, ANA1- 0b0001..Single Ended: ANA1, Differential: ANA0+, ANA1- 0b0010..Single Ended: ANA2, Differential: ANA2+, ANA3- 0b0011..Single Ended: ANA3, Differential: ANA2+, ANA3- 0b0100..Single Ended: ANA4, Differential: ANA4+, ANA5- 0b0101..Single Ended: ANA5, Differential: ANA4+, ANA5- 0b0110..Single Ended: ANA6, Differential: ANA6+, ANA7- 0b0111..Single Ended: ANA7, Differential: ANA6+, ANA7- 0b1000..Single Ended: ANB0, Differential: ANB0+, ANB1- 0b1001..Single Ended: ANB1, Differential: ANB0+, ANB1- 0b1010..Single Ended: ANB2, Differential: ANB2+, ANB3- 0b1011..Single Ended: ANB3, Differential: ANB2+, ANB3- 0b1100..Single Ended: ANB4, Differential: ANB4+, ANB5- 0b1101..Single Ended: ANB5, Differential: ANB4+, ANB5- 0b1110..Single Ended: ANB6, Differential: ANB6+, ANB7-. See Input Multiplex Function section for more details. 0b1111..Single Ended: ANB7, Differential: ANB6+, ANB7-

◆ HSADC_CTRL1_CHNCFG_L

#define HSADC_CTRL1_CHNCFG_L ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_CHNCFG_L_SHIFT)) & HSADC_CTRL1_CHNCFG_L_MASK)

CHNCFG_L - CHCNF (Channel Configure Low) bits 0bxxx1..Inputs = ANA0-ANA1 0bxxx0..Inputs = ANA0-ANA1 0bxx1x..Inputs = ANA2-ANA3 0bxx0x..Inputs = ANA2-ANA3 0bx1xx..Inputs = ANB0-ANB1 0bx0xx..Inputs = ANB0-ANB1 0b1xxx..Inputs = ANB2-ANB3

◆ HSADC_CTRL1_DMAENA

#define HSADC_CTRL1_DMAENA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_DMAENA_SHIFT)) & HSADC_CTRL1_DMAENA_MASK)

DMAENA - DMA enable 0b0..DMA is not enabled. 0b1..DMA is enabled.

◆ HSADC_CTRL1_EOSIEA

#define HSADC_CTRL1_EOSIEA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_EOSIEA_SHIFT)) & HSADC_CTRL1_EOSIEA_MASK)

EOSIEA - End Of Scan Interrupt Enable 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ HSADC_CTRL1_HLMTIE

#define HSADC_CTRL1_HLMTIE ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_HLMTIE_SHIFT)) & HSADC_CTRL1_HLMTIE_MASK)

HLMTIE - High Limit Interrupt Enable 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ HSADC_CTRL1_LLMTIE

#define HSADC_CTRL1_LLMTIE ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_LLMTIE_SHIFT)) & HSADC_CTRL1_LLMTIE_MASK)

LLMTIE - Low Limit Interrupt Enable 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ HSADC_CTRL1_SMODE

#define HSADC_CTRL1_SMODE ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_SMODE_SHIFT)) & HSADC_CTRL1_SMODE_MASK)

SMODE - HSADC Scan Mode Control 0b000..Once (single) sequential 0b001..Once parallel 0b010..Loop sequential 0b011..Loop parallel 0b100..Triggered sequential 0b101..Triggered parallel (default) 0b11x..Reserved value

◆ HSADC_CTRL1_STARTA

#define HSADC_CTRL1_STARTA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_STARTA_SHIFT)) & HSADC_CTRL1_STARTA_MASK)

STARTA - STARTA Conversion 0b0..No action 0b1..Start command is issued

◆ HSADC_CTRL1_STOPA

#define HSADC_CTRL1_STOPA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_STOPA_SHIFT)) & HSADC_CTRL1_STOPA_MASK)

STOPA - Stop 0b0..Normal operation 0b1..Stop mode

◆ HSADC_CTRL1_SYNCA

#define HSADC_CTRL1_SYNCA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_SYNCA_SHIFT)) & HSADC_CTRL1_SYNCA_MASK)

SYNCA - SYNCA Enable 0b0..Scan is initiated by a write to CTRL1[STARTA] only 0b1..Use a SYNCA input pulse or CTRL1[STARTA] to initiate a scan

◆ HSADC_CTRL1_ZCIE

#define HSADC_CTRL1_ZCIE ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL1_ZCIE_SHIFT)) & HSADC_CTRL1_ZCIE_MASK)

ZCIE - Zero Crossing Interrupt Enable 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ HSADC_CTRL2_CHNCFG_H

#define HSADC_CTRL2_CHNCFG_H ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_CHNCFG_H_SHIFT)) & HSADC_CTRL2_CHNCFG_H_MASK)

CHNCFG_H - CHNCFG_H (Channel Configure High) bits 0bxxx1..Inputs = ANA4-ANA5 0bxxx0..Inputs = ANA4-ANA5 0bxx1x..Inputs = ANA6-ANA7 0bxx0x..Inputs = ANA6-ANA7 0bx1xx..Inputs = ANB4-ANB5 0bx0xx..Inputs = ANB4-ANB5 0b1xxx..Inputs = ANB6-ANB7

◆ HSADC_CTRL2_DMAENB

#define HSADC_CTRL2_DMAENB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_DMAENB_SHIFT)) & HSADC_CTRL2_DMAENB_MASK)

DMAENB - DMA enable 0b0..DMA is not enabled. 0b1..DMA is enabled.

◆ HSADC_CTRL2_EOSIEB

#define HSADC_CTRL2_EOSIEB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_EOSIEB_SHIFT)) & HSADC_CTRL2_EOSIEB_MASK)

EOSIEB - End Of Scan Interrupt Enable 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ HSADC_CTRL2_SIMULT

#define HSADC_CTRL2_SIMULT ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_SIMULT_SHIFT)) & HSADC_CTRL2_SIMULT_MASK)

SIMULT - Simultaneous mode 0b0..Parallel scans done independently 0b1..Parallel scans done simultaneously (default)

◆ HSADC_CTRL2_STARTB

#define HSADC_CTRL2_STARTB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_STARTB_SHIFT)) & HSADC_CTRL2_STARTB_MASK)

STARTB - STARTB Conversion 0b0..No action 0b1..Start command is issued

◆ HSADC_CTRL2_STOPB

#define HSADC_CTRL2_STOPB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_STOPB_SHIFT)) & HSADC_CTRL2_STOPB_MASK)

STOPB - Stop 0b0..Normal operation 0b1..Stop mode

◆ HSADC_CTRL2_SYNCB

#define HSADC_CTRL2_SYNCB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL2_SYNCB_SHIFT)) & HSADC_CTRL2_SYNCB_MASK)

SYNCB - SYNCB Enable 0b0..B converter parallel scan is initiated by a write to CTRL2[STARTB] only 0b1..Use a SYNCB input pulse or CTRL2[STARTB] to initiate a B converter parallel scan

◆ HSADC_CTRL3_ADCRES

#define HSADC_CTRL3_ADCRES ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL3_ADCRES_SHIFT)) & HSADC_CTRL3_ADCRES_MASK)

ADCRES - ADCA/B Conversion Resolution 0b00..6-bit mode 0b01..8-bit mode 0b10..10-bit mode 0b11..12-bit mode

◆ HSADC_CTRL3_DMASRC

#define HSADC_CTRL3_DMASRC ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_CTRL3_DMASRC_SHIFT)) & HSADC_CTRL3_DMASRC_MASK)

DMASRC - DMA Trigger Source 0b0..DMA trigger source is end of scan interrupt 0b1..DMA trigger source is RDY bits

◆ HSADC_PWR_APD

#define HSADC_PWR_APD ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_APD_SHIFT)) & HSADC_PWR_APD_MASK)

APD - Auto Powerdown 0b0..Auto Powerdown Mode is not active 0b1..Auto Powerdown Mode is active

◆ HSADC_PWR_ASB

#define HSADC_PWR_ASB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_ASB_SHIFT)) & HSADC_PWR_ASB_MASK)

ASB - Auto Standby 0b0..Auto standby mode disabled 0b1..Auto standby mode enabled

◆ HSADC_PWR_PDA

#define HSADC_PWR_PDA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PDA_SHIFT)) & HSADC_PWR_PDA_MASK)

PDA - Manual Power Down for Converter A 0b0..Power Up ADC converter A 0b1..Power Down ADC converter A

◆ HSADC_PWR_PDB

#define HSADC_PWR_PDB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PDB_SHIFT)) & HSADC_PWR_PDB_MASK)

PDB - Manual Power Down for Converter B 0b0..Power Up ADC converter B 0b1..Power Down ADC converter B

◆ HSADC_PWR_PSTSA

#define HSADC_PWR_PSTSA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PSTSA_SHIFT)) & HSADC_PWR_PSTSA_MASK)

PSTSA - ADC Converter A Power Status 0b0..ADC Converter A is currently powered up 0b1..ADC Converter A is currently powered down

◆ HSADC_PWR_PSTSB

#define HSADC_PWR_PSTSB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_PWR_PSTSB_SHIFT)) & HSADC_PWR_PSTSB_MASK)

PSTSB - ADC Converter B Power Status 0b0..ADC Converter B is currently powered up 0b1..ADC Converter B is currently powered down

◆ HSADC_RDY_RDY

#define HSADC_RDY_RDY ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_RDY_RDY_SHIFT)) & HSADC_RDY_RDY_MASK)

RDY - Ready Sample 0b0000000000000000..Sample not ready or has been read 0b0000000000000001..Sample ready to be read

◆ HSADC_SCINTEN_SCINTEN

#define HSADC_SCINTEN_SCINTEN ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_SCINTEN_SCINTEN_SHIFT)) & HSADC_SCINTEN_SCINTEN_MASK)

SCINTEN - Scan Interrupt Enable 0b0000000000000000..Scan interrupt is not enabled for this sample. 0b0000000000000001..Scan interrupt is enabled for this sample.

◆ HSADC_SCTRL_SC

#define HSADC_SCTRL_SC ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_SCTRL_SC_SHIFT)) & HSADC_SCTRL_SC_MASK)

SC - Scan Control Bits 0b0000000000000000..Perform sample immediately after the completion of the current sample. 0b0000000000000001..Delay sample until a new sync input occurs.

◆ HSADC_SDIS_DS

#define HSADC_SDIS_DS ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_SDIS_DS_SHIFT)) & HSADC_SDIS_DS_MASK)

DS - Disable Sample Bits 0b0000000000000000..SAMPLEx channel is enabled for HSADC scan. 0b0000000000000001..SAMPLEx channel is disabled for HSADC scan and corresponding channels after SAMPLEx will also not occur in an HSADC scan.

◆ HSADC_STAT_CALONA

#define HSADC_STAT_CALONA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CALONA_SHIFT)) & HSADC_STAT_CALONA_MASK)

CALONA - HSADCA Calibration execution status 0b0..Calibration is not running 0b1..ADCA is running calibration conversions

◆ HSADC_STAT_CALONB

#define HSADC_STAT_CALONB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CALONB_SHIFT)) & HSADC_STAT_CALONB_MASK)

CALONB - HSADCB Calibration execution status 0b0..Calibration is not running 0b1..ADCB is running calibration conversions

◆ HSADC_STAT_CIPA

#define HSADC_STAT_CIPA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CIPA_SHIFT)) & HSADC_STAT_CIPA_MASK)

CIPA - Conversion in Progress 0b0..Idle state 0b1..A scan cycle is in progress. The HSADC will ignore all sync pulses or start commands

◆ HSADC_STAT_CIPB

#define HSADC_STAT_CIPB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_CIPB_SHIFT)) & HSADC_STAT_CIPB_MASK)

CIPB - Conversion in Progress 0b0..Idle state 0b1..A scan cycle is in progress. The HSADC will ignore all sync pulses or start commands

◆ HSADC_STAT_DUMMYA

#define HSADC_STAT_DUMMYA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_DUMMYA_SHIFT)) & HSADC_STAT_DUMMYA_MASK)

DUMMYA - Dummy conversion running on HSADCA 0b0..Dummy conversion is not running 0b1..Dummy conversion is running on ADCA

◆ HSADC_STAT_DUMMYB

#define HSADC_STAT_DUMMYB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_DUMMYB_SHIFT)) & HSADC_STAT_DUMMYB_MASK)

DUMMYB - Dummy conversion running on HSADCB 0b0..Dummy conversion is not running 0b1..Dummy conversion is running on ADCB

◆ HSADC_STAT_EOCALIA

#define HSADC_STAT_EOCALIA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOCALIA_SHIFT)) & HSADC_STAT_EOCALIA_MASK)

EOCALIA - End of Calibration on ADCA Interrupt 0b0..Calibration is not finished. 0b1..Calibration is finished on ADCA. The IRQ occurs if CALIB[EOCALIEA] is asserted.

◆ HSADC_STAT_EOCALIB

#define HSADC_STAT_EOCALIB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOCALIB_SHIFT)) & HSADC_STAT_EOCALIB_MASK)

EOCALIB - End of Calibration on ADCB Interrupt 0b0..Calibration is not finished. 0b1..Calibration is finished on ADCB. The IRQ occurs if CALIB[EOCALIEB] is asserted.

◆ HSADC_STAT_EOSIA

#define HSADC_STAT_EOSIA ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOSIA_SHIFT)) & HSADC_STAT_EOSIA_MASK)

EOSIA - End of Scan Interrupt 0b0..A scan cycle has not been completed, no end of scan IRQ pending 0b1..A scan cycle has been completed, end of scan IRQ pending

◆ HSADC_STAT_EOSIB

#define HSADC_STAT_EOSIB ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_EOSIB_SHIFT)) & HSADC_STAT_EOSIB_MASK)

EOSIB - End of Scan Interrupt 0b0..A scan cycle has not been completed, no end of scan IRQ pending 0b1..A scan cycle has been completed, end of scan IRQ pending

◆ HSADC_STAT_HLMTI

#define HSADC_STAT_HLMTI ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_HLMTI_SHIFT)) & HSADC_STAT_HLMTI_MASK)

HLMTI - High Limit Interrupt 0b0..No high limit interrupt request 0b1..High limit exceeded, IRQ pending if CTRL1[HLMTIE] is set

◆ HSADC_STAT_LLMTI

#define HSADC_STAT_LLMTI ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_LLMTI_SHIFT)) & HSADC_STAT_LLMTI_MASK)

LLMTI - Low Limit Interrupt 0b0..No low limit interrupt request 0b1..Low limit exceeded, IRQ pending if CTRL1[LLMTIE] is set

◆ HSADC_STAT_ZCI

#define HSADC_STAT_ZCI ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_STAT_ZCI_SHIFT)) & HSADC_STAT_ZCI_MASK)

ZCI - Zero Crossing Interrupt 0b0..No zero crossing interrupt request 0b1..Zero crossing encountered, IRQ pending if CTRL1[ZCIE] is set

◆ HSADC_ZXCTRL1_ZCE0

#define HSADC_ZXCTRL1_ZCE0 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE0_SHIFT)) & HSADC_ZXCTRL1_ZCE0_MASK)

ZCE0 - Zero crossing enable 0 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL1_ZCE1

#define HSADC_ZXCTRL1_ZCE1 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE1_SHIFT)) & HSADC_ZXCTRL1_ZCE1_MASK)

ZCE1 - Zero crossing enable 1 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL1_ZCE2

#define HSADC_ZXCTRL1_ZCE2 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE2_SHIFT)) & HSADC_ZXCTRL1_ZCE2_MASK)

ZCE2 - Zero crossing enable 2 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL1_ZCE3

#define HSADC_ZXCTRL1_ZCE3 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE3_SHIFT)) & HSADC_ZXCTRL1_ZCE3_MASK)

ZCE3 - Zero crossing enable 3 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL1_ZCE4

#define HSADC_ZXCTRL1_ZCE4 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE4_SHIFT)) & HSADC_ZXCTRL1_ZCE4_MASK)

ZCE4 - Zero crossing enable 4 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL1_ZCE5

#define HSADC_ZXCTRL1_ZCE5 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE5_SHIFT)) & HSADC_ZXCTRL1_ZCE5_MASK)

ZCE5 - Zero crossing enable 5 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL1_ZCE6

#define HSADC_ZXCTRL1_ZCE6 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE6_SHIFT)) & HSADC_ZXCTRL1_ZCE6_MASK)

ZCE6 - Zero crossing enable 6 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL1_ZCE7

#define HSADC_ZXCTRL1_ZCE7 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL1_ZCE7_SHIFT)) & HSADC_ZXCTRL1_ZCE7_MASK)

ZCE7 - Zero crossing enable 7 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL2_ZCE10

#define HSADC_ZXCTRL2_ZCE10 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE10_SHIFT)) & HSADC_ZXCTRL2_ZCE10_MASK)

ZCE10 - Zero crossing enable 10 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL2_ZCE11

#define HSADC_ZXCTRL2_ZCE11 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE11_SHIFT)) & HSADC_ZXCTRL2_ZCE11_MASK)

ZCE11 - Zero crossing enable 11 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL2_ZCE12

#define HSADC_ZXCTRL2_ZCE12 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE12_SHIFT)) & HSADC_ZXCTRL2_ZCE12_MASK)

ZCE12 - Zero crossing enable 12 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL2_ZCE13

#define HSADC_ZXCTRL2_ZCE13 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE13_SHIFT)) & HSADC_ZXCTRL2_ZCE13_MASK)

ZCE13 - Zero crossing enable 13 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL2_ZCE14

#define HSADC_ZXCTRL2_ZCE14 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE14_SHIFT)) & HSADC_ZXCTRL2_ZCE14_MASK)

ZCE14 - Zero crossing enable 14 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL2_ZCE15

#define HSADC_ZXCTRL2_ZCE15 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE15_SHIFT)) & HSADC_ZXCTRL2_ZCE15_MASK)

ZCE15 - Zero crossing enable 15 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL2_ZCE8

#define HSADC_ZXCTRL2_ZCE8 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE8_SHIFT)) & HSADC_ZXCTRL2_ZCE8_MASK)

ZCE8 - Zero crossing enable 8 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXCTRL2_ZCE9

#define HSADC_ZXCTRL2_ZCE9 ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXCTRL2_ZCE9_SHIFT)) & HSADC_ZXCTRL2_ZCE9_MASK)

ZCE9 - Zero crossing enable 9 0b00..Zero Crossing disabled 0b01..Zero Crossing enabled for positive to negative sign change 0b10..Zero Crossing enabled for negative to positive sign change 0b11..Zero Crossing enabled for any sign change

◆ HSADC_ZXSTAT_ZCS

#define HSADC_ZXSTAT_ZCS ( x)    (((uint16_t)(((uint16_t)(x)) << HSADC_ZXSTAT_ZCS_SHIFT)) & HSADC_ZXSTAT_ZCS_MASK)

ZCS - Zero Crossing Status 0b0000000000000000..Either: A sign change did not occur in a comparison between the current channelx result and the previous channelx result, or Zero crossing control is disabled for channelx in the zero crossing control register, ZXCTRL 0b0000000000000001..In a comparison between the current channelx result and the previous channelx result, a sign change condition occurred as defined in the zero crossing control register (ZXCTRL)