PCCCR - Cache control register
#define	LMEM_PCCCR_ENCACHE_MASK (0x1U)

#define	LMEM_PCCCR_ENCACHE_SHIFT (0U)

#define	LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)

#define	LMEM_PCCCR_ENWRBUF_MASK (0x2U)

#define	LMEM_PCCCR_ENWRBUF_SHIFT (1U)

#define	LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)

#define	LMEM_PCCCR_PCCR2_MASK (0x4U)

#define	LMEM_PCCCR_PCCR2_SHIFT (2U)

#define	LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)

#define	LMEM_PCCCR_PCCR3_MASK (0x8U)

#define	LMEM_PCCCR_PCCR3_SHIFT (3U)

#define	LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)

#define	LMEM_PCCCR_INVW0_MASK (0x1000000U)

#define	LMEM_PCCCR_INVW0_SHIFT (24U)

#define	LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)

#define	LMEM_PCCCR_PUSHW0_MASK (0x2000000U)

#define	LMEM_PCCCR_PUSHW0_SHIFT (25U)

#define	LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)

#define	LMEM_PCCCR_INVW1_MASK (0x4000000U)

#define	LMEM_PCCCR_INVW1_SHIFT (26U)

#define	LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)

#define	LMEM_PCCCR_PUSHW1_MASK (0x8000000U)

#define	LMEM_PCCCR_PUSHW1_SHIFT (27U)

#define	LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)

#define	LMEM_PCCCR_GO_MASK (0x80000000U)

#define	LMEM_PCCCR_GO_SHIFT (31U)

#define	LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)

#define	LMEM_PCCCR_ENCACHE_MASK (0x1U)

#define	LMEM_PCCCR_ENCACHE_SHIFT (0U)

#define	LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)

#define	LMEM_PCCCR_ENWRBUF_MASK (0x2U)

#define	LMEM_PCCCR_ENWRBUF_SHIFT (1U)

#define	LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)

#define	LMEM_PCCCR_PCCR2_MASK (0x4U)

#define	LMEM_PCCCR_PCCR2_SHIFT (2U)

#define	LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)

#define	LMEM_PCCCR_PCCR3_MASK (0x8U)

#define	LMEM_PCCCR_PCCR3_SHIFT (3U)

#define	LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)

#define	LMEM_PCCCR_INVW0_MASK (0x1000000U)

#define	LMEM_PCCCR_INVW0_SHIFT (24U)

#define	LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)

#define	LMEM_PCCCR_PUSHW0_MASK (0x2000000U)

#define	LMEM_PCCCR_PUSHW0_SHIFT (25U)

#define	LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)

#define	LMEM_PCCCR_INVW1_MASK (0x4000000U)

#define	LMEM_PCCCR_INVW1_SHIFT (26U)

#define	LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)

#define	LMEM_PCCCR_PUSHW1_MASK (0x8000000U)

#define	LMEM_PCCCR_PUSHW1_SHIFT (27U)

#define	LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)

#define	LMEM_PCCCR_GO_MASK (0x80000000U)

#define	LMEM_PCCCR_GO_SHIFT (31U)

#define	LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)

PCCLCR - Cache line control register
#define	LMEM_PCCLCR_LGO_MASK (0x1U)

#define	LMEM_PCCLCR_LGO_SHIFT (0U)

#define	LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)

#define	LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU)

#define	LMEM_PCCLCR_CACHEADDR_SHIFT (2U)

#define	LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)

#define	LMEM_PCCLCR_WSEL_MASK (0x4000U)

#define	LMEM_PCCLCR_WSEL_SHIFT (14U)

#define	LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)

#define	LMEM_PCCLCR_TDSEL_MASK (0x10000U)

#define	LMEM_PCCLCR_TDSEL_SHIFT (16U)

#define	LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)

#define	LMEM_PCCLCR_LCIVB_MASK (0x100000U)

#define	LMEM_PCCLCR_LCIVB_SHIFT (20U)

#define	LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)

#define	LMEM_PCCLCR_LCIMB_MASK (0x200000U)

#define	LMEM_PCCLCR_LCIMB_SHIFT (21U)

#define	LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)

#define	LMEM_PCCLCR_LCWAY_MASK (0x400000U)

#define	LMEM_PCCLCR_LCWAY_SHIFT (22U)

#define	LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)

#define	LMEM_PCCLCR_LCMD_MASK (0x3000000U)

#define	LMEM_PCCLCR_LCMD_SHIFT (24U)

#define	LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)

#define	LMEM_PCCLCR_LADSEL_MASK (0x4000000U)

#define	LMEM_PCCLCR_LADSEL_SHIFT (26U)

#define	LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)

#define	LMEM_PCCLCR_LACC_MASK (0x8000000U)

#define	LMEM_PCCLCR_LACC_SHIFT (27U)

#define	LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)

#define	LMEM_PCCLCR_LGO_MASK (0x1U)

#define	LMEM_PCCLCR_LGO_SHIFT (0U)

#define	LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)

#define	LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU)

#define	LMEM_PCCLCR_CACHEADDR_SHIFT (2U)

#define	LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)

#define	LMEM_PCCLCR_WSEL_MASK (0x4000U)

#define	LMEM_PCCLCR_WSEL_SHIFT (14U)

#define	LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)

#define	LMEM_PCCLCR_TDSEL_MASK (0x10000U)

#define	LMEM_PCCLCR_TDSEL_SHIFT (16U)

#define	LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)

#define	LMEM_PCCLCR_LCIVB_MASK (0x100000U)

#define	LMEM_PCCLCR_LCIVB_SHIFT (20U)

#define	LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)

#define	LMEM_PCCLCR_LCIMB_MASK (0x200000U)

#define	LMEM_PCCLCR_LCIMB_SHIFT (21U)

#define	LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)

#define	LMEM_PCCLCR_LCWAY_MASK (0x400000U)

#define	LMEM_PCCLCR_LCWAY_SHIFT (22U)

#define	LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)

#define	LMEM_PCCLCR_LCMD_MASK (0x3000000U)

#define	LMEM_PCCLCR_LCMD_SHIFT (24U)

#define	LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)

#define	LMEM_PCCLCR_LADSEL_MASK (0x4000000U)

#define	LMEM_PCCLCR_LADSEL_SHIFT (26U)

#define	LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)

#define	LMEM_PCCLCR_LACC_MASK (0x8000000U)

#define	LMEM_PCCLCR_LACC_SHIFT (27U)

#define	LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)

PCCSAR - Cache search address register
#define	LMEM_PCCSAR_LGO_MASK (0x1U)

#define	LMEM_PCCSAR_LGO_SHIFT (0U)

#define	LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)

#define	LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU)

#define	LMEM_PCCSAR_PHYADDR_SHIFT (2U)

#define	LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)

#define	LMEM_PCCSAR_LGO_MASK (0x1U)

#define	LMEM_PCCSAR_LGO_SHIFT (0U)

#define	LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)

#define	LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU)

#define	LMEM_PCCSAR_PHYADDR_SHIFT (2U)

#define	LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)

PCCCVR - Cache read/write value register
#define	LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU)

#define	LMEM_PCCCVR_DATA_SHIFT (0U)

#define	LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)

#define	LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU)

#define	LMEM_PCCCVR_DATA_SHIFT (0U)

#define	LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)

PCCRMR - Cache regions mode register
#define	LMEM_PCCRMR_R15_MASK (0x3U)

#define	LMEM_PCCRMR_R15_SHIFT (0U)

#define	LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)

#define	LMEM_PCCRMR_R14_MASK (0xCU)

#define	LMEM_PCCRMR_R14_SHIFT (2U)

#define	LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)

#define	LMEM_PCCRMR_R13_MASK (0x30U)

#define	LMEM_PCCRMR_R13_SHIFT (4U)

#define	LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)

#define	LMEM_PCCRMR_R12_MASK (0xC0U)

#define	LMEM_PCCRMR_R12_SHIFT (6U)

#define	LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)

#define	LMEM_PCCRMR_R11_MASK (0x300U)

#define	LMEM_PCCRMR_R11_SHIFT (8U)

#define	LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)

#define	LMEM_PCCRMR_R10_MASK (0xC00U)

#define	LMEM_PCCRMR_R10_SHIFT (10U)

#define	LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)

#define	LMEM_PCCRMR_R9_MASK (0x3000U)

#define	LMEM_PCCRMR_R9_SHIFT (12U)

#define	LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)

#define	LMEM_PCCRMR_R8_MASK (0xC000U)

#define	LMEM_PCCRMR_R8_SHIFT (14U)

#define	LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)

#define	LMEM_PCCRMR_R7_MASK (0x30000U)

#define	LMEM_PCCRMR_R7_SHIFT (16U)

#define	LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)

#define	LMEM_PCCRMR_R6_MASK (0xC0000U)

#define	LMEM_PCCRMR_R6_SHIFT (18U)

#define	LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)

#define	LMEM_PCCRMR_R5_MASK (0x300000U)

#define	LMEM_PCCRMR_R5_SHIFT (20U)

#define	LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)

#define	LMEM_PCCRMR_R4_MASK (0xC00000U)

#define	LMEM_PCCRMR_R4_SHIFT (22U)

#define	LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)

#define	LMEM_PCCRMR_R3_MASK (0x3000000U)

#define	LMEM_PCCRMR_R3_SHIFT (24U)

#define	LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)

#define	LMEM_PCCRMR_R2_MASK (0xC000000U)

#define	LMEM_PCCRMR_R2_SHIFT (26U)

#define	LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)

#define	LMEM_PCCRMR_R1_MASK (0x30000000U)

#define	LMEM_PCCRMR_R1_SHIFT (28U)

#define	LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)

#define	LMEM_PCCRMR_R0_MASK (0xC0000000U)

#define	LMEM_PCCRMR_R0_SHIFT (30U)

#define	LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)

#define	LMEM_PCCRMR_R15_MASK (0x3U)

#define	LMEM_PCCRMR_R15_SHIFT (0U)

#define	LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)

#define	LMEM_PCCRMR_R14_MASK (0xCU)

#define	LMEM_PCCRMR_R14_SHIFT (2U)

#define	LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)

#define	LMEM_PCCRMR_R13_MASK (0x30U)

#define	LMEM_PCCRMR_R13_SHIFT (4U)

#define	LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)

#define	LMEM_PCCRMR_R12_MASK (0xC0U)

#define	LMEM_PCCRMR_R12_SHIFT (6U)

#define	LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)

#define	LMEM_PCCRMR_R11_MASK (0x300U)

#define	LMEM_PCCRMR_R11_SHIFT (8U)

#define	LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)

#define	LMEM_PCCRMR_R10_MASK (0xC00U)

#define	LMEM_PCCRMR_R10_SHIFT (10U)

#define	LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)

#define	LMEM_PCCRMR_R9_MASK (0x3000U)

#define	LMEM_PCCRMR_R9_SHIFT (12U)

#define	LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)

#define	LMEM_PCCRMR_R8_MASK (0xC000U)

#define	LMEM_PCCRMR_R8_SHIFT (14U)

#define	LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)

#define	LMEM_PCCRMR_R7_MASK (0x30000U)

#define	LMEM_PCCRMR_R7_SHIFT (16U)

#define	LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)

#define	LMEM_PCCRMR_R6_MASK (0xC0000U)

#define	LMEM_PCCRMR_R6_SHIFT (18U)

#define	LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)

#define	LMEM_PCCRMR_R5_MASK (0x300000U)

#define	LMEM_PCCRMR_R5_SHIFT (20U)

#define	LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)

#define	LMEM_PCCRMR_R4_MASK (0xC00000U)

#define	LMEM_PCCRMR_R4_SHIFT (22U)

#define	LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)

#define	LMEM_PCCRMR_R3_MASK (0x3000000U)

#define	LMEM_PCCRMR_R3_SHIFT (24U)

#define	LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)

#define	LMEM_PCCRMR_R2_MASK (0xC000000U)

#define	LMEM_PCCRMR_R2_SHIFT (26U)

#define	LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)

#define	LMEM_PCCRMR_R1_MASK (0x30000000U)

#define	LMEM_PCCRMR_R1_SHIFT (28U)

#define	LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)

#define	LMEM_PCCRMR_R0_MASK (0xC0000000U)

#define	LMEM_PCCRMR_R0_SHIFT (30U)

#define	LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)

Macro Definition Documentation

◆ LMEM_PCCCR_ENCACHE [1/2]

#define LMEM_PCCCR_ENCACHE ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)

ENCACHE - Cache enable 0b0..Cache disabled 0b1..Cache enabled

◆ LMEM_PCCCR_ENCACHE [2/2]

#define LMEM_PCCCR_ENCACHE ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)

ENCACHE - Cache enable 0b0..Cache disabled 0b1..Cache enabled

◆ LMEM_PCCCR_ENWRBUF [1/2]

#define LMEM_PCCCR_ENWRBUF ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)

ENWRBUF - Enable Write Buffer 0b0..Write buffer disabled 0b1..Write buffer enabled

◆ LMEM_PCCCR_ENWRBUF [2/2]

#define LMEM_PCCCR_ENWRBUF ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)

ENWRBUF - Enable Write Buffer 0b0..Write buffer disabled 0b1..Write buffer enabled

◆ LMEM_PCCCR_GO [1/2]

#define LMEM_PCCCR_GO ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)

GO - Initiate Cache Command 0b0..Write: no effect. Read: no cache command active. 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.

◆ LMEM_PCCCR_GO [2/2]

#define LMEM_PCCCR_GO ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)

GO - Initiate Cache Command 0b0..Write: no effect. Read: no cache command active. 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.

◆ LMEM_PCCCR_INVW0 [1/2]

#define LMEM_PCCCR_INVW0 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)

INVW0 - Invalidate Way 0 0b0..No operation 0b1..When setting the GO bit, invalidate all lines in way 0.

◆ LMEM_PCCCR_INVW0 [2/2]

#define LMEM_PCCCR_INVW0 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)

INVW0 - Invalidate Way 0 0b0..No operation 0b1..When setting the GO bit, invalidate all lines in way 0.

◆ LMEM_PCCCR_INVW1 [1/2]

#define LMEM_PCCCR_INVW1 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)

INVW1 - Invalidate Way 1 0b0..No operation 0b1..When setting the GO bit, invalidate all lines in way 1

◆ LMEM_PCCCR_INVW1 [2/2]

#define LMEM_PCCCR_INVW1 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)

INVW1 - Invalidate Way 1 0b0..No operation 0b1..When setting the GO bit, invalidate all lines in way 1

◆ LMEM_PCCCR_PUSHW0 [1/2]

#define LMEM_PCCCR_PUSHW0 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)

PUSHW0 - Push Way 0 0b0..No operation 0b1..When setting the GO bit, push all modified lines in way 0

◆ LMEM_PCCCR_PUSHW0 [2/2]

#define LMEM_PCCCR_PUSHW0 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)

PUSHW0 - Push Way 0 0b0..No operation 0b1..When setting the GO bit, push all modified lines in way 0

◆ LMEM_PCCCR_PUSHW1 [1/2]

#define LMEM_PCCCR_PUSHW1 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)

PUSHW1 - Push Way 1 0b0..No operation 0b1..When setting the GO bit, push all modified lines in way 1

◆ LMEM_PCCCR_PUSHW1 [2/2]

#define LMEM_PCCCR_PUSHW1 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)

PUSHW1 - Push Way 1 0b0..No operation 0b1..When setting the GO bit, push all modified lines in way 1

◆ LMEM_PCCLCR_LACC [1/2]

#define LMEM_PCCLCR_LACC ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)

LACC - Line access type 0b0..Read 0b1..Write

◆ LMEM_PCCLCR_LACC [2/2]

#define LMEM_PCCLCR_LACC ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)

LACC - Line access type 0b0..Read 0b1..Write

◆ LMEM_PCCLCR_LADSEL [1/2]

#define LMEM_PCCLCR_LADSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)

LADSEL - Line Address Select 0b0..Cache address 0b1..Physical address

◆ LMEM_PCCLCR_LADSEL [2/2]

#define LMEM_PCCLCR_LADSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)

LADSEL - Line Address Select 0b0..Cache address 0b1..Physical address

◆ LMEM_PCCLCR_LCMD [1/2]

#define LMEM_PCCLCR_LCMD ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)

LCMD - Line Command 0b00..Search and read or write 0b01..Invalidate 0b10..Push 0b11..Clear

◆ LMEM_PCCLCR_LCMD [2/2]

#define LMEM_PCCLCR_LCMD ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)

LCMD - Line Command 0b00..Search and read or write 0b01..Invalidate 0b10..Push 0b11..Clear

◆ LMEM_PCCLCR_LGO [1/2]

#define LMEM_PCCLCR_LGO ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)

LGO - Initiate Cache Line Command 0b0..Write: no effect. Read: no line command active. 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.

◆ LMEM_PCCLCR_LGO [2/2]

#define LMEM_PCCLCR_LGO ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)

LGO - Initiate Cache Line Command 0b0..Write: no effect. Read: no line command active. 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.

◆ LMEM_PCCLCR_TDSEL [1/2]

#define LMEM_PCCLCR_TDSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)

TDSEL - Tag/Data Select 0b0..Data 0b1..Tag

◆ LMEM_PCCLCR_TDSEL [2/2]

#define LMEM_PCCLCR_TDSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)

TDSEL - Tag/Data Select 0b0..Data 0b1..Tag

◆ LMEM_PCCLCR_WSEL [1/2]

#define LMEM_PCCLCR_WSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)

WSEL - Way select 0b0..Way 0 0b1..Way 1

◆ LMEM_PCCLCR_WSEL [2/2]

#define LMEM_PCCLCR_WSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)

WSEL - Way select 0b0..Way 0 0b1..Way 1

◆ LMEM_PCCRMR_R0 [1/2]

#define LMEM_PCCRMR_R0 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)

R0 - Region 0 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R0 [2/2]

#define LMEM_PCCRMR_R0 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)

R0 - Region 0 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R1 [1/2]

#define LMEM_PCCRMR_R1 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)

R1 - Region 1 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R1 [2/2]

#define LMEM_PCCRMR_R1 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)

R1 - Region 1 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R10 [1/2]

#define LMEM_PCCRMR_R10 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)

R10 - Region 10 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R10 [2/2]

#define LMEM_PCCRMR_R10 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)

R10 - Region 10 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R11 [1/2]

#define LMEM_PCCRMR_R11 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)

R11 - Region 11 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R11 [2/2]

#define LMEM_PCCRMR_R11 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)

R11 - Region 11 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R12 [1/2]

#define LMEM_PCCRMR_R12 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)

R12 - Region 12 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R12 [2/2]

#define LMEM_PCCRMR_R12 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)

R12 - Region 12 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R13 [1/2]

#define LMEM_PCCRMR_R13 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)

R13 - Region 13 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R13 [2/2]

#define LMEM_PCCRMR_R13 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)

R13 - Region 13 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R14 [1/2]

#define LMEM_PCCRMR_R14 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)

R14 - Region 14 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R14 [2/2]

#define LMEM_PCCRMR_R14 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)

R14 - Region 14 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R15 [1/2]

#define LMEM_PCCRMR_R15 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)

R15 - Region 15 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R15 [2/2]

#define LMEM_PCCRMR_R15 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)

R15 - Region 15 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R2 [1/2]

#define LMEM_PCCRMR_R2 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)

R2 - Region 2 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R2 [2/2]

#define LMEM_PCCRMR_R2 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)

R2 - Region 2 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R3 [1/2]

#define LMEM_PCCRMR_R3 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)

R3 - Region 3 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R3 [2/2]

#define LMEM_PCCRMR_R3 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)

R3 - Region 3 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R4 [1/2]

#define LMEM_PCCRMR_R4 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)

R4 - Region 4 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R4 [2/2]

#define LMEM_PCCRMR_R4 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)

R4 - Region 4 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R5 [1/2]

#define LMEM_PCCRMR_R5 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)

R5 - Region 5 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R5 [2/2]

#define LMEM_PCCRMR_R5 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)

R5 - Region 5 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R6 [1/2]

#define LMEM_PCCRMR_R6 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)

R6 - Region 6 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R6 [2/2]

#define LMEM_PCCRMR_R6 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)

R6 - Region 6 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R7 [1/2]

#define LMEM_PCCRMR_R7 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)

R7 - Region 7 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R7 [2/2]

#define LMEM_PCCRMR_R7 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)

R7 - Region 7 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R8 [1/2]

#define LMEM_PCCRMR_R8 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)

R8 - Region 8 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R8 [2/2]

#define LMEM_PCCRMR_R8 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)

R8 - Region 8 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R9 [1/2]

#define LMEM_PCCRMR_R9 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)

R9 - Region 9 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCRMR_R9 [2/2]

#define LMEM_PCCRMR_R9 ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)

R9 - Region 9 mode 0b00..Non-cacheable 0b01..Non-cacheable 0b10..Write-through 0b11..Write-back

◆ LMEM_PCCSAR_LGO [1/2]

#define LMEM_PCCSAR_LGO ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)

LGO - Initiate Cache Line Command 0b0..Write: no effect. Read: no line command active. 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.

◆ LMEM_PCCSAR_LGO [2/2]

#define LMEM_PCCSAR_LGO ( x ) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)

LGO - Initiate Cache Line Command 0b0..Write: no effect. Read: no line command active. 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.

PCCCR - Cache control register

PCCLCR - Cache line control register

PCCSAR - Cache search address register

PCCCVR - Cache read/write value register

PCCRMR - Cache regions mode register

Macro Definition Documentation

◆ LMEM_PCCCR_ENCACHE [1/2]

◆ LMEM_PCCCR_ENCACHE [2/2]

◆ LMEM_PCCCR_ENWRBUF [1/2]

◆ LMEM_PCCCR_ENWRBUF [2/2]

◆ LMEM_PCCCR_GO [1/2]

◆ LMEM_PCCCR_GO [2/2]

◆ LMEM_PCCCR_INVW0 [1/2]

◆ LMEM_PCCCR_INVW0 [2/2]

◆ LMEM_PCCCR_INVW1 [1/2]

◆ LMEM_PCCCR_INVW1 [2/2]

◆ LMEM_PCCCR_PUSHW0 [1/2]

◆ LMEM_PCCCR_PUSHW0 [2/2]

◆ LMEM_PCCCR_PUSHW1 [1/2]

◆ LMEM_PCCCR_PUSHW1 [2/2]

◆ LMEM_PCCLCR_LACC [1/2]

◆ LMEM_PCCLCR_LACC [2/2]

◆ LMEM_PCCLCR_LADSEL [1/2]

◆ LMEM_PCCLCR_LADSEL [2/2]

◆ LMEM_PCCLCR_LCMD [1/2]

◆ LMEM_PCCLCR_LCMD [2/2]

◆ LMEM_PCCLCR_LGO [1/2]

◆ LMEM_PCCLCR_LGO [2/2]

◆ LMEM_PCCLCR_TDSEL [1/2]

◆ LMEM_PCCLCR_TDSEL [2/2]

◆ LMEM_PCCLCR_WSEL [1/2]

◆ LMEM_PCCLCR_WSEL [2/2]

◆ LMEM_PCCRMR_R0 [1/2]

◆ LMEM_PCCRMR_R0 [2/2]

◆ LMEM_PCCRMR_R1 [1/2]

◆ LMEM_PCCRMR_R1 [2/2]

◆ LMEM_PCCRMR_R10 [1/2]

◆ LMEM_PCCRMR_R10 [2/2]

◆ LMEM_PCCRMR_R11 [1/2]

◆ LMEM_PCCRMR_R11 [2/2]

◆ LMEM_PCCRMR_R12 [1/2]

◆ LMEM_PCCRMR_R12 [2/2]

◆ LMEM_PCCRMR_R13 [1/2]

◆ LMEM_PCCRMR_R13 [2/2]

◆ LMEM_PCCRMR_R14 [1/2]

◆ LMEM_PCCRMR_R14 [2/2]

◆ LMEM_PCCRMR_R15 [1/2]

◆ LMEM_PCCRMR_R15 [2/2]

◆ LMEM_PCCRMR_R2 [1/2]

◆ LMEM_PCCRMR_R2 [2/2]

◆ LMEM_PCCRMR_R3 [1/2]

◆ LMEM_PCCRMR_R3 [2/2]

◆ LMEM_PCCRMR_R4 [1/2]

◆ LMEM_PCCRMR_R4 [2/2]

◆ LMEM_PCCRMR_R5 [1/2]

◆ LMEM_PCCRMR_R5 [2/2]

◆ LMEM_PCCRMR_R6 [1/2]

◆ LMEM_PCCRMR_R6 [2/2]

◆ LMEM_PCCRMR_R7 [1/2]

◆ LMEM_PCCRMR_R7 [2/2]

◆ LMEM_PCCRMR_R8 [1/2]

◆ LMEM_PCCRMR_R8 [2/2]

◆ LMEM_PCCRMR_R9 [1/2]

◆ LMEM_PCCRMR_R9 [2/2]

◆ LMEM_PCCSAR_LGO [1/2]

◆ LMEM_PCCSAR_LGO [2/2]