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#define | MPU_CESR_VLD_MASK 0x1u |
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#define | MPU_CESR_VLD_SHIFT 0 |
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#define | MPU_CESR_NRGD_MASK 0xF00u |
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#define | MPU_CESR_NRGD_SHIFT 8 |
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#define | MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK) |
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#define | MPU_CESR_NSP_MASK 0xF000u |
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#define | MPU_CESR_NSP_SHIFT 12 |
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#define | MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK) |
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#define | MPU_CESR_HRL_MASK 0xF0000u |
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#define | MPU_CESR_HRL_SHIFT 16 |
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#define | MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK) |
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#define | MPU_CESR_SPERR_MASK 0xF8000000u |
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#define | MPU_CESR_SPERR_SHIFT 27 |
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#define | MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK) |
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#define | MPU_EAR_EADDR_MASK 0xFFFFFFFFu |
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#define | MPU_EAR_EADDR_SHIFT 0 |
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#define | MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK) |
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#define | MPU_EDR_ERW_MASK 0x1u |
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#define | MPU_EDR_ERW_SHIFT 0 |
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#define | MPU_EDR_EATTR_MASK 0xEu |
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#define | MPU_EDR_EATTR_SHIFT 1 |
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#define | MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK) |
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#define | MPU_EDR_EMN_MASK 0xF0u |
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#define | MPU_EDR_EMN_SHIFT 4 |
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#define | MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK) |
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#define | MPU_EDR_EACD_MASK 0xFFFF0000u |
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#define | MPU_EDR_EACD_SHIFT 16 |
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#define | MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK) |
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#define | MPU_WORD_M0UM_MASK 0x7u |
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#define | MPU_WORD_M0UM_SHIFT 0 |
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#define | MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK) |
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#define | MPU_WORD_VLD_MASK 0x1u |
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#define | MPU_WORD_VLD_SHIFT 0 |
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#define | MPU_WORD_M0SM_MASK 0x18u |
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#define | MPU_WORD_M0SM_SHIFT 3 |
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#define | MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK) |
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#define | MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u |
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#define | MPU_WORD_ENDADDR_SHIFT 5 |
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#define | MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK) |
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#define | MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u |
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#define | MPU_WORD_SRTADDR_SHIFT 5 |
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#define | MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK) |
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#define | MPU_WORD_M1UM_MASK 0x1C0u |
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#define | MPU_WORD_M1UM_SHIFT 6 |
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#define | MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK) |
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#define | MPU_WORD_M1SM_MASK 0x600u |
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#define | MPU_WORD_M1SM_SHIFT 9 |
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#define | MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK) |
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#define | MPU_WORD_M2UM_MASK 0x7000u |
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#define | MPU_WORD_M2UM_SHIFT 12 |
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#define | MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK) |
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#define | MPU_WORD_M2SM_MASK 0x18000u |
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#define | MPU_WORD_M2SM_SHIFT 15 |
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#define | MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK) |
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#define | MPU_WORD_M3UM_MASK 0x1C0000u |
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#define | MPU_WORD_M3UM_SHIFT 18 |
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#define | MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK) |
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#define | MPU_WORD_M3SM_MASK 0x600000u |
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#define | MPU_WORD_M3SM_SHIFT 21 |
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#define | MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK) |
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#define | MPU_WORD_M4WE_MASK 0x1000000u |
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#define | MPU_WORD_M4WE_SHIFT 24 |
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#define | MPU_WORD_M4RE_MASK 0x2000000u |
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#define | MPU_WORD_M4RE_SHIFT 25 |
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#define | MPU_WORD_M5WE_MASK 0x4000000u |
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#define | MPU_WORD_M5WE_SHIFT 26 |
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#define | MPU_WORD_M5RE_MASK 0x8000000u |
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#define | MPU_WORD_M5RE_SHIFT 27 |
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#define | MPU_WORD_M6WE_MASK 0x10000000u |
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#define | MPU_WORD_M6WE_SHIFT 28 |
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#define | MPU_WORD_M6RE_MASK 0x20000000u |
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#define | MPU_WORD_M6RE_SHIFT 29 |
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#define | MPU_WORD_M7WE_MASK 0x40000000u |
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#define | MPU_WORD_M7WE_SHIFT 30 |
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#define | MPU_WORD_M7RE_MASK 0x80000000u |
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#define | MPU_WORD_M7RE_SHIFT 31 |
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#define | MPU_RGDAAC_M0UM_MASK 0x7u |
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#define | MPU_RGDAAC_M0UM_SHIFT 0 |
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#define | MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK) |
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#define | MPU_RGDAAC_M0SM_MASK 0x18u |
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#define | MPU_RGDAAC_M0SM_SHIFT 3 |
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#define | MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK) |
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#define | MPU_RGDAAC_M1UM_MASK 0x1C0u |
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#define | MPU_RGDAAC_M1UM_SHIFT 6 |
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#define | MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK) |
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#define | MPU_RGDAAC_M1SM_MASK 0x600u |
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#define | MPU_RGDAAC_M1SM_SHIFT 9 |
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#define | MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK) |
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#define | MPU_RGDAAC_M2UM_MASK 0x7000u |
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#define | MPU_RGDAAC_M2UM_SHIFT 12 |
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#define | MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK) |
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#define | MPU_RGDAAC_M2SM_MASK 0x18000u |
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#define | MPU_RGDAAC_M2SM_SHIFT 15 |
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#define | MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK) |
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#define | MPU_RGDAAC_M3UM_MASK 0x1C0000u |
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#define | MPU_RGDAAC_M3UM_SHIFT 18 |
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#define | MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK) |
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#define | MPU_RGDAAC_M3SM_MASK 0x600000u |
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#define | MPU_RGDAAC_M3SM_SHIFT 21 |
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#define | MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK) |
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#define | MPU_RGDAAC_M4WE_MASK 0x1000000u |
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#define | MPU_RGDAAC_M4WE_SHIFT 24 |
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#define | MPU_RGDAAC_M4RE_MASK 0x2000000u |
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#define | MPU_RGDAAC_M4RE_SHIFT 25 |
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#define | MPU_RGDAAC_M5WE_MASK 0x4000000u |
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#define | MPU_RGDAAC_M5WE_SHIFT 26 |
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#define | MPU_RGDAAC_M5RE_MASK 0x8000000u |
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#define | MPU_RGDAAC_M5RE_SHIFT 27 |
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#define | MPU_RGDAAC_M6WE_MASK 0x10000000u |
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#define | MPU_RGDAAC_M6WE_SHIFT 28 |
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#define | MPU_RGDAAC_M6RE_MASK 0x20000000u |
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#define | MPU_RGDAAC_M6RE_SHIFT 29 |
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#define | MPU_RGDAAC_M7WE_MASK 0x40000000u |
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#define | MPU_RGDAAC_M7WE_SHIFT 30 |
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#define | MPU_RGDAAC_M7RE_MASK 0x80000000u |
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#define | MPU_RGDAAC_M7RE_SHIFT 31 |
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