|
mikroSDK Reference Manual
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Data Structures | |
| struct | ADC_TypeDef |
| Analog to Digital Converter More... | |
| struct | ADC_Common_TypeDef |
| struct | BKP_TypeDef |
| Backup Registers More... | |
| struct | CAN_TxMailBox_TypeDef |
| Controller Area Network TxMailBox. More... | |
| struct | CAN_FIFOMailBox_TypeDef |
| Controller Area Network FIFOMailBox. More... | |
| struct | CAN_FilterRegister_TypeDef |
| Controller Area Network FilterRegister. More... | |
| struct | CAN_TypeDef |
| Controller Area Network. More... | |
| struct | CRC_TypeDef |
| CRC calculation unit. More... | |
| struct | DAC_TypeDef |
| Digital to Analog Converter. More... | |
| struct | DBGMCU_TypeDef |
| Debug MCU. More... | |
| struct | DMA_Channel_TypeDef |
| DMA Controller. More... | |
| struct | DMA_TypeDef |
| struct | ETH_TypeDef |
| Ethernet MAC. More... | |
| struct | EXTI_TypeDef |
| External Interrupt/Event Controller. More... | |
| struct | FLASH_TypeDef |
| FLASH Registers. More... | |
| struct | OB_TypeDef |
| Option Bytes Registers. More... | |
| struct | GPIO_TypeDef |
| General Purpose I/O. More... | |
| struct | AFIO_TypeDef |
| Alternate Function I/O. More... | |
| struct | I2C_TypeDef |
| Inter Integrated Circuit Interface. More... | |
| struct | IWDG_TypeDef |
| Independent WATCHDOG. More... | |
| struct | PWR_TypeDef |
| Power Control. More... | |
| struct | RCC_TypeDef |
| Reset and Clock Control. More... | |
| struct | RTC_TypeDef |
| Real-Time Clock. More... | |
| struct | SPI_TypeDef |
| Serial Peripheral Interface. More... | |
| struct | TIM_TypeDef |
| TIM Timers. More... | |
| struct | USART_TypeDef |
| Universal Synchronous Asynchronous Receiver Transmitter. More... | |
| struct | USB_OTG_GlobalTypeDef |
| __USB_OTG_Core_register More... | |
| struct | USB_OTG_DeviceTypeDef |
| __device_Registers More... | |
| struct | USB_OTG_INEndpointTypeDef |
| __IN_Endpoint-Specific_Register More... | |
| struct | USB_OTG_OUTEndpointTypeDef |
| __OUT_Endpoint-Specific_Registers More... | |
| struct | USB_OTG_HostTypeDef |
| __Host_Mode_Register_Structures More... | |
| struct | USB_OTG_HostChannelTypeDef |
| __Host_Channel_Specific_Registers More... | |
| struct | WWDG_TypeDef |
| Window WATCHDOG. More... | |
| struct | DCMI_TypeDef |
| DCMI. More... | |
| struct | DMA_Stream_TypeDef |
| DMA Controller. More... | |
| struct | FSMC_Bank1_TypeDef |
| Flexible Static Memory Controller. More... | |
| struct | FSMC_Bank1E_TypeDef |
| Flexible Static Memory Controller Bank1E. More... | |
| struct | FSMC_Bank2_3_TypeDef |
| Flexible Static Memory Controller Bank2. More... | |
| struct | FSMC_Bank4_TypeDef |
| Flexible Static Memory Controller Bank4. More... | |
| struct | SYSCFG_TypeDef |
| System configuration controller. More... | |
| struct | SDIO_TypeDef |
| SD host Interface. More... | |
| struct | RNG_TypeDef |
| RNG. More... | |
| struct | CRYP_TypeDef |
| Crypto Processor. More... | |
| struct | HASH_TypeDef |
| HASH. More... | |
| struct | HASH_DIGEST_TypeDef |
| HASH_DIGEST. More... | |
| struct | DMA2D_TypeDef |
| DMA2D Controller. More... | |
| struct | FMC_Bank1_TypeDef |
| Flexible Memory Controller. More... | |
| struct | FMC_Bank1E_TypeDef |
| Flexible Memory Controller Bank1E. More... | |
| struct | FMC_Bank2_3_TypeDef |
| Flexible Memory Controller Bank2. More... | |
| struct | FMC_Bank4_TypeDef |
| Flexible Memory Controller Bank4. More... | |
| struct | FMC_Bank5_6_TypeDef |
| Flexible Memory Controller Bank5_6. More... | |
| struct | SAI_TypeDef |
| Serial Audio Interface. More... | |
| struct | SAI_Block_TypeDef |
| struct | LTDC_TypeDef |
| LCD-TFT Display Controller. More... | |
| struct | LTDC_Layer_TypeDef |
| LCD-TFT Display layer x Controller. More... | |
| struct | DSI_TypeDef |
| DSI Controller. More... | |
| struct | FMC_Bank3_TypeDef |
| Flexible Memory Controller Bank3. More... | |
| struct | QUADSPI_TypeDef |
| QUAD Serial Peripheral Interface. More... | |
| struct | CEC_TypeDef |
| HDMI-CEC. More... | |
| struct | SPDIFRX_TypeDef |
| SPDIF-RX Interface. More... | |
| struct | SDMMC_TypeDef |
| SD host Interface. More... | |
| struct | LPTIM_TypeDef |
| LPTIMIMER. More... | |
| struct | DFSDM_Filter_TypeDef |
| DFSDM module registers. More... | |
| struct | DFSDM_Channel_TypeDef |
| DFSDM channel configuration registers. More... | |
| struct | VREFBUF_TypeDef |
| VREFBUF. More... | |
| struct | FDCAN_GlobalTypeDef |
| FD Controller Area Network. More... | |
| struct | TTCAN_TypeDef |
| TTFD Controller Area Network. More... | |
| struct | FDCAN_ClockCalibrationUnit_TypeDef |
| FD Controller Area Network. More... | |
| struct | CRS_TypeDef |
| Clock Recovery System. More... | |
| struct | BDMA_Channel_TypeDef |
| struct | BDMA_TypeDef |
| struct | DMAMUX_Channel_TypeDef |
| struct | DMAMUX_ChannelStatus_TypeDef |
| struct | DMAMUX_RequestGen_TypeDef |
| struct | DMAMUX_RequestGenStatus_TypeDef |
| struct | MDMA_TypeDef |
| MDMA Controller. More... | |
| struct | MDMA_Channel_TypeDef |
| struct | EXTI_Core_TypeDef |
| This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only. More... | |
| struct | FMC_Bank2_TypeDef |
| Flexible Memory Controller Bank2. More... | |
| struct | OPAMP_TypeDef |
| Operational Amplifier (OPAMP) More... | |
| struct | JPEG_TypeDef |
| JPEG Codec. More... | |
| struct | DLYB_TypeDef |
| Delay Block DLYB. More... | |
| struct | HSEM_TypeDef |
| HW Semaphore HSEM. More... | |
| struct | HSEM_Common_TypeDef |
| struct | COMPOPT_TypeDef |
| Comparator. More... | |
| struct | COMP_TypeDef |
| struct | COMP_Common_TypeDef |
| struct | SWPMI_TypeDef |
| Single Wire Protocol Master Interface SPWMI. More... | |
| struct | RAMECC_MonitorTypeDef |
| RAM_ECC_Specific_Registers. More... | |
| struct | RAMECC_TypeDef |
Macros | |
| #define | FLASH_BASE 0x08000000UL |
| Peripheral_memory_map. | |
| #define | SRAM1_BASE 0x20000000UL |
| #define | SRAM2_BASE 0x2001C000UL |
| #define | PERIPH_BASE 0x40000000UL |
| #define | BKPSRAM_BASE 0x40024000UL |
| #define | FSMC_R_BASE 0xA0000000UL |
| #define | SRAM1_BB_BASE 0x22000000UL |
| #define | SRAM2_BB_BASE 0x22380000UL |
| #define | PERIPH_BB_BASE 0x42000000UL |
| #define | BKPSRAM_BB_BASE 0x42480000UL |
| #define | FLASH_END 0x080FFFFFUL |
| #define | FLASH_OTP_BASE 0x1FFF7800UL |
| #define | FLASH_OTP_END 0x1FFF7A0FUL |
| #define | SRAM_BASE SRAM1_BASE |
| #define | SRAM_BB_BASE SRAM1_BB_BASE |
| #define | APB1PERIPH_BASE PERIPH_BASE |
| #define | APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
| #define | AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| #define | AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) |
| #define | TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) |
| #define | TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) |
| #define | TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) |
| #define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) |
| #define | TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) |
| #define | TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) |
| #define | TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) |
| #define | TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) |
| #define | TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) |
| #define | RTC_BASE (APB1PERIPH_BASE + 0x2800UL) |
| #define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) |
| #define | IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) |
| #define | SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) |
| #define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) |
| #define | USART2_BASE (APB1PERIPH_BASE + 0x4400UL) |
| #define | USART3_BASE (APB1PERIPH_BASE + 0x4800UL) |
| #define | UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) |
| #define | UART5_BASE (APB1PERIPH_BASE + 0x5000UL) |
| #define | I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) |
| #define | I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) |
| #define | I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) |
| #define | CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) |
| #define | CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) |
| #define | PWR_BASE (APB1PERIPH_BASE + 0x7000UL) |
| #define | DAC_BASE (APB1PERIPH_BASE + 0x7400UL) |
| #define | TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) |
| #define | TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) |
| #define | USART1_BASE (APB2PERIPH_BASE + 0x1000UL) |
| #define | USART6_BASE (APB2PERIPH_BASE + 0x1400UL) |
| #define | ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) |
| #define | ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) |
| #define | ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) |
| #define | ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL) |
| #define | ADC_BASE ADC123_COMMON_BASE |
| #define | SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL) |
| #define | SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) |
| #define | SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) |
| #define | EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) |
| #define | TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) |
| #define | TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) |
| #define | TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) |
| #define | GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) |
| #define | GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) |
| #define | GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) |
| #define | GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) |
| #define | GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) |
| #define | GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) |
| #define | GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) |
| #define | GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) |
| #define | GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL) |
| #define | CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) |
| #define | RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) |
| #define | FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) |
| #define | DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) |
| #define | DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) |
| #define | DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) |
| #define | DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) |
| #define | DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) |
| #define | DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) |
| #define | DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) |
| #define | DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) |
| #define | DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) |
| #define | DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) |
| #define | DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) |
| #define | DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) |
| #define | DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) |
| #define | DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) |
| #define | DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) |
| #define | DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) |
| #define | DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) |
| #define | DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) |
| #define | ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) |
| #define | ETH_MAC_BASE (ETH_BASE) |
| #define | ETH_MMC_BASE (ETH_BASE + 0x0100UL) |
| #define | ETH_PTP_BASE (ETH_BASE + 0x0700UL) |
| #define | ETH_DMA_BASE (ETH_BASE + 0x1000UL) |
| #define | DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) |
| #define | RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) |
| #define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL) |
| #define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL) |
| #define | FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL) |
| #define | FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL) |
| #define | DBGMCU_BASE 0xE0042000UL |
| #define | USB_OTG_HS_PERIPH_BASE 0x40040000UL |
| #define | USB_OTG_FS_PERIPH_BASE 0x50000000UL |
| #define | USB_OTG_GLOBAL_BASE 0x000UL |
| #define | USB_OTG_DEVICE_BASE 0x800UL |
| #define | USB_OTG_IN_ENDPOINT_BASE 0x900UL |
| #define | USB_OTG_OUT_ENDPOINT_BASE 0xB00UL |
| #define | USB_OTG_EP_REG_SIZE 0x20UL |
| #define | USB_OTG_HOST_BASE 0x400UL |
| #define | USB_OTG_HOST_PORT_BASE 0x440UL |
| #define | USB_OTG_HOST_CHANNEL_BASE 0x500UL |
| #define | USB_OTG_HOST_CHANNEL_SIZE 0x20UL |
| #define | USB_OTG_PCGCCTL_BASE 0xE00UL |
| #define | USB_OTG_FIFO_BASE 0x1000UL |
| #define | USB_OTG_FIFO_SIZE 0x1000UL |
| #define | UID_BASE 0x1FFF7A10UL |
| #define | FLASHSIZE_BASE 0x1FFF7A22UL |
| #define | FLASH_BASE 0x08000000UL |
| Peripheral_memory_map. | |
| #define | SRAM1_BASE 0x20000000UL |
| #define | SRAM2_BASE 0x2001C000UL |
| #define | PERIPH_BASE 0x40000000UL |
| #define | BKPSRAM_BASE 0x40024000UL |
| #define | FSMC_R_BASE 0xA0000000UL |
| #define | SRAM1_BB_BASE 0x22000000UL |
| #define | SRAM2_BB_BASE 0x22380000UL |
| #define | PERIPH_BB_BASE 0x42000000UL |
| #define | BKPSRAM_BB_BASE 0x42480000UL |
| #define | FLASH_END 0x080FFFFFUL |
| #define | FLASH_OTP_BASE 0x1FFF7800UL |
| #define | FLASH_OTP_END 0x1FFF7A0FUL |
| #define | SRAM_BASE SRAM1_BASE |
| #define | SRAM_BB_BASE SRAM1_BB_BASE |
| #define | APB1PERIPH_BASE PERIPH_BASE |
| #define | APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
| #define | AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| #define | AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) |
| #define | TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) |
| #define | TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) |
| #define | TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) |
| #define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) |
| #define | TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) |
| #define | TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) |
| #define | TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) |
| #define | TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) |
| #define | TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) |
| #define | RTC_BASE (APB1PERIPH_BASE + 0x2800UL) |
| #define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) |
| #define | IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) |
| #define | SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) |
| #define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) |
| #define | USART2_BASE (APB1PERIPH_BASE + 0x4400UL) |
| #define | USART3_BASE (APB1PERIPH_BASE + 0x4800UL) |
| #define | UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) |
| #define | UART5_BASE (APB1PERIPH_BASE + 0x5000UL) |
| #define | I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) |
| #define | I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) |
| #define | I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) |
| #define | CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) |
| #define | CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) |
| #define | PWR_BASE (APB1PERIPH_BASE + 0x7000UL) |
| #define | DAC_BASE (APB1PERIPH_BASE + 0x7400UL) |
| #define | TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) |
| #define | TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) |
| #define | USART1_BASE (APB2PERIPH_BASE + 0x1000UL) |
| #define | USART6_BASE (APB2PERIPH_BASE + 0x1400UL) |
| #define | ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) |
| #define | ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) |
| #define | ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) |
| #define | ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL) |
| #define | ADC_BASE ADC123_COMMON_BASE |
| #define | SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL) |
| #define | SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) |
| #define | SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) |
| #define | EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) |
| #define | TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) |
| #define | TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) |
| #define | TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) |
| #define | GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) |
| #define | GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) |
| #define | GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) |
| #define | GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) |
| #define | GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) |
| #define | GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) |
| #define | GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) |
| #define | GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) |
| #define | GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL) |
| #define | CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) |
| #define | RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) |
| #define | FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) |
| #define | DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) |
| #define | DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) |
| #define | DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) |
| #define | DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) |
| #define | DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) |
| #define | DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) |
| #define | DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) |
| #define | DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) |
| #define | DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) |
| #define | DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) |
| #define | DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) |
| #define | DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) |
| #define | DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) |
| #define | DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) |
| #define | DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) |
| #define | DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) |
| #define | DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) |
| #define | DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) |
| #define | ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) |
| #define | ETH_MAC_BASE (ETH_BASE) |
| #define | ETH_MMC_BASE (ETH_BASE + 0x0100UL) |
| #define | ETH_PTP_BASE (ETH_BASE + 0x0700UL) |
| #define | ETH_DMA_BASE (ETH_BASE + 0x1000UL) |
| #define | DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) |
| #define | CRYP_BASE (AHB2PERIPH_BASE + 0x60000UL) |
| #define | HASH_BASE (AHB2PERIPH_BASE + 0x60400UL) |
| #define | RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) |
| #define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL) |
| #define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL) |
| #define | FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL) |
| #define | FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL) |
| #define | DBGMCU_BASE 0xE0042000UL |
| #define | USB_OTG_HS_PERIPH_BASE 0x40040000UL |
| #define | USB_OTG_FS_PERIPH_BASE 0x50000000UL |
| #define | USB_OTG_GLOBAL_BASE 0x000UL |
| #define | USB_OTG_DEVICE_BASE 0x800UL |
| #define | USB_OTG_IN_ENDPOINT_BASE 0x900UL |
| #define | USB_OTG_OUT_ENDPOINT_BASE 0xB00UL |
| #define | USB_OTG_EP_REG_SIZE 0x20UL |
| #define | USB_OTG_HOST_BASE 0x400UL |
| #define | USB_OTG_HOST_PORT_BASE 0x440UL |
| #define | USB_OTG_HOST_CHANNEL_BASE 0x500UL |
| #define | USB_OTG_HOST_CHANNEL_SIZE 0x20UL |
| #define | USB_OTG_PCGCCTL_BASE 0xE00UL |
| #define | USB_OTG_FIFO_BASE 0x1000UL |
| #define | USB_OTG_FIFO_SIZE 0x1000UL |
| #define | UID_BASE 0x1FFF7A10UL |
| #define | FLASHSIZE_BASE 0x1FFF7A22UL |
| #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) |
APB1 peripherals
| #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) |
APB1 peripherals
| #define BKPSRAM_BASE 0x40024000UL |
Backup SRAM(4 KB) base address in the alias region
| #define BKPSRAM_BASE 0x40024000UL |
Backup SRAM(4 KB) base address in the alias region
| #define BKPSRAM_BB_BASE 0x42480000UL |
Backup SRAM(4 KB) base address in the bit-band region
| #define BKPSRAM_BB_BASE 0x42480000UL |
Backup SRAM(4 KB) base address in the bit-band region
| #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) |
APB2 peripherals
| #define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) |
APB2 peripherals
| #define DBGMCU_BASE 0xE0042000UL |
USB registers base address
| #define DBGMCU_BASE 0xE0042000UL |
USB registers base address
| #define ETH_DMA_BASE (ETH_BASE + 0x1000UL) |
AHB2 peripherals
| #define ETH_DMA_BASE (ETH_BASE + 0x1000UL) |
AHB2 peripherals
| #define FLASH_BASE 0x08000000UL |
FLASH(up to 1 MB) base address in the alias region
| #define FLASH_BASE 0x08000000UL |
FLASH(up to 1 MB) base address in the alias region
| #define FLASH_END 0x080FFFFFUL |
FLASH end address
| #define FLASH_END 0x080FFFFFUL |
FLASH end address
| #define FLASH_OTP_BASE 0x1FFF7800UL |
Base address of : (up to 528 Bytes) embedded FLASH OTP Area
| #define FLASH_OTP_BASE 0x1FFF7800UL |
Base address of : (up to 528 Bytes) embedded FLASH OTP Area
| #define FLASH_OTP_END 0x1FFF7A0FUL |
End address of : (up to 528 Bytes) embedded FLASH OTP Area
| #define FLASH_OTP_END 0x1FFF7A0FUL |
End address of : (up to 528 Bytes) embedded FLASH OTP Area
| #define FLASHSIZE_BASE 0x1FFF7A22UL |
FLASH Size register base address
| #define FLASHSIZE_BASE 0x1FFF7A22UL |
FLASH Size register base address
| #define FSMC_R_BASE 0xA0000000UL |
FSMC registers base address
| #define FSMC_R_BASE 0xA0000000UL |
FSMC registers base address
| #define PERIPH_BASE 0x40000000UL |
Peripheral base address in the alias region
| #define PERIPH_BASE 0x40000000UL |
Peripheral base address in the alias region
| #define PERIPH_BB_BASE 0x42000000UL |
Peripheral base address in the bit-band region
| #define PERIPH_BB_BASE 0x42000000UL |
Peripheral base address in the bit-band region
| #define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) |
FSMC Bankx registers base address
| #define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) |
FSMC Bankx registers base address
| #define SRAM1_BASE 0x20000000UL |
SRAM1(112 KB) base address in the alias region
| #define SRAM1_BASE 0x20000000UL |
SRAM1(112 KB) base address in the alias region
| #define SRAM1_BB_BASE 0x22000000UL |
SRAM1(112 KB) base address in the bit-band region
| #define SRAM1_BB_BASE 0x22000000UL |
SRAM1(112 KB) base address in the bit-band region
| #define SRAM2_BASE 0x2001C000UL |
SRAM2(16 KB) base address in the alias region
| #define SRAM2_BASE 0x2001C000UL |
SRAM2(16 KB) base address in the alias region
| #define SRAM2_BB_BASE 0x22380000UL |
SRAM2(16 KB) base address in the bit-band region
| #define SRAM2_BB_BASE 0x22380000UL |
SRAM2(16 KB) base address in the bit-band region
| #define SRAM_BB_BASE SRAM1_BB_BASE |
Peripheral memory map
| #define SRAM_BB_BASE SRAM1_BB_BASE |
Peripheral memory map
| #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) |
AHB1 peripherals
| #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) |
AHB1 peripherals
| #define UID_BASE 0x1FFF7A10UL |
Unique device ID register base address
| #define UID_BASE 0x1FFF7A10UL |
Unique device ID register base address