PLL Configuration

Macros
#define	__HAL_RCC_PLL_ENABLE()   (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
	Macro to enable the main PLL.
#define	__HAL_RCC_PLL_DISABLE()   (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
	Macro to disable the main PLL.
#define	__HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)    MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
	Macro to configure the main PLL clock source and multiplication factors.
#define	__HAL_RCC_GET_PLL_OSCSOURCE()   ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
	Get oscillator clock selected as PLL input clock.
#define	__HAL_RCC_PLL_ENABLE()   (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
	Macros to enable or disable the main PLL.
#define	__HAL_RCC_PLL_DISABLE()   (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
#define	__HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)
	Macro to configure the main PLL clock source, multiplication and division factors.
#define	__HAL_RCC_PLL_ENABLE()   (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
	Macros to enable or disable the main PLL.
#define	__HAL_RCC_PLL_DISABLE()   (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
#define	__HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__)   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
	Macro to configure the PLL clock source.
#define	__HAL_RCC_PLL_PLLM_CONFIG(__PLLM__)   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
	Macro to configure the PLL multiplication factor.
#define	__HAL_RCC_PLL_ENABLE()   SET_BIT(RCC->CR, RCC_CR_PLLON)
	Macros to enable or disable the main PLL.
#define	__HAL_RCC_PLL_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
#define	__HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__)   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
	Macro to configure the PLL clock source.
#define	__HAL_RCC_PLL_PLLM_CONFIG(__PLLM__)   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
	Macro to configure the PLL multiplication factor.

Macro Definition Documentation

__HAL_RCC_GET_PLL_OSCSOURCE

#define __HAL_RCC_GET_PLL_OSCSOURCE

(

)

((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))

Return values

The	clock source used for PLL entry. The returned value can be one of the following: RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock

__HAL_RCC_PLL_CONFIG [1/2]

#define __HAL_RCC_PLL_CONFIG	(		__RCC_PLLSource__,
			__PLLM__,
			__PLLN__,
			__PLLP__,
			__PLLQ__ )

Value:

                   MODIFY_REG(RCC->PLLCFGR, \
                              (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ), \
                              ((__RCC_PLLSource__) | (__PLLM__)| ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \
                               ((((__PLLP__) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)))

Note

This function must be used only when the main PLL is disabled.

Parameters

__RCC_PLLSource__

specifies the PLL entry clock source. This parameter can be one of the following values: RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

Note

This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.

Parameters

__PLLM__

specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note

You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

Parameters

__PLLN__

specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 192 and Max_Data = 432.

Note

You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.

Parameters

__PLLP__	specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
__PLLQ__	specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.

Note

If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.

__HAL_RCC_PLL_CONFIG [2/2]

#define __HAL_RCC_PLL_CONFIG	(		__RCC_PLLSOURCE__,
			__PLLMUL__ )    MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))

Macro to configure the main PLL clock source, multiplication and division factors.

Note

This function must be used only when the main PLL is disabled.

Parameters

__RCC_PLLSOURCE__

specifies the PLL entry clock source. This parameter can be one of the following values: RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry

__PLLMUL__

specifies the multiplication factor for PLL VCO output clock This parameter can be one of the following values: RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9

Note

This function must be used only when the main PLL is disabled.

Parameters

__RCC_PLLSource__

specifies the PLL entry clock source. This parameter can be one of the following values: RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

Note

This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.

Parameters

__PLLM__

specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note

You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

Parameters

__PLLN__

specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 192 and Max_Data = 432.

Note

You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.

Parameters

__PLLP__	specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
__PLLQ__	specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.

Note

If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.

__HAL_RCC_PLL_DISABLE

#define __HAL_RCC_PLL_DISABLE

(

)

(*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)

Note

The main PLL can not be disabled if it is used as system clock source

__HAL_RCC_PLL_ENABLE [1/4]

#define __HAL_RCC_PLL_ENABLE

(

)

(*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)

Macros to enable or disable the main PLL.

Note

After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.

The main PLL is disabled by hardware when entering STOP and STANDBY modes.

After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.

The main PLL can not be disabled if it is used as system clock source

The main PLL is disabled by hardware when entering STOP and STANDBY modes.

__HAL_RCC_PLL_ENABLE [2/4]

#define __HAL_RCC_PLL_ENABLE

(

)

(*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)

Note

After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.

The main PLL can not be disabled if it is used as system clock source

The main PLL is disabled by hardware when entering STOP and STANDBY modes.

__HAL_RCC_PLL_ENABLE [3/4]

#define __HAL_RCC_PLL_ENABLE

(

)

(*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)

Note

After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.

The main PLL can not be disabled if it is used as system clock source

The main PLL is disabled by hardware when entering STOP and STANDBY modes.

__HAL_RCC_PLL_ENABLE [4/4]

#define __HAL_RCC_PLL_ENABLE

(

)

SET_BIT(RCC->CR, RCC_CR_PLLON)

Note

After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.

The main PLL can not be disabled if it is used as system clock source

The main PLL is disabled by hardware when entering STOP and STANDBY modes.

__HAL_RCC_PLL_PLLM_CONFIG [1/2]

#define __HAL_RCC_PLL_PLLM_CONFIG

(

__PLLM__

)

MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))

Note

This function must be used only when the main PLL is disabled.

Parameters

__PLLM__

specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note

You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

__HAL_RCC_PLL_PLLM_CONFIG [2/2]

#define __HAL_RCC_PLL_PLLM_CONFIG

(

__PLLM__

)

MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))

Note

This function must be used only when the main PLL is disabled.

Parameters

__PLLM__

specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note

You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

__HAL_RCC_PLL_PLLSOURCE_CONFIG [1/2]

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG

(

__PLLSOURCE__

)

MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))

Note

This function must be used only when the main PLL is disabled.

Parameters

__PLLSOURCE__

specifies the PLL entry clock source. This parameter can be one of the following values: RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

__HAL_RCC_PLL_PLLSOURCE_CONFIG [2/2]

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG

(

__PLLSOURCE__

)

MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))

Note

This function must be used only when the main PLL is disabled.

Parameters

__PLLSOURCE__

specifies the PLL entry clock source. This parameter can be one of the following values: RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry