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#define | RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) |
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#define | RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) |
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#define | RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) |
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#define | CR_REG_INDEX ((uint8_t)1) |
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#define | BDCR_REG_INDEX ((uint8_t)2) |
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#define | CSR_REG_INDEX ((uint8_t)3) |
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#define | RCC_FLAG_MASK ((uint8_t)0x1F) |
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#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
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#define | HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ |
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#define | LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ |
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#define | PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ |
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#define | CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
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#define | PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ |
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#define | PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ |
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#define | HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
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#define | HSI_TIMEOUT_VALUE (2U) /* 2 ms */ |
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#define | HSI48_TIMEOUT_VALUE (2U) /* 2 ms */ |
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#define | CSI_TIMEOUT_VALUE (2U) /* 2 ms */ |
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#define | LSI_TIMEOUT_VALUE (2U) /* 2 ms */ |
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#define | PLL_TIMEOUT_VALUE (2U) /* 2 ms */ |
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#define | CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ |
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#define | RCC_DBP_TIMEOUT_VALUE (100U) |
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#define | RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
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