Macros
#define	SDRAM_AC_COUNT (2U)

#define	SDRAM_CM_COUNT (2U)

#define	SDRAM_AC_COUNT (2U)

#define	SDRAM_CM_COUNT (2U)

CTRL - Control Register
#define	SDRAM_CTRL_RC_MASK (0x1FFU)

#define	SDRAM_CTRL_RC_SHIFT (0U)

#define	SDRAM_CTRL_RC(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)

#define	SDRAM_CTRL_RTIM_MASK (0x600U)

#define	SDRAM_CTRL_RTIM_SHIFT (9U)

#define	SDRAM_CTRL_RTIM(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)

#define	SDRAM_CTRL_IS_MASK (0x800U)

#define	SDRAM_CTRL_IS_SHIFT (11U)

#define	SDRAM_CTRL_IS(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)

#define	SDRAM_CTRL_RC_MASK (0x1FFU)

#define	SDRAM_CTRL_RC_SHIFT (0U)

#define	SDRAM_CTRL_RC(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)

#define	SDRAM_CTRL_RTIM_MASK (0x600U)

#define	SDRAM_CTRL_RTIM_SHIFT (9U)

#define	SDRAM_CTRL_RTIM(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)

#define	SDRAM_CTRL_IS_MASK (0x800U)

#define	SDRAM_CTRL_IS_SHIFT (11U)

#define	SDRAM_CTRL_IS(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)

AC - Address and Control Register
#define	SDRAM_AC_IP_MASK (0x8U)

#define	SDRAM_AC_IP_SHIFT (3U)

#define	SDRAM_AC_IP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)

#define	SDRAM_AC_PS_MASK (0x30U)

#define	SDRAM_AC_PS_SHIFT (4U)

#define	SDRAM_AC_PS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)

#define	SDRAM_AC_IMRS_MASK (0x40U)

#define	SDRAM_AC_IMRS_SHIFT (6U)

#define	SDRAM_AC_IMRS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)

#define	SDRAM_AC_CBM_MASK (0x700U)

#define	SDRAM_AC_CBM_SHIFT (8U)

#define	SDRAM_AC_CBM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)

#define	SDRAM_AC_CASL_MASK (0x3000U)

#define	SDRAM_AC_CASL_SHIFT (12U)

#define	SDRAM_AC_CASL(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)

#define	SDRAM_AC_RE_MASK (0x8000U)

#define	SDRAM_AC_RE_SHIFT (15U)

#define	SDRAM_AC_RE(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)

#define	SDRAM_AC_BA_MASK (0xFFFC0000U)

#define	SDRAM_AC_BA_SHIFT (18U)

#define	SDRAM_AC_BA(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)

#define	SDRAM_AC_IP_MASK (0x8U)

#define	SDRAM_AC_IP_SHIFT (3U)

#define	SDRAM_AC_IP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)

#define	SDRAM_AC_PS_MASK (0x30U)

#define	SDRAM_AC_PS_SHIFT (4U)

#define	SDRAM_AC_PS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)

#define	SDRAM_AC_IMRS_MASK (0x40U)

#define	SDRAM_AC_IMRS_SHIFT (6U)

#define	SDRAM_AC_IMRS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)

#define	SDRAM_AC_CBM_MASK (0x700U)

#define	SDRAM_AC_CBM_SHIFT (8U)

#define	SDRAM_AC_CBM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)

#define	SDRAM_AC_CASL_MASK (0x3000U)

#define	SDRAM_AC_CASL_SHIFT (12U)

#define	SDRAM_AC_CASL(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)

#define	SDRAM_AC_RE_MASK (0x8000U)

#define	SDRAM_AC_RE_SHIFT (15U)

#define	SDRAM_AC_RE(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)

#define	SDRAM_AC_BA_MASK (0xFFFC0000U)

#define	SDRAM_AC_BA_SHIFT (18U)

#define	SDRAM_AC_BA(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)

CM - Control Mask
#define	SDRAM_CM_V_MASK (0x1U)

#define	SDRAM_CM_V_SHIFT (0U)

#define	SDRAM_CM_V(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)

#define	SDRAM_CM_WP_MASK (0x100U)

#define	SDRAM_CM_WP_SHIFT (8U)

#define	SDRAM_CM_WP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)

#define	SDRAM_CM_BAM_MASK (0xFFFC0000U)

#define	SDRAM_CM_BAM_SHIFT (18U)

#define	SDRAM_CM_BAM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)

#define	SDRAM_CM_V_MASK (0x1U)

#define	SDRAM_CM_V_SHIFT (0U)

#define	SDRAM_CM_V(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)

#define	SDRAM_CM_WP_MASK (0x100U)

#define	SDRAM_CM_WP_SHIFT (8U)

#define	SDRAM_CM_WP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)

#define	SDRAM_CM_BAM_MASK (0xFFFC0000U)

#define	SDRAM_CM_BAM_SHIFT (18U)

#define	SDRAM_CM_BAM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)

Macro Definition Documentation

◆ SDRAM_AC_IMRS [1/2]

#define SDRAM_AC_IMRS ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)

IMRS - Initiate mode register set (mrs) command. 0b0..Take no action 0b1..Initiate mrs command

◆ SDRAM_AC_IMRS [2/2]

#define SDRAM_AC_IMRS ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)

IMRS - Initiate mode register set (mrs) command. 0b0..Take no action 0b1..Initiate mrs command

◆ SDRAM_AC_IP [1/2]

#define SDRAM_AC_IP ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)

IP - Initiate precharge all (pall) command. 0b0..Take no action. 0b1..A pall command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the pall command to the SDRAM block.

◆ SDRAM_AC_IP [2/2]

#define SDRAM_AC_IP ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)

IP - Initiate precharge all (pall) command. 0b0..Take no action. 0b1..A pall command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the pall command to the SDRAM block.

◆ SDRAM_AC_PS [1/2]

#define SDRAM_AC_PS ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)

PS - Port size. 0b00..32-bit port 0b01..8-bit port 0b10..16-bit port 0b11..16-bit port

◆ SDRAM_AC_PS [2/2]

#define SDRAM_AC_PS ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)

PS - Port size. 0b00..32-bit port 0b01..8-bit port 0b10..16-bit port 0b11..16-bit port

◆ SDRAM_AC_RE [1/2]

#define SDRAM_AC_RE ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)

RE - Refresh enable 0b0..Do not refresh associated DRAM block 0b1..Refresh associated DRAM block

◆ SDRAM_AC_RE [2/2]

#define SDRAM_AC_RE ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)

RE - Refresh enable 0b0..Do not refresh associated DRAM block 0b1..Refresh associated DRAM block

◆ SDRAM_CM_BAM [1/2]

#define SDRAM_CM_BAM ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)

BAM - Base address mask. 0b00000000000000..The associated address bit is used in decoding the DRAM hit to a memory block 0b00000000000001..The associated address bit is not used in the DRAM hit decode

◆ SDRAM_CM_BAM [2/2]

#define SDRAM_CM_BAM ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)

BAM - Base address mask. 0b00000000000000..The associated address bit is used in decoding the DRAM hit to a memory block 0b00000000000001..The associated address bit is not used in the DRAM hit decode

◆ SDRAM_CM_V [1/2]

#define SDRAM_CM_V ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)

V - Valid. 0b0..Do not decode DRAM accesses. 0b1..Registers controlling the DRAM block are initialized; DRAM accesses can be decoded

◆ SDRAM_CM_V [2/2]

#define SDRAM_CM_V ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)

V - Valid. 0b0..Do not decode DRAM accesses. 0b1..Registers controlling the DRAM block are initialized; DRAM accesses can be decoded

◆ SDRAM_CM_WP [1/2]

#define SDRAM_CM_WP ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)

WP - Write protect. 0b0..Allow write accesses 0b1..Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs.

◆ SDRAM_CM_WP [2/2]

#define SDRAM_CM_WP ( x ) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)

WP - Write protect. 0b0..Allow write accesses 0b1..Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs.

◆ SDRAM_CTRL_IS [1/2]

#define SDRAM_CTRL_IS ( x ) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)

IS 0b0..Take no action or issue a selfx command to exit self refresh. 0b1..SDRAM controller sends a self command to both SDRAM blocks to put them in low-power, self-refresh state where they remain until IS is cleared. When IS is cleared, the controller sends a selfx command for the SDRAMs to exit self-refresh. The refresh counter is suspended while the SDRAMs are in self-refresh; the SDRAM controls the refresh period.

◆ SDRAM_CTRL_IS [2/2]