Macros
#define	TPM_CnSC_COUNT (2U)

#define	TPM_CnV_COUNT (2U)

#define	TPM_CnSC_COUNT (2U)

#define	TPM_CnV_COUNT (2U)

SC - Status And Control
#define	TPM_SC_PS_MASK (0x7U)

#define	TPM_SC_PS_SHIFT (0U)

#define	TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)

#define	TPM_SC_CMOD_MASK (0x18U)

#define	TPM_SC_CMOD_SHIFT (3U)

#define	TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)

#define	TPM_SC_CPWMS_MASK (0x20U)

#define	TPM_SC_CPWMS_SHIFT (5U)

#define	TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)

#define	TPM_SC_TOIE_MASK (0x40U)

#define	TPM_SC_TOIE_SHIFT (6U)

#define	TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)

#define	TPM_SC_TOF_MASK (0x80U)

#define	TPM_SC_TOF_SHIFT (7U)

#define	TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)

#define	TPM_SC_DMA_MASK (0x100U)

#define	TPM_SC_DMA_SHIFT (8U)

#define	TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)

#define	TPM_SC_PS_MASK (0x7U)

#define	TPM_SC_PS_SHIFT (0U)

#define	TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)

#define	TPM_SC_CMOD_MASK (0x18U)

#define	TPM_SC_CMOD_SHIFT (3U)

#define	TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)

#define	TPM_SC_CPWMS_MASK (0x20U)

#define	TPM_SC_CPWMS_SHIFT (5U)

#define	TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)

#define	TPM_SC_TOIE_MASK (0x40U)

#define	TPM_SC_TOIE_SHIFT (6U)

#define	TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)

#define	TPM_SC_TOF_MASK (0x80U)

#define	TPM_SC_TOF_SHIFT (7U)

#define	TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)

#define	TPM_SC_DMA_MASK (0x100U)

#define	TPM_SC_DMA_SHIFT (8U)

#define	TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)

CNT - Counter
#define	TPM_CNT_COUNT_MASK (0xFFFFU)

#define	TPM_CNT_COUNT_SHIFT (0U)

#define	TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)

#define	TPM_CNT_COUNT_MASK (0xFFFFU)

#define	TPM_CNT_COUNT_SHIFT (0U)

#define	TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)

MOD - Modulo
#define	TPM_MOD_MOD_MASK (0xFFFFU)

#define	TPM_MOD_MOD_SHIFT (0U)

#define	TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)

#define	TPM_MOD_MOD_MASK (0xFFFFU)

#define	TPM_MOD_MOD_SHIFT (0U)

#define	TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)

CnSC - Channel (n) Status And Control
#define	TPM_CnSC_DMA_MASK (0x1U)

#define	TPM_CnSC_DMA_SHIFT (0U)

#define	TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)

#define	TPM_CnSC_ELSA_MASK (0x4U)

#define	TPM_CnSC_ELSA_SHIFT (2U)

#define	TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)

#define	TPM_CnSC_ELSB_MASK (0x8U)

#define	TPM_CnSC_ELSB_SHIFT (3U)

#define	TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)

#define	TPM_CnSC_MSA_MASK (0x10U)

#define	TPM_CnSC_MSA_SHIFT (4U)

#define	TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)

#define	TPM_CnSC_MSB_MASK (0x20U)

#define	TPM_CnSC_MSB_SHIFT (5U)

#define	TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)

#define	TPM_CnSC_CHIE_MASK (0x40U)

#define	TPM_CnSC_CHIE_SHIFT (6U)

#define	TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)

#define	TPM_CnSC_CHF_MASK (0x80U)

#define	TPM_CnSC_CHF_SHIFT (7U)

#define	TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)

#define	TPM_CnSC_DMA_MASK (0x1U)

#define	TPM_CnSC_DMA_SHIFT (0U)

#define	TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)

#define	TPM_CnSC_ELSA_MASK (0x4U)

#define	TPM_CnSC_ELSA_SHIFT (2U)

#define	TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)

#define	TPM_CnSC_ELSB_MASK (0x8U)

#define	TPM_CnSC_ELSB_SHIFT (3U)

#define	TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)

#define	TPM_CnSC_MSA_MASK (0x10U)

#define	TPM_CnSC_MSA_SHIFT (4U)

#define	TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)

#define	TPM_CnSC_MSB_MASK (0x20U)

#define	TPM_CnSC_MSB_SHIFT (5U)

#define	TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)

#define	TPM_CnSC_CHIE_MASK (0x40U)

#define	TPM_CnSC_CHIE_SHIFT (6U)

#define	TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)

#define	TPM_CnSC_CHF_MASK (0x80U)

#define	TPM_CnSC_CHF_SHIFT (7U)

#define	TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)

CnV - Channel (n) Value
#define	TPM_CnV_VAL_MASK (0xFFFFU)

#define	TPM_CnV_VAL_SHIFT (0U)

#define	TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)

#define	TPM_CnV_VAL_MASK (0xFFFFU)

#define	TPM_CnV_VAL_SHIFT (0U)

#define	TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)

STATUS - Capture And Compare Status
#define	TPM_STATUS_CH0F_MASK (0x1U)

#define	TPM_STATUS_CH0F_SHIFT (0U)

#define	TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)

#define	TPM_STATUS_CH1F_MASK (0x2U)

#define	TPM_STATUS_CH1F_SHIFT (1U)

#define	TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)

#define	TPM_STATUS_TOF_MASK (0x100U)

#define	TPM_STATUS_TOF_SHIFT (8U)

#define	TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)

#define	TPM_STATUS_CH0F_MASK (0x1U)

#define	TPM_STATUS_CH0F_SHIFT (0U)

#define	TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)

#define	TPM_STATUS_CH1F_MASK (0x2U)

#define	TPM_STATUS_CH1F_SHIFT (1U)

#define	TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)

#define	TPM_STATUS_TOF_MASK (0x100U)

#define	TPM_STATUS_TOF_SHIFT (8U)

#define	TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)

COMBINE - Combine Channel Register
#define	TPM_COMBINE_COMBINE0_MASK (0x1U)

#define	TPM_COMBINE_COMBINE0_SHIFT (0U)

#define	TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)

#define	TPM_COMBINE_COMSWAP0_MASK (0x2U)

#define	TPM_COMBINE_COMSWAP0_SHIFT (1U)

#define	TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)

#define	TPM_COMBINE_COMBINE0_MASK (0x1U)

#define	TPM_COMBINE_COMBINE0_SHIFT (0U)

#define	TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)

#define	TPM_COMBINE_COMSWAP0_MASK (0x2U)

#define	TPM_COMBINE_COMSWAP0_SHIFT (1U)

#define	TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)

POL - Channel Polarity
#define	TPM_POL_POL0_MASK (0x1U)

#define	TPM_POL_POL0_SHIFT (0U)

#define	TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)

#define	TPM_POL_POL1_MASK (0x2U)

#define	TPM_POL_POL1_SHIFT (1U)

#define	TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)

#define	TPM_POL_POL0_MASK (0x1U)

#define	TPM_POL_POL0_SHIFT (0U)

#define	TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)

#define	TPM_POL_POL1_MASK (0x2U)

#define	TPM_POL_POL1_SHIFT (1U)

#define	TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)

FILTER - Filter Control
#define	TPM_FILTER_CH0FVAL_MASK (0xFU)

#define	TPM_FILTER_CH0FVAL_SHIFT (0U)

#define	TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)

#define	TPM_FILTER_CH1FVAL_MASK (0xF0U)

#define	TPM_FILTER_CH1FVAL_SHIFT (4U)

#define	TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)

#define	TPM_FILTER_CH0FVAL_MASK (0xFU)

#define	TPM_FILTER_CH0FVAL_SHIFT (0U)

#define	TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)

#define	TPM_FILTER_CH1FVAL_MASK (0xF0U)

#define	TPM_FILTER_CH1FVAL_SHIFT (4U)

#define	TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)

QDCTRL - Quadrature Decoder Control And Status
#define	TPM_QDCTRL_QUADEN_MASK (0x1U)

#define	TPM_QDCTRL_QUADEN_SHIFT (0U)

#define	TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)

#define	TPM_QDCTRL_TOFDIR_MASK (0x2U)

#define	TPM_QDCTRL_TOFDIR_SHIFT (1U)

#define	TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)

#define	TPM_QDCTRL_QUADIR_MASK (0x4U)

#define	TPM_QDCTRL_QUADIR_SHIFT (2U)

#define	TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)

#define	TPM_QDCTRL_QUADMODE_MASK (0x8U)

#define	TPM_QDCTRL_QUADMODE_SHIFT (3U)

#define	TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)

#define	TPM_QDCTRL_QUADEN_MASK (0x1U)

#define	TPM_QDCTRL_QUADEN_SHIFT (0U)

#define	TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)

#define	TPM_QDCTRL_TOFDIR_MASK (0x2U)

#define	TPM_QDCTRL_TOFDIR_SHIFT (1U)

#define	TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)

#define	TPM_QDCTRL_QUADIR_MASK (0x4U)

#define	TPM_QDCTRL_QUADIR_SHIFT (2U)

#define	TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)

#define	TPM_QDCTRL_QUADMODE_MASK (0x8U)

#define	TPM_QDCTRL_QUADMODE_SHIFT (3U)

#define	TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)

CONF - Configuration
#define	TPM_CONF_DOZEEN_MASK (0x20U)

#define	TPM_CONF_DOZEEN_SHIFT (5U)

#define	TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)

#define	TPM_CONF_DBGMODE_MASK (0xC0U)

#define	TPM_CONF_DBGMODE_SHIFT (6U)

#define	TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)

#define	TPM_CONF_GTBSYNC_MASK (0x100U)

#define	TPM_CONF_GTBSYNC_SHIFT (8U)

#define	TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)

#define	TPM_CONF_GTBEEN_MASK (0x200U)

#define	TPM_CONF_GTBEEN_SHIFT (9U)

#define	TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)

#define	TPM_CONF_CSOT_MASK (0x10000U)

#define	TPM_CONF_CSOT_SHIFT (16U)

#define	TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)

#define	TPM_CONF_CSOO_MASK (0x20000U)

#define	TPM_CONF_CSOO_SHIFT (17U)

#define	TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)

#define	TPM_CONF_CROT_MASK (0x40000U)

#define	TPM_CONF_CROT_SHIFT (18U)

#define	TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)

#define	TPM_CONF_CPOT_MASK (0x80000U)

#define	TPM_CONF_CPOT_SHIFT (19U)

#define	TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)

#define	TPM_CONF_TRGPOL_MASK (0x400000U)

#define	TPM_CONF_TRGPOL_SHIFT (22U)

#define	TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)

#define	TPM_CONF_TRGSRC_MASK (0x800000U)

#define	TPM_CONF_TRGSRC_SHIFT (23U)

#define	TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)

#define	TPM_CONF_TRGSEL_MASK (0xF000000U)

#define	TPM_CONF_TRGSEL_SHIFT (24U)

#define	TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)

#define	TPM_CONF_DOZEEN_MASK (0x20U)

#define	TPM_CONF_DOZEEN_SHIFT (5U)

#define	TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)

#define	TPM_CONF_DBGMODE_MASK (0xC0U)

#define	TPM_CONF_DBGMODE_SHIFT (6U)

#define	TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)

#define	TPM_CONF_GTBSYNC_MASK (0x100U)

#define	TPM_CONF_GTBSYNC_SHIFT (8U)

#define	TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)

#define	TPM_CONF_GTBEEN_MASK (0x200U)

#define	TPM_CONF_GTBEEN_SHIFT (9U)

#define	TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)

#define	TPM_CONF_CSOT_MASK (0x10000U)

#define	TPM_CONF_CSOT_SHIFT (16U)

#define	TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)

#define	TPM_CONF_CSOO_MASK (0x20000U)

#define	TPM_CONF_CSOO_SHIFT (17U)

#define	TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)

#define	TPM_CONF_CROT_MASK (0x40000U)

#define	TPM_CONF_CROT_SHIFT (18U)

#define	TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)

#define	TPM_CONF_CPOT_MASK (0x80000U)

#define	TPM_CONF_CPOT_SHIFT (19U)

#define	TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)

#define	TPM_CONF_TRGPOL_MASK (0x400000U)

#define	TPM_CONF_TRGPOL_SHIFT (22U)

#define	TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)

#define	TPM_CONF_TRGSRC_MASK (0x800000U)

#define	TPM_CONF_TRGSRC_SHIFT (23U)

#define	TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)

#define	TPM_CONF_TRGSEL_MASK (0xF000000U)

#define	TPM_CONF_TRGSEL_SHIFT (24U)

#define	TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)

Macro Definition Documentation

◆ TPM_CnSC_CHF [1/2]

#define TPM_CnSC_CHF ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)

CHF - Channel Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ TPM_CnSC_CHF [2/2]

#define TPM_CnSC_CHF ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)

CHF - Channel Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ TPM_CnSC_CHIE [1/2]

#define TPM_CnSC_CHIE ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)

CHIE - Channel Interrupt Enable 0b0..Disable channel interrupts. 0b1..Enable channel interrupts.

◆ TPM_CnSC_CHIE [2/2]

#define TPM_CnSC_CHIE ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)

CHIE - Channel Interrupt Enable 0b0..Disable channel interrupts. 0b1..Enable channel interrupts.

◆ TPM_CnSC_DMA [1/2]

#define TPM_CnSC_DMA ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)

DMA - DMA Enable 0b0..Disable DMA transfers. 0b1..Enable DMA transfers.

◆ TPM_CnSC_DMA [2/2]

#define TPM_CnSC_DMA ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)

DMA - DMA Enable 0b0..Disable DMA transfers. 0b1..Enable DMA transfers.

◆ TPM_COMBINE_COMBINE0 [1/2]

#define TPM_COMBINE_COMBINE0 ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)

COMBINE0 - Combine Channels 0 and 1 0b0..Channels 0 and 1 are independent. 0b1..Channels 0 and 1 are combined.

◆ TPM_COMBINE_COMBINE0 [2/2]

#define TPM_COMBINE_COMBINE0 ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)

COMBINE0 - Combine Channels 0 and 1 0b0..Channels 0 and 1 are independent. 0b1..Channels 0 and 1 are combined.

◆ TPM_COMBINE_COMSWAP0 [1/2]

#define TPM_COMBINE_COMSWAP0 ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)

COMSWAP0 - Combine Channel 0 and 1 Swap 0b0..Even channel is used for input capture and 1st compare. 0b1..Odd channel is used for input capture and 1st compare.

◆ TPM_COMBINE_COMSWAP0 [2/2]

#define TPM_COMBINE_COMSWAP0 ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)

COMSWAP0 - Combine Channel 0 and 1 Swap 0b0..Even channel is used for input capture and 1st compare. 0b1..Odd channel is used for input capture and 1st compare.

◆ TPM_CONF_CROT [1/2]

#define TPM_CONF_CROT ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)

CROT - Counter Reload On Trigger 0b0..Counter is not reloaded due to a rising edge on the selected input trigger 0b1..Counter is reloaded when a rising edge is detected on the selected input trigger

◆ TPM_CONF_CROT [2/2]

#define TPM_CONF_CROT ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)

CROT - Counter Reload On Trigger 0b0..Counter is not reloaded due to a rising edge on the selected input trigger 0b1..Counter is reloaded when a rising edge is detected on the selected input trigger

◆ TPM_CONF_CSOO [1/2]

#define TPM_CONF_CSOO ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)

CSOO - Counter Stop On Overflow 0b0..TPM counter continues incrementing or decrementing after overflow 0b1..TPM counter stops incrementing or decrementing after overflow.

◆ TPM_CONF_CSOO [2/2]

#define TPM_CONF_CSOO ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)

CSOO - Counter Stop On Overflow 0b0..TPM counter continues incrementing or decrementing after overflow 0b1..TPM counter stops incrementing or decrementing after overflow.

◆ TPM_CONF_CSOT [1/2]

#define TPM_CONF_CSOT ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)

CSOT - Counter Start on Trigger 0b0..TPM counter starts to increment immediately, once it is enabled. 0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.

◆ TPM_CONF_CSOT [2/2]

#define TPM_CONF_CSOT ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)

CSOT - Counter Start on Trigger 0b0..TPM counter starts to increment immediately, once it is enabled. 0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.

◆ TPM_CONF_DBGMODE [1/2]

#define TPM_CONF_DBGMODE ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)

DBGMODE - Debug Mode 0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. 0b11..TPM counter continues in debug mode.

◆ TPM_CONF_DBGMODE [2/2]

#define TPM_CONF_DBGMODE ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)

DBGMODE - Debug Mode 0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. 0b11..TPM counter continues in debug mode.

◆ TPM_CONF_DOZEEN [1/2]

#define TPM_CONF_DOZEEN ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)

DOZEEN - Doze Enable 0b0..Internal TPM counter continues in Doze mode. 0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.

◆ TPM_CONF_DOZEEN [2/2]

#define TPM_CONF_DOZEEN ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)

DOZEEN - Doze Enable 0b0..Internal TPM counter continues in Doze mode. 0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.

◆ TPM_CONF_GTBEEN [1/2]

#define TPM_CONF_GTBEEN ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)

GTBEEN - Global time base enable 0b0..All channels use the internally generated TPM counter as their timebase 0b1..All channels use an externally generated global timebase as their timebase

◆ TPM_CONF_GTBEEN [2/2]

#define TPM_CONF_GTBEEN ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)

GTBEEN - Global time base enable 0b0..All channels use the internally generated TPM counter as their timebase 0b1..All channels use an externally generated global timebase as their timebase

◆ TPM_CONF_GTBSYNC [1/2]

#define TPM_CONF_GTBSYNC ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)

GTBSYNC - Global Time Base Synchronization 0b0..Global timebase synchronization disabled. 0b1..Global timebase synchronization enabled.

◆ TPM_CONF_GTBSYNC [2/2]

#define TPM_CONF_GTBSYNC ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)

GTBSYNC - Global Time Base Synchronization 0b0..Global timebase synchronization disabled. 0b1..Global timebase synchronization enabled.

◆ TPM_CONF_TRGPOL [1/2]

#define TPM_CONF_TRGPOL ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)

TRGPOL - Trigger Polarity 0b0..Trigger is active high. 0b1..Trigger is active low.

◆ TPM_CONF_TRGPOL [2/2]

#define TPM_CONF_TRGPOL ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)

TRGPOL - Trigger Polarity 0b0..Trigger is active high. 0b1..Trigger is active low.

◆ TPM_CONF_TRGSEL [1/2]

#define TPM_CONF_TRGSEL ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)

TRGSEL - Trigger Select 0b0001..Channel 0 pin input capture 0b0010..Channel 1 pin input capture 0b0011..Channel 0 or Channel 1 pin input capture

◆ TPM_CONF_TRGSEL [2/2]

#define TPM_CONF_TRGSEL ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)

TRGSEL - Trigger Select 0b0001..Channel 0 pin input capture 0b0010..Channel 1 pin input capture 0b0011..Channel 0 or Channel 1 pin input capture

◆ TPM_CONF_TRGSRC [1/2]

#define TPM_CONF_TRGSRC ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)

TRGSRC - Trigger Source 0b0..Trigger source selected by TRGSEL is external. 0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).

◆ TPM_CONF_TRGSRC [2/2]

#define TPM_CONF_TRGSRC ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)

TRGSRC - Trigger Source 0b0..Trigger source selected by TRGSEL is external. 0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).

◆ TPM_POL_POL0 [1/2]

#define TPM_POL_POL0 ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)

POL0 - Channel 0 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ TPM_POL_POL0 [2/2]

#define TPM_POL_POL0 ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)

POL0 - Channel 0 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ TPM_POL_POL1 [1/2]

#define TPM_POL_POL1 ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)

POL1 - Channel 1 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ TPM_POL_POL1 [2/2]

#define TPM_POL_POL1 ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)

POL1 - Channel 1 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ TPM_QDCTRL_QUADEN [1/2]

#define TPM_QDCTRL_QUADEN ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)

QUADEN 0b0..Quadrature decoder mode is disabled. 0b1..Quadrature decoder mode is enabled.

◆ TPM_QDCTRL_QUADEN [2/2]

#define TPM_QDCTRL_QUADEN ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)

QUADEN 0b0..Quadrature decoder mode is disabled. 0b1..Quadrature decoder mode is enabled.

◆ TPM_QDCTRL_QUADIR [1/2]

#define TPM_QDCTRL_QUADIR ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)

QUADIR - Counter Direction in Quadrature Decode Mode 0b0..Counter direction is decreasing (counter decrement). 0b1..Counter direction is increasing (counter increment).

◆ TPM_QDCTRL_QUADIR [2/2]

#define TPM_QDCTRL_QUADIR ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)

QUADIR - Counter Direction in Quadrature Decode Mode 0b0..Counter direction is decreasing (counter decrement). 0b1..Counter direction is increasing (counter increment).

◆ TPM_QDCTRL_QUADMODE [1/2]

#define TPM_QDCTRL_QUADMODE ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)

QUADMODE - Quadrature Decoder Mode 0b0..Phase encoding mode. 0b1..Count and direction encoding mode.

◆ TPM_QDCTRL_QUADMODE [2/2]

#define TPM_QDCTRL_QUADMODE ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)

QUADMODE - Quadrature Decoder Mode 0b0..Phase encoding mode. 0b1..Count and direction encoding mode.

◆ TPM_QDCTRL_TOFDIR [1/2]

#define TPM_QDCTRL_TOFDIR ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)

TOFDIR 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero).

◆ TPM_QDCTRL_TOFDIR [2/2]

#define TPM_QDCTRL_TOFDIR ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)

TOFDIR 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero).

◆ TPM_SC_CMOD [1/2]

#define TPM_SC_CMOD ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)

CMOD - Clock Mode Selection 0b00..TPM counter is disabled 0b01..TPM counter increments on every TPM counter clock 0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock 0b11..Reserved.

◆ TPM_SC_CMOD [2/2]

#define TPM_SC_CMOD ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)

CMOD - Clock Mode Selection 0b00..TPM counter is disabled 0b01..TPM counter increments on every TPM counter clock 0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock 0b11..Reserved.

◆ TPM_SC_CPWMS [1/2]

#define TPM_SC_CPWMS ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)

CPWMS - Center-Aligned PWM Select 0b0..TPM counter operates in up counting mode. 0b1..TPM counter operates in up-down counting mode.

◆ TPM_SC_CPWMS [2/2]

#define TPM_SC_CPWMS ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)

CPWMS - Center-Aligned PWM Select 0b0..TPM counter operates in up counting mode. 0b1..TPM counter operates in up-down counting mode.

◆ TPM_SC_DMA [1/2]

#define TPM_SC_DMA ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)

DMA - DMA Enable 0b0..Disables DMA transfers. 0b1..Enables DMA transfers.

◆ TPM_SC_DMA [2/2]

#define TPM_SC_DMA ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)

DMA - DMA Enable 0b0..Disables DMA transfers. 0b1..Enables DMA transfers.

◆ TPM_SC_PS [1/2]

#define TPM_SC_PS ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)

PS - Prescale Factor Selection 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ TPM_SC_PS [2/2]

#define TPM_SC_PS ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)

PS - Prescale Factor Selection 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ TPM_SC_TOF [1/2]

#define TPM_SC_TOF ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)

TOF - Timer Overflow Flag 0b0..TPM counter has not overflowed. 0b1..TPM counter has overflowed.

◆ TPM_SC_TOF [2/2]

#define TPM_SC_TOF ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)

TOF - Timer Overflow Flag 0b0..TPM counter has not overflowed. 0b1..TPM counter has overflowed.

◆ TPM_SC_TOIE [1/2]

#define TPM_SC_TOIE ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)

TOIE - Timer Overflow Interrupt Enable 0b0..Disable TOF interrupts. Use software polling or DMA request. 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.

◆ TPM_SC_TOIE [2/2]

#define TPM_SC_TOIE ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)

TOIE - Timer Overflow Interrupt Enable 0b0..Disable TOF interrupts. Use software polling or DMA request. 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.

◆ TPM_STATUS_CH0F [1/2]

#define TPM_STATUS_CH0F ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)

CH0F - Channel 0 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ TPM_STATUS_CH0F [2/2]

#define TPM_STATUS_CH0F ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)

CH0F - Channel 0 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ TPM_STATUS_CH1F [1/2]

#define TPM_STATUS_CH1F ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)

CH1F - Channel 1 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ TPM_STATUS_CH1F [2/2]

#define TPM_STATUS_CH1F ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)

CH1F - Channel 1 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ TPM_STATUS_TOF [1/2]

#define TPM_STATUS_TOF ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)

TOF - Timer Overflow Flag 0b0..TPM counter has not overflowed. 0b1..TPM counter has overflowed.

◆ TPM_STATUS_TOF [2/2]

#define TPM_STATUS_TOF ( x ) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)

TOF - Timer Overflow Flag 0b0..TPM counter has not overflowed. 0b1..TPM counter has overflowed.

Macros

SC - Status And Control

CNT - Counter

MOD - Modulo

CnSC - Channel (n) Status And Control

CnV - Channel (n) Value

STATUS - Capture And Compare Status

COMBINE - Combine Channel Register

POL - Channel Polarity

FILTER - Filter Control

QDCTRL - Quadrature Decoder Control And Status

CONF - Configuration

Macro Definition Documentation

◆ TPM_CnSC_CHF [1/2]

◆ TPM_CnSC_CHF [2/2]

◆ TPM_CnSC_CHIE [1/2]

◆ TPM_CnSC_CHIE [2/2]

◆ TPM_CnSC_DMA [1/2]

◆ TPM_CnSC_DMA [2/2]

◆ TPM_COMBINE_COMBINE0 [1/2]

◆ TPM_COMBINE_COMBINE0 [2/2]

◆ TPM_COMBINE_COMSWAP0 [1/2]

◆ TPM_COMBINE_COMSWAP0 [2/2]

◆ TPM_CONF_CROT [1/2]

◆ TPM_CONF_CROT [2/2]

◆ TPM_CONF_CSOO [1/2]

◆ TPM_CONF_CSOO [2/2]

◆ TPM_CONF_CSOT [1/2]

◆ TPM_CONF_CSOT [2/2]

◆ TPM_CONF_DBGMODE [1/2]

◆ TPM_CONF_DBGMODE [2/2]

◆ TPM_CONF_DOZEEN [1/2]

◆ TPM_CONF_DOZEEN [2/2]

◆ TPM_CONF_GTBEEN [1/2]

◆ TPM_CONF_GTBEEN [2/2]

◆ TPM_CONF_GTBSYNC [1/2]

◆ TPM_CONF_GTBSYNC [2/2]

◆ TPM_CONF_TRGPOL [1/2]

◆ TPM_CONF_TRGPOL [2/2]

◆ TPM_CONF_TRGSEL [1/2]

◆ TPM_CONF_TRGSEL [2/2]

◆ TPM_CONF_TRGSRC [1/2]

◆ TPM_CONF_TRGSRC [2/2]

◆ TPM_POL_POL0 [1/2]

◆ TPM_POL_POL0 [2/2]

◆ TPM_POL_POL1 [1/2]

◆ TPM_POL_POL1 [2/2]

◆ TPM_QDCTRL_QUADEN [1/2]

◆ TPM_QDCTRL_QUADEN [2/2]

◆ TPM_QDCTRL_QUADIR [1/2]

◆ TPM_QDCTRL_QUADIR [2/2]

◆ TPM_QDCTRL_QUADMODE [1/2]

◆ TPM_QDCTRL_QUADMODE [2/2]

◆ TPM_QDCTRL_TOFDIR [1/2]

◆ TPM_QDCTRL_TOFDIR [2/2]

◆ TPM_SC_CMOD [1/2]

◆ TPM_SC_CMOD [2/2]

◆ TPM_SC_CPWMS [1/2]

◆ TPM_SC_CPWMS [2/2]

◆ TPM_SC_DMA [1/2]

◆ TPM_SC_DMA [2/2]

◆ TPM_SC_PS [1/2]

◆ TPM_SC_PS [2/2]

◆ TPM_SC_TOF [1/2]

◆ TPM_SC_TOF [2/2]

◆ TPM_SC_TOIE [1/2]

◆ TPM_SC_TOIE [2/2]

◆ TPM_STATUS_CH0F [1/2]

◆ TPM_STATUS_CH0F [2/2]

◆ TPM_STATUS_CH1F [1/2]

◆ TPM_STATUS_CH1F [2/2]

◆ TPM_STATUS_TOF [1/2]

◆ TPM_STATUS_TOF [2/2]