USBHS Register Masks

Macros
#define	USBHS_EPCR_COUNT   (7U)
#define	USBHS_EPCR_COUNT   (7U)

ID - Identification Register
#define	USBHS_ID_ID_MASK   (0x3FU)
#define	USBHS_ID_ID_SHIFT   (0U)
#define	USBHS_ID_ID(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
#define	USBHS_ID_NID_MASK   (0x3F00U)
#define	USBHS_ID_NID_SHIFT   (8U)
#define	USBHS_ID_NID(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
#define	USBHS_ID_TAG_MASK   (0x1F0000U)
#define	USBHS_ID_TAG_SHIFT   (16U)
#define	USBHS_ID_TAG(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_TAG_SHIFT)) & USBHS_ID_TAG_MASK)
#define	USBHS_ID_REVISION_MASK   (0x1E00000U)
#define	USBHS_ID_REVISION_SHIFT   (21U)
#define	USBHS_ID_REVISION(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
#define	USBHS_ID_VERSION_MASK   (0x1E000000U)
#define	USBHS_ID_VERSION_SHIFT   (25U)
#define	USBHS_ID_VERSION(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSION_SHIFT)) & USBHS_ID_VERSION_MASK)
#define	USBHS_ID_VERSIONID_MASK   (0xE0000000U)
#define	USBHS_ID_VERSIONID_SHIFT   (29U)
#define	USBHS_ID_VERSIONID(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSIONID_SHIFT)) & USBHS_ID_VERSIONID_MASK)
#define	USBHS_ID_ID_MASK   (0x3FU)
#define	USBHS_ID_ID_SHIFT   (0U)
#define	USBHS_ID_ID(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
#define	USBHS_ID_NID_MASK   (0x3F00U)
#define	USBHS_ID_NID_SHIFT   (8U)
#define	USBHS_ID_NID(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
#define	USBHS_ID_TAG_MASK   (0x1F0000U)
#define	USBHS_ID_TAG_SHIFT   (16U)
#define	USBHS_ID_TAG(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_TAG_SHIFT)) & USBHS_ID_TAG_MASK)
#define	USBHS_ID_REVISION_MASK   (0x1E00000U)
#define	USBHS_ID_REVISION_SHIFT   (21U)
#define	USBHS_ID_REVISION(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
#define	USBHS_ID_VERSION_MASK   (0x1E000000U)
#define	USBHS_ID_VERSION_SHIFT   (25U)
#define	USBHS_ID_VERSION(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSION_SHIFT)) & USBHS_ID_VERSION_MASK)
#define	USBHS_ID_VERSIONID_MASK   (0xE0000000U)
#define	USBHS_ID_VERSIONID_SHIFT   (29U)
#define	USBHS_ID_VERSIONID(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSIONID_SHIFT)) & USBHS_ID_VERSIONID_MASK)

HWGENERAL - General Hardware Parameters Register
#define	USBHS_HWGENERAL_PHYW_MASK   (0x30U)
#define	USBHS_HWGENERAL_PHYW_SHIFT   (4U)
#define	USBHS_HWGENERAL_PHYW(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
#define	USBHS_HWGENERAL_PHYM_MASK   (0x1C0U)
#define	USBHS_HWGENERAL_PHYM_SHIFT   (6U)
#define	USBHS_HWGENERAL_PHYM(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
#define	USBHS_HWGENERAL_SM_MASK   (0x600U)
#define	USBHS_HWGENERAL_SM_SHIFT   (9U)
#define	USBHS_HWGENERAL_SM(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)
#define	USBHS_HWGENERAL_PHYW_MASK   (0x30U)
#define	USBHS_HWGENERAL_PHYW_SHIFT   (4U)
#define	USBHS_HWGENERAL_PHYW(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
#define	USBHS_HWGENERAL_PHYM_MASK   (0x1C0U)
#define	USBHS_HWGENERAL_PHYM_SHIFT   (6U)
#define	USBHS_HWGENERAL_PHYM(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
#define	USBHS_HWGENERAL_SM_MASK   (0x600U)
#define	USBHS_HWGENERAL_SM_SHIFT   (9U)
#define	USBHS_HWGENERAL_SM(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)

HWHOST - Host Hardware Parameters Register
#define	USBHS_HWHOST_HC_MASK   (0x1U)
#define	USBHS_HWHOST_HC_SHIFT   (0U)
#define	USBHS_HWHOST_HC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
#define	USBHS_HWHOST_NPORT_MASK   (0xEU)
#define	USBHS_HWHOST_NPORT_SHIFT   (1U)
#define	USBHS_HWHOST_NPORT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
#define	USBHS_HWHOST_TTASY_MASK   (0xFF0000U)
#define	USBHS_HWHOST_TTASY_SHIFT   (16U)
#define	USBHS_HWHOST_TTASY(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTASY_SHIFT)) & USBHS_HWHOST_TTASY_MASK)
#define	USBHS_HWHOST_TTPER_MASK   (0xFF000000U)
#define	USBHS_HWHOST_TTPER_SHIFT   (24U)
#define	USBHS_HWHOST_TTPER(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTPER_SHIFT)) & USBHS_HWHOST_TTPER_MASK)
#define	USBHS_HWHOST_HC_MASK   (0x1U)
#define	USBHS_HWHOST_HC_SHIFT   (0U)
#define	USBHS_HWHOST_HC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
#define	USBHS_HWHOST_NPORT_MASK   (0xEU)
#define	USBHS_HWHOST_NPORT_SHIFT   (1U)
#define	USBHS_HWHOST_NPORT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
#define	USBHS_HWHOST_TTASY_MASK   (0xFF0000U)
#define	USBHS_HWHOST_TTASY_SHIFT   (16U)
#define	USBHS_HWHOST_TTASY(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTASY_SHIFT)) & USBHS_HWHOST_TTASY_MASK)
#define	USBHS_HWHOST_TTPER_MASK   (0xFF000000U)
#define	USBHS_HWHOST_TTPER_SHIFT   (24U)
#define	USBHS_HWHOST_TTPER(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTPER_SHIFT)) & USBHS_HWHOST_TTPER_MASK)

HWDEVICE - Device Hardware Parameters Register
#define	USBHS_HWDEVICE_DC_MASK   (0x1U)
#define	USBHS_HWDEVICE_DC_SHIFT   (0U)
#define	USBHS_HWDEVICE_DC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
#define	USBHS_HWDEVICE_DEVEP_MASK   (0x3EU)
#define	USBHS_HWDEVICE_DEVEP_SHIFT   (1U)
#define	USBHS_HWDEVICE_DEVEP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)
#define	USBHS_HWDEVICE_DC_MASK   (0x1U)
#define	USBHS_HWDEVICE_DC_SHIFT   (0U)
#define	USBHS_HWDEVICE_DC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
#define	USBHS_HWDEVICE_DEVEP_MASK   (0x3EU)
#define	USBHS_HWDEVICE_DEVEP_SHIFT   (1U)
#define	USBHS_HWDEVICE_DEVEP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)

HWTXBUF - Transmit Buffer Hardware Parameters Register
#define	USBHS_HWTXBUF_TXBURST_MASK   (0xFFU)
#define	USBHS_HWTXBUF_TXBURST_SHIFT   (0U)
#define	USBHS_HWTXBUF_TXBURST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
#define	USBHS_HWTXBUF_TXADD_MASK   (0xFF00U)
#define	USBHS_HWTXBUF_TXADD_SHIFT   (8U)
#define	USBHS_HWTXBUF_TXADD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXADD_SHIFT)) & USBHS_HWTXBUF_TXADD_MASK)
#define	USBHS_HWTXBUF_TXCHANADD_MASK   (0xFF0000U)
#define	USBHS_HWTXBUF_TXCHANADD_SHIFT   (16U)
#define	USBHS_HWTXBUF_TXCHANADD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
#define	USBHS_HWTXBUF_TXLC_MASK   (0x80000000U)
#define	USBHS_HWTXBUF_TXLC_SHIFT   (31U)
#define	USBHS_HWTXBUF_TXLC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)
#define	USBHS_HWTXBUF_TXBURST_MASK   (0xFFU)
#define	USBHS_HWTXBUF_TXBURST_SHIFT   (0U)
#define	USBHS_HWTXBUF_TXBURST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
#define	USBHS_HWTXBUF_TXADD_MASK   (0xFF00U)
#define	USBHS_HWTXBUF_TXADD_SHIFT   (8U)
#define	USBHS_HWTXBUF_TXADD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXADD_SHIFT)) & USBHS_HWTXBUF_TXADD_MASK)
#define	USBHS_HWTXBUF_TXCHANADD_MASK   (0xFF0000U)
#define	USBHS_HWTXBUF_TXCHANADD_SHIFT   (16U)
#define	USBHS_HWTXBUF_TXCHANADD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
#define	USBHS_HWTXBUF_TXLC_MASK   (0x80000000U)
#define	USBHS_HWTXBUF_TXLC_SHIFT   (31U)
#define	USBHS_HWTXBUF_TXLC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)

HWRXBUF - Receive Buffer Hardware Parameters Register
#define	USBHS_HWRXBUF_RXBURST_MASK   (0xFFU)
#define	USBHS_HWRXBUF_RXBURST_SHIFT   (0U)
#define	USBHS_HWRXBUF_RXBURST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
#define	USBHS_HWRXBUF_RXADD_MASK   (0xFF00U)
#define	USBHS_HWRXBUF_RXADD_SHIFT   (8U)
#define	USBHS_HWRXBUF_RXADD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)
#define	USBHS_HWRXBUF_RXBURST_MASK   (0xFFU)
#define	USBHS_HWRXBUF_RXBURST_SHIFT   (0U)
#define	USBHS_HWRXBUF_RXBURST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
#define	USBHS_HWRXBUF_RXADD_MASK   (0xFF00U)
#define	USBHS_HWRXBUF_RXADD_SHIFT   (8U)
#define	USBHS_HWRXBUF_RXADD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)

GPTIMER0LD - General Purpose Timer n Load Register
#define	USBHS_GPTIMER0LD_GPTLD_MASK   (0xFFFFFFU)
#define	USBHS_GPTIMER0LD_GPTLD_SHIFT   (0U)
#define	USBHS_GPTIMER0LD_GPTLD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)
#define	USBHS_GPTIMER0LD_GPTLD_MASK   (0xFFFFFFU)
#define	USBHS_GPTIMER0LD_GPTLD_SHIFT   (0U)
#define	USBHS_GPTIMER0LD_GPTLD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)

GPTIMER0CTL - General Purpose Timer n Control Register
#define	USBHS_GPTIMER0CTL_GPTCNT_MASK   (0xFFFFFFU)
#define	USBHS_GPTIMER0CTL_GPTCNT_SHIFT   (0U)
#define	USBHS_GPTIMER0CTL_GPTCNT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTL_GPTCNT_MASK)
#define	USBHS_GPTIMER0CTL_MODE_MASK   (0x1000000U)
#define	USBHS_GPTIMER0CTL_MODE_SHIFT   (24U)
#define	USBHS_GPTIMER0CTL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)
#define	USBHS_GPTIMER0CTL_RST_MASK   (0x40000000U)
#define	USBHS_GPTIMER0CTL_RST_SHIFT   (30U)
#define	USBHS_GPTIMER0CTL_RST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)
#define	USBHS_GPTIMER0CTL_RUN_MASK   (0x80000000U)
#define	USBHS_GPTIMER0CTL_RUN_SHIFT   (31U)
#define	USBHS_GPTIMER0CTL_RUN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)
#define	USBHS_GPTIMER0CTL_GPTCNT_MASK   (0xFFFFFFU)
#define	USBHS_GPTIMER0CTL_GPTCNT_SHIFT   (0U)
#define	USBHS_GPTIMER0CTL_GPTCNT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTL_GPTCNT_MASK)
#define	USBHS_GPTIMER0CTL_MODE_MASK   (0x1000000U)
#define	USBHS_GPTIMER0CTL_MODE_SHIFT   (24U)
#define	USBHS_GPTIMER0CTL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)
#define	USBHS_GPTIMER0CTL_RST_MASK   (0x40000000U)
#define	USBHS_GPTIMER0CTL_RST_SHIFT   (30U)
#define	USBHS_GPTIMER0CTL_RST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)
#define	USBHS_GPTIMER0CTL_RUN_MASK   (0x80000000U)
#define	USBHS_GPTIMER0CTL_RUN_SHIFT   (31U)
#define	USBHS_GPTIMER0CTL_RUN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)

GPTIMER1LD - General Purpose Timer n Load Register
#define	USBHS_GPTIMER1LD_GPTLD_MASK   (0xFFFFFFU)
#define	USBHS_GPTIMER1LD_GPTLD_SHIFT   (0U)
#define	USBHS_GPTIMER1LD_GPTLD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)
#define	USBHS_GPTIMER1LD_GPTLD_MASK   (0xFFFFFFU)
#define	USBHS_GPTIMER1LD_GPTLD_SHIFT   (0U)
#define	USBHS_GPTIMER1LD_GPTLD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)

GPTIMER1CTL - General Purpose Timer n Control Register
#define	USBHS_GPTIMER1CTL_GPTCNT_MASK   (0xFFFFFFU)
#define	USBHS_GPTIMER1CTL_GPTCNT_SHIFT   (0U)
#define	USBHS_GPTIMER1CTL_GPTCNT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTL_GPTCNT_MASK)
#define	USBHS_GPTIMER1CTL_MODE_MASK   (0x1000000U)
#define	USBHS_GPTIMER1CTL_MODE_SHIFT   (24U)
#define	USBHS_GPTIMER1CTL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)
#define	USBHS_GPTIMER1CTL_RST_MASK   (0x40000000U)
#define	USBHS_GPTIMER1CTL_RST_SHIFT   (30U)
#define	USBHS_GPTIMER1CTL_RST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)
#define	USBHS_GPTIMER1CTL_RUN_MASK   (0x80000000U)
#define	USBHS_GPTIMER1CTL_RUN_SHIFT   (31U)
#define	USBHS_GPTIMER1CTL_RUN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)
#define	USBHS_GPTIMER1CTL_GPTCNT_MASK   (0xFFFFFFU)
#define	USBHS_GPTIMER1CTL_GPTCNT_SHIFT   (0U)
#define	USBHS_GPTIMER1CTL_GPTCNT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTL_GPTCNT_MASK)
#define	USBHS_GPTIMER1CTL_MODE_MASK   (0x1000000U)
#define	USBHS_GPTIMER1CTL_MODE_SHIFT   (24U)
#define	USBHS_GPTIMER1CTL_MODE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)
#define	USBHS_GPTIMER1CTL_RST_MASK   (0x40000000U)
#define	USBHS_GPTIMER1CTL_RST_SHIFT   (30U)
#define	USBHS_GPTIMER1CTL_RST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)
#define	USBHS_GPTIMER1CTL_RUN_MASK   (0x80000000U)
#define	USBHS_GPTIMER1CTL_RUN_SHIFT   (31U)
#define	USBHS_GPTIMER1CTL_RUN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)

USB_SBUSCFG - System Bus Interface Configuration Register
#define	USBHS_USB_SBUSCFG_BURSTMODE_MASK   (0x7U)
#define	USBHS_USB_SBUSCFG_BURSTMODE_SHIFT   (0U)
#define	USBHS_USB_SBUSCFG_BURSTMODE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USB_SBUSCFG_BURSTMODE_MASK)
#define	USBHS_USB_SBUSCFG_BURSTMODE_MASK   (0x7U)
#define	USBHS_USB_SBUSCFG_BURSTMODE_SHIFT   (0U)
#define	USBHS_USB_SBUSCFG_BURSTMODE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USB_SBUSCFG_BURSTMODE_MASK)

HCIVERSION - Host Controller Interface Version and Capability Registers Length Register
#define	USBHS_HCIVERSION_CAPLENGTH_MASK   (0xFFU)
#define	USBHS_HCIVERSION_CAPLENGTH_SHIFT   (0U)
#define	USBHS_HCIVERSION_CAPLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_CAPLENGTH_SHIFT)) & USBHS_HCIVERSION_CAPLENGTH_MASK)
#define	USBHS_HCIVERSION_HCIVERSION_MASK   (0xFFFF0000U)
#define	USBHS_HCIVERSION_HCIVERSION_SHIFT   (16U)
#define	USBHS_HCIVERSION_HCIVERSION(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)
#define	USBHS_HCIVERSION_CAPLENGTH_MASK   (0xFFU)
#define	USBHS_HCIVERSION_CAPLENGTH_SHIFT   (0U)
#define	USBHS_HCIVERSION_CAPLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_CAPLENGTH_SHIFT)) & USBHS_HCIVERSION_CAPLENGTH_MASK)
#define	USBHS_HCIVERSION_HCIVERSION_MASK   (0xFFFF0000U)
#define	USBHS_HCIVERSION_HCIVERSION_SHIFT   (16U)
#define	USBHS_HCIVERSION_HCIVERSION(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)

HCSPARAMS - Host Controller Structural Parameters Register
#define	USBHS_HCSPARAMS_N_PORTS_MASK   (0xFU)
#define	USBHS_HCSPARAMS_N_PORTS_SHIFT   (0U)
#define	USBHS_HCSPARAMS_N_PORTS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
#define	USBHS_HCSPARAMS_PPC_MASK   (0x10U)
#define	USBHS_HCSPARAMS_PPC_SHIFT   (4U)
#define	USBHS_HCSPARAMS_PPC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
#define	USBHS_HCSPARAMS_N_PCC_MASK   (0xF00U)
#define	USBHS_HCSPARAMS_N_PCC_SHIFT   (8U)
#define	USBHS_HCSPARAMS_N_PCC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
#define	USBHS_HCSPARAMS_N_CC_MASK   (0xF000U)
#define	USBHS_HCSPARAMS_N_CC_SHIFT   (12U)
#define	USBHS_HCSPARAMS_N_CC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
#define	USBHS_HCSPARAMS_PI_MASK   (0x10000U)
#define	USBHS_HCSPARAMS_PI_SHIFT   (16U)
#define	USBHS_HCSPARAMS_PI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
#define	USBHS_HCSPARAMS_N_PTT_MASK   (0xF00000U)
#define	USBHS_HCSPARAMS_N_PTT_SHIFT   (20U)
#define	USBHS_HCSPARAMS_N_PTT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
#define	USBHS_HCSPARAMS_N_TT_MASK   (0xF000000U)
#define	USBHS_HCSPARAMS_N_TT_SHIFT   (24U)
#define	USBHS_HCSPARAMS_N_TT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)
#define	USBHS_HCSPARAMS_N_PORTS_MASK   (0xFU)
#define	USBHS_HCSPARAMS_N_PORTS_SHIFT   (0U)
#define	USBHS_HCSPARAMS_N_PORTS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
#define	USBHS_HCSPARAMS_PPC_MASK   (0x10U)
#define	USBHS_HCSPARAMS_PPC_SHIFT   (4U)
#define	USBHS_HCSPARAMS_PPC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
#define	USBHS_HCSPARAMS_N_PCC_MASK   (0xF00U)
#define	USBHS_HCSPARAMS_N_PCC_SHIFT   (8U)
#define	USBHS_HCSPARAMS_N_PCC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
#define	USBHS_HCSPARAMS_N_CC_MASK   (0xF000U)
#define	USBHS_HCSPARAMS_N_CC_SHIFT   (12U)
#define	USBHS_HCSPARAMS_N_CC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
#define	USBHS_HCSPARAMS_PI_MASK   (0x10000U)
#define	USBHS_HCSPARAMS_PI_SHIFT   (16U)
#define	USBHS_HCSPARAMS_PI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
#define	USBHS_HCSPARAMS_N_PTT_MASK   (0xF00000U)
#define	USBHS_HCSPARAMS_N_PTT_SHIFT   (20U)
#define	USBHS_HCSPARAMS_N_PTT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
#define	USBHS_HCSPARAMS_N_TT_MASK   (0xF000000U)
#define	USBHS_HCSPARAMS_N_TT_SHIFT   (24U)
#define	USBHS_HCSPARAMS_N_TT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)

HCCPARAMS - Host Controller Capability Parameters Register
#define	USBHS_HCCPARAMS_ADC_MASK   (0x1U)
#define	USBHS_HCCPARAMS_ADC_SHIFT   (0U)
#define	USBHS_HCCPARAMS_ADC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK)
#define	USBHS_HCCPARAMS_PFL_MASK   (0x2U)
#define	USBHS_HCCPARAMS_PFL_SHIFT   (1U)
#define	USBHS_HCCPARAMS_PFL(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
#define	USBHS_HCCPARAMS_ASP_MASK   (0x4U)
#define	USBHS_HCCPARAMS_ASP_SHIFT   (2U)
#define	USBHS_HCCPARAMS_ASP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
#define	USBHS_HCCPARAMS_IST_MASK   (0xF0U)
#define	USBHS_HCCPARAMS_IST_SHIFT   (4U)
#define	USBHS_HCCPARAMS_IST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
#define	USBHS_HCCPARAMS_EECP_MASK   (0xFF00U)
#define	USBHS_HCCPARAMS_EECP_SHIFT   (8U)
#define	USBHS_HCCPARAMS_EECP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)
#define	USBHS_HCCPARAMS_ADC_MASK   (0x1U)
#define	USBHS_HCCPARAMS_ADC_SHIFT   (0U)
#define	USBHS_HCCPARAMS_ADC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK)
#define	USBHS_HCCPARAMS_PFL_MASK   (0x2U)
#define	USBHS_HCCPARAMS_PFL_SHIFT   (1U)
#define	USBHS_HCCPARAMS_PFL(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
#define	USBHS_HCCPARAMS_ASP_MASK   (0x4U)
#define	USBHS_HCCPARAMS_ASP_SHIFT   (2U)
#define	USBHS_HCCPARAMS_ASP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
#define	USBHS_HCCPARAMS_IST_MASK   (0xF0U)
#define	USBHS_HCCPARAMS_IST_SHIFT   (4U)
#define	USBHS_HCCPARAMS_IST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
#define	USBHS_HCCPARAMS_EECP_MASK   (0xFF00U)
#define	USBHS_HCCPARAMS_EECP_SHIFT   (8U)
#define	USBHS_HCCPARAMS_EECP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)

DCIVERSION - Device Controller Interface Version
#define	USBHS_DCIVERSION_DCIVERSION_MASK   (0xFFFFU)
#define	USBHS_DCIVERSION_DCIVERSION_SHIFT   (0U)
#define	USBHS_DCIVERSION_DCIVERSION(x)   (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)
#define	USBHS_DCIVERSION_DCIVERSION_MASK   (0xFFFFU)
#define	USBHS_DCIVERSION_DCIVERSION_SHIFT   (0U)
#define	USBHS_DCIVERSION_DCIVERSION(x)   (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)

DCCPARAMS - Device Controller Capability Parameters
#define	USBHS_DCCPARAMS_DEN_MASK   (0x1FU)
#define	USBHS_DCCPARAMS_DEN_SHIFT   (0U)
#define	USBHS_DCCPARAMS_DEN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
#define	USBHS_DCCPARAMS_DC_MASK   (0x80U)
#define	USBHS_DCCPARAMS_DC_SHIFT   (7U)
#define	USBHS_DCCPARAMS_DC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
#define	USBHS_DCCPARAMS_HC_MASK   (0x100U)
#define	USBHS_DCCPARAMS_HC_SHIFT   (8U)
#define	USBHS_DCCPARAMS_HC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)
#define	USBHS_DCCPARAMS_DEN_MASK   (0x1FU)
#define	USBHS_DCCPARAMS_DEN_SHIFT   (0U)
#define	USBHS_DCCPARAMS_DEN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
#define	USBHS_DCCPARAMS_DC_MASK   (0x80U)
#define	USBHS_DCCPARAMS_DC_SHIFT   (7U)
#define	USBHS_DCCPARAMS_DC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
#define	USBHS_DCCPARAMS_HC_MASK   (0x100U)
#define	USBHS_DCCPARAMS_HC_SHIFT   (8U)
#define	USBHS_DCCPARAMS_HC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)

USBCMD - USB Command Register
#define	USBHS_USBCMD_RS_MASK   (0x1U)
#define	USBHS_USBCMD_RS_SHIFT   (0U)
#define	USBHS_USBCMD_RS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
#define	USBHS_USBCMD_RST_MASK   (0x2U)
#define	USBHS_USBCMD_RST_SHIFT   (1U)
#define	USBHS_USBCMD_RST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
#define	USBHS_USBCMD_FS_MASK   (0xCU)
#define	USBHS_USBCMD_FS_SHIFT   (2U)
#define	USBHS_USBCMD_FS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)
#define	USBHS_USBCMD_PSE_MASK   (0x10U)
#define	USBHS_USBCMD_PSE_SHIFT   (4U)
#define	USBHS_USBCMD_PSE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
#define	USBHS_USBCMD_ASE_MASK   (0x20U)
#define	USBHS_USBCMD_ASE_SHIFT   (5U)
#define	USBHS_USBCMD_ASE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
#define	USBHS_USBCMD_IAA_MASK   (0x40U)
#define	USBHS_USBCMD_IAA_SHIFT   (6U)
#define	USBHS_USBCMD_IAA(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
#define	USBHS_USBCMD_ASP_MASK   (0x300U)
#define	USBHS_USBCMD_ASP_SHIFT   (8U)
#define	USBHS_USBCMD_ASP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
#define	USBHS_USBCMD_ASPE_MASK   (0x800U)
#define	USBHS_USBCMD_ASPE_SHIFT   (11U)
#define	USBHS_USBCMD_ASPE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
#define	USBHS_USBCMD_SUTW_MASK   (0x2000U)
#define	USBHS_USBCMD_SUTW_SHIFT   (13U)
#define	USBHS_USBCMD_SUTW(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
#define	USBHS_USBCMD_ATDTW_MASK   (0x4000U)
#define	USBHS_USBCMD_ATDTW_SHIFT   (14U)
#define	USBHS_USBCMD_ATDTW(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
#define	USBHS_USBCMD_FS2_MASK   (0x8000U)
#define	USBHS_USBCMD_FS2_SHIFT   (15U)
#define	USBHS_USBCMD_FS2(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS2_SHIFT)) & USBHS_USBCMD_FS2_MASK)
#define	USBHS_USBCMD_ITC_MASK   (0xFF0000U)
#define	USBHS_USBCMD_ITC_SHIFT   (16U)
#define	USBHS_USBCMD_ITC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)
#define	USBHS_USBCMD_RS_MASK   (0x1U)
#define	USBHS_USBCMD_RS_SHIFT   (0U)
#define	USBHS_USBCMD_RS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
#define	USBHS_USBCMD_RST_MASK   (0x2U)
#define	USBHS_USBCMD_RST_SHIFT   (1U)
#define	USBHS_USBCMD_RST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
#define	USBHS_USBCMD_FS_MASK   (0xCU)
#define	USBHS_USBCMD_FS_SHIFT   (2U)
#define	USBHS_USBCMD_FS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)
#define	USBHS_USBCMD_PSE_MASK   (0x10U)
#define	USBHS_USBCMD_PSE_SHIFT   (4U)
#define	USBHS_USBCMD_PSE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
#define	USBHS_USBCMD_ASE_MASK   (0x20U)
#define	USBHS_USBCMD_ASE_SHIFT   (5U)
#define	USBHS_USBCMD_ASE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
#define	USBHS_USBCMD_IAA_MASK   (0x40U)
#define	USBHS_USBCMD_IAA_SHIFT   (6U)
#define	USBHS_USBCMD_IAA(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
#define	USBHS_USBCMD_ASP_MASK   (0x300U)
#define	USBHS_USBCMD_ASP_SHIFT   (8U)
#define	USBHS_USBCMD_ASP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
#define	USBHS_USBCMD_ASPE_MASK   (0x800U)
#define	USBHS_USBCMD_ASPE_SHIFT   (11U)
#define	USBHS_USBCMD_ASPE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
#define	USBHS_USBCMD_SUTW_MASK   (0x2000U)
#define	USBHS_USBCMD_SUTW_SHIFT   (13U)
#define	USBHS_USBCMD_SUTW(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
#define	USBHS_USBCMD_ATDTW_MASK   (0x4000U)
#define	USBHS_USBCMD_ATDTW_SHIFT   (14U)
#define	USBHS_USBCMD_ATDTW(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
#define	USBHS_USBCMD_FS2_MASK   (0x8000U)
#define	USBHS_USBCMD_FS2_SHIFT   (15U)
#define	USBHS_USBCMD_FS2(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS2_SHIFT)) & USBHS_USBCMD_FS2_MASK)
#define	USBHS_USBCMD_ITC_MASK   (0xFF0000U)
#define	USBHS_USBCMD_ITC_SHIFT   (16U)
#define	USBHS_USBCMD_ITC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)

USBSTS - USB Status Register
#define	USBHS_USBSTS_UI_MASK   (0x1U)
#define	USBHS_USBSTS_UI_SHIFT   (0U)
#define	USBHS_USBSTS_UI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
#define	USBHS_USBSTS_UEI_MASK   (0x2U)
#define	USBHS_USBSTS_UEI_SHIFT   (1U)
#define	USBHS_USBSTS_UEI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
#define	USBHS_USBSTS_PCI_MASK   (0x4U)
#define	USBHS_USBSTS_PCI_SHIFT   (2U)
#define	USBHS_USBSTS_PCI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
#define	USBHS_USBSTS_FRI_MASK   (0x8U)
#define	USBHS_USBSTS_FRI_SHIFT   (3U)
#define	USBHS_USBSTS_FRI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
#define	USBHS_USBSTS_SEI_MASK   (0x10U)
#define	USBHS_USBSTS_SEI_SHIFT   (4U)
#define	USBHS_USBSTS_SEI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
#define	USBHS_USBSTS_AAI_MASK   (0x20U)
#define	USBHS_USBSTS_AAI_SHIFT   (5U)
#define	USBHS_USBSTS_AAI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
#define	USBHS_USBSTS_URI_MASK   (0x40U)
#define	USBHS_USBSTS_URI_SHIFT   (6U)
#define	USBHS_USBSTS_URI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
#define	USBHS_USBSTS_SRI_MASK   (0x80U)
#define	USBHS_USBSTS_SRI_SHIFT   (7U)
#define	USBHS_USBSTS_SRI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
#define	USBHS_USBSTS_SLI_MASK   (0x100U)
#define	USBHS_USBSTS_SLI_SHIFT   (8U)
#define	USBHS_USBSTS_SLI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
#define	USBHS_USBSTS_HCH_MASK   (0x1000U)
#define	USBHS_USBSTS_HCH_SHIFT   (12U)
#define	USBHS_USBSTS_HCH(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
#define	USBHS_USBSTS_RCL_MASK   (0x2000U)
#define	USBHS_USBSTS_RCL_SHIFT   (13U)
#define	USBHS_USBSTS_RCL(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
#define	USBHS_USBSTS_PS_MASK   (0x4000U)
#define	USBHS_USBSTS_PS_SHIFT   (14U)
#define	USBHS_USBSTS_PS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
#define	USBHS_USBSTS_AS_MASK   (0x8000U)
#define	USBHS_USBSTS_AS_SHIFT   (15U)
#define	USBHS_USBSTS_AS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
#define	USBHS_USBSTS_NAKI_MASK   (0x10000U)
#define	USBHS_USBSTS_NAKI_SHIFT   (16U)
#define	USBHS_USBSTS_NAKI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
#define	USBHS_USBSTS_UAI_MASK   (0x40000U)
#define	USBHS_USBSTS_UAI_SHIFT   (18U)
#define	USBHS_USBSTS_UAI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UAI_SHIFT)) & USBHS_USBSTS_UAI_MASK)
#define	USBHS_USBSTS_UPI_MASK   (0x80000U)
#define	USBHS_USBSTS_UPI_SHIFT   (19U)
#define	USBHS_USBSTS_UPI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UPI_SHIFT)) & USBHS_USBSTS_UPI_MASK)
#define	USBHS_USBSTS_TI0_MASK   (0x1000000U)
#define	USBHS_USBSTS_TI0_SHIFT   (24U)
#define	USBHS_USBSTS_TI0(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
#define	USBHS_USBSTS_TI1_MASK   (0x2000000U)
#define	USBHS_USBSTS_TI1_SHIFT   (25U)
#define	USBHS_USBSTS_TI1(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)
#define	USBHS_USBSTS_UI_MASK   (0x1U)
#define	USBHS_USBSTS_UI_SHIFT   (0U)
#define	USBHS_USBSTS_UI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
#define	USBHS_USBSTS_UEI_MASK   (0x2U)
#define	USBHS_USBSTS_UEI_SHIFT   (1U)
#define	USBHS_USBSTS_UEI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
#define	USBHS_USBSTS_PCI_MASK   (0x4U)
#define	USBHS_USBSTS_PCI_SHIFT   (2U)
#define	USBHS_USBSTS_PCI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
#define	USBHS_USBSTS_FRI_MASK   (0x8U)
#define	USBHS_USBSTS_FRI_SHIFT   (3U)
#define	USBHS_USBSTS_FRI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
#define	USBHS_USBSTS_SEI_MASK   (0x10U)
#define	USBHS_USBSTS_SEI_SHIFT   (4U)
#define	USBHS_USBSTS_SEI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
#define	USBHS_USBSTS_AAI_MASK   (0x20U)
#define	USBHS_USBSTS_AAI_SHIFT   (5U)
#define	USBHS_USBSTS_AAI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
#define	USBHS_USBSTS_URI_MASK   (0x40U)
#define	USBHS_USBSTS_URI_SHIFT   (6U)
#define	USBHS_USBSTS_URI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
#define	USBHS_USBSTS_SRI_MASK   (0x80U)
#define	USBHS_USBSTS_SRI_SHIFT   (7U)
#define	USBHS_USBSTS_SRI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
#define	USBHS_USBSTS_SLI_MASK   (0x100U)
#define	USBHS_USBSTS_SLI_SHIFT   (8U)
#define	USBHS_USBSTS_SLI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
#define	USBHS_USBSTS_HCH_MASK   (0x1000U)
#define	USBHS_USBSTS_HCH_SHIFT   (12U)
#define	USBHS_USBSTS_HCH(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
#define	USBHS_USBSTS_RCL_MASK   (0x2000U)
#define	USBHS_USBSTS_RCL_SHIFT   (13U)
#define	USBHS_USBSTS_RCL(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
#define	USBHS_USBSTS_PS_MASK   (0x4000U)
#define	USBHS_USBSTS_PS_SHIFT   (14U)
#define	USBHS_USBSTS_PS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
#define	USBHS_USBSTS_AS_MASK   (0x8000U)
#define	USBHS_USBSTS_AS_SHIFT   (15U)
#define	USBHS_USBSTS_AS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
#define	USBHS_USBSTS_NAKI_MASK   (0x10000U)
#define	USBHS_USBSTS_NAKI_SHIFT   (16U)
#define	USBHS_USBSTS_NAKI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
#define	USBHS_USBSTS_UAI_MASK   (0x40000U)
#define	USBHS_USBSTS_UAI_SHIFT   (18U)
#define	USBHS_USBSTS_UAI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UAI_SHIFT)) & USBHS_USBSTS_UAI_MASK)
#define	USBHS_USBSTS_UPI_MASK   (0x80000U)
#define	USBHS_USBSTS_UPI_SHIFT   (19U)
#define	USBHS_USBSTS_UPI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UPI_SHIFT)) & USBHS_USBSTS_UPI_MASK)
#define	USBHS_USBSTS_TI0_MASK   (0x1000000U)
#define	USBHS_USBSTS_TI0_SHIFT   (24U)
#define	USBHS_USBSTS_TI0(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
#define	USBHS_USBSTS_TI1_MASK   (0x2000000U)
#define	USBHS_USBSTS_TI1_SHIFT   (25U)
#define	USBHS_USBSTS_TI1(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)

USBINTR - USB Interrupt Enable Register
#define	USBHS_USBINTR_UE_MASK   (0x1U)
#define	USBHS_USBINTR_UE_SHIFT   (0U)
#define	USBHS_USBINTR_UE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
#define	USBHS_USBINTR_UEE_MASK   (0x2U)
#define	USBHS_USBINTR_UEE_SHIFT   (1U)
#define	USBHS_USBINTR_UEE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
#define	USBHS_USBINTR_PCE_MASK   (0x4U)
#define	USBHS_USBINTR_PCE_SHIFT   (2U)
#define	USBHS_USBINTR_PCE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
#define	USBHS_USBINTR_FRE_MASK   (0x8U)
#define	USBHS_USBINTR_FRE_SHIFT   (3U)
#define	USBHS_USBINTR_FRE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
#define	USBHS_USBINTR_SEE_MASK   (0x10U)
#define	USBHS_USBINTR_SEE_SHIFT   (4U)
#define	USBHS_USBINTR_SEE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
#define	USBHS_USBINTR_AAE_MASK   (0x20U)
#define	USBHS_USBINTR_AAE_SHIFT   (5U)
#define	USBHS_USBINTR_AAE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
#define	USBHS_USBINTR_URE_MASK   (0x40U)
#define	USBHS_USBINTR_URE_SHIFT   (6U)
#define	USBHS_USBINTR_URE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
#define	USBHS_USBINTR_SRE_MASK   (0x80U)
#define	USBHS_USBINTR_SRE_SHIFT   (7U)
#define	USBHS_USBINTR_SRE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
#define	USBHS_USBINTR_SLE_MASK   (0x100U)
#define	USBHS_USBINTR_SLE_SHIFT   (8U)
#define	USBHS_USBINTR_SLE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
#define	USBHS_USBINTR_NAKE_MASK   (0x10000U)
#define	USBHS_USBINTR_NAKE_SHIFT   (16U)
#define	USBHS_USBINTR_NAKE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
#define	USBHS_USBINTR_UAIE_MASK   (0x40000U)
#define	USBHS_USBINTR_UAIE_SHIFT   (18U)
#define	USBHS_USBINTR_UAIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
#define	USBHS_USBINTR_UPIE_MASK   (0x80000U)
#define	USBHS_USBINTR_UPIE_SHIFT   (19U)
#define	USBHS_USBINTR_UPIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
#define	USBHS_USBINTR_TIE0_MASK   (0x1000000U)
#define	USBHS_USBINTR_TIE0_SHIFT   (24U)
#define	USBHS_USBINTR_TIE0(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
#define	USBHS_USBINTR_TIE1_MASK   (0x2000000U)
#define	USBHS_USBINTR_TIE1_SHIFT   (25U)
#define	USBHS_USBINTR_TIE1(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)
#define	USBHS_USBINTR_UE_MASK   (0x1U)
#define	USBHS_USBINTR_UE_SHIFT   (0U)
#define	USBHS_USBINTR_UE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
#define	USBHS_USBINTR_UEE_MASK   (0x2U)
#define	USBHS_USBINTR_UEE_SHIFT   (1U)
#define	USBHS_USBINTR_UEE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
#define	USBHS_USBINTR_PCE_MASK   (0x4U)
#define	USBHS_USBINTR_PCE_SHIFT   (2U)
#define	USBHS_USBINTR_PCE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
#define	USBHS_USBINTR_FRE_MASK   (0x8U)
#define	USBHS_USBINTR_FRE_SHIFT   (3U)
#define	USBHS_USBINTR_FRE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
#define	USBHS_USBINTR_SEE_MASK   (0x10U)
#define	USBHS_USBINTR_SEE_SHIFT   (4U)
#define	USBHS_USBINTR_SEE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
#define	USBHS_USBINTR_AAE_MASK   (0x20U)
#define	USBHS_USBINTR_AAE_SHIFT   (5U)
#define	USBHS_USBINTR_AAE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
#define	USBHS_USBINTR_URE_MASK   (0x40U)
#define	USBHS_USBINTR_URE_SHIFT   (6U)
#define	USBHS_USBINTR_URE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
#define	USBHS_USBINTR_SRE_MASK   (0x80U)
#define	USBHS_USBINTR_SRE_SHIFT   (7U)
#define	USBHS_USBINTR_SRE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
#define	USBHS_USBINTR_SLE_MASK   (0x100U)
#define	USBHS_USBINTR_SLE_SHIFT   (8U)
#define	USBHS_USBINTR_SLE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
#define	USBHS_USBINTR_NAKE_MASK   (0x10000U)
#define	USBHS_USBINTR_NAKE_SHIFT   (16U)
#define	USBHS_USBINTR_NAKE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
#define	USBHS_USBINTR_UAIE_MASK   (0x40000U)
#define	USBHS_USBINTR_UAIE_SHIFT   (18U)
#define	USBHS_USBINTR_UAIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
#define	USBHS_USBINTR_UPIE_MASK   (0x80000U)
#define	USBHS_USBINTR_UPIE_SHIFT   (19U)
#define	USBHS_USBINTR_UPIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
#define	USBHS_USBINTR_TIE0_MASK   (0x1000000U)
#define	USBHS_USBINTR_TIE0_SHIFT   (24U)
#define	USBHS_USBINTR_TIE0(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
#define	USBHS_USBINTR_TIE1_MASK   (0x2000000U)
#define	USBHS_USBINTR_TIE1_SHIFT   (25U)
#define	USBHS_USBINTR_TIE1(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)

FRINDEX - Frame Index Register
#define	USBHS_FRINDEX_FRINDEX_MASK   (0x3FFFU)
#define	USBHS_FRINDEX_FRINDEX_SHIFT   (0U)
#define	USBHS_FRINDEX_FRINDEX(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
#define	USBHS_FRINDEX_Reerved_MASK   (0xFFFFC000U)
#define	USBHS_FRINDEX_Reerved_SHIFT   (14U)
#define	USBHS_FRINDEX_Reerved(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_Reerved_SHIFT)) & USBHS_FRINDEX_Reerved_MASK)
#define	USBHS_FRINDEX_FRINDEX_MASK   (0x3FFFU)
#define	USBHS_FRINDEX_FRINDEX_SHIFT   (0U)
#define	USBHS_FRINDEX_FRINDEX(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
#define	USBHS_FRINDEX_Reerved_MASK   (0xFFFFC000U)
#define	USBHS_FRINDEX_Reerved_SHIFT   (14U)
#define	USBHS_FRINDEX_Reerved(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_Reerved_SHIFT)) & USBHS_FRINDEX_Reerved_MASK)

DEVICEADDR - Device Address Register
#define	USBHS_DEVICEADDR_USBADRA_MASK   (0x1000000U)
#define	USBHS_DEVICEADDR_USBADRA_SHIFT   (24U)
#define	USBHS_DEVICEADDR_USBADRA(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
#define	USBHS_DEVICEADDR_USBADR_MASK   (0xFE000000U)
#define	USBHS_DEVICEADDR_USBADR_SHIFT   (25U)
#define	USBHS_DEVICEADDR_USBADR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)
#define	USBHS_DEVICEADDR_USBADRA_MASK   (0x1000000U)
#define	USBHS_DEVICEADDR_USBADRA_SHIFT   (24U)
#define	USBHS_DEVICEADDR_USBADRA(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
#define	USBHS_DEVICEADDR_USBADR_MASK   (0xFE000000U)
#define	USBHS_DEVICEADDR_USBADR_SHIFT   (25U)
#define	USBHS_DEVICEADDR_USBADR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)

PERIODICLISTBASE - Periodic Frame List Base Address Register
#define	USBHS_PERIODICLISTBASE_PERBASE_MASK   (0xFFFFF000U)
#define	USBHS_PERIODICLISTBASE_PERBASE_SHIFT   (12U)
#define	USBHS_PERIODICLISTBASE_PERBASE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_PERBASE_SHIFT)) & USBHS_PERIODICLISTBASE_PERBASE_MASK)
#define	USBHS_PERIODICLISTBASE_PERBASE_MASK   (0xFFFFF000U)
#define	USBHS_PERIODICLISTBASE_PERBASE_SHIFT   (12U)
#define	USBHS_PERIODICLISTBASE_PERBASE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_PERBASE_SHIFT)) & USBHS_PERIODICLISTBASE_PERBASE_MASK)

ASYNCLISTADDR - Current Asynchronous List Address Register
#define	USBHS_ASYNCLISTADDR_ASYBASE_MASK   (0xFFFFFFE0U)
#define	USBHS_ASYNCLISTADDR_ASYBASE_SHIFT   (5U)
#define	USBHS_ASYNCLISTADDR_ASYBASE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)
#define	USBHS_ASYNCLISTADDR_ASYBASE_MASK   (0xFFFFFFE0U)
#define	USBHS_ASYNCLISTADDR_ASYBASE_SHIFT   (5U)
#define	USBHS_ASYNCLISTADDR_ASYBASE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)

EPLISTADDR - Endpoint List Address Register
#define	USBHS_EPLISTADDR_EPBASE_MASK   (0xFFFFF800U)
#define	USBHS_EPLISTADDR_EPBASE_SHIFT   (11U)
#define	USBHS_EPLISTADDR_EPBASE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPLISTADDR_EPBASE_SHIFT)) & USBHS_EPLISTADDR_EPBASE_MASK)
#define	USBHS_EPLISTADDR_EPBASE_MASK   (0xFFFFF800U)
#define	USBHS_EPLISTADDR_EPBASE_SHIFT   (11U)
#define	USBHS_EPLISTADDR_EPBASE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPLISTADDR_EPBASE_SHIFT)) & USBHS_EPLISTADDR_EPBASE_MASK)

TTCTRL - Host TT Asynchronous Buffer Control
#define	USBHS_TTCTRL_TTHA_MASK   (0x7F000000U)
#define	USBHS_TTCTRL_TTHA_SHIFT   (24U)
#define	USBHS_TTCTRL_TTHA(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_TTHA_SHIFT)) & USBHS_TTCTRL_TTHA_MASK)
#define	USBHS_TTCTRL_Reerved_MASK   (0x80000000U)
#define	USBHS_TTCTRL_Reerved_SHIFT   (31U)
#define	USBHS_TTCTRL_Reerved(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_Reerved_SHIFT)) & USBHS_TTCTRL_Reerved_MASK)
#define	USBHS_TTCTRL_TTHA_MASK   (0x7F000000U)
#define	USBHS_TTCTRL_TTHA_SHIFT   (24U)
#define	USBHS_TTCTRL_TTHA(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_TTHA_SHIFT)) & USBHS_TTCTRL_TTHA_MASK)
#define	USBHS_TTCTRL_Reerved_MASK   (0x80000000U)
#define	USBHS_TTCTRL_Reerved_SHIFT   (31U)
#define	USBHS_TTCTRL_Reerved(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_Reerved_SHIFT)) & USBHS_TTCTRL_Reerved_MASK)

BURSTSIZE - Master Interface Data Burst Size Register
#define	USBHS_BURSTSIZE_RXPBURST_MASK   (0xFFU)
#define	USBHS_BURSTSIZE_RXPBURST_SHIFT   (0U)
#define	USBHS_BURSTSIZE_RXPBURST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
#define	USBHS_BURSTSIZE_TXPBURST_MASK   (0xFF00U)
#define	USBHS_BURSTSIZE_TXPBURST_SHIFT   (8U)
#define	USBHS_BURSTSIZE_TXPBURST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)
#define	USBHS_BURSTSIZE_RXPBURST_MASK   (0xFFU)
#define	USBHS_BURSTSIZE_RXPBURST_SHIFT   (0U)
#define	USBHS_BURSTSIZE_RXPBURST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
#define	USBHS_BURSTSIZE_TXPBURST_MASK   (0xFF00U)
#define	USBHS_BURSTSIZE_TXPBURST_SHIFT   (8U)
#define	USBHS_BURSTSIZE_TXPBURST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)

TXFILLTUNING - Transmit FIFO Tuning Control Register
#define	USBHS_TXFILLTUNING_TXSCHOH_MASK   (0x7FU)
#define	USBHS_TXFILLTUNING_TXSCHOH_SHIFT   (0U)
#define	USBHS_TXFILLTUNING_TXSCHOH(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
#define	USBHS_TXFILLTUNING_TXSCHHEALTH_MASK   (0x1F00U)
#define	USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT   (8U)
#define	USBHS_TXFILLTUNING_TXSCHHEALTH(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
#define	USBHS_TXFILLTUNING_TXFIFOTHRES_MASK   (0x3F0000U)
#define	USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT   (16U)
#define	USBHS_TXFILLTUNING_TXFIFOTHRES(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)
#define	USBHS_TXFILLTUNING_TXSCHOH_MASK   (0x7FU)
#define	USBHS_TXFILLTUNING_TXSCHOH_SHIFT   (0U)
#define	USBHS_TXFILLTUNING_TXSCHOH(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
#define	USBHS_TXFILLTUNING_TXSCHHEALTH_MASK   (0x1F00U)
#define	USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT   (8U)
#define	USBHS_TXFILLTUNING_TXSCHHEALTH(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
#define	USBHS_TXFILLTUNING_TXFIFOTHRES_MASK   (0x3F0000U)
#define	USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT   (16U)
#define	USBHS_TXFILLTUNING_TXFIFOTHRES(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)

ENDPTNAK - Endpoint NAK Register
#define	USBHS_ENDPTNAK_EPRN_MASK   (0xFU)
#define	USBHS_ENDPTNAK_EPRN_SHIFT   (0U)
#define	USBHS_ENDPTNAK_EPRN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
#define	USBHS_ENDPTNAK_EPTN_MASK   (0xF0000U)
#define	USBHS_ENDPTNAK_EPTN_SHIFT   (16U)
#define	USBHS_ENDPTNAK_EPTN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)
#define	USBHS_ENDPTNAK_EPRN_MASK   (0xFU)
#define	USBHS_ENDPTNAK_EPRN_SHIFT   (0U)
#define	USBHS_ENDPTNAK_EPRN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
#define	USBHS_ENDPTNAK_EPTN_MASK   (0xF0000U)
#define	USBHS_ENDPTNAK_EPTN_SHIFT   (16U)
#define	USBHS_ENDPTNAK_EPTN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)

ENDPTNAKEN - Endpoint NAK Enable Register
#define	USBHS_ENDPTNAKEN_EPRNE_MASK   (0xFU)
#define	USBHS_ENDPTNAKEN_EPRNE_SHIFT   (0U)
#define	USBHS_ENDPTNAKEN_EPRNE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
#define	USBHS_ENDPTNAKEN_EPTNE_MASK   (0xF0000U)
#define	USBHS_ENDPTNAKEN_EPTNE_SHIFT   (16U)
#define	USBHS_ENDPTNAKEN_EPTNE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)
#define	USBHS_ENDPTNAKEN_EPRNE_MASK   (0xFU)
#define	USBHS_ENDPTNAKEN_EPRNE_SHIFT   (0U)
#define	USBHS_ENDPTNAKEN_EPRNE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
#define	USBHS_ENDPTNAKEN_EPTNE_MASK   (0xF0000U)
#define	USBHS_ENDPTNAKEN_EPTNE_SHIFT   (16U)
#define	USBHS_ENDPTNAKEN_EPTNE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)

PORTSC1 - Port Status and Control Registers
#define	USBHS_PORTSC1_CCS_MASK   (0x1U)
#define	USBHS_PORTSC1_CCS_SHIFT   (0U)
#define	USBHS_PORTSC1_CCS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
#define	USBHS_PORTSC1_CSC_MASK   (0x2U)
#define	USBHS_PORTSC1_CSC_SHIFT   (1U)
#define	USBHS_PORTSC1_CSC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
#define	USBHS_PORTSC1_PE_MASK   (0x4U)
#define	USBHS_PORTSC1_PE_SHIFT   (2U)
#define	USBHS_PORTSC1_PE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
#define	USBHS_PORTSC1_PEC_MASK   (0x8U)
#define	USBHS_PORTSC1_PEC_SHIFT   (3U)
#define	USBHS_PORTSC1_PEC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
#define	USBHS_PORTSC1_OCA_MASK   (0x10U)
#define	USBHS_PORTSC1_OCA_SHIFT   (4U)
#define	USBHS_PORTSC1_OCA(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
#define	USBHS_PORTSC1_OCC_MASK   (0x20U)
#define	USBHS_PORTSC1_OCC_SHIFT   (5U)
#define	USBHS_PORTSC1_OCC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
#define	USBHS_PORTSC1_FPR_MASK   (0x40U)
#define	USBHS_PORTSC1_FPR_SHIFT   (6U)
#define	USBHS_PORTSC1_FPR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
#define	USBHS_PORTSC1_SUSP_MASK   (0x80U)
#define	USBHS_PORTSC1_SUSP_SHIFT   (7U)
#define	USBHS_PORTSC1_SUSP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
#define	USBHS_PORTSC1_PR_MASK   (0x100U)
#define	USBHS_PORTSC1_PR_SHIFT   (8U)
#define	USBHS_PORTSC1_PR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
#define	USBHS_PORTSC1_HSP_MASK   (0x200U)
#define	USBHS_PORTSC1_HSP_SHIFT   (9U)
#define	USBHS_PORTSC1_HSP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
#define	USBHS_PORTSC1_LS_MASK   (0xC00U)
#define	USBHS_PORTSC1_LS_SHIFT   (10U)
#define	USBHS_PORTSC1_LS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
#define	USBHS_PORTSC1_PP_MASK   (0x1000U)
#define	USBHS_PORTSC1_PP_SHIFT   (12U)
#define	USBHS_PORTSC1_PP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
#define	USBHS_PORTSC1_PO_MASK   (0x2000U)
#define	USBHS_PORTSC1_PO_SHIFT   (13U)
#define	USBHS_PORTSC1_PO(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
#define	USBHS_PORTSC1_PIC_MASK   (0xC000U)
#define	USBHS_PORTSC1_PIC_SHIFT   (14U)
#define	USBHS_PORTSC1_PIC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
#define	USBHS_PORTSC1_PTC_MASK   (0xF0000U)
#define	USBHS_PORTSC1_PTC_SHIFT   (16U)
#define	USBHS_PORTSC1_PTC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
#define	USBHS_PORTSC1_WKCN_MASK   (0x100000U)
#define	USBHS_PORTSC1_WKCN_SHIFT   (20U)
#define	USBHS_PORTSC1_WKCN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
#define	USBHS_PORTSC1_WKDS_MASK   (0x200000U)
#define	USBHS_PORTSC1_WKDS_SHIFT   (21U)
#define	USBHS_PORTSC1_WKDS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDS_SHIFT)) & USBHS_PORTSC1_WKDS_MASK)
#define	USBHS_PORTSC1_WKOC_MASK   (0x400000U)
#define	USBHS_PORTSC1_WKOC_SHIFT   (22U)
#define	USBHS_PORTSC1_WKOC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
#define	USBHS_PORTSC1_PHCD_MASK   (0x800000U)
#define	USBHS_PORTSC1_PHCD_SHIFT   (23U)
#define	USBHS_PORTSC1_PHCD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
#define	USBHS_PORTSC1_PFSC_MASK   (0x1000000U)
#define	USBHS_PORTSC1_PFSC_SHIFT   (24U)
#define	USBHS_PORTSC1_PFSC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
#define	USBHS_PORTSC1_PTS2_MASK   (0x2000000U)
#define	USBHS_PORTSC1_PTS2_SHIFT   (25U)
#define	USBHS_PORTSC1_PTS2(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS2_SHIFT)) & USBHS_PORTSC1_PTS2_MASK)
#define	USBHS_PORTSC1_PSPD_MASK   (0xC000000U)
#define	USBHS_PORTSC1_PSPD_SHIFT   (26U)
#define	USBHS_PORTSC1_PSPD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
#define	USBHS_PORTSC1_PTS_MASK   (0xC0000000U)
#define	USBHS_PORTSC1_PTS_SHIFT   (30U)
#define	USBHS_PORTSC1_PTS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)
#define	USBHS_PORTSC1_CCS_MASK   (0x1U)
#define	USBHS_PORTSC1_CCS_SHIFT   (0U)
#define	USBHS_PORTSC1_CCS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
#define	USBHS_PORTSC1_CSC_MASK   (0x2U)
#define	USBHS_PORTSC1_CSC_SHIFT   (1U)
#define	USBHS_PORTSC1_CSC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
#define	USBHS_PORTSC1_PE_MASK   (0x4U)
#define	USBHS_PORTSC1_PE_SHIFT   (2U)
#define	USBHS_PORTSC1_PE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
#define	USBHS_PORTSC1_PEC_MASK   (0x8U)
#define	USBHS_PORTSC1_PEC_SHIFT   (3U)
#define	USBHS_PORTSC1_PEC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
#define	USBHS_PORTSC1_OCA_MASK   (0x10U)
#define	USBHS_PORTSC1_OCA_SHIFT   (4U)
#define	USBHS_PORTSC1_OCA(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
#define	USBHS_PORTSC1_OCC_MASK   (0x20U)
#define	USBHS_PORTSC1_OCC_SHIFT   (5U)
#define	USBHS_PORTSC1_OCC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
#define	USBHS_PORTSC1_FPR_MASK   (0x40U)
#define	USBHS_PORTSC1_FPR_SHIFT   (6U)
#define	USBHS_PORTSC1_FPR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
#define	USBHS_PORTSC1_SUSP_MASK   (0x80U)
#define	USBHS_PORTSC1_SUSP_SHIFT   (7U)
#define	USBHS_PORTSC1_SUSP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
#define	USBHS_PORTSC1_PR_MASK   (0x100U)
#define	USBHS_PORTSC1_PR_SHIFT   (8U)
#define	USBHS_PORTSC1_PR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
#define	USBHS_PORTSC1_HSP_MASK   (0x200U)
#define	USBHS_PORTSC1_HSP_SHIFT   (9U)
#define	USBHS_PORTSC1_HSP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
#define	USBHS_PORTSC1_LS_MASK   (0xC00U)
#define	USBHS_PORTSC1_LS_SHIFT   (10U)
#define	USBHS_PORTSC1_LS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
#define	USBHS_PORTSC1_PP_MASK   (0x1000U)
#define	USBHS_PORTSC1_PP_SHIFT   (12U)
#define	USBHS_PORTSC1_PP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
#define	USBHS_PORTSC1_PO_MASK   (0x2000U)
#define	USBHS_PORTSC1_PO_SHIFT   (13U)
#define	USBHS_PORTSC1_PO(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
#define	USBHS_PORTSC1_PIC_MASK   (0xC000U)
#define	USBHS_PORTSC1_PIC_SHIFT   (14U)
#define	USBHS_PORTSC1_PIC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
#define	USBHS_PORTSC1_PTC_MASK   (0xF0000U)
#define	USBHS_PORTSC1_PTC_SHIFT   (16U)
#define	USBHS_PORTSC1_PTC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
#define	USBHS_PORTSC1_WKCN_MASK   (0x100000U)
#define	USBHS_PORTSC1_WKCN_SHIFT   (20U)
#define	USBHS_PORTSC1_WKCN(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
#define	USBHS_PORTSC1_WKDS_MASK   (0x200000U)
#define	USBHS_PORTSC1_WKDS_SHIFT   (21U)
#define	USBHS_PORTSC1_WKDS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDS_SHIFT)) & USBHS_PORTSC1_WKDS_MASK)
#define	USBHS_PORTSC1_WKOC_MASK   (0x400000U)
#define	USBHS_PORTSC1_WKOC_SHIFT   (22U)
#define	USBHS_PORTSC1_WKOC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
#define	USBHS_PORTSC1_PHCD_MASK   (0x800000U)
#define	USBHS_PORTSC1_PHCD_SHIFT   (23U)
#define	USBHS_PORTSC1_PHCD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
#define	USBHS_PORTSC1_PFSC_MASK   (0x1000000U)
#define	USBHS_PORTSC1_PFSC_SHIFT   (24U)
#define	USBHS_PORTSC1_PFSC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
#define	USBHS_PORTSC1_PTS2_MASK   (0x2000000U)
#define	USBHS_PORTSC1_PTS2_SHIFT   (25U)
#define	USBHS_PORTSC1_PTS2(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS2_SHIFT)) & USBHS_PORTSC1_PTS2_MASK)
#define	USBHS_PORTSC1_PSPD_MASK   (0xC000000U)
#define	USBHS_PORTSC1_PSPD_SHIFT   (26U)
#define	USBHS_PORTSC1_PSPD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
#define	USBHS_PORTSC1_PTS_MASK   (0xC0000000U)
#define	USBHS_PORTSC1_PTS_SHIFT   (30U)
#define	USBHS_PORTSC1_PTS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)

OTGSC - On-the-Go Status and Control Register
#define	USBHS_OTGSC_VD_MASK   (0x1U)
#define	USBHS_OTGSC_VD_SHIFT   (0U)
#define	USBHS_OTGSC_VD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
#define	USBHS_OTGSC_VC_MASK   (0x2U)
#define	USBHS_OTGSC_VC_SHIFT   (1U)
#define	USBHS_OTGSC_VC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
#define	USBHS_OTGSC_HAAR_MASK   (0x4U)
#define	USBHS_OTGSC_HAAR_SHIFT   (2U)
#define	USBHS_OTGSC_HAAR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)
#define	USBHS_OTGSC_OT_MASK   (0x8U)
#define	USBHS_OTGSC_OT_SHIFT   (3U)
#define	USBHS_OTGSC_OT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
#define	USBHS_OTGSC_DP_MASK   (0x10U)
#define	USBHS_OTGSC_DP_SHIFT   (4U)
#define	USBHS_OTGSC_DP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
#define	USBHS_OTGSC_IDPU_MASK   (0x20U)
#define	USBHS_OTGSC_IDPU_SHIFT   (5U)
#define	USBHS_OTGSC_IDPU(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
#define	USBHS_OTGSC_HABA_MASK   (0x80U)
#define	USBHS_OTGSC_HABA_SHIFT   (7U)
#define	USBHS_OTGSC_HABA(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)
#define	USBHS_OTGSC_ID_MASK   (0x100U)
#define	USBHS_OTGSC_ID_SHIFT   (8U)
#define	USBHS_OTGSC_ID(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
#define	USBHS_OTGSC_AVV_MASK   (0x200U)
#define	USBHS_OTGSC_AVV_SHIFT   (9U)
#define	USBHS_OTGSC_AVV(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
#define	USBHS_OTGSC_ASV_MASK   (0x400U)
#define	USBHS_OTGSC_ASV_SHIFT   (10U)
#define	USBHS_OTGSC_ASV(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
#define	USBHS_OTGSC_BSV_MASK   (0x800U)
#define	USBHS_OTGSC_BSV_SHIFT   (11U)
#define	USBHS_OTGSC_BSV(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
#define	USBHS_OTGSC_BSE_MASK   (0x1000U)
#define	USBHS_OTGSC_BSE_SHIFT   (12U)
#define	USBHS_OTGSC_BSE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
#define	USBHS_OTGSC_MST_MASK   (0x2000U)
#define	USBHS_OTGSC_MST_SHIFT   (13U)
#define	USBHS_OTGSC_MST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MST_SHIFT)) & USBHS_OTGSC_MST_MASK)
#define	USBHS_OTGSC_DPS_MASK   (0x4000U)
#define	USBHS_OTGSC_DPS_SHIFT   (14U)
#define	USBHS_OTGSC_DPS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
#define	USBHS_OTGSC_IDIS_MASK   (0x10000U)
#define	USBHS_OTGSC_IDIS_SHIFT   (16U)
#define	USBHS_OTGSC_IDIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
#define	USBHS_OTGSC_AVVIS_MASK   (0x20000U)
#define	USBHS_OTGSC_AVVIS_SHIFT   (17U)
#define	USBHS_OTGSC_AVVIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
#define	USBHS_OTGSC_ASVIS_MASK   (0x40000U)
#define	USBHS_OTGSC_ASVIS_SHIFT   (18U)
#define	USBHS_OTGSC_ASVIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
#define	USBHS_OTGSC_BSVIS_MASK   (0x80000U)
#define	USBHS_OTGSC_BSVIS_SHIFT   (19U)
#define	USBHS_OTGSC_BSVIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
#define	USBHS_OTGSC_BSEIS_MASK   (0x100000U)
#define	USBHS_OTGSC_BSEIS_SHIFT   (20U)
#define	USBHS_OTGSC_BSEIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
#define	USBHS_OTGSC_MSS_MASK   (0x200000U)
#define	USBHS_OTGSC_MSS_SHIFT   (21U)
#define	USBHS_OTGSC_MSS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSS_SHIFT)) & USBHS_OTGSC_MSS_MASK)
#define	USBHS_OTGSC_DPIS_MASK   (0x400000U)
#define	USBHS_OTGSC_DPIS_SHIFT   (22U)
#define	USBHS_OTGSC_DPIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
#define	USBHS_OTGSC_IDIE_MASK   (0x1000000U)
#define	USBHS_OTGSC_IDIE_SHIFT   (24U)
#define	USBHS_OTGSC_IDIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
#define	USBHS_OTGSC_AVVIE_MASK   (0x2000000U)
#define	USBHS_OTGSC_AVVIE_SHIFT   (25U)
#define	USBHS_OTGSC_AVVIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
#define	USBHS_OTGSC_ASVIE_MASK   (0x4000000U)
#define	USBHS_OTGSC_ASVIE_SHIFT   (26U)
#define	USBHS_OTGSC_ASVIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
#define	USBHS_OTGSC_BSVIE_MASK   (0x8000000U)
#define	USBHS_OTGSC_BSVIE_SHIFT   (27U)
#define	USBHS_OTGSC_BSVIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
#define	USBHS_OTGSC_BSEIE_MASK   (0x10000000U)
#define	USBHS_OTGSC_BSEIE_SHIFT   (28U)
#define	USBHS_OTGSC_BSEIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
#define	USBHS_OTGSC_MSE_MASK   (0x20000000U)
#define	USBHS_OTGSC_MSE_SHIFT   (29U)
#define	USBHS_OTGSC_MSE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)
#define	USBHS_OTGSC_DPIE_MASK   (0x40000000U)
#define	USBHS_OTGSC_DPIE_SHIFT   (30U)
#define	USBHS_OTGSC_DPIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)
#define	USBHS_OTGSC_VD_MASK   (0x1U)
#define	USBHS_OTGSC_VD_SHIFT   (0U)
#define	USBHS_OTGSC_VD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
#define	USBHS_OTGSC_VC_MASK   (0x2U)
#define	USBHS_OTGSC_VC_SHIFT   (1U)
#define	USBHS_OTGSC_VC(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
#define	USBHS_OTGSC_HAAR_MASK   (0x4U)
#define	USBHS_OTGSC_HAAR_SHIFT   (2U)
#define	USBHS_OTGSC_HAAR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)
#define	USBHS_OTGSC_OT_MASK   (0x8U)
#define	USBHS_OTGSC_OT_SHIFT   (3U)
#define	USBHS_OTGSC_OT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
#define	USBHS_OTGSC_DP_MASK   (0x10U)
#define	USBHS_OTGSC_DP_SHIFT   (4U)
#define	USBHS_OTGSC_DP(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
#define	USBHS_OTGSC_IDPU_MASK   (0x20U)
#define	USBHS_OTGSC_IDPU_SHIFT   (5U)
#define	USBHS_OTGSC_IDPU(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
#define	USBHS_OTGSC_HABA_MASK   (0x80U)
#define	USBHS_OTGSC_HABA_SHIFT   (7U)
#define	USBHS_OTGSC_HABA(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)
#define	USBHS_OTGSC_ID_MASK   (0x100U)
#define	USBHS_OTGSC_ID_SHIFT   (8U)
#define	USBHS_OTGSC_ID(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
#define	USBHS_OTGSC_AVV_MASK   (0x200U)
#define	USBHS_OTGSC_AVV_SHIFT   (9U)
#define	USBHS_OTGSC_AVV(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
#define	USBHS_OTGSC_ASV_MASK   (0x400U)
#define	USBHS_OTGSC_ASV_SHIFT   (10U)
#define	USBHS_OTGSC_ASV(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
#define	USBHS_OTGSC_BSV_MASK   (0x800U)
#define	USBHS_OTGSC_BSV_SHIFT   (11U)
#define	USBHS_OTGSC_BSV(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
#define	USBHS_OTGSC_BSE_MASK   (0x1000U)
#define	USBHS_OTGSC_BSE_SHIFT   (12U)
#define	USBHS_OTGSC_BSE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
#define	USBHS_OTGSC_MST_MASK   (0x2000U)
#define	USBHS_OTGSC_MST_SHIFT   (13U)
#define	USBHS_OTGSC_MST(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MST_SHIFT)) & USBHS_OTGSC_MST_MASK)
#define	USBHS_OTGSC_DPS_MASK   (0x4000U)
#define	USBHS_OTGSC_DPS_SHIFT   (14U)
#define	USBHS_OTGSC_DPS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
#define	USBHS_OTGSC_IDIS_MASK   (0x10000U)
#define	USBHS_OTGSC_IDIS_SHIFT   (16U)
#define	USBHS_OTGSC_IDIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
#define	USBHS_OTGSC_AVVIS_MASK   (0x20000U)
#define	USBHS_OTGSC_AVVIS_SHIFT   (17U)
#define	USBHS_OTGSC_AVVIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
#define	USBHS_OTGSC_ASVIS_MASK   (0x40000U)
#define	USBHS_OTGSC_ASVIS_SHIFT   (18U)
#define	USBHS_OTGSC_ASVIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
#define	USBHS_OTGSC_BSVIS_MASK   (0x80000U)
#define	USBHS_OTGSC_BSVIS_SHIFT   (19U)
#define	USBHS_OTGSC_BSVIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
#define	USBHS_OTGSC_BSEIS_MASK   (0x100000U)
#define	USBHS_OTGSC_BSEIS_SHIFT   (20U)
#define	USBHS_OTGSC_BSEIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
#define	USBHS_OTGSC_MSS_MASK   (0x200000U)
#define	USBHS_OTGSC_MSS_SHIFT   (21U)
#define	USBHS_OTGSC_MSS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSS_SHIFT)) & USBHS_OTGSC_MSS_MASK)
#define	USBHS_OTGSC_DPIS_MASK   (0x400000U)
#define	USBHS_OTGSC_DPIS_SHIFT   (22U)
#define	USBHS_OTGSC_DPIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
#define	USBHS_OTGSC_IDIE_MASK   (0x1000000U)
#define	USBHS_OTGSC_IDIE_SHIFT   (24U)
#define	USBHS_OTGSC_IDIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
#define	USBHS_OTGSC_AVVIE_MASK   (0x2000000U)
#define	USBHS_OTGSC_AVVIE_SHIFT   (25U)
#define	USBHS_OTGSC_AVVIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
#define	USBHS_OTGSC_ASVIE_MASK   (0x4000000U)
#define	USBHS_OTGSC_ASVIE_SHIFT   (26U)
#define	USBHS_OTGSC_ASVIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
#define	USBHS_OTGSC_BSVIE_MASK   (0x8000000U)
#define	USBHS_OTGSC_BSVIE_SHIFT   (27U)
#define	USBHS_OTGSC_BSVIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
#define	USBHS_OTGSC_BSEIE_MASK   (0x10000000U)
#define	USBHS_OTGSC_BSEIE_SHIFT   (28U)
#define	USBHS_OTGSC_BSEIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
#define	USBHS_OTGSC_MSE_MASK   (0x20000000U)
#define	USBHS_OTGSC_MSE_SHIFT   (29U)
#define	USBHS_OTGSC_MSE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)
#define	USBHS_OTGSC_DPIE_MASK   (0x40000000U)
#define	USBHS_OTGSC_DPIE_SHIFT   (30U)
#define	USBHS_OTGSC_DPIE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)

USBMODE - USB Mode Register
#define	USBHS_USBMODE_CM_MASK   (0x3U)
#define	USBHS_USBMODE_CM_SHIFT   (0U)
#define	USBHS_USBMODE_CM(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
#define	USBHS_USBMODE_ES_MASK   (0x4U)
#define	USBHS_USBMODE_ES_SHIFT   (2U)
#define	USBHS_USBMODE_ES(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
#define	USBHS_USBMODE_SLOM_MASK   (0x8U)
#define	USBHS_USBMODE_SLOM_SHIFT   (3U)
#define	USBHS_USBMODE_SLOM(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
#define	USBHS_USBMODE_SDIS_MASK   (0x10U)
#define	USBHS_USBMODE_SDIS_SHIFT   (4U)
#define	USBHS_USBMODE_SDIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
#define	USBHS_USBMODE_TXHSD_MASK   (0x7000U)
#define	USBHS_USBMODE_TXHSD_SHIFT   (12U)
#define	USBHS_USBMODE_TXHSD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)
#define	USBHS_USBMODE_CM_MASK   (0x3U)
#define	USBHS_USBMODE_CM_SHIFT   (0U)
#define	USBHS_USBMODE_CM(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
#define	USBHS_USBMODE_ES_MASK   (0x4U)
#define	USBHS_USBMODE_ES_SHIFT   (2U)
#define	USBHS_USBMODE_ES(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
#define	USBHS_USBMODE_SLOM_MASK   (0x8U)
#define	USBHS_USBMODE_SLOM_SHIFT   (3U)
#define	USBHS_USBMODE_SLOM(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
#define	USBHS_USBMODE_SDIS_MASK   (0x10U)
#define	USBHS_USBMODE_SDIS_SHIFT   (4U)
#define	USBHS_USBMODE_SDIS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
#define	USBHS_USBMODE_TXHSD_MASK   (0x7000U)
#define	USBHS_USBMODE_TXHSD_SHIFT   (12U)
#define	USBHS_USBMODE_TXHSD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)

EPSETUPSR - Endpoint Setup Status Register
#define	USBHS_EPSETUPSR_EPSETUPSTAT_MASK   (0xFU)
#define	USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT   (0U)
#define	USBHS_EPSETUPSR_EPSETUPSTAT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT)) & USBHS_EPSETUPSR_EPSETUPSTAT_MASK)
#define	USBHS_EPSETUPSR_EPSETUPSTAT_MASK   (0xFU)
#define	USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT   (0U)
#define	USBHS_EPSETUPSR_EPSETUPSTAT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT)) & USBHS_EPSETUPSR_EPSETUPSTAT_MASK)

EPPRIME - Endpoint Initialization Register
#define	USBHS_EPPRIME_PERB_MASK   (0xFU)
#define	USBHS_EPPRIME_PERB_SHIFT   (0U)
#define	USBHS_EPPRIME_PERB(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PERB_SHIFT)) & USBHS_EPPRIME_PERB_MASK)
#define	USBHS_EPPRIME_PETB_MASK   (0xF0000U)
#define	USBHS_EPPRIME_PETB_SHIFT   (16U)
#define	USBHS_EPPRIME_PETB(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PETB_SHIFT)) & USBHS_EPPRIME_PETB_MASK)
#define	USBHS_EPPRIME_PERB_MASK   (0xFU)
#define	USBHS_EPPRIME_PERB_SHIFT   (0U)
#define	USBHS_EPPRIME_PERB(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PERB_SHIFT)) & USBHS_EPPRIME_PERB_MASK)
#define	USBHS_EPPRIME_PETB_MASK   (0xF0000U)
#define	USBHS_EPPRIME_PETB_SHIFT   (16U)
#define	USBHS_EPPRIME_PETB(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PETB_SHIFT)) & USBHS_EPPRIME_PETB_MASK)

EPFLUSH - Endpoint Flush Register
#define	USBHS_EPFLUSH_FERB_MASK   (0xFU)
#define	USBHS_EPFLUSH_FERB_SHIFT   (0U)
#define	USBHS_EPFLUSH_FERB(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FERB_SHIFT)) & USBHS_EPFLUSH_FERB_MASK)
#define	USBHS_EPFLUSH_FETB_MASK   (0xF0000U)
#define	USBHS_EPFLUSH_FETB_SHIFT   (16U)
#define	USBHS_EPFLUSH_FETB(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FETB_SHIFT)) & USBHS_EPFLUSH_FETB_MASK)
#define	USBHS_EPFLUSH_FERB_MASK   (0xFU)
#define	USBHS_EPFLUSH_FERB_SHIFT   (0U)
#define	USBHS_EPFLUSH_FERB(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FERB_SHIFT)) & USBHS_EPFLUSH_FERB_MASK)
#define	USBHS_EPFLUSH_FETB_MASK   (0xF0000U)
#define	USBHS_EPFLUSH_FETB_SHIFT   (16U)
#define	USBHS_EPFLUSH_FETB(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FETB_SHIFT)) & USBHS_EPFLUSH_FETB_MASK)

EPSR - Endpoint Status Register
#define	USBHS_EPSR_ERBR_MASK   (0xFU)
#define	USBHS_EPSR_ERBR_SHIFT   (0U)
#define	USBHS_EPSR_ERBR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ERBR_SHIFT)) & USBHS_EPSR_ERBR_MASK)
#define	USBHS_EPSR_ETBR_MASK   (0xF0000U)
#define	USBHS_EPSR_ETBR_SHIFT   (16U)
#define	USBHS_EPSR_ETBR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ETBR_SHIFT)) & USBHS_EPSR_ETBR_MASK)
#define	USBHS_EPSR_ERBR_MASK   (0xFU)
#define	USBHS_EPSR_ERBR_SHIFT   (0U)
#define	USBHS_EPSR_ERBR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ERBR_SHIFT)) & USBHS_EPSR_ERBR_MASK)
#define	USBHS_EPSR_ETBR_MASK   (0xF0000U)
#define	USBHS_EPSR_ETBR_SHIFT   (16U)
#define	USBHS_EPSR_ETBR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ETBR_SHIFT)) & USBHS_EPSR_ETBR_MASK)

EPCOMPLETE - Endpoint Complete Register
#define	USBHS_EPCOMPLETE_ERCE_MASK   (0xFU)
#define	USBHS_EPCOMPLETE_ERCE_SHIFT   (0U)
#define	USBHS_EPCOMPLETE_ERCE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ERCE_SHIFT)) & USBHS_EPCOMPLETE_ERCE_MASK)
#define	USBHS_EPCOMPLETE_ETCE_MASK   (0xF0000U)
#define	USBHS_EPCOMPLETE_ETCE_SHIFT   (16U)
#define	USBHS_EPCOMPLETE_ETCE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ETCE_SHIFT)) & USBHS_EPCOMPLETE_ETCE_MASK)
#define	USBHS_EPCOMPLETE_ERCE_MASK   (0xFU)
#define	USBHS_EPCOMPLETE_ERCE_SHIFT   (0U)
#define	USBHS_EPCOMPLETE_ERCE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ERCE_SHIFT)) & USBHS_EPCOMPLETE_ERCE_MASK)
#define	USBHS_EPCOMPLETE_ETCE_MASK   (0xF0000U)
#define	USBHS_EPCOMPLETE_ETCE_SHIFT   (16U)
#define	USBHS_EPCOMPLETE_ETCE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ETCE_SHIFT)) & USBHS_EPCOMPLETE_ETCE_MASK)

EPCR0 - Endpoint Control Register 0
#define	USBHS_EPCR0_RXS_MASK   (0x1U)
#define	USBHS_EPCR0_RXS_SHIFT   (0U)
#define	USBHS_EPCR0_RXS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)
#define	USBHS_EPCR0_RXT_MASK   (0xCU)
#define	USBHS_EPCR0_RXT_SHIFT   (2U)
#define	USBHS_EPCR0_RXT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)
#define	USBHS_EPCR0_RXE_MASK   (0x80U)
#define	USBHS_EPCR0_RXE_SHIFT   (7U)
#define	USBHS_EPCR0_RXE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)
#define	USBHS_EPCR0_TXS_MASK   (0x10000U)
#define	USBHS_EPCR0_TXS_SHIFT   (16U)
#define	USBHS_EPCR0_TXS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)
#define	USBHS_EPCR0_TXT_MASK   (0xC0000U)
#define	USBHS_EPCR0_TXT_SHIFT   (18U)
#define	USBHS_EPCR0_TXT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)
#define	USBHS_EPCR0_TXE_MASK   (0x800000U)
#define	USBHS_EPCR0_TXE_SHIFT   (23U)
#define	USBHS_EPCR0_TXE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)
#define	USBHS_EPCR0_RXS_MASK   (0x1U)
#define	USBHS_EPCR0_RXS_SHIFT   (0U)
#define	USBHS_EPCR0_RXS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)
#define	USBHS_EPCR0_RXT_MASK   (0xCU)
#define	USBHS_EPCR0_RXT_SHIFT   (2U)
#define	USBHS_EPCR0_RXT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)
#define	USBHS_EPCR0_RXE_MASK   (0x80U)
#define	USBHS_EPCR0_RXE_SHIFT   (7U)
#define	USBHS_EPCR0_RXE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)
#define	USBHS_EPCR0_TXS_MASK   (0x10000U)
#define	USBHS_EPCR0_TXS_SHIFT   (16U)
#define	USBHS_EPCR0_TXS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)
#define	USBHS_EPCR0_TXT_MASK   (0xC0000U)
#define	USBHS_EPCR0_TXT_SHIFT   (18U)
#define	USBHS_EPCR0_TXT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)
#define	USBHS_EPCR0_TXE_MASK   (0x800000U)
#define	USBHS_EPCR0_TXE_SHIFT   (23U)
#define	USBHS_EPCR0_TXE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)

EPCR - Endpoint Control Register n
#define	USBHS_EPCR_RXS_MASK   (0x1U)
#define	USBHS_EPCR_RXS_SHIFT   (0U)
#define	USBHS_EPCR_RXS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)
#define	USBHS_EPCR_RXD_MASK   (0x2U)
#define	USBHS_EPCR_RXD_SHIFT   (1U)
#define	USBHS_EPCR_RXD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXD_SHIFT)) & USBHS_EPCR_RXD_MASK)
#define	USBHS_EPCR_RXT_MASK   (0xCU)
#define	USBHS_EPCR_RXT_SHIFT   (2U)
#define	USBHS_EPCR_RXT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)
#define	USBHS_EPCR_RXI_MASK   (0x20U)
#define	USBHS_EPCR_RXI_SHIFT   (5U)
#define	USBHS_EPCR_RXI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)
#define	USBHS_EPCR_RXR_MASK   (0x40U)
#define	USBHS_EPCR_RXR_SHIFT   (6U)
#define	USBHS_EPCR_RXR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXR_SHIFT)) & USBHS_EPCR_RXR_MASK)
#define	USBHS_EPCR_RXE_MASK   (0x80U)
#define	USBHS_EPCR_RXE_SHIFT   (7U)
#define	USBHS_EPCR_RXE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)
#define	USBHS_EPCR_TXS_MASK   (0x10000U)
#define	USBHS_EPCR_TXS_SHIFT   (16U)
#define	USBHS_EPCR_TXS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)
#define	USBHS_EPCR_TXD_MASK   (0x20000U)
#define	USBHS_EPCR_TXD_SHIFT   (17U)
#define	USBHS_EPCR_TXD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXD_SHIFT)) & USBHS_EPCR_TXD_MASK)
#define	USBHS_EPCR_TXT_MASK   (0xC0000U)
#define	USBHS_EPCR_TXT_SHIFT   (18U)
#define	USBHS_EPCR_TXT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)
#define	USBHS_EPCR_TXI_MASK   (0x200000U)
#define	USBHS_EPCR_TXI_SHIFT   (21U)
#define	USBHS_EPCR_TXI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)
#define	USBHS_EPCR_TXR_MASK   (0x400000U)
#define	USBHS_EPCR_TXR_SHIFT   (22U)
#define	USBHS_EPCR_TXR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXR_SHIFT)) & USBHS_EPCR_TXR_MASK)
#define	USBHS_EPCR_TXE_MASK   (0x800000U)
#define	USBHS_EPCR_TXE_SHIFT   (23U)
#define	USBHS_EPCR_TXE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)
#define	USBHS_EPCR_RXS_MASK   (0x1U)
#define	USBHS_EPCR_RXS_SHIFT   (0U)
#define	USBHS_EPCR_RXS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)
#define	USBHS_EPCR_RXD_MASK   (0x2U)
#define	USBHS_EPCR_RXD_SHIFT   (1U)
#define	USBHS_EPCR_RXD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXD_SHIFT)) & USBHS_EPCR_RXD_MASK)
#define	USBHS_EPCR_RXT_MASK   (0xCU)
#define	USBHS_EPCR_RXT_SHIFT   (2U)
#define	USBHS_EPCR_RXT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)
#define	USBHS_EPCR_RXI_MASK   (0x20U)
#define	USBHS_EPCR_RXI_SHIFT   (5U)
#define	USBHS_EPCR_RXI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)
#define	USBHS_EPCR_RXR_MASK   (0x40U)
#define	USBHS_EPCR_RXR_SHIFT   (6U)
#define	USBHS_EPCR_RXR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXR_SHIFT)) & USBHS_EPCR_RXR_MASK)
#define	USBHS_EPCR_RXE_MASK   (0x80U)
#define	USBHS_EPCR_RXE_SHIFT   (7U)
#define	USBHS_EPCR_RXE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)
#define	USBHS_EPCR_TXS_MASK   (0x10000U)
#define	USBHS_EPCR_TXS_SHIFT   (16U)
#define	USBHS_EPCR_TXS(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)
#define	USBHS_EPCR_TXD_MASK   (0x20000U)
#define	USBHS_EPCR_TXD_SHIFT   (17U)
#define	USBHS_EPCR_TXD(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXD_SHIFT)) & USBHS_EPCR_TXD_MASK)
#define	USBHS_EPCR_TXT_MASK   (0xC0000U)
#define	USBHS_EPCR_TXT_SHIFT   (18U)
#define	USBHS_EPCR_TXT(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)
#define	USBHS_EPCR_TXI_MASK   (0x200000U)
#define	USBHS_EPCR_TXI_SHIFT   (21U)
#define	USBHS_EPCR_TXI(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)
#define	USBHS_EPCR_TXR_MASK   (0x400000U)
#define	USBHS_EPCR_TXR_SHIFT   (22U)
#define	USBHS_EPCR_TXR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXR_SHIFT)) & USBHS_EPCR_TXR_MASK)
#define	USBHS_EPCR_TXE_MASK   (0x800000U)
#define	USBHS_EPCR_TXE_SHIFT   (23U)
#define	USBHS_EPCR_TXE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)

USBGENCTRL - USB General Control Register
#define	USBHS_USBGENCTRL_WU_IE_MASK   (0x1U)
#define	USBHS_USBGENCTRL_WU_IE_SHIFT   (0U)
#define	USBHS_USBGENCTRL_WU_IE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)
#define	USBHS_USBGENCTRL_WU_INT_CLR_MASK   (0x20U)
#define	USBHS_USBGENCTRL_WU_INT_CLR_SHIFT   (5U)
#define	USBHS_USBGENCTRL_WU_INT_CLR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)
#define	USBHS_USBGENCTRL_WU_IE_MASK   (0x1U)
#define	USBHS_USBGENCTRL_WU_IE_SHIFT   (0U)
#define	USBHS_USBGENCTRL_WU_IE(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)
#define	USBHS_USBGENCTRL_WU_INT_CLR_MASK   (0x20U)
#define	USBHS_USBGENCTRL_WU_INT_CLR_SHIFT   (5U)
#define	USBHS_USBGENCTRL_WU_INT_CLR(x)   (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)

Macro Definition Documentation

USBHS_DEVICEADDR_USBADRA [1/2]

#define USBHS_DEVICEADDR_USBADRA

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)

USBADRA - Device Address Advance 0b0..Writes to USBADR are instantaneous. 0b1..When this bit is written to a 1 at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR is loaded from the holding register.

USBHS_DEVICEADDR_USBADRA [2/2]

#define USBHS_DEVICEADDR_USBADRA

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)

USBADRA - Device Address Advance 0b0..Writes to USBADR are instantaneous. 0b1..When this bit is written to a 1 at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR is loaded from the holding register.

USBHS_EPCR0_RXE [1/2]

#define USBHS_EPCR0_RXE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)

RXE - RX endpoint Enable 0b1..Enabled

USBHS_EPCR0_RXE [2/2]

#define USBHS_EPCR0_RXE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)

RXE - RX endpoint Enable 0b1..Enabled

USBHS_EPCR0_RXS [1/2]

#define USBHS_EPCR0_RXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)

RXS - RX endpoint Stall 0b0..Endpoint OK 0b1..Endpoint stalled

USBHS_EPCR0_RXS [2/2]

#define USBHS_EPCR0_RXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)

RXS - RX endpoint Stall 0b0..Endpoint OK 0b1..Endpoint stalled

USBHS_EPCR0_RXT [1/2]

#define USBHS_EPCR0_RXT

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)

RXT - RX endpoint Type 0b00..Control

USBHS_EPCR0_RXT [2/2]

#define USBHS_EPCR0_RXT

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)

RXT - RX endpoint Type 0b00..Control

USBHS_EPCR0_TXE [1/2]

#define USBHS_EPCR0_TXE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)

TXE - TX Endpoint Enable 0b1..Enable

USBHS_EPCR0_TXE [2/2]

#define USBHS_EPCR0_TXE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)

TXE - TX Endpoint Enable 0b1..Enable

USBHS_EPCR0_TXS [1/2]

#define USBHS_EPCR0_TXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)

TXS - TX Endpoint Stall 0b0..Endpoint OK 0b1..Endpoint stalled

USBHS_EPCR0_TXS [2/2]

#define USBHS_EPCR0_TXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)

TXS - TX Endpoint Stall 0b0..Endpoint OK 0b1..Endpoint stalled

USBHS_EPCR0_TXT [1/2]

#define USBHS_EPCR0_TXT

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)

TXT - TX Endpoint Type 0b00..Control

USBHS_EPCR0_TXT [2/2]

#define USBHS_EPCR0_TXT

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)

TXT - TX Endpoint Type 0b00..Control

USBHS_EPCR_RXE [1/2]

#define USBHS_EPCR_RXE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)

RXE - RX endpoint Enable 0b0..Disabled 0b1..Enabled

USBHS_EPCR_RXE [2/2]

#define USBHS_EPCR_RXE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)

RXE - RX endpoint Enable 0b0..Disabled 0b1..Enabled

USBHS_EPCR_RXI [1/2]

#define USBHS_EPCR_RXI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)

RXI - RX data toggle Inhibit 0b0..PID sequencing enabled 0b1..PID sequencing disabled

USBHS_EPCR_RXI [2/2]

#define USBHS_EPCR_RXI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)

RXI - RX data toggle Inhibit 0b0..PID sequencing enabled 0b1..PID sequencing disabled

USBHS_EPCR_RXS [1/2]

#define USBHS_EPCR_RXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)

RXS - RX endpoint Stall 0b0..Endpoint OK 0b1..Endpoint stalled

USBHS_EPCR_RXS [2/2]

#define USBHS_EPCR_RXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)

RXS - RX endpoint Stall 0b0..Endpoint OK 0b1..Endpoint stalled

USBHS_EPCR_RXT [1/2]

#define USBHS_EPCR_RXT

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)

RXT - RX endpoint Type 0b00..Control 0b01..Isochronous 0b10..Bulk 0b11..Interrupt

USBHS_EPCR_RXT [2/2]

#define USBHS_EPCR_RXT

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)

RXT - RX endpoint Type 0b00..Control 0b01..Isochronous 0b10..Bulk 0b11..Interrupt

USBHS_EPCR_TXE [1/2]

#define USBHS_EPCR_TXE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)

TXE - TX endpoint Enable 0b0..Disabled 0b1..Enabled

USBHS_EPCR_TXE [2/2]

#define USBHS_EPCR_TXE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)

TXE - TX endpoint Enable 0b0..Disabled 0b1..Enabled

USBHS_EPCR_TXI [1/2]

#define USBHS_EPCR_TXI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)

TXI - TX data toggle Inhibit 0b0..PID sequencing enabled 0b1..PID sequencing disabled

USBHS_EPCR_TXI [2/2]

#define USBHS_EPCR_TXI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)

TXI - TX data toggle Inhibit 0b0..PID sequencing enabled 0b1..PID sequencing disabled

USBHS_EPCR_TXS [1/2]

#define USBHS_EPCR_TXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)

TXS - TX endpoint Stall 0b0..Endpoint OK 0b1..Endpoint stalled

USBHS_EPCR_TXS [2/2]

#define USBHS_EPCR_TXS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)

TXS - TX endpoint Stall 0b0..Endpoint OK 0b1..Endpoint stalled

USBHS_EPCR_TXT [1/2]

#define USBHS_EPCR_TXT

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)

TXT - TX endpoint Type 0b00..Control 0b01..Isochronous 0b10..Bulk 0b11..Interrupt

USBHS_EPCR_TXT [2/2]

#define USBHS_EPCR_TXT

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)

TXT - TX endpoint Type 0b00..Control 0b01..Isochronous 0b10..Bulk 0b11..Interrupt

USBHS_GPTIMER0CTL_MODE [1/2]

#define USBHS_GPTIMER0CTL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)

MODE - Timer Mode 0b0..One shot 0b1..Repeat

USBHS_GPTIMER0CTL_MODE [2/2]

#define USBHS_GPTIMER0CTL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)

MODE - Timer Mode 0b0..One shot 0b1..Repeat

USBHS_GPTIMER0CTL_RST [1/2]

#define USBHS_GPTIMER0CTL_RST

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)

RST - Timer Reset 0b0..No action 0b1..Load counter value

USBHS_GPTIMER0CTL_RST [2/2]

#define USBHS_GPTIMER0CTL_RST

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)

RST - Timer Reset 0b0..No action 0b1..Load counter value

USBHS_GPTIMER0CTL_RUN [1/2]

#define USBHS_GPTIMER0CTL_RUN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)

RUN - Timer Run 0b0..Timer stop 0b1..Timer run

USBHS_GPTIMER0CTL_RUN [2/2]

#define USBHS_GPTIMER0CTL_RUN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)

RUN - Timer Run 0b0..Timer stop 0b1..Timer run

USBHS_GPTIMER1CTL_MODE [1/2]

#define USBHS_GPTIMER1CTL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)

MODE - Timer Mode 0b0..One shot 0b1..Repeat

USBHS_GPTIMER1CTL_MODE [2/2]

#define USBHS_GPTIMER1CTL_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)

MODE - Timer Mode 0b0..One shot 0b1..Repeat

USBHS_GPTIMER1CTL_RST [1/2]

#define USBHS_GPTIMER1CTL_RST

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)

RST - Timer Reset 0b0..No action 0b1..Load counter value

USBHS_GPTIMER1CTL_RST [2/2]

#define USBHS_GPTIMER1CTL_RST

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)

RST - Timer Reset 0b0..No action 0b1..Load counter value

USBHS_GPTIMER1CTL_RUN [1/2]

#define USBHS_GPTIMER1CTL_RUN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)

RUN - Timer Run 0b0..Timer stop 0b1..Timer run

USBHS_GPTIMER1CTL_RUN [2/2]

#define USBHS_GPTIMER1CTL_RUN

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)

RUN - Timer Run 0b0..Timer stop 0b1..Timer run

USBHS_HCCPARAMS_ASP [1/2]

#define USBHS_HCCPARAMS_ASP

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)

ASP - Asynchronous Schedule Park capability 0b0..Park not supported. 0b1..Park supported.

USBHS_HCCPARAMS_ASP [2/2]

#define USBHS_HCCPARAMS_ASP

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)

ASP - Asynchronous Schedule Park capability 0b0..Park not supported. 0b1..Park supported.

USBHS_HCCPARAMS_EECP [1/2]

#define USBHS_HCCPARAMS_EECP

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)

EECP - EHCI Extended Capabilities Pointer 0b00000000..No extended capabilities are implemented

USBHS_HCCPARAMS_EECP [2/2]

#define USBHS_HCCPARAMS_EECP

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)

EECP - EHCI Extended Capabilities Pointer 0b00000000..No extended capabilities are implemented

USBHS_HCCPARAMS_IST [1/2]

#define USBHS_HCCPARAMS_IST

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)

IST - Isochronous Scheduling Threshold 0b0000..The value of the least significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data structures (one or more) before flushing the state

USBHS_HCCPARAMS_IST [2/2]

#define USBHS_HCCPARAMS_IST

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)

IST - Isochronous Scheduling Threshold 0b0000..The value of the least significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data structures (one or more) before flushing the state

USBHS_HCSPARAMS_PI [1/2]

#define USBHS_HCSPARAMS_PI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)

PI - Port Indicators 0b0..No port indicator fields 0b1..The port status and control registers include a R/W field for controlling the state of the port indicator

USBHS_HCSPARAMS_PI [2/2]

#define USBHS_HCSPARAMS_PI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)

PI - Port Indicators 0b0..No port indicator fields 0b1..The port status and control registers include a R/W field for controlling the state of the port indicator

USBHS_HCSPARAMS_PPC [1/2]

#define USBHS_HCSPARAMS_PPC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)

PPC - Power Port Control 0b1..Ports have power port switches

USBHS_HCSPARAMS_PPC [2/2]

#define USBHS_HCSPARAMS_PPC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)

PPC - Power Port Control 0b1..Ports have power port switches

USBHS_HWGENERAL_PHYM [1/2]

#define USBHS_HWGENERAL_PHYM

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)

PHYM - PHY Mode 0b000..Controller configured for UTMI/UTMI+ interface.

USBHS_HWGENERAL_PHYM [2/2]

#define USBHS_HWGENERAL_PHYM

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)

PHYM - PHY Mode 0b000..Controller configured for UTMI/UTMI+ interface.

USBHS_HWGENERAL_PHYW [1/2]

#define USBHS_HWGENERAL_PHYW

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)

PHYW - PHY Width 0b01..16 bit wide data bus

USBHS_HWGENERAL_PHYW [2/2]

#define USBHS_HWGENERAL_PHYW

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)

PHYW - PHY Width 0b01..16 bit wide data bus

USBHS_HWGENERAL_SM [1/2]

#define USBHS_HWGENERAL_SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)

SM - Serial mode 0b00..No Serial Engine, always use parallel signaling.

USBHS_HWGENERAL_SM [2/2]

#define USBHS_HWGENERAL_SM

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)

SM - Serial mode 0b00..No Serial Engine, always use parallel signaling.

USBHS_HWTXBUF_TXLC [1/2]

#define USBHS_HWTXBUF_TXLC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)

TXLC - Transmit local Context Registers 0b0..Store device transmit contexts in the TX FIFO 0b1..Store device transmit contexts in a register file

USBHS_HWTXBUF_TXLC [2/2]

#define USBHS_HWTXBUF_TXLC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)

TXLC - Transmit local Context Registers 0b0..Store device transmit contexts in the TX FIFO 0b1..Store device transmit contexts in a register file

USBHS_OTGSC_ASV [1/2]

#define USBHS_OTGSC_ASV

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)

ASV - A Session Valid 0b0..VBus is below A session valid threshold 0b1..VBus is above A session valid threshold

USBHS_OTGSC_ASV [2/2]

#define USBHS_OTGSC_ASV

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)

ASV - A Session Valid 0b0..VBus is below A session valid threshold 0b1..VBus is above A session valid threshold

USBHS_OTGSC_ASVIE [1/2]

#define USBHS_OTGSC_ASVIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)

ASVIE - A Session Valid Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_ASVIE [2/2]

#define USBHS_OTGSC_ASVIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)

ASVIE - A Session Valid Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_AVV [1/2]

#define USBHS_OTGSC_AVV

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)

AVV - A VBus Valid 0b0..VBus is below A VBus valid threshold 0b1..VBus is above A VBus valid threshold

USBHS_OTGSC_AVV [2/2]

#define USBHS_OTGSC_AVV

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)

AVV - A VBus Valid 0b0..VBus is below A VBus valid threshold 0b1..VBus is above A VBus valid threshold

USBHS_OTGSC_AVVIE [1/2]

#define USBHS_OTGSC_AVVIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)

AVVIE - A VBUS Valid Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_AVVIE [2/2]

#define USBHS_OTGSC_AVVIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)

AVVIE - A VBUS Valid Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_BSE [1/2]

#define USBHS_OTGSC_BSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)

BSE - B Session End 0b0..VBus is above B session end threshold 0b1..VBus is below B session end threshold

USBHS_OTGSC_BSE [2/2]

#define USBHS_OTGSC_BSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)

BSE - B Session End 0b0..VBus is above B session end threshold 0b1..VBus is below B session end threshold

USBHS_OTGSC_BSEIE [1/2]

#define USBHS_OTGSC_BSEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)

BSEIE - B Session End Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_BSEIE [2/2]

#define USBHS_OTGSC_BSEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)

BSEIE - B Session End Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_BSV [1/2]

#define USBHS_OTGSC_BSV

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)

BSV - B Session Valid 0b0..VBus is below B session valid threshold 0b1..VBus is above B session valid threshold

USBHS_OTGSC_BSV [2/2]

#define USBHS_OTGSC_BSV

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)

BSV - B Session Valid 0b0..VBus is below B session valid threshold 0b1..VBus is above B session valid threshold

USBHS_OTGSC_BSVIE [1/2]

#define USBHS_OTGSC_BSVIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)

BSVIE - B Session Valid Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_BSVIE [2/2]

#define USBHS_OTGSC_BSVIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)

BSVIE - B Session Valid Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_DP [1/2]

#define USBHS_OTGSC_DP

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)

DP - Data Pulsing 0b0..The pull-up on DP is not asserted 0b1..The pull-up on DP is asserted for data pulsing during SRP

USBHS_OTGSC_DP [2/2]

#define USBHS_OTGSC_DP

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)

DP - Data Pulsing 0b0..The pull-up on DP is not asserted 0b1..The pull-up on DP is asserted for data pulsing during SRP

USBHS_OTGSC_DPIE [1/2]

#define USBHS_OTGSC_DPIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)

DPIE - Data Pulse Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_DPIE [2/2]

#define USBHS_OTGSC_DPIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)

DPIE - Data Pulse Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_DPS [1/2]

#define USBHS_OTGSC_DPS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)

DPS - Data bus Pulsing Status 0b0..No pulsing on port 0b1..Pulsing detected on port

USBHS_OTGSC_DPS [2/2]

#define USBHS_OTGSC_DPS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)

DPS - Data bus Pulsing Status 0b0..No pulsing on port 0b1..Pulsing detected on port

USBHS_OTGSC_HAAR [1/2]

#define USBHS_OTGSC_HAAR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)

HAAR - Hardware Assist Auto-Reset 0b0..Disabled. 0b1..Enable automatic reset after connect on host port.

USBHS_OTGSC_HAAR [2/2]

#define USBHS_OTGSC_HAAR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)

HAAR - Hardware Assist Auto-Reset 0b0..Disabled. 0b1..Enable automatic reset after connect on host port.

USBHS_OTGSC_HABA [1/2]

#define USBHS_OTGSC_HABA

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)

HABA - Hardware Assist B-Disconnect to A-connect 0b0..Disabled. 0b1..Enable automatic B-disconnect to A-connect sequence.

USBHS_OTGSC_HABA [2/2]

#define USBHS_OTGSC_HABA

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)

HABA - Hardware Assist B-Disconnect to A-connect 0b0..Disabled. 0b1..Enable automatic B-disconnect to A-connect sequence.

USBHS_OTGSC_ID [1/2]

#define USBHS_OTGSC_ID

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)

ID - USB ID 0b0..A device 0b1..B device

USBHS_OTGSC_ID [2/2]

#define USBHS_OTGSC_ID

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)

ID - USB ID 0b0..A device 0b1..B device

USBHS_OTGSC_IDIE [1/2]

#define USBHS_OTGSC_IDIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)

IDIE - USB ID Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_IDIE [2/2]

#define USBHS_OTGSC_IDIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)

IDIE - USB ID Interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_IDPU [1/2]

#define USBHS_OTGSC_IDPU

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)

IDPU - ID Pull-Up 0b0..Disable pull-up. ID input not sampled. 0b1..Enable pull-up

USBHS_OTGSC_IDPU [2/2]

#define USBHS_OTGSC_IDPU

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)

IDPU - ID Pull-Up 0b0..Disable pull-up. ID input not sampled. 0b1..Enable pull-up

USBHS_OTGSC_MSE [1/2]

#define USBHS_OTGSC_MSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)

MSE - 1 Milli-Second timer interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_MSE [2/2]

#define USBHS_OTGSC_MSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)

MSE - 1 Milli-Second timer interrupt Enable 0b0..Disable 0b1..Enable

USBHS_OTGSC_OT [1/2]

#define USBHS_OTGSC_OT

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)

OT - OTG Termination 0b0..Disable pull-down on DM 0b1..Enable pull-down on DM

USBHS_OTGSC_OT [2/2]

#define USBHS_OTGSC_OT

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)

OT - OTG Termination 0b0..Disable pull-down on DM 0b1..Enable pull-down on DM

USBHS_PORTSC1_CCS [1/2]

#define USBHS_PORTSC1_CCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)

CCS - Current Connect Status 0b0..No device present (host mode) or attached (device mode) 0b1..Device is present (host mode) or attached (device mode)

USBHS_PORTSC1_CCS [2/2]

#define USBHS_PORTSC1_CCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)

CCS - Current Connect Status 0b0..No device present (host mode) or attached (device mode) 0b1..Device is present (host mode) or attached (device mode)

USBHS_PORTSC1_CSC [1/2]

#define USBHS_PORTSC1_CSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)

CSC - Connect Change Status 0b0..No change 0b1..Connect status has changed

USBHS_PORTSC1_CSC [2/2]

#define USBHS_PORTSC1_CSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)

CSC - Connect Change Status 0b0..No change 0b1..Connect status has changed

USBHS_PORTSC1_FPR [1/2]

#define USBHS_PORTSC1_FPR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)

FPR - Force Port Resume 0b0..No resume (K-state) detected/driven on port 0b1..Resume detected/driven on port

USBHS_PORTSC1_FPR [2/2]

#define USBHS_PORTSC1_FPR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)

FPR - Force Port Resume 0b0..No resume (K-state) detected/driven on port 0b1..Resume detected/driven on port

USBHS_PORTSC1_HSP [1/2]

#define USBHS_PORTSC1_HSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)

HSP - High Speed Port. 0b0..FS or LS 0b1..HS

USBHS_PORTSC1_HSP [2/2]

#define USBHS_PORTSC1_HSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)

HSP - High Speed Port. 0b0..FS or LS 0b1..HS

USBHS_PORTSC1_LS [1/2]

#define USBHS_PORTSC1_LS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)

LS - Line Status 0b00..SE0 0b01..J-state 0b10..K-state 0b11..Undefined

USBHS_PORTSC1_LS [2/2]

#define USBHS_PORTSC1_LS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)

LS - Line Status 0b00..SE0 0b01..J-state 0b10..K-state 0b11..Undefined

USBHS_PORTSC1_OCA [1/2]

#define USBHS_PORTSC1_OCA

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)

OCA - Over-current active 0b0..Port not in over-current condition 0b1..Port currently in over-current condition

USBHS_PORTSC1_OCA [2/2]

#define USBHS_PORTSC1_OCA

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)

OCA - Over-current active 0b0..Port not in over-current condition 0b1..Port currently in over-current condition

USBHS_PORTSC1_OCC [1/2]

#define USBHS_PORTSC1_OCC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)

OCC - Over-Current Change 0b0..No over-current 0b1..Over-current detect

USBHS_PORTSC1_OCC [2/2]

#define USBHS_PORTSC1_OCC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)

OCC - Over-Current Change 0b0..No over-current 0b1..Over-current detect

USBHS_PORTSC1_PEC [1/2]

#define USBHS_PORTSC1_PEC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)

PEC - Port Enable/disable Change 0b0..No change 0b1..Port disabled

USBHS_PORTSC1_PEC [2/2]

#define USBHS_PORTSC1_PEC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)

PEC - Port Enable/disable Change 0b0..No change 0b1..Port disabled

USBHS_PORTSC1_PFSC [1/2]

#define USBHS_PORTSC1_PFSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)

PFSC - Port force Full-Speed Connect 0b0..Allow the port to identify itself as high speed 0b1..Force the port to only connect at full speed

USBHS_PORTSC1_PFSC [2/2]

#define USBHS_PORTSC1_PFSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)

PFSC - Port force Full-Speed Connect 0b0..Allow the port to identify itself as high speed 0b1..Force the port to only connect at full speed

USBHS_PORTSC1_PR [1/2]

#define USBHS_PORTSC1_PR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)

PR - Port Reset 0b0..Port is not in reset 0b1..Port is in reset

USBHS_PORTSC1_PR [2/2]

#define USBHS_PORTSC1_PR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)

PR - Port Reset 0b0..Port is not in reset 0b1..Port is in reset

USBHS_PORTSC1_PSPD [1/2]

#define USBHS_PORTSC1_PSPD

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)

PSPD - Port Speed 0b00..Full speed 0b01..Low speed 0b10..High speed 0b11..Undefined

USBHS_PORTSC1_PSPD [2/2]

#define USBHS_PORTSC1_PSPD

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)

PSPD - Port Speed 0b00..Full speed 0b01..Low speed 0b10..High speed 0b11..Undefined

USBHS_PORTSC1_PTC [1/2]

#define USBHS_PORTSC1_PTC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)

PTC - Port Test Control 0b0000..Not enabled 0b0001..J_STATE 0b0010..K_STATE 0b0011..SE0_NAK 0b0100..Packet 0b0101..FORCE_ENABLE_HS 0b0110..FORCE_ENABLE_FS 0b0111..FORCE_ENABLE_LS

USBHS_PORTSC1_PTC [2/2]

#define USBHS_PORTSC1_PTC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)

PTC - Port Test Control 0b0000..Not enabled 0b0001..J_STATE 0b0010..K_STATE 0b0011..SE0_NAK 0b0100..Packet 0b0101..FORCE_ENABLE_HS 0b0110..FORCE_ENABLE_FS 0b0111..FORCE_ENABLE_LS

USBHS_PORTSC1_PTS [1/2]

#define USBHS_PORTSC1_PTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)

PTS - Port Transceiver Select [1:0] 0b00..Use UTMI transceiver interface.

USBHS_PORTSC1_PTS [2/2]

#define USBHS_PORTSC1_PTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)

PTS - Port Transceiver Select [1:0] 0b00..Use UTMI transceiver interface.

USBHS_PORTSC1_SUSP [1/2]

#define USBHS_PORTSC1_SUSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)

SUSP - Suspend 0b0..Port not in suspend state 0b1..Port in suspend state

USBHS_PORTSC1_SUSP [2/2]

#define USBHS_PORTSC1_SUSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)

SUSP - Suspend 0b0..Port not in suspend state 0b1..Port in suspend state

USBHS_USB_SBUSCFG_BURSTMODE [1/2]

#define USBHS_USB_SBUSCFG_BURSTMODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USB_SBUSCFG_BURSTMODE_MASK)

BURSTMODE - Burst mode 0b000..INCR burst of unspecified length 0b001..INCR4, non-multiple transfers of INCR4 is decomposed into singles. 0b010..INCR8, non-multiple transfers of INCR8, is decomposed into INCR4 or singles. 0b011..INCR16, non-multiple transfers of INCR16, is decomposed into INCR8, INCR4 or singles. 0b100..Reserved, do not use. 0b101..INCR4, non-multiple transfers of INCR4 is decomposed into smaller unspecified length bursts. 0b110..INCR8, non-multiple transfers of INCR8 is decomposed into smaller unspecified length bursts. 0b111..INCR16, non-multiple transfers of INCR16 is decomposed into smaller unspecified length bursts.

USBHS_USB_SBUSCFG_BURSTMODE [2/2]

#define USBHS_USB_SBUSCFG_BURSTMODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USB_SBUSCFG_BURSTMODE_MASK)

BURSTMODE - Burst mode 0b000..INCR burst of unspecified length 0b001..INCR4, non-multiple transfers of INCR4 is decomposed into singles. 0b010..INCR8, non-multiple transfers of INCR8, is decomposed into INCR4 or singles. 0b011..INCR16, non-multiple transfers of INCR16, is decomposed into INCR8, INCR4 or singles. 0b100..Reserved, do not use. 0b101..INCR4, non-multiple transfers of INCR4 is decomposed into smaller unspecified length bursts. 0b110..INCR8, non-multiple transfers of INCR8 is decomposed into smaller unspecified length bursts. 0b111..INCR16, non-multiple transfers of INCR16 is decomposed into smaller unspecified length bursts.

USBHS_USBCMD_ASE [1/2]

#define USBHS_USBCMD_ASE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)

ASE - Asynchronous Schedule Enable 0b0..Do not process asynchronous schedule. 0b1..Use the ASYNCLISTADDR register to access asynchronous schedule.

USBHS_USBCMD_ASE [2/2]

#define USBHS_USBCMD_ASE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)

ASE - Asynchronous Schedule Enable 0b0..Do not process asynchronous schedule. 0b1..Use the ASYNCLISTADDR register to access asynchronous schedule.

USBHS_USBCMD_ASPE [1/2]

#define USBHS_USBCMD_ASPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)

ASPE - Asynchronous Schedule Park mode Enable 0b0..Park mode disabled 0b1..Park mode enabled

USBHS_USBCMD_ASPE [2/2]

#define USBHS_USBCMD_ASPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)

ASPE - Asynchronous Schedule Park mode Enable 0b0..Park mode disabled 0b1..Park mode enabled

USBHS_USBCMD_FS [1/2]

#define USBHS_USBCMD_FS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)

FS - Frame list Size 0b00..When FS2 = 0, the size is 1024 elements (4096 bytes). When FS2 = 1, the size is 64 elements (256 bytes). 0b01..When FS2 = 0, the size is 512 elements (2048 bytes). When FS2 = 1, the size is 32 elements (128 bytes). 0b10..When FS2 = 0, the size is 256 elements (1024 bytes). When FS2 = 1, the size is 16 elements (64 bytes). 0b11..When FS2 = 0, the size is 128 elements (512 bytes). When FS2 = 1, the size is 8 elements (32 bytes).

USBHS_USBCMD_FS [2/2]

#define USBHS_USBCMD_FS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)

FS - Frame list Size 0b00..When FS2 = 0, the size is 1024 elements (4096 bytes). When FS2 = 1, the size is 64 elements (256 bytes). 0b01..When FS2 = 0, the size is 512 elements (2048 bytes). When FS2 = 1, the size is 32 elements (128 bytes). 0b10..When FS2 = 0, the size is 256 elements (1024 bytes). When FS2 = 1, the size is 16 elements (64 bytes). 0b11..When FS2 = 0, the size is 128 elements (512 bytes). When FS2 = 1, the size is 8 elements (32 bytes).

USBHS_USBCMD_ITC [1/2]

#define USBHS_USBCMD_ITC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)

ITC - Interrupt Threshold Control 0b00000000..Immediate (no threshold) 0b00000001..1 microframe 0b00000010..2 microframes 0b00000100..4 microframes 0b00001000..8 microframes 0b00010000..16 microframes 0b00100000..32 microframes 0b01000000..64 microframes

USBHS_USBCMD_ITC [2/2]

#define USBHS_USBCMD_ITC

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)

ITC - Interrupt Threshold Control 0b00000000..Immediate (no threshold) 0b00000001..1 microframe 0b00000010..2 microframes 0b00000100..4 microframes 0b00001000..8 microframes 0b00010000..16 microframes 0b00100000..32 microframes 0b01000000..64 microframes

USBHS_USBCMD_PSE [1/2]

#define USBHS_USBCMD_PSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)

PSE - Periodic Schedule Enable 0b0..Do not process periodic schedule. 0b1..Use the PERIODICLISTBASE register to access the periodic schedule.

USBHS_USBCMD_PSE [2/2]

#define USBHS_USBCMD_PSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)

PSE - Periodic Schedule Enable 0b0..Do not process periodic schedule. 0b1..Use the PERIODICLISTBASE register to access the periodic schedule.

USBHS_USBGENCTRL_WU_IE [1/2]

#define USBHS_USBGENCTRL_WU_IE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)

WU_IE - Wakeup Interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBGENCTRL_WU_IE [2/2]

#define USBHS_USBGENCTRL_WU_IE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)

WU_IE - Wakeup Interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBGENCTRL_WU_INT_CLR [1/2]

#define USBHS_USBGENCTRL_WU_INT_CLR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)

WU_INT_CLR - Wakeup Interrupt Clear 0b0..Default, no action. 0b1..Clear the wake-up interrupt.

USBHS_USBGENCTRL_WU_INT_CLR [2/2]

#define USBHS_USBGENCTRL_WU_INT_CLR

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)

WU_INT_CLR - Wakeup Interrupt Clear 0b0..Default, no action. 0b1..Clear the wake-up interrupt.

USBHS_USBINTR_AAE [1/2]

#define USBHS_USBINTR_AAE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)

AAE - Interrupt on Async advance Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_AAE [2/2]

#define USBHS_USBINTR_AAE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)

AAE - Interrupt on Async advance Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_FRE [1/2]

#define USBHS_USBINTR_FRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)

FRE - Frame list Rollover Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_FRE [2/2]

#define USBHS_USBINTR_FRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)

FRE - Frame list Rollover Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_NAKE [1/2]

#define USBHS_USBINTR_NAKE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)

NAKE - NAK Interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_NAKE [2/2]

#define USBHS_USBINTR_NAKE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)

NAKE - NAK Interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_PCE [1/2]

#define USBHS_USBINTR_PCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)

PCE - Port Change detect Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_PCE [2/2]

#define USBHS_USBINTR_PCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)

PCE - Port Change detect Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_SEE [1/2]

#define USBHS_USBINTR_SEE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)

SEE - System Error Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_SEE [2/2]

#define USBHS_USBINTR_SEE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)

SEE - System Error Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_SLE [1/2]

#define USBHS_USBINTR_SLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)

SLE - Sleep (DC suspend) Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_SLE [2/2]

#define USBHS_USBINTR_SLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)

SLE - Sleep (DC suspend) Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_SRE [1/2]

#define USBHS_USBINTR_SRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)

SRE - SOF-Received Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_SRE [2/2]

#define USBHS_USBINTR_SRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)

SRE - SOF-Received Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_TIE0 [1/2]

#define USBHS_USBINTR_TIE0

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)

TIE0 - General purpose Timer 0 Interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_TIE0 [2/2]

#define USBHS_USBINTR_TIE0

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)

TIE0 - General purpose Timer 0 Interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_TIE1 [1/2]

#define USBHS_USBINTR_TIE1

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)

TIE1 - General purpose Timer 1 Interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_TIE1 [2/2]

#define USBHS_USBINTR_TIE1

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)

TIE1 - General purpose Timer 1 Interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_UE [1/2]

#define USBHS_USBINTR_UE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)

UE - USB interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_UE [2/2]

#define USBHS_USBINTR_UE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)

UE - USB interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_UEE [1/2]

#define USBHS_USBINTR_UEE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)

UEE - USB Error interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_UEE [2/2]

#define USBHS_USBINTR_UEE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)

UEE - USB Error interrupt Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_URE [1/2]

#define USBHS_USBINTR_URE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)

URE - USB-Reset Enable 0b0..Disabled 0b1..Enabled

USBHS_USBINTR_URE [2/2]

#define USBHS_USBINTR_URE

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)

URE - USB-Reset Enable 0b0..Disabled 0b1..Enabled

USBHS_USBMODE_CM [1/2]

#define USBHS_USBMODE_CM

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)

CM - Controller Mode 0b00..Idle (default for the USBHS module) 0b01..Reserved 0b10..Device controller 0b11..Host controller

USBHS_USBMODE_CM [2/2]

#define USBHS_USBMODE_CM

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)

CM - Controller Mode 0b00..Idle (default for the USBHS module) 0b01..Reserved 0b10..Device controller 0b11..Host controller

USBHS_USBMODE_ES [1/2]

#define USBHS_USBMODE_ES

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)

ES - Endian Select 0b0..Little endian. First byte referenced in least significant byte of 32-bit word. 0b1..Big endian. First byte referenced in most significant byte of 32-bit word.

USBHS_USBMODE_ES [2/2]

#define USBHS_USBMODE_ES

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)

ES - Endian Select 0b0..Little endian. First byte referenced in least significant byte of 32-bit word. 0b1..Big endian. First byte referenced in most significant byte of 32-bit word.

USBHS_USBMODE_SDIS [1/2]

#define USBHS_USBMODE_SDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)

SDIS - Stream DISable 0b0..Inactive 0b1..Active

USBHS_USBMODE_SDIS [2/2]

#define USBHS_USBMODE_SDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)

SDIS - Stream DISable 0b0..Inactive 0b1..Active

USBHS_USBMODE_TXHSD [1/2]

#define USBHS_USBMODE_TXHSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)

TXHSD - Tx to Tx HS Delay 0b000..10 0b001..11 0b010..12 0b011..13 0b100..14 0b101..15 0b110..16 0b111..17

USBHS_USBMODE_TXHSD [2/2]

#define USBHS_USBMODE_TXHSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)

TXHSD - Tx to Tx HS Delay 0b000..10 0b001..11 0b010..12 0b011..13 0b100..14 0b101..15 0b110..16 0b111..17

USBHS_USBSTS_AAI [1/2]

#define USBHS_USBSTS_AAI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)

AAI - Interrupt on Async Advance 0b0..No async advance interrupt 0b1..Async advance interrupt

USBHS_USBSTS_AAI [2/2]

#define USBHS_USBSTS_AAI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)

AAI - Interrupt on Async Advance 0b0..No async advance interrupt 0b1..Async advance interrupt

USBHS_USBSTS_AS [1/2]

#define USBHS_USBSTS_AS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)

AS - Asynchronous schedule Status 0b0..Disabled 0b1..Enabled

USBHS_USBSTS_AS [2/2]

#define USBHS_USBSTS_AS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)

AS - Asynchronous schedule Status 0b0..Disabled 0b1..Enabled

USBHS_USBSTS_HCH [1/2]

#define USBHS_USBSTS_HCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)

HCH - Host Controller Halted 0b0..Running 0b1..Halted

USBHS_USBSTS_HCH [2/2]

#define USBHS_USBSTS_HCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)

HCH - Host Controller Halted 0b0..Running 0b1..Halted

USBHS_USBSTS_PS [1/2]

#define USBHS_USBSTS_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)

PS - Periodic schedule Status 0b0..Disabled 0b1..Enabled

USBHS_USBSTS_PS [2/2]

#define USBHS_USBSTS_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)

PS - Periodic schedule Status 0b0..Disabled 0b1..Enabled

USBHS_USBSTS_RCL [1/2]

#define USBHS_USBSTS_RCL

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)

RCL - Reclamation 0b0..Non-empty asynchronous schedule 0b1..Empty asynchronous schedule

USBHS_USBSTS_RCL [2/2]

#define USBHS_USBSTS_RCL

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)

RCL - Reclamation 0b0..Non-empty asynchronous schedule 0b1..Empty asynchronous schedule

USBHS_USBSTS_SEI [1/2]

#define USBHS_USBSTS_SEI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)

SEI - System Error 0b0..Normal operation 0b1..Error

USBHS_USBSTS_SEI [2/2]

#define USBHS_USBSTS_SEI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)

SEI - System Error 0b0..Normal operation 0b1..Error

USBHS_USBSTS_SLI [1/2]

#define USBHS_USBSTS_SLI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)

SLI - Device-controller suspend 0b0..Active 0b1..Suspended

USBHS_USBSTS_SLI [2/2]

#define USBHS_USBSTS_SLI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)

SLI - Device-controller suspend 0b0..Active 0b1..Suspended

USBHS_USBSTS_TI0 [1/2]

#define USBHS_USBSTS_TI0

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)

TI0 - General purpose Timer 0 Interrupt 0b0..No interrupt 0b1..Interrupt occurred

USBHS_USBSTS_TI0 [2/2]

#define USBHS_USBSTS_TI0

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)

TI0 - General purpose Timer 0 Interrupt 0b0..No interrupt 0b1..Interrupt occurred

USBHS_USBSTS_TI1 [1/2]

#define USBHS_USBSTS_TI1

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)

TI1 - General purpose Timer 1 Interrupt 0b0..No interrupt 0b1..Interrupt occurred

USBHS_USBSTS_TI1 [2/2]

#define USBHS_USBSTS_TI1

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)

TI1 - General purpose Timer 1 Interrupt 0b0..No interrupt 0b1..Interrupt occurred

USBHS_USBSTS_UEI [1/2]

#define USBHS_USBSTS_UEI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)

UEI - USB Error Interrupt 0b0..No error 0b1..Error detected

USBHS_USBSTS_UEI [2/2]

#define USBHS_USBSTS_UEI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)

UEI - USB Error Interrupt 0b0..No error 0b1..Error detected

USBHS_USBSTS_URI [1/2]

#define USBHS_USBSTS_URI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)

URI - USB Reset received 0b0..No reset received 0b1..Reset received

USBHS_USBSTS_URI [2/2]

#define USBHS_USBSTS_URI

(

x

)

(((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)

URI - USB Reset received 0b0..No reset received 0b1..Reset received