SEL0 - Crossbar A Select Register 0
#define	XBARA_SEL0_SEL0_MASK (0x3FU)

#define	XBARA_SEL0_SEL0_SHIFT (0U)

#define	XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)

#define	XBARA_SEL0_SEL1_MASK (0x3F00U)

#define	XBARA_SEL0_SEL1_SHIFT (8U)

#define	XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)

SEL1 - Crossbar A Select Register 1
#define	XBARA_SEL1_SEL2_MASK (0x3FU)

#define	XBARA_SEL1_SEL2_SHIFT (0U)

#define	XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)

#define	XBARA_SEL1_SEL3_MASK (0x3F00U)

#define	XBARA_SEL1_SEL3_SHIFT (8U)

#define	XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)

SEL2 - Crossbar A Select Register 2
#define	XBARA_SEL2_SEL4_MASK (0x3FU)

#define	XBARA_SEL2_SEL4_SHIFT (0U)

#define	XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)

#define	XBARA_SEL2_SEL5_MASK (0x3F00U)

#define	XBARA_SEL2_SEL5_SHIFT (8U)

#define	XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)

SEL3 - Crossbar A Select Register 3
#define	XBARA_SEL3_SEL6_MASK (0x3FU)

#define	XBARA_SEL3_SEL6_SHIFT (0U)

#define	XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)

#define	XBARA_SEL3_SEL7_MASK (0x3F00U)

#define	XBARA_SEL3_SEL7_SHIFT (8U)

#define	XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)

SEL4 - Crossbar A Select Register 4
#define	XBARA_SEL4_SEL8_MASK (0x3FU)

#define	XBARA_SEL4_SEL8_SHIFT (0U)

#define	XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)

#define	XBARA_SEL4_SEL9_MASK (0x3F00U)

#define	XBARA_SEL4_SEL9_SHIFT (8U)

#define	XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)

SEL5 - Crossbar A Select Register 5
#define	XBARA_SEL5_SEL10_MASK (0x3FU)

#define	XBARA_SEL5_SEL10_SHIFT (0U)

#define	XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)

#define	XBARA_SEL5_SEL11_MASK (0x3F00U)

#define	XBARA_SEL5_SEL11_SHIFT (8U)

#define	XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)

SEL6 - Crossbar A Select Register 6
#define	XBARA_SEL6_SEL12_MASK (0x3FU)

#define	XBARA_SEL6_SEL12_SHIFT (0U)

#define	XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)

#define	XBARA_SEL6_SEL13_MASK (0x3F00U)

#define	XBARA_SEL6_SEL13_SHIFT (8U)

#define	XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)

SEL7 - Crossbar A Select Register 7
#define	XBARA_SEL7_SEL14_MASK (0x3FU)

#define	XBARA_SEL7_SEL14_SHIFT (0U)

#define	XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)

#define	XBARA_SEL7_SEL15_MASK (0x3F00U)

#define	XBARA_SEL7_SEL15_SHIFT (8U)

#define	XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)

SEL8 - Crossbar A Select Register 8
#define	XBARA_SEL8_SEL16_MASK (0x3FU)

#define	XBARA_SEL8_SEL16_SHIFT (0U)

#define	XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)

#define	XBARA_SEL8_SEL17_MASK (0x3F00U)

#define	XBARA_SEL8_SEL17_SHIFT (8U)

#define	XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)

SEL9 - Crossbar A Select Register 9
#define	XBARA_SEL9_SEL18_MASK (0x3FU)

#define	XBARA_SEL9_SEL18_SHIFT (0U)

#define	XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)

#define	XBARA_SEL9_SEL19_MASK (0x3F00U)

#define	XBARA_SEL9_SEL19_SHIFT (8U)

#define	XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)

SEL10 - Crossbar A Select Register 10
#define	XBARA_SEL10_SEL20_MASK (0x3FU)

#define	XBARA_SEL10_SEL20_SHIFT (0U)

#define	XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)

#define	XBARA_SEL10_SEL21_MASK (0x3F00U)

#define	XBARA_SEL10_SEL21_SHIFT (8U)

#define	XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)

SEL11 - Crossbar A Select Register 11
#define	XBARA_SEL11_SEL22_MASK (0x3FU)

#define	XBARA_SEL11_SEL22_SHIFT (0U)

#define	XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)

#define	XBARA_SEL11_SEL23_MASK (0x3F00U)

#define	XBARA_SEL11_SEL23_SHIFT (8U)

#define	XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)

SEL12 - Crossbar A Select Register 12
#define	XBARA_SEL12_SEL24_MASK (0x3FU)

#define	XBARA_SEL12_SEL24_SHIFT (0U)

#define	XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)

#define	XBARA_SEL12_SEL25_MASK (0x3F00U)

#define	XBARA_SEL12_SEL25_SHIFT (8U)

#define	XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)

SEL13 - Crossbar A Select Register 13
#define	XBARA_SEL13_SEL26_MASK (0x3FU)

#define	XBARA_SEL13_SEL26_SHIFT (0U)

#define	XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)

#define	XBARA_SEL13_SEL27_MASK (0x3F00U)

#define	XBARA_SEL13_SEL27_SHIFT (8U)

#define	XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)

SEL14 - Crossbar A Select Register 14
#define	XBARA_SEL14_SEL28_MASK (0x3FU)

#define	XBARA_SEL14_SEL28_SHIFT (0U)

#define	XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)

#define	XBARA_SEL14_SEL29_MASK (0x3F00U)

#define	XBARA_SEL14_SEL29_SHIFT (8U)

#define	XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)

SEL15 - Crossbar A Select Register 15
#define	XBARA_SEL15_SEL30_MASK (0x3FU)

#define	XBARA_SEL15_SEL30_SHIFT (0U)

#define	XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)

#define	XBARA_SEL15_SEL31_MASK (0x3F00U)

#define	XBARA_SEL15_SEL31_SHIFT (8U)

#define	XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)

SEL16 - Crossbar A Select Register 16
#define	XBARA_SEL16_SEL32_MASK (0x3FU)

#define	XBARA_SEL16_SEL32_SHIFT (0U)

#define	XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)

#define	XBARA_SEL16_SEL33_MASK (0x3F00U)

#define	XBARA_SEL16_SEL33_SHIFT (8U)

#define	XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)

SEL17 - Crossbar A Select Register 17
#define	XBARA_SEL17_SEL34_MASK (0x3FU)

#define	XBARA_SEL17_SEL34_SHIFT (0U)

#define	XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)

#define	XBARA_SEL17_SEL35_MASK (0x3F00U)

#define	XBARA_SEL17_SEL35_SHIFT (8U)

#define	XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)

SEL18 - Crossbar A Select Register 18
#define	XBARA_SEL18_SEL36_MASK (0x3FU)

#define	XBARA_SEL18_SEL36_SHIFT (0U)

#define	XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)

#define	XBARA_SEL18_SEL37_MASK (0x3F00U)

#define	XBARA_SEL18_SEL37_SHIFT (8U)

#define	XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)

SEL19 - Crossbar A Select Register 19
#define	XBARA_SEL19_SEL38_MASK (0x3FU)

#define	XBARA_SEL19_SEL38_SHIFT (0U)

#define	XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)

#define	XBARA_SEL19_SEL39_MASK (0x3F00U)

#define	XBARA_SEL19_SEL39_SHIFT (8U)

#define	XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)

SEL20 - Crossbar A Select Register 20
#define	XBARA_SEL20_SEL40_MASK (0x3FU)

#define	XBARA_SEL20_SEL40_SHIFT (0U)

#define	XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)

#define	XBARA_SEL20_SEL41_MASK (0x3F00U)

#define	XBARA_SEL20_SEL41_SHIFT (8U)

#define	XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)

SEL21 - Crossbar A Select Register 21
#define	XBARA_SEL21_SEL42_MASK (0x3FU)

#define	XBARA_SEL21_SEL42_SHIFT (0U)

#define	XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)

#define	XBARA_SEL21_SEL43_MASK (0x3F00U)

#define	XBARA_SEL21_SEL43_SHIFT (8U)

#define	XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)

SEL22 - Crossbar A Select Register 22
#define	XBARA_SEL22_SEL44_MASK (0x3FU)

#define	XBARA_SEL22_SEL44_SHIFT (0U)

#define	XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)

#define	XBARA_SEL22_SEL45_MASK (0x3F00U)

#define	XBARA_SEL22_SEL45_SHIFT (8U)

#define	XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)

SEL23 - Crossbar A Select Register 23
#define	XBARA_SEL23_SEL46_MASK (0x3FU)

#define	XBARA_SEL23_SEL46_SHIFT (0U)

#define	XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)

#define	XBARA_SEL23_SEL47_MASK (0x3F00U)

#define	XBARA_SEL23_SEL47_SHIFT (8U)

#define	XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)

SEL24 - Crossbar A Select Register 24
#define	XBARA_SEL24_SEL48_MASK (0x3FU)

#define	XBARA_SEL24_SEL48_SHIFT (0U)

#define	XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)

#define	XBARA_SEL24_SEL49_MASK (0x3F00U)

#define	XBARA_SEL24_SEL49_SHIFT (8U)

#define	XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)

SEL25 - Crossbar A Select Register 25
#define	XBARA_SEL25_SEL50_MASK (0x3FU)

#define	XBARA_SEL25_SEL50_SHIFT (0U)

#define	XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)

#define	XBARA_SEL25_SEL51_MASK (0x3F00U)

#define	XBARA_SEL25_SEL51_SHIFT (8U)

#define	XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)

SEL26 - Crossbar A Select Register 26
#define	XBARA_SEL26_SEL52_MASK (0x3FU)

#define	XBARA_SEL26_SEL52_SHIFT (0U)

#define	XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)

#define	XBARA_SEL26_SEL53_MASK (0x3F00U)

#define	XBARA_SEL26_SEL53_SHIFT (8U)

#define	XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)

SEL27 - Crossbar A Select Register 27
#define	XBARA_SEL27_SEL54_MASK (0x3FU)

#define	XBARA_SEL27_SEL54_SHIFT (0U)

#define	XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)

#define	XBARA_SEL27_SEL55_MASK (0x3F00U)

#define	XBARA_SEL27_SEL55_SHIFT (8U)

#define	XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)

SEL28 - Crossbar A Select Register 28
#define	XBARA_SEL28_SEL56_MASK (0x3FU)

#define	XBARA_SEL28_SEL56_SHIFT (0U)

#define	XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)

#define	XBARA_SEL28_SEL57_MASK (0x3F00U)

#define	XBARA_SEL28_SEL57_SHIFT (8U)

#define	XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)

SEL29 - Crossbar A Select Register 29
#define	XBARA_SEL29_SEL58_MASK (0x3FU)

#define	XBARA_SEL29_SEL58_SHIFT (0U)

#define	XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)

CTRL0 - Crossbar A Control Register 0
#define	XBARA_CTRL0_DEN0_MASK (0x1U)

#define	XBARA_CTRL0_DEN0_SHIFT (0U)

#define	XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)

#define	XBARA_CTRL0_IEN0_MASK (0x2U)

#define	XBARA_CTRL0_IEN0_SHIFT (1U)

#define	XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)

#define	XBARA_CTRL0_EDGE0_MASK (0xCU)

#define	XBARA_CTRL0_EDGE0_SHIFT (2U)

#define	XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)

#define	XBARA_CTRL0_STS0_MASK (0x10U)

#define	XBARA_CTRL0_STS0_SHIFT (4U)

#define	XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)

#define	XBARA_CTRL0_DEN1_MASK (0x100U)

#define	XBARA_CTRL0_DEN1_SHIFT (8U)

#define	XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)

#define	XBARA_CTRL0_IEN1_MASK (0x200U)

#define	XBARA_CTRL0_IEN1_SHIFT (9U)

#define	XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)

#define	XBARA_CTRL0_EDGE1_MASK (0xC00U)

#define	XBARA_CTRL0_EDGE1_SHIFT (10U)

#define	XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)

#define	XBARA_CTRL0_STS1_MASK (0x1000U)

#define	XBARA_CTRL0_STS1_SHIFT (12U)

#define	XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)

CTRL1 - Crossbar A Control Register 1
#define	XBARA_CTRL1_DEN2_MASK (0x1U)

#define	XBARA_CTRL1_DEN2_SHIFT (0U)

#define	XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)

#define	XBARA_CTRL1_IEN2_MASK (0x2U)

#define	XBARA_CTRL1_IEN2_SHIFT (1U)

#define	XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)

#define	XBARA_CTRL1_EDGE2_MASK (0xCU)

#define	XBARA_CTRL1_EDGE2_SHIFT (2U)

#define	XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)

#define	XBARA_CTRL1_STS2_MASK (0x10U)

#define	XBARA_CTRL1_STS2_SHIFT (4U)

#define	XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)

#define	XBARA_CTRL1_DEN3_MASK (0x100U)

#define	XBARA_CTRL1_DEN3_SHIFT (8U)

#define	XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)

#define	XBARA_CTRL1_IEN3_MASK (0x200U)

#define	XBARA_CTRL1_IEN3_SHIFT (9U)

#define	XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)

#define	XBARA_CTRL1_EDGE3_MASK (0xC00U)

#define	XBARA_CTRL1_EDGE3_SHIFT (10U)

#define	XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)

#define	XBARA_CTRL1_STS3_MASK (0x1000U)

#define	XBARA_CTRL1_STS3_SHIFT (12U)

#define	XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)

Macro Definition Documentation

◆ XBARA_CTRL0_DEN0

#define XBARA_CTRL0_DEN0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)

DEN0 - DMA Enable for XBAR_OUT0 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL0_DEN1

#define XBARA_CTRL0_DEN1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)

DEN1 - DMA Enable for XBAR_OUT1 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL0_EDGE0

#define XBARA_CTRL0_EDGE0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)

EDGE0 - Active edge for edge detection on XBAR_OUT0 0b00..STS0 never asserts 0b01..STS0 asserts on rising edges of XBAR_OUT0 0b10..STS0 asserts on falling edges of XBAR_OUT0 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0

◆ XBARA_CTRL0_EDGE1

#define XBARA_CTRL0_EDGE1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)

EDGE1 - Active edge for edge detection on XBAR_OUT1 0b00..STS1 never asserts 0b01..STS1 asserts on rising edges of XBAR_OUT1 0b10..STS1 asserts on falling edges of XBAR_OUT1 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1

◆ XBARA_CTRL0_IEN0

#define XBARA_CTRL0_IEN0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)

IEN0 - Interrupt Enable for XBAR_OUT0 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL0_IEN1

#define XBARA_CTRL0_IEN1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)

IEN1 - Interrupt Enable for XBAR_OUT1 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL0_STS0

#define XBARA_CTRL0_STS0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)

STS0 - Edge detection status for XBAR_OUT0 0b0..Active edge not yet detected on XBAR_OUT0 0b1..Active edge detected on XBAR_OUT0

◆ XBARA_CTRL0_STS1

#define XBARA_CTRL0_STS1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)

STS1 - Edge detection status for XBAR_OUT1 0b0..Active edge not yet detected on XBAR_OUT1 0b1..Active edge detected on XBAR_OUT1

◆ XBARA_CTRL1_DEN2

#define XBARA_CTRL1_DEN2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)

DEN2 - DMA Enable for XBAR_OUT2 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL1_DEN3

#define XBARA_CTRL1_DEN3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)

DEN3 - DMA Enable for XBAR_OUT3 0b0..DMA disabled 0b1..DMA enabled

◆ XBARA_CTRL1_EDGE2

#define XBARA_CTRL1_EDGE2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)

EDGE2 - Active edge for edge detection on XBAR_OUT2 0b00..STS2 never asserts 0b01..STS2 asserts on rising edges of XBAR_OUT2 0b10..STS2 asserts on falling edges of XBAR_OUT2 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2

◆ XBARA_CTRL1_EDGE3

#define XBARA_CTRL1_EDGE3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)

EDGE3 - Active edge for edge detection on XBAR_OUT3 0b00..STS3 never asserts 0b01..STS3 asserts on rising edges of XBAR_OUT3 0b10..STS3 asserts on falling edges of XBAR_OUT3 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3

◆ XBARA_CTRL1_IEN2

#define XBARA_CTRL1_IEN2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)

IEN2 - Interrupt Enable for XBAR_OUT2 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL1_IEN3

#define XBARA_CTRL1_IEN3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)

IEN3 - Interrupt Enable for XBAR_OUT3 0b0..Interrupt disabled 0b1..Interrupt enabled

◆ XBARA_CTRL1_STS2

#define XBARA_CTRL1_STS2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)

STS2 - Edge detection status for XBAR_OUT2 0b0..Active edge not yet detected on XBAR_OUT2 0b1..Active edge detected on XBAR_OUT2

◆ XBARA_CTRL1_STS3

#define XBARA_CTRL1_STS3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)

STS3 - Edge detection status for XBAR_OUT3 0b0..Active edge not yet detected on XBAR_OUT3 0b1..Active edge detected on XBAR_OUT3

◆ XBARA_SEL0_SEL0

#define XBARA_SEL0_SEL0 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)

SEL0 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL0_SEL1

#define XBARA_SEL0_SEL1 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)

SEL1 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL10_SEL20

#define XBARA_SEL10_SEL20 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)

SEL20 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL10_SEL21

#define XBARA_SEL10_SEL21 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)

SEL21 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL11_SEL22

#define XBARA_SEL11_SEL22 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)

SEL22 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL11_SEL23

#define XBARA_SEL11_SEL23 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)

SEL23 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL12_SEL24

#define XBARA_SEL12_SEL24 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)

SEL24 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL12_SEL25

#define XBARA_SEL12_SEL25 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)

SEL25 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL13_SEL26

#define XBARA_SEL13_SEL26 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)

SEL26 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL13_SEL27

#define XBARA_SEL13_SEL27 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)

SEL27 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL14_SEL28

#define XBARA_SEL14_SEL28 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)

SEL28 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL14_SEL29

#define XBARA_SEL14_SEL29 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)

SEL29 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL15_SEL30

#define XBARA_SEL15_SEL30 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)

SEL30 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL15_SEL31

#define XBARA_SEL15_SEL31 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)

SEL31 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL16_SEL32

#define XBARA_SEL16_SEL32 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)

SEL32 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL16_SEL33

#define XBARA_SEL16_SEL33 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)

SEL33 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL17_SEL34

#define XBARA_SEL17_SEL34 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)

SEL34 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL17_SEL35

#define XBARA_SEL17_SEL35 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)

SEL35 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL18_SEL36

#define XBARA_SEL18_SEL36 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)

SEL36 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL18_SEL37

#define XBARA_SEL18_SEL37 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)

SEL37 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL19_SEL38

#define XBARA_SEL19_SEL38 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)

SEL38 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL19_SEL39

#define XBARA_SEL19_SEL39 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)

SEL39 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL1_SEL2

#define XBARA_SEL1_SEL2 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)

SEL2 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL1_SEL3

#define XBARA_SEL1_SEL3 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)

SEL3 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL20_SEL41

#define XBARA_SEL20_SEL41 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)

SEL41 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL21_SEL42

#define XBARA_SEL21_SEL42 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)

SEL42 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL21_SEL43

#define XBARA_SEL21_SEL43 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)

SEL43 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL22_SEL44

#define XBARA_SEL22_SEL44 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)

SEL44 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL22_SEL45

#define XBARA_SEL22_SEL45 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)

SEL45 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL23_SEL46

#define XBARA_SEL23_SEL46 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)

SEL46 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL23_SEL47

#define XBARA_SEL23_SEL47 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)

SEL47 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL24_SEL48

#define XBARA_SEL24_SEL48 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)

SEL48 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL24_SEL49

#define XBARA_SEL24_SEL49 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)

SEL49 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL25_SEL50

#define XBARA_SEL25_SEL50 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)

SEL50 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL25_SEL51

#define XBARA_SEL25_SEL51 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)

SEL51 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL26_SEL52

#define XBARA_SEL26_SEL52 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)

SEL52 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL26_SEL53

#define XBARA_SEL26_SEL53 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)

SEL53 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL27_SEL54

#define XBARA_SEL27_SEL54 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)

SEL54 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL27_SEL55

#define XBARA_SEL27_SEL55 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)

SEL55 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL28_SEL56

#define XBARA_SEL28_SEL56 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)

SEL56 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL28_SEL57

#define XBARA_SEL28_SEL57 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)

SEL57 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL29_SEL58

#define XBARA_SEL29_SEL58 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)

SEL58 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL2_SEL4

#define XBARA_SEL2_SEL4 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)

SEL4 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL2_SEL5

#define XBARA_SEL2_SEL5 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)

SEL5 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL3_SEL6

#define XBARA_SEL3_SEL6 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)

SEL6 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL3_SEL7

#define XBARA_SEL3_SEL7 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)

SEL7 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL4_SEL8

#define XBARA_SEL4_SEL8 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)

SEL8 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL4_SEL9

#define XBARA_SEL4_SEL9 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)

SEL9 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL5_SEL10

#define XBARA_SEL5_SEL10 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)

SEL10 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL5_SEL11

#define XBARA_SEL5_SEL11 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)

SEL11 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL6_SEL12

#define XBARA_SEL6_SEL12 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)

SEL12 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL6_SEL13

#define XBARA_SEL6_SEL13 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)

SEL13 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL7_SEL15

#define XBARA_SEL7_SEL15 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)

SEL15 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL8_SEL16

#define XBARA_SEL8_SEL16 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)

SEL16 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL8_SEL17

#define XBARA_SEL8_SEL17 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)

SEL17 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL9_SEL18

#define XBARA_SEL9_SEL18 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)

SEL18 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

◆ XBARA_SEL9_SEL19

#define XBARA_SEL9_SEL19 ( x ) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)

SEL19 0b000000..Logic zero 0b000001..Logic one 0b000010..XB_IN2 input pin 0b000011..XB_IN3 input pin 0b000100..XB_IN4 input pin 0b000101..XB_IN5 input pin 0b000110..XB_IN6 input pin 0b000111..XB_IN7 input pin 0b001000..XB_IN8 input pin 0b001001..XB_IN9 input pin 0b001010..XB_IN10 input pin 0b001011..XB_IN11 input pin 0b001100..CMP0 Output 0b001101..CMP1 Output 0b001110..CMP2 Output 0b001111..CMP3 Output 0b010000..FTM0 all channels match trigger ORed together 0b010001..FTM0 counter init trigger 0b010010..FTM3 all channels match trigger ORed together 0b010011..FTM3 counter init trigger 0b010100..PWMA channel 0 trigger 0 0b010101..PWMA channel 0 trigger 1 0b010110..PWMA channel 1 trigger 0 0b010111..PWMA channel 1 trigger 1 0b011000..PWMA channel 2 trigger 0 0b011001..PWMA channel 2 trigger 1 0b011010..PWMA channel 3 trigger 0 0b011011..PWMA channel 3 trigger 1 0b011100..PDB0 channel 1 output trigger 0b011101..PDB0 channel 0 output trigger 0b011110..PDB1 channel 1 output trigger 0b011111..PDB1 channel 0 output trigger 0b100000..High Speed Analog-to-Digital Converter 1 conversion A complete 0b100001..High Speed Analog-to-Digital Converter 0 conversion A complete 0b100010..High Speed Analog-to-Digital Converter 1 conversion B complete 0b100011..High Speed Analog-to-Digital Converter 0 conversion B complete 0b100100..FTM1 all channels match trigger ORed together 0b100101..FTM1 counter init trigger 0b100110..DMA channel 0 done 0b100111..DMA channel 1 done 0b101000..DMA channel 6 done 0b101001..DMA channel 7 done 0b101010..PIT trigger 0 0b101011..PIT trigger 1 0b101100..Analog-to-Digital Converter 0 conversion complete 0b101101..ENC compare trigger and position match 0b101110..AOI output 0 0b101111..AOI output 1 0b110000..AOI output 2 0b110001..AOI output 3 0b110010..PIT trigger 2 0b110011..PIT trigger 3 0b110100..PWMB channel 0 trigger 0 or trigger 1 0b110101..PWMB channel 1 trigger 0 or trigger 1 0b110110..PWMB channel 2 trigger 0 or trigger 1 0b110111..PWMB channel 3 trigger 0 or trigger 1 0b111000..FTM2 all channels match trigger ORed together 0b111001..FTM2 counter init trigger

SEL0 - Crossbar A Select Register 0

SEL1 - Crossbar A Select Register 1

SEL2 - Crossbar A Select Register 2

SEL3 - Crossbar A Select Register 3

SEL4 - Crossbar A Select Register 4

SEL5 - Crossbar A Select Register 5

SEL6 - Crossbar A Select Register 6

SEL7 - Crossbar A Select Register 7

SEL8 - Crossbar A Select Register 8

SEL9 - Crossbar A Select Register 9

SEL10 - Crossbar A Select Register 10

SEL11 - Crossbar A Select Register 11

SEL12 - Crossbar A Select Register 12

SEL13 - Crossbar A Select Register 13

SEL14 - Crossbar A Select Register 14

SEL15 - Crossbar A Select Register 15

SEL16 - Crossbar A Select Register 16

SEL17 - Crossbar A Select Register 17

SEL18 - Crossbar A Select Register 18

SEL19 - Crossbar A Select Register 19

SEL20 - Crossbar A Select Register 20

SEL21 - Crossbar A Select Register 21

SEL22 - Crossbar A Select Register 22

SEL23 - Crossbar A Select Register 23

SEL24 - Crossbar A Select Register 24

SEL25 - Crossbar A Select Register 25

SEL26 - Crossbar A Select Register 26

SEL27 - Crossbar A Select Register 27

SEL28 - Crossbar A Select Register 28

SEL29 - Crossbar A Select Register 29

CTRL0 - Crossbar A Control Register 0

CTRL1 - Crossbar A Control Register 1