Edma_request

Typedefs
typedef enum _dma_request_source	dma_request_source_t
	Structure for the DMA hardware request.
typedef enum _dma_request_source	dma_request_source_t
	Structure for the DMA hardware request.
typedef enum _dma_request_source	dma_request_source_t
	Structure for the DMA hardware request.
typedef enum _dma_request_source	dma_request_source_t
	Structure for the DMA hardware request.
typedef enum _dma_request_source	dma_request_source_t
	Structure for the DMA hardware request.
typedef enum _xbar_input_signal	xbar_input_signal_t
typedef enum _xbar_output_signal	xbar_output_signal_t

Enumerations
enum	_dma_request_source {   kDmaRequestMux0Disable = 0|0x100U , kDmaRequestMux0Reserved1 = 1|0x100U , kDmaRequestMux0UART0Rx = 2|0x100U , kDmaRequestMux0UART0Tx = 3|0x100U ,   kDmaRequestMux0UART1Rx = 4|0x100U , kDmaRequestMux0UART1Tx = 5|0x100U , kDmaRequestMux0UART2Rx = 6|0x100U , kDmaRequestMux0UART2Tx = 7|0x100U ,   kDmaRequestMux0UART3Rx = 8|0x100U , kDmaRequestMux0UART3Tx = 9|0x100U , kDmaRequestMux0UART4Rx = 10|0x100U , kDmaRequestMux0UART4Tx = 11|0x100U ,   kDmaRequestMux0UART5Rx = 12|0x100U , kDmaRequestMux0UART5Tx = 13|0x100U , kDmaRequestMux0I2S0Rx = 14|0x100U , kDmaRequestMux0I2S0Tx = 15|0x100U ,   kDmaRequestMux0SPI0Rx = 16|0x100U , kDmaRequestMux0SPI0Tx = 17|0x100U , kDmaRequestMux0SPI1Rx = 18|0x100U , kDmaRequestMux0SPI1Tx = 19|0x100U ,   kDmaRequestMux0SPI2Rx = 20|0x100U , kDmaRequestMux0SPI2Tx = 21|0x100U , kDmaRequestMux0I2C0 = 22|0x100U , kDmaRequestMux0I2C1 = 23|0x100U ,   kDmaRequestMux0FTM0Channel0 = 24|0x100U , kDmaRequestMux0FTM0Channel1 = 25|0x100U , kDmaRequestMux0FTM0Channel2 = 26|0x100U , kDmaRequestMux0FTM0Channel3 = 27|0x100U ,   kDmaRequestMux0FTM0Channel4 = 28|0x100U , kDmaRequestMux0FTM0Channel5 = 29|0x100U , kDmaRequestMux0FTM0Channel6 = 30|0x100U , kDmaRequestMux0FTM0Channel7 = 31|0x100U ,   kDmaRequestMux0FTM1Channel0 = 32|0x100U , kDmaRequestMux0FTM1Channel1 = 33|0x100U , kDmaRequestMux0FTM2Channel0 = 34|0x100U , kDmaRequestMux0FTM2Channel1 = 35|0x100U ,   kDmaRequestMux0IEEE1588Timer0 = 36|0x100U , kDmaRequestMux0IEEE1588Timer1 = 37|0x100U , kDmaRequestMux0IEEE1588Timer2 = 38|0x100U , kDmaRequestMux0IEEE1588Timer3 = 39|0x100U ,   kDmaRequestMux0ADC0 = 40|0x100U , kDmaRequestMux0ADC1 = 41|0x100U , kDmaRequestMux0CMP0 = 42|0x100U , kDmaRequestMux0CMP1 = 43|0x100U ,   kDmaRequestMux0CMP2 = 44|0x100U , kDmaRequestMux0DAC0 = 45|0x100U , kDmaRequestMux0DAC1 = 46|0x100U , kDmaRequestMux0CMT = 47|0x100U ,   kDmaRequestMux0PDB0 = 48|0x100U , kDmaRequestMux0PortA = 49|0x100U , kDmaRequestMux0PortB = 50|0x100U , kDmaRequestMux0PortC = 51|0x100U ,   kDmaRequestMux0PortD = 52|0x100U , kDmaRequestMux0PortE = 53|0x100U , kDmaRequestMux0AlwaysOn54 = 54|0x100U , kDmaRequestMux0AlwaysOn55 = 55|0x100U ,   kDmaRequestMux0AlwaysOn56 = 56|0x100U , kDmaRequestMux0AlwaysOn57 = 57|0x100U , kDmaRequestMux0AlwaysOn58 = 58|0x100U , kDmaRequestMux0AlwaysOn59 = 59|0x100U ,   kDmaRequestMux0AlwaysOn60 = 60|0x100U , kDmaRequestMux0AlwaysOn61 = 61|0x100U , kDmaRequestMux0AlwaysOn62 = 62|0x100U , kDmaRequestMux0AlwaysOn63 = 63|0x100U }
	Structure for the DMA hardware request. More...
enum	_dma_request_source {   kDmaRequestMux0Disable = 0|0x100U , kDmaRequestMux0Reserved1 = 1|0x100U , kDmaRequestMux0UART0Rx = 2|0x100U , kDmaRequestMux0UART0Tx = 3|0x100U ,   kDmaRequestMux0UART1Rx = 4|0x100U , kDmaRequestMux0UART1Tx = 5|0x100U , kDmaRequestMux0UART2Rx = 6|0x100U , kDmaRequestMux0UART2Tx = 7|0x100U ,   kDmaRequestMux0UART3Rx = 8|0x100U , kDmaRequestMux0UART3Tx = 9|0x100U , kDmaRequestMux0UART4 = 10|0x100U , kDmaRequestMux0UART5 = 11|0x100U ,   kDmaRequestMux0I2S0Rx = 12|0x100U , kDmaRequestMux0I2S0Tx = 13|0x100U , kDmaRequestMux0SPI0Rx = 14|0x100U , kDmaRequestMux0SPI0Tx = 15|0x100U ,   kDmaRequestMux0SPI1 = 16|0x100U , kDmaRequestMux0SPI2 = 17|0x100U , kDmaRequestMux0I2C0 = 18|0x100U , kDmaRequestMux0I2C1I2C2 = 19|0x100U ,   kDmaRequestMux0I2C1 = 19|0x100U , kDmaRequestMux0I2C2 = 19|0x100U , kDmaRequestMux0FTM0Channel0 = 20|0x100U , kDmaRequestMux0FTM0Channel1 = 21|0x100U ,   kDmaRequestMux0FTM0Channel2 = 22|0x100U , kDmaRequestMux0FTM0Channel3 = 23|0x100U , kDmaRequestMux0FTM0Channel4 = 24|0x100U , kDmaRequestMux0FTM0Channel5 = 25|0x100U ,   kDmaRequestMux0FTM0Channel6 = 26|0x100U , kDmaRequestMux0FTM0Channel7 = 27|0x100U , kDmaRequestMux0FTM1Channel0 = 28|0x100U , kDmaRequestMux0FTM1Channel1 = 29|0x100U ,   kDmaRequestMux0FTM2Channel0 = 30|0x100U , kDmaRequestMux0FTM2Channel1 = 31|0x100U , kDmaRequestMux0FTM3Channel0 = 32|0x100U , kDmaRequestMux0FTM3Channel1 = 33|0x100U ,   kDmaRequestMux0FTM3Channel2 = 34|0x100U , kDmaRequestMux0FTM3Channel3 = 35|0x100U , kDmaRequestMux0FTM3Channel4 = 36|0x100U , kDmaRequestMux0FTM3Channel5 = 37|0x100U ,   kDmaRequestMux0FTM3Channel6 = 38|0x100U , kDmaRequestMux0FTM3Channel7 = 39|0x100U , kDmaRequestMux0ADC0 = 40|0x100U , kDmaRequestMux0ADC1 = 41|0x100U ,   kDmaRequestMux0CMP0 = 42|0x100U , kDmaRequestMux0CMP1 = 43|0x100U , kDmaRequestMux0CMP2 = 44|0x100U , kDmaRequestMux0DAC0 = 45|0x100U ,   kDmaRequestMux0DAC1 = 46|0x100U , kDmaRequestMux0CMT = 47|0x100U , kDmaRequestMux0PDB = 48|0x100U , kDmaRequestMux0PortA = 49|0x100U ,   kDmaRequestMux0PortB = 50|0x100U , kDmaRequestMux0PortC = 51|0x100U , kDmaRequestMux0PortD = 52|0x100U , kDmaRequestMux0PortE = 53|0x100U ,   kDmaRequestMux0IEEE1588Timer0 = 54|0x100U , kDmaRequestMux0IEEE1588Timer1 = 55|0x100U , kDmaRequestMux0IEEE1588Timer2 = 56|0x100U , kDmaRequestMux0IEEE1588Timer3 = 57|0x100U ,   kDmaRequestMux0AlwaysOn58 = 58|0x100U , kDmaRequestMux0AlwaysOn59 = 59|0x100U , kDmaRequestMux0AlwaysOn60 = 60|0x100U , kDmaRequestMux0AlwaysOn61 = 61|0x100U ,   kDmaRequestMux0AlwaysOn62 = 62|0x100U , kDmaRequestMux0AlwaysOn63 = 63|0x100U }
	Structure for the DMA hardware request. More...
enum	_dma_request_source {   kDmaRequestMux0Disable = 0|0x100U , kDmaRequestMux0TSI0 = 1|0x100U , kDmaRequestMux0UART0Rx = 2|0x100U , kDmaRequestMux0UART0Tx = 3|0x100U ,   kDmaRequestMux0UART1Rx = 4|0x100U , kDmaRequestMux0UART1Tx = 5|0x100U , kDmaRequestMux0UART2Rx = 6|0x100U , kDmaRequestMux0UART2Tx = 7|0x100U ,   kDmaRequestMux0UART3Rx = 8|0x100U , kDmaRequestMux0UART3Tx = 9|0x100U , kDmaRequestMux0UART4 = 10|0x100U , kDmaRequestMux0Reserved11 = 11|0x100U ,   kDmaRequestMux0I2S0Rx = 12|0x100U , kDmaRequestMux0I2S0Tx = 13|0x100U , kDmaRequestMux0SPI0Rx = 14|0x100U , kDmaRequestMux0SPI0Tx = 15|0x100U ,   kDmaRequestMux0SPI1Rx = 16|0x100U , kDmaRequestMux0SPI1Tx = 17|0x100U , kDmaRequestMux0I2C0I2C3 = 18|0x100U , kDmaRequestMux0I2C0 = 18|0x100U ,   kDmaRequestMux0I2C3 = 18|0x100U , kDmaRequestMux0I2C1I2C2 = 19|0x100U , kDmaRequestMux0I2C1 = 19|0x100U , kDmaRequestMux0I2C2 = 19|0x100U ,   kDmaRequestMux0FTM0Channel0 = 20|0x100U , kDmaRequestMux0FTM0Channel1 = 21|0x100U , kDmaRequestMux0FTM0Channel2 = 22|0x100U , kDmaRequestMux0FTM0Channel3 = 23|0x100U ,   kDmaRequestMux0FTM0Channel4 = 24|0x100U , kDmaRequestMux0FTM0Channel5 = 25|0x100U , kDmaRequestMux0FTM0Channel6 = 26|0x100U , kDmaRequestMux0FTM0Channel7 = 27|0x100U ,   kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U , kDmaRequestMux0FTM1Channel0 = 28|0x100U , kDmaRequestMux0TPM1Channel0 = 28|0x100U , kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U ,   kDmaRequestMux0FTM1Channel1 = 29|0x100U , kDmaRequestMux0TPM1Channel1 = 29|0x100U , kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U , kDmaRequestMux0FTM2Channel0 = 30|0x100U ,   kDmaRequestMux0TPM2Channel0 = 30|0x100U , kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U , kDmaRequestMux0FTM2Channel1 = 31|0x100U , kDmaRequestMux0TPM2Channel1 = 31|0x100U ,   kDmaRequestMux0FTM3Channel0 = 32|0x100U , kDmaRequestMux0FTM3Channel1 = 33|0x100U , kDmaRequestMux0FTM3Channel2 = 34|0x100U , kDmaRequestMux0FTM3Channel3 = 35|0x100U ,   kDmaRequestMux0FTM3Channel4 = 36|0x100U , kDmaRequestMux0FTM3Channel5 = 37|0x100U , kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U , kDmaRequestMux0FTM3Channel6 = 38|0x100U ,   kDmaRequestMux0SPI2Rx = 38|0x100U , kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U , kDmaRequestMux0FTM3Channel7 = 39|0x100U , kDmaRequestMux0SPI2Tx = 39|0x100U ,   kDmaRequestMux0ADC0 = 40|0x100U , kDmaRequestMux0ADC1 = 41|0x100U , kDmaRequestMux0CMP0 = 42|0x100U , kDmaRequestMux0CMP1 = 43|0x100U ,   kDmaRequestMux0CMP2CMP3 = 44|0x100U , kDmaRequestMux0CMP2 = 44|0x100U , kDmaRequestMux0CMP3 = 44|0x100U , kDmaRequestMux0DAC0 = 45|0x100U ,   kDmaRequestMux0DAC1 = 46|0x100U , kDmaRequestMux0CMT = 47|0x100U , kDmaRequestMux0PDB = 48|0x100U , kDmaRequestMux0PortA = 49|0x100U ,   kDmaRequestMux0PortB = 50|0x100U , kDmaRequestMux0PortC = 51|0x100U , kDmaRequestMux0PortD = 52|0x100U , kDmaRequestMux0PortE = 53|0x100U ,   kDmaRequestMux0IEEE1588Timer0 = 54|0x100U , kDmaRequestMux0IEEE1588Timer1TPM1Overflow = 55|0x100U , kDmaRequestMux0IEEE1588Timer1 = 55|0x100U , kDmaRequestMux0TPM1Overflow = 55|0x100U ,   kDmaRequestMux0IEEE1588Timer2TPM2Overflow = 56|0x100U , kDmaRequestMux0IEEE1588Timer2 = 56|0x100U , kDmaRequestMux0TPM2Overflow = 56|0x100U , kDmaRequestMux0IEEE1588Timer3 = 57|0x100U ,   kDmaRequestMux0LPUART0Rx = 58|0x100U , kDmaRequestMux0LPUART0Tx = 59|0x100U , kDmaRequestMux0AlwaysOn60 = 60|0x100U , kDmaRequestMux0AlwaysOn61 = 61|0x100U ,   kDmaRequestMux0AlwaysOn62 = 62|0x100U , kDmaRequestMux0AlwaysOn63 = 63|0x100U }
	Structure for the DMA hardware request. More...
enum	_dma_request_source {   kDmaRequestMux0Disable = 0|0x100U , kDmaRequestMux0TSI0 = 1|0x100U , kDmaRequestMux0UART0Rx = 2|0x100U , kDmaRequestMux0UART0Tx = 3|0x100U ,   kDmaRequestMux0UART1Rx = 4|0x100U , kDmaRequestMux0UART1Tx = 5|0x100U , kDmaRequestMux0UART2Rx = 6|0x100U , kDmaRequestMux0UART2Tx = 7|0x100U ,   kDmaRequestMux0UART3Rx = 8|0x100U , kDmaRequestMux0UART3Tx = 9|0x100U , kDmaRequestMux0UART4 = 10|0x100U , kDmaRequestMux0Reserved11 = 11|0x100U ,   kDmaRequestMux0I2S0Rx = 12|0x100U , kDmaRequestMux0I2S0Tx = 13|0x100U , kDmaRequestMux0SPI0Rx = 14|0x100U , kDmaRequestMux0SPI0Tx = 15|0x100U ,   kDmaRequestMux0SPI1Rx = 16|0x100U , kDmaRequestMux0SPI1Tx = 17|0x100U , kDmaRequestMux0I2C0I2C3 = 18|0x100U , kDmaRequestMux0I2C0 = 18|0x100U ,   kDmaRequestMux0I2C3 = 18|0x100U , kDmaRequestMux0I2C1I2C2 = 19|0x100U , kDmaRequestMux0I2C1 = 19|0x100U , kDmaRequestMux0I2C2 = 19|0x100U ,   kDmaRequestMux0FTM0Channel0 = 20|0x100U , kDmaRequestMux0FTM0Channel1 = 21|0x100U , kDmaRequestMux0FTM0Channel2 = 22|0x100U , kDmaRequestMux0FTM0Channel3 = 23|0x100U ,   kDmaRequestMux0FTM0Channel4 = 24|0x100U , kDmaRequestMux0FTM0Channel5 = 25|0x100U , kDmaRequestMux0FTM0Channel6 = 26|0x100U , kDmaRequestMux0FTM0Channel7 = 27|0x100U ,   kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U , kDmaRequestMux0FTM1Channel0 = 28|0x100U , kDmaRequestMux0TPM1Channel0 = 28|0x100U , kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U ,   kDmaRequestMux0FTM1Channel1 = 29|0x100U , kDmaRequestMux0TPM1Channel1 = 29|0x100U , kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U , kDmaRequestMux0FTM2Channel0 = 30|0x100U ,   kDmaRequestMux0TPM2Channel0 = 30|0x100U , kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U , kDmaRequestMux0FTM2Channel1 = 31|0x100U , kDmaRequestMux0TPM2Channel1 = 31|0x100U ,   kDmaRequestMux0FTM3Channel0 = 32|0x100U , kDmaRequestMux0FTM3Channel1 = 33|0x100U , kDmaRequestMux0FTM3Channel2 = 34|0x100U , kDmaRequestMux0FTM3Channel3 = 35|0x100U ,   kDmaRequestMux0FTM3Channel4 = 36|0x100U , kDmaRequestMux0FTM3Channel5 = 37|0x100U , kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U , kDmaRequestMux0FTM3Channel6 = 38|0x100U ,   kDmaRequestMux0SPI2Rx = 38|0x100U , kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U , kDmaRequestMux0FTM3Channel7 = 39|0x100U , kDmaRequestMux0SPI2Tx = 39|0x100U ,   kDmaRequestMux0ADC0 = 40|0x100U , kDmaRequestMux0ADC1 = 41|0x100U , kDmaRequestMux0CMP0 = 42|0x100U , kDmaRequestMux0CMP1 = 43|0x100U ,   kDmaRequestMux0CMP2CMP3 = 44|0x100U , kDmaRequestMux0CMP2 = 44|0x100U , kDmaRequestMux0CMP3 = 44|0x100U , kDmaRequestMux0DAC0 = 45|0x100U ,   kDmaRequestMux0DAC1 = 46|0x100U , kDmaRequestMux0CMT = 47|0x100U , kDmaRequestMux0PDB = 48|0x100U , kDmaRequestMux0PortA = 49|0x100U ,   kDmaRequestMux0PortB = 50|0x100U , kDmaRequestMux0PortC = 51|0x100U , kDmaRequestMux0PortD = 52|0x100U , kDmaRequestMux0PortE = 53|0x100U ,   kDmaRequestMux0IEEE1588Timer0 = 54|0x100U , kDmaRequestMux0IEEE1588Timer1TPM1Overflow = 55|0x100U , kDmaRequestMux0IEEE1588Timer1 = 55|0x100U , kDmaRequestMux0TPM1Overflow = 55|0x100U ,   kDmaRequestMux0IEEE1588Timer2TPM2Overflow = 56|0x100U , kDmaRequestMux0IEEE1588Timer2 = 56|0x100U , kDmaRequestMux0TPM2Overflow = 56|0x100U , kDmaRequestMux0IEEE1588Timer3 = 57|0x100U ,   kDmaRequestMux0LPUART0Rx = 58|0x100U , kDmaRequestMux0LPUART0Tx = 59|0x100U , kDmaRequestMux0AlwaysOn60 = 60|0x100U , kDmaRequestMux0AlwaysOn61 = 61|0x100U ,   kDmaRequestMux0AlwaysOn62 = 62|0x100U , kDmaRequestMux0AlwaysOn63 = 63|0x100U }
	Structure for the DMA hardware request. More...
enum	_dma_request_source {   kDmaRequestMux0Disable = 0|0x100U , kDmaRequestMux0Reserved1 = 1|0x100U , kDmaRequestMux0UART0Rx = 2|0x100U , kDmaRequestMux0UART0Tx = 3|0x100U ,   kDmaRequestMux0UART1Rx = 4|0x100U , kDmaRequestMux0UART1Tx = 5|0x100U , kDmaRequestMux0PWM0WR0 = 6|0x100U , kDmaRequestMux0PWM0WR1 = 7|0x100U ,   kDmaRequestMux0PWM0WR2 = 8|0x100U , kDmaRequestMux0PWM0WR3 = 9|0x100U , kDmaRequestMux0PWM0CP0 = 10|0x100U , kDmaRequestMux0PWM0CP1 = 11|0x100U ,   kDmaRequestMux0PWM0CP2 = 12|0x100U , kDmaRequestMux0PWM0CP3 = 13|0x100U , kDmaRequestMux0CAN0 = 14|0x100U , kDmaRequestMux0CAN1 = 15|0x100U ,   kDmaRequestMux0SPI0Rx = 16|0x100U , kDmaRequestMux0SPI0Tx = 17|0x100U , kDmaRequestMux0XBARAOUT0 = 18|0x100U , kDmaRequestMux0XBARAOUT1 = 19|0x100U ,   kDmaRequestMux0XBARAOUT2 = 20|0x100U , kDmaRequestMux0XBARAOUT3 = 21|0x100U , kDmaRequestMux0I2C0 = 22|0x100U , kDmaRequestMux0Reserved23 = 23|0x100U ,   kDmaRequestMux0FTM0Channel0 = 24|0x100U , kDmaRequestMux0FTM0Channel1 = 25|0x100U , kDmaRequestMux0FTM0Channel2 = 26|0x100U , kDmaRequestMux0FTM0Channel3 = 27|0x100U ,   kDmaRequestMux0FTM0Channel4 = 28|0x100U , kDmaRequestMux0FTM0Channel5 = 29|0x100U , kDmaRequestMux0FTM0Channel6 = 30|0x100U , kDmaRequestMux0FTM0Channel7 = 31|0x100U ,   kDmaRequestMux0FTM1Channel0 = 32|0x100U , kDmaRequestMux0FTM1Channel1 = 33|0x100U , kDmaRequestMux0CMP3 = 34|0x100U , kDmaRequestMux0Reserved35 = 35|0x100U ,   kDmaRequestMux0FTM3Channel0 = 36|0x100U , kDmaRequestMux0FTM3Channel1 = 37|0x100U , kDmaRequestMux0FTM3Channel2 = 38|0x100U , kDmaRequestMux0FTM3Channel3 = 39|0x100U ,   kDmaRequestMux0HSADC0A = 40|0x100U , kDmaRequestMux0HSADC0B = 41|0x100U , kDmaRequestMux0CMP0 = 42|0x100U , kDmaRequestMux0CMP1 = 43|0x100U ,   kDmaRequestMux0CMP2 = 44|0x100U , kDmaRequestMux0DAC0 = 45|0x100U , kDmaRequestMux0Reserved46 = 46|0x100U , kDmaRequestMux0PDB1 = 47|0x100U ,   kDmaRequestMux0PDB0 = 48|0x100U , kDmaRequestMux0PortA = 49|0x100U , kDmaRequestMux0PortB = 50|0x100U , kDmaRequestMux0PortC = 51|0x100U ,   kDmaRequestMux0PortD = 52|0x100U , kDmaRequestMux0PortE = 53|0x100U , kDmaRequestMux0FTM3Channel4 = 54|0x100U , kDmaRequestMux0FTM3Channel5 = 55|0x100U ,   kDmaRequestMux0FTM3Channel6 = 56|0x100U , kDmaRequestMux0FTM3Channel7 = 57|0x100U , kDmaRequestMux0Reserved58 = 58|0x100U , kDmaRequestMux0Reserved59 = 59|0x100U ,   kDmaRequestMux0AlwaysOn60 = 60|0x100U , kDmaRequestMux0AlwaysOn61 = 61|0x100U , kDmaRequestMux0AlwaysOn62 = 62|0x100U , kDmaRequestMux0AlwaysOn63 = 63|0x100U ,   kDmaRequestMux0Group1Disable = 0|0x200U , kDmaRequestMux0Group1Reserved1 = 1|0x200U , kDmaRequestMux0Group1UART2Rx = 2|0x200U , kDmaRequestMux0Group1UART2Tx = 3|0x200U ,   kDmaRequestMux0Group1UART3Rx = 4|0x200U , kDmaRequestMux0Group1UART3Tx = 5|0x200U , kDmaRequestMux0Group1PWM1WR0 = 6|0x200U , kDmaRequestMux0Group1PWM1WR1 = 7|0x200U ,   kDmaRequestMux0Group1PWM1WR2 = 8|0x200U , kDmaRequestMux0Group1PWM1WR3 = 9|0x200U , kDmaRequestMux0Group1PWM1CP0 = 10|0x200U , kDmaRequestMux0Group1PWM1CP1 = 11|0x200U ,   kDmaRequestMux0Group1PWM1CP2 = 12|0x200U , kDmaRequestMux0Group1PWM1CP3 = 13|0x200U , kDmaRequestMux0Group1CAN2 = 14|0x200U , kDmaRequestMux0Group1Reserved15 = 15|0x200U ,   kDmaRequestMux0Group1SPI1Rx = 16|0x200U , kDmaRequestMux0Group1SPI1Tx = 17|0x200U , kDmaRequestMux0Group1Reserved18 = 18|0x200U , kDmaRequestMux0Group1Reserved19 = 19|0x200U ,   kDmaRequestMux0Group1Reserved20 = 20|0x200U , kDmaRequestMux0Group1Reserved21 = 21|0x200U , kDmaRequestMux0Group1I2C1 = 22|0x200U , kDmaRequestMux0Group1Reserved23 = 23|0x200U ,   kDmaRequestMux0Group1Reserved24 = 24|0x200U , kDmaRequestMux0Group1Reserved25 = 25|0x200U , kDmaRequestMux0Group1Reserved26 = 26|0x200U , kDmaRequestMux0Group1Reserved27 = 27|0x200U ,   kDmaRequestMux0Group1Reserved28 = 28|0x200U , kDmaRequestMux0Group1Reserved29 = 29|0x200U , kDmaRequestMux0Group1Reserved30 = 30|0x200U , kDmaRequestMux0Group1Reserved31 = 31|0x200U ,   kDmaRequestMux0Group1FTM2Channel0 = 32|0x200U , kDmaRequestMux0Group1FTM2Channel1 = 33|0x200U , kDmaRequestMux0Group1SPI2Rx = 34|0x200U , kDmaRequestMux0Group1SPI2Tx = 35|0x200U ,   kDmaRequestMux0Group1IEEE1588Timer0 = 36|0x200U , kDmaRequestMux0Group1IEEE1588Timer1 = 37|0x200U , kDmaRequestMux0Group1IEEE1588Timer2 = 38|0x200U , kDmaRequestMux0Group1IEEE1588Timer3 = 39|0x200U ,   kDmaRequestMux0Group1HSADC1A = 40|0x200U , kDmaRequestMux0Group1HSADC1B = 41|0x200U , kDmaRequestMux0Group1Reserved42 = 42|0x200U , kDmaRequestMux0Group1Reserved43 = 43|0x200U ,   kDmaRequestMux0Group1Reserved44 = 44|0x200U , kDmaRequestMux0Group1ADC0 = 45|0x200U , kDmaRequestMux0Group1Reserved46 = 46|0x200U , kDmaRequestMux0Group1Reserved47 = 47|0x200U ,   kDmaRequestMux0Group1Reserved48 = 48|0x200U , kDmaRequestMux0Group1Reserved49 = 49|0x200U , kDmaRequestMux0Group1Reserved50 = 50|0x200U , kDmaRequestMux0Group1Reserved51 = 51|0x200U ,   kDmaRequestMux0Group1Reserved52 = 52|0x200U , kDmaRequestMux0Group1Reserved53 = 53|0x200U , kDmaRequestMux0Group1UART4Rx = 54|0x200U , kDmaRequestMux0Group1UART4Tx = 55|0x200U ,   kDmaRequestMux0Group1UART5Rx = 56|0x200U , kDmaRequestMux0Group1UART5Tx = 57|0x200U , kDmaRequestMux0Group1Reserved58 = 58|0x200U , kDmaRequestMux0Group1Reserved59 = 59|0x200U ,   kDmaRequestMux0Group1AlwaysOn60 = 60|0x200U , kDmaRequestMux0Group1AlwaysOn61 = 61|0x200U , kDmaRequestMux0Group1AlwaysOn62 = 62|0x200U , kDmaRequestMux0Group1AlwaysOn63 = 63|0x200U }
	Structure for the DMA hardware request. More...
enum	_xbar_input_signal {   kXBARA_InputVss = 0|0x100U , kXBARA_InputVdd = 1|0x100U , kXBARA_InputXbarIn2 = 2|0x100U , kXBARA_InputXbarIn3 = 3|0x100U ,   kXBARA_InputXbarIn4 = 4|0x100U , kXBARA_InputXbarIn5 = 5|0x100U , kXBARA_InputXbarIn6 = 6|0x100U , kXBARA_InputXbarIn7 = 7|0x100U ,   kXBARA_InputXbarIn8 = 8|0x100U , kXBARA_InputXbarIn9 = 9|0x100U , kXBARA_InputXbarIn10 = 10|0x100U , kXBARA_InputXbarIn11 = 11|0x100U ,   kXBARA_InputCmp0Output = 12|0x100U , kXBARA_InputCmp1Output = 13|0x100U , kXBARA_InputCmp2Output = 14|0x100U , kXBARA_InputCmp3Output = 15|0x100U ,   kXBARA_InputFtm0Match = 16|0x100U , kXBARA_InputFtm0Extrig = 17|0x100U , kXBARA_InputFtm3Match = 18|0x100U , kXBARA_InputFtm3Extrig = 19|0x100U ,   kXBARA_InputPwm0Ch0Trg0 = 20|0x100U , kXBARA_InputPwm0Ch0Trg1 = 21|0x100U , kXBARA_InputPwm0Ch1Trg0 = 22|0x100U , kXBARA_InputPwm0Ch1Trg1 = 23|0x100U ,   kXBARA_InputPwm0Ch2Trg0 = 24|0x100U , kXBARA_InputPwm0Ch2Trg1 = 25|0x100U , kXBARA_InputPwm0Ch3Trg0 = 26|0x100U , kXBARA_InputPwm0Ch3Trg1 = 27|0x100U ,   kXBARA_InputPdb0Ch1Output = 28|0x100U , kXBARA_InputPdb0Ch0Output = 29|0x100U , kXBARA_InputPdb1Ch1Output = 30|0x100U , kXBARA_InputPdb1Ch0Output = 31|0x100U ,   kXBARA_InputHsadc1Cca = 32|0x100U , kXBARA_InputHsadc0Cca = 33|0x100U , kXBARA_InputHsadc1Ccb = 34|0x100U , kXBARA_InputHsadc0Ccb = 35|0x100U ,   kXBARA_InputFtm1Match = 36|0x100U , kXBARA_InputFtm1Extrig = 37|0x100U , kXBARA_InputDmaCh0Done = 38|0x100U , kXBARA_InputDmaCh1Done = 39|0x100U ,   kXBARA_InputDmaCh6Done = 40|0x100U , kXBARA_InputDmaCh7Done = 41|0x100U , kXBARA_InputPitTrigger0 = 42|0x100U , kXBARA_InputPitTrigger1 = 43|0x100U ,   kXBARA_InputAdc0Coco = 44|0x100U , kXBARA_InputEnc0CmpPosMatch = 45|0x100U , kXBARA_InputAndOrInvert0 = 46|0x100U , kXBARA_InputAndOrInvert1 = 47|0x100U ,   kXBARA_InputAndOrInvert2 = 48|0x100U , kXBARA_InputAndOrInvert3 = 49|0x100U , kXBARA_InputPitTrigger2 = 50|0x100U , kXBARA_InputPitTrigger3 = 51|0x100U ,   kXBARA_InputPwm1Ch0Trg0OrTrg1 = 52|0x100U , kXBARA_InputPwm1Ch1Trg0OrTrg1 = 53|0x100U , kXBARA_InputPwm1Ch2Trg0OrTrg1 = 54|0x100U , kXBARA_InputPwm1Ch3Trg0OrTrg1 = 55|0x100U ,   kXBARA_InputFtm2Match = 56|0x100U , kXBARA_InputFtm2Extrig = 57|0x100U , kXBARB_InputCmp0Output = 0|0x200U , kXBARB_InputCmp1Output = 1|0x200U ,   kXBARB_InputCmp2Output = 2|0x200U , kXBARB_InputCmp3Output = 3|0x200U , kXBARB_InputFtm0Match = 4|0x200U , kXBARB_InputFtm0Extrig = 5|0x200U ,   kXBARB_InputFtm3Match = 6|0x200U , kXBARB_InputFtm3Extrig = 7|0x200U , kXBARB_InputPwm0Ch0Trg0 = 8|0x200U , kXBARB_InputPwm0Ch1Trg0 = 9|0x200U ,   kXBARB_InputPwm0Ch2Trg0 = 10|0x200U , kXBARB_InputPwm0Ch3Trg0 = 11|0x200U , kXBARB_InputPdb0Ch0Output = 12|0x200U , kXBARB_InputHsadc0Cca = 13|0x200U ,   kXBARB_InputXbarIn2 = 14|0x200U , kXBARB_InputXbarIn3 = 15|0x200U , kXBARB_InputFtm1Match = 16|0x200U , kXBARB_InputFtm1Extrig = 17|0x200U ,   kXBARB_InputDmaCh0Done = 18|0x200U , kXBARB_InputDmaCh1Done = 19|0x200U , kXBARB_InputXbarIn10 = 20|0x200U , kXBARB_InputXbarIn11 = 21|0x200U ,   kXBARB_InputDmaCh6Done = 22|0x200U , kXBARB_InputDmaCh7Done = 23|0x200U , kXBARB_InputPitTrigger0 = 24|0x200U , kXBARB_InputPitTrigger1 = 25|0x200U ,   kXBARB_InputPdb1Ch0Output = 26|0x200U , kXBARB_InputHsadc0Ccb = 27|0x200U , kXBARB_InputPwm1Ch0Trg0OrTrg1 = 28|0x200U , kXBARB_InputPwm1Ch1Trg0OrTrg1 = 29|0x200U ,   kXBARB_InputPwm1Ch2Trg0OrTrg1 = 30|0x200U , kXBARB_InputPwm1Ch3Trg0OrTrg1 = 31|0x200U , kXBARB_InputFtm2Match = 32|0x200U , kXBARB_InputFtm2Extrig = 33|0x200U ,   kXBARB_InputPdb0Ch1Output = 34|0x200U , kXBARB_InputPdb1Ch1Output = 35|0x200U , kXBARB_InputHsadc1Cca = 36|0x200U , kXBARB_InputHsadc1Ccb = 37|0x200U ,   kXBARB_InputAdc0Coco = 38|0x200U }
enum	_xbar_output_signal {   kXBARA_OutputDmamux18 = 0|0x100U , kXBARA_OutputDmamux19 = 1|0x100U , kXBARA_OutputDmamux20 = 2|0x100U , kXBARA_OutputDmamux21 = 3|0x100U ,   kXBARA_OutputXbOut4 = 4|0x100U , kXBARA_OutputXbOut5 = 5|0x100U , kXBARA_OutputXbOut6 = 6|0x100U , kXBARA_OutputXbOut7 = 7|0x100U ,   kXBARA_OutputXbOut8 = 8|0x100U , kXBARA_OutputXbOut9 = 9|0x100U , kXBARA_OutputXbOut10 = 10|0x100U , kXBARA_OutputXbOut11 = 11|0x100U ,   kXBARA_OutputHsadc0ATrig = 12|0x100U , kXBARA_OutputHsadc0BTrig = 13|0x100U , kXBARA_OutputRESERVED14 = 14|0x100U , kXBARA_OutputDac12bSync = 15|0x100U ,   kXBARA_OutputCmp0 = 16|0x100U , kXBARA_OutputCmp1 = 17|0x100U , kXBARA_OutputCmp2 = 18|0x100U , kXBARA_OutputCmp3 = 19|0x100U ,   kXBARA_OutputPwmCh0ExtA = 20|0x100U , kXBARA_OutputPwmCh1ExtA = 21|0x100U , kXBARA_OutputPwmCh2ExtA = 22|0x100U , kXBARA_OutputPwmCh3ExtA = 23|0x100U ,   kXBARA_OutputPwm0Ch0ExtSync = 24|0x100U , kXBARA_OutputPwm0Ch1ExtSync = 25|0x100U , kXBARA_OutputPwm0Ch2ExtSync = 26|0x100U , kXBARA_OutputPwm0Ch3ExtSync = 27|0x100U ,   kXBARA_OutputPwmExtClk = 28|0x100U , kXBARA_OutputPwm0Fault0 = 29|0x100U , kXBARA_OutputPwm0Fault1 = 30|0x100U , kXBARA_OutputPwm0Fault2 = 31|0x100U ,   kXBARA_OutputPwm0Fault3 = 32|0x100U , kXBARA_OutputPwm0Force = 33|0x100U , kXBARA_OutputFtm0Trig2 = 34|0x100U , kXBARA_OutputFtm1Trig2 = 35|0x100U ,   kXBARA_OutputFtm2Trig2 = 36|0x100U , kXBARA_OutputFtm3Trig2 = 37|0x100U , kXBARA_OutputPdb0InCh12 = 38|0x100U , kXBARA_OutputAdc0Hdwt = 39|0x100U ,   kXBARA_OutputRESERVED40 = 40|0x100U , kXBARA_OutputPdb1InCh12 = 41|0x100U , kXBARA_OutputHsadc1ATrig = 42|0x100U , kXBARA_OutputHsadc1BTrig = 43|0x100U ,   kXBARA_OutputEncPhA = 44|0x100U , kXBARA_OutputEncPhB = 45|0x100U , kXBARA_OutputEncIndex = 46|0x100U , kXBARA_OutputEncHome = 47|0x100U ,   kXBARA_OutputEncCapTrigger = 48|0x100U , kXBARA_OutputFtm0Fault3 = 49|0x100U , kXBARA_OutputFtm1Fault1 = 50|0x100U , kXBARA_OutputFtm2Fault1 = 51|0x100U ,   kXBARA_OutputFtm3Fault3 = 52|0x100U , kXBARA_OutputPwm1Ch0ExtSync = 53|0x100U , kXBARA_OutputPwm1Ch1ExtSync = 54|0x100U , kXBARA_OutputPwm1Ch2ExtSync = 55|0x100U ,   kXBARA_OutputPwm1Ch3ExtSync = 56|0x100U , kXBARA_OutputPwm1Force = 57|0x100U , kXBARA_OutputEwmIn = 58|0x100U , kXBARB_OutputAoiIn0 = 0|0x200U ,   kXBARB_OutputAoiIn1 = 1|0x200U , kXBARB_OutputAoiIn2 = 2|0x200U , kXBARB_OutputAoiIn3 = 3|0x200U , kXBARB_OutputAoiIn4 = 4|0x200U ,   kXBARB_OutputAoiIn5 = 5|0x200U , kXBARB_OutputAoiIn6 = 6|0x200U , kXBARB_OutputAoiIn7 = 7|0x200U , kXBARB_OutputAoiIn8 = 8|0x200U ,   kXBARB_OutputAoiIn9 = 9|0x200U , kXBARB_OutputAoiIn10 = 10|0x200U , kXBARB_OutputAoiIn11 = 11|0x200U , kXBARB_OutputAoiIn12 = 12|0x200U ,   kXBARB_OutputAoiIn13 = 13|0x200U , kXBARB_OutputAoiIn14 = 14|0x200U , kXBARB_OutputAoiIn15 = 15|0x200U }

Typedef Documentation

dma_request_source_t [1/5]

typedef enum _dma_request_source dma_request_source_t

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

dma_request_source_t [2/5]

typedef enum _dma_request_source dma_request_source_t

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

dma_request_source_t [3/5]

typedef enum _dma_request_source dma_request_source_t

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

dma_request_source_t [4/5]

typedef enum _dma_request_source dma_request_source_t

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

dma_request_source_t [5/5]

typedef enum _dma_request_source dma_request_source_t

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

Enumeration Type Documentation

_dma_request_source [1/5]

enum _dma_request_source

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

Enumerator
kDmaRequestMux0Disable	Disable
kDmaRequestMux0Reserved1	Reserved1
kDmaRequestMux0UART0Rx	UART0 receive complete
kDmaRequestMux0UART0Tx	UART0 transmit complete
kDmaRequestMux0UART1Rx	UART1 receive complete
kDmaRequestMux0UART1Tx	UART1 transmit complete
kDmaRequestMux0UART2Rx	UART2 receive complete
kDmaRequestMux0UART2Tx	UART2 transmit complete
kDmaRequestMux0UART3Rx	UART3 receive complete
kDmaRequestMux0UART3Tx	UART3 transmit complete
kDmaRequestMux0UART4Rx	UART4 receive complete
kDmaRequestMux0UART4Tx	UART4 transmit complete
kDmaRequestMux0UART5Rx	UART5 receive complete
kDmaRequestMux0UART5Tx	UART5 transmit complete
kDmaRequestMux0I2S0Rx	I2S0 receive complete
kDmaRequestMux0I2S0Tx	I2S0 transmit complete
kDmaRequestMux0SPI0Rx	SPI0 receive complete
kDmaRequestMux0SPI0Tx	SPI0 transmit complete
kDmaRequestMux0SPI1Rx	SPI1 receive complete
kDmaRequestMux0SPI1Tx	SPI1 transmit complete
kDmaRequestMux0SPI2Rx	SPI2 receive complete
kDmaRequestMux0SPI2Tx	SPI2 transmit complete
kDmaRequestMux0I2C0	I2C0 transmission complete
kDmaRequestMux0I2C1	I2C1 transmission complete
kDmaRequestMux0FTM0Channel0	FTM0 channel 0 event (CMP or CAP)
kDmaRequestMux0FTM0Channel1	FTM0 channel 1 event (CMP or CAP)
kDmaRequestMux0FTM0Channel2	FTM0 channel 2 event (CMP or CAP)
kDmaRequestMux0FTM0Channel3	FTM0 channel 3 event (CMP or CAP)
kDmaRequestMux0FTM0Channel4	FTM0 channel 4 event (CMP or CAP)
kDmaRequestMux0FTM0Channel5	FTM0 channel 5 event (CMP or CAP)
kDmaRequestMux0FTM0Channel6	FTM0 channel 6 event (CMP or CAP)
kDmaRequestMux0FTM0Channel7	FTM0 channel 7 event (CMP or CAP)
kDmaRequestMux0FTM1Channel0	FTM1 channel 0 event (CMP or CAP)
kDmaRequestMux0FTM1Channel1	FTM1 channel 1 event (CMP or CAP)
kDmaRequestMux0FTM2Channel0	FTM2 channel 0 event (CMP or CAP)
kDmaRequestMux0FTM2Channel1	FTM2 channel 1 event (CMP or CAP)
kDmaRequestMux0IEEE1588Timer0	Ethernet IEEE 1588 timer 0
kDmaRequestMux0IEEE1588Timer1	Ethernet IEEE 1588 timer 1
kDmaRequestMux0IEEE1588Timer2	Ethernet IEEE 1588 timer 2
kDmaRequestMux0IEEE1588Timer3	Ethernet IEEE 1588 timer 3
kDmaRequestMux0ADC0	ADC0 conversion complete
kDmaRequestMux0ADC1	ADC1 conversion complete
kDmaRequestMux0CMP0	CMP0 Output
kDmaRequestMux0CMP1	CMP1 Output
kDmaRequestMux0CMP2	CMP2 Output
kDmaRequestMux0DAC0	DAC0 buffer pointer reaches upper or lower limit
kDmaRequestMux0DAC1	DAC1 buffer pointer reaches upper or lower limit
kDmaRequestMux0CMT	CMT end of modulation cycle event
kDmaRequestMux0PDB0	PDB0 programmable interrupt delay event
kDmaRequestMux0PortA	PORTA rising, falling or both edges
kDmaRequestMux0PortB	PORTB rising, falling or both edges
kDmaRequestMux0PortC	PORTC rising, falling or both edges
kDmaRequestMux0PortD	PORTD rising, falling or both edges
kDmaRequestMux0PortE	PORTE rising, falling or both edges
kDmaRequestMux0AlwaysOn54	Always enabled 54
kDmaRequestMux0AlwaysOn55	Always enabled 55
kDmaRequestMux0AlwaysOn56	Always enabled 56
kDmaRequestMux0AlwaysOn57	Always enabled 57
kDmaRequestMux0AlwaysOn58	Always enabled 58
kDmaRequestMux0AlwaysOn59	Always enabled 59
kDmaRequestMux0AlwaysOn60	Always enabled 60
kDmaRequestMux0AlwaysOn61	Always enabled 61
kDmaRequestMux0AlwaysOn62	Always enabled 62
kDmaRequestMux0AlwaysOn63	Always enabled 63

_dma_request_source [2/5]

enum _dma_request_source

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

Enumerator
kDmaRequestMux0Disable	DMAMUX TriggerDisabled.
kDmaRequestMux0Reserved1	Reserved1
kDmaRequestMux0UART0Rx	UART0 Receive.
kDmaRequestMux0UART0Tx	UART0 Transmit.
kDmaRequestMux0UART1Rx	UART1 Receive.
kDmaRequestMux0UART1Tx	UART1 Transmit.
kDmaRequestMux0UART2Rx	UART2 Receive.
kDmaRequestMux0UART2Tx	UART2 Transmit.
kDmaRequestMux0UART3Rx	UART3 Receive.
kDmaRequestMux0UART3Tx	UART3 Transmit.
kDmaRequestMux0UART4	UART4 Transmit or Receive.
kDmaRequestMux0UART5	UART5 Transmit or Receive.
kDmaRequestMux0I2S0Rx	I2S0 Receive.
kDmaRequestMux0I2S0Tx	I2S0 Transmit.
kDmaRequestMux0SPI0Rx	SPI0 Receive.
kDmaRequestMux0SPI0Tx	SPI0 Transmit.
kDmaRequestMux0SPI1	SPI1 Transmit or Receive.
kDmaRequestMux0SPI2	SPI2 Transmit or Receive.
kDmaRequestMux0I2C0	I2C0.
kDmaRequestMux0I2C1I2C2	I2C1 and I2C2.
kDmaRequestMux0I2C1	I2C1 and I2C2.
kDmaRequestMux0I2C2	I2C1 and I2C2.
kDmaRequestMux0FTM0Channel0	FTM0 C0V.
kDmaRequestMux0FTM0Channel1	FTM0 C1V.
kDmaRequestMux0FTM0Channel2	FTM0 C2V.
kDmaRequestMux0FTM0Channel3	FTM0 C3V.
kDmaRequestMux0FTM0Channel4	FTM0 C4V.
kDmaRequestMux0FTM0Channel5	FTM0 C5V.
kDmaRequestMux0FTM0Channel6	FTM0 C6V.
kDmaRequestMux0FTM0Channel7	FTM0 C7V.
kDmaRequestMux0FTM1Channel0	FTM1 C0V.
kDmaRequestMux0FTM1Channel1	FTM1 C1V.
kDmaRequestMux0FTM2Channel0	FTM2 C0V.
kDmaRequestMux0FTM2Channel1	FTM2 C1V.
kDmaRequestMux0FTM3Channel0	FTM3 C0V.
kDmaRequestMux0FTM3Channel1	FTM3 C1V.
kDmaRequestMux0FTM3Channel2	FTM3 C2V.
kDmaRequestMux0FTM3Channel3	FTM3 C3V.
kDmaRequestMux0FTM3Channel4	FTM3 C4V.
kDmaRequestMux0FTM3Channel5	FTM3 C5V.
kDmaRequestMux0FTM3Channel6	FTM3 C6V.
kDmaRequestMux0FTM3Channel7	FTM3 C7V.
kDmaRequestMux0ADC0	ADC0.
kDmaRequestMux0ADC1	ADC1.
kDmaRequestMux0CMP0	CMP0.
kDmaRequestMux0CMP1	CMP1.
kDmaRequestMux0CMP2	CMP2.
kDmaRequestMux0DAC0	DAC0.
kDmaRequestMux0DAC1	DAC1.
kDmaRequestMux0CMT	CMT.
kDmaRequestMux0PDB	PDB0.
kDmaRequestMux0PortA	PTA.
kDmaRequestMux0PortB	PTB.
kDmaRequestMux0PortC	PTC.
kDmaRequestMux0PortD	PTD.
kDmaRequestMux0PortE	PTE.
kDmaRequestMux0IEEE1588Timer0	ENET IEEE 1588 timer 0.
kDmaRequestMux0IEEE1588Timer1	ENET IEEE 1588 timer 1.
kDmaRequestMux0IEEE1588Timer2	ENET IEEE 1588 timer 2.
kDmaRequestMux0IEEE1588Timer3	ENET IEEE 1588 timer 3.
kDmaRequestMux0AlwaysOn58	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn59	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn60	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn61	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn62	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn63	DMAMUX Always Enabled slot.

_dma_request_source [3/5]

enum _dma_request_source

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

Enumerator
kDmaRequestMux0Disable	DMAMUX TriggerDisabled.
kDmaRequestMux0TSI0	TSI0.
kDmaRequestMux0UART0Rx	UART0 Receive.
kDmaRequestMux0UART0Tx	UART0 Transmit.
kDmaRequestMux0UART1Rx	UART1 Receive.
kDmaRequestMux0UART1Tx	UART1 Transmit.
kDmaRequestMux0UART2Rx	UART2 Receive.
kDmaRequestMux0UART2Tx	UART2 Transmit.
kDmaRequestMux0UART3Rx	UART3 Receive.
kDmaRequestMux0UART3Tx	UART3 Transmit.
kDmaRequestMux0UART4	UART4 Transmit or Receive.
kDmaRequestMux0Reserved11	Reserved11
kDmaRequestMux0I2S0Rx	I2S0 Receive.
kDmaRequestMux0I2S0Tx	I2S0 Transmit.
kDmaRequestMux0SPI0Rx	SPI0 Receive.
kDmaRequestMux0SPI0Tx	SPI0 Transmit.
kDmaRequestMux0SPI1Rx	SPI1 Receive.
kDmaRequestMux0SPI1Tx	SPI1 Transmit.
kDmaRequestMux0I2C0I2C3	I2C0 and I2C3.
kDmaRequestMux0I2C0	I2C0 and I2C3.
kDmaRequestMux0I2C3	I2C0 and I2C3.
kDmaRequestMux0I2C1I2C2	I2C1 and I2C2.
kDmaRequestMux0I2C1	I2C1 and I2C2.
kDmaRequestMux0I2C2	I2C1 and I2C2.
kDmaRequestMux0FTM0Channel0	FTM0 C0V.
kDmaRequestMux0FTM0Channel1	FTM0 C1V.
kDmaRequestMux0FTM0Channel2	FTM0 C2V.
kDmaRequestMux0FTM0Channel3	FTM0 C3V.
kDmaRequestMux0FTM0Channel4	FTM0 C4V.
kDmaRequestMux0FTM0Channel5	FTM0 C5V.
kDmaRequestMux0FTM0Channel6	FTM0 C6V.
kDmaRequestMux0FTM0Channel7	FTM0 C7V.
kDmaRequestMux0FTM1TPM1Channel0	FTM1 C0V and TPM1 C0V.
kDmaRequestMux0FTM1Channel0	FTM1 C0V and TPM1 C0V.
kDmaRequestMux0TPM1Channel0	FTM1 C0V and TPM1 C0V.
kDmaRequestMux0FTM1TPM1Channel1	FTM1 C1V and TPM1 C1V.
kDmaRequestMux0FTM1Channel1	FTM1 C1V and TPM1 C1V.
kDmaRequestMux0TPM1Channel1	FTM1 C1V and TPM1 C1V.
kDmaRequestMux0FTM2TPM2Channel0	FTM2 C0V and TPM2 C0V.
kDmaRequestMux0FTM2Channel0	FTM2 C0V and TPM2 C0V.
kDmaRequestMux0TPM2Channel0	FTM2 C0V and TPM2 C0V.
kDmaRequestMux0FTM2TPM2Channel1	FTM2 C1V and TPM2 C1V.
kDmaRequestMux0FTM2Channel1	FTM2 C1V and TPM2 C1V.
kDmaRequestMux0TPM2Channel1	FTM2 C1V and TPM2 C1V.
kDmaRequestMux0FTM3Channel0	FTM3 C0V.
kDmaRequestMux0FTM3Channel1	FTM3 C1V.
kDmaRequestMux0FTM3Channel2	FTM3 C2V.
kDmaRequestMux0FTM3Channel3	FTM3 C3V.
kDmaRequestMux0FTM3Channel4	FTM3 C4V.
kDmaRequestMux0FTM3Channel5	FTM3 C5V.
kDmaRequestMux0FTM3Channel6SPI2Rx	FTM3 C6V and SPI2 Receive.
kDmaRequestMux0FTM3Channel6	FTM3 C6V and SPI2 Receive.
kDmaRequestMux0SPI2Rx	FTM3 C6V and SPI2 Receive.
kDmaRequestMux0FTM3Channel7SPI2Tx	FTM3 C7V and SPI2 Transmit.
kDmaRequestMux0FTM3Channel7	FTM3 C7V and SPI2 Transmit.
kDmaRequestMux0SPI2Tx	FTM3 C7V and SPI2 Transmit.
kDmaRequestMux0ADC0	ADC0.
kDmaRequestMux0ADC1	ADC1.
kDmaRequestMux0CMP0	CMP0.
kDmaRequestMux0CMP1	CMP1.
kDmaRequestMux0CMP2CMP3	CMP2 and CMP3.
kDmaRequestMux0CMP2	CMP2 and CMP3.
kDmaRequestMux0CMP3	CMP2 and CMP3.
kDmaRequestMux0DAC0	DAC0.
kDmaRequestMux0DAC1	DAC1.
kDmaRequestMux0CMT	CMT.
kDmaRequestMux0PDB	PDB0.
kDmaRequestMux0PortA	PTA.
kDmaRequestMux0PortB	PTB.
kDmaRequestMux0PortC	PTC.
kDmaRequestMux0PortD	PTD.
kDmaRequestMux0PortE	PTE.
kDmaRequestMux0IEEE1588Timer0	ENET IEEE 1588 timer 0.
kDmaRequestMux0IEEE1588Timer1TPM1Overflow	ENET IEEE 1588 timer 1 and TPM1.
kDmaRequestMux0IEEE1588Timer1	ENET IEEE 1588 timer 1 and TPM1.
kDmaRequestMux0TPM1Overflow	ENET IEEE 1588 timer 1 and TPM1.
kDmaRequestMux0IEEE1588Timer2TPM2Overflow	ENET IEEE 1588 timer 2 and TPM2.
kDmaRequestMux0IEEE1588Timer2	ENET IEEE 1588 timer 2 and TPM2.
kDmaRequestMux0TPM2Overflow	ENET IEEE 1588 timer 2 and TPM2.
kDmaRequestMux0IEEE1588Timer3	ENET IEEE 1588 timer 3.
kDmaRequestMux0LPUART0Rx	LPUART0 Receive.
kDmaRequestMux0LPUART0Tx	LPUART0 Transmit.
kDmaRequestMux0AlwaysOn60	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn61	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn62	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn63	DMAMUX Always Enabled slot.

_dma_request_source [4/5]

enum _dma_request_source

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

Enumerator
kDmaRequestMux0Disable	DMAMUX TriggerDisabled.
kDmaRequestMux0TSI0	TSI0.
kDmaRequestMux0UART0Rx	UART0 Receive.
kDmaRequestMux0UART0Tx	UART0 Transmit.
kDmaRequestMux0UART1Rx	UART1 Receive.
kDmaRequestMux0UART1Tx	UART1 Transmit.
kDmaRequestMux0UART2Rx	UART2 Receive.
kDmaRequestMux0UART2Tx	UART2 Transmit.
kDmaRequestMux0UART3Rx	UART3 Receive.
kDmaRequestMux0UART3Tx	UART3 Transmit.
kDmaRequestMux0UART4	UART4 Transmit or Receive.
kDmaRequestMux0Reserved11	Reserved11
kDmaRequestMux0I2S0Rx	I2S0 Receive.
kDmaRequestMux0I2S0Tx	I2S0 Transmit.
kDmaRequestMux0SPI0Rx	SPI0 Receive.
kDmaRequestMux0SPI0Tx	SPI0 Transmit.
kDmaRequestMux0SPI1Rx	SPI1 Receive.
kDmaRequestMux0SPI1Tx	SPI1 Transmit.
kDmaRequestMux0I2C0I2C3	I2C0 and I2C3.
kDmaRequestMux0I2C0	I2C0 and I2C3.
kDmaRequestMux0I2C3	I2C0 and I2C3.
kDmaRequestMux0I2C1I2C2	I2C1 and I2C2.
kDmaRequestMux0I2C1	I2C1 and I2C2.
kDmaRequestMux0I2C2	I2C1 and I2C2.
kDmaRequestMux0FTM0Channel0	FTM0 C0V.
kDmaRequestMux0FTM0Channel1	FTM0 C1V.
kDmaRequestMux0FTM0Channel2	FTM0 C2V.
kDmaRequestMux0FTM0Channel3	FTM0 C3V.
kDmaRequestMux0FTM0Channel4	FTM0 C4V.
kDmaRequestMux0FTM0Channel5	FTM0 C5V.
kDmaRequestMux0FTM0Channel6	FTM0 C6V.
kDmaRequestMux0FTM0Channel7	FTM0 C7V.
kDmaRequestMux0FTM1TPM1Channel0	FTM1 C0V and TPM1 C0V.
kDmaRequestMux0FTM1Channel0	FTM1 C0V and TPM1 C0V.
kDmaRequestMux0TPM1Channel0	FTM1 C0V and TPM1 C0V.
kDmaRequestMux0FTM1TPM1Channel1	FTM1 C1V and TPM1 C1V.
kDmaRequestMux0FTM1Channel1	FTM1 C1V and TPM1 C1V.
kDmaRequestMux0TPM1Channel1	FTM1 C1V and TPM1 C1V.
kDmaRequestMux0FTM2TPM2Channel0	FTM2 C0V and TPM2 C0V.
kDmaRequestMux0FTM2Channel0	FTM2 C0V and TPM2 C0V.
kDmaRequestMux0TPM2Channel0	FTM2 C0V and TPM2 C0V.
kDmaRequestMux0FTM2TPM2Channel1	FTM2 C1V and TPM2 C1V.
kDmaRequestMux0FTM2Channel1	FTM2 C1V and TPM2 C1V.
kDmaRequestMux0TPM2Channel1	FTM2 C1V and TPM2 C1V.
kDmaRequestMux0FTM3Channel0	FTM3 C0V.
kDmaRequestMux0FTM3Channel1	FTM3 C1V.
kDmaRequestMux0FTM3Channel2	FTM3 C2V.
kDmaRequestMux0FTM3Channel3	FTM3 C3V.
kDmaRequestMux0FTM3Channel4	FTM3 C4V.
kDmaRequestMux0FTM3Channel5	FTM3 C5V.
kDmaRequestMux0FTM3Channel6SPI2Rx	FTM3 C6V and SPI2 Receive.
kDmaRequestMux0FTM3Channel6	FTM3 C6V and SPI2 Receive.
kDmaRequestMux0SPI2Rx	FTM3 C6V and SPI2 Receive.
kDmaRequestMux0FTM3Channel7SPI2Tx	FTM3 C7V and SPI2 Transmit.
kDmaRequestMux0FTM3Channel7	FTM3 C7V and SPI2 Transmit.
kDmaRequestMux0SPI2Tx	FTM3 C7V and SPI2 Transmit.
kDmaRequestMux0ADC0	ADC0.
kDmaRequestMux0ADC1	ADC1.
kDmaRequestMux0CMP0	CMP0.
kDmaRequestMux0CMP1	CMP1.
kDmaRequestMux0CMP2CMP3	CMP2 and CMP3.
kDmaRequestMux0CMP2	CMP2 and CMP3.
kDmaRequestMux0CMP3	CMP2 and CMP3.
kDmaRequestMux0DAC0	DAC0.
kDmaRequestMux0DAC1	DAC1.
kDmaRequestMux0CMT	CMT.
kDmaRequestMux0PDB	PDB0.
kDmaRequestMux0PortA	PTA.
kDmaRequestMux0PortB	PTB.
kDmaRequestMux0PortC	PTC.
kDmaRequestMux0PortD	PTD.
kDmaRequestMux0PortE	PTE.
kDmaRequestMux0IEEE1588Timer0	ENET IEEE 1588 timer 0.
kDmaRequestMux0IEEE1588Timer1TPM1Overflow	ENET IEEE 1588 timer 1 and TPM1.
kDmaRequestMux0IEEE1588Timer1	ENET IEEE 1588 timer 1 and TPM1.
kDmaRequestMux0TPM1Overflow	ENET IEEE 1588 timer 1 and TPM1.
kDmaRequestMux0IEEE1588Timer2TPM2Overflow	ENET IEEE 1588 timer 2 and TPM2.
kDmaRequestMux0IEEE1588Timer2	ENET IEEE 1588 timer 2 and TPM2.
kDmaRequestMux0TPM2Overflow	ENET IEEE 1588 timer 2 and TPM2.
kDmaRequestMux0IEEE1588Timer3	ENET IEEE 1588 timer 3.
kDmaRequestMux0LPUART0Rx	LPUART0 Receive.
kDmaRequestMux0LPUART0Tx	LPUART0 Transmit.
kDmaRequestMux0AlwaysOn60	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn61	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn62	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn63	DMAMUX Always Enabled slot.

_dma_request_source [5/5]

enum _dma_request_source

Defines the structure for the DMA hardware request collections. The user can configure the hardware request into DMAMUX to trigger the DMA transfer accordingly. The index of the hardware request varies according to the to SoC.

Enumerator
kDmaRequestMux0Disable	DMAMUX TriggerDisabled.
kDmaRequestMux0Reserved1	Reserved1
kDmaRequestMux0UART0Rx	UART0 Receive.
kDmaRequestMux0UART0Tx	UART0 Transmit.
kDmaRequestMux0UART1Rx	UART1 Receive.
kDmaRequestMux0UART1Tx	UART1 Transmit.
kDmaRequestMux0PWM0WR0	PWM0 Write Request 0.
kDmaRequestMux0PWM0WR1	PWM0 Write Request 1.
kDmaRequestMux0PWM0WR2	PWM0 Write Request 2.
kDmaRequestMux0PWM0WR3	PWM0 Write Request 3.
kDmaRequestMux0PWM0CP0	PWM0 Capture 0.
kDmaRequestMux0PWM0CP1	PWM0 Capture 1.
kDmaRequestMux0PWM0CP2	PWM0 Capture 2.
kDmaRequestMux0PWM0CP3	PWM0 Capture 3.
kDmaRequestMux0CAN0	CAN0.
kDmaRequestMux0CAN1	CAN1.
kDmaRequestMux0SPI0Rx	SPI0 Receive.
kDmaRequestMux0SPI0Tx	SPI0 Transmit.
kDmaRequestMux0XBARAOUT0	XBARA Output 0.
kDmaRequestMux0XBARAOUT1	XBARA Output 1.
kDmaRequestMux0XBARAOUT2	XBARA Output 2.
kDmaRequestMux0XBARAOUT3	XBARA Output 3.
kDmaRequestMux0I2C0	I2C0.
kDmaRequestMux0Reserved23	Reserved23
kDmaRequestMux0FTM0Channel0	FTM0 C0V.
kDmaRequestMux0FTM0Channel1	FTM0 C1V.
kDmaRequestMux0FTM0Channel2	FTM0 C2V.
kDmaRequestMux0FTM0Channel3	FTM0 C3V.
kDmaRequestMux0FTM0Channel4	FTM0 C4V.
kDmaRequestMux0FTM0Channel5	FTM0 C5V.
kDmaRequestMux0FTM0Channel6	FTM0 C6V.
kDmaRequestMux0FTM0Channel7	FTM0 C7V.
kDmaRequestMux0FTM1Channel0	FTM1 C0V.
kDmaRequestMux0FTM1Channel1	FTM1 C1V.
kDmaRequestMux0CMP3	CMP3.
kDmaRequestMux0Reserved35	Reserved35
kDmaRequestMux0FTM3Channel0	FTM3 C0V.
kDmaRequestMux0FTM3Channel1	FTM3 C1V.
kDmaRequestMux0FTM3Channel2	FTM3 C2V.
kDmaRequestMux0FTM3Channel3	FTM3 C3V.
kDmaRequestMux0HSADC0A	HSADC0.
kDmaRequestMux0HSADC0B	HSADC0.
kDmaRequestMux0CMP0	CMP0.
kDmaRequestMux0CMP1	CMP1.
kDmaRequestMux0CMP2	CMP2.
kDmaRequestMux0DAC0	DAC0.
kDmaRequestMux0Reserved46	Reserved46
kDmaRequestMux0PDB1	PDB1.
kDmaRequestMux0PDB0	PDB0.
kDmaRequestMux0PortA	PTA.
kDmaRequestMux0PortB	PTB.
kDmaRequestMux0PortC	PTC.
kDmaRequestMux0PortD	PTD.
kDmaRequestMux0PortE	PTE.
kDmaRequestMux0FTM3Channel4	FTM3 C4V.
kDmaRequestMux0FTM3Channel5	FTM3 C5V.
kDmaRequestMux0FTM3Channel6	FTM3 C6V.
kDmaRequestMux0FTM3Channel7	FTM3 C7V.
kDmaRequestMux0Reserved58	Reserved58
kDmaRequestMux0Reserved59	Reserved59
kDmaRequestMux0AlwaysOn60	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn61	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn62	DMAMUX Always Enabled slot.
kDmaRequestMux0AlwaysOn63	DMAMUX Always Enabled slot.
kDmaRequestMux0Group1Disable	DMAMUX TriggerDisabled.
kDmaRequestMux0Group1Reserved1	Reserved1
kDmaRequestMux0Group1UART2Rx	UART2 Receive.
kDmaRequestMux0Group1UART2Tx	UART2 Transmit.
kDmaRequestMux0Group1UART3Rx	UART3 Receive.
kDmaRequestMux0Group1UART3Tx	UART3 Transmit.
kDmaRequestMux0Group1PWM1WR0	PWM1 Write Request 0.
kDmaRequestMux0Group1PWM1WR1	PWM1 Write Request 1.
kDmaRequestMux0Group1PWM1WR2	PWM1 Write Request 2.
kDmaRequestMux0Group1PWM1WR3	PWM1 Write Request 3.
kDmaRequestMux0Group1PWM1CP0	PWM1 Capture 0.
kDmaRequestMux0Group1PWM1CP1	PWM1 Capture 1.
kDmaRequestMux0Group1PWM1CP2	PWM1 Capture 2.
kDmaRequestMux0Group1PWM1CP3	PWM1 Capture 3.
kDmaRequestMux0Group1CAN2	CAN2.
kDmaRequestMux0Group1Reserved15	Reserved15
kDmaRequestMux0Group1SPI1Rx	SPI1 Receive.
kDmaRequestMux0Group1SPI1Tx	SPI1 Transmit.
kDmaRequestMux0Group1Reserved18	Reserved18
kDmaRequestMux0Group1Reserved19	Reserved19
kDmaRequestMux0Group1Reserved20	Reserved20
kDmaRequestMux0Group1Reserved21	Reserved21
kDmaRequestMux0Group1I2C1	I2C1.
kDmaRequestMux0Group1Reserved23	Reserved23
kDmaRequestMux0Group1Reserved24	Reserved24
kDmaRequestMux0Group1Reserved25	Reserved25
kDmaRequestMux0Group1Reserved26	Reserved26
kDmaRequestMux0Group1Reserved27	Reserved27
kDmaRequestMux0Group1Reserved28	Reserved28
kDmaRequestMux0Group1Reserved29	Reserved29
kDmaRequestMux0Group1Reserved30	Reserved30
kDmaRequestMux0Group1Reserved31	Reserved31
kDmaRequestMux0Group1FTM2Channel0	FTM2 C0V.
kDmaRequestMux0Group1FTM2Channel1	FTM2 C1V.
kDmaRequestMux0Group1SPI2Rx	SPI2 Receive.
kDmaRequestMux0Group1SPI2Tx	SPI2 Transmit.
kDmaRequestMux0Group1IEEE1588Timer0	ENET IEEE 1588 timer 0.
kDmaRequestMux0Group1IEEE1588Timer1	ENET IEEE 1588 timer 1.
kDmaRequestMux0Group1IEEE1588Timer2	ENET IEEE 1588 timer 2.
kDmaRequestMux0Group1IEEE1588Timer3	ENET IEEE 1588 timer 3.
kDmaRequestMux0Group1HSADC1A	HSADC1.
kDmaRequestMux0Group1HSADC1B	HSADC1.
kDmaRequestMux0Group1Reserved42	Reserved42
kDmaRequestMux0Group1Reserved43	Reserved43
kDmaRequestMux0Group1Reserved44	Reserved44
kDmaRequestMux0Group1ADC0	ADC0.
kDmaRequestMux0Group1Reserved46	Reserved46
kDmaRequestMux0Group1Reserved47	Reserved47
kDmaRequestMux0Group1Reserved48	Reserved48
kDmaRequestMux0Group1Reserved49	Reserved49
kDmaRequestMux0Group1Reserved50	Reserved50
kDmaRequestMux0Group1Reserved51	Reserved51
kDmaRequestMux0Group1Reserved52	Reserved52
kDmaRequestMux0Group1Reserved53	Reserved53
kDmaRequestMux0Group1UART4Rx	UART4 Receive.
kDmaRequestMux0Group1UART4Tx	UART4 Transmit.
kDmaRequestMux0Group1UART5Rx	UART5 Receive.
kDmaRequestMux0Group1UART5Tx	UART5 Transmit.
kDmaRequestMux0Group1Reserved58	Reserved58
kDmaRequestMux0Group1Reserved59	Reserved59
kDmaRequestMux0Group1AlwaysOn60	DMAMUX Always Enabled slot.
kDmaRequestMux0Group1AlwaysOn61	DMAMUX Always Enabled slot.
kDmaRequestMux0Group1AlwaysOn62	DMAMUX Always Enabled slot.
kDmaRequestMux0Group1AlwaysOn63	DMAMUX Always Enabled slot.

_xbar_input_signal

enum _xbar_input_signal

Enumerator
kXBARA_InputVss	Logic zero output assigned to XBARA_IN0 input.
kXBARA_InputVdd	Logic one output assigned to XBARA_IN1 input.
kXBARA_InputXbarIn2	XB_IN2 input pin output assigned to XBARA_IN2 input.
kXBARA_InputXbarIn3	XB_IN3 input pin output assigned to XBARA_IN3 input.
kXBARA_InputXbarIn4	XB_IN4 input pin output assigned to XBARA_IN4 input.
kXBARA_InputXbarIn5	XB_IN5 input pin output assigned to XBARA_IN5 input.
kXBARA_InputXbarIn6	XB_IN6 input pin output assigned to XBARA_IN6 input.
kXBARA_InputXbarIn7	XB_IN7 input pin output assigned to XBARA_IN7 input.
kXBARA_InputXbarIn8	XB_IN8 input pin output assigned to XBARA_IN8 input.
kXBARA_InputXbarIn9	XB_IN9 input pin output assigned to XBARA_IN9 input.
kXBARA_InputXbarIn10	XB_IN10 input pin output assigned to XBARA_IN10 input.
kXBARA_InputXbarIn11	XB_IN11 input pin output assigned to XBARA_IN11 input.
kXBARA_InputCmp0Output	CMP0 Output output assigned to XBARA_IN12 input.
kXBARA_InputCmp1Output	CMP1 Output output assigned to XBARA_IN13 input.
kXBARA_InputCmp2Output	CMP2 Output output assigned to XBARA_IN14 input.
kXBARA_InputCmp3Output	CMP3 Output output assigned to XBARA_IN15 input.
kXBARA_InputFtm0Match	FTM0 all channels match trigger ORed together output assigned to XBARA_IN16 input.
kXBARA_InputFtm0Extrig	FTM0 counter init trigger output assigned to XBARA_IN17 input.
kXBARA_InputFtm3Match	FTM3 all channels match trigger ORed together output assigned to XBARA_IN18 input.
kXBARA_InputFtm3Extrig	FTM3 counter init trigger output assigned to XBARA_IN19 input.
kXBARA_InputPwm0Ch0Trg0	PWMA channel 0 trigger 0 output assigned to XBARA_IN20 input.
kXBARA_InputPwm0Ch0Trg1	PWMA channel 0 trigger 1 output assigned to XBARA_IN21 input.
kXBARA_InputPwm0Ch1Trg0	PWMA channel 1 trigger 0 output assigned to XBARA_IN22 input.
kXBARA_InputPwm0Ch1Trg1	PWMA channel 1 trigger 1 output assigned to XBARA_IN23 input.
kXBARA_InputPwm0Ch2Trg0	PWMA channel 2 trigger 0 output assigned to XBARA_IN24 input.
kXBARA_InputPwm0Ch2Trg1	PWMA channel 2 trigger 1 output assigned to XBARA_IN25 input.
kXBARA_InputPwm0Ch3Trg0	PWMA channel 3 trigger 0 output assigned to XBARA_IN26 input.
kXBARA_InputPwm0Ch3Trg1	PWMA channel 3 trigger 1 output assigned to XBARA_IN27 input.
kXBARA_InputPdb0Ch1Output	PDB0 channel 1 output trigger output assigned to XBARA_IN28 input.
kXBARA_InputPdb0Ch0Output	PDB0 channel 0 output trigger output assigned to XBARA_IN29 input.
kXBARA_InputPdb1Ch1Output	PDB1 channel 1 output trigger output assigned to XBARA_IN30 input.
kXBARA_InputPdb1Ch0Output	PDB1 channel 0 output trigger output assigned to XBARA_IN31 input.
kXBARA_InputHsadc1Cca	High Speed Analog-to-Digital Converter 1 conversion A complete output assigned to XBARA_IN32 input.
kXBARA_InputHsadc0Cca	High Speed Analog-to-Digital Converter 0 conversion A complete output assigned to XBARA_IN33 input.
kXBARA_InputHsadc1Ccb	High Speed Analog-to-Digital Converter 1 conversion B complete output assigned to XBARA_IN34 input.
kXBARA_InputHsadc0Ccb	High Speed Analog-to-Digital Converter 0 conversion B complete output assigned to XBARA_IN35 input.
kXBARA_InputFtm1Match	FTM1 all channels match trigger ORed together output assigned to XBARA_IN36 input.
kXBARA_InputFtm1Extrig	FTM1 counter init trigger output assigned to XBARA_IN37 input.
kXBARA_InputDmaCh0Done	DMA channel 0 done output assigned to XBARA_IN38 input.
kXBARA_InputDmaCh1Done	DMA channel 1 done output assigned to XBARA_IN39 input.
kXBARA_InputDmaCh6Done	DMA channel 6 done output assigned to XBARA_IN40 input.
kXBARA_InputDmaCh7Done	DMA channel 7 done output assigned to XBARA_IN41 input.
kXBARA_InputPitTrigger0	PIT trigger 0 output assigned to XBARA_IN42 input.
kXBARA_InputPitTrigger1	PIT trigger 1 output assigned to XBARA_IN43 input.
kXBARA_InputAdc0Coco	Analog-to-Digital Converter 0 conversion complete output assigned to XBARA_IN44 input.
kXBARA_InputEnc0CmpPosMatch	ENC compare trigger and position match output assigned to XBARA_IN45 input.
kXBARA_InputAndOrInvert0	AOI output 0 output assigned to XBARA_IN46 input.
kXBARA_InputAndOrInvert1	AOI output 1 output assigned to XBARA_IN47 input.
kXBARA_InputAndOrInvert2	AOI output 2 output assigned to XBARA_IN48 input.
kXBARA_InputAndOrInvert3	AOI output 3 output assigned to XBARA_IN49 input.
kXBARA_InputPitTrigger2	PIT trigger 2 output assigned to XBARA_IN50 input.
kXBARA_InputPitTrigger3	PIT trigger 3 output assigned to XBARA_IN51 input.
kXBARA_InputPwm1Ch0Trg0OrTrg1	PWMB channel 0 trigger 0 or trigger 1 output assigned to XBARA_IN52 input.
kXBARA_InputPwm1Ch1Trg0OrTrg1	PWMB channel 1 trigger 0 or trigger 1 output assigned to XBARA_IN53 input.
kXBARA_InputPwm1Ch2Trg0OrTrg1	PWMB channel 2 trigger 0 or trigger 1 output assigned to XBARA_IN54 input.
kXBARA_InputPwm1Ch3Trg0OrTrg1	PWMB channel 3 trigger 0 or trigger 1 output assigned to XBARA_IN55 input.
kXBARA_InputFtm2Match	FTM2 all channels match trigger ORed together output assigned to XBARA_IN56 input.
kXBARA_InputFtm2Extrig	FTM2 counter init trigger output assigned to XBARA_IN57 input.
kXBARB_InputCmp0Output	CMP0 Output output assigned to XBARB_IN0 input.
kXBARB_InputCmp1Output	CMP1 Output output assigned to XBARB_IN1 input.
kXBARB_InputCmp2Output	CMP2 Output output assigned to XBARB_IN2 input.
kXBARB_InputCmp3Output	CMP3 Output output assigned to XBARB_IN3 input.
kXBARB_InputFtm0Match	FTM0 all channels match trigger ORed together output assigned to XBARB_IN4 input.
kXBARB_InputFtm0Extrig	FTM0 counter init trigger output assigned to XBARB_IN5 input.
kXBARB_InputFtm3Match	FTM3 all channels match trigger ORed together output assigned to XBARB_IN6 input.
kXBARB_InputFtm3Extrig	FTM3 counter init trigger output assigned to XBARB_IN7 input.
kXBARB_InputPwm0Ch0Trg0	PWMA channel 0 trigger 0 output assigned to XBARB_IN8 input.
kXBARB_InputPwm0Ch1Trg0	PWMA channel 1 trigger 0 output assigned to XBARB_IN9 input.
kXBARB_InputPwm0Ch2Trg0	PWMA channel 2 trigger 0 output assigned to XBARB_IN10 input.
kXBARB_InputPwm0Ch3Trg0	PWMA channel 3 trigger 0 output assigned to XBARB_IN11 input.
kXBARB_InputPdb0Ch0Output	PDB0 channel 0 output trigger output assigned to XBARB_IN12 input.
kXBARB_InputHsadc0Cca	High Speed Analog-to-Digital Converter 0 conversion A complete output assigned to XBARB_IN13 input.
kXBARB_InputXbarIn2	XB_IN2 input pin output assigned to XBARB_IN14 input.
kXBARB_InputXbarIn3	XB_IN3 input pin output assigned to XBARB_IN15 input.
kXBARB_InputFtm1Match	FTM1 all channels match trigger ORed together output assigned to XBARB_IN16 input.
kXBARB_InputFtm1Extrig	FTM1 counter init trigger output assigned to XBARB_IN17 input.
kXBARB_InputDmaCh0Done	DMA channel 0 done output assigned to XBARB_IN18 input.
kXBARB_InputDmaCh1Done	DMA channel 1 done output assigned to XBARB_IN19 input.
kXBARB_InputXbarIn10	XB_IN10 input pin output assigned to XBARB_IN20 input.
kXBARB_InputXbarIn11	XB_IN11 input pin output assigned to XBARB_IN21 input.
kXBARB_InputDmaCh6Done	DMA channel 6 done output assigned to XBARB_IN22 input.
kXBARB_InputDmaCh7Done	DMA channel 7 done output assigned to XBARB_IN23 input.
kXBARB_InputPitTrigger0	PIT trigger 0 output assigned to XBARB_IN24 input.
kXBARB_InputPitTrigger1	PIT trigger 1 output assigned to XBARB_IN25 input.
kXBARB_InputPdb1Ch0Output	PDB1 channel 0 output trigger output assigned to XBARB_IN26 input.
kXBARB_InputHsadc0Ccb	High Speed Analog-to-Digital Converter 0 conversion B complete output assigned to XBARB_IN27 input.
kXBARB_InputPwm1Ch0Trg0OrTrg1	PWMB channel 0 trigger 0 or trigger 1 output assigned to XBARB_IN28 input.
kXBARB_InputPwm1Ch1Trg0OrTrg1	PWMB channel 1 trigger 0 or trigger 1 output assigned to XBARB_IN29 input.
kXBARB_InputPwm1Ch2Trg0OrTrg1	PWMB channel 2 trigger 0 or trigger 1 output assigned to XBARB_IN30 input.
kXBARB_InputPwm1Ch3Trg0OrTrg1	PWMB channel 3 trigger 0 or trigger 1 output assigned to XBARB_IN31 input.
kXBARB_InputFtm2Match	FTM2 all channels match trigger ORed together output assigned to XBARB_IN32 input.
kXBARB_InputFtm2Extrig	FTM2 counter init trigger output assigned to XBARB_IN33 input.
kXBARB_InputPdb0Ch1Output	PDB0 channel 1 output trigger output assigned to XBARB_IN34 input.
kXBARB_InputPdb1Ch1Output	PDB1 channel 1 output trigger output assigned to XBARB_IN35 input.
kXBARB_InputHsadc1Cca	High Speed Analog-to-Digital Converter 1 conversion A complete output assigned to XBARB_IN36 input.
kXBARB_InputHsadc1Ccb	High Speed Analog-to-Digital Converter 1 conversion B complete output assigned to XBARB_IN37 input.
kXBARB_InputAdc0Coco	Analog-to-Digital Converter 0 conversion complete output assigned to XBARB_IN38 input.

_xbar_output_signal

enum _xbar_output_signal

Enumerator
kXBARA_OutputDmamux18	XBARA_OUT0 output assigned to DMAMUX slot 18
kXBARA_OutputDmamux19	XBARA_OUT1 output assigned to DMAMUX slot 19
kXBARA_OutputDmamux20	XBARA_OUT2 output assigned to DMAMUX slot 20
kXBARA_OutputDmamux21	XBARA_OUT3 output assigned to DMAMUX slot 21
kXBARA_OutputXbOut4	XBARA_OUT4 output assigned to XBAROUT4 output pin
kXBARA_OutputXbOut5	XBARA_OUT5 output assigned to XBAROUT5 output pin
kXBARA_OutputXbOut6	XBARA_OUT6 output assigned to XBAROUT6 output pin
kXBARA_OutputXbOut7	XBARA_OUT7 output assigned to XBAROUT7 output pin
kXBARA_OutputXbOut8	XBARA_OUT8 output assigned to XBAROUT8 output pin
kXBARA_OutputXbOut9	XBARA_OUT9 output assigned to XBAROUT9 output pin
kXBARA_OutputXbOut10	XBARA_OUT10 output assigned to XBAROUT10 output pin
kXBARA_OutputXbOut11	XBARA_OUT11 output assigned to XBAROUT11 output pin
kXBARA_OutputHsadc0ATrig	XBARA_OUT12 output assigned to HSADC0 converter A trigger
kXBARA_OutputHsadc0BTrig	XBARA_OUT13 output assigned to HSADC0 converter B trigger
kXBARA_OutputRESERVED14	XBARA_OUT14 output is reserved.
kXBARA_OutputDac12bSync	XBARA_OUT15 output assigned to DAC synchronisation trigger
kXBARA_OutputCmp0	XBARA_OUT16 output assigned to CMP0 window/sample
kXBARA_OutputCmp1	XBARA_OUT17 output assigned to CMP1 window/sample
kXBARA_OutputCmp2	XBARA_OUT18 output assigned to CMP2 window/sample
kXBARA_OutputCmp3	XBARA_OUT19 output assigned to CMP3 window/sample
kXBARA_OutputPwmCh0ExtA	XBARA_OUT20 output assigned to PWM0 and PWM1 channel 0 external control A
kXBARA_OutputPwmCh1ExtA	XBARA_OUT21 output assigned to PWM0 and PWM1 channel 1 external control A
kXBARA_OutputPwmCh2ExtA	XBARA_OUT22 output assigned to PWM0 and PWM1 channel 2 external control A
kXBARA_OutputPwmCh3ExtA	XBARA_OUT23 output assigned to PWM0 and PWM1 channel 3 external control A
kXBARA_OutputPwm0Ch0ExtSync	XBARA_OUT24 output assigned to PWM0 channel 0 external synchronization
kXBARA_OutputPwm0Ch1ExtSync	XBARA_OUT25 output assigned to PWM0 channel 1 external synchronization
kXBARA_OutputPwm0Ch2ExtSync	XBARA_OUT26 output assigned to PWM0 channel 2 external synchronization
kXBARA_OutputPwm0Ch3ExtSync	XBARA_OUT27 output assigned to PWM0 channel 3 external synchronization
kXBARA_OutputPwmExtClk	XBARA_OUT28 output assigned to PWM0 and PWM1 external clock
kXBARA_OutputPwm0Fault0	XBARA_OUT29 output assigned to PWM0 and PWM1 fault 0
kXBARA_OutputPwm0Fault1	XBARA_OUT30 output assigned to PWM0 and PWM1 fault 1
kXBARA_OutputPwm0Fault2	XBARA_OUT31 output assigned to PWM0 and PWM1 fault 2
kXBARA_OutputPwm0Fault3	XBARA_OUT32 output assigned to PWM0 and PWM1 fault 3
kXBARA_OutputPwm0Force	XBARA_OUT33 output assigned to PWM0 external output force
kXBARA_OutputFtm0Trig2	XBARA_OUT34 output assigned to FTM0 hardware trigger 2
kXBARA_OutputFtm1Trig2	XBARA_OUT35 output assigned to FTM1 hardware trigger 2
kXBARA_OutputFtm2Trig2	XBARA_OUT36 output assigned to FTM2 hardware trigger 2
kXBARA_OutputFtm3Trig2	XBARA_OUT37 output assigned to FTM3 hardware trigger 2
kXBARA_OutputPdb0InCh12	XBARA_OUT38 output assigned to PDB0 trigger option 12
kXBARA_OutputAdc0Hdwt	XBARA_OUT39 output assigned to ADC0 hardware trigger
kXBARA_OutputRESERVED40	XBARA_OUT40 output is reserved.
kXBARA_OutputPdb1InCh12	XBARA_OUT41 output assigned to PDB1 trigger option 12
kXBARA_OutputHsadc1ATrig	XBARA_OUT42 output assigned to HSADC1 converter A trigger and FTM1 channel 1 signal XOR input
kXBARA_OutputHsadc1BTrig	XBARA_OUT43 output assigned to HSADC1 converter B trigger
kXBARA_OutputEncPhA	XBARA_OUT44 output assigned to ENC quadrature waveform phase A
kXBARA_OutputEncPhB	XBARA_OUT45 output assigned to ENC quadrature waveform phase B
kXBARA_OutputEncIndex	XBARA_OUT46 output assigned to ENC refresh/reload
kXBARA_OutputEncHome	XBARA_OUT47 output assigned to ENC home position
kXBARA_OutputEncCapTrigger	XBARA_OUT48 output assigned to ENC clear/snapshot
kXBARA_OutputFtm0Fault3	XBARA_OUT49 output assigned to FTM0 fault 3
kXBARA_OutputFtm1Fault1	XBARA_OUT50 output assigned to FTM1 fault 1
kXBARA_OutputFtm2Fault1	XBARA_OUT51 output assigned to FTM2 fault 1
kXBARA_OutputFtm3Fault3	XBARA_OUT52 output assigned to FTM3 fault 3
kXBARA_OutputPwm1Ch0ExtSync	XBARA_OUT53 output assigned to PWM0 and PWM1 channel 0 external synchronization
kXBARA_OutputPwm1Ch1ExtSync	XBARA_OUT54 output assigned to PWM0 and PWM1 channel 1 external synchronization
kXBARA_OutputPwm1Ch2ExtSync	XBARA_OUT55 output assigned to PWM0 and PWM1 channel 2 external synchronization
kXBARA_OutputPwm1Ch3ExtSync	XBARA_OUT56 output assigned to PWM0 and PWM1 channel 3 external synchronization
kXBARA_OutputPwm1Force	XBARA_OUT57 output assigned to PWM1 external output force
kXBARA_OutputEwmIn	XBARA_OUT58 output assigned to EWM input
kXBARB_OutputAoiIn0	XBARB_OUT0 output assigned to AOI input0
kXBARB_OutputAoiIn1	XBARB_OUT1 output assigned to AOI input1
kXBARB_OutputAoiIn2	XBARB_OUT2 output assigned to AOI input2
kXBARB_OutputAoiIn3	XBARB_OUT3 output assigned to AOI input3
kXBARB_OutputAoiIn4	XBARB_OUT4 output assigned to AOI input4
kXBARB_OutputAoiIn5	XBARB_OUT5 output assigned to AOI input5
kXBARB_OutputAoiIn6	XBARB_OUT6 output assigned to AOI input6
kXBARB_OutputAoiIn7	XBARB_OUT7 output assigned to AOI input7
kXBARB_OutputAoiIn8	XBARB_OUT8 output assigned to AOI input8
kXBARB_OutputAoiIn9	XBARB_OUT9 output assigned to AOI input9
kXBARB_OutputAoiIn10	XBARB_OUT10 output assigned to AOI input10
kXBARB_OutputAoiIn11	XBARB_OUT11 output assigned to AOI input11
kXBARB_OutputAoiIn12	XBARB_OUT12 output assigned to AOI input12
kXBARB_OutputAoiIn13	XBARB_OUT13 output assigned to AOI input13
kXBARB_OutputAoiIn14	XBARB_OUT14 output assigned to AOI input14
kXBARB_OutputAoiIn15	XBARB_OUT15 output assigned to AOI input15