mikroSDK Reference Manual
stm32f107xc.h
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1
37#ifndef __STM32F107xC_H
38#define __STM32F107xC_H
39
40#ifdef __cplusplus
41 extern "C" {
42#endif
43
50#define __CM3_REV 0x0200U
51 #define __MPU_PRESENT 0U
52#define __NVIC_PRIO_BITS 4U
53#define __Vendor_SysTickConfig 0U
69typedef enum
70{
71/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
72 NonMaskableInt_IRQn = -14,
73 HardFault_IRQn = -13,
74 MemoryManagement_IRQn = -12,
75 BusFault_IRQn = -11,
76 UsageFault_IRQn = -10,
77 SVCall_IRQn = -5,
78 DebugMonitor_IRQn = -4,
79 PendSV_IRQn = -2,
80 SysTick_IRQn = -1,
82/****** STM32 specific Interrupt Numbers *********************************************************/
83 WWDG_IRQn = 0,
84 PVD_IRQn = 1,
85 TAMPER_IRQn = 2,
86 RTC_IRQn = 3,
87 FLASH_IRQn = 4,
88 RCC_IRQn = 5,
89 EXTI0_IRQn = 6,
90 EXTI1_IRQn = 7,
91 EXTI2_IRQn = 8,
92 EXTI3_IRQn = 9,
93 EXTI4_IRQn = 10,
94 DMA1_Channel1_IRQn = 11,
95 DMA1_Channel2_IRQn = 12,
96 DMA1_Channel3_IRQn = 13,
97 DMA1_Channel4_IRQn = 14,
98 DMA1_Channel5_IRQn = 15,
99 DMA1_Channel6_IRQn = 16,
100 DMA1_Channel7_IRQn = 17,
101 ADC1_2_IRQn = 18,
102 CAN1_TX_IRQn = 19,
103 CAN1_RX0_IRQn = 20,
104 CAN1_RX1_IRQn = 21,
105 CAN1_SCE_IRQn = 22,
106 EXTI9_5_IRQn = 23,
107 TIM1_BRK_IRQn = 24,
108 TIM1_UP_IRQn = 25,
109 TIM1_TRG_COM_IRQn = 26,
110 TIM1_CC_IRQn = 27,
111 TIM2_IRQn = 28,
112 TIM3_IRQn = 29,
113 TIM4_IRQn = 30,
114 I2C1_EV_IRQn = 31,
115 I2C1_ER_IRQn = 32,
116 I2C2_EV_IRQn = 33,
117 I2C2_ER_IRQn = 34,
118 SPI1_IRQn = 35,
119 SPI2_IRQn = 36,
120 USART1_IRQn = 37,
121 USART2_IRQn = 38,
122 USART3_IRQn = 39,
123 EXTI15_10_IRQn = 40,
124 RTC_Alarm_IRQn = 41,
125 OTG_FS_WKUP_IRQn = 42,
126 TIM5_IRQn = 50,
127 SPI3_IRQn = 51,
128 UART4_IRQn = 52,
129 UART5_IRQn = 53,
130 TIM6_IRQn = 54,
131 TIM7_IRQn = 55,
132 DMA2_Channel1_IRQn = 56,
133 DMA2_Channel2_IRQn = 57,
134 DMA2_Channel3_IRQn = 58,
135 DMA2_Channel4_IRQn = 59,
136 DMA2_Channel5_IRQn = 60,
137 ETH_IRQn = 61,
138 ETH_WKUP_IRQn = 62,
139 CAN2_TX_IRQn = 63,
140 CAN2_RX0_IRQn = 64,
141 CAN2_RX1_IRQn = 65,
142 CAN2_SCE_IRQn = 66,
143 OTG_FS_IRQn = 67
144} IRQn_Type;
145
150#include "core_cm3.h"
151#include "system_stm32f1xx.h"
152#include <stdint.h>
153
162typedef struct
163{
164 __IO uint32_t SR;
165 __IO uint32_t CR1;
166 __IO uint32_t CR2;
167 __IO uint32_t SMPR1;
168 __IO uint32_t SMPR2;
169 __IO uint32_t JOFR1;
170 __IO uint32_t JOFR2;
171 __IO uint32_t JOFR3;
172 __IO uint32_t JOFR4;
173 __IO uint32_t HTR;
174 __IO uint32_t LTR;
175 __IO uint32_t SQR1;
176 __IO uint32_t SQR2;
177 __IO uint32_t SQR3;
178 __IO uint32_t JSQR;
179 __IO uint32_t JDR1;
180 __IO uint32_t JDR2;
181 __IO uint32_t JDR3;
182 __IO uint32_t JDR4;
183 __IO uint32_t DR;
184} ADC_TypeDef;
185
186typedef struct
187{
188 __IO uint32_t SR;
189 __IO uint32_t CR1;
190 __IO uint32_t CR2;
191 uint32_t RESERVED[16];
192 __IO uint32_t DR;
193} ADC_Common_TypeDef;
194
199typedef struct
200{
201 uint32_t RESERVED0;
202 __IO uint32_t DR1;
203 __IO uint32_t DR2;
204 __IO uint32_t DR3;
205 __IO uint32_t DR4;
206 __IO uint32_t DR5;
207 __IO uint32_t DR6;
208 __IO uint32_t DR7;
209 __IO uint32_t DR8;
210 __IO uint32_t DR9;
211 __IO uint32_t DR10;
212 __IO uint32_t RTCCR;
213 __IO uint32_t CR;
214 __IO uint32_t CSR;
215 uint32_t RESERVED13[2];
216 __IO uint32_t DR11;
217 __IO uint32_t DR12;
218 __IO uint32_t DR13;
219 __IO uint32_t DR14;
220 __IO uint32_t DR15;
221 __IO uint32_t DR16;
222 __IO uint32_t DR17;
223 __IO uint32_t DR18;
224 __IO uint32_t DR19;
225 __IO uint32_t DR20;
226 __IO uint32_t DR21;
227 __IO uint32_t DR22;
228 __IO uint32_t DR23;
229 __IO uint32_t DR24;
230 __IO uint32_t DR25;
231 __IO uint32_t DR26;
232 __IO uint32_t DR27;
233 __IO uint32_t DR28;
234 __IO uint32_t DR29;
235 __IO uint32_t DR30;
236 __IO uint32_t DR31;
237 __IO uint32_t DR32;
238 __IO uint32_t DR33;
239 __IO uint32_t DR34;
240 __IO uint32_t DR35;
241 __IO uint32_t DR36;
242 __IO uint32_t DR37;
243 __IO uint32_t DR38;
244 __IO uint32_t DR39;
245 __IO uint32_t DR40;
246 __IO uint32_t DR41;
247 __IO uint32_t DR42;
248} BKP_TypeDef;
249
254typedef struct
255{
256 __IO uint32_t TIR;
257 __IO uint32_t TDTR;
258 __IO uint32_t TDLR;
259 __IO uint32_t TDHR;
260} CAN_TxMailBox_TypeDef;
261
266typedef struct
267{
268 __IO uint32_t RIR;
269 __IO uint32_t RDTR;
270 __IO uint32_t RDLR;
271 __IO uint32_t RDHR;
272} CAN_FIFOMailBox_TypeDef;
273
278typedef struct
279{
280 __IO uint32_t FR1;
281 __IO uint32_t FR2;
282} CAN_FilterRegister_TypeDef;
283
288typedef struct
289{
290 __IO uint32_t MCR;
291 __IO uint32_t MSR;
292 __IO uint32_t TSR;
293 __IO uint32_t RF0R;
294 __IO uint32_t RF1R;
295 __IO uint32_t IER;
296 __IO uint32_t ESR;
297 __IO uint32_t BTR;
298 uint32_t RESERVED0[88];
299 CAN_TxMailBox_TypeDef sTxMailBox[3];
300 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
301 uint32_t RESERVED1[12];
302 __IO uint32_t FMR;
303 __IO uint32_t FM1R;
304 uint32_t RESERVED2;
305 __IO uint32_t FS1R;
306 uint32_t RESERVED3;
307 __IO uint32_t FFA1R;
308 uint32_t RESERVED4;
309 __IO uint32_t FA1R;
310 uint32_t RESERVED5[8];
311 CAN_FilterRegister_TypeDef sFilterRegister[28];
312} CAN_TypeDef;
313
318typedef struct
319{
320 __IO uint32_t DR;
321 __IO uint8_t IDR;
322 uint8_t RESERVED0;
323 uint16_t RESERVED1;
324 __IO uint32_t CR;
325} CRC_TypeDef;
326
331typedef struct
332{
333 __IO uint32_t CR;
334 __IO uint32_t SWTRIGR;
335 __IO uint32_t DHR12R1;
336 __IO uint32_t DHR12L1;
337 __IO uint32_t DHR8R1;
338 __IO uint32_t DHR12R2;
339 __IO uint32_t DHR12L2;
340 __IO uint32_t DHR8R2;
341 __IO uint32_t DHR12RD;
342 __IO uint32_t DHR12LD;
343 __IO uint32_t DHR8RD;
344 __IO uint32_t DOR1;
345 __IO uint32_t DOR2;
346} DAC_TypeDef;
347
352typedef struct
353{
354 __IO uint32_t IDCODE;
355 __IO uint32_t CR;
356}DBGMCU_TypeDef;
357
362typedef struct
363{
364 __IO uint32_t CCR;
365 __IO uint32_t CNDTR;
366 __IO uint32_t CPAR;
367 __IO uint32_t CMAR;
368} DMA_Channel_TypeDef;
369
370typedef struct
371{
372 __IO uint32_t ISR;
373 __IO uint32_t IFCR;
374} DMA_TypeDef;
375
376
377
382typedef struct
383{
384 __IO uint32_t MACCR;
385 __IO uint32_t MACFFR;
386 __IO uint32_t MACHTHR;
387 __IO uint32_t MACHTLR;
388 __IO uint32_t MACMIIAR;
389 __IO uint32_t MACMIIDR;
390 __IO uint32_t MACFCR;
391 __IO uint32_t MACVLANTR; /* 8 */
392 uint32_t RESERVED0[2];
393 __IO uint32_t MACRWUFFR; /* 11 */
394 __IO uint32_t MACPMTCSR;
395 uint32_t RESERVED1[2];
396 __IO uint32_t MACSR; /* 15 */
397 __IO uint32_t MACIMR;
398 __IO uint32_t MACA0HR;
399 __IO uint32_t MACA0LR;
400 __IO uint32_t MACA1HR;
401 __IO uint32_t MACA1LR;
402 __IO uint32_t MACA2HR;
403 __IO uint32_t MACA2LR;
404 __IO uint32_t MACA3HR;
405 __IO uint32_t MACA3LR; /* 24 */
406 uint32_t RESERVED2[40];
407 __IO uint32_t MMCCR; /* 65 */
408 __IO uint32_t MMCRIR;
409 __IO uint32_t MMCTIR;
410 __IO uint32_t MMCRIMR;
411 __IO uint32_t MMCTIMR; /* 69 */
412 uint32_t RESERVED3[14];
413 __IO uint32_t MMCTGFSCCR; /* 84 */
414 __IO uint32_t MMCTGFMSCCR;
415 uint32_t RESERVED4[5];
416 __IO uint32_t MMCTGFCR;
417 uint32_t RESERVED5[10];
418 __IO uint32_t MMCRFCECR;
419 __IO uint32_t MMCRFAECR;
420 uint32_t RESERVED6[10];
421 __IO uint32_t MMCRGUFCR;
422 uint32_t RESERVED7[334];
423 __IO uint32_t PTPTSCR;
424 __IO uint32_t PTPSSIR;
425 __IO uint32_t PTPTSHR;
426 __IO uint32_t PTPTSLR;
427 __IO uint32_t PTPTSHUR;
428 __IO uint32_t PTPTSLUR;
429 __IO uint32_t PTPTSAR;
430 __IO uint32_t PTPTTHR;
431 __IO uint32_t PTPTTLR;
432 uint32_t RESERVED8[567];
433 __IO uint32_t DMABMR;
434 __IO uint32_t DMATPDR;
435 __IO uint32_t DMARPDR;
436 __IO uint32_t DMARDLAR;
437 __IO uint32_t DMATDLAR;
438 __IO uint32_t DMASR;
439 __IO uint32_t DMAOMR;
440 __IO uint32_t DMAIER;
441 __IO uint32_t DMAMFBOCR;
442 uint32_t RESERVED9[9];
443 __IO uint32_t DMACHTDR;
444 __IO uint32_t DMACHRDR;
445 __IO uint32_t DMACHTBAR;
446 __IO uint32_t DMACHRBAR;
447} ETH_TypeDef;
448
449
454typedef struct
455{
456 __IO uint32_t IMR;
457 __IO uint32_t EMR;
458 __IO uint32_t RTSR;
459 __IO uint32_t FTSR;
460 __IO uint32_t SWIER;
461 __IO uint32_t PR;
462} EXTI_TypeDef;
463
468typedef struct
469{
470 __IO uint32_t ACR;
471 __IO uint32_t KEYR;
472 __IO uint32_t OPTKEYR;
473 __IO uint32_t SR;
474 __IO uint32_t CR;
475 __IO uint32_t AR;
476 __IO uint32_t RESERVED;
477 __IO uint32_t OBR;
478 __IO uint32_t WRPR;
479} FLASH_TypeDef;
480
485typedef struct
486{
487 __IO uint16_t RDP;
488 __IO uint16_t USER;
489 __IO uint16_t Data0;
490 __IO uint16_t Data1;
491 __IO uint16_t WRP0;
492 __IO uint16_t WRP1;
493 __IO uint16_t WRP2;
494 __IO uint16_t WRP3;
495} OB_TypeDef;
496
501typedef struct
502{
503 __IO uint32_t CRL;
504 __IO uint32_t CRH;
505 __IO uint32_t IDR;
506 __IO uint32_t ODR;
507 __IO uint32_t BSRR;
508 __IO uint32_t BRR;
509 __IO uint32_t LCKR;
510} GPIO_TypeDef;
511
516typedef struct
517{
518 __IO uint32_t EVCR;
519 __IO uint32_t MAPR;
520 __IO uint32_t EXTICR[4];
521 uint32_t RESERVED0;
522 __IO uint32_t MAPR2;
523} AFIO_TypeDef;
528typedef struct
529{
530 __IO uint32_t CR1;
531 __IO uint32_t CR2;
532 __IO uint32_t OAR1;
533 __IO uint32_t OAR2;
534 __IO uint32_t DR;
535 __IO uint32_t SR1;
536 __IO uint32_t SR2;
537 __IO uint32_t CCR;
538 __IO uint32_t TRISE;
539} I2C_TypeDef;
540
545typedef struct
546{
547 __IO uint32_t KR;
548 __IO uint32_t PR;
549 __IO uint32_t RLR;
550 __IO uint32_t SR;
551} IWDG_TypeDef;
552
557typedef struct
558{
559 __IO uint32_t CR;
560 __IO uint32_t CSR;
561} PWR_TypeDef;
562
567typedef struct
568{
569 __IO uint32_t CR;
570 __IO uint32_t CFGR;
571 __IO uint32_t CIR;
572 __IO uint32_t APB2RSTR;
573 __IO uint32_t APB1RSTR;
574 __IO uint32_t AHBENR;
575 __IO uint32_t APB2ENR;
576 __IO uint32_t APB1ENR;
577 __IO uint32_t BDCR;
578 __IO uint32_t CSR;
579
580 __IO uint32_t AHBRSTR;
581 __IO uint32_t CFGR2;
582
583} RCC_TypeDef;
584
589typedef struct
590{
591 __IO uint32_t CRH;
592 __IO uint32_t CRL;
593 __IO uint32_t PRLH;
594 __IO uint32_t PRLL;
595 __IO uint32_t DIVH;
596 __IO uint32_t DIVL;
597 __IO uint32_t CNTH;
598 __IO uint32_t CNTL;
599 __IO uint32_t ALRH;
600 __IO uint32_t ALRL;
601} RTC_TypeDef;
602
607typedef struct
608{
609 __IO uint32_t CR1;
610 __IO uint32_t CR2;
611 __IO uint32_t SR;
612 __IO uint32_t DR;
613 __IO uint32_t CRCPR;
614 __IO uint32_t RXCRCR;
615 __IO uint32_t TXCRCR;
616 __IO uint32_t I2SCFGR;
617 __IO uint32_t I2SPR;
618} SPI_TypeDef;
619
623typedef struct
624{
625 __IO uint32_t CR1;
626 __IO uint32_t CR2;
627 __IO uint32_t SMCR;
628 __IO uint32_t DIER;
629 __IO uint32_t SR;
630 __IO uint32_t EGR;
631 __IO uint32_t CCMR1;
632 __IO uint32_t CCMR2;
633 __IO uint32_t CCER;
634 __IO uint32_t CNT;
635 __IO uint32_t PSC;
636 __IO uint32_t ARR;
637 __IO uint32_t RCR;
638 __IO uint32_t CCR1;
639 __IO uint32_t CCR2;
640 __IO uint32_t CCR3;
641 __IO uint32_t CCR4;
642 __IO uint32_t BDTR;
643 __IO uint32_t DCR;
644 __IO uint32_t DMAR;
645 __IO uint32_t OR;
646}TIM_TypeDef;
647
648
653typedef struct
654{
655 __IO uint32_t SR;
656 __IO uint32_t DR;
657 __IO uint32_t BRR;
658 __IO uint32_t CR1;
659 __IO uint32_t CR2;
660 __IO uint32_t CR3;
661 __IO uint32_t GTPR;
662} USART_TypeDef;
663
664
669typedef struct
670{
671 __IO uint32_t GOTGCTL;
672 __IO uint32_t GOTGINT;
673 __IO uint32_t GAHBCFG;
674 __IO uint32_t GUSBCFG;
675 __IO uint32_t GRSTCTL;
676 __IO uint32_t GINTSTS;
677 __IO uint32_t GINTMSK;
678 __IO uint32_t GRXSTSR;
679 __IO uint32_t GRXSTSP;
680 __IO uint32_t GRXFSIZ;
681 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
682 __IO uint32_t HNPTXSTS;
683 uint32_t Reserved30[2];
684 __IO uint32_t GCCFG;
685 __IO uint32_t CID;
686 uint32_t Reserved40[48];
687 __IO uint32_t HPTXFSIZ;
688 __IO uint32_t DIEPTXF[0x0F];
689} USB_OTG_GlobalTypeDef;
690
695typedef struct
696{
697 __IO uint32_t DCFG;
698 __IO uint32_t DCTL;
699 __IO uint32_t DSTS;
700 uint32_t Reserved0C;
701 __IO uint32_t DIEPMSK;
702 __IO uint32_t DOEPMSK;
703 __IO uint32_t DAINT;
704 __IO uint32_t DAINTMSK;
705 uint32_t Reserved20;
706 uint32_t Reserved9;
707 __IO uint32_t DVBUSDIS;
708 __IO uint32_t DVBUSPULSE;
709 __IO uint32_t DTHRCTL;
710 __IO uint32_t DIEPEMPMSK;
711 __IO uint32_t DEACHINT;
712 __IO uint32_t DEACHMSK;
713 uint32_t Reserved40;
714 __IO uint32_t DINEP1MSK;
715 uint32_t Reserved44[15];
716 __IO uint32_t DOUTEP1MSK;
717} USB_OTG_DeviceTypeDef;
718
723typedef struct
724{
725 __IO uint32_t DIEPCTL;
726 uint32_t Reserved04;
727 __IO uint32_t DIEPINT;
728 uint32_t Reserved0C;
729 __IO uint32_t DIEPTSIZ;
730 __IO uint32_t DIEPDMA;
731 __IO uint32_t DTXFSTS;
732 uint32_t Reserved18;
733} USB_OTG_INEndpointTypeDef;
734
739typedef struct
740{
741 __IO uint32_t DOEPCTL;
742 uint32_t Reserved04;
743 __IO uint32_t DOEPINT;
744 uint32_t Reserved0C;
745 __IO uint32_t DOEPTSIZ;
746 __IO uint32_t DOEPDMA;
747 uint32_t Reserved18[2];
748} USB_OTG_OUTEndpointTypeDef;
749
754typedef struct
755{
756 __IO uint32_t HCFG;
757 __IO uint32_t HFIR;
758 __IO uint32_t HFNUM;
759 uint32_t Reserved40C;
760 __IO uint32_t HPTXSTS;
761 __IO uint32_t HAINT;
762 __IO uint32_t HAINTMSK;
763} USB_OTG_HostTypeDef;
764
769typedef struct
770{
771 __IO uint32_t HCCHAR;
772 __IO uint32_t HCSPLT;
773 __IO uint32_t HCINT;
774 __IO uint32_t HCINTMSK;
775 __IO uint32_t HCTSIZ;
776 __IO uint32_t HCDMA;
777 uint32_t Reserved[2];
778} USB_OTG_HostChannelTypeDef;
779
784typedef struct
785{
786 __IO uint32_t CR;
787 __IO uint32_t CFR;
788 __IO uint32_t SR;
789} WWDG_TypeDef;
790
800#define FLASH_BASE 0x08000000UL
801#define FLASH_BANK1_END 0x0803FFFFUL
802#define SRAM_BASE 0x20000000UL
803#define PERIPH_BASE 0x40000000UL
805#define SRAM_BB_BASE 0x22000000UL
806#define PERIPH_BB_BASE 0x42000000UL
810#define APB1PERIPH_BASE PERIPH_BASE
811#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
812#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
813
814#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
815#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
816#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
817#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL)
818#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)
819#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)
820#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
821#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
822#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
823#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
824#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)
825#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
826#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
827#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)
828#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)
829#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
830#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
831#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)
832#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800UL)
833#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)
834#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
835#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)
836#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)
837#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
838#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)
839#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)
840#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)
841#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)
842#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)
843#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
844#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)
845#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
846#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
847#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
848
849
850#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
851#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
852#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
853#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)
854#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)
855#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)
856#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)
857#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)
858#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL)
859#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL)
860#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL)
861#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL)
862#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL)
863#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL)
864#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
865#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
866
867#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
868#define FLASHSIZE_BASE 0x1FFFF7E0UL
869#define UID_BASE 0x1FFFF7E8UL
870#define OB_BASE 0x1FFFF800UL
872#define ETH_BASE (AHBPERIPH_BASE + 0x00008000UL)
873#define ETH_MAC_BASE (ETH_BASE)
874#define ETH_MMC_BASE (ETH_BASE + 0x00000100UL)
875#define ETH_PTP_BASE (ETH_BASE + 0x00000700UL)
876#define ETH_DMA_BASE (ETH_BASE + 0x00001000UL)
877
878
879#define DBGMCU_BASE 0xE0042000UL
883#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
884
885#define USB_OTG_GLOBAL_BASE 0x00000000UL
886#define USB_OTG_DEVICE_BASE 0x00000800UL
887#define USB_OTG_IN_ENDPOINT_BASE 0x00000900UL
888#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL
889#define USB_OTG_EP_REG_SIZE 0x00000020UL
890#define USB_OTG_HOST_BASE 0x00000400UL
891#define USB_OTG_HOST_PORT_BASE 0x00000440UL
892#define USB_OTG_HOST_CHANNEL_BASE 0x00000500UL
893#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL
894#define USB_OTG_PCGCCTL_BASE 0x00000E00UL
895#define USB_OTG_FIFO_BASE 0x00001000UL
896#define USB_OTG_FIFO_SIZE 0x00001000UL
897
906#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
907#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
908#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
909#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
910#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
911#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
912#define RTC ((RTC_TypeDef *)RTC_BASE)
913#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
914#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
915#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
916#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
917#define USART2 ((USART_TypeDef *)USART2_BASE)
918#define USART3 ((USART_TypeDef *)USART3_BASE)
919#define UART4 ((USART_TypeDef *)UART4_BASE)
920#define UART5 ((USART_TypeDef *)UART5_BASE)
921#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
922#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
923#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
924#define CAN2 ((CAN_TypeDef *)CAN2_BASE)
925#define BKP ((BKP_TypeDef *)BKP_BASE)
926#define PWR ((PWR_TypeDef *)PWR_BASE)
927#define DAC1 ((DAC_TypeDef *)DAC_BASE)
928#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
929#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
930#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
931#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
932#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
933#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
934#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
935#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
936#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
937#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
938#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
939#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
940#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
941#define USART1 ((USART_TypeDef *)USART1_BASE)
942#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
943#define DMA2 ((DMA_TypeDef *)DMA2_BASE)
944#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
945#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
946#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
947#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
948#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
949#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
950#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
951#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
952#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
953#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
954#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
955#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
956#define RCC ((RCC_TypeDef *)RCC_BASE)
957#define CRC ((CRC_TypeDef *)CRC_BASE)
958#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
959#define OB ((OB_TypeDef *)OB_BASE)
960#define ETH ((ETH_TypeDef *) ETH_BASE)
961#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
962
963#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE)
964
976#define LSI_STARTUP_TIME 85U
985/******************************************************************************/
986/* Peripheral Registers_Bits_Definition */
987/******************************************************************************/
988
989/******************************************************************************/
990/* */
991/* CRC calculation unit (CRC) */
992/* */
993/******************************************************************************/
994
995/******************* Bit definition for CRC_DR register *********************/
996#define CRC_DR_DR_Pos (0U)
997#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
998#define CRC_DR_DR CRC_DR_DR_Msk
1000/******************* Bit definition for CRC_IDR register ********************/
1001#define CRC_IDR_IDR_Pos (0U)
1002#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
1003#define CRC_IDR_IDR CRC_IDR_IDR_Msk
1005/******************** Bit definition for CRC_CR register ********************/
1006#define CRC_CR_RESET_Pos (0U)
1007#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
1008#define CRC_CR_RESET CRC_CR_RESET_Msk
1010/******************************************************************************/
1011/* */
1012/* Power Control */
1013/* */
1014/******************************************************************************/
1015
1016/******************** Bit definition for PWR_CR register ********************/
1017#define PWR_CR_LPDS_Pos (0U)
1018#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
1019#define PWR_CR_LPDS PWR_CR_LPDS_Msk
1020#define PWR_CR_PDDS_Pos (1U)
1021#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
1022#define PWR_CR_PDDS PWR_CR_PDDS_Msk
1023#define PWR_CR_CWUF_Pos (2U)
1024#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
1025#define PWR_CR_CWUF PWR_CR_CWUF_Msk
1026#define PWR_CR_CSBF_Pos (3U)
1027#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
1028#define PWR_CR_CSBF PWR_CR_CSBF_Msk
1029#define PWR_CR_PVDE_Pos (4U)
1030#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
1031#define PWR_CR_PVDE PWR_CR_PVDE_Msk
1033#define PWR_CR_PLS_Pos (5U)
1034#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
1035#define PWR_CR_PLS PWR_CR_PLS_Msk
1036#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
1037#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
1038#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
1041#define PWR_CR_PLS_LEV0 0x00000000U
1042#define PWR_CR_PLS_LEV1 0x00000020U
1043#define PWR_CR_PLS_LEV2 0x00000040U
1044#define PWR_CR_PLS_LEV3 0x00000060U
1045#define PWR_CR_PLS_LEV4 0x00000080U
1046#define PWR_CR_PLS_LEV5 0x000000A0U
1047#define PWR_CR_PLS_LEV6 0x000000C0U
1048#define PWR_CR_PLS_LEV7 0x000000E0U
1050/* Legacy defines */
1051#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
1052#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
1053#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
1054#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
1055#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
1056#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
1057#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
1058#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
1059
1060#define PWR_CR_DBP_Pos (8U)
1061#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
1062#define PWR_CR_DBP PWR_CR_DBP_Msk
1065/******************* Bit definition for PWR_CSR register ********************/
1066#define PWR_CSR_WUF_Pos (0U)
1067#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
1068#define PWR_CSR_WUF PWR_CSR_WUF_Msk
1069#define PWR_CSR_SBF_Pos (1U)
1070#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
1071#define PWR_CSR_SBF PWR_CSR_SBF_Msk
1072#define PWR_CSR_PVDO_Pos (2U)
1073#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
1074#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
1075#define PWR_CSR_EWUP_Pos (8U)
1076#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
1077#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
1079/******************************************************************************/
1080/* */
1081/* Backup registers */
1082/* */
1083/******************************************************************************/
1084
1085/******************* Bit definition for BKP_DR1 register ********************/
1086#define BKP_DR1_D_Pos (0U)
1087#define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos)
1088#define BKP_DR1_D BKP_DR1_D_Msk
1090/******************* Bit definition for BKP_DR2 register ********************/
1091#define BKP_DR2_D_Pos (0U)
1092#define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos)
1093#define BKP_DR2_D BKP_DR2_D_Msk
1095/******************* Bit definition for BKP_DR3 register ********************/
1096#define BKP_DR3_D_Pos (0U)
1097#define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos)
1098#define BKP_DR3_D BKP_DR3_D_Msk
1100/******************* Bit definition for BKP_DR4 register ********************/
1101#define BKP_DR4_D_Pos (0U)
1102#define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos)
1103#define BKP_DR4_D BKP_DR4_D_Msk
1105/******************* Bit definition for BKP_DR5 register ********************/
1106#define BKP_DR5_D_Pos (0U)
1107#define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos)
1108#define BKP_DR5_D BKP_DR5_D_Msk
1110/******************* Bit definition for BKP_DR6 register ********************/
1111#define BKP_DR6_D_Pos (0U)
1112#define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos)
1113#define BKP_DR6_D BKP_DR6_D_Msk
1115/******************* Bit definition for BKP_DR7 register ********************/
1116#define BKP_DR7_D_Pos (0U)
1117#define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos)
1118#define BKP_DR7_D BKP_DR7_D_Msk
1120/******************* Bit definition for BKP_DR8 register ********************/
1121#define BKP_DR8_D_Pos (0U)
1122#define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos)
1123#define BKP_DR8_D BKP_DR8_D_Msk
1125/******************* Bit definition for BKP_DR9 register ********************/
1126#define BKP_DR9_D_Pos (0U)
1127#define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos)
1128#define BKP_DR9_D BKP_DR9_D_Msk
1130/******************* Bit definition for BKP_DR10 register *******************/
1131#define BKP_DR10_D_Pos (0U)
1132#define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos)
1133#define BKP_DR10_D BKP_DR10_D_Msk
1135/******************* Bit definition for BKP_DR11 register *******************/
1136#define BKP_DR11_D_Pos (0U)
1137#define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos)
1138#define BKP_DR11_D BKP_DR11_D_Msk
1140/******************* Bit definition for BKP_DR12 register *******************/
1141#define BKP_DR12_D_Pos (0U)
1142#define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos)
1143#define BKP_DR12_D BKP_DR12_D_Msk
1145/******************* Bit definition for BKP_DR13 register *******************/
1146#define BKP_DR13_D_Pos (0U)
1147#define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos)
1148#define BKP_DR13_D BKP_DR13_D_Msk
1150/******************* Bit definition for BKP_DR14 register *******************/
1151#define BKP_DR14_D_Pos (0U)
1152#define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos)
1153#define BKP_DR14_D BKP_DR14_D_Msk
1155/******************* Bit definition for BKP_DR15 register *******************/
1156#define BKP_DR15_D_Pos (0U)
1157#define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos)
1158#define BKP_DR15_D BKP_DR15_D_Msk
1160/******************* Bit definition for BKP_DR16 register *******************/
1161#define BKP_DR16_D_Pos (0U)
1162#define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos)
1163#define BKP_DR16_D BKP_DR16_D_Msk
1165/******************* Bit definition for BKP_DR17 register *******************/
1166#define BKP_DR17_D_Pos (0U)
1167#define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos)
1168#define BKP_DR17_D BKP_DR17_D_Msk
1170/****************** Bit definition for BKP_DR18 register ********************/
1171#define BKP_DR18_D_Pos (0U)
1172#define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos)
1173#define BKP_DR18_D BKP_DR18_D_Msk
1175/******************* Bit definition for BKP_DR19 register *******************/
1176#define BKP_DR19_D_Pos (0U)
1177#define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos)
1178#define BKP_DR19_D BKP_DR19_D_Msk
1180/******************* Bit definition for BKP_DR20 register *******************/
1181#define BKP_DR20_D_Pos (0U)
1182#define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos)
1183#define BKP_DR20_D BKP_DR20_D_Msk
1185/******************* Bit definition for BKP_DR21 register *******************/
1186#define BKP_DR21_D_Pos (0U)
1187#define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos)
1188#define BKP_DR21_D BKP_DR21_D_Msk
1190/******************* Bit definition for BKP_DR22 register *******************/
1191#define BKP_DR22_D_Pos (0U)
1192#define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos)
1193#define BKP_DR22_D BKP_DR22_D_Msk
1195/******************* Bit definition for BKP_DR23 register *******************/
1196#define BKP_DR23_D_Pos (0U)
1197#define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos)
1198#define BKP_DR23_D BKP_DR23_D_Msk
1200/******************* Bit definition for BKP_DR24 register *******************/
1201#define BKP_DR24_D_Pos (0U)
1202#define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos)
1203#define BKP_DR24_D BKP_DR24_D_Msk
1205/******************* Bit definition for BKP_DR25 register *******************/
1206#define BKP_DR25_D_Pos (0U)
1207#define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos)
1208#define BKP_DR25_D BKP_DR25_D_Msk
1210/******************* Bit definition for BKP_DR26 register *******************/
1211#define BKP_DR26_D_Pos (0U)
1212#define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos)
1213#define BKP_DR26_D BKP_DR26_D_Msk
1215/******************* Bit definition for BKP_DR27 register *******************/
1216#define BKP_DR27_D_Pos (0U)
1217#define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos)
1218#define BKP_DR27_D BKP_DR27_D_Msk
1220/******************* Bit definition for BKP_DR28 register *******************/
1221#define BKP_DR28_D_Pos (0U)
1222#define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos)
1223#define BKP_DR28_D BKP_DR28_D_Msk
1225/******************* Bit definition for BKP_DR29 register *******************/
1226#define BKP_DR29_D_Pos (0U)
1227#define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos)
1228#define BKP_DR29_D BKP_DR29_D_Msk
1230/******************* Bit definition for BKP_DR30 register *******************/
1231#define BKP_DR30_D_Pos (0U)
1232#define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos)
1233#define BKP_DR30_D BKP_DR30_D_Msk
1235/******************* Bit definition for BKP_DR31 register *******************/
1236#define BKP_DR31_D_Pos (0U)
1237#define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos)
1238#define BKP_DR31_D BKP_DR31_D_Msk
1240/******************* Bit definition for BKP_DR32 register *******************/
1241#define BKP_DR32_D_Pos (0U)
1242#define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos)
1243#define BKP_DR32_D BKP_DR32_D_Msk
1245/******************* Bit definition for BKP_DR33 register *******************/
1246#define BKP_DR33_D_Pos (0U)
1247#define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos)
1248#define BKP_DR33_D BKP_DR33_D_Msk
1250/******************* Bit definition for BKP_DR34 register *******************/
1251#define BKP_DR34_D_Pos (0U)
1252#define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos)
1253#define BKP_DR34_D BKP_DR34_D_Msk
1255/******************* Bit definition for BKP_DR35 register *******************/
1256#define BKP_DR35_D_Pos (0U)
1257#define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos)
1258#define BKP_DR35_D BKP_DR35_D_Msk
1260/******************* Bit definition for BKP_DR36 register *******************/
1261#define BKP_DR36_D_Pos (0U)
1262#define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos)
1263#define BKP_DR36_D BKP_DR36_D_Msk
1265/******************* Bit definition for BKP_DR37 register *******************/
1266#define BKP_DR37_D_Pos (0U)
1267#define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos)
1268#define BKP_DR37_D BKP_DR37_D_Msk
1270/******************* Bit definition for BKP_DR38 register *******************/
1271#define BKP_DR38_D_Pos (0U)
1272#define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos)
1273#define BKP_DR38_D BKP_DR38_D_Msk
1275/******************* Bit definition for BKP_DR39 register *******************/
1276#define BKP_DR39_D_Pos (0U)
1277#define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos)
1278#define BKP_DR39_D BKP_DR39_D_Msk
1280/******************* Bit definition for BKP_DR40 register *******************/
1281#define BKP_DR40_D_Pos (0U)
1282#define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos)
1283#define BKP_DR40_D BKP_DR40_D_Msk
1285/******************* Bit definition for BKP_DR41 register *******************/
1286#define BKP_DR41_D_Pos (0U)
1287#define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos)
1288#define BKP_DR41_D BKP_DR41_D_Msk
1290/******************* Bit definition for BKP_DR42 register *******************/
1291#define BKP_DR42_D_Pos (0U)
1292#define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos)
1293#define BKP_DR42_D BKP_DR42_D_Msk
1295#define RTC_BKP_NUMBER 42
1296
1297/****************** Bit definition for BKP_RTCCR register *******************/
1298#define BKP_RTCCR_CAL_Pos (0U)
1299#define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos)
1300#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk
1301#define BKP_RTCCR_CCO_Pos (7U)
1302#define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos)
1303#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk
1304#define BKP_RTCCR_ASOE_Pos (8U)
1305#define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos)
1306#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk
1307#define BKP_RTCCR_ASOS_Pos (9U)
1308#define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos)
1309#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk
1311/******************** Bit definition for BKP_CR register ********************/
1312#define BKP_CR_TPE_Pos (0U)
1313#define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos)
1314#define BKP_CR_TPE BKP_CR_TPE_Msk
1315#define BKP_CR_TPAL_Pos (1U)
1316#define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos)
1317#define BKP_CR_TPAL BKP_CR_TPAL_Msk
1319/******************* Bit definition for BKP_CSR register ********************/
1320#define BKP_CSR_CTE_Pos (0U)
1321#define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos)
1322#define BKP_CSR_CTE BKP_CSR_CTE_Msk
1323#define BKP_CSR_CTI_Pos (1U)
1324#define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos)
1325#define BKP_CSR_CTI BKP_CSR_CTI_Msk
1326#define BKP_CSR_TPIE_Pos (2U)
1327#define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos)
1328#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk
1329#define BKP_CSR_TEF_Pos (8U)
1330#define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos)
1331#define BKP_CSR_TEF BKP_CSR_TEF_Msk
1332#define BKP_CSR_TIF_Pos (9U)
1333#define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos)
1334#define BKP_CSR_TIF BKP_CSR_TIF_Msk
1336/******************************************************************************/
1337/* */
1338/* Reset and Clock Control */
1339/* */
1340/******************************************************************************/
1341/*
1342 * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
1343 */
1344#define RCC_PLL2_SUPPORT
1345#define RCC_PLLI2S_SUPPORT
1346
1347/******************** Bit definition for RCC_CR register ********************/
1348#define RCC_CR_HSION_Pos (0U)
1349#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
1350#define RCC_CR_HSION RCC_CR_HSION_Msk
1351#define RCC_CR_HSIRDY_Pos (1U)
1352#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
1353#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
1354#define RCC_CR_HSITRIM_Pos (3U)
1355#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
1356#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
1357#define RCC_CR_HSICAL_Pos (8U)
1358#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
1359#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
1360#define RCC_CR_HSEON_Pos (16U)
1361#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
1362#define RCC_CR_HSEON RCC_CR_HSEON_Msk
1363#define RCC_CR_HSERDY_Pos (17U)
1364#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
1365#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
1366#define RCC_CR_HSEBYP_Pos (18U)
1367#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
1368#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
1369#define RCC_CR_CSSON_Pos (19U)
1370#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
1371#define RCC_CR_CSSON RCC_CR_CSSON_Msk
1372#define RCC_CR_PLLON_Pos (24U)
1373#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
1374#define RCC_CR_PLLON RCC_CR_PLLON_Msk
1375#define RCC_CR_PLLRDY_Pos (25U)
1376#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
1377#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
1379#define RCC_CR_PLL2ON_Pos (26U)
1380#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos)
1381#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk
1382#define RCC_CR_PLL2RDY_Pos (27U)
1383#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos)
1384#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk
1386#define RCC_CR_PLL3ON_Pos (28U)
1387#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos)
1388#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk
1389#define RCC_CR_PLL3RDY_Pos (29U)
1390#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos)
1391#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk
1393/******************* Bit definition for RCC_CFGR register *******************/
1395#define RCC_CFGR_SW_Pos (0U)
1396#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
1397#define RCC_CFGR_SW RCC_CFGR_SW_Msk
1398#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
1399#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
1401#define RCC_CFGR_SW_HSI 0x00000000U
1402#define RCC_CFGR_SW_HSE 0x00000001U
1403#define RCC_CFGR_SW_PLL 0x00000002U
1406#define RCC_CFGR_SWS_Pos (2U)
1407#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
1408#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
1409#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
1410#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
1412#define RCC_CFGR_SWS_HSI 0x00000000U
1413#define RCC_CFGR_SWS_HSE 0x00000004U
1414#define RCC_CFGR_SWS_PLL 0x00000008U
1417#define RCC_CFGR_HPRE_Pos (4U)
1418#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
1419#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
1420#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
1421#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
1422#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
1423#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
1425#define RCC_CFGR_HPRE_DIV1 0x00000000U
1426#define RCC_CFGR_HPRE_DIV2 0x00000080U
1427#define RCC_CFGR_HPRE_DIV4 0x00000090U
1428#define RCC_CFGR_HPRE_DIV8 0x000000A0U
1429#define RCC_CFGR_HPRE_DIV16 0x000000B0U
1430#define RCC_CFGR_HPRE_DIV64 0x000000C0U
1431#define RCC_CFGR_HPRE_DIV128 0x000000D0U
1432#define RCC_CFGR_HPRE_DIV256 0x000000E0U
1433#define RCC_CFGR_HPRE_DIV512 0x000000F0U
1436#define RCC_CFGR_PPRE1_Pos (8U)
1437#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
1438#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
1439#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
1440#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
1441#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
1443#define RCC_CFGR_PPRE1_DIV1 0x00000000U
1444#define RCC_CFGR_PPRE1_DIV2 0x00000400U
1445#define RCC_CFGR_PPRE1_DIV4 0x00000500U
1446#define RCC_CFGR_PPRE1_DIV8 0x00000600U
1447#define RCC_CFGR_PPRE1_DIV16 0x00000700U
1450#define RCC_CFGR_PPRE2_Pos (11U)
1451#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
1452#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
1453#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
1454#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
1455#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
1457#define RCC_CFGR_PPRE2_DIV1 0x00000000U
1458#define RCC_CFGR_PPRE2_DIV2 0x00002000U
1459#define RCC_CFGR_PPRE2_DIV4 0x00002800U
1460#define RCC_CFGR_PPRE2_DIV8 0x00003000U
1461#define RCC_CFGR_PPRE2_DIV16 0x00003800U
1464#define RCC_CFGR_ADCPRE_Pos (14U)
1465#define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos)
1466#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk
1467#define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos)
1468#define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos)
1470#define RCC_CFGR_ADCPRE_DIV2 0x00000000U
1471#define RCC_CFGR_ADCPRE_DIV4 0x00004000U
1472#define RCC_CFGR_ADCPRE_DIV6 0x00008000U
1473#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U
1475#define RCC_CFGR_PLLSRC_Pos (16U)
1476#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)
1477#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk
1479#define RCC_CFGR_PLLXTPRE_Pos (17U)
1480#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)
1481#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk
1484#define RCC_CFGR_PLLMULL_Pos (18U)
1485#define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos)
1486#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk
1487#define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos)
1488#define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos)
1489#define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos)
1490#define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos)
1492#define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U
1493#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U
1495#define RCC_CFGR_PLLMULL4_Pos (19U)
1496#define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos)
1497#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk
1498#define RCC_CFGR_PLLMULL5_Pos (18U)
1499#define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos)
1500#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk
1501#define RCC_CFGR_PLLMULL6_Pos (20U)
1502#define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos)
1503#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk
1504#define RCC_CFGR_PLLMULL7_Pos (18U)
1505#define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos)
1506#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk
1507#define RCC_CFGR_PLLMULL8_Pos (19U)
1508#define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos)
1509#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk
1510#define RCC_CFGR_PLLMULL9_Pos (18U)
1511#define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos)
1512#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk
1513#define RCC_CFGR_PLLMULL6_5 0x00340000U
1515#define RCC_CFGR_OTGFSPRE_Pos (22U)
1516#define RCC_CFGR_OTGFSPRE_Msk (0x1UL << RCC_CFGR_OTGFSPRE_Pos)
1517#define RCC_CFGR_OTGFSPRE RCC_CFGR_OTGFSPRE_Msk
1520#define RCC_CFGR_MCO_Pos (24U)
1521#define RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos)
1522#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk
1523#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)
1524#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)
1525#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)
1526#define RCC_CFGR_MCO_3 (0x8UL << RCC_CFGR_MCO_Pos)
1528#define RCC_CFGR_MCO_NOCLOCK 0x00000000U
1529#define RCC_CFGR_MCO_SYSCLK 0x04000000U
1530#define RCC_CFGR_MCO_HSI 0x05000000U
1531#define RCC_CFGR_MCO_HSE 0x06000000U
1532#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U
1533#define RCC_CFGR_MCO_PLL2CLK 0x08000000U
1534#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U
1535#define RCC_CFGR_MCO_EXT_HSE 0x0A000000U
1536#define RCC_CFGR_MCO_PLL3CLK 0x0B000000U
1538 /* Reference defines */
1539 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
1540 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
1541 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
1542 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
1543 #define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3
1544 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
1545 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
1546 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
1547 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
1548 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
1549 #define RCC_CFGR_MCOSEL_PLL2 RCC_CFGR_MCO_PLL2CLK
1550 #define RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2
1551 #define RCC_CFGR_MCOSEL_EXT_HSE RCC_CFGR_MCO_EXT_HSE
1552 #define RCC_CFGR_MCOSEL_PLL3CLK RCC_CFGR_MCO_PLL3CLK
1553
1555#define RCC_CIR_LSIRDYF_Pos (0U)
1556#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
1557#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
1558#define RCC_CIR_LSERDYF_Pos (1U)
1559#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
1560#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
1561#define RCC_CIR_HSIRDYF_Pos (2U)
1562#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
1563#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
1564#define RCC_CIR_HSERDYF_Pos (3U)
1565#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
1566#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
1567#define RCC_CIR_PLLRDYF_Pos (4U)
1568#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
1569#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
1570#define RCC_CIR_CSSF_Pos (7U)
1571#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
1572#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
1573#define RCC_CIR_LSIRDYIE_Pos (8U)
1574#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
1575#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
1576#define RCC_CIR_LSERDYIE_Pos (9U)
1577#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
1578#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
1579#define RCC_CIR_HSIRDYIE_Pos (10U)
1580#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
1581#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
1582#define RCC_CIR_HSERDYIE_Pos (11U)
1583#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
1584#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
1585#define RCC_CIR_PLLRDYIE_Pos (12U)
1586#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
1587#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
1588#define RCC_CIR_LSIRDYC_Pos (16U)
1589#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
1590#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
1591#define RCC_CIR_LSERDYC_Pos (17U)
1592#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
1593#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
1594#define RCC_CIR_HSIRDYC_Pos (18U)
1595#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
1596#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
1597#define RCC_CIR_HSERDYC_Pos (19U)
1598#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
1599#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
1600#define RCC_CIR_PLLRDYC_Pos (20U)
1601#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
1602#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
1603#define RCC_CIR_CSSC_Pos (23U)
1604#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
1605#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
1607#define RCC_CIR_PLL2RDYF_Pos (5U)
1608#define RCC_CIR_PLL2RDYF_Msk (0x1UL << RCC_CIR_PLL2RDYF_Pos)
1609#define RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF_Msk
1610#define RCC_CIR_PLL3RDYF_Pos (6U)
1611#define RCC_CIR_PLL3RDYF_Msk (0x1UL << RCC_CIR_PLL3RDYF_Pos)
1612#define RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF_Msk
1613#define RCC_CIR_PLL2RDYIE_Pos (13U)
1614#define RCC_CIR_PLL2RDYIE_Msk (0x1UL << RCC_CIR_PLL2RDYIE_Pos)
1615#define RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE_Msk
1616#define RCC_CIR_PLL3RDYIE_Pos (14U)
1617#define RCC_CIR_PLL3RDYIE_Msk (0x1UL << RCC_CIR_PLL3RDYIE_Pos)
1618#define RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE_Msk
1619#define RCC_CIR_PLL2RDYC_Pos (21U)
1620#define RCC_CIR_PLL2RDYC_Msk (0x1UL << RCC_CIR_PLL2RDYC_Pos)
1621#define RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC_Msk
1622#define RCC_CIR_PLL3RDYC_Pos (22U)
1623#define RCC_CIR_PLL3RDYC_Msk (0x1UL << RCC_CIR_PLL3RDYC_Pos)
1624#define RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC_Msk
1626/***************** Bit definition for RCC_APB2RSTR register *****************/
1627#define RCC_APB2RSTR_AFIORST_Pos (0U)
1628#define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos)
1629#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk
1630#define RCC_APB2RSTR_IOPARST_Pos (2U)
1631#define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos)
1632#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk
1633#define RCC_APB2RSTR_IOPBRST_Pos (3U)
1634#define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos)
1635#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk
1636#define RCC_APB2RSTR_IOPCRST_Pos (4U)
1637#define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos)
1638#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk
1639#define RCC_APB2RSTR_IOPDRST_Pos (5U)
1640#define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos)
1641#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk
1642#define RCC_APB2RSTR_ADC1RST_Pos (9U)
1643#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos)
1644#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk
1646#define RCC_APB2RSTR_ADC2RST_Pos (10U)
1647#define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos)
1648#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk
1650#define RCC_APB2RSTR_TIM1RST_Pos (11U)
1651#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
1652#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
1653#define RCC_APB2RSTR_SPI1RST_Pos (12U)
1654#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
1655#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
1656#define RCC_APB2RSTR_USART1RST_Pos (14U)
1657#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
1658#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
1661#define RCC_APB2RSTR_IOPERST_Pos (6U)
1662#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos)
1663#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk
1668/***************** Bit definition for RCC_APB1RSTR register *****************/
1669#define RCC_APB1RSTR_TIM2RST_Pos (0U)
1670#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
1671#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
1672#define RCC_APB1RSTR_TIM3RST_Pos (1U)
1673#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
1674#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
1675#define RCC_APB1RSTR_WWDGRST_Pos (11U)
1676#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
1677#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
1678#define RCC_APB1RSTR_USART2RST_Pos (17U)
1679#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
1680#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
1681#define RCC_APB1RSTR_I2C1RST_Pos (21U)
1682#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
1683#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
1685#define RCC_APB1RSTR_CAN1RST_Pos (25U)
1686#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
1687#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
1689#define RCC_APB1RSTR_BKPRST_Pos (27U)
1690#define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos)
1691#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk
1692#define RCC_APB1RSTR_PWRRST_Pos (28U)
1693#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
1694#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
1696#define RCC_APB1RSTR_TIM4RST_Pos (2U)
1697#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
1698#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
1699#define RCC_APB1RSTR_SPI2RST_Pos (14U)
1700#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
1701#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
1702#define RCC_APB1RSTR_USART3RST_Pos (18U)
1703#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
1704#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
1705#define RCC_APB1RSTR_I2C2RST_Pos (22U)
1706#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
1707#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
1710#define RCC_APB1RSTR_TIM5RST_Pos (3U)
1711#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
1712#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
1713#define RCC_APB1RSTR_TIM6RST_Pos (4U)
1714#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
1715#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
1716#define RCC_APB1RSTR_TIM7RST_Pos (5U)
1717#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
1718#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
1719#define RCC_APB1RSTR_SPI3RST_Pos (15U)
1720#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
1721#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
1722#define RCC_APB1RSTR_UART4RST_Pos (19U)
1723#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
1724#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
1725#define RCC_APB1RSTR_UART5RST_Pos (20U)
1726#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
1727#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
1731#define RCC_APB1RSTR_CAN2RST_Pos (26U)
1732#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
1733#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
1735#define RCC_APB1RSTR_DACRST_Pos (29U)
1736#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
1737#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
1739/****************** Bit definition for RCC_AHBENR register ******************/
1740#define RCC_AHBENR_DMA1EN_Pos (0U)
1741#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos)
1742#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk
1743#define RCC_AHBENR_SRAMEN_Pos (2U)
1744#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos)
1745#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk
1746#define RCC_AHBENR_FLITFEN_Pos (4U)
1747#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos)
1748#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk
1749#define RCC_AHBENR_CRCEN_Pos (6U)
1750#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)
1751#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk
1753#define RCC_AHBENR_DMA2EN_Pos (1U)
1754#define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos)
1755#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk
1758#define RCC_AHBENR_OTGFSEN_Pos (12U)
1759#define RCC_AHBENR_OTGFSEN_Msk (0x1UL << RCC_AHBENR_OTGFSEN_Pos)
1760#define RCC_AHBENR_OTGFSEN RCC_AHBENR_OTGFSEN_Msk
1761#define RCC_AHBENR_ETHMACEN_Pos (14U)
1762#define RCC_AHBENR_ETHMACEN_Msk (0x1UL << RCC_AHBENR_ETHMACEN_Pos)
1763#define RCC_AHBENR_ETHMACEN RCC_AHBENR_ETHMACEN_Msk
1764#define RCC_AHBENR_ETHMACTXEN_Pos (15U)
1765#define RCC_AHBENR_ETHMACTXEN_Msk (0x1UL << RCC_AHBENR_ETHMACTXEN_Pos)
1766#define RCC_AHBENR_ETHMACTXEN RCC_AHBENR_ETHMACTXEN_Msk
1767#define RCC_AHBENR_ETHMACRXEN_Pos (16U)
1768#define RCC_AHBENR_ETHMACRXEN_Msk (0x1UL << RCC_AHBENR_ETHMACRXEN_Pos)
1769#define RCC_AHBENR_ETHMACRXEN RCC_AHBENR_ETHMACRXEN_Msk
1771/****************** Bit definition for RCC_APB2ENR register *****************/
1772#define RCC_APB2ENR_AFIOEN_Pos (0U)
1773#define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos)
1774#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk
1775#define RCC_APB2ENR_IOPAEN_Pos (2U)
1776#define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos)
1777#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk
1778#define RCC_APB2ENR_IOPBEN_Pos (3U)
1779#define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos)
1780#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk
1781#define RCC_APB2ENR_IOPCEN_Pos (4U)
1782#define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos)
1783#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk
1784#define RCC_APB2ENR_IOPDEN_Pos (5U)
1785#define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos)
1786#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk
1787#define RCC_APB2ENR_ADC1EN_Pos (9U)
1788#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
1789#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
1791#define RCC_APB2ENR_ADC2EN_Pos (10U)
1792#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
1793#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
1795#define RCC_APB2ENR_TIM1EN_Pos (11U)
1796#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
1797#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
1798#define RCC_APB2ENR_SPI1EN_Pos (12U)
1799#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
1800#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
1801#define RCC_APB2ENR_USART1EN_Pos (14U)
1802#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
1803#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
1806#define RCC_APB2ENR_IOPEEN_Pos (6U)
1807#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos)
1808#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk
1813/***************** Bit definition for RCC_APB1ENR register ******************/
1814#define RCC_APB1ENR_TIM2EN_Pos (0U)
1815#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
1816#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
1817#define RCC_APB1ENR_TIM3EN_Pos (1U)
1818#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
1819#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
1820#define RCC_APB1ENR_WWDGEN_Pos (11U)
1821#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
1822#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
1823#define RCC_APB1ENR_USART2EN_Pos (17U)
1824#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
1825#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
1826#define RCC_APB1ENR_I2C1EN_Pos (21U)
1827#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
1828#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
1830#define RCC_APB1ENR_CAN1EN_Pos (25U)
1831#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
1832#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
1834#define RCC_APB1ENR_BKPEN_Pos (27U)
1835#define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos)
1836#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk
1837#define RCC_APB1ENR_PWREN_Pos (28U)
1838#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
1839#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
1841#define RCC_APB1ENR_TIM4EN_Pos (2U)
1842#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
1843#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
1844#define RCC_APB1ENR_SPI2EN_Pos (14U)
1845#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
1846#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
1847#define RCC_APB1ENR_USART3EN_Pos (18U)
1848#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
1849#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
1850#define RCC_APB1ENR_I2C2EN_Pos (22U)
1851#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
1852#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
1855#define RCC_APB1ENR_TIM5EN_Pos (3U)
1856#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
1857#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
1858#define RCC_APB1ENR_TIM6EN_Pos (4U)
1859#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
1860#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
1861#define RCC_APB1ENR_TIM7EN_Pos (5U)
1862#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
1863#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
1864#define RCC_APB1ENR_SPI3EN_Pos (15U)
1865#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
1866#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
1867#define RCC_APB1ENR_UART4EN_Pos (19U)
1868#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
1869#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
1870#define RCC_APB1ENR_UART5EN_Pos (20U)
1871#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
1872#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
1876#define RCC_APB1ENR_CAN2EN_Pos (26U)
1877#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
1878#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
1880#define RCC_APB1ENR_DACEN_Pos (29U)
1881#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
1882#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
1884/******************* Bit definition for RCC_BDCR register *******************/
1885#define RCC_BDCR_LSEON_Pos (0U)
1886#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
1887#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
1888#define RCC_BDCR_LSERDY_Pos (1U)
1889#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
1890#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
1891#define RCC_BDCR_LSEBYP_Pos (2U)
1892#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
1893#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
1895#define RCC_BDCR_RTCSEL_Pos (8U)
1896#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
1897#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
1898#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
1899#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
1902#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U
1903#define RCC_BDCR_RTCSEL_LSE 0x00000100U
1904#define RCC_BDCR_RTCSEL_LSI 0x00000200U
1905#define RCC_BDCR_RTCSEL_HSE 0x00000300U
1907#define RCC_BDCR_RTCEN_Pos (15U)
1908#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
1909#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
1910#define RCC_BDCR_BDRST_Pos (16U)
1911#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
1912#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
1914/******************* Bit definition for RCC_CSR register ********************/
1915#define RCC_CSR_LSION_Pos (0U)
1916#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
1917#define RCC_CSR_LSION RCC_CSR_LSION_Msk
1918#define RCC_CSR_LSIRDY_Pos (1U)
1919#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
1920#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
1921#define RCC_CSR_RMVF_Pos (24U)
1922#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
1923#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
1924#define RCC_CSR_PINRSTF_Pos (26U)
1925#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
1926#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
1927#define RCC_CSR_PORRSTF_Pos (27U)
1928#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
1929#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
1930#define RCC_CSR_SFTRSTF_Pos (28U)
1931#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
1932#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
1933#define RCC_CSR_IWDGRSTF_Pos (29U)
1934#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
1935#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
1936#define RCC_CSR_WWDGRSTF_Pos (30U)
1937#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
1938#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
1939#define RCC_CSR_LPWRRSTF_Pos (31U)
1940#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
1941#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
1943/******************* Bit definition for RCC_AHBRSTR register ****************/
1944#define RCC_AHBRSTR_OTGFSRST_Pos (12U)
1945#define RCC_AHBRSTR_OTGFSRST_Msk (0x1UL << RCC_AHBRSTR_OTGFSRST_Pos)
1946#define RCC_AHBRSTR_OTGFSRST RCC_AHBRSTR_OTGFSRST_Msk
1947#define RCC_AHBRSTR_ETHMACRST_Pos (14U)
1948#define RCC_AHBRSTR_ETHMACRST_Msk (0x1UL << RCC_AHBRSTR_ETHMACRST_Pos)
1949#define RCC_AHBRSTR_ETHMACRST RCC_AHBRSTR_ETHMACRST_Msk
1951/******************* Bit definition for RCC_CFGR2 register ******************/
1953#define RCC_CFGR2_PREDIV1_Pos (0U)
1954#define RCC_CFGR2_PREDIV1_Msk (0xFUL << RCC_CFGR2_PREDIV1_Pos)
1955#define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk
1956#define RCC_CFGR2_PREDIV1_0 (0x1UL << RCC_CFGR2_PREDIV1_Pos)
1957#define RCC_CFGR2_PREDIV1_1 (0x2UL << RCC_CFGR2_PREDIV1_Pos)
1958#define RCC_CFGR2_PREDIV1_2 (0x4UL << RCC_CFGR2_PREDIV1_Pos)
1959#define RCC_CFGR2_PREDIV1_3 (0x8UL << RCC_CFGR2_PREDIV1_Pos)
1961#define RCC_CFGR2_PREDIV1_DIV1 0x00000000U
1962#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
1963#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV2_Pos)
1964#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk
1965#define RCC_CFGR2_PREDIV1_DIV3_Pos (1U)
1966#define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV3_Pos)
1967#define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk
1968#define RCC_CFGR2_PREDIV1_DIV4_Pos (0U)
1969#define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV4_Pos)
1970#define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk
1971#define RCC_CFGR2_PREDIV1_DIV5_Pos (2U)
1972#define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV5_Pos)
1973#define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk
1974#define RCC_CFGR2_PREDIV1_DIV6_Pos (0U)
1975#define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV6_Pos)
1976#define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk
1977#define RCC_CFGR2_PREDIV1_DIV7_Pos (1U)
1978#define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV7_Pos)
1979#define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk
1980#define RCC_CFGR2_PREDIV1_DIV8_Pos (0U)
1981#define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV8_Pos)
1982#define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk
1983#define RCC_CFGR2_PREDIV1_DIV9_Pos (3U)
1984#define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV9_Pos)
1985#define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk
1986#define RCC_CFGR2_PREDIV1_DIV10_Pos (0U)
1987#define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV1_DIV10_Pos)
1988#define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk
1989#define RCC_CFGR2_PREDIV1_DIV11_Pos (1U)
1990#define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV11_Pos)
1991#define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk
1992#define RCC_CFGR2_PREDIV1_DIV12_Pos (0U)
1993#define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV1_DIV12_Pos)
1994#define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk
1995#define RCC_CFGR2_PREDIV1_DIV13_Pos (2U)
1996#define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV13_Pos)
1997#define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk
1998#define RCC_CFGR2_PREDIV1_DIV14_Pos (0U)
1999#define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV1_DIV14_Pos)
2000#define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk
2001#define RCC_CFGR2_PREDIV1_DIV15_Pos (1U)
2002#define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV15_Pos)
2003#define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk
2004#define RCC_CFGR2_PREDIV1_DIV16_Pos (0U)
2005#define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV1_DIV16_Pos)
2006#define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk
2009#define RCC_CFGR2_PREDIV2_Pos (4U)
2010#define RCC_CFGR2_PREDIV2_Msk (0xFUL << RCC_CFGR2_PREDIV2_Pos)
2011#define RCC_CFGR2_PREDIV2 RCC_CFGR2_PREDIV2_Msk
2012#define RCC_CFGR2_PREDIV2_0 (0x1UL << RCC_CFGR2_PREDIV2_Pos)
2013#define RCC_CFGR2_PREDIV2_1 (0x2UL << RCC_CFGR2_PREDIV2_Pos)
2014#define RCC_CFGR2_PREDIV2_2 (0x4UL << RCC_CFGR2_PREDIV2_Pos)
2015#define RCC_CFGR2_PREDIV2_3 (0x8UL << RCC_CFGR2_PREDIV2_Pos)
2017#define RCC_CFGR2_PREDIV2_DIV1 0x00000000U
2018#define RCC_CFGR2_PREDIV2_DIV2_Pos (4U)
2019#define RCC_CFGR2_PREDIV2_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV2_Pos)
2020#define RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk
2021#define RCC_CFGR2_PREDIV2_DIV3_Pos (5U)
2022#define RCC_CFGR2_PREDIV2_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV3_Pos)
2023#define RCC_CFGR2_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3_Msk
2024#define RCC_CFGR2_PREDIV2_DIV4_Pos (4U)
2025#define RCC_CFGR2_PREDIV2_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV4_Pos)
2026#define RCC_CFGR2_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4_Msk
2027#define RCC_CFGR2_PREDIV2_DIV5_Pos (6U)
2028#define RCC_CFGR2_PREDIV2_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV5_Pos)
2029#define RCC_CFGR2_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5_Msk
2030#define RCC_CFGR2_PREDIV2_DIV6_Pos (4U)
2031#define RCC_CFGR2_PREDIV2_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV6_Pos)
2032#define RCC_CFGR2_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6_Msk
2033#define RCC_CFGR2_PREDIV2_DIV7_Pos (5U)
2034#define RCC_CFGR2_PREDIV2_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV7_Pos)
2035#define RCC_CFGR2_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7_Msk
2036#define RCC_CFGR2_PREDIV2_DIV8_Pos (4U)
2037#define RCC_CFGR2_PREDIV2_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV8_Pos)
2038#define RCC_CFGR2_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8_Msk
2039#define RCC_CFGR2_PREDIV2_DIV9_Pos (7U)
2040#define RCC_CFGR2_PREDIV2_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV9_Pos)
2041#define RCC_CFGR2_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9_Msk
2042#define RCC_CFGR2_PREDIV2_DIV10_Pos (4U)
2043#define RCC_CFGR2_PREDIV2_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV2_DIV10_Pos)
2044#define RCC_CFGR2_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10_Msk
2045#define RCC_CFGR2_PREDIV2_DIV11_Pos (5U)
2046#define RCC_CFGR2_PREDIV2_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV11_Pos)
2047#define RCC_CFGR2_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11_Msk
2048#define RCC_CFGR2_PREDIV2_DIV12_Pos (4U)
2049#define RCC_CFGR2_PREDIV2_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV2_DIV12_Pos)
2050#define RCC_CFGR2_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12_Msk
2051#define RCC_CFGR2_PREDIV2_DIV13_Pos (6U)
2052#define RCC_CFGR2_PREDIV2_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV13_Pos)
2053#define RCC_CFGR2_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13_Msk
2054#define RCC_CFGR2_PREDIV2_DIV14_Pos (4U)
2055#define RCC_CFGR2_PREDIV2_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV2_DIV14_Pos)
2056#define RCC_CFGR2_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14_Msk
2057#define RCC_CFGR2_PREDIV2_DIV15_Pos (5U)
2058#define RCC_CFGR2_PREDIV2_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV15_Pos)
2059#define RCC_CFGR2_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15_Msk
2060#define RCC_CFGR2_PREDIV2_DIV16_Pos (4U)
2061#define RCC_CFGR2_PREDIV2_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV2_DIV16_Pos)
2062#define RCC_CFGR2_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16_Msk
2065#define RCC_CFGR2_PLL2MUL_Pos (8U)
2066#define RCC_CFGR2_PLL2MUL_Msk (0xFUL << RCC_CFGR2_PLL2MUL_Pos)
2067#define RCC_CFGR2_PLL2MUL RCC_CFGR2_PLL2MUL_Msk
2068#define RCC_CFGR2_PLL2MUL_0 (0x1UL << RCC_CFGR2_PLL2MUL_Pos)
2069#define RCC_CFGR2_PLL2MUL_1 (0x2UL << RCC_CFGR2_PLL2MUL_Pos)
2070#define RCC_CFGR2_PLL2MUL_2 (0x4UL << RCC_CFGR2_PLL2MUL_Pos)
2071#define RCC_CFGR2_PLL2MUL_3 (0x8UL << RCC_CFGR2_PLL2MUL_Pos)
2073#define RCC_CFGR2_PLL2MUL8_Pos (9U)
2074#define RCC_CFGR2_PLL2MUL8_Msk (0x3UL << RCC_CFGR2_PLL2MUL8_Pos)
2075#define RCC_CFGR2_PLL2MUL8 RCC_CFGR2_PLL2MUL8_Msk
2076#define RCC_CFGR2_PLL2MUL9_Pos (8U)
2077#define RCC_CFGR2_PLL2MUL9_Msk (0x7UL << RCC_CFGR2_PLL2MUL9_Pos)
2078#define RCC_CFGR2_PLL2MUL9 RCC_CFGR2_PLL2MUL9_Msk
2079#define RCC_CFGR2_PLL2MUL10_Pos (11U)
2080#define RCC_CFGR2_PLL2MUL10_Msk (0x1UL << RCC_CFGR2_PLL2MUL10_Pos)
2081#define RCC_CFGR2_PLL2MUL10 RCC_CFGR2_PLL2MUL10_Msk
2082#define RCC_CFGR2_PLL2MUL11_Pos (8U)
2083#define RCC_CFGR2_PLL2MUL11_Msk (0x9UL << RCC_CFGR2_PLL2MUL11_Pos)
2084#define RCC_CFGR2_PLL2MUL11 RCC_CFGR2_PLL2MUL11_Msk
2085#define RCC_CFGR2_PLL2MUL12_Pos (9U)
2086#define RCC_CFGR2_PLL2MUL12_Msk (0x5UL << RCC_CFGR2_PLL2MUL12_Pos)
2087#define RCC_CFGR2_PLL2MUL12 RCC_CFGR2_PLL2MUL12_Msk
2088#define RCC_CFGR2_PLL2MUL13_Pos (8U)
2089#define RCC_CFGR2_PLL2MUL13_Msk (0xBUL << RCC_CFGR2_PLL2MUL13_Pos)
2090#define RCC_CFGR2_PLL2MUL13 RCC_CFGR2_PLL2MUL13_Msk
2091#define RCC_CFGR2_PLL2MUL14_Pos (10U)
2092#define RCC_CFGR2_PLL2MUL14_Msk (0x3UL << RCC_CFGR2_PLL2MUL14_Pos)
2093#define RCC_CFGR2_PLL2MUL14 RCC_CFGR2_PLL2MUL14_Msk
2094#define RCC_CFGR2_PLL2MUL16_Pos (9U)
2095#define RCC_CFGR2_PLL2MUL16_Msk (0x7UL << RCC_CFGR2_PLL2MUL16_Pos)
2096#define RCC_CFGR2_PLL2MUL16 RCC_CFGR2_PLL2MUL16_Msk
2097#define RCC_CFGR2_PLL2MUL20_Pos (8U)
2098#define RCC_CFGR2_PLL2MUL20_Msk (0xFUL << RCC_CFGR2_PLL2MUL20_Pos)
2099#define RCC_CFGR2_PLL2MUL20 RCC_CFGR2_PLL2MUL20_Msk
2102#define RCC_CFGR2_PLL3MUL_Pos (12U)
2103#define RCC_CFGR2_PLL3MUL_Msk (0xFUL << RCC_CFGR2_PLL3MUL_Pos)
2104#define RCC_CFGR2_PLL3MUL RCC_CFGR2_PLL3MUL_Msk
2105#define RCC_CFGR2_PLL3MUL_0 (0x1UL << RCC_CFGR2_PLL3MUL_Pos)
2106#define RCC_CFGR2_PLL3MUL_1 (0x2UL << RCC_CFGR2_PLL3MUL_Pos)
2107#define RCC_CFGR2_PLL3MUL_2 (0x4UL << RCC_CFGR2_PLL3MUL_Pos)
2108#define RCC_CFGR2_PLL3MUL_3 (0x8UL << RCC_CFGR2_PLL3MUL_Pos)
2110#define RCC_CFGR2_PLL3MUL8_Pos (13U)
2111#define RCC_CFGR2_PLL3MUL8_Msk (0x3UL << RCC_CFGR2_PLL3MUL8_Pos)
2112#define RCC_CFGR2_PLL3MUL8 RCC_CFGR2_PLL3MUL8_Msk
2113#define RCC_CFGR2_PLL3MUL9_Pos (12U)
2114#define RCC_CFGR2_PLL3MUL9_Msk (0x7UL << RCC_CFGR2_PLL3MUL9_Pos)
2115#define RCC_CFGR2_PLL3MUL9 RCC_CFGR2_PLL3MUL9_Msk
2116#define RCC_CFGR2_PLL3MUL10_Pos (15U)
2117#define RCC_CFGR2_PLL3MUL10_Msk (0x1UL << RCC_CFGR2_PLL3MUL10_Pos)
2118#define RCC_CFGR2_PLL3MUL10 RCC_CFGR2_PLL3MUL10_Msk
2119#define RCC_CFGR2_PLL3MUL11_Pos (12U)
2120#define RCC_CFGR2_PLL3MUL11_Msk (0x9UL << RCC_CFGR2_PLL3MUL11_Pos)
2121#define RCC_CFGR2_PLL3MUL11 RCC_CFGR2_PLL3MUL11_Msk
2122#define RCC_CFGR2_PLL3MUL12_Pos (13U)
2123#define RCC_CFGR2_PLL3MUL12_Msk (0x5UL << RCC_CFGR2_PLL3MUL12_Pos)
2124#define RCC_CFGR2_PLL3MUL12 RCC_CFGR2_PLL3MUL12_Msk
2125#define RCC_CFGR2_PLL3MUL13_Pos (12U)
2126#define RCC_CFGR2_PLL3MUL13_Msk (0xBUL << RCC_CFGR2_PLL3MUL13_Pos)
2127#define RCC_CFGR2_PLL3MUL13 RCC_CFGR2_PLL3MUL13_Msk
2128#define RCC_CFGR2_PLL3MUL14_Pos (14U)
2129#define RCC_CFGR2_PLL3MUL14_Msk (0x3UL << RCC_CFGR2_PLL3MUL14_Pos)
2130#define RCC_CFGR2_PLL3MUL14 RCC_CFGR2_PLL3MUL14_Msk
2131#define RCC_CFGR2_PLL3MUL16_Pos (13U)
2132#define RCC_CFGR2_PLL3MUL16_Msk (0x7UL << RCC_CFGR2_PLL3MUL16_Pos)
2133#define RCC_CFGR2_PLL3MUL16 RCC_CFGR2_PLL3MUL16_Msk
2134#define RCC_CFGR2_PLL3MUL20_Pos (12U)
2135#define RCC_CFGR2_PLL3MUL20_Msk (0xFUL << RCC_CFGR2_PLL3MUL20_Pos)
2136#define RCC_CFGR2_PLL3MUL20 RCC_CFGR2_PLL3MUL20_Msk
2138#define RCC_CFGR2_PREDIV1SRC_Pos (16U)
2139#define RCC_CFGR2_PREDIV1SRC_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_Pos)
2140#define RCC_CFGR2_PREDIV1SRC RCC_CFGR2_PREDIV1SRC_Msk
2141#define RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U)
2142#define RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_PLL2_Pos)
2143#define RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk
2144#define RCC_CFGR2_PREDIV1SRC_HSE 0x00000000U
2145#define RCC_CFGR2_I2S2SRC_Pos (17U)
2146#define RCC_CFGR2_I2S2SRC_Msk (0x1UL << RCC_CFGR2_I2S2SRC_Pos)
2147#define RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk
2148#define RCC_CFGR2_I2S3SRC_Pos (18U)
2149#define RCC_CFGR2_I2S3SRC_Msk (0x1UL << RCC_CFGR2_I2S3SRC_Pos)
2150#define RCC_CFGR2_I2S3SRC RCC_CFGR2_I2S3SRC_Msk
2153/******************************************************************************/
2154/* */
2155/* General Purpose and Alternate Function I/O */
2156/* */
2157/******************************************************************************/
2158
2159/******************* Bit definition for GPIO_CRL register *******************/
2160#define GPIO_CRL_MODE_Pos (0U)
2161#define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos)
2162#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk
2164#define GPIO_CRL_MODE0_Pos (0U)
2165#define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos)
2166#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk
2167#define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos)
2168#define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos)
2170#define GPIO_CRL_MODE1_Pos (4U)
2171#define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos)
2172#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk
2173#define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos)
2174#define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos)
2176#define GPIO_CRL_MODE2_Pos (8U)
2177#define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos)
2178#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk
2179#define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos)
2180#define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos)
2182#define GPIO_CRL_MODE3_Pos (12U)
2183#define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos)
2184#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk
2185#define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos)
2186#define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos)
2188#define GPIO_CRL_MODE4_Pos (16U)
2189#define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos)
2190#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk
2191#define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos)
2192#define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos)
2194#define GPIO_CRL_MODE5_Pos (20U)
2195#define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos)
2196#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk
2197#define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos)
2198#define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos)
2200#define GPIO_CRL_MODE6_Pos (24U)
2201#define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos)
2202#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk
2203#define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos)
2204#define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos)
2206#define GPIO_CRL_MODE7_Pos (28U)
2207#define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos)
2208#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk
2209#define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos)
2210#define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos)
2212#define GPIO_CRL_CNF_Pos (2U)
2213#define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos)
2214#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk
2216#define GPIO_CRL_CNF0_Pos (2U)
2217#define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos)
2218#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk
2219#define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos)
2220#define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos)
2222#define GPIO_CRL_CNF1_Pos (6U)
2223#define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos)
2224#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk
2225#define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos)
2226#define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos)
2228#define GPIO_CRL_CNF2_Pos (10U)
2229#define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos)
2230#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk
2231#define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos)
2232#define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos)
2234#define GPIO_CRL_CNF3_Pos (14U)
2235#define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos)
2236#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk
2237#define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos)
2238#define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos)
2240#define GPIO_CRL_CNF4_Pos (18U)
2241#define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos)
2242#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk
2243#define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos)
2244#define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos)
2246#define GPIO_CRL_CNF5_Pos (22U)
2247#define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos)
2248#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk
2249#define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos)
2250#define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos)
2252#define GPIO_CRL_CNF6_Pos (26U)
2253#define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos)
2254#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk
2255#define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos)
2256#define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos)
2258#define GPIO_CRL_CNF7_Pos (30U)
2259#define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos)
2260#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk
2261#define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos)
2262#define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos)
2264/******************* Bit definition for GPIO_CRH register *******************/
2265#define GPIO_CRH_MODE_Pos (0U)
2266#define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos)
2267#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk
2269#define GPIO_CRH_MODE8_Pos (0U)
2270#define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos)
2271#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk
2272#define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos)
2273#define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos)
2275#define GPIO_CRH_MODE9_Pos (4U)
2276#define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos)
2277#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk
2278#define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos)
2279#define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos)
2281#define GPIO_CRH_MODE10_Pos (8U)
2282#define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos)
2283#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk
2284#define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos)
2285#define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos)
2287#define GPIO_CRH_MODE11_Pos (12U)
2288#define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos)
2289#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk
2290#define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos)
2291#define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos)
2293#define GPIO_CRH_MODE12_Pos (16U)
2294#define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos)
2295#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk
2296#define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos)
2297#define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos)
2299#define GPIO_CRH_MODE13_Pos (20U)
2300#define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos)
2301#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk
2302#define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos)
2303#define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos)
2305#define GPIO_CRH_MODE14_Pos (24U)
2306#define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos)
2307#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk
2308#define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos)
2309#define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos)
2311#define GPIO_CRH_MODE15_Pos (28U)
2312#define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos)
2313#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk
2314#define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos)
2315#define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos)
2317#define GPIO_CRH_CNF_Pos (2U)
2318#define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos)
2319#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk
2321#define GPIO_CRH_CNF8_Pos (2U)
2322#define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos)
2323#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk
2324#define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos)
2325#define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos)
2327#define GPIO_CRH_CNF9_Pos (6U)
2328#define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos)
2329#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk
2330#define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos)
2331#define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos)
2333#define GPIO_CRH_CNF10_Pos (10U)
2334#define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos)
2335#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk
2336#define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos)
2337#define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos)
2339#define GPIO_CRH_CNF11_Pos (14U)
2340#define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos)
2341#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk
2342#define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos)
2343#define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos)
2345#define GPIO_CRH_CNF12_Pos (18U)
2346#define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos)
2347#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk
2348#define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos)
2349#define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos)
2351#define GPIO_CRH_CNF13_Pos (22U)
2352#define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos)
2353#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk
2354#define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos)
2355#define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos)
2357#define GPIO_CRH_CNF14_Pos (26U)
2358#define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos)
2359#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk
2360#define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos)
2361#define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos)
2363#define GPIO_CRH_CNF15_Pos (30U)
2364#define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos)
2365#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk
2366#define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos)
2367#define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos)
2370#define GPIO_IDR_IDR0_Pos (0U)
2371#define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos)
2372#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk
2373#define GPIO_IDR_IDR1_Pos (1U)
2374#define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos)
2375#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk
2376#define GPIO_IDR_IDR2_Pos (2U)
2377#define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos)
2378#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk
2379#define GPIO_IDR_IDR3_Pos (3U)
2380#define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos)
2381#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk
2382#define GPIO_IDR_IDR4_Pos (4U)
2383#define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos)
2384#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk
2385#define GPIO_IDR_IDR5_Pos (5U)
2386#define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos)
2387#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk
2388#define GPIO_IDR_IDR6_Pos (6U)
2389#define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos)
2390#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk
2391#define GPIO_IDR_IDR7_Pos (7U)
2392#define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos)
2393#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk
2394#define GPIO_IDR_IDR8_Pos (8U)
2395#define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos)
2396#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk
2397#define GPIO_IDR_IDR9_Pos (9U)
2398#define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos)
2399#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk
2400#define GPIO_IDR_IDR10_Pos (10U)
2401#define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos)
2402#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk
2403#define GPIO_IDR_IDR11_Pos (11U)
2404#define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos)
2405#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk
2406#define GPIO_IDR_IDR12_Pos (12U)
2407#define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos)
2408#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk
2409#define GPIO_IDR_IDR13_Pos (13U)
2410#define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos)
2411#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk
2412#define GPIO_IDR_IDR14_Pos (14U)
2413#define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos)
2414#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk
2415#define GPIO_IDR_IDR15_Pos (15U)
2416#define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos)
2417#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk
2419/******************* Bit definition for GPIO_ODR register *******************/
2420#define GPIO_ODR_ODR0_Pos (0U)
2421#define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos)
2422#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk
2423#define GPIO_ODR_ODR1_Pos (1U)
2424#define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos)
2425#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk
2426#define GPIO_ODR_ODR2_Pos (2U)
2427#define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos)
2428#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk
2429#define GPIO_ODR_ODR3_Pos (3U)
2430#define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos)
2431#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk
2432#define GPIO_ODR_ODR4_Pos (4U)
2433#define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos)
2434#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk
2435#define GPIO_ODR_ODR5_Pos (5U)
2436#define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos)
2437#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk
2438#define GPIO_ODR_ODR6_Pos (6U)
2439#define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos)
2440#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk
2441#define GPIO_ODR_ODR7_Pos (7U)
2442#define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos)
2443#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk
2444#define GPIO_ODR_ODR8_Pos (8U)
2445#define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos)
2446#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk
2447#define GPIO_ODR_ODR9_Pos (9U)
2448#define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos)
2449#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk
2450#define GPIO_ODR_ODR10_Pos (10U)
2451#define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos)
2452#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk
2453#define GPIO_ODR_ODR11_Pos (11U)
2454#define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos)
2455#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk
2456#define GPIO_ODR_ODR12_Pos (12U)
2457#define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos)
2458#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk
2459#define GPIO_ODR_ODR13_Pos (13U)
2460#define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos)
2461#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk
2462#define GPIO_ODR_ODR14_Pos (14U)
2463#define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos)
2464#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk
2465#define GPIO_ODR_ODR15_Pos (15U)
2466#define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos)
2467#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk
2469/****************** Bit definition for GPIO_BSRR register *******************/
2470#define GPIO_BSRR_BS0_Pos (0U)
2471#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
2472#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
2473#define GPIO_BSRR_BS1_Pos (1U)
2474#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
2475#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
2476#define GPIO_BSRR_BS2_Pos (2U)
2477#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
2478#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
2479#define GPIO_BSRR_BS3_Pos (3U)
2480#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
2481#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
2482#define GPIO_BSRR_BS4_Pos (4U)
2483#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
2484#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
2485#define GPIO_BSRR_BS5_Pos (5U)
2486#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
2487#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
2488#define GPIO_BSRR_BS6_Pos (6U)
2489#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
2490#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
2491#define GPIO_BSRR_BS7_Pos (7U)
2492#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
2493#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
2494#define GPIO_BSRR_BS8_Pos (8U)
2495#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
2496#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
2497#define GPIO_BSRR_BS9_Pos (9U)
2498#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
2499#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
2500#define GPIO_BSRR_BS10_Pos (10U)
2501#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
2502#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
2503#define GPIO_BSRR_BS11_Pos (11U)
2504#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
2505#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
2506#define GPIO_BSRR_BS12_Pos (12U)
2507#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
2508#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
2509#define GPIO_BSRR_BS13_Pos (13U)
2510#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
2511#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
2512#define GPIO_BSRR_BS14_Pos (14U)
2513#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
2514#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
2515#define GPIO_BSRR_BS15_Pos (15U)
2516#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
2517#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
2519#define GPIO_BSRR_BR0_Pos (16U)
2520#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
2521#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
2522#define GPIO_BSRR_BR1_Pos (17U)
2523#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
2524#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
2525#define GPIO_BSRR_BR2_Pos (18U)
2526#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
2527#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
2528#define GPIO_BSRR_BR3_Pos (19U)
2529#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
2530#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
2531#define GPIO_BSRR_BR4_Pos (20U)
2532#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
2533#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
2534#define GPIO_BSRR_BR5_Pos (21U)
2535#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
2536#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
2537#define GPIO_BSRR_BR6_Pos (22U)
2538#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
2539#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
2540#define GPIO_BSRR_BR7_Pos (23U)
2541#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
2542#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
2543#define GPIO_BSRR_BR8_Pos (24U)
2544#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
2545#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
2546#define GPIO_BSRR_BR9_Pos (25U)
2547#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
2548#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
2549#define GPIO_BSRR_BR10_Pos (26U)
2550#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
2551#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
2552#define GPIO_BSRR_BR11_Pos (27U)
2553#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
2554#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
2555#define GPIO_BSRR_BR12_Pos (28U)
2556#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
2557#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
2558#define GPIO_BSRR_BR13_Pos (29U)
2559#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
2560#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
2561#define GPIO_BSRR_BR14_Pos (30U)
2562#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
2563#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
2564#define GPIO_BSRR_BR15_Pos (31U)
2565#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
2566#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
2568/******************* Bit definition for GPIO_BRR register *******************/
2569#define GPIO_BRR_BR0_Pos (0U)
2570#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)
2571#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
2572#define GPIO_BRR_BR1_Pos (1U)
2573#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)
2574#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
2575#define GPIO_BRR_BR2_Pos (2U)
2576#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)
2577#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
2578#define GPIO_BRR_BR3_Pos (3U)
2579#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)
2580#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
2581#define GPIO_BRR_BR4_Pos (4U)
2582#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)
2583#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
2584#define GPIO_BRR_BR5_Pos (5U)
2585#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)
2586#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
2587#define GPIO_BRR_BR6_Pos (6U)
2588#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)
2589#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
2590#define GPIO_BRR_BR7_Pos (7U)
2591#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)
2592#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
2593#define GPIO_BRR_BR8_Pos (8U)
2594#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)
2595#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
2596#define GPIO_BRR_BR9_Pos (9U)
2597#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)
2598#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
2599#define GPIO_BRR_BR10_Pos (10U)
2600#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)
2601#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
2602#define GPIO_BRR_BR11_Pos (11U)
2603#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)
2604#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
2605#define GPIO_BRR_BR12_Pos (12U)
2606#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)
2607#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
2608#define GPIO_BRR_BR13_Pos (13U)
2609#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)
2610#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
2611#define GPIO_BRR_BR14_Pos (14U)
2612#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)
2613#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
2614#define GPIO_BRR_BR15_Pos (15U)
2615#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)
2616#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
2618/****************** Bit definition for GPIO_LCKR register *******************/
2619#define GPIO_LCKR_LCK0_Pos (0U)
2620#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
2621#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
2622#define GPIO_LCKR_LCK1_Pos (1U)
2623#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
2624#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
2625#define GPIO_LCKR_LCK2_Pos (2U)
2626#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
2627#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
2628#define GPIO_LCKR_LCK3_Pos (3U)
2629#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
2630#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
2631#define GPIO_LCKR_LCK4_Pos (4U)
2632#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
2633#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
2634#define GPIO_LCKR_LCK5_Pos (5U)
2635#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
2636#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
2637#define GPIO_LCKR_LCK6_Pos (6U)
2638#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
2639#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
2640#define GPIO_LCKR_LCK7_Pos (7U)
2641#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
2642#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
2643#define GPIO_LCKR_LCK8_Pos (8U)
2644#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
2645#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
2646#define GPIO_LCKR_LCK9_Pos (9U)
2647#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
2648#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
2649#define GPIO_LCKR_LCK10_Pos (10U)
2650#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
2651#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
2652#define GPIO_LCKR_LCK11_Pos (11U)
2653#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
2654#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
2655#define GPIO_LCKR_LCK12_Pos (12U)
2656#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
2657#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
2658#define GPIO_LCKR_LCK13_Pos (13U)
2659#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
2660#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
2661#define GPIO_LCKR_LCK14_Pos (14U)
2662#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
2663#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
2664#define GPIO_LCKR_LCK15_Pos (15U)
2665#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
2666#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
2667#define GPIO_LCKR_LCKK_Pos (16U)
2668#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
2669#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
2671/*----------------------------------------------------------------------------*/
2672
2673/****************** Bit definition for AFIO_EVCR register *******************/
2674#define AFIO_EVCR_PIN_Pos (0U)
2675#define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos)
2676#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk
2677#define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos)
2678#define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos)
2679#define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos)
2680#define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos)
2683#define AFIO_EVCR_PIN_PX0 0x00000000U
2684#define AFIO_EVCR_PIN_PX1_Pos (0U)
2685#define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos)
2686#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk
2687#define AFIO_EVCR_PIN_PX2_Pos (1U)
2688#define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos)
2689#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk
2690#define AFIO_EVCR_PIN_PX3_Pos (0U)
2691#define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos)
2692#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk
2693#define AFIO_EVCR_PIN_PX4_Pos (2U)
2694#define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos)
2695#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk
2696#define AFIO_EVCR_PIN_PX5_Pos (0U)
2697#define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos)
2698#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk
2699#define AFIO_EVCR_PIN_PX6_Pos (1U)
2700#define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos)
2701#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk
2702#define AFIO_EVCR_PIN_PX7_Pos (0U)
2703#define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos)
2704#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk
2705#define AFIO_EVCR_PIN_PX8_Pos (3U)
2706#define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos)
2707#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk
2708#define AFIO_EVCR_PIN_PX9_Pos (0U)
2709#define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos)
2710#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk
2711#define AFIO_EVCR_PIN_PX10_Pos (1U)
2712#define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos)
2713#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk
2714#define AFIO_EVCR_PIN_PX11_Pos (0U)
2715#define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos)
2716#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk
2717#define AFIO_EVCR_PIN_PX12_Pos (2U)
2718#define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos)
2719#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk
2720#define AFIO_EVCR_PIN_PX13_Pos (0U)
2721#define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos)
2722#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk
2723#define AFIO_EVCR_PIN_PX14_Pos (1U)
2724#define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos)
2725#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk
2726#define AFIO_EVCR_PIN_PX15_Pos (0U)
2727#define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos)
2728#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk
2730#define AFIO_EVCR_PORT_Pos (4U)
2731#define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos)
2732#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk
2733#define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos)
2734#define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos)
2735#define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos)
2738#define AFIO_EVCR_PORT_PA 0x00000000
2739#define AFIO_EVCR_PORT_PB_Pos (4U)
2740#define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos)
2741#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk
2742#define AFIO_EVCR_PORT_PC_Pos (5U)
2743#define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos)
2744#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk
2745#define AFIO_EVCR_PORT_PD_Pos (4U)
2746#define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos)
2747#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk
2748#define AFIO_EVCR_PORT_PE_Pos (6U)
2749#define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos)
2750#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk
2752#define AFIO_EVCR_EVOE_Pos (7U)
2753#define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos)
2754#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk
2756/****************** Bit definition for AFIO_MAPR register *******************/
2757#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
2758#define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos)
2759#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk
2760#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
2761#define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos)
2762#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk
2763#define AFIO_MAPR_USART1_REMAP_Pos (2U)
2764#define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos)
2765#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk
2766#define AFIO_MAPR_USART2_REMAP_Pos (3U)
2767#define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos)
2768#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk
2770#define AFIO_MAPR_USART3_REMAP_Pos (4U)
2771#define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos)
2772#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk
2773#define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos)
2774#define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos)
2776/* USART3_REMAP configuration */
2777#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U
2778#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
2779#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos)
2780#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk
2781#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
2782#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos)
2783#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk
2785#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
2786#define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos)
2787#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk
2788#define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos)
2789#define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos)
2792#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U
2793#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
2794#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos)
2795#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk
2796#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
2797#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos)
2798#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk
2800#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
2801#define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos)
2802#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk
2803#define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos)
2804#define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos)
2807#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U
2808#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
2809#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos)
2810#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk
2811#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
2812#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos)
2813#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk
2814#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
2815#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos)
2816#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk
2818#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
2819#define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos)
2820#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk
2821#define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos)
2822#define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos)
2825#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U
2826#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
2827#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos)
2828#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk
2829#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
2830#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos)
2831#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk
2833#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
2834#define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos)
2835#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk
2837#define AFIO_MAPR_CAN_REMAP_Pos (13U)
2838#define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos)
2839#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk
2840#define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos)
2841#define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos)
2844#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U
2845#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
2846#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos)
2847#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk
2848#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
2849#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos)
2850#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk
2852#define AFIO_MAPR_PD01_REMAP_Pos (15U)
2853#define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos)
2854#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk
2855#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)
2856#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos)
2857#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk
2860#define AFIO_MAPR_SWJ_CFG_Pos (24U)
2861#define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos)
2862#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk
2863#define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos)
2864#define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos)
2865#define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos)
2867#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U
2868#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
2869#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos)
2870#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk
2871#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
2872#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos)
2873#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk
2874#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
2875#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos)
2876#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk
2879#define AFIO_MAPR_ETH_REMAP_Pos (21U)
2880#define AFIO_MAPR_ETH_REMAP_Msk (0x1UL << AFIO_MAPR_ETH_REMAP_Pos)
2881#define AFIO_MAPR_ETH_REMAP AFIO_MAPR_ETH_REMAP_Msk
2884#define AFIO_MAPR_CAN2_REMAP_Pos (22U)
2885#define AFIO_MAPR_CAN2_REMAP_Msk (0x1UL << AFIO_MAPR_CAN2_REMAP_Pos)
2886#define AFIO_MAPR_CAN2_REMAP AFIO_MAPR_CAN2_REMAP_Msk
2889#define AFIO_MAPR_MII_RMII_SEL_Pos (23U)
2890#define AFIO_MAPR_MII_RMII_SEL_Msk (0x1UL << AFIO_MAPR_MII_RMII_SEL_Pos)
2891#define AFIO_MAPR_MII_RMII_SEL AFIO_MAPR_MII_RMII_SEL_Msk
2894#define AFIO_MAPR_SPI3_REMAP_Pos (28U)
2895#define AFIO_MAPR_SPI3_REMAP_Msk (0x1UL << AFIO_MAPR_SPI3_REMAP_Pos)
2896#define AFIO_MAPR_SPI3_REMAP AFIO_MAPR_SPI3_REMAP_Msk
2899#define AFIO_MAPR_TIM2ITR1_IREMAP_Pos (29U)
2900#define AFIO_MAPR_TIM2ITR1_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM2ITR1_IREMAP_Pos)
2901#define AFIO_MAPR_TIM2ITR1_IREMAP AFIO_MAPR_TIM2ITR1_IREMAP_Msk
2904#define AFIO_MAPR_PTP_PPS_REMAP_Pos (30U)
2905#define AFIO_MAPR_PTP_PPS_REMAP_Msk (0x1UL << AFIO_MAPR_PTP_PPS_REMAP_Pos)
2906#define AFIO_MAPR_PTP_PPS_REMAP AFIO_MAPR_PTP_PPS_REMAP_Msk
2908/***************** Bit definition for AFIO_EXTICR1 register *****************/
2909#define AFIO_EXTICR1_EXTI0_Pos (0U)
2910#define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos)
2911#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk
2912#define AFIO_EXTICR1_EXTI1_Pos (4U)
2913#define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos)
2914#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk
2915#define AFIO_EXTICR1_EXTI2_Pos (8U)
2916#define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos)
2917#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk
2918#define AFIO_EXTICR1_EXTI3_Pos (12U)
2919#define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos)
2920#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk
2923#define AFIO_EXTICR1_EXTI0_PA 0x00000000U
2924#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
2925#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos)
2926#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk
2927#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
2928#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos)
2929#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk
2930#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
2931#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos)
2932#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk
2933#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
2934#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos)
2935#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk
2936#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
2937#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos)
2938#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk
2939#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
2940#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos)
2941#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk
2944#define AFIO_EXTICR1_EXTI1_PA 0x00000000U
2945#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
2946#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos)
2947#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk
2948#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
2949#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos)
2950#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk
2951#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
2952#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos)
2953#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk
2954#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
2955#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos)
2956#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk
2957#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
2958#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos)
2959#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk
2960#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
2961#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos)
2962#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk
2965#define AFIO_EXTICR1_EXTI2_PA 0x00000000U
2966#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
2967#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos)
2968#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk
2969#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
2970#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos)
2971#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk
2972#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
2973#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos)
2974#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk
2975#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
2976#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos)
2977#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk
2978#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
2979#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos)
2980#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk
2981#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
2982#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos)
2983#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk
2986#define AFIO_EXTICR1_EXTI3_PA 0x00000000U
2987#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
2988#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos)
2989#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk
2990#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
2991#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos)
2992#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk
2993#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
2994#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos)
2995#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk
2996#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
2997#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos)
2998#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk
2999#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
3000#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos)
3001#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk
3002#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
3003#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos)
3004#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk
3006/***************** Bit definition for AFIO_EXTICR2 register *****************/
3007#define AFIO_EXTICR2_EXTI4_Pos (0U)
3008#define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos)
3009#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk
3010#define AFIO_EXTICR2_EXTI5_Pos (4U)
3011#define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos)
3012#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk
3013#define AFIO_EXTICR2_EXTI6_Pos (8U)
3014#define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos)
3015#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk
3016#define AFIO_EXTICR2_EXTI7_Pos (12U)
3017#define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos)
3018#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk
3021#define AFIO_EXTICR2_EXTI4_PA 0x00000000U
3022#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
3023#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos)
3024#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk
3025#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
3026#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos)
3027#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk
3028#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
3029#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos)
3030#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk
3031#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
3032#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos)
3033#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk
3034#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
3035#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos)
3036#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk
3037#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
3038#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos)
3039#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk
3041/* EXTI5 configuration */
3042#define AFIO_EXTICR2_EXTI5_PA 0x00000000U
3043#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
3044#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos)
3045#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk
3046#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
3047#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos)
3048#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk
3049#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
3050#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos)
3051#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk
3052#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
3053#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos)
3054#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk
3055#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
3056#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos)
3057#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk
3058#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
3059#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos)
3060#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk
3063#define AFIO_EXTICR2_EXTI6_PA 0x00000000U
3064#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
3065#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos)
3066#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk
3067#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
3068#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos)
3069#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk
3070#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
3071#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos)
3072#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk
3073#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
3074#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos)
3075#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk
3076#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
3077#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos)
3078#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk
3079#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
3080#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos)
3081#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk
3084#define AFIO_EXTICR2_EXTI7_PA 0x00000000U
3085#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
3086#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos)
3087#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk
3088#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
3089#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos)
3090#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk
3091#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
3092#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos)
3093#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk
3094#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
3095#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos)
3096#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk
3097#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
3098#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos)
3099#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk
3100#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
3101#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos)
3102#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk
3104/***************** Bit definition for AFIO_EXTICR3 register *****************/
3105#define AFIO_EXTICR3_EXTI8_Pos (0U)
3106#define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos)
3107#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk
3108#define AFIO_EXTICR3_EXTI9_Pos (4U)
3109#define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos)
3110#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk
3111#define AFIO_EXTICR3_EXTI10_Pos (8U)
3112#define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos)
3113#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk
3114#define AFIO_EXTICR3_EXTI11_Pos (12U)
3115#define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos)
3116#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk
3119#define AFIO_EXTICR3_EXTI8_PA 0x00000000U
3120#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
3121#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos)
3122#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk
3123#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
3124#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos)
3125#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk
3126#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
3127#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos)
3128#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk
3129#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
3130#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos)
3131#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk
3132#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
3133#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos)
3134#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk
3135#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
3136#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos)
3137#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk
3140#define AFIO_EXTICR3_EXTI9_PA 0x00000000U
3141#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
3142#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos)
3143#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk
3144#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
3145#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos)
3146#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk
3147#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
3148#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos)
3149#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk
3150#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
3151#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos)
3152#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk
3153#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
3154#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos)
3155#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk
3156#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
3157#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos)
3158#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk
3161#define AFIO_EXTICR3_EXTI10_PA 0x00000000U
3162#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
3163#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos)
3164#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk
3165#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
3166#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos)
3167#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk
3168#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
3169#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos)
3170#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk
3171#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
3172#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos)
3173#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk
3174#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
3175#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos)
3176#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk
3177#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
3178#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos)
3179#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk
3182#define AFIO_EXTICR3_EXTI11_PA 0x00000000U
3183#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
3184#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos)
3185#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk
3186#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
3187#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos)
3188#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk
3189#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
3190#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos)
3191#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk
3192#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
3193#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos)
3194#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk
3195#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
3196#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos)
3197#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk
3198#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
3199#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos)
3200#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk
3202/***************** Bit definition for AFIO_EXTICR4 register *****************/
3203#define AFIO_EXTICR4_EXTI12_Pos (0U)
3204#define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos)
3205#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk
3206#define AFIO_EXTICR4_EXTI13_Pos (4U)
3207#define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos)
3208#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk
3209#define AFIO_EXTICR4_EXTI14_Pos (8U)
3210#define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos)
3211#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk
3212#define AFIO_EXTICR4_EXTI15_Pos (12U)
3213#define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos)
3214#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk
3216/* EXTI12 configuration */
3217#define AFIO_EXTICR4_EXTI12_PA 0x00000000U
3218#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
3219#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos)
3220#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk
3221#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
3222#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos)
3223#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk
3224#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
3225#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos)
3226#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk
3227#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
3228#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos)
3229#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk
3230#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
3231#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos)
3232#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk
3233#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
3234#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos)
3235#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk
3237/* EXTI13 configuration */
3238#define AFIO_EXTICR4_EXTI13_PA 0x00000000U
3239#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
3240#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos)
3241#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk
3242#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
3243#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos)
3244#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk
3245#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
3246#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos)
3247#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk
3248#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
3249#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos)
3250#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk
3251#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
3252#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos)
3253#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk
3254#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
3255#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos)
3256#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk
3259#define AFIO_EXTICR4_EXTI14_PA 0x00000000U
3260#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
3261#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos)
3262#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk
3263#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
3264#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos)
3265#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk
3266#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
3267#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos)
3268#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk
3269#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
3270#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos)
3271#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk
3272#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
3273#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos)
3274#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk
3275#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
3276#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos)
3277#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk
3280#define AFIO_EXTICR4_EXTI15_PA 0x00000000U
3281#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
3282#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos)
3283#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk
3284#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
3285#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos)
3286#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk
3287#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
3288#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos)
3289#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk
3290#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
3291#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos)
3292#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk
3293#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
3294#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos)
3295#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk
3296#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
3297#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos)
3298#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk
3300/****************** Bit definition for AFIO_MAPR2 register ******************/
3301
3302
3303
3304/******************************************************************************/
3305/* */
3306/* External Interrupt/Event Controller */
3307/* */
3308/******************************************************************************/
3309
3310/******************* Bit definition for EXTI_IMR register *******************/
3311#define EXTI_IMR_MR0_Pos (0U)
3312#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
3313#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
3314#define EXTI_IMR_MR1_Pos (1U)
3315#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
3316#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
3317#define EXTI_IMR_MR2_Pos (2U)
3318#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
3319#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
3320#define EXTI_IMR_MR3_Pos (3U)
3321#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
3322#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
3323#define EXTI_IMR_MR4_Pos (4U)
3324#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
3325#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
3326#define EXTI_IMR_MR5_Pos (5U)
3327#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
3328#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
3329#define EXTI_IMR_MR6_Pos (6U)
3330#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
3331#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
3332#define EXTI_IMR_MR7_Pos (7U)
3333#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
3334#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
3335#define EXTI_IMR_MR8_Pos (8U)
3336#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
3337#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
3338#define EXTI_IMR_MR9_Pos (9U)
3339#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
3340#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
3341#define EXTI_IMR_MR10_Pos (10U)
3342#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
3343#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
3344#define EXTI_IMR_MR11_Pos (11U)
3345#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
3346#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
3347#define EXTI_IMR_MR12_Pos (12U)
3348#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
3349#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
3350#define EXTI_IMR_MR13_Pos (13U)
3351#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
3352#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
3353#define EXTI_IMR_MR14_Pos (14U)
3354#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
3355#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
3356#define EXTI_IMR_MR15_Pos (15U)
3357#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
3358#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
3359#define EXTI_IMR_MR16_Pos (16U)
3360#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
3361#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
3362#define EXTI_IMR_MR17_Pos (17U)
3363#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
3364#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
3365#define EXTI_IMR_MR18_Pos (18U)
3366#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
3367#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
3368#define EXTI_IMR_MR19_Pos (19U)
3369#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
3370#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
3372/* References Defines */
3373#define EXTI_IMR_IM0 EXTI_IMR_MR0
3374#define EXTI_IMR_IM1 EXTI_IMR_MR1
3375#define EXTI_IMR_IM2 EXTI_IMR_MR2
3376#define EXTI_IMR_IM3 EXTI_IMR_MR3
3377#define EXTI_IMR_IM4 EXTI_IMR_MR4
3378#define EXTI_IMR_IM5 EXTI_IMR_MR5
3379#define EXTI_IMR_IM6 EXTI_IMR_MR6
3380#define EXTI_IMR_IM7 EXTI_IMR_MR7
3381#define EXTI_IMR_IM8 EXTI_IMR_MR8
3382#define EXTI_IMR_IM9 EXTI_IMR_MR9
3383#define EXTI_IMR_IM10 EXTI_IMR_MR10
3384#define EXTI_IMR_IM11 EXTI_IMR_MR11
3385#define EXTI_IMR_IM12 EXTI_IMR_MR12
3386#define EXTI_IMR_IM13 EXTI_IMR_MR13
3387#define EXTI_IMR_IM14 EXTI_IMR_MR14
3388#define EXTI_IMR_IM15 EXTI_IMR_MR15
3389#define EXTI_IMR_IM16 EXTI_IMR_MR16
3390#define EXTI_IMR_IM17 EXTI_IMR_MR17
3391#define EXTI_IMR_IM18 EXTI_IMR_MR18
3392#define EXTI_IMR_IM19 EXTI_IMR_MR19
3393#define EXTI_IMR_IM 0x000FFFFFU
3395/******************* Bit definition for EXTI_EMR register *******************/
3396#define EXTI_EMR_MR0_Pos (0U)
3397#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
3398#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
3399#define EXTI_EMR_MR1_Pos (1U)
3400#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
3401#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
3402#define EXTI_EMR_MR2_Pos (2U)
3403#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
3404#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
3405#define EXTI_EMR_MR3_Pos (3U)
3406#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
3407#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
3408#define EXTI_EMR_MR4_Pos (4U)
3409#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
3410#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
3411#define EXTI_EMR_MR5_Pos (5U)
3412#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
3413#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
3414#define EXTI_EMR_MR6_Pos (6U)
3415#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
3416#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
3417#define EXTI_EMR_MR7_Pos (7U)
3418#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
3419#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
3420#define EXTI_EMR_MR8_Pos (8U)
3421#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
3422#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
3423#define EXTI_EMR_MR9_Pos (9U)
3424#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
3425#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
3426#define EXTI_EMR_MR10_Pos (10U)
3427#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
3428#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
3429#define EXTI_EMR_MR11_Pos (11U)
3430#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
3431#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
3432#define EXTI_EMR_MR12_Pos (12U)
3433#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
3434#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
3435#define EXTI_EMR_MR13_Pos (13U)
3436#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
3437#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
3438#define EXTI_EMR_MR14_Pos (14U)
3439#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
3440#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
3441#define EXTI_EMR_MR15_Pos (15U)
3442#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
3443#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
3444#define EXTI_EMR_MR16_Pos (16U)
3445#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
3446#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
3447#define EXTI_EMR_MR17_Pos (17U)
3448#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
3449#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
3450#define EXTI_EMR_MR18_Pos (18U)
3451#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
3452#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
3453#define EXTI_EMR_MR19_Pos (19U)
3454#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
3455#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
3457/* References Defines */
3458#define EXTI_EMR_EM0 EXTI_EMR_MR0
3459#define EXTI_EMR_EM1 EXTI_EMR_MR1
3460#define EXTI_EMR_EM2 EXTI_EMR_MR2
3461#define EXTI_EMR_EM3 EXTI_EMR_MR3
3462#define EXTI_EMR_EM4 EXTI_EMR_MR4
3463#define EXTI_EMR_EM5 EXTI_EMR_MR5
3464#define EXTI_EMR_EM6 EXTI_EMR_MR6
3465#define EXTI_EMR_EM7 EXTI_EMR_MR7
3466#define EXTI_EMR_EM8 EXTI_EMR_MR8
3467#define EXTI_EMR_EM9 EXTI_EMR_MR9
3468#define EXTI_EMR_EM10 EXTI_EMR_MR10
3469#define EXTI_EMR_EM11 EXTI_EMR_MR11
3470#define EXTI_EMR_EM12 EXTI_EMR_MR12
3471#define EXTI_EMR_EM13 EXTI_EMR_MR13
3472#define EXTI_EMR_EM14 EXTI_EMR_MR14
3473#define EXTI_EMR_EM15 EXTI_EMR_MR15
3474#define EXTI_EMR_EM16 EXTI_EMR_MR16
3475#define EXTI_EMR_EM17 EXTI_EMR_MR17
3476#define EXTI_EMR_EM18 EXTI_EMR_MR18
3477#define EXTI_EMR_EM19 EXTI_EMR_MR19
3478
3479/****************** Bit definition for EXTI_RTSR register *******************/
3480#define EXTI_RTSR_TR0_Pos (0U)
3481#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
3482#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
3483#define EXTI_RTSR_TR1_Pos (1U)
3484#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
3485#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
3486#define EXTI_RTSR_TR2_Pos (2U)
3487#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
3488#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
3489#define EXTI_RTSR_TR3_Pos (3U)
3490#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
3491#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
3492#define EXTI_RTSR_TR4_Pos (4U)
3493#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
3494#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
3495#define EXTI_RTSR_TR5_Pos (5U)
3496#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
3497#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
3498#define EXTI_RTSR_TR6_Pos (6U)
3499#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
3500#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
3501#define EXTI_RTSR_TR7_Pos (7U)
3502#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
3503#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
3504#define EXTI_RTSR_TR8_Pos (8U)
3505#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
3506#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
3507#define EXTI_RTSR_TR9_Pos (9U)
3508#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
3509#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
3510#define EXTI_RTSR_TR10_Pos (10U)
3511#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
3512#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
3513#define EXTI_RTSR_TR11_Pos (11U)
3514#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
3515#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
3516#define EXTI_RTSR_TR12_Pos (12U)
3517#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
3518#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
3519#define EXTI_RTSR_TR13_Pos (13U)
3520#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
3521#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
3522#define EXTI_RTSR_TR14_Pos (14U)
3523#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
3524#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
3525#define EXTI_RTSR_TR15_Pos (15U)
3526#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
3527#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
3528#define EXTI_RTSR_TR16_Pos (16U)
3529#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
3530#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
3531#define EXTI_RTSR_TR17_Pos (17U)
3532#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
3533#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
3534#define EXTI_RTSR_TR18_Pos (18U)
3535#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
3536#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
3537#define EXTI_RTSR_TR19_Pos (19U)
3538#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
3539#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
3541/* References Defines */
3542#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
3543#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
3544#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
3545#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
3546#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
3547#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
3548#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
3549#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
3550#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
3551#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
3552#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
3553#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
3554#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
3555#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
3556#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
3557#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
3558#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
3559#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
3560#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
3561#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
3562
3563/****************** Bit definition for EXTI_FTSR register *******************/
3564#define EXTI_FTSR_TR0_Pos (0U)
3565#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
3566#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
3567#define EXTI_FTSR_TR1_Pos (1U)
3568#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
3569#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
3570#define EXTI_FTSR_TR2_Pos (2U)
3571#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
3572#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
3573#define EXTI_FTSR_TR3_Pos (3U)
3574#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
3575#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
3576#define EXTI_FTSR_TR4_Pos (4U)
3577#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
3578#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
3579#define EXTI_FTSR_TR5_Pos (5U)
3580#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
3581#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
3582#define EXTI_FTSR_TR6_Pos (6U)
3583#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
3584#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
3585#define EXTI_FTSR_TR7_Pos (7U)
3586#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
3587#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
3588#define EXTI_FTSR_TR8_Pos (8U)
3589#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
3590#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
3591#define EXTI_FTSR_TR9_Pos (9U)
3592#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
3593#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
3594#define EXTI_FTSR_TR10_Pos (10U)
3595#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
3596#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
3597#define EXTI_FTSR_TR11_Pos (11U)
3598#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
3599#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
3600#define EXTI_FTSR_TR12_Pos (12U)
3601#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
3602#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
3603#define EXTI_FTSR_TR13_Pos (13U)
3604#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
3605#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
3606#define EXTI_FTSR_TR14_Pos (14U)
3607#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
3608#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
3609#define EXTI_FTSR_TR15_Pos (15U)
3610#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
3611#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
3612#define EXTI_FTSR_TR16_Pos (16U)
3613#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
3614#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
3615#define EXTI_FTSR_TR17_Pos (17U)
3616#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
3617#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
3618#define EXTI_FTSR_TR18_Pos (18U)
3619#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
3620#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
3621#define EXTI_FTSR_TR19_Pos (19U)
3622#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
3623#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
3625/* References Defines */
3626#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
3627#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
3628#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
3629#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
3630#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
3631#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
3632#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
3633#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
3634#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
3635#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
3636#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
3637#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
3638#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
3639#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
3640#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
3641#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
3642#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
3643#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
3644#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
3645#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
3646
3647/****************** Bit definition for EXTI_SWIER register ******************/
3648#define EXTI_SWIER_SWIER0_Pos (0U)
3649#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
3650#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
3651#define EXTI_SWIER_SWIER1_Pos (1U)
3652#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
3653#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
3654#define EXTI_SWIER_SWIER2_Pos (2U)
3655#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
3656#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
3657#define EXTI_SWIER_SWIER3_Pos (3U)
3658#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
3659#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
3660#define EXTI_SWIER_SWIER4_Pos (4U)
3661#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
3662#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
3663#define EXTI_SWIER_SWIER5_Pos (5U)
3664#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
3665#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
3666#define EXTI_SWIER_SWIER6_Pos (6U)
3667#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
3668#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
3669#define EXTI_SWIER_SWIER7_Pos (7U)
3670#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
3671#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
3672#define EXTI_SWIER_SWIER8_Pos (8U)
3673#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
3674#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
3675#define EXTI_SWIER_SWIER9_Pos (9U)
3676#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
3677#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
3678#define EXTI_SWIER_SWIER10_Pos (10U)
3679#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
3680#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
3681#define EXTI_SWIER_SWIER11_Pos (11U)
3682#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
3683#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
3684#define EXTI_SWIER_SWIER12_Pos (12U)
3685#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
3686#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
3687#define EXTI_SWIER_SWIER13_Pos (13U)
3688#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
3689#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
3690#define EXTI_SWIER_SWIER14_Pos (14U)
3691#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
3692#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
3693#define EXTI_SWIER_SWIER15_Pos (15U)
3694#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
3695#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
3696#define EXTI_SWIER_SWIER16_Pos (16U)
3697#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
3698#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
3699#define EXTI_SWIER_SWIER17_Pos (17U)
3700#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
3701#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
3702#define EXTI_SWIER_SWIER18_Pos (18U)
3703#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
3704#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
3705#define EXTI_SWIER_SWIER19_Pos (19U)
3706#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
3707#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
3709/* References Defines */
3710#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
3711#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
3712#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
3713#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
3714#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
3715#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
3716#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
3717#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
3718#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
3719#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
3720#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
3721#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
3722#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
3723#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
3724#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
3725#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
3726#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
3727#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
3728#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
3729#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
3730
3731/******************* Bit definition for EXTI_PR register ********************/
3732#define EXTI_PR_PR0_Pos (0U)
3733#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
3734#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
3735#define EXTI_PR_PR1_Pos (1U)
3736#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
3737#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
3738#define EXTI_PR_PR2_Pos (2U)
3739#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
3740#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
3741#define EXTI_PR_PR3_Pos (3U)
3742#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
3743#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
3744#define EXTI_PR_PR4_Pos (4U)
3745#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
3746#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
3747#define EXTI_PR_PR5_Pos (5U)
3748#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
3749#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
3750#define EXTI_PR_PR6_Pos (6U)
3751#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
3752#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
3753#define EXTI_PR_PR7_Pos (7U)
3754#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
3755#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
3756#define EXTI_PR_PR8_Pos (8U)
3757#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
3758#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
3759#define EXTI_PR_PR9_Pos (9U)
3760#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
3761#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
3762#define EXTI_PR_PR10_Pos (10U)
3763#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
3764#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
3765#define EXTI_PR_PR11_Pos (11U)
3766#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
3767#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
3768#define EXTI_PR_PR12_Pos (12U)
3769#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
3770#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
3771#define EXTI_PR_PR13_Pos (13U)
3772#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
3773#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
3774#define EXTI_PR_PR14_Pos (14U)
3775#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
3776#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
3777#define EXTI_PR_PR15_Pos (15U)
3778#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
3779#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
3780#define EXTI_PR_PR16_Pos (16U)
3781#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
3782#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
3783#define EXTI_PR_PR17_Pos (17U)
3784#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
3785#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
3786#define EXTI_PR_PR18_Pos (18U)
3787#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
3788#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
3789#define EXTI_PR_PR19_Pos (19U)
3790#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
3791#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
3793/* References Defines */
3794#define EXTI_PR_PIF0 EXTI_PR_PR0
3795#define EXTI_PR_PIF1 EXTI_PR_PR1
3796#define EXTI_PR_PIF2 EXTI_PR_PR2
3797#define EXTI_PR_PIF3 EXTI_PR_PR3
3798#define EXTI_PR_PIF4 EXTI_PR_PR4
3799#define EXTI_PR_PIF5 EXTI_PR_PR5
3800#define EXTI_PR_PIF6 EXTI_PR_PR6
3801#define EXTI_PR_PIF7 EXTI_PR_PR7
3802#define EXTI_PR_PIF8 EXTI_PR_PR8
3803#define EXTI_PR_PIF9 EXTI_PR_PR9
3804#define EXTI_PR_PIF10 EXTI_PR_PR10
3805#define EXTI_PR_PIF11 EXTI_PR_PR11
3806#define EXTI_PR_PIF12 EXTI_PR_PR12
3807#define EXTI_PR_PIF13 EXTI_PR_PR13
3808#define EXTI_PR_PIF14 EXTI_PR_PR14
3809#define EXTI_PR_PIF15 EXTI_PR_PR15
3810#define EXTI_PR_PIF16 EXTI_PR_PR16
3811#define EXTI_PR_PIF17 EXTI_PR_PR17
3812#define EXTI_PR_PIF18 EXTI_PR_PR18
3813#define EXTI_PR_PIF19 EXTI_PR_PR19
3814
3815/******************************************************************************/
3816/* */
3817/* DMA Controller */
3818/* */
3819/******************************************************************************/
3820
3821/******************* Bit definition for DMA_ISR register ********************/
3822#define DMA_ISR_GIF1_Pos (0U)
3823#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)
3824#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk
3825#define DMA_ISR_TCIF1_Pos (1U)
3826#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)
3827#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk
3828#define DMA_ISR_HTIF1_Pos (2U)
3829#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)
3830#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk
3831#define DMA_ISR_TEIF1_Pos (3U)
3832#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)
3833#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk
3834#define DMA_ISR_GIF2_Pos (4U)
3835#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)
3836#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk
3837#define DMA_ISR_TCIF2_Pos (5U)
3838#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)
3839#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk
3840#define DMA_ISR_HTIF2_Pos (6U)
3841#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)
3842#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk
3843#define DMA_ISR_TEIF2_Pos (7U)
3844#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)
3845#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk
3846#define DMA_ISR_GIF3_Pos (8U)
3847#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)
3848#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk
3849#define DMA_ISR_TCIF3_Pos (9U)
3850#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)
3851#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk
3852#define DMA_ISR_HTIF3_Pos (10U)
3853#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)
3854#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk
3855#define DMA_ISR_TEIF3_Pos (11U)
3856#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)
3857#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk
3858#define DMA_ISR_GIF4_Pos (12U)
3859#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)
3860#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk
3861#define DMA_ISR_TCIF4_Pos (13U)
3862#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)
3863#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk
3864#define DMA_ISR_HTIF4_Pos (14U)
3865#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)
3866#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk
3867#define DMA_ISR_TEIF4_Pos (15U)
3868#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)
3869#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk
3870#define DMA_ISR_GIF5_Pos (16U)
3871#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)
3872#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk
3873#define DMA_ISR_TCIF5_Pos (17U)
3874#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)
3875#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk
3876#define DMA_ISR_HTIF5_Pos (18U)
3877#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)
3878#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk
3879#define DMA_ISR_TEIF5_Pos (19U)
3880#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)
3881#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk
3882#define DMA_ISR_GIF6_Pos (20U)
3883#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)
3884#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk
3885#define DMA_ISR_TCIF6_Pos (21U)
3886#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)
3887#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk
3888#define DMA_ISR_HTIF6_Pos (22U)
3889#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)
3890#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk
3891#define DMA_ISR_TEIF6_Pos (23U)
3892#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)
3893#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk
3894#define DMA_ISR_GIF7_Pos (24U)
3895#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)
3896#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk
3897#define DMA_ISR_TCIF7_Pos (25U)
3898#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)
3899#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk
3900#define DMA_ISR_HTIF7_Pos (26U)
3901#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)
3902#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk
3903#define DMA_ISR_TEIF7_Pos (27U)
3904#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)
3905#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk
3907/******************* Bit definition for DMA_IFCR register *******************/
3908#define DMA_IFCR_CGIF1_Pos (0U)
3909#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)
3910#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk
3911#define DMA_IFCR_CTCIF1_Pos (1U)
3912#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)
3913#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk
3914#define DMA_IFCR_CHTIF1_Pos (2U)
3915#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)
3916#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk
3917#define DMA_IFCR_CTEIF1_Pos (3U)
3918#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)
3919#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk
3920#define DMA_IFCR_CGIF2_Pos (4U)
3921#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)
3922#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk
3923#define DMA_IFCR_CTCIF2_Pos (5U)
3924#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)
3925#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk
3926#define DMA_IFCR_CHTIF2_Pos (6U)
3927#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)
3928#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk
3929#define DMA_IFCR_CTEIF2_Pos (7U)
3930#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)
3931#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk
3932#define DMA_IFCR_CGIF3_Pos (8U)
3933#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)
3934#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk
3935#define DMA_IFCR_CTCIF3_Pos (9U)
3936#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)
3937#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk
3938#define DMA_IFCR_CHTIF3_Pos (10U)
3939#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
3940#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk
3941#define DMA_IFCR_CTEIF3_Pos (11U)
3942#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
3943#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
3944#define DMA_IFCR_CGIF4_Pos (12U)
3945#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
3946#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
3947#define DMA_IFCR_CTCIF4_Pos (13U)
3948#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
3949#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
3950#define DMA_IFCR_CHTIF4_Pos (14U)
3951#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
3952#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk
3953#define DMA_IFCR_CTEIF4_Pos (15U)
3954#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)
3955#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk
3956#define DMA_IFCR_CGIF5_Pos (16U)
3957#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
3958#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
3959#define DMA_IFCR_CTCIF5_Pos (17U)
3960#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
3961#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
3962#define DMA_IFCR_CHTIF5_Pos (18U)
3963#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
3964#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
3965#define DMA_IFCR_CTEIF5_Pos (19U)
3966#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
3967#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
3968#define DMA_IFCR_CGIF6_Pos (20U)
3969#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)
3970#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk
3971#define DMA_IFCR_CTCIF6_Pos (21U)
3972#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)
3973#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk
3974#define DMA_IFCR_CHTIF6_Pos (22U)
3975#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)
3976#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk
3977#define DMA_IFCR_CTEIF6_Pos (23U)
3978#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)
3979#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk
3980#define DMA_IFCR_CGIF7_Pos (24U)
3981#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)
3982#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk
3983#define DMA_IFCR_CTCIF7_Pos (25U)
3984#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)
3985#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk
3986#define DMA_IFCR_CHTIF7_Pos (26U)
3987#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)
3988#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk
3989#define DMA_IFCR_CTEIF7_Pos (27U)
3990#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)
3991#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk
3993/******************* Bit definition for DMA_CCR register *******************/
3994#define DMA_CCR_EN_Pos (0U)
3995#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)
3996#define DMA_CCR_EN DMA_CCR_EN_Msk
3997#define DMA_CCR_TCIE_Pos (1U)
3998#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)
3999#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk
4000#define DMA_CCR_HTIE_Pos (2U)
4001#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)
4002#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk
4003#define DMA_CCR_TEIE_Pos (3U)
4004#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)
4005#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk
4006#define DMA_CCR_DIR_Pos (4U)
4007#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)
4008#define DMA_CCR_DIR DMA_CCR_DIR_Msk
4009#define DMA_CCR_CIRC_Pos (5U)
4010#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)
4011#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk
4012#define DMA_CCR_PINC_Pos (6U)
4013#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)
4014#define DMA_CCR_PINC DMA_CCR_PINC_Msk
4015#define DMA_CCR_MINC_Pos (7U)
4016#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)
4017#define DMA_CCR_MINC DMA_CCR_MINC_Msk
4019#define DMA_CCR_PSIZE_Pos (8U)
4020#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)
4021#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk
4022#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)
4023#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)
4025#define DMA_CCR_MSIZE_Pos (10U)
4026#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)
4027#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk
4028#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)
4029#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)
4031#define DMA_CCR_PL_Pos (12U)
4032#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)
4033#define DMA_CCR_PL DMA_CCR_PL_Msk
4034#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)
4035#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)
4037#define DMA_CCR_MEM2MEM_Pos (14U)
4038#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)
4039#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk
4041/****************** Bit definition for DMA_CNDTR register ******************/
4042#define DMA_CNDTR_NDT_Pos (0U)
4043#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)
4044#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk
4046/****************** Bit definition for DMA_CPAR register *******************/
4047#define DMA_CPAR_PA_Pos (0U)
4048#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)
4049#define DMA_CPAR_PA DMA_CPAR_PA_Msk
4051/****************** Bit definition for DMA_CMAR register *******************/
4052#define DMA_CMAR_MA_Pos (0U)
4053#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)
4054#define DMA_CMAR_MA DMA_CMAR_MA_Msk
4056/******************************************************************************/
4057/* */
4058/* Analog to Digital Converter (ADC) */
4059/* */
4060/******************************************************************************/
4061
4062/*
4063 * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
4064 */
4065#define ADC_MULTIMODE_SUPPORT
4067/******************** Bit definition for ADC_SR register ********************/
4068#define ADC_SR_AWD_Pos (0U)
4069#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
4070#define ADC_SR_AWD ADC_SR_AWD_Msk
4071#define ADC_SR_EOS_Pos (1U)
4072#define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos)
4073#define ADC_SR_EOS ADC_SR_EOS_Msk
4074#define ADC_SR_JEOS_Pos (2U)
4075#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos)
4076#define ADC_SR_JEOS ADC_SR_JEOS_Msk
4077#define ADC_SR_JSTRT_Pos (3U)
4078#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
4079#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
4080#define ADC_SR_STRT_Pos (4U)
4081#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
4082#define ADC_SR_STRT ADC_SR_STRT_Msk
4084/* Legacy defines */
4085#define ADC_SR_EOC (ADC_SR_EOS)
4086#define ADC_SR_JEOC (ADC_SR_JEOS)
4087
4088/******************* Bit definition for ADC_CR1 register ********************/
4089#define ADC_CR1_AWDCH_Pos (0U)
4090#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
4091#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
4092#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
4093#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
4094#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
4095#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
4096#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
4098#define ADC_CR1_EOSIE_Pos (5U)
4099#define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos)
4100#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk
4101#define ADC_CR1_AWDIE_Pos (6U)
4102#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
4103#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
4104#define ADC_CR1_JEOSIE_Pos (7U)
4105#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos)
4106#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk
4107#define ADC_CR1_SCAN_Pos (8U)
4108#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
4109#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
4110#define ADC_CR1_AWDSGL_Pos (9U)
4111#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
4112#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
4113#define ADC_CR1_JAUTO_Pos (10U)
4114#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
4115#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
4116#define ADC_CR1_DISCEN_Pos (11U)
4117#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
4118#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
4119#define ADC_CR1_JDISCEN_Pos (12U)
4120#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
4121#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
4123#define ADC_CR1_DISCNUM_Pos (13U)
4124#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
4125#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
4126#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
4127#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
4128#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
4130#define ADC_CR1_DUALMOD_Pos (16U)
4131#define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos)
4132#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk
4133#define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos)
4134#define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos)
4135#define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos)
4136#define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos)
4138#define ADC_CR1_JAWDEN_Pos (22U)
4139#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
4140#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
4141#define ADC_CR1_AWDEN_Pos (23U)
4142#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
4143#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
4145/* Legacy defines */
4146#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
4147#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
4148
4149/******************* Bit definition for ADC_CR2 register ********************/
4150#define ADC_CR2_ADON_Pos (0U)
4151#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
4152#define ADC_CR2_ADON ADC_CR2_ADON_Msk
4153#define ADC_CR2_CONT_Pos (1U)
4154#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
4155#define ADC_CR2_CONT ADC_CR2_CONT_Msk
4156#define ADC_CR2_CAL_Pos (2U)
4157#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos)
4158#define ADC_CR2_CAL ADC_CR2_CAL_Msk
4159#define ADC_CR2_RSTCAL_Pos (3U)
4160#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos)
4161#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk
4162#define ADC_CR2_DMA_Pos (8U)
4163#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
4164#define ADC_CR2_DMA ADC_CR2_DMA_Msk
4165#define ADC_CR2_ALIGN_Pos (11U)
4166#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
4167#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
4169#define ADC_CR2_JEXTSEL_Pos (12U)
4170#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos)
4171#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
4172#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
4173#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
4174#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
4176#define ADC_CR2_JEXTTRIG_Pos (15U)
4177#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos)
4178#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk
4180#define ADC_CR2_EXTSEL_Pos (17U)
4181#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos)
4182#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
4183#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
4184#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
4185#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
4187#define ADC_CR2_EXTTRIG_Pos (20U)
4188#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos)
4189#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk
4190#define ADC_CR2_JSWSTART_Pos (21U)
4191#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
4192#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
4193#define ADC_CR2_SWSTART_Pos (22U)
4194#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
4195#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
4196#define ADC_CR2_TSVREFE_Pos (23U)
4197#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos)
4198#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk
4200/****************** Bit definition for ADC_SMPR1 register *******************/
4201#define ADC_SMPR1_SMP10_Pos (0U)
4202#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
4203#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
4204#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
4205#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
4206#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
4208#define ADC_SMPR1_SMP11_Pos (3U)
4209#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
4210#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
4211#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
4212#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
4213#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
4215#define ADC_SMPR1_SMP12_Pos (6U)
4216#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
4217#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
4218#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
4219#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
4220#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
4222#define ADC_SMPR1_SMP13_Pos (9U)
4223#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
4224#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
4225#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
4226#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
4227#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
4229#define ADC_SMPR1_SMP14_Pos (12U)
4230#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
4231#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
4232#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
4233#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
4234#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
4236#define ADC_SMPR1_SMP15_Pos (15U)
4237#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
4238#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
4239#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
4240#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
4241#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
4243#define ADC_SMPR1_SMP16_Pos (18U)
4244#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
4245#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
4246#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
4247#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
4248#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
4250#define ADC_SMPR1_SMP17_Pos (21U)
4251#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
4252#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
4253#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
4254#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
4255#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
4257/****************** Bit definition for ADC_SMPR2 register *******************/
4258#define ADC_SMPR2_SMP0_Pos (0U)
4259#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
4260#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
4261#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
4262#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
4263#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
4265#define ADC_SMPR2_SMP1_Pos (3U)
4266#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
4267#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
4268#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
4269#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
4270#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
4272#define ADC_SMPR2_SMP2_Pos (6U)
4273#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
4274#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
4275#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
4276#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
4277#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
4279#define ADC_SMPR2_SMP3_Pos (9U)
4280#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
4281#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
4282#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
4283#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
4284#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
4286#define ADC_SMPR2_SMP4_Pos (12U)
4287#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
4288#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
4289#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
4290#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
4291#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
4293#define ADC_SMPR2_SMP5_Pos (15U)
4294#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
4295#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
4296#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
4297#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
4298#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
4300#define ADC_SMPR2_SMP6_Pos (18U)
4301#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
4302#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
4303#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
4304#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
4305#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
4307#define ADC_SMPR2_SMP7_Pos (21U)
4308#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
4309#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
4310#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
4311#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
4312#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
4314#define ADC_SMPR2_SMP8_Pos (24U)
4315#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
4316#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
4317#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
4318#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
4319#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
4321#define ADC_SMPR2_SMP9_Pos (27U)
4322#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
4323#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
4324#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
4325#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
4326#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
4328/****************** Bit definition for ADC_JOFR1 register *******************/
4329#define ADC_JOFR1_JOFFSET1_Pos (0U)
4330#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
4331#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
4333/****************** Bit definition for ADC_JOFR2 register *******************/
4334#define ADC_JOFR2_JOFFSET2_Pos (0U)
4335#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
4336#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
4338/****************** Bit definition for ADC_JOFR3 register *******************/
4339#define ADC_JOFR3_JOFFSET3_Pos (0U)
4340#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
4341#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
4343/****************** Bit definition for ADC_JOFR4 register *******************/
4344#define ADC_JOFR4_JOFFSET4_Pos (0U)
4345#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
4346#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
4348/******************* Bit definition for ADC_HTR register ********************/
4349#define ADC_HTR_HT_Pos (0U)
4350#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
4351#define ADC_HTR_HT ADC_HTR_HT_Msk
4353/******************* Bit definition for ADC_LTR register ********************/
4354#define ADC_LTR_LT_Pos (0U)
4355#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
4356#define ADC_LTR_LT ADC_LTR_LT_Msk
4358/******************* Bit definition for ADC_SQR1 register *******************/
4359#define ADC_SQR1_SQ13_Pos (0U)
4360#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
4361#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
4362#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
4363#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
4364#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
4365#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
4366#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
4368#define ADC_SQR1_SQ14_Pos (5U)
4369#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
4370#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
4371#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
4372#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
4373#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
4374#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
4375#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
4377#define ADC_SQR1_SQ15_Pos (10U)
4378#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
4379#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
4380#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
4381#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
4382#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
4383#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
4384#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
4386#define ADC_SQR1_SQ16_Pos (15U)
4387#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
4388#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
4389#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
4390#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
4391#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
4392#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
4393#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
4395#define ADC_SQR1_L_Pos (20U)
4396#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
4397#define ADC_SQR1_L ADC_SQR1_L_Msk
4398#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
4399#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
4400#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
4401#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
4403/******************* Bit definition for ADC_SQR2 register *******************/
4404#define ADC_SQR2_SQ7_Pos (0U)
4405#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
4406#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
4407#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
4408#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
4409#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
4410#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
4411#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
4413#define ADC_SQR2_SQ8_Pos (5U)
4414#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
4415#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
4416#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
4417#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
4418#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
4419#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
4420#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
4422#define ADC_SQR2_SQ9_Pos (10U)
4423#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
4424#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
4425#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
4426#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
4427#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
4428#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
4429#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
4431#define ADC_SQR2_SQ10_Pos (15U)
4432#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
4433#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
4434#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
4435#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
4436#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
4437#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
4438#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
4440#define ADC_SQR2_SQ11_Pos (20U)
4441#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
4442#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
4443#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
4444#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
4445#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
4446#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
4447#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
4449#define ADC_SQR2_SQ12_Pos (25U)
4450#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
4451#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
4452#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
4453#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
4454#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
4455#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
4456#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
4458/******************* Bit definition for ADC_SQR3 register *******************/
4459#define ADC_SQR3_SQ1_Pos (0U)
4460#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
4461#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
4462#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
4463#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
4464#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
4465#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
4466#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
4468#define ADC_SQR3_SQ2_Pos (5U)
4469#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
4470#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
4471#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
4472#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
4473#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
4474#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
4475#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
4477#define ADC_SQR3_SQ3_Pos (10U)
4478#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
4479#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
4480#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
4481#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
4482#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
4483#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
4484#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
4486#define ADC_SQR3_SQ4_Pos (15U)
4487#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
4488#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
4489#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
4490#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
4491#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
4492#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
4493#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
4495#define ADC_SQR3_SQ5_Pos (20U)
4496#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
4497#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
4498#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
4499#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
4500#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
4501#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
4502#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
4504#define ADC_SQR3_SQ6_Pos (25U)
4505#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
4506#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
4507#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
4508#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
4509#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
4510#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
4511#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
4513/******************* Bit definition for ADC_JSQR register *******************/
4514#define ADC_JSQR_JSQ1_Pos (0U)
4515#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
4516#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
4517#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
4518#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
4519#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
4520#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
4521#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
4523#define ADC_JSQR_JSQ2_Pos (5U)
4524#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
4525#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
4526#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
4527#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
4528#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
4529#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
4530#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
4532#define ADC_JSQR_JSQ3_Pos (10U)
4533#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
4534#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
4535#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
4536#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
4537#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
4538#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
4539#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
4541#define ADC_JSQR_JSQ4_Pos (15U)
4542#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
4543#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
4544#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
4545#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
4546#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
4547#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
4548#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
4550#define ADC_JSQR_JL_Pos (20U)
4551#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
4552#define ADC_JSQR_JL ADC_JSQR_JL_Msk
4553#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
4554#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
4556/******************* Bit definition for ADC_JDR1 register *******************/
4557#define ADC_JDR1_JDATA_Pos (0U)
4558#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
4559#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
4561/******************* Bit definition for ADC_JDR2 register *******************/
4562#define ADC_JDR2_JDATA_Pos (0U)
4563#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
4564#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
4566/******************* Bit definition for ADC_JDR3 register *******************/
4567#define ADC_JDR3_JDATA_Pos (0U)
4568#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
4569#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
4571/******************* Bit definition for ADC_JDR4 register *******************/
4572#define ADC_JDR4_JDATA_Pos (0U)
4573#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
4574#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
4576/******************** Bit definition for ADC_DR register ********************/
4577#define ADC_DR_DATA_Pos (0U)
4578#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
4579#define ADC_DR_DATA ADC_DR_DATA_Msk
4580#define ADC_DR_ADC2DATA_Pos (16U)
4581#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
4582#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
4583/******************************************************************************/
4584/* */
4585/* Digital to Analog Converter */
4586/* */
4587/******************************************************************************/
4588
4589/******************** Bit definition for DAC_CR register ********************/
4590#define DAC_CR_EN1_Pos (0U)
4591#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
4592#define DAC_CR_EN1 DAC_CR_EN1_Msk
4593#define DAC_CR_BOFF1_Pos (1U)
4594#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
4595#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
4596#define DAC_CR_TEN1_Pos (2U)
4597#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
4598#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
4600#define DAC_CR_TSEL1_Pos (3U)
4601#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
4602#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
4603#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
4604#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
4605#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
4607#define DAC_CR_WAVE1_Pos (6U)
4608#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
4609#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
4610#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
4611#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
4613#define DAC_CR_MAMP1_Pos (8U)
4614#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
4615#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
4616#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
4617#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
4618#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
4619#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
4621#define DAC_CR_DMAEN1_Pos (12U)
4622#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
4623#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
4624#define DAC_CR_EN2_Pos (16U)
4625#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
4626#define DAC_CR_EN2 DAC_CR_EN2_Msk
4627#define DAC_CR_BOFF2_Pos (17U)
4628#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
4629#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
4630#define DAC_CR_TEN2_Pos (18U)
4631#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
4632#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
4634#define DAC_CR_TSEL2_Pos (19U)
4635#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
4636#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
4637#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
4638#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
4639#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
4641#define DAC_CR_WAVE2_Pos (22U)
4642#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
4643#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
4644#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
4645#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
4647#define DAC_CR_MAMP2_Pos (24U)
4648#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
4649#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
4650#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
4651#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
4652#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
4653#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
4655#define DAC_CR_DMAEN2_Pos (28U)
4656#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
4657#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
4660/***************** Bit definition for DAC_SWTRIGR register ******************/
4661#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
4662#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
4663#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
4664#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
4665#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
4666#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
4668/***************** Bit definition for DAC_DHR12R1 register ******************/
4669#define DAC_DHR12R1_DACC1DHR_Pos (0U)
4670#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
4671#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
4673/***************** Bit definition for DAC_DHR12L1 register ******************/
4674#define DAC_DHR12L1_DACC1DHR_Pos (4U)
4675#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
4676#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
4678/****************** Bit definition for DAC_DHR8R1 register ******************/
4679#define DAC_DHR8R1_DACC1DHR_Pos (0U)
4680#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
4681#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
4683/***************** Bit definition for DAC_DHR12R2 register ******************/
4684#define DAC_DHR12R2_DACC2DHR_Pos (0U)
4685#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
4686#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
4688/***************** Bit definition for DAC_DHR12L2 register ******************/
4689#define DAC_DHR12L2_DACC2DHR_Pos (4U)
4690#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
4691#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
4693/****************** Bit definition for DAC_DHR8R2 register ******************/
4694#define DAC_DHR8R2_DACC2DHR_Pos (0U)
4695#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
4696#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
4698/***************** Bit definition for DAC_DHR12RD register ******************/
4699#define DAC_DHR12RD_DACC1DHR_Pos (0U)
4700#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
4701#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
4702#define DAC_DHR12RD_DACC2DHR_Pos (16U)
4703#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
4704#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
4706/***************** Bit definition for DAC_DHR12LD register ******************/
4707#define DAC_DHR12LD_DACC1DHR_Pos (4U)
4708#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
4709#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
4710#define DAC_DHR12LD_DACC2DHR_Pos (20U)
4711#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
4712#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
4714/****************** Bit definition for DAC_DHR8RD register ******************/
4715#define DAC_DHR8RD_DACC1DHR_Pos (0U)
4716#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
4717#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
4718#define DAC_DHR8RD_DACC2DHR_Pos (8U)
4719#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
4720#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
4722/******************* Bit definition for DAC_DOR1 register *******************/
4723#define DAC_DOR1_DACC1DOR_Pos (0U)
4724#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
4725#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
4727/******************* Bit definition for DAC_DOR2 register *******************/
4728#define DAC_DOR2_DACC2DOR_Pos (0U)
4729#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
4730#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
4734/*****************************************************************************/
4735/* */
4736/* Timers (TIM) */
4737/* */
4738/*****************************************************************************/
4739/******************* Bit definition for TIM_CR1 register *******************/
4740#define TIM_CR1_CEN_Pos (0U)
4741#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
4742#define TIM_CR1_CEN TIM_CR1_CEN_Msk
4743#define TIM_CR1_UDIS_Pos (1U)
4744#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
4745#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
4746#define TIM_CR1_URS_Pos (2U)
4747#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
4748#define TIM_CR1_URS TIM_CR1_URS_Msk
4749#define TIM_CR1_OPM_Pos (3U)
4750#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
4751#define TIM_CR1_OPM TIM_CR1_OPM_Msk
4752#define TIM_CR1_DIR_Pos (4U)
4753#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
4754#define TIM_CR1_DIR TIM_CR1_DIR_Msk
4756#define TIM_CR1_CMS_Pos (5U)
4757#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
4758#define TIM_CR1_CMS TIM_CR1_CMS_Msk
4759#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
4760#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
4762#define TIM_CR1_ARPE_Pos (7U)
4763#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
4764#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
4766#define TIM_CR1_CKD_Pos (8U)
4767#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
4768#define TIM_CR1_CKD TIM_CR1_CKD_Msk
4769#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
4770#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
4772/******************* Bit definition for TIM_CR2 register *******************/
4773#define TIM_CR2_CCPC_Pos (0U)
4774#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
4775#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
4776#define TIM_CR2_CCUS_Pos (2U)
4777#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
4778#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
4779#define TIM_CR2_CCDS_Pos (3U)
4780#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
4781#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
4783#define TIM_CR2_MMS_Pos (4U)
4784#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
4785#define TIM_CR2_MMS TIM_CR2_MMS_Msk
4786#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
4787#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
4788#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
4790#define TIM_CR2_TI1S_Pos (7U)
4791#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
4792#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
4793#define TIM_CR2_OIS1_Pos (8U)
4794#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
4795#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
4796#define TIM_CR2_OIS1N_Pos (9U)
4797#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
4798#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
4799#define TIM_CR2_OIS2_Pos (10U)
4800#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
4801#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
4802#define TIM_CR2_OIS2N_Pos (11U)
4803#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
4804#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
4805#define TIM_CR2_OIS3_Pos (12U)
4806#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
4807#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
4808#define TIM_CR2_OIS3N_Pos (13U)
4809#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
4810#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
4811#define TIM_CR2_OIS4_Pos (14U)
4812#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
4813#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
4815/******************* Bit definition for TIM_SMCR register ******************/
4816#define TIM_SMCR_SMS_Pos (0U)
4817#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
4818#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
4819#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
4820#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
4821#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
4823#define TIM_SMCR_TS_Pos (4U)
4824#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
4825#define TIM_SMCR_TS TIM_SMCR_TS_Msk
4826#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
4827#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
4828#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
4830#define TIM_SMCR_MSM_Pos (7U)
4831#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
4832#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
4834#define TIM_SMCR_ETF_Pos (8U)
4835#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
4836#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
4837#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
4838#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
4839#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
4840#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
4842#define TIM_SMCR_ETPS_Pos (12U)
4843#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
4844#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
4845#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
4846#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
4848#define TIM_SMCR_ECE_Pos (14U)
4849#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
4850#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
4851#define TIM_SMCR_ETP_Pos (15U)
4852#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
4853#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
4855/******************* Bit definition for TIM_DIER register ******************/
4856#define TIM_DIER_UIE_Pos (0U)
4857#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
4858#define TIM_DIER_UIE TIM_DIER_UIE_Msk
4859#define TIM_DIER_CC1IE_Pos (1U)
4860#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
4861#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
4862#define TIM_DIER_CC2IE_Pos (2U)
4863#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
4864#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
4865#define TIM_DIER_CC3IE_Pos (3U)
4866#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
4867#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
4868#define TIM_DIER_CC4IE_Pos (4U)
4869#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
4870#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
4871#define TIM_DIER_COMIE_Pos (5U)
4872#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
4873#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
4874#define TIM_DIER_TIE_Pos (6U)
4875#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
4876#define TIM_DIER_TIE TIM_DIER_TIE_Msk
4877#define TIM_DIER_BIE_Pos (7U)
4878#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
4879#define TIM_DIER_BIE TIM_DIER_BIE_Msk
4880#define TIM_DIER_UDE_Pos (8U)
4881#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
4882#define TIM_DIER_UDE TIM_DIER_UDE_Msk
4883#define TIM_DIER_CC1DE_Pos (9U)
4884#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
4885#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
4886#define TIM_DIER_CC2DE_Pos (10U)
4887#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
4888#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
4889#define TIM_DIER_CC3DE_Pos (11U)
4890#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
4891#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
4892#define TIM_DIER_CC4DE_Pos (12U)
4893#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
4894#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
4895#define TIM_DIER_COMDE_Pos (13U)
4896#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
4897#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
4898#define TIM_DIER_TDE_Pos (14U)
4899#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
4900#define TIM_DIER_TDE TIM_DIER_TDE_Msk
4902/******************** Bit definition for TIM_SR register *******************/
4903#define TIM_SR_UIF_Pos (0U)
4904#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
4905#define TIM_SR_UIF TIM_SR_UIF_Msk
4906#define TIM_SR_CC1IF_Pos (1U)
4907#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
4908#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
4909#define TIM_SR_CC2IF_Pos (2U)
4910#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
4911#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
4912#define TIM_SR_CC3IF_Pos (3U)
4913#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
4914#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
4915#define TIM_SR_CC4IF_Pos (4U)
4916#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
4917#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
4918#define TIM_SR_COMIF_Pos (5U)
4919#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
4920#define TIM_SR_COMIF TIM_SR_COMIF_Msk
4921#define TIM_SR_TIF_Pos (6U)
4922#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
4923#define TIM_SR_TIF TIM_SR_TIF_Msk
4924#define TIM_SR_BIF_Pos (7U)
4925#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
4926#define TIM_SR_BIF TIM_SR_BIF_Msk
4927#define TIM_SR_CC1OF_Pos (9U)
4928#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
4929#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
4930#define TIM_SR_CC2OF_Pos (10U)
4931#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
4932#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
4933#define TIM_SR_CC3OF_Pos (11U)
4934#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
4935#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
4936#define TIM_SR_CC4OF_Pos (12U)
4937#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
4938#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
4940/******************* Bit definition for TIM_EGR register *******************/
4941#define TIM_EGR_UG_Pos (0U)
4942#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
4943#define TIM_EGR_UG TIM_EGR_UG_Msk
4944#define TIM_EGR_CC1G_Pos (1U)
4945#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
4946#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
4947#define TIM_EGR_CC2G_Pos (2U)
4948#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
4949#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
4950#define TIM_EGR_CC3G_Pos (3U)
4951#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
4952#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
4953#define TIM_EGR_CC4G_Pos (4U)
4954#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
4955#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
4956#define TIM_EGR_COMG_Pos (5U)
4957#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
4958#define TIM_EGR_COMG TIM_EGR_COMG_Msk
4959#define TIM_EGR_TG_Pos (6U)
4960#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
4961#define TIM_EGR_TG TIM_EGR_TG_Msk
4962#define TIM_EGR_BG_Pos (7U)
4963#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
4964#define TIM_EGR_BG TIM_EGR_BG_Msk
4966/****************** Bit definition for TIM_CCMR1 register ******************/
4967#define TIM_CCMR1_CC1S_Pos (0U)
4968#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
4969#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
4970#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
4971#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
4973#define TIM_CCMR1_OC1FE_Pos (2U)
4974#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
4975#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
4976#define TIM_CCMR1_OC1PE_Pos (3U)
4977#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
4978#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
4980#define TIM_CCMR1_OC1M_Pos (4U)
4981#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
4982#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
4983#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
4984#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
4985#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
4987#define TIM_CCMR1_OC1CE_Pos (7U)
4988#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
4989#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
4991#define TIM_CCMR1_CC2S_Pos (8U)
4992#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
4993#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
4994#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
4995#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
4997#define TIM_CCMR1_OC2FE_Pos (10U)
4998#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
4999#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
5000#define TIM_CCMR1_OC2PE_Pos (11U)
5001#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
5002#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
5004#define TIM_CCMR1_OC2M_Pos (12U)
5005#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
5006#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
5007#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
5008#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
5009#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
5011#define TIM_CCMR1_OC2CE_Pos (15U)
5012#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
5013#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
5015/*---------------------------------------------------------------------------*/
5016
5017#define TIM_CCMR1_IC1PSC_Pos (2U)
5018#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
5019#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
5020#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
5021#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
5023#define TIM_CCMR1_IC1F_Pos (4U)
5024#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
5025#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
5026#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
5027#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
5028#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
5029#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
5031#define TIM_CCMR1_IC2PSC_Pos (10U)
5032#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
5033#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
5034#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
5035#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
5037#define TIM_CCMR1_IC2F_Pos (12U)
5038#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
5039#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
5040#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
5041#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
5042#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
5043#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
5045/****************** Bit definition for TIM_CCMR2 register ******************/
5046#define TIM_CCMR2_CC3S_Pos (0U)
5047#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
5048#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
5049#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
5050#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
5052#define TIM_CCMR2_OC3FE_Pos (2U)
5053#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
5054#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
5055#define TIM_CCMR2_OC3PE_Pos (3U)
5056#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
5057#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
5059#define TIM_CCMR2_OC3M_Pos (4U)
5060#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
5061#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
5062#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
5063#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
5064#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
5066#define TIM_CCMR2_OC3CE_Pos (7U)
5067#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
5068#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
5070#define TIM_CCMR2_CC4S_Pos (8U)
5071#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
5072#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
5073#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
5074#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
5076#define TIM_CCMR2_OC4FE_Pos (10U)
5077#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
5078#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
5079#define TIM_CCMR2_OC4PE_Pos (11U)
5080#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
5081#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
5083#define TIM_CCMR2_OC4M_Pos (12U)
5084#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
5085#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
5086#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
5087#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
5088#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
5090#define TIM_CCMR2_OC4CE_Pos (15U)
5091#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
5092#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
5094/*---------------------------------------------------------------------------*/
5095
5096#define TIM_CCMR2_IC3PSC_Pos (2U)
5097#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
5098#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
5099#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
5100#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
5102#define TIM_CCMR2_IC3F_Pos (4U)
5103#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
5104#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
5105#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
5106#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
5107#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
5108#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
5110#define TIM_CCMR2_IC4PSC_Pos (10U)
5111#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
5112#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
5113#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
5114#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
5116#define TIM_CCMR2_IC4F_Pos (12U)
5117#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
5118#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
5119#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
5120#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
5121#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
5122#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
5124/******************* Bit definition for TIM_CCER register ******************/
5125#define TIM_CCER_CC1E_Pos (0U)
5126#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
5127#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
5128#define TIM_CCER_CC1P_Pos (1U)
5129#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
5130#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
5131#define TIM_CCER_CC1NE_Pos (2U)
5132#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
5133#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
5134#define TIM_CCER_CC1NP_Pos (3U)
5135#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
5136#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
5137#define TIM_CCER_CC2E_Pos (4U)
5138#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
5139#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
5140#define TIM_CCER_CC2P_Pos (5U)
5141#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
5142#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
5143#define TIM_CCER_CC2NE_Pos (6U)
5144#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
5145#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
5146#define TIM_CCER_CC2NP_Pos (7U)
5147#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
5148#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
5149#define TIM_CCER_CC3E_Pos (8U)
5150#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
5151#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
5152#define TIM_CCER_CC3P_Pos (9U)
5153#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
5154#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
5155#define TIM_CCER_CC3NE_Pos (10U)
5156#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
5157#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
5158#define TIM_CCER_CC3NP_Pos (11U)
5159#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
5160#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
5161#define TIM_CCER_CC4E_Pos (12U)
5162#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
5163#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
5164#define TIM_CCER_CC4P_Pos (13U)
5165#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
5166#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
5168/******************* Bit definition for TIM_CNT register *******************/
5169#define TIM_CNT_CNT_Pos (0U)
5170#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
5171#define TIM_CNT_CNT TIM_CNT_CNT_Msk
5173/******************* Bit definition for TIM_PSC register *******************/
5174#define TIM_PSC_PSC_Pos (0U)
5175#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
5176#define TIM_PSC_PSC TIM_PSC_PSC_Msk
5178/******************* Bit definition for TIM_ARR register *******************/
5179#define TIM_ARR_ARR_Pos (0U)
5180#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
5181#define TIM_ARR_ARR TIM_ARR_ARR_Msk
5183/******************* Bit definition for TIM_RCR register *******************/
5184#define TIM_RCR_REP_Pos (0U)
5185#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
5186#define TIM_RCR_REP TIM_RCR_REP_Msk
5188/******************* Bit definition for TIM_CCR1 register ******************/
5189#define TIM_CCR1_CCR1_Pos (0U)
5190#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
5191#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
5193/******************* Bit definition for TIM_CCR2 register ******************/
5194#define TIM_CCR2_CCR2_Pos (0U)
5195#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
5196#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
5198/******************* Bit definition for TIM_CCR3 register ******************/
5199#define TIM_CCR3_CCR3_Pos (0U)
5200#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
5201#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
5203/******************* Bit definition for TIM_CCR4 register ******************/
5204#define TIM_CCR4_CCR4_Pos (0U)
5205#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
5206#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
5208/******************* Bit definition for TIM_BDTR register ******************/
5209#define TIM_BDTR_DTG_Pos (0U)
5210#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
5211#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
5212#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
5213#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
5214#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
5215#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
5216#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
5217#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
5218#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
5219#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
5221#define TIM_BDTR_LOCK_Pos (8U)
5222#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
5223#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
5224#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
5225#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
5227#define TIM_BDTR_OSSI_Pos (10U)
5228#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
5229#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
5230#define TIM_BDTR_OSSR_Pos (11U)
5231#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
5232#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
5233#define TIM_BDTR_BKE_Pos (12U)
5234#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
5235#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
5236#define TIM_BDTR_BKP_Pos (13U)
5237#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
5238#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
5239#define TIM_BDTR_AOE_Pos (14U)
5240#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
5241#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
5242#define TIM_BDTR_MOE_Pos (15U)
5243#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
5244#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
5246/******************* Bit definition for TIM_DCR register *******************/
5247#define TIM_DCR_DBA_Pos (0U)
5248#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
5249#define TIM_DCR_DBA TIM_DCR_DBA_Msk
5250#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
5251#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
5252#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
5253#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
5254#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
5256#define TIM_DCR_DBL_Pos (8U)
5257#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
5258#define TIM_DCR_DBL TIM_DCR_DBL_Msk
5259#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
5260#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
5261#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
5262#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
5263#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
5265/******************* Bit definition for TIM_DMAR register ******************/
5266#define TIM_DMAR_DMAB_Pos (0U)
5267#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
5268#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
5270/******************************************************************************/
5271/* */
5272/* Real-Time Clock */
5273/* */
5274/******************************************************************************/
5275
5276/******************* Bit definition for RTC_CRH register ********************/
5277#define RTC_CRH_SECIE_Pos (0U)
5278#define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos)
5279#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk
5280#define RTC_CRH_ALRIE_Pos (1U)
5281#define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos)
5282#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk
5283#define RTC_CRH_OWIE_Pos (2U)
5284#define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos)
5285#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk
5287/******************* Bit definition for RTC_CRL register ********************/
5288#define RTC_CRL_SECF_Pos (0U)
5289#define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos)
5290#define RTC_CRL_SECF RTC_CRL_SECF_Msk
5291#define RTC_CRL_ALRF_Pos (1U)
5292#define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos)
5293#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk
5294#define RTC_CRL_OWF_Pos (2U)
5295#define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos)
5296#define RTC_CRL_OWF RTC_CRL_OWF_Msk
5297#define RTC_CRL_RSF_Pos (3U)
5298#define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos)
5299#define RTC_CRL_RSF RTC_CRL_RSF_Msk
5300#define RTC_CRL_CNF_Pos (4U)
5301#define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos)
5302#define RTC_CRL_CNF RTC_CRL_CNF_Msk
5303#define RTC_CRL_RTOFF_Pos (5U)
5304#define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos)
5305#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk
5307/******************* Bit definition for RTC_PRLH register *******************/
5308#define RTC_PRLH_PRL_Pos (0U)
5309#define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos)
5310#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk
5312/******************* Bit definition for RTC_PRLL register *******************/
5313#define RTC_PRLL_PRL_Pos (0U)
5314#define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos)
5315#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk
5317/******************* Bit definition for RTC_DIVH register *******************/
5318#define RTC_DIVH_RTC_DIV_Pos (0U)
5319#define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos)
5320#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk
5322/******************* Bit definition for RTC_DIVL register *******************/
5323#define RTC_DIVL_RTC_DIV_Pos (0U)
5324#define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos)
5325#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk
5327/******************* Bit definition for RTC_CNTH register *******************/
5328#define RTC_CNTH_RTC_CNT_Pos (0U)
5329#define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos)
5330#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk
5332/******************* Bit definition for RTC_CNTL register *******************/
5333#define RTC_CNTL_RTC_CNT_Pos (0U)
5334#define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos)
5335#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk
5337/******************* Bit definition for RTC_ALRH register *******************/
5338#define RTC_ALRH_RTC_ALR_Pos (0U)
5339#define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos)
5340#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk
5342/******************* Bit definition for RTC_ALRL register *******************/
5343#define RTC_ALRL_RTC_ALR_Pos (0U)
5344#define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos)
5345#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk
5347/******************************************************************************/
5348/* */
5349/* Independent WATCHDOG (IWDG) */
5350/* */
5351/******************************************************************************/
5352
5353/******************* Bit definition for IWDG_KR register ********************/
5354#define IWDG_KR_KEY_Pos (0U)
5355#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
5356#define IWDG_KR_KEY IWDG_KR_KEY_Msk
5358/******************* Bit definition for IWDG_PR register ********************/
5359#define IWDG_PR_PR_Pos (0U)
5360#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
5361#define IWDG_PR_PR IWDG_PR_PR_Msk
5362#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
5363#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
5364#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
5366/******************* Bit definition for IWDG_RLR register *******************/
5367#define IWDG_RLR_RL_Pos (0U)
5368#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
5369#define IWDG_RLR_RL IWDG_RLR_RL_Msk
5371/******************* Bit definition for IWDG_SR register ********************/
5372#define IWDG_SR_PVU_Pos (0U)
5373#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
5374#define IWDG_SR_PVU IWDG_SR_PVU_Msk
5375#define IWDG_SR_RVU_Pos (1U)
5376#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
5377#define IWDG_SR_RVU IWDG_SR_RVU_Msk
5379/******************************************************************************/
5380/* */
5381/* Window WATCHDOG (WWDG) */
5382/* */
5383/******************************************************************************/
5384
5385/******************* Bit definition for WWDG_CR register ********************/
5386#define WWDG_CR_T_Pos (0U)
5387#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
5388#define WWDG_CR_T WWDG_CR_T_Msk
5389#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
5390#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
5391#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
5392#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
5393#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
5394#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
5395#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
5397/* Legacy defines */
5398#define WWDG_CR_T0 WWDG_CR_T_0
5399#define WWDG_CR_T1 WWDG_CR_T_1
5400#define WWDG_CR_T2 WWDG_CR_T_2
5401#define WWDG_CR_T3 WWDG_CR_T_3
5402#define WWDG_CR_T4 WWDG_CR_T_4
5403#define WWDG_CR_T5 WWDG_CR_T_5
5404#define WWDG_CR_T6 WWDG_CR_T_6
5405
5406#define WWDG_CR_WDGA_Pos (7U)
5407#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
5408#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
5410/******************* Bit definition for WWDG_CFR register *******************/
5411#define WWDG_CFR_W_Pos (0U)
5412#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
5413#define WWDG_CFR_W WWDG_CFR_W_Msk
5414#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
5415#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
5416#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
5417#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
5418#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
5419#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
5420#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
5422/* Legacy defines */
5423#define WWDG_CFR_W0 WWDG_CFR_W_0
5424#define WWDG_CFR_W1 WWDG_CFR_W_1
5425#define WWDG_CFR_W2 WWDG_CFR_W_2
5426#define WWDG_CFR_W3 WWDG_CFR_W_3
5427#define WWDG_CFR_W4 WWDG_CFR_W_4
5428#define WWDG_CFR_W5 WWDG_CFR_W_5
5429#define WWDG_CFR_W6 WWDG_CFR_W_6
5430
5431#define WWDG_CFR_WDGTB_Pos (7U)
5432#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
5433#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
5434#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
5435#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
5437/* Legacy defines */
5438#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
5439#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
5440
5441#define WWDG_CFR_EWI_Pos (9U)
5442#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
5443#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
5445/******************* Bit definition for WWDG_SR register ********************/
5446#define WWDG_SR_EWIF_Pos (0U)
5447#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
5448#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
5451/******************************************************************************/
5452/* */
5453/* Controller Area Network */
5454/* */
5455/******************************************************************************/
5456
5458/******************* Bit definition for CAN_MCR register ********************/
5459#define CAN_MCR_INRQ_Pos (0U)
5460#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
5461#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
5462#define CAN_MCR_SLEEP_Pos (1U)
5463#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
5464#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
5465#define CAN_MCR_TXFP_Pos (2U)
5466#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
5467#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
5468#define CAN_MCR_RFLM_Pos (3U)
5469#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
5470#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
5471#define CAN_MCR_NART_Pos (4U)
5472#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
5473#define CAN_MCR_NART CAN_MCR_NART_Msk
5474#define CAN_MCR_AWUM_Pos (5U)
5475#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
5476#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
5477#define CAN_MCR_ABOM_Pos (6U)
5478#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
5479#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
5480#define CAN_MCR_TTCM_Pos (7U)
5481#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
5482#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
5483#define CAN_MCR_RESET_Pos (15U)
5484#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
5485#define CAN_MCR_RESET CAN_MCR_RESET_Msk
5486#define CAN_MCR_DBF_Pos (16U)
5487#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
5488#define CAN_MCR_DBF CAN_MCR_DBF_Msk
5490/******************* Bit definition for CAN_MSR register ********************/
5491#define CAN_MSR_INAK_Pos (0U)
5492#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
5493#define CAN_MSR_INAK CAN_MSR_INAK_Msk
5494#define CAN_MSR_SLAK_Pos (1U)
5495#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
5496#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
5497#define CAN_MSR_ERRI_Pos (2U)
5498#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
5499#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
5500#define CAN_MSR_WKUI_Pos (3U)
5501#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
5502#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
5503#define CAN_MSR_SLAKI_Pos (4U)
5504#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
5505#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
5506#define CAN_MSR_TXM_Pos (8U)
5507#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
5508#define CAN_MSR_TXM CAN_MSR_TXM_Msk
5509#define CAN_MSR_RXM_Pos (9U)
5510#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
5511#define CAN_MSR_RXM CAN_MSR_RXM_Msk
5512#define CAN_MSR_SAMP_Pos (10U)
5513#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
5514#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
5515#define CAN_MSR_RX_Pos (11U)
5516#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
5517#define CAN_MSR_RX CAN_MSR_RX_Msk
5519/******************* Bit definition for CAN_TSR register ********************/
5520#define CAN_TSR_RQCP0_Pos (0U)
5521#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
5522#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
5523#define CAN_TSR_TXOK0_Pos (1U)
5524#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
5525#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
5526#define CAN_TSR_ALST0_Pos (2U)
5527#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
5528#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
5529#define CAN_TSR_TERR0_Pos (3U)
5530#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
5531#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
5532#define CAN_TSR_ABRQ0_Pos (7U)
5533#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
5534#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
5535#define CAN_TSR_RQCP1_Pos (8U)
5536#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
5537#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
5538#define CAN_TSR_TXOK1_Pos (9U)
5539#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
5540#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
5541#define CAN_TSR_ALST1_Pos (10U)
5542#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
5543#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
5544#define CAN_TSR_TERR1_Pos (11U)
5545#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
5546#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
5547#define CAN_TSR_ABRQ1_Pos (15U)
5548#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
5549#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
5550#define CAN_TSR_RQCP2_Pos (16U)
5551#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
5552#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
5553#define CAN_TSR_TXOK2_Pos (17U)
5554#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
5555#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
5556#define CAN_TSR_ALST2_Pos (18U)
5557#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
5558#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
5559#define CAN_TSR_TERR2_Pos (19U)
5560#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
5561#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
5562#define CAN_TSR_ABRQ2_Pos (23U)
5563#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
5564#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
5565#define CAN_TSR_CODE_Pos (24U)
5566#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
5567#define CAN_TSR_CODE CAN_TSR_CODE_Msk
5569#define CAN_TSR_TME_Pos (26U)
5570#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
5571#define CAN_TSR_TME CAN_TSR_TME_Msk
5572#define CAN_TSR_TME0_Pos (26U)
5573#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
5574#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
5575#define CAN_TSR_TME1_Pos (27U)
5576#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
5577#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
5578#define CAN_TSR_TME2_Pos (28U)
5579#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
5580#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
5582#define CAN_TSR_LOW_Pos (29U)
5583#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
5584#define CAN_TSR_LOW CAN_TSR_LOW_Msk
5585#define CAN_TSR_LOW0_Pos (29U)
5586#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
5587#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
5588#define CAN_TSR_LOW1_Pos (30U)
5589#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
5590#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
5591#define CAN_TSR_LOW2_Pos (31U)
5592#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
5593#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
5595/******************* Bit definition for CAN_RF0R register *******************/
5596#define CAN_RF0R_FMP0_Pos (0U)
5597#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
5598#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
5599#define CAN_RF0R_FULL0_Pos (3U)
5600#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
5601#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
5602#define CAN_RF0R_FOVR0_Pos (4U)
5603#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
5604#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
5605#define CAN_RF0R_RFOM0_Pos (5U)
5606#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
5607#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
5609/******************* Bit definition for CAN_RF1R register *******************/
5610#define CAN_RF1R_FMP1_Pos (0U)
5611#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
5612#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
5613#define CAN_RF1R_FULL1_Pos (3U)
5614#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
5615#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
5616#define CAN_RF1R_FOVR1_Pos (4U)
5617#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
5618#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
5619#define CAN_RF1R_RFOM1_Pos (5U)
5620#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
5621#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
5623/******************** Bit definition for CAN_IER register *******************/
5624#define CAN_IER_TMEIE_Pos (0U)
5625#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
5626#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
5627#define CAN_IER_FMPIE0_Pos (1U)
5628#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
5629#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
5630#define CAN_IER_FFIE0_Pos (2U)
5631#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
5632#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
5633#define CAN_IER_FOVIE0_Pos (3U)
5634#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
5635#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
5636#define CAN_IER_FMPIE1_Pos (4U)
5637#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
5638#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
5639#define CAN_IER_FFIE1_Pos (5U)
5640#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
5641#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
5642#define CAN_IER_FOVIE1_Pos (6U)
5643#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
5644#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
5645#define CAN_IER_EWGIE_Pos (8U)
5646#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
5647#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
5648#define CAN_IER_EPVIE_Pos (9U)
5649#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
5650#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
5651#define CAN_IER_BOFIE_Pos (10U)
5652#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
5653#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
5654#define CAN_IER_LECIE_Pos (11U)
5655#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
5656#define CAN_IER_LECIE CAN_IER_LECIE_Msk
5657#define CAN_IER_ERRIE_Pos (15U)
5658#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
5659#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
5660#define CAN_IER_WKUIE_Pos (16U)
5661#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
5662#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
5663#define CAN_IER_SLKIE_Pos (17U)
5664#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
5665#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
5667/******************** Bit definition for CAN_ESR register *******************/
5668#define CAN_ESR_EWGF_Pos (0U)
5669#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
5670#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
5671#define CAN_ESR_EPVF_Pos (1U)
5672#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
5673#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
5674#define CAN_ESR_BOFF_Pos (2U)
5675#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
5676#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
5678#define CAN_ESR_LEC_Pos (4U)
5679#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
5680#define CAN_ESR_LEC CAN_ESR_LEC_Msk
5681#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
5682#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
5683#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
5685#define CAN_ESR_TEC_Pos (16U)
5686#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
5687#define CAN_ESR_TEC CAN_ESR_TEC_Msk
5688#define CAN_ESR_REC_Pos (24U)
5689#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
5690#define CAN_ESR_REC CAN_ESR_REC_Msk
5692/******************* Bit definition for CAN_BTR register ********************/
5693#define CAN_BTR_BRP_Pos (0U)
5694#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
5695#define CAN_BTR_BRP CAN_BTR_BRP_Msk
5696#define CAN_BTR_TS1_Pos (16U)
5697#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
5698#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
5699#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
5700#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
5701#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
5702#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
5703#define CAN_BTR_TS2_Pos (20U)
5704#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
5705#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
5706#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
5707#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
5708#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
5709#define CAN_BTR_SJW_Pos (24U)
5710#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
5711#define CAN_BTR_SJW CAN_BTR_SJW_Msk
5712#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
5713#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
5714#define CAN_BTR_LBKM_Pos (30U)
5715#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
5716#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
5717#define CAN_BTR_SILM_Pos (31U)
5718#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
5719#define CAN_BTR_SILM CAN_BTR_SILM_Msk
5722/****************** Bit definition for CAN_TI0R register ********************/
5723#define CAN_TI0R_TXRQ_Pos (0U)
5724#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
5725#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
5726#define CAN_TI0R_RTR_Pos (1U)
5727#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
5728#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
5729#define CAN_TI0R_IDE_Pos (2U)
5730#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
5731#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
5732#define CAN_TI0R_EXID_Pos (3U)
5733#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
5734#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
5735#define CAN_TI0R_STID_Pos (21U)
5736#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
5737#define CAN_TI0R_STID CAN_TI0R_STID_Msk
5739/****************** Bit definition for CAN_TDT0R register *******************/
5740#define CAN_TDT0R_DLC_Pos (0U)
5741#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
5742#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
5743#define CAN_TDT0R_TGT_Pos (8U)
5744#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
5745#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
5746#define CAN_TDT0R_TIME_Pos (16U)
5747#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
5748#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
5750/****************** Bit definition for CAN_TDL0R register *******************/
5751#define CAN_TDL0R_DATA0_Pos (0U)
5752#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
5753#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
5754#define CAN_TDL0R_DATA1_Pos (8U)
5755#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
5756#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
5757#define CAN_TDL0R_DATA2_Pos (16U)
5758#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
5759#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
5760#define CAN_TDL0R_DATA3_Pos (24U)
5761#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
5762#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
5764/****************** Bit definition for CAN_TDH0R register *******************/
5765#define CAN_TDH0R_DATA4_Pos (0U)
5766#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
5767#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
5768#define CAN_TDH0R_DATA5_Pos (8U)
5769#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
5770#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
5771#define CAN_TDH0R_DATA6_Pos (16U)
5772#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
5773#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
5774#define CAN_TDH0R_DATA7_Pos (24U)
5775#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
5776#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
5778/******************* Bit definition for CAN_TI1R register *******************/
5779#define CAN_TI1R_TXRQ_Pos (0U)
5780#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
5781#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
5782#define CAN_TI1R_RTR_Pos (1U)
5783#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
5784#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
5785#define CAN_TI1R_IDE_Pos (2U)
5786#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
5787#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
5788#define CAN_TI1R_EXID_Pos (3U)
5789#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
5790#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
5791#define CAN_TI1R_STID_Pos (21U)
5792#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
5793#define CAN_TI1R_STID CAN_TI1R_STID_Msk
5795/******************* Bit definition for CAN_TDT1R register ******************/
5796#define CAN_TDT1R_DLC_Pos (0U)
5797#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
5798#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
5799#define CAN_TDT1R_TGT_Pos (8U)
5800#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
5801#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
5802#define CAN_TDT1R_TIME_Pos (16U)
5803#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
5804#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
5806/******************* Bit definition for CAN_TDL1R register ******************/
5807#define CAN_TDL1R_DATA0_Pos (0U)
5808#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
5809#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
5810#define CAN_TDL1R_DATA1_Pos (8U)
5811#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
5812#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
5813#define CAN_TDL1R_DATA2_Pos (16U)
5814#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
5815#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
5816#define CAN_TDL1R_DATA3_Pos (24U)
5817#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
5818#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
5820/******************* Bit definition for CAN_TDH1R register ******************/
5821#define CAN_TDH1R_DATA4_Pos (0U)
5822#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
5823#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
5824#define CAN_TDH1R_DATA5_Pos (8U)
5825#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
5826#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
5827#define CAN_TDH1R_DATA6_Pos (16U)
5828#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
5829#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
5830#define CAN_TDH1R_DATA7_Pos (24U)
5831#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
5832#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
5834/******************* Bit definition for CAN_TI2R register *******************/
5835#define CAN_TI2R_TXRQ_Pos (0U)
5836#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
5837#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
5838#define CAN_TI2R_RTR_Pos (1U)
5839#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
5840#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
5841#define CAN_TI2R_IDE_Pos (2U)
5842#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
5843#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
5844#define CAN_TI2R_EXID_Pos (3U)
5845#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
5846#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
5847#define CAN_TI2R_STID_Pos (21U)
5848#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
5849#define CAN_TI2R_STID CAN_TI2R_STID_Msk
5851/******************* Bit definition for CAN_TDT2R register ******************/
5852#define CAN_TDT2R_DLC_Pos (0U)
5853#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
5854#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
5855#define CAN_TDT2R_TGT_Pos (8U)
5856#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
5857#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
5858#define CAN_TDT2R_TIME_Pos (16U)
5859#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
5860#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
5862/******************* Bit definition for CAN_TDL2R register ******************/
5863#define CAN_TDL2R_DATA0_Pos (0U)
5864#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
5865#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
5866#define CAN_TDL2R_DATA1_Pos (8U)
5867#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
5868#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
5869#define CAN_TDL2R_DATA2_Pos (16U)
5870#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
5871#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
5872#define CAN_TDL2R_DATA3_Pos (24U)
5873#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
5874#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
5876/******************* Bit definition for CAN_TDH2R register ******************/
5877#define CAN_TDH2R_DATA4_Pos (0U)
5878#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
5879#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
5880#define CAN_TDH2R_DATA5_Pos (8U)
5881#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
5882#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
5883#define CAN_TDH2R_DATA6_Pos (16U)
5884#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
5885#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
5886#define CAN_TDH2R_DATA7_Pos (24U)
5887#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
5888#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
5890/******************* Bit definition for CAN_RI0R register *******************/
5891#define CAN_RI0R_RTR_Pos (1U)
5892#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
5893#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
5894#define CAN_RI0R_IDE_Pos (2U)
5895#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
5896#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
5897#define CAN_RI0R_EXID_Pos (3U)
5898#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
5899#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
5900#define CAN_RI0R_STID_Pos (21U)
5901#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
5902#define CAN_RI0R_STID CAN_RI0R_STID_Msk
5904/******************* Bit definition for CAN_RDT0R register ******************/
5905#define CAN_RDT0R_DLC_Pos (0U)
5906#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
5907#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
5908#define CAN_RDT0R_FMI_Pos (8U)
5909#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
5910#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
5911#define CAN_RDT0R_TIME_Pos (16U)
5912#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
5913#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
5915/******************* Bit definition for CAN_RDL0R register ******************/
5916#define CAN_RDL0R_DATA0_Pos (0U)
5917#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
5918#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
5919#define CAN_RDL0R_DATA1_Pos (8U)
5920#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
5921#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
5922#define CAN_RDL0R_DATA2_Pos (16U)
5923#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
5924#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
5925#define CAN_RDL0R_DATA3_Pos (24U)
5926#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
5927#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
5929/******************* Bit definition for CAN_RDH0R register ******************/
5930#define CAN_RDH0R_DATA4_Pos (0U)
5931#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
5932#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
5933#define CAN_RDH0R_DATA5_Pos (8U)
5934#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
5935#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
5936#define CAN_RDH0R_DATA6_Pos (16U)
5937#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
5938#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
5939#define CAN_RDH0R_DATA7_Pos (24U)
5940#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
5941#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
5943/******************* Bit definition for CAN_RI1R register *******************/
5944#define CAN_RI1R_RTR_Pos (1U)
5945#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
5946#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
5947#define CAN_RI1R_IDE_Pos (2U)
5948#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
5949#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
5950#define CAN_RI1R_EXID_Pos (3U)
5951#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
5952#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
5953#define CAN_RI1R_STID_Pos (21U)
5954#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
5955#define CAN_RI1R_STID CAN_RI1R_STID_Msk
5957/******************* Bit definition for CAN_RDT1R register ******************/
5958#define CAN_RDT1R_DLC_Pos (0U)
5959#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
5960#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
5961#define CAN_RDT1R_FMI_Pos (8U)
5962#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
5963#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
5964#define CAN_RDT1R_TIME_Pos (16U)
5965#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
5966#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
5968/******************* Bit definition for CAN_RDL1R register ******************/
5969#define CAN_RDL1R_DATA0_Pos (0U)
5970#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
5971#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
5972#define CAN_RDL1R_DATA1_Pos (8U)
5973#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
5974#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
5975#define CAN_RDL1R_DATA2_Pos (16U)
5976#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
5977#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
5978#define CAN_RDL1R_DATA3_Pos (24U)
5979#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
5980#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
5982/******************* Bit definition for CAN_RDH1R register ******************/
5983#define CAN_RDH1R_DATA4_Pos (0U)
5984#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
5985#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
5986#define CAN_RDH1R_DATA5_Pos (8U)
5987#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
5988#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
5989#define CAN_RDH1R_DATA6_Pos (16U)
5990#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
5991#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
5992#define CAN_RDH1R_DATA7_Pos (24U)
5993#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
5994#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
5997/******************* Bit definition for CAN_FMR register ********************/
5998#define CAN_FMR_FINIT_Pos (0U)
5999#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
6000#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
6001#define CAN_FMR_CAN2SB_Pos (8U)
6002#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
6003#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
6005/******************* Bit definition for CAN_FM1R register *******************/
6006#define CAN_FM1R_FBM_Pos (0U)
6007#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
6008#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
6009#define CAN_FM1R_FBM0_Pos (0U)
6010#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
6011#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
6012#define CAN_FM1R_FBM1_Pos (1U)
6013#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
6014#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
6015#define CAN_FM1R_FBM2_Pos (2U)
6016#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
6017#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
6018#define CAN_FM1R_FBM3_Pos (3U)
6019#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
6020#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
6021#define CAN_FM1R_FBM4_Pos (4U)
6022#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
6023#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
6024#define CAN_FM1R_FBM5_Pos (5U)
6025#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
6026#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
6027#define CAN_FM1R_FBM6_Pos (6U)
6028#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
6029#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
6030#define CAN_FM1R_FBM7_Pos (7U)
6031#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
6032#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
6033#define CAN_FM1R_FBM8_Pos (8U)
6034#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
6035#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
6036#define CAN_FM1R_FBM9_Pos (9U)
6037#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
6038#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
6039#define CAN_FM1R_FBM10_Pos (10U)
6040#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
6041#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
6042#define CAN_FM1R_FBM11_Pos (11U)
6043#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
6044#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
6045#define CAN_FM1R_FBM12_Pos (12U)
6046#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
6047#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
6048#define CAN_FM1R_FBM13_Pos (13U)
6049#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
6050#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
6051#define CAN_FM1R_FBM14_Pos (14U)
6052#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
6053#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
6054#define CAN_FM1R_FBM15_Pos (15U)
6055#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
6056#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
6057#define CAN_FM1R_FBM16_Pos (16U)
6058#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
6059#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
6060#define CAN_FM1R_FBM17_Pos (17U)
6061#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
6062#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
6063#define CAN_FM1R_FBM18_Pos (18U)
6064#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
6065#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
6066#define CAN_FM1R_FBM19_Pos (19U)
6067#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
6068#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
6069#define CAN_FM1R_FBM20_Pos (20U)
6070#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
6071#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
6072#define CAN_FM1R_FBM21_Pos (21U)
6073#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
6074#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
6075#define CAN_FM1R_FBM22_Pos (22U)
6076#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
6077#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
6078#define CAN_FM1R_FBM23_Pos (23U)
6079#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
6080#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
6081#define CAN_FM1R_FBM24_Pos (24U)
6082#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
6083#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
6084#define CAN_FM1R_FBM25_Pos (25U)
6085#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
6086#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
6087#define CAN_FM1R_FBM26_Pos (26U)
6088#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
6089#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
6090#define CAN_FM1R_FBM27_Pos (27U)
6091#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
6092#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
6094/******************* Bit definition for CAN_FS1R register *******************/
6095#define CAN_FS1R_FSC_Pos (0U)
6096#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
6097#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
6098#define CAN_FS1R_FSC0_Pos (0U)
6099#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
6100#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
6101#define CAN_FS1R_FSC1_Pos (1U)
6102#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
6103#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
6104#define CAN_FS1R_FSC2_Pos (2U)
6105#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
6106#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
6107#define CAN_FS1R_FSC3_Pos (3U)
6108#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
6109#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
6110#define CAN_FS1R_FSC4_Pos (4U)
6111#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
6112#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
6113#define CAN_FS1R_FSC5_Pos (5U)
6114#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
6115#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
6116#define CAN_FS1R_FSC6_Pos (6U)
6117#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
6118#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
6119#define CAN_FS1R_FSC7_Pos (7U)
6120#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
6121#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
6122#define CAN_FS1R_FSC8_Pos (8U)
6123#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
6124#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
6125#define CAN_FS1R_FSC9_Pos (9U)
6126#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
6127#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
6128#define CAN_FS1R_FSC10_Pos (10U)
6129#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
6130#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
6131#define CAN_FS1R_FSC11_Pos (11U)
6132#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
6133#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
6134#define CAN_FS1R_FSC12_Pos (12U)
6135#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
6136#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
6137#define CAN_FS1R_FSC13_Pos (13U)
6138#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
6139#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
6140#define CAN_FS1R_FSC14_Pos (14U)
6141#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
6142#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
6143#define CAN_FS1R_FSC15_Pos (15U)
6144#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
6145#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
6146#define CAN_FS1R_FSC16_Pos (16U)
6147#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
6148#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
6149#define CAN_FS1R_FSC17_Pos (17U)
6150#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
6151#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
6152#define CAN_FS1R_FSC18_Pos (18U)
6153#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
6154#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
6155#define CAN_FS1R_FSC19_Pos (19U)
6156#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
6157#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
6158#define CAN_FS1R_FSC20_Pos (20U)
6159#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
6160#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
6161#define CAN_FS1R_FSC21_Pos (21U)
6162#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
6163#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
6164#define CAN_FS1R_FSC22_Pos (22U)
6165#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
6166#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
6167#define CAN_FS1R_FSC23_Pos (23U)
6168#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
6169#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
6170#define CAN_FS1R_FSC24_Pos (24U)
6171#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
6172#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
6173#define CAN_FS1R_FSC25_Pos (25U)
6174#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
6175#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
6176#define CAN_FS1R_FSC26_Pos (26U)
6177#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
6178#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
6179#define CAN_FS1R_FSC27_Pos (27U)
6180#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
6181#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
6183/****************** Bit definition for CAN_FFA1R register *******************/
6184#define CAN_FFA1R_FFA_Pos (0U)
6185#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
6186#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
6187#define CAN_FFA1R_FFA0_Pos (0U)
6188#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
6189#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
6190#define CAN_FFA1R_FFA1_Pos (1U)
6191#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
6192#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
6193#define CAN_FFA1R_FFA2_Pos (2U)
6194#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
6195#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
6196#define CAN_FFA1R_FFA3_Pos (3U)
6197#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
6198#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
6199#define CAN_FFA1R_FFA4_Pos (4U)
6200#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
6201#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
6202#define CAN_FFA1R_FFA5_Pos (5U)
6203#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
6204#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
6205#define CAN_FFA1R_FFA6_Pos (6U)
6206#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
6207#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
6208#define CAN_FFA1R_FFA7_Pos (7U)
6209#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
6210#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
6211#define CAN_FFA1R_FFA8_Pos (8U)
6212#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
6213#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
6214#define CAN_FFA1R_FFA9_Pos (9U)
6215#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
6216#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
6217#define CAN_FFA1R_FFA10_Pos (10U)
6218#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
6219#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
6220#define CAN_FFA1R_FFA11_Pos (11U)
6221#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
6222#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
6223#define CAN_FFA1R_FFA12_Pos (12U)
6224#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
6225#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
6226#define CAN_FFA1R_FFA13_Pos (13U)
6227#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
6228#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
6229#define CAN_FFA1_FFA14_Pos (14U)
6230#define CAN_FFA1_FFA14_Msk (0x1UL << CAN_FFA1_FFA14_Pos)
6231#define CAN_FFA1_FFA14 CAN_FFA1_FFA14_Msk
6232#define CAN_FFA1_FFA15_Pos (15U)
6233#define CAN_FFA1_FFA15_Msk (0x1UL << CAN_FFA1_FFA15_Pos)
6234#define CAN_FFA1_FFA15 CAN_FFA1_FFA15_Msk
6235#define CAN_FFA1_FFA16_Pos (16U)
6236#define CAN_FFA1_FFA16_Msk (0x1UL << CAN_FFA1_FFA16_Pos)
6237#define CAN_FFA1_FFA16 CAN_FFA1_FFA16_Msk
6238#define CAN_FFA1_FFA17_Pos (17U)
6239#define CAN_FFA1_FFA17_Msk (0x1UL << CAN_FFA1_FFA17_Pos)
6240#define CAN_FFA1_FFA17 CAN_FFA1_FFA17_Msk
6241#define CAN_FFA1_FFA18_Pos (18U)
6242#define CAN_FFA1_FFA18_Msk (0x1UL << CAN_FFA1_FFA18_Pos)
6243#define CAN_FFA1_FFA18 CAN_FFA1_FFA18_Msk
6244#define CAN_FFA1_FFA19_Pos (19U)
6245#define CAN_FFA1_FFA19_Msk (0x1UL << CAN_FFA1_FFA19_Pos)
6246#define CAN_FFA1_FFA19 CAN_FFA1_FFA19_Msk
6247#define CAN_FFA1_FFA20_Pos (20U)
6248#define CAN_FFA1_FFA20_Msk (0x1UL << CAN_FFA1_FFA20_Pos)
6249#define CAN_FFA1_FFA20 CAN_FFA1_FFA20_Msk
6250#define CAN_FFA1_FFA21_Pos (21U)
6251#define CAN_FFA1_FFA21_Msk (0x1UL << CAN_FFA1_FFA21_Pos)
6252#define CAN_FFA1_FFA21 CAN_FFA1_FFA21_Msk
6253#define CAN_FFA1_FFA22_Pos (22U)
6254#define CAN_FFA1_FFA22_Msk (0x1UL << CAN_FFA1_FFA22_Pos)
6255#define CAN_FFA1_FFA22 CAN_FFA1_FFA22_Msk
6256#define CAN_FFA1_FFA23_Pos (23U)
6257#define CAN_FFA1_FFA23_Msk (0x1UL << CAN_FFA1_FFA23_Pos)
6258#define CAN_FFA1_FFA23 CAN_FFA1_FFA23_Msk
6259#define CAN_FFA1_FFA24_Pos (24U)
6260#define CAN_FFA1_FFA24_Msk (0x1UL << CAN_FFA1_FFA24_Pos)
6261#define CAN_FFA1_FFA24 CAN_FFA1_FFA24_Msk
6262#define CAN_FFA1_FFA25_Pos (25U)
6263#define CAN_FFA1_FFA25_Msk (0x1UL << CAN_FFA1_FFA25_Pos)
6264#define CAN_FFA1_FFA25 CAN_FFA1_FFA25_Msk
6265#define CAN_FFA1_FFA26_Pos (26U)
6266#define CAN_FFA1_FFA26_Msk (0x1UL << CAN_FFA1_FFA26_Pos)
6267#define CAN_FFA1_FFA26 CAN_FFA1_FFA26_Msk
6268#define CAN_FFA1_FFA27_Pos (27U)
6269#define CAN_FFA1_FFA27_Msk (0x1UL << CAN_FFA1_FFA27_Pos)
6270#define CAN_FFA1_FFA27 CAN_FFA1_FFA27_Msk
6272/******************* Bit definition for CAN_FA1R register *******************/
6273#define CAN_FA1R_FACT_Pos (0U)
6274#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
6275#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
6276#define CAN_FA1R_FACT0_Pos (0U)
6277#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
6278#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
6279#define CAN_FA1R_FACT1_Pos (1U)
6280#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
6281#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
6282#define CAN_FA1R_FACT2_Pos (2U)
6283#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
6284#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
6285#define CAN_FA1R_FACT3_Pos (3U)
6286#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
6287#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
6288#define CAN_FA1R_FACT4_Pos (4U)
6289#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
6290#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
6291#define CAN_FA1R_FACT5_Pos (5U)
6292#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
6293#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
6294#define CAN_FA1R_FACT6_Pos (6U)
6295#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
6296#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
6297#define CAN_FA1R_FACT7_Pos (7U)
6298#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
6299#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
6300#define CAN_FA1R_FACT8_Pos (8U)
6301#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
6302#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
6303#define CAN_FA1R_FACT9_Pos (9U)
6304#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
6305#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
6306#define CAN_FA1R_FACT10_Pos (10U)
6307#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
6308#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
6309#define CAN_FA1R_FACT11_Pos (11U)
6310#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
6311#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
6312#define CAN_FA1R_FACT12_Pos (12U)
6313#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
6314#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
6315#define CAN_FA1R_FACT13_Pos (13U)
6316#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
6317#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
6318#define CAN_FA1R_FACT14_Pos (14U)
6319#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
6320#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
6321#define CAN_FA1R_FACT15_Pos (15U)
6322#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
6323#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
6324#define CAN_FA1R_FACT16_Pos (16U)
6325#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
6326#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
6327#define CAN_FA1R_FACT17_Pos (17U)
6328#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
6329#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
6330#define CAN_FA1R_FACT18_Pos (18U)
6331#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
6332#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
6333#define CAN_FA1R_FACT19_Pos (19U)
6334#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
6335#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
6336#define CAN_FA1R_FACT20_Pos (20U)
6337#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
6338#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
6339#define CAN_FA1R_FACT21_Pos (21U)
6340#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
6341#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
6342#define CAN_FA1R_FACT22_Pos (22U)
6343#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
6344#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
6345#define CAN_FA1R_FACT23_Pos (23U)
6346#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
6347#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
6348#define CAN_FA1R_FACT24_Pos (24U)
6349#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
6350#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
6351#define CAN_FA1R_FACT25_Pos (25U)
6352#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
6353#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
6354#define CAN_FA1R_FACT26_Pos (26U)
6355#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
6356#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
6357#define CAN_FA1R_FACT27_Pos (27U)
6358#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
6359#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
6361/******************* Bit definition for CAN_F0R1 register *******************/
6362#define CAN_F0R1_FB0_Pos (0U)
6363#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
6364#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
6365#define CAN_F0R1_FB1_Pos (1U)
6366#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
6367#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
6368#define CAN_F0R1_FB2_Pos (2U)
6369#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
6370#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
6371#define CAN_F0R1_FB3_Pos (3U)
6372#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
6373#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
6374#define CAN_F0R1_FB4_Pos (4U)
6375#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
6376#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
6377#define CAN_F0R1_FB5_Pos (5U)
6378#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
6379#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
6380#define CAN_F0R1_FB6_Pos (6U)
6381#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
6382#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
6383#define CAN_F0R1_FB7_Pos (7U)
6384#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
6385#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
6386#define CAN_F0R1_FB8_Pos (8U)
6387#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
6388#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
6389#define CAN_F0R1_FB9_Pos (9U)
6390#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
6391#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
6392#define CAN_F0R1_FB10_Pos (10U)
6393#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
6394#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
6395#define CAN_F0R1_FB11_Pos (11U)
6396#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
6397#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
6398#define CAN_F0R1_FB12_Pos (12U)
6399#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
6400#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
6401#define CAN_F0R1_FB13_Pos (13U)
6402#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
6403#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
6404#define CAN_F0R1_FB14_Pos (14U)
6405#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
6406#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
6407#define CAN_F0R1_FB15_Pos (15U)
6408#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
6409#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
6410#define CAN_F0R1_FB16_Pos (16U)
6411#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
6412#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
6413#define CAN_F0R1_FB17_Pos (17U)
6414#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
6415#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
6416#define CAN_F0R1_FB18_Pos (18U)
6417#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
6418#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
6419#define CAN_F0R1_FB19_Pos (19U)
6420#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
6421#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
6422#define CAN_F0R1_FB20_Pos (20U)
6423#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
6424#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
6425#define CAN_F0R1_FB21_Pos (21U)
6426#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
6427#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
6428#define CAN_F0R1_FB22_Pos (22U)
6429#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
6430#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
6431#define CAN_F0R1_FB23_Pos (23U)
6432#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
6433#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
6434#define CAN_F0R1_FB24_Pos (24U)
6435#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
6436#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
6437#define CAN_F0R1_FB25_Pos (25U)
6438#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
6439#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
6440#define CAN_F0R1_FB26_Pos (26U)
6441#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
6442#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
6443#define CAN_F0R1_FB27_Pos (27U)
6444#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
6445#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
6446#define CAN_F0R1_FB28_Pos (28U)
6447#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
6448#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
6449#define CAN_F0R1_FB29_Pos (29U)
6450#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
6451#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
6452#define CAN_F0R1_FB30_Pos (30U)
6453#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
6454#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
6455#define CAN_F0R1_FB31_Pos (31U)
6456#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
6457#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
6459/******************* Bit definition for CAN_F1R1 register *******************/
6460#define CAN_F1R1_FB0_Pos (0U)
6461#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
6462#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
6463#define CAN_F1R1_FB1_Pos (1U)
6464#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
6465#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
6466#define CAN_F1R1_FB2_Pos (2U)
6467#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
6468#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
6469#define CAN_F1R1_FB3_Pos (3U)
6470#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
6471#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
6472#define CAN_F1R1_FB4_Pos (4U)
6473#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
6474#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
6475#define CAN_F1R1_FB5_Pos (5U)
6476#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
6477#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
6478#define CAN_F1R1_FB6_Pos (6U)
6479#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
6480#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
6481#define CAN_F1R1_FB7_Pos (7U)
6482#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
6483#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
6484#define CAN_F1R1_FB8_Pos (8U)
6485#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
6486#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
6487#define CAN_F1R1_FB9_Pos (9U)
6488#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
6489#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
6490#define CAN_F1R1_FB10_Pos (10U)
6491#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
6492#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
6493#define CAN_F1R1_FB11_Pos (11U)
6494#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
6495#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
6496#define CAN_F1R1_FB12_Pos (12U)
6497#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
6498#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
6499#define CAN_F1R1_FB13_Pos (13U)
6500#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
6501#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
6502#define CAN_F1R1_FB14_Pos (14U)
6503#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
6504#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
6505#define CAN_F1R1_FB15_Pos (15U)
6506#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
6507#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
6508#define CAN_F1R1_FB16_Pos (16U)
6509#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
6510#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
6511#define CAN_F1R1_FB17_Pos (17U)
6512#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
6513#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
6514#define CAN_F1R1_FB18_Pos (18U)
6515#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
6516#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
6517#define CAN_F1R1_FB19_Pos (19U)
6518#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
6519#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
6520#define CAN_F1R1_FB20_Pos (20U)
6521#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
6522#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
6523#define CAN_F1R1_FB21_Pos (21U)
6524#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
6525#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
6526#define CAN_F1R1_FB22_Pos (22U)
6527#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
6528#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
6529#define CAN_F1R1_FB23_Pos (23U)
6530#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
6531#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
6532#define CAN_F1R1_FB24_Pos (24U)
6533#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
6534#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
6535#define CAN_F1R1_FB25_Pos (25U)
6536#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
6537#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
6538#define CAN_F1R1_FB26_Pos (26U)
6539#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
6540#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
6541#define CAN_F1R1_FB27_Pos (27U)
6542#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
6543#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
6544#define CAN_F1R1_FB28_Pos (28U)
6545#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
6546#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
6547#define CAN_F1R1_FB29_Pos (29U)
6548#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
6549#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
6550#define CAN_F1R1_FB30_Pos (30U)
6551#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
6552#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
6553#define CAN_F1R1_FB31_Pos (31U)
6554#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
6555#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
6557/******************* Bit definition for CAN_F2R1 register *******************/
6558#define CAN_F2R1_FB0_Pos (0U)
6559#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
6560#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
6561#define CAN_F2R1_FB1_Pos (1U)
6562#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
6563#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
6564#define CAN_F2R1_FB2_Pos (2U)
6565#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
6566#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
6567#define CAN_F2R1_FB3_Pos (3U)
6568#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
6569#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
6570#define CAN_F2R1_FB4_Pos (4U)
6571#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
6572#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
6573#define CAN_F2R1_FB5_Pos (5U)
6574#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
6575#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
6576#define CAN_F2R1_FB6_Pos (6U)
6577#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
6578#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
6579#define CAN_F2R1_FB7_Pos (7U)
6580#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
6581#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
6582#define CAN_F2R1_FB8_Pos (8U)
6583#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
6584#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
6585#define CAN_F2R1_FB9_Pos (9U)
6586#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
6587#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
6588#define CAN_F2R1_FB10_Pos (10U)
6589#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
6590#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
6591#define CAN_F2R1_FB11_Pos (11U)
6592#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
6593#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
6594#define CAN_F2R1_FB12_Pos (12U)
6595#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
6596#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
6597#define CAN_F2R1_FB13_Pos (13U)
6598#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
6599#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
6600#define CAN_F2R1_FB14_Pos (14U)
6601#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
6602#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
6603#define CAN_F2R1_FB15_Pos (15U)
6604#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
6605#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
6606#define CAN_F2R1_FB16_Pos (16U)
6607#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
6608#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
6609#define CAN_F2R1_FB17_Pos (17U)
6610#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
6611#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
6612#define CAN_F2R1_FB18_Pos (18U)
6613#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
6614#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
6615#define CAN_F2R1_FB19_Pos (19U)
6616#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
6617#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
6618#define CAN_F2R1_FB20_Pos (20U)
6619#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
6620#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
6621#define CAN_F2R1_FB21_Pos (21U)
6622#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
6623#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
6624#define CAN_F2R1_FB22_Pos (22U)
6625#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
6626#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
6627#define CAN_F2R1_FB23_Pos (23U)
6628#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
6629#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
6630#define CAN_F2R1_FB24_Pos (24U)
6631#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
6632#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
6633#define CAN_F2R1_FB25_Pos (25U)
6634#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
6635#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
6636#define CAN_F2R1_FB26_Pos (26U)
6637#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
6638#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
6639#define CAN_F2R1_FB27_Pos (27U)
6640#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
6641#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
6642#define CAN_F2R1_FB28_Pos (28U)
6643#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
6644#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
6645#define CAN_F2R1_FB29_Pos (29U)
6646#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
6647#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
6648#define CAN_F2R1_FB30_Pos (30U)
6649#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
6650#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
6651#define CAN_F2R1_FB31_Pos (31U)
6652#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
6653#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
6655/******************* Bit definition for CAN_F3R1 register *******************/
6656#define CAN_F3R1_FB0_Pos (0U)
6657#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
6658#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
6659#define CAN_F3R1_FB1_Pos (1U)
6660#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
6661#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
6662#define CAN_F3R1_FB2_Pos (2U)
6663#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
6664#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
6665#define CAN_F3R1_FB3_Pos (3U)
6666#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
6667#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
6668#define CAN_F3R1_FB4_Pos (4U)
6669#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
6670#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
6671#define CAN_F3R1_FB5_Pos (5U)
6672#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
6673#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
6674#define CAN_F3R1_FB6_Pos (6U)
6675#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
6676#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
6677#define CAN_F3R1_FB7_Pos (7U)
6678#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
6679#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
6680#define CAN_F3R1_FB8_Pos (8U)
6681#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
6682#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
6683#define CAN_F3R1_FB9_Pos (9U)
6684#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
6685#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
6686#define CAN_F3R1_FB10_Pos (10U)
6687#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
6688#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
6689#define CAN_F3R1_FB11_Pos (11U)
6690#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
6691#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
6692#define CAN_F3R1_FB12_Pos (12U)
6693#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
6694#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
6695#define CAN_F3R1_FB13_Pos (13U)
6696#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
6697#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
6698#define CAN_F3R1_FB14_Pos (14U)
6699#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
6700#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
6701#define CAN_F3R1_FB15_Pos (15U)
6702#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
6703#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
6704#define CAN_F3R1_FB16_Pos (16U)
6705#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
6706#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
6707#define CAN_F3R1_FB17_Pos (17U)
6708#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
6709#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
6710#define CAN_F3R1_FB18_Pos (18U)
6711#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
6712#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
6713#define CAN_F3R1_FB19_Pos (19U)
6714#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
6715#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
6716#define CAN_F3R1_FB20_Pos (20U)
6717#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
6718#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
6719#define CAN_F3R1_FB21_Pos (21U)
6720#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
6721#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
6722#define CAN_F3R1_FB22_Pos (22U)
6723#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
6724#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
6725#define CAN_F3R1_FB23_Pos (23U)
6726#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
6727#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
6728#define CAN_F3R1_FB24_Pos (24U)
6729#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
6730#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
6731#define CAN_F3R1_FB25_Pos (25U)
6732#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
6733#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
6734#define CAN_F3R1_FB26_Pos (26U)
6735#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
6736#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
6737#define CAN_F3R1_FB27_Pos (27U)
6738#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
6739#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
6740#define CAN_F3R1_FB28_Pos (28U)
6741#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
6742#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
6743#define CAN_F3R1_FB29_Pos (29U)
6744#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
6745#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
6746#define CAN_F3R1_FB30_Pos (30U)
6747#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
6748#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
6749#define CAN_F3R1_FB31_Pos (31U)
6750#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
6751#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
6753/******************* Bit definition for CAN_F4R1 register *******************/
6754#define CAN_F4R1_FB0_Pos (0U)
6755#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
6756#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
6757#define CAN_F4R1_FB1_Pos (1U)
6758#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
6759#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
6760#define CAN_F4R1_FB2_Pos (2U)
6761#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
6762#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
6763#define CAN_F4R1_FB3_Pos (3U)
6764#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
6765#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
6766#define CAN_F4R1_FB4_Pos (4U)
6767#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
6768#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
6769#define CAN_F4R1_FB5_Pos (5U)
6770#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
6771#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
6772#define CAN_F4R1_FB6_Pos (6U)
6773#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
6774#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
6775#define CAN_F4R1_FB7_Pos (7U)
6776#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
6777#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
6778#define CAN_F4R1_FB8_Pos (8U)
6779#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
6780#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
6781#define CAN_F4R1_FB9_Pos (9U)
6782#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
6783#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
6784#define CAN_F4R1_FB10_Pos (10U)
6785#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
6786#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
6787#define CAN_F4R1_FB11_Pos (11U)
6788#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
6789#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
6790#define CAN_F4R1_FB12_Pos (12U)
6791#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
6792#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
6793#define CAN_F4R1_FB13_Pos (13U)
6794#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
6795#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
6796#define CAN_F4R1_FB14_Pos (14U)
6797#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
6798#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
6799#define CAN_F4R1_FB15_Pos (15U)
6800#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
6801#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
6802#define CAN_F4R1_FB16_Pos (16U)
6803#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
6804#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
6805#define CAN_F4R1_FB17_Pos (17U)
6806#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
6807#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
6808#define CAN_F4R1_FB18_Pos (18U)
6809#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
6810#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
6811#define CAN_F4R1_FB19_Pos (19U)
6812#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
6813#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
6814#define CAN_F4R1_FB20_Pos (20U)
6815#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
6816#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
6817#define CAN_F4R1_FB21_Pos (21U)
6818#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
6819#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
6820#define CAN_F4R1_FB22_Pos (22U)
6821#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
6822#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
6823#define CAN_F4R1_FB23_Pos (23U)
6824#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
6825#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
6826#define CAN_F4R1_FB24_Pos (24U)
6827#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
6828#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
6829#define CAN_F4R1_FB25_Pos (25U)
6830#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
6831#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
6832#define CAN_F4R1_FB26_Pos (26U)
6833#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
6834#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
6835#define CAN_F4R1_FB27_Pos (27U)
6836#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
6837#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
6838#define CAN_F4R1_FB28_Pos (28U)
6839#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
6840#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
6841#define CAN_F4R1_FB29_Pos (29U)
6842#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
6843#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
6844#define CAN_F4R1_FB30_Pos (30U)
6845#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
6846#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
6847#define CAN_F4R1_FB31_Pos (31U)
6848#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
6849#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
6851/******************* Bit definition for CAN_F5R1 register *******************/
6852#define CAN_F5R1_FB0_Pos (0U)
6853#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
6854#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
6855#define CAN_F5R1_FB1_Pos (1U)
6856#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
6857#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
6858#define CAN_F5R1_FB2_Pos (2U)
6859#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
6860#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
6861#define CAN_F5R1_FB3_Pos (3U)
6862#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
6863#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
6864#define CAN_F5R1_FB4_Pos (4U)
6865#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
6866#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
6867#define CAN_F5R1_FB5_Pos (5U)
6868#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
6869#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
6870#define CAN_F5R1_FB6_Pos (6U)
6871#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
6872#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
6873#define CAN_F5R1_FB7_Pos (7U)
6874#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
6875#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
6876#define CAN_F5R1_FB8_Pos (8U)
6877#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
6878#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
6879#define CAN_F5R1_FB9_Pos (9U)
6880#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
6881#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
6882#define CAN_F5R1_FB10_Pos (10U)
6883#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
6884#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
6885#define CAN_F5R1_FB11_Pos (11U)
6886#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
6887#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
6888#define CAN_F5R1_FB12_Pos (12U)
6889#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
6890#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
6891#define CAN_F5R1_FB13_Pos (13U)
6892#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
6893#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
6894#define CAN_F5R1_FB14_Pos (14U)
6895#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
6896#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
6897#define CAN_F5R1_FB15_Pos (15U)
6898#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
6899#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
6900#define CAN_F5R1_FB16_Pos (16U)
6901#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
6902#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
6903#define CAN_F5R1_FB17_Pos (17U)
6904#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
6905#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
6906#define CAN_F5R1_FB18_Pos (18U)
6907#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
6908#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
6909#define CAN_F5R1_FB19_Pos (19U)
6910#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
6911#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
6912#define CAN_F5R1_FB20_Pos (20U)
6913#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
6914#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
6915#define CAN_F5R1_FB21_Pos (21U)
6916#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
6917#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
6918#define CAN_F5R1_FB22_Pos (22U)
6919#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
6920#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
6921#define CAN_F5R1_FB23_Pos (23U)
6922#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
6923#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
6924#define CAN_F5R1_FB24_Pos (24U)
6925#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
6926#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
6927#define CAN_F5R1_FB25_Pos (25U)
6928#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
6929#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
6930#define CAN_F5R1_FB26_Pos (26U)
6931#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
6932#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
6933#define CAN_F5R1_FB27_Pos (27U)
6934#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
6935#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
6936#define CAN_F5R1_FB28_Pos (28U)
6937#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
6938#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
6939#define CAN_F5R1_FB29_Pos (29U)
6940#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
6941#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
6942#define CAN_F5R1_FB30_Pos (30U)
6943#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
6944#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
6945#define CAN_F5R1_FB31_Pos (31U)
6946#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
6947#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
6949/******************* Bit definition for CAN_F6R1 register *******************/
6950#define CAN_F6R1_FB0_Pos (0U)
6951#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
6952#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
6953#define CAN_F6R1_FB1_Pos (1U)
6954#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
6955#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
6956#define CAN_F6R1_FB2_Pos (2U)
6957#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
6958#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
6959#define CAN_F6R1_FB3_Pos (3U)
6960#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
6961#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
6962#define CAN_F6R1_FB4_Pos (4U)
6963#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
6964#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
6965#define CAN_F6R1_FB5_Pos (5U)
6966#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
6967#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
6968#define CAN_F6R1_FB6_Pos (6U)
6969#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
6970#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
6971#define CAN_F6R1_FB7_Pos (7U)
6972#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
6973#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
6974#define CAN_F6R1_FB8_Pos (8U)
6975#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
6976#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
6977#define CAN_F6R1_FB9_Pos (9U)
6978#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
6979#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
6980#define CAN_F6R1_FB10_Pos (10U)
6981#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
6982#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
6983#define CAN_F6R1_FB11_Pos (11U)
6984#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
6985#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
6986#define CAN_F6R1_FB12_Pos (12U)
6987#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
6988#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
6989#define CAN_F6R1_FB13_Pos (13U)
6990#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
6991#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
6992#define CAN_F6R1_FB14_Pos (14U)
6993#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
6994#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
6995#define CAN_F6R1_FB15_Pos (15U)
6996#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
6997#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
6998#define CAN_F6R1_FB16_Pos (16U)
6999#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
7000#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
7001#define CAN_F6R1_FB17_Pos (17U)
7002#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
7003#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
7004#define CAN_F6R1_FB18_Pos (18U)
7005#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
7006#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
7007#define CAN_F6R1_FB19_Pos (19U)
7008#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
7009#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
7010#define CAN_F6R1_FB20_Pos (20U)
7011#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
7012#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
7013#define CAN_F6R1_FB21_Pos (21U)
7014#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
7015#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
7016#define CAN_F6R1_FB22_Pos (22U)
7017#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
7018#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
7019#define CAN_F6R1_FB23_Pos (23U)
7020#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
7021#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
7022#define CAN_F6R1_FB24_Pos (24U)
7023#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
7024#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
7025#define CAN_F6R1_FB25_Pos (25U)
7026#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
7027#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
7028#define CAN_F6R1_FB26_Pos (26U)
7029#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
7030#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
7031#define CAN_F6R1_FB27_Pos (27U)
7032#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
7033#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
7034#define CAN_F6R1_FB28_Pos (28U)
7035#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
7036#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
7037#define CAN_F6R1_FB29_Pos (29U)
7038#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
7039#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
7040#define CAN_F6R1_FB30_Pos (30U)
7041#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
7042#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
7043#define CAN_F6R1_FB31_Pos (31U)
7044#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
7045#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
7047/******************* Bit definition for CAN_F7R1 register *******************/
7048#define CAN_F7R1_FB0_Pos (0U)
7049#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
7050#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
7051#define CAN_F7R1_FB1_Pos (1U)
7052#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
7053#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
7054#define CAN_F7R1_FB2_Pos (2U)
7055#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
7056#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
7057#define CAN_F7R1_FB3_Pos (3U)
7058#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
7059#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
7060#define CAN_F7R1_FB4_Pos (4U)
7061#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
7062#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
7063#define CAN_F7R1_FB5_Pos (5U)
7064#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
7065#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
7066#define CAN_F7R1_FB6_Pos (6U)
7067#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
7068#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
7069#define CAN_F7R1_FB7_Pos (7U)
7070#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
7071#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
7072#define CAN_F7R1_FB8_Pos (8U)
7073#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
7074#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
7075#define CAN_F7R1_FB9_Pos (9U)
7076#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
7077#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
7078#define CAN_F7R1_FB10_Pos (10U)
7079#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
7080#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
7081#define CAN_F7R1_FB11_Pos (11U)
7082#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
7083#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
7084#define CAN_F7R1_FB12_Pos (12U)
7085#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
7086#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
7087#define CAN_F7R1_FB13_Pos (13U)
7088#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
7089#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
7090#define CAN_F7R1_FB14_Pos (14U)
7091#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
7092#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
7093#define CAN_F7R1_FB15_Pos (15U)
7094#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
7095#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
7096#define CAN_F7R1_FB16_Pos (16U)
7097#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
7098#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
7099#define CAN_F7R1_FB17_Pos (17U)
7100#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
7101#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
7102#define CAN_F7R1_FB18_Pos (18U)
7103#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
7104#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
7105#define CAN_F7R1_FB19_Pos (19U)
7106#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
7107#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
7108#define CAN_F7R1_FB20_Pos (20U)
7109#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
7110#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
7111#define CAN_F7R1_FB21_Pos (21U)
7112#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
7113#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
7114#define CAN_F7R1_FB22_Pos (22U)
7115#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
7116#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
7117#define CAN_F7R1_FB23_Pos (23U)
7118#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
7119#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
7120#define CAN_F7R1_FB24_Pos (24U)
7121#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
7122#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
7123#define CAN_F7R1_FB25_Pos (25U)
7124#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
7125#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
7126#define CAN_F7R1_FB26_Pos (26U)
7127#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
7128#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
7129#define CAN_F7R1_FB27_Pos (27U)
7130#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
7131#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
7132#define CAN_F7R1_FB28_Pos (28U)
7133#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
7134#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
7135#define CAN_F7R1_FB29_Pos (29U)
7136#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
7137#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
7138#define CAN_F7R1_FB30_Pos (30U)
7139#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
7140#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
7141#define CAN_F7R1_FB31_Pos (31U)
7142#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
7143#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
7145/******************* Bit definition for CAN_F8R1 register *******************/
7146#define CAN_F8R1_FB0_Pos (0U)
7147#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
7148#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
7149#define CAN_F8R1_FB1_Pos (1U)
7150#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
7151#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
7152#define CAN_F8R1_FB2_Pos (2U)
7153#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
7154#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
7155#define CAN_F8R1_FB3_Pos (3U)
7156#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
7157#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
7158#define CAN_F8R1_FB4_Pos (4U)
7159#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
7160#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
7161#define CAN_F8R1_FB5_Pos (5U)
7162#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
7163#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
7164#define CAN_F8R1_FB6_Pos (6U)
7165#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
7166#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
7167#define CAN_F8R1_FB7_Pos (7U)
7168#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
7169#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
7170#define CAN_F8R1_FB8_Pos (8U)
7171#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
7172#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
7173#define CAN_F8R1_FB9_Pos (9U)
7174#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
7175#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
7176#define CAN_F8R1_FB10_Pos (10U)
7177#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
7178#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
7179#define CAN_F8R1_FB11_Pos (11U)
7180#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
7181#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
7182#define CAN_F8R1_FB12_Pos (12U)
7183#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
7184#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
7185#define CAN_F8R1_FB13_Pos (13U)
7186#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
7187#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
7188#define CAN_F8R1_FB14_Pos (14U)
7189#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
7190#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
7191#define CAN_F8R1_FB15_Pos (15U)
7192#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
7193#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
7194#define CAN_F8R1_FB16_Pos (16U)
7195#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
7196#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
7197#define CAN_F8R1_FB17_Pos (17U)
7198#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
7199#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
7200#define CAN_F8R1_FB18_Pos (18U)
7201#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
7202#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
7203#define CAN_F8R1_FB19_Pos (19U)
7204#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
7205#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
7206#define CAN_F8R1_FB20_Pos (20U)
7207#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
7208#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
7209#define CAN_F8R1_FB21_Pos (21U)
7210#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
7211#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
7212#define CAN_F8R1_FB22_Pos (22U)
7213#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
7214#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
7215#define CAN_F8R1_FB23_Pos (23U)
7216#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
7217#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
7218#define CAN_F8R1_FB24_Pos (24U)
7219#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
7220#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
7221#define CAN_F8R1_FB25_Pos (25U)
7222#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
7223#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
7224#define CAN_F8R1_FB26_Pos (26U)
7225#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
7226#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
7227#define CAN_F8R1_FB27_Pos (27U)
7228#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
7229#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
7230#define CAN_F8R1_FB28_Pos (28U)
7231#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
7232#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
7233#define CAN_F8R1_FB29_Pos (29U)
7234#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
7235#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
7236#define CAN_F8R1_FB30_Pos (30U)
7237#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
7238#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
7239#define CAN_F8R1_FB31_Pos (31U)
7240#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
7241#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
7243/******************* Bit definition for CAN_F9R1 register *******************/
7244#define CAN_F9R1_FB0_Pos (0U)
7245#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
7246#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
7247#define CAN_F9R1_FB1_Pos (1U)
7248#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
7249#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
7250#define CAN_F9R1_FB2_Pos (2U)
7251#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
7252#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
7253#define CAN_F9R1_FB3_Pos (3U)
7254#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
7255#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
7256#define CAN_F9R1_FB4_Pos (4U)
7257#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
7258#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
7259#define CAN_F9R1_FB5_Pos (5U)
7260#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
7261#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
7262#define CAN_F9R1_FB6_Pos (6U)
7263#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
7264#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
7265#define CAN_F9R1_FB7_Pos (7U)
7266#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
7267#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
7268#define CAN_F9R1_FB8_Pos (8U)
7269#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
7270#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
7271#define CAN_F9R1_FB9_Pos (9U)
7272#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
7273#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
7274#define CAN_F9R1_FB10_Pos (10U)
7275#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
7276#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
7277#define CAN_F9R1_FB11_Pos (11U)
7278#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
7279#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
7280#define CAN_F9R1_FB12_Pos (12U)
7281#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
7282#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
7283#define CAN_F9R1_FB13_Pos (13U)
7284#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
7285#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
7286#define CAN_F9R1_FB14_Pos (14U)
7287#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
7288#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
7289#define CAN_F9R1_FB15_Pos (15U)
7290#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
7291#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
7292#define CAN_F9R1_FB16_Pos (16U)
7293#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
7294#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
7295#define CAN_F9R1_FB17_Pos (17U)
7296#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
7297#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
7298#define CAN_F9R1_FB18_Pos (18U)
7299#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
7300#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
7301#define CAN_F9R1_FB19_Pos (19U)
7302#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
7303#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
7304#define CAN_F9R1_FB20_Pos (20U)
7305#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
7306#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
7307#define CAN_F9R1_FB21_Pos (21U)
7308#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
7309#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
7310#define CAN_F9R1_FB22_Pos (22U)
7311#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
7312#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
7313#define CAN_F9R1_FB23_Pos (23U)
7314#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
7315#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
7316#define CAN_F9R1_FB24_Pos (24U)
7317#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
7318#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
7319#define CAN_F9R1_FB25_Pos (25U)
7320#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
7321#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
7322#define CAN_F9R1_FB26_Pos (26U)
7323#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
7324#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
7325#define CAN_F9R1_FB27_Pos (27U)
7326#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
7327#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
7328#define CAN_F9R1_FB28_Pos (28U)
7329#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
7330#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
7331#define CAN_F9R1_FB29_Pos (29U)
7332#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
7333#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
7334#define CAN_F9R1_FB30_Pos (30U)
7335#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
7336#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
7337#define CAN_F9R1_FB31_Pos (31U)
7338#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
7339#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
7341/******************* Bit definition for CAN_F10R1 register ******************/
7342#define CAN_F10R1_FB0_Pos (0U)
7343#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
7344#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
7345#define CAN_F10R1_FB1_Pos (1U)
7346#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
7347#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
7348#define CAN_F10R1_FB2_Pos (2U)
7349#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
7350#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
7351#define CAN_F10R1_FB3_Pos (3U)
7352#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
7353#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
7354#define CAN_F10R1_FB4_Pos (4U)
7355#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
7356#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
7357#define CAN_F10R1_FB5_Pos (5U)
7358#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
7359#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
7360#define CAN_F10R1_FB6_Pos (6U)
7361#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
7362#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
7363#define CAN_F10R1_FB7_Pos (7U)
7364#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
7365#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
7366#define CAN_F10R1_FB8_Pos (8U)
7367#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
7368#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
7369#define CAN_F10R1_FB9_Pos (9U)
7370#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
7371#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
7372#define CAN_F10R1_FB10_Pos (10U)
7373#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
7374#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
7375#define CAN_F10R1_FB11_Pos (11U)
7376#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
7377#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
7378#define CAN_F10R1_FB12_Pos (12U)
7379#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
7380#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
7381#define CAN_F10R1_FB13_Pos (13U)
7382#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
7383#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
7384#define CAN_F10R1_FB14_Pos (14U)
7385#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
7386#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
7387#define CAN_F10R1_FB15_Pos (15U)
7388#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
7389#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
7390#define CAN_F10R1_FB16_Pos (16U)
7391#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
7392#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
7393#define CAN_F10R1_FB17_Pos (17U)
7394#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
7395#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
7396#define CAN_F10R1_FB18_Pos (18U)
7397#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
7398#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
7399#define CAN_F10R1_FB19_Pos (19U)
7400#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
7401#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
7402#define CAN_F10R1_FB20_Pos (20U)
7403#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
7404#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
7405#define CAN_F10R1_FB21_Pos (21U)
7406#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
7407#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
7408#define CAN_F10R1_FB22_Pos (22U)
7409#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
7410#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
7411#define CAN_F10R1_FB23_Pos (23U)
7412#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
7413#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
7414#define CAN_F10R1_FB24_Pos (24U)
7415#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
7416#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
7417#define CAN_F10R1_FB25_Pos (25U)
7418#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
7419#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
7420#define CAN_F10R1_FB26_Pos (26U)
7421#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
7422#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
7423#define CAN_F10R1_FB27_Pos (27U)
7424#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
7425#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
7426#define CAN_F10R1_FB28_Pos (28U)
7427#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
7428#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
7429#define CAN_F10R1_FB29_Pos (29U)
7430#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
7431#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
7432#define CAN_F10R1_FB30_Pos (30U)
7433#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
7434#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
7435#define CAN_F10R1_FB31_Pos (31U)
7436#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
7437#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
7439/******************* Bit definition for CAN_F11R1 register ******************/
7440#define CAN_F11R1_FB0_Pos (0U)
7441#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
7442#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
7443#define CAN_F11R1_FB1_Pos (1U)
7444#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
7445#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
7446#define CAN_F11R1_FB2_Pos (2U)
7447#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
7448#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
7449#define CAN_F11R1_FB3_Pos (3U)
7450#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
7451#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
7452#define CAN_F11R1_FB4_Pos (4U)
7453#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
7454#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
7455#define CAN_F11R1_FB5_Pos (5U)
7456#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
7457#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
7458#define CAN_F11R1_FB6_Pos (6U)
7459#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
7460#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
7461#define CAN_F11R1_FB7_Pos (7U)
7462#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
7463#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
7464#define CAN_F11R1_FB8_Pos (8U)
7465#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
7466#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
7467#define CAN_F11R1_FB9_Pos (9U)
7468#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
7469#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
7470#define CAN_F11R1_FB10_Pos (10U)
7471#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
7472#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
7473#define CAN_F11R1_FB11_Pos (11U)
7474#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
7475#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
7476#define CAN_F11R1_FB12_Pos (12U)
7477#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
7478#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
7479#define CAN_F11R1_FB13_Pos (13U)
7480#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
7481#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
7482#define CAN_F11R1_FB14_Pos (14U)
7483#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
7484#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
7485#define CAN_F11R1_FB15_Pos (15U)
7486#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
7487#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
7488#define CAN_F11R1_FB16_Pos (16U)
7489#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
7490#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
7491#define CAN_F11R1_FB17_Pos (17U)
7492#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
7493#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
7494#define CAN_F11R1_FB18_Pos (18U)
7495#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
7496#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
7497#define CAN_F11R1_FB19_Pos (19U)
7498#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
7499#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
7500#define CAN_F11R1_FB20_Pos (20U)
7501#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
7502#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
7503#define CAN_F11R1_FB21_Pos (21U)
7504#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
7505#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
7506#define CAN_F11R1_FB22_Pos (22U)
7507#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
7508#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
7509#define CAN_F11R1_FB23_Pos (23U)
7510#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
7511#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
7512#define CAN_F11R1_FB24_Pos (24U)
7513#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
7514#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
7515#define CAN_F11R1_FB25_Pos (25U)
7516#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
7517#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
7518#define CAN_F11R1_FB26_Pos (26U)
7519#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
7520#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
7521#define CAN_F11R1_FB27_Pos (27U)
7522#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
7523#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
7524#define CAN_F11R1_FB28_Pos (28U)
7525#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
7526#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
7527#define CAN_F11R1_FB29_Pos (29U)
7528#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
7529#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
7530#define CAN_F11R1_FB30_Pos (30U)
7531#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
7532#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
7533#define CAN_F11R1_FB31_Pos (31U)
7534#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
7535#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
7537/******************* Bit definition for CAN_F12R1 register ******************/
7538#define CAN_F12R1_FB0_Pos (0U)
7539#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
7540#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
7541#define CAN_F12R1_FB1_Pos (1U)
7542#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
7543#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
7544#define CAN_F12R1_FB2_Pos (2U)
7545#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
7546#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
7547#define CAN_F12R1_FB3_Pos (3U)
7548#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
7549#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
7550#define CAN_F12R1_FB4_Pos (4U)
7551#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
7552#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
7553#define CAN_F12R1_FB5_Pos (5U)
7554#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
7555#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
7556#define CAN_F12R1_FB6_Pos (6U)
7557#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
7558#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
7559#define CAN_F12R1_FB7_Pos (7U)
7560#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
7561#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
7562#define CAN_F12R1_FB8_Pos (8U)
7563#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
7564#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
7565#define CAN_F12R1_FB9_Pos (9U)
7566#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
7567#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
7568#define CAN_F12R1_FB10_Pos (10U)
7569#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
7570#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
7571#define CAN_F12R1_FB11_Pos (11U)
7572#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
7573#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
7574#define CAN_F12R1_FB12_Pos (12U)
7575#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
7576#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
7577#define CAN_F12R1_FB13_Pos (13U)
7578#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
7579#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
7580#define CAN_F12R1_FB14_Pos (14U)
7581#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
7582#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
7583#define CAN_F12R1_FB15_Pos (15U)
7584#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
7585#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
7586#define CAN_F12R1_FB16_Pos (16U)
7587#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
7588#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
7589#define CAN_F12R1_FB17_Pos (17U)
7590#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
7591#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
7592#define CAN_F12R1_FB18_Pos (18U)
7593#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
7594#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
7595#define CAN_F12R1_FB19_Pos (19U)
7596#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
7597#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
7598#define CAN_F12R1_FB20_Pos (20U)
7599#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
7600#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
7601#define CAN_F12R1_FB21_Pos (21U)
7602#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
7603#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
7604#define CAN_F12R1_FB22_Pos (22U)
7605#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
7606#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
7607#define CAN_F12R1_FB23_Pos (23U)
7608#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
7609#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
7610#define CAN_F12R1_FB24_Pos (24U)
7611#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
7612#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
7613#define CAN_F12R1_FB25_Pos (25U)
7614#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
7615#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
7616#define CAN_F12R1_FB26_Pos (26U)
7617#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
7618#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
7619#define CAN_F12R1_FB27_Pos (27U)
7620#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
7621#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
7622#define CAN_F12R1_FB28_Pos (28U)
7623#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
7624#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
7625#define CAN_F12R1_FB29_Pos (29U)
7626#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
7627#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
7628#define CAN_F12R1_FB30_Pos (30U)
7629#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
7630#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
7631#define CAN_F12R1_FB31_Pos (31U)
7632#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
7633#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
7635/******************* Bit definition for CAN_F13R1 register ******************/
7636#define CAN_F13R1_FB0_Pos (0U)
7637#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
7638#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
7639#define CAN_F13R1_FB1_Pos (1U)
7640#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
7641#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
7642#define CAN_F13R1_FB2_Pos (2U)
7643#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
7644#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
7645#define CAN_F13R1_FB3_Pos (3U)
7646#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
7647#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
7648#define CAN_F13R1_FB4_Pos (4U)
7649#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
7650#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
7651#define CAN_F13R1_FB5_Pos (5U)
7652#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
7653#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
7654#define CAN_F13R1_FB6_Pos (6U)
7655#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
7656#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
7657#define CAN_F13R1_FB7_Pos (7U)
7658#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
7659#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
7660#define CAN_F13R1_FB8_Pos (8U)
7661#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
7662#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
7663#define CAN_F13R1_FB9_Pos (9U)
7664#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
7665#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
7666#define CAN_F13R1_FB10_Pos (10U)
7667#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
7668#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
7669#define CAN_F13R1_FB11_Pos (11U)
7670#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
7671#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
7672#define CAN_F13R1_FB12_Pos (12U)
7673#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
7674#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
7675#define CAN_F13R1_FB13_Pos (13U)
7676#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
7677#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
7678#define CAN_F13R1_FB14_Pos (14U)
7679#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
7680#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
7681#define CAN_F13R1_FB15_Pos (15U)
7682#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
7683#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
7684#define CAN_F13R1_FB16_Pos (16U)
7685#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
7686#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
7687#define CAN_F13R1_FB17_Pos (17U)
7688#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
7689#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
7690#define CAN_F13R1_FB18_Pos (18U)
7691#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
7692#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
7693#define CAN_F13R1_FB19_Pos (19U)
7694#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
7695#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
7696#define CAN_F13R1_FB20_Pos (20U)
7697#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
7698#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
7699#define CAN_F13R1_FB21_Pos (21U)
7700#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
7701#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
7702#define CAN_F13R1_FB22_Pos (22U)
7703#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
7704#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
7705#define CAN_F13R1_FB23_Pos (23U)
7706#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
7707#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
7708#define CAN_F13R1_FB24_Pos (24U)
7709#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
7710#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
7711#define CAN_F13R1_FB25_Pos (25U)
7712#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
7713#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
7714#define CAN_F13R1_FB26_Pos (26U)
7715#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
7716#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
7717#define CAN_F13R1_FB27_Pos (27U)
7718#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
7719#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
7720#define CAN_F13R1_FB28_Pos (28U)
7721#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
7722#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
7723#define CAN_F13R1_FB29_Pos (29U)
7724#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
7725#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
7726#define CAN_F13R1_FB30_Pos (30U)
7727#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
7728#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
7729#define CAN_F13R1_FB31_Pos (31U)
7730#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
7731#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
7733/******************* Bit definition for CAN_F14R1 register ******************/
7734#define CAN_F14R1_FB0_Pos (0U)
7735#define CAN_F14R1_FB0_Msk (0x1UL << CAN_F14R1_FB0_Pos)
7736#define CAN_F14R1_FB0 CAN_F14R1_FB0_Msk
7737#define CAN_F14R1_FB1_Pos (1U)
7738#define CAN_F14R1_FB1_Msk (0x1UL << CAN_F14R1_FB1_Pos)
7739#define CAN_F14R1_FB1 CAN_F14R1_FB1_Msk
7740#define CAN_F14R1_FB2_Pos (2U)
7741#define CAN_F14R1_FB2_Msk (0x1UL << CAN_F14R1_FB2_Pos)
7742#define CAN_F14R1_FB2 CAN_F14R1_FB2_Msk
7743#define CAN_F14R1_FB3_Pos (3U)
7744#define CAN_F14R1_FB3_Msk (0x1UL << CAN_F14R1_FB3_Pos)
7745#define CAN_F14R1_FB3 CAN_F14R1_FB3_Msk
7746#define CAN_F14R1_FB4_Pos (4U)
7747#define CAN_F14R1_FB4_Msk (0x1UL << CAN_F14R1_FB4_Pos)
7748#define CAN_F14R1_FB4 CAN_F14R1_FB4_Msk
7749#define CAN_F14R1_FB5_Pos (5U)
7750#define CAN_F14R1_FB5_Msk (0x1UL << CAN_F14R1_FB5_Pos)
7751#define CAN_F14R1_FB5 CAN_F14R1_FB5_Msk
7752#define CAN_F14R1_FB6_Pos (6U)
7753#define CAN_F14R1_FB6_Msk (0x1UL << CAN_F14R1_FB6_Pos)
7754#define CAN_F14R1_FB6 CAN_F14R1_FB6_Msk
7755#define CAN_F14R1_FB7_Pos (7U)
7756#define CAN_F14R1_FB7_Msk (0x1UL << CAN_F14R1_FB7_Pos)
7757#define CAN_F14R1_FB7 CAN_F14R1_FB7_Msk
7758#define CAN_F14R1_FB8_Pos (8U)
7759#define CAN_F14R1_FB8_Msk (0x1UL << CAN_F14R1_FB8_Pos)
7760#define CAN_F14R1_FB8 CAN_F14R1_FB8_Msk
7761#define CAN_F14R1_FB9_Pos (9U)
7762#define CAN_F14R1_FB9_Msk (0x1UL << CAN_F14R1_FB9_Pos)
7763#define CAN_F14R1_FB9 CAN_F14R1_FB9_Msk
7764#define CAN_F14R1_FB10_Pos (10U)
7765#define CAN_F14R1_FB10_Msk (0x1UL << CAN_F14R1_FB10_Pos)
7766#define CAN_F14R1_FB10 CAN_F14R1_FB10_Msk
7767#define CAN_F14R1_FB11_Pos (11U)
7768#define CAN_F14R1_FB11_Msk (0x1UL << CAN_F14R1_FB11_Pos)
7769#define CAN_F14R1_FB11 CAN_F14R1_FB11_Msk
7770#define CAN_F14R1_FB12_Pos (12U)
7771#define CAN_F14R1_FB12_Msk (0x1UL << CAN_F14R1_FB12_Pos)
7772#define CAN_F14R1_FB12 CAN_F14R1_FB12_Msk
7773#define CAN_F14R1_FB13_Pos (13U)
7774#define CAN_F14R1_FB13_Msk (0x1UL << CAN_F14R1_FB13_Pos)
7775#define CAN_F14R1_FB13 CAN_F14R1_FB13_Msk
7776#define CAN_F14R1_FB14_Pos (14U)
7777#define CAN_F14R1_FB14_Msk (0x1UL << CAN_F14R1_FB14_Pos)
7778#define CAN_F14R1_FB14 CAN_F14R1_FB14_Msk
7779#define CAN_F14R1_FB15_Pos (15U)
7780#define CAN_F14R1_FB15_Msk (0x1UL << CAN_F14R1_FB15_Pos)
7781#define CAN_F14R1_FB15 CAN_F14R1_FB15_Msk
7782#define CAN_F14R1_FB16_Pos (16U)
7783#define CAN_F14R1_FB16_Msk (0x1UL << CAN_F14R1_FB16_Pos)
7784#define CAN_F14R1_FB16 CAN_F14R1_FB16_Msk
7785#define CAN_F14R1_FB17_Pos (17U)
7786#define CAN_F14R1_FB17_Msk (0x1UL << CAN_F14R1_FB17_Pos)
7787#define CAN_F14R1_FB17 CAN_F14R1_FB17_Msk
7788#define CAN_F14R1_FB18_Pos (18U)
7789#define CAN_F14R1_FB18_Msk (0x1UL << CAN_F14R1_FB18_Pos)
7790#define CAN_F14R1_FB18 CAN_F14R1_FB18_Msk
7791#define CAN_F14R1_FB19_Pos (19U)
7792#define CAN_F14R1_FB19_Msk (0x1UL << CAN_F14R1_FB19_Pos)
7793#define CAN_F14R1_FB19 CAN_F14R1_FB19_Msk
7794#define CAN_F14R1_FB20_Pos (20U)
7795#define CAN_F14R1_FB20_Msk (0x1UL << CAN_F14R1_FB20_Pos)
7796#define CAN_F14R1_FB20 CAN_F14R1_FB20_Msk
7797#define CAN_F14R1_FB21_Pos (21U)
7798#define CAN_F14R1_FB21_Msk (0x1UL << CAN_F14R1_FB21_Pos)
7799#define CAN_F14R1_FB21 CAN_F14R1_FB21_Msk
7800#define CAN_F14R1_FB22_Pos (22U)
7801#define CAN_F14R1_FB22_Msk (0x1UL << CAN_F14R1_FB22_Pos)
7802#define CAN_F14R1_FB22 CAN_F14R1_FB22_Msk
7803#define CAN_F14R1_FB23_Pos (23U)
7804#define CAN_F14R1_FB23_Msk (0x1UL << CAN_F14R1_FB23_Pos)
7805#define CAN_F14R1_FB23 CAN_F14R1_FB23_Msk
7806#define CAN_F14R1_FB24_Pos (24U)
7807#define CAN_F14R1_FB24_Msk (0x1UL << CAN_F14R1_FB24_Pos)
7808#define CAN_F14R1_FB24 CAN_F14R1_FB24_Msk
7809#define CAN_F14R1_FB25_Pos (25U)
7810#define CAN_F14R1_FB25_Msk (0x1UL << CAN_F14R1_FB25_Pos)
7811#define CAN_F14R1_FB25 CAN_F14R1_FB25_Msk
7812#define CAN_F14R1_FB26_Pos (26U)
7813#define CAN_F14R1_FB26_Msk (0x1UL << CAN_F14R1_FB26_Pos)
7814#define CAN_F14R1_FB26 CAN_F14R1_FB26_Msk
7815#define CAN_F14R1_FB27_Pos (27U)
7816#define CAN_F14R1_FB27_Msk (0x1UL << CAN_F14R1_FB27_Pos)
7817#define CAN_F14R1_FB27 CAN_F14R1_FB27_Msk
7818#define CAN_F14R1_FB28_Pos (28U)
7819#define CAN_F14R1_FB28_Msk (0x1UL << CAN_F14R1_FB28_Pos)
7820#define CAN_F14R1_FB28 CAN_F14R1_FB28_Msk
7821#define CAN_F14R1_FB29_Pos (29U)
7822#define CAN_F14R1_FB29_Msk (0x1UL << CAN_F14R1_FB29_Pos)
7823#define CAN_F14R1_FB29 CAN_F14R1_FB29_Msk
7824#define CAN_F14R1_FB30_Pos (30U)
7825#define CAN_F14R1_FB30_Msk (0x1UL << CAN_F14R1_FB30_Pos)
7826#define CAN_F14R1_FB30 CAN_F14R1_FB30_Msk
7827#define CAN_F14R1_FB31_Pos (31U)
7828#define CAN_F14R1_FB31_Msk (0x1UL << CAN_F14R1_FB31_Pos)
7829#define CAN_F14R1_FB31 CAN_F14R1_FB31_Msk
7831/******************* Bit definition for CAN_F15R1 register ******************/
7832#define CAN_F15R1_FB0_Pos (0U)
7833#define CAN_F15R1_FB0_Msk (0x1UL << CAN_F15R1_FB0_Pos)
7834#define CAN_F15R1_FB0 CAN_F15R1_FB0_Msk
7835#define CAN_F15R1_FB1_Pos (1U)
7836#define CAN_F15R1_FB1_Msk (0x1UL << CAN_F15R1_FB1_Pos)
7837#define CAN_F15R1_FB1 CAN_F15R1_FB1_Msk
7838#define CAN_F15R1_FB2_Pos (2U)
7839#define CAN_F15R1_FB2_Msk (0x1UL << CAN_F15R1_FB2_Pos)
7840#define CAN_F15R1_FB2 CAN_F15R1_FB2_Msk
7841#define CAN_F15R1_FB3_Pos (3U)
7842#define CAN_F15R1_FB3_Msk (0x1UL << CAN_F15R1_FB3_Pos)
7843#define CAN_F15R1_FB3 CAN_F15R1_FB3_Msk
7844#define CAN_F15R1_FB4_Pos (4U)
7845#define CAN_F15R1_FB4_Msk (0x1UL << CAN_F15R1_FB4_Pos)
7846#define CAN_F15R1_FB4 CAN_F15R1_FB4_Msk
7847#define CAN_F15R1_FB5_Pos (5U)
7848#define CAN_F15R1_FB5_Msk (0x1UL << CAN_F15R1_FB5_Pos)
7849#define CAN_F15R1_FB5 CAN_F15R1_FB5_Msk
7850#define CAN_F15R1_FB6_Pos (6U)
7851#define CAN_F15R1_FB6_Msk (0x1UL << CAN_F15R1_FB6_Pos)
7852#define CAN_F15R1_FB6 CAN_F15R1_FB6_Msk
7853#define CAN_F15R1_FB7_Pos (7U)
7854#define CAN_F15R1_FB7_Msk (0x1UL << CAN_F15R1_FB7_Pos)
7855#define CAN_F15R1_FB7 CAN_F15R1_FB7_Msk
7856#define CAN_F15R1_FB8_Pos (8U)
7857#define CAN_F15R1_FB8_Msk (0x1UL << CAN_F15R1_FB8_Pos)
7858#define CAN_F15R1_FB8 CAN_F15R1_FB8_Msk
7859#define CAN_F15R1_FB9_Pos (9U)
7860#define CAN_F15R1_FB9_Msk (0x1UL << CAN_F15R1_FB9_Pos)
7861#define CAN_F15R1_FB9 CAN_F15R1_FB9_Msk
7862#define CAN_F15R1_FB10_Pos (10U)
7863#define CAN_F15R1_FB10_Msk (0x1UL << CAN_F15R1_FB10_Pos)
7864#define CAN_F15R1_FB10 CAN_F15R1_FB10_Msk
7865#define CAN_F15R1_FB11_Pos (11U)
7866#define CAN_F15R1_FB11_Msk (0x1UL << CAN_F15R1_FB11_Pos)
7867#define CAN_F15R1_FB11 CAN_F15R1_FB11_Msk
7868#define CAN_F15R1_FB12_Pos (12U)
7869#define CAN_F15R1_FB12_Msk (0x1UL << CAN_F15R1_FB12_Pos)
7870#define CAN_F15R1_FB12 CAN_F15R1_FB12_Msk
7871#define CAN_F15R1_FB13_Pos (13U)
7872#define CAN_F15R1_FB13_Msk (0x1UL << CAN_F15R1_FB13_Pos)
7873#define CAN_F15R1_FB13 CAN_F15R1_FB13_Msk
7874#define CAN_F15R1_FB14_Pos (14U)
7875#define CAN_F15R1_FB14_Msk (0x1UL << CAN_F15R1_FB14_Pos)
7876#define CAN_F15R1_FB14 CAN_F15R1_FB14_Msk
7877#define CAN_F15R1_FB15_Pos (15U)
7878#define CAN_F15R1_FB15_Msk (0x1UL << CAN_F15R1_FB15_Pos)
7879#define CAN_F15R1_FB15 CAN_F15R1_FB15_Msk
7880#define CAN_F15R1_FB16_Pos (16U)
7881#define CAN_F15R1_FB16_Msk (0x1UL << CAN_F15R1_FB16_Pos)
7882#define CAN_F15R1_FB16 CAN_F15R1_FB16_Msk
7883#define CAN_F15R1_FB17_Pos (17U)
7884#define CAN_F15R1_FB17_Msk (0x1UL << CAN_F15R1_FB17_Pos)
7885#define CAN_F15R1_FB17 CAN_F15R1_FB17_Msk
7886#define CAN_F15R1_FB18_Pos (18U)
7887#define CAN_F15R1_FB18_Msk (0x1UL << CAN_F15R1_FB18_Pos)
7888#define CAN_F15R1_FB18 CAN_F15R1_FB18_Msk
7889#define CAN_F15R1_FB19_Pos (19U)
7890#define CAN_F15R1_FB19_Msk (0x1UL << CAN_F15R1_FB19_Pos)
7891#define CAN_F15R1_FB19 CAN_F15R1_FB19_Msk
7892#define CAN_F15R1_FB20_Pos (20U)
7893#define CAN_F15R1_FB20_Msk (0x1UL << CAN_F15R1_FB20_Pos)
7894#define CAN_F15R1_FB20 CAN_F15R1_FB20_Msk
7895#define CAN_F15R1_FB21_Pos (21U)
7896#define CAN_F15R1_FB21_Msk (0x1UL << CAN_F15R1_FB21_Pos)
7897#define CAN_F15R1_FB21 CAN_F15R1_FB21_Msk
7898#define CAN_F15R1_FB22_Pos (22U)
7899#define CAN_F15R1_FB22_Msk (0x1UL << CAN_F15R1_FB22_Pos)
7900#define CAN_F15R1_FB22 CAN_F15R1_FB22_Msk
7901#define CAN_F15R1_FB23_Pos (23U)
7902#define CAN_F15R1_FB23_Msk (0x1UL << CAN_F15R1_FB23_Pos)
7903#define CAN_F15R1_FB23 CAN_F15R1_FB23_Msk
7904#define CAN_F15R1_FB24_Pos (24U)
7905#define CAN_F15R1_FB24_Msk (0x1UL << CAN_F15R1_FB24_Pos)
7906#define CAN_F15R1_FB24 CAN_F15R1_FB24_Msk
7907#define CAN_F15R1_FB25_Pos (25U)
7908#define CAN_F15R1_FB25_Msk (0x1UL << CAN_F15R1_FB25_Pos)
7909#define CAN_F15R1_FB25 CAN_F15R1_FB25_Msk
7910#define CAN_F15R1_FB26_Pos (26U)
7911#define CAN_F15R1_FB26_Msk (0x1UL << CAN_F15R1_FB26_Pos)
7912#define CAN_F15R1_FB26 CAN_F15R1_FB26_Msk
7913#define CAN_F15R1_FB27_Pos (27U)
7914#define CAN_F15R1_FB27_Msk (0x1UL << CAN_F15R1_FB27_Pos)
7915#define CAN_F15R1_FB27 CAN_F15R1_FB27_Msk
7916#define CAN_F15R1_FB28_Pos (28U)
7917#define CAN_F15R1_FB28_Msk (0x1UL << CAN_F15R1_FB28_Pos)
7918#define CAN_F15R1_FB28 CAN_F15R1_FB28_Msk
7919#define CAN_F15R1_FB29_Pos (29U)
7920#define CAN_F15R1_FB29_Msk (0x1UL << CAN_F15R1_FB29_Pos)
7921#define CAN_F15R1_FB29 CAN_F15R1_FB29_Msk
7922#define CAN_F15R1_FB30_Pos (30U)
7923#define CAN_F15R1_FB30_Msk (0x1UL << CAN_F15R1_FB30_Pos)
7924#define CAN_F15R1_FB30 CAN_F15R1_FB30_Msk
7925#define CAN_F15R1_FB31_Pos (31U)
7926#define CAN_F15R1_FB31_Msk (0x1UL << CAN_F15R1_FB31_Pos)
7927#define CAN_F15R1_FB31 CAN_F15R1_FB31_Msk
7929/******************* Bit definition for CAN_F16R1 register ******************/
7930#define CAN_F16R1_FB0_Pos (0U)
7931#define CAN_F16R1_FB0_Msk (0x1UL << CAN_F16R1_FB0_Pos)
7932#define CAN_F16R1_FB0 CAN_F16R1_FB0_Msk
7933#define CAN_F16R1_FB1_Pos (1U)
7934#define CAN_F16R1_FB1_Msk (0x1UL << CAN_F16R1_FB1_Pos)
7935#define CAN_F16R1_FB1 CAN_F16R1_FB1_Msk
7936#define CAN_F16R1_FB2_Pos (2U)
7937#define CAN_F16R1_FB2_Msk (0x1UL << CAN_F16R1_FB2_Pos)
7938#define CAN_F16R1_FB2 CAN_F16R1_FB2_Msk
7939#define CAN_F16R1_FB3_Pos (3U)
7940#define CAN_F16R1_FB3_Msk (0x1UL << CAN_F16R1_FB3_Pos)
7941#define CAN_F16R1_FB3 CAN_F16R1_FB3_Msk
7942#define CAN_F16R1_FB4_Pos (4U)
7943#define CAN_F16R1_FB4_Msk (0x1UL << CAN_F16R1_FB4_Pos)
7944#define CAN_F16R1_FB4 CAN_F16R1_FB4_Msk
7945#define CAN_F16R1_FB5_Pos (5U)
7946#define CAN_F16R1_FB5_Msk (0x1UL << CAN_F16R1_FB5_Pos)
7947#define CAN_F16R1_FB5 CAN_F16R1_FB5_Msk
7948#define CAN_F16R1_FB6_Pos (6U)
7949#define CAN_F16R1_FB6_Msk (0x1UL << CAN_F16R1_FB6_Pos)
7950#define CAN_F16R1_FB6 CAN_F16R1_FB6_Msk
7951#define CAN_F16R1_FB7_Pos (7U)
7952#define CAN_F16R1_FB7_Msk (0x1UL << CAN_F16R1_FB7_Pos)
7953#define CAN_F16R1_FB7 CAN_F16R1_FB7_Msk
7954#define CAN_F16R1_FB8_Pos (8U)
7955#define CAN_F16R1_FB8_Msk (0x1UL << CAN_F16R1_FB8_Pos)
7956#define CAN_F16R1_FB8 CAN_F16R1_FB8_Msk
7957#define CAN_F16R1_FB9_Pos (9U)
7958#define CAN_F16R1_FB9_Msk (0x1UL << CAN_F16R1_FB9_Pos)
7959#define CAN_F16R1_FB9 CAN_F16R1_FB9_Msk
7960#define CAN_F16R1_FB10_Pos (10U)
7961#define CAN_F16R1_FB10_Msk (0x1UL << CAN_F16R1_FB10_Pos)
7962#define CAN_F16R1_FB10 CAN_F16R1_FB10_Msk
7963#define CAN_F16R1_FB11_Pos (11U)
7964#define CAN_F16R1_FB11_Msk (0x1UL << CAN_F16R1_FB11_Pos)
7965#define CAN_F16R1_FB11 CAN_F16R1_FB11_Msk
7966#define CAN_F16R1_FB12_Pos (12U)
7967#define CAN_F16R1_FB12_Msk (0x1UL << CAN_F16R1_FB12_Pos)
7968#define CAN_F16R1_FB12 CAN_F16R1_FB12_Msk
7969#define CAN_F16R1_FB13_Pos (13U)
7970#define CAN_F16R1_FB13_Msk (0x1UL << CAN_F16R1_FB13_Pos)
7971#define CAN_F16R1_FB13 CAN_F16R1_FB13_Msk
7972#define CAN_F16R1_FB14_Pos (14U)
7973#define CAN_F16R1_FB14_Msk (0x1UL << CAN_F16R1_FB14_Pos)
7974#define CAN_F16R1_FB14 CAN_F16R1_FB14_Msk
7975#define CAN_F16R1_FB15_Pos (15U)
7976#define CAN_F16R1_FB15_Msk (0x1UL << CAN_F16R1_FB15_Pos)
7977#define CAN_F16R1_FB15 CAN_F16R1_FB15_Msk
7978#define CAN_F16R1_FB16_Pos (16U)
7979#define CAN_F16R1_FB16_Msk (0x1UL << CAN_F16R1_FB16_Pos)
7980#define CAN_F16R1_FB16 CAN_F16R1_FB16_Msk
7981#define CAN_F16R1_FB17_Pos (17U)
7982#define CAN_F16R1_FB17_Msk (0x1UL << CAN_F16R1_FB17_Pos)
7983#define CAN_F16R1_FB17 CAN_F16R1_FB17_Msk
7984#define CAN_F16R1_FB18_Pos (18U)
7985#define CAN_F16R1_FB18_Msk (0x1UL << CAN_F16R1_FB18_Pos)
7986#define CAN_F16R1_FB18 CAN_F16R1_FB18_Msk
7987#define CAN_F16R1_FB19_Pos (19U)
7988#define CAN_F16R1_FB19_Msk (0x1UL << CAN_F16R1_FB19_Pos)
7989#define CAN_F16R1_FB19 CAN_F16R1_FB19_Msk
7990#define CAN_F16R1_FB20_Pos (20U)
7991#define CAN_F16R1_FB20_Msk (0x1UL << CAN_F16R1_FB20_Pos)
7992#define CAN_F16R1_FB20 CAN_F16R1_FB20_Msk
7993#define CAN_F16R1_FB21_Pos (21U)
7994#define CAN_F16R1_FB21_Msk (0x1UL << CAN_F16R1_FB21_Pos)
7995#define CAN_F16R1_FB21 CAN_F16R1_FB21_Msk
7996#define CAN_F16R1_FB22_Pos (22U)
7997#define CAN_F16R1_FB22_Msk (0x1UL << CAN_F16R1_FB22_Pos)
7998#define CAN_F16R1_FB22 CAN_F16R1_FB22_Msk
7999#define CAN_F16R1_FB23_Pos (23U)
8000#define CAN_F16R1_FB23_Msk (0x1UL << CAN_F16R1_FB23_Pos)
8001#define CAN_F16R1_FB23 CAN_F16R1_FB23_Msk
8002#define CAN_F16R1_FB24_Pos (24U)
8003#define CAN_F16R1_FB24_Msk (0x1UL << CAN_F16R1_FB24_Pos)
8004#define CAN_F16R1_FB24 CAN_F16R1_FB24_Msk
8005#define CAN_F16R1_FB25_Pos (25U)
8006#define CAN_F16R1_FB25_Msk (0x1UL << CAN_F16R1_FB25_Pos)
8007#define CAN_F16R1_FB25 CAN_F16R1_FB25_Msk
8008#define CAN_F16R1_FB26_Pos (26U)
8009#define CAN_F16R1_FB26_Msk (0x1UL << CAN_F16R1_FB26_Pos)
8010#define CAN_F16R1_FB26 CAN_F16R1_FB26_Msk
8011#define CAN_F16R1_FB27_Pos (27U)
8012#define CAN_F16R1_FB27_Msk (0x1UL << CAN_F16R1_FB27_Pos)
8013#define CAN_F16R1_FB27 CAN_F16R1_FB27_Msk
8014#define CAN_F16R1_FB28_Pos (28U)
8015#define CAN_F16R1_FB28_Msk (0x1UL << CAN_F16R1_FB28_Pos)
8016#define CAN_F16R1_FB28 CAN_F16R1_FB28_Msk
8017#define CAN_F16R1_FB29_Pos (29U)
8018#define CAN_F16R1_FB29_Msk (0x1UL << CAN_F16R1_FB29_Pos)
8019#define CAN_F16R1_FB29 CAN_F16R1_FB29_Msk
8020#define CAN_F16R1_FB30_Pos (30U)
8021#define CAN_F16R1_FB30_Msk (0x1UL << CAN_F16R1_FB30_Pos)
8022#define CAN_F16R1_FB30 CAN_F16R1_FB30_Msk
8023#define CAN_F16R1_FB31_Pos (31U)
8024#define CAN_F16R1_FB31_Msk (0x1UL << CAN_F16R1_FB31_Pos)
8025#define CAN_F16R1_FB31 CAN_F16R1_FB31_Msk
8027/******************* Bit definition for CAN_F17R1 register ******************/
8028#define CAN_F17R1_FB0_Pos (0U)
8029#define CAN_F17R1_FB0_Msk (0x1UL << CAN_F17R1_FB0_Pos)
8030#define CAN_F17R1_FB0 CAN_F17R1_FB0_Msk
8031#define CAN_F17R1_FB1_Pos (1U)
8032#define CAN_F17R1_FB1_Msk (0x1UL << CAN_F17R1_FB1_Pos)
8033#define CAN_F17R1_FB1 CAN_F17R1_FB1_Msk
8034#define CAN_F17R1_FB2_Pos (2U)
8035#define CAN_F17R1_FB2_Msk (0x1UL << CAN_F17R1_FB2_Pos)
8036#define CAN_F17R1_FB2 CAN_F17R1_FB2_Msk
8037#define CAN_F17R1_FB3_Pos (3U)
8038#define CAN_F17R1_FB3_Msk (0x1UL << CAN_F17R1_FB3_Pos)
8039#define CAN_F17R1_FB3 CAN_F17R1_FB3_Msk
8040#define CAN_F17R1_FB4_Pos (4U)
8041#define CAN_F17R1_FB4_Msk (0x1UL << CAN_F17R1_FB4_Pos)
8042#define CAN_F17R1_FB4 CAN_F17R1_FB4_Msk
8043#define CAN_F17R1_FB5_Pos (5U)
8044#define CAN_F17R1_FB5_Msk (0x1UL << CAN_F17R1_FB5_Pos)
8045#define CAN_F17R1_FB5 CAN_F17R1_FB5_Msk
8046#define CAN_F17R1_FB6_Pos (6U)
8047#define CAN_F17R1_FB6_Msk (0x1UL << CAN_F17R1_FB6_Pos)
8048#define CAN_F17R1_FB6 CAN_F17R1_FB6_Msk
8049#define CAN_F17R1_FB7_Pos (7U)
8050#define CAN_F17R1_FB7_Msk (0x1UL << CAN_F17R1_FB7_Pos)
8051#define CAN_F17R1_FB7 CAN_F17R1_FB7_Msk
8052#define CAN_F17R1_FB8_Pos (8U)
8053#define CAN_F17R1_FB8_Msk (0x1UL << CAN_F17R1_FB8_Pos)
8054#define CAN_F17R1_FB8 CAN_F17R1_FB8_Msk
8055#define CAN_F17R1_FB9_Pos (9U)
8056#define CAN_F17R1_FB9_Msk (0x1UL << CAN_F17R1_FB9_Pos)
8057#define CAN_F17R1_FB9 CAN_F17R1_FB9_Msk
8058#define CAN_F17R1_FB10_Pos (10U)
8059#define CAN_F17R1_FB10_Msk (0x1UL << CAN_F17R1_FB10_Pos)
8060#define CAN_F17R1_FB10 CAN_F17R1_FB10_Msk
8061#define CAN_F17R1_FB11_Pos (11U)
8062#define CAN_F17R1_FB11_Msk (0x1UL << CAN_F17R1_FB11_Pos)
8063#define CAN_F17R1_FB11 CAN_F17R1_FB11_Msk
8064#define CAN_F17R1_FB12_Pos (12U)
8065#define CAN_F17R1_FB12_Msk (0x1UL << CAN_F17R1_FB12_Pos)
8066#define CAN_F17R1_FB12 CAN_F17R1_FB12_Msk
8067#define CAN_F17R1_FB13_Pos (13U)
8068#define CAN_F17R1_FB13_Msk (0x1UL << CAN_F17R1_FB13_Pos)
8069#define CAN_F17R1_FB13 CAN_F17R1_FB13_Msk
8070#define CAN_F17R1_FB14_Pos (14U)
8071#define CAN_F17R1_FB14_Msk (0x1UL << CAN_F17R1_FB14_Pos)
8072#define CAN_F17R1_FB14 CAN_F17R1_FB14_Msk
8073#define CAN_F17R1_FB15_Pos (15U)
8074#define CAN_F17R1_FB15_Msk (0x1UL << CAN_F17R1_FB15_Pos)
8075#define CAN_F17R1_FB15 CAN_F17R1_FB15_Msk
8076#define CAN_F17R1_FB16_Pos (16U)
8077#define CAN_F17R1_FB16_Msk (0x1UL << CAN_F17R1_FB16_Pos)
8078#define CAN_F17R1_FB16 CAN_F17R1_FB16_Msk
8079#define CAN_F17R1_FB17_Pos (17U)
8080#define CAN_F17R1_FB17_Msk (0x1UL << CAN_F17R1_FB17_Pos)
8081#define CAN_F17R1_FB17 CAN_F17R1_FB17_Msk
8082#define CAN_F17R1_FB18_Pos (18U)
8083#define CAN_F17R1_FB18_Msk (0x1UL << CAN_F17R1_FB18_Pos)
8084#define CAN_F17R1_FB18 CAN_F17R1_FB18_Msk
8085#define CAN_F17R1_FB19_Pos (19U)
8086#define CAN_F17R1_FB19_Msk (0x1UL << CAN_F17R1_FB19_Pos)
8087#define CAN_F17R1_FB19 CAN_F17R1_FB19_Msk
8088#define CAN_F17R1_FB20_Pos (20U)
8089#define CAN_F17R1_FB20_Msk (0x1UL << CAN_F17R1_FB20_Pos)
8090#define CAN_F17R1_FB20 CAN_F17R1_FB20_Msk
8091#define CAN_F17R1_FB21_Pos (21U)
8092#define CAN_F17R1_FB21_Msk (0x1UL << CAN_F17R1_FB21_Pos)
8093#define CAN_F17R1_FB21 CAN_F17R1_FB21_Msk
8094#define CAN_F17R1_FB22_Pos (22U)
8095#define CAN_F17R1_FB22_Msk (0x1UL << CAN_F17R1_FB22_Pos)
8096#define CAN_F17R1_FB22 CAN_F17R1_FB22_Msk
8097#define CAN_F17R1_FB23_Pos (23U)
8098#define CAN_F17R1_FB23_Msk (0x1UL << CAN_F17R1_FB23_Pos)
8099#define CAN_F17R1_FB23 CAN_F17R1_FB23_Msk
8100#define CAN_F17R1_FB24_Pos (24U)
8101#define CAN_F17R1_FB24_Msk (0x1UL << CAN_F17R1_FB24_Pos)
8102#define CAN_F17R1_FB24 CAN_F17R1_FB24_Msk
8103#define CAN_F17R1_FB25_Pos (25U)
8104#define CAN_F17R1_FB25_Msk (0x1UL << CAN_F17R1_FB25_Pos)
8105#define CAN_F17R1_FB25 CAN_F17R1_FB25_Msk
8106#define CAN_F17R1_FB26_Pos (26U)
8107#define CAN_F17R1_FB26_Msk (0x1UL << CAN_F17R1_FB26_Pos)
8108#define CAN_F17R1_FB26 CAN_F17R1_FB26_Msk
8109#define CAN_F17R1_FB27_Pos (27U)
8110#define CAN_F17R1_FB27_Msk (0x1UL << CAN_F17R1_FB27_Pos)
8111#define CAN_F17R1_FB27 CAN_F17R1_FB27_Msk
8112#define CAN_F17R1_FB28_Pos (28U)
8113#define CAN_F17R1_FB28_Msk (0x1UL << CAN_F17R1_FB28_Pos)
8114#define CAN_F17R1_FB28 CAN_F17R1_FB28_Msk
8115#define CAN_F17R1_FB29_Pos (29U)
8116#define CAN_F17R1_FB29_Msk (0x1UL << CAN_F17R1_FB29_Pos)
8117#define CAN_F17R1_FB29 CAN_F17R1_FB29_Msk
8118#define CAN_F17R1_FB30_Pos (30U)
8119#define CAN_F17R1_FB30_Msk (0x1UL << CAN_F17R1_FB30_Pos)
8120#define CAN_F17R1_FB30 CAN_F17R1_FB30_Msk
8121#define CAN_F17R1_FB31_Pos (31U)
8122#define CAN_F17R1_FB31_Msk (0x1UL << CAN_F17R1_FB31_Pos)
8123#define CAN_F17R1_FB31 CAN_F17R1_FB31_Msk
8125/******************* Bit definition for CAN_F18R1 register ******************/
8126#define CAN_F18R1_FB0_Pos (0U)
8127#define CAN_F18R1_FB0_Msk (0x1UL << CAN_F18R1_FB0_Pos)
8128#define CAN_F18R1_FB0 CAN_F18R1_FB0_Msk
8129#define CAN_F18R1_FB1_Pos (1U)
8130#define CAN_F18R1_FB1_Msk (0x1UL << CAN_F18R1_FB1_Pos)
8131#define CAN_F18R1_FB1 CAN_F18R1_FB1_Msk
8132#define CAN_F18R1_FB2_Pos (2U)
8133#define CAN_F18R1_FB2_Msk (0x1UL << CAN_F18R1_FB2_Pos)
8134#define CAN_F18R1_FB2 CAN_F18R1_FB2_Msk
8135#define CAN_F18R1_FB3_Pos (3U)
8136#define CAN_F18R1_FB3_Msk (0x1UL << CAN_F18R1_FB3_Pos)
8137#define CAN_F18R1_FB3 CAN_F18R1_FB3_Msk
8138#define CAN_F18R1_FB4_Pos (4U)
8139#define CAN_F18R1_FB4_Msk (0x1UL << CAN_F18R1_FB4_Pos)
8140#define CAN_F18R1_FB4 CAN_F18R1_FB4_Msk
8141#define CAN_F18R1_FB5_Pos (5U)
8142#define CAN_F18R1_FB5_Msk (0x1UL << CAN_F18R1_FB5_Pos)
8143#define CAN_F18R1_FB5 CAN_F18R1_FB5_Msk
8144#define CAN_F18R1_FB6_Pos (6U)
8145#define CAN_F18R1_FB6_Msk (0x1UL << CAN_F18R1_FB6_Pos)
8146#define CAN_F18R1_FB6 CAN_F18R1_FB6_Msk
8147#define CAN_F18R1_FB7_Pos (7U)
8148#define CAN_F18R1_FB7_Msk (0x1UL << CAN_F18R1_FB7_Pos)
8149#define CAN_F18R1_FB7 CAN_F18R1_FB7_Msk
8150#define CAN_F18R1_FB8_Pos (8U)
8151#define CAN_F18R1_FB8_Msk (0x1UL << CAN_F18R1_FB8_Pos)
8152#define CAN_F18R1_FB8 CAN_F18R1_FB8_Msk
8153#define CAN_F18R1_FB9_Pos (9U)
8154#define CAN_F18R1_FB9_Msk (0x1UL << CAN_F18R1_FB9_Pos)
8155#define CAN_F18R1_FB9 CAN_F18R1_FB9_Msk
8156#define CAN_F18R1_FB10_Pos (10U)
8157#define CAN_F18R1_FB10_Msk (0x1UL << CAN_F18R1_FB10_Pos)
8158#define CAN_F18R1_FB10 CAN_F18R1_FB10_Msk
8159#define CAN_F18R1_FB11_Pos (11U)
8160#define CAN_F18R1_FB11_Msk (0x1UL << CAN_F18R1_FB11_Pos)
8161#define CAN_F18R1_FB11 CAN_F18R1_FB11_Msk
8162#define CAN_F18R1_FB12_Pos (12U)
8163#define CAN_F18R1_FB12_Msk (0x1UL << CAN_F18R1_FB12_Pos)
8164#define CAN_F18R1_FB12 CAN_F18R1_FB12_Msk
8165#define CAN_F18R1_FB13_Pos (13U)
8166#define CAN_F18R1_FB13_Msk (0x1UL << CAN_F18R1_FB13_Pos)
8167#define CAN_F18R1_FB13 CAN_F18R1_FB13_Msk
8168#define CAN_F18R1_FB14_Pos (14U)
8169#define CAN_F18R1_FB14_Msk (0x1UL << CAN_F18R1_FB14_Pos)
8170#define CAN_F18R1_FB14 CAN_F18R1_FB14_Msk
8171#define CAN_F18R1_FB15_Pos (15U)
8172#define CAN_F18R1_FB15_Msk (0x1UL << CAN_F18R1_FB15_Pos)
8173#define CAN_F18R1_FB15 CAN_F18R1_FB15_Msk
8174#define CAN_F18R1_FB16_Pos (16U)
8175#define CAN_F18R1_FB16_Msk (0x1UL << CAN_F18R1_FB16_Pos)
8176#define CAN_F18R1_FB16 CAN_F18R1_FB16_Msk
8177#define CAN_F18R1_FB17_Pos (17U)
8178#define CAN_F18R1_FB17_Msk (0x1UL << CAN_F18R1_FB17_Pos)
8179#define CAN_F18R1_FB17 CAN_F18R1_FB17_Msk
8180#define CAN_F18R1_FB18_Pos (18U)
8181#define CAN_F18R1_FB18_Msk (0x1UL << CAN_F18R1_FB18_Pos)
8182#define CAN_F18R1_FB18 CAN_F18R1_FB18_Msk
8183#define CAN_F18R1_FB19_Pos (19U)
8184#define CAN_F18R1_FB19_Msk (0x1UL << CAN_F18R1_FB19_Pos)
8185#define CAN_F18R1_FB19 CAN_F18R1_FB19_Msk
8186#define CAN_F18R1_FB20_Pos (20U)
8187#define CAN_F18R1_FB20_Msk (0x1UL << CAN_F18R1_FB20_Pos)
8188#define CAN_F18R1_FB20 CAN_F18R1_FB20_Msk
8189#define CAN_F18R1_FB21_Pos (21U)
8190#define CAN_F18R1_FB21_Msk (0x1UL << CAN_F18R1_FB21_Pos)
8191#define CAN_F18R1_FB21 CAN_F18R1_FB21_Msk
8192#define CAN_F18R1_FB22_Pos (22U)
8193#define CAN_F18R1_FB22_Msk (0x1UL << CAN_F18R1_FB22_Pos)
8194#define CAN_F18R1_FB22 CAN_F18R1_FB22_Msk
8195#define CAN_F18R1_FB23_Pos (23U)
8196#define CAN_F18R1_FB23_Msk (0x1UL << CAN_F18R1_FB23_Pos)
8197#define CAN_F18R1_FB23 CAN_F18R1_FB23_Msk
8198#define CAN_F18R1_FB24_Pos (24U)
8199#define CAN_F18R1_FB24_Msk (0x1UL << CAN_F18R1_FB24_Pos)
8200#define CAN_F18R1_FB24 CAN_F18R1_FB24_Msk
8201#define CAN_F18R1_FB25_Pos (25U)
8202#define CAN_F18R1_FB25_Msk (0x1UL << CAN_F18R1_FB25_Pos)
8203#define CAN_F18R1_FB25 CAN_F18R1_FB25_Msk
8204#define CAN_F18R1_FB26_Pos (26U)
8205#define CAN_F18R1_FB26_Msk (0x1UL << CAN_F18R1_FB26_Pos)
8206#define CAN_F18R1_FB26 CAN_F18R1_FB26_Msk
8207#define CAN_F18R1_FB27_Pos (27U)
8208#define CAN_F18R1_FB27_Msk (0x1UL << CAN_F18R1_FB27_Pos)
8209#define CAN_F18R1_FB27 CAN_F18R1_FB27_Msk
8210#define CAN_F18R1_FB28_Pos (28U)
8211#define CAN_F18R1_FB28_Msk (0x1UL << CAN_F18R1_FB28_Pos)
8212#define CAN_F18R1_FB28 CAN_F18R1_FB28_Msk
8213#define CAN_F18R1_FB29_Pos (29U)
8214#define CAN_F18R1_FB29_Msk (0x1UL << CAN_F18R1_FB29_Pos)
8215#define CAN_F18R1_FB29 CAN_F18R1_FB29_Msk
8216#define CAN_F18R1_FB30_Pos (30U)
8217#define CAN_F18R1_FB30_Msk (0x1UL << CAN_F18R1_FB30_Pos)
8218#define CAN_F18R1_FB30 CAN_F18R1_FB30_Msk
8219#define CAN_F18R1_FB31_Pos (31U)
8220#define CAN_F18R1_FB31_Msk (0x1UL << CAN_F18R1_FB31_Pos)
8221#define CAN_F18R1_FB31 CAN_F18R1_FB31_Msk
8223/******************* Bit definition for CAN_F19R1 register ******************/
8224#define CAN_F19R1_FB0_Pos (0U)
8225#define CAN_F19R1_FB0_Msk (0x1UL << CAN_F19R1_FB0_Pos)
8226#define CAN_F19R1_FB0 CAN_F19R1_FB0_Msk
8227#define CAN_F19R1_FB1_Pos (1U)
8228#define CAN_F19R1_FB1_Msk (0x1UL << CAN_F19R1_FB1_Pos)
8229#define CAN_F19R1_FB1 CAN_F19R1_FB1_Msk
8230#define CAN_F19R1_FB2_Pos (2U)
8231#define CAN_F19R1_FB2_Msk (0x1UL << CAN_F19R1_FB2_Pos)
8232#define CAN_F19R1_FB2 CAN_F19R1_FB2_Msk
8233#define CAN_F19R1_FB3_Pos (3U)
8234#define CAN_F19R1_FB3_Msk (0x1UL << CAN_F19R1_FB3_Pos)
8235#define CAN_F19R1_FB3 CAN_F19R1_FB3_Msk
8236#define CAN_F19R1_FB4_Pos (4U)
8237#define CAN_F19R1_FB4_Msk (0x1UL << CAN_F19R1_FB4_Pos)
8238#define CAN_F19R1_FB4 CAN_F19R1_FB4_Msk
8239#define CAN_F19R1_FB5_Pos (5U)
8240#define CAN_F19R1_FB5_Msk (0x1UL << CAN_F19R1_FB5_Pos)
8241#define CAN_F19R1_FB5 CAN_F19R1_FB5_Msk
8242#define CAN_F19R1_FB6_Pos (6U)
8243#define CAN_F19R1_FB6_Msk (0x1UL << CAN_F19R1_FB6_Pos)
8244#define CAN_F19R1_FB6 CAN_F19R1_FB6_Msk
8245#define CAN_F19R1_FB7_Pos (7U)
8246#define CAN_F19R1_FB7_Msk (0x1UL << CAN_F19R1_FB7_Pos)
8247#define CAN_F19R1_FB7 CAN_F19R1_FB7_Msk
8248#define CAN_F19R1_FB8_Pos (8U)
8249#define CAN_F19R1_FB8_Msk (0x1UL << CAN_F19R1_FB8_Pos)
8250#define CAN_F19R1_FB8 CAN_F19R1_FB8_Msk
8251#define CAN_F19R1_FB9_Pos (9U)
8252#define CAN_F19R1_FB9_Msk (0x1UL << CAN_F19R1_FB9_Pos)
8253#define CAN_F19R1_FB9 CAN_F19R1_FB9_Msk
8254#define CAN_F19R1_FB10_Pos (10U)
8255#define CAN_F19R1_FB10_Msk (0x1UL << CAN_F19R1_FB10_Pos)
8256#define CAN_F19R1_FB10 CAN_F19R1_FB10_Msk
8257#define CAN_F19R1_FB11_Pos (11U)
8258#define CAN_F19R1_FB11_Msk (0x1UL << CAN_F19R1_FB11_Pos)
8259#define CAN_F19R1_FB11 CAN_F19R1_FB11_Msk
8260#define CAN_F19R1_FB12_Pos (12U)
8261#define CAN_F19R1_FB12_Msk (0x1UL << CAN_F19R1_FB12_Pos)
8262#define CAN_F19R1_FB12 CAN_F19R1_FB12_Msk
8263#define CAN_F19R1_FB13_Pos (13U)
8264#define CAN_F19R1_FB13_Msk (0x1UL << CAN_F19R1_FB13_Pos)
8265#define CAN_F19R1_FB13 CAN_F19R1_FB13_Msk
8266#define CAN_F19R1_FB14_Pos (14U)
8267#define CAN_F19R1_FB14_Msk (0x1UL << CAN_F19R1_FB14_Pos)
8268#define CAN_F19R1_FB14 CAN_F19R1_FB14_Msk
8269#define CAN_F19R1_FB15_Pos (15U)
8270#define CAN_F19R1_FB15_Msk (0x1UL << CAN_F19R1_FB15_Pos)
8271#define CAN_F19R1_FB15 CAN_F19R1_FB15_Msk
8272#define CAN_F19R1_FB16_Pos (16U)
8273#define CAN_F19R1_FB16_Msk (0x1UL << CAN_F19R1_FB16_Pos)
8274#define CAN_F19R1_FB16 CAN_F19R1_FB16_Msk
8275#define CAN_F19R1_FB17_Pos (17U)
8276#define CAN_F19R1_FB17_Msk (0x1UL << CAN_F19R1_FB17_Pos)
8277#define CAN_F19R1_FB17 CAN_F19R1_FB17_Msk
8278#define CAN_F19R1_FB18_Pos (18U)
8279#define CAN_F19R1_FB18_Msk (0x1UL << CAN_F19R1_FB18_Pos)
8280#define CAN_F19R1_FB18 CAN_F19R1_FB18_Msk
8281#define CAN_F19R1_FB19_Pos (19U)
8282#define CAN_F19R1_FB19_Msk (0x1UL << CAN_F19R1_FB19_Pos)
8283#define CAN_F19R1_FB19 CAN_F19R1_FB19_Msk
8284#define CAN_F19R1_FB20_Pos (20U)
8285#define CAN_F19R1_FB20_Msk (0x1UL << CAN_F19R1_FB20_Pos)
8286#define CAN_F19R1_FB20 CAN_F19R1_FB20_Msk
8287#define CAN_F19R1_FB21_Pos (21U)
8288#define CAN_F19R1_FB21_Msk (0x1UL << CAN_F19R1_FB21_Pos)
8289#define CAN_F19R1_FB21 CAN_F19R1_FB21_Msk
8290#define CAN_F19R1_FB22_Pos (22U)
8291#define CAN_F19R1_FB22_Msk (0x1UL << CAN_F19R1_FB22_Pos)
8292#define CAN_F19R1_FB22 CAN_F19R1_FB22_Msk
8293#define CAN_F19R1_FB23_Pos (23U)
8294#define CAN_F19R1_FB23_Msk (0x1UL << CAN_F19R1_FB23_Pos)
8295#define CAN_F19R1_FB23 CAN_F19R1_FB23_Msk
8296#define CAN_F19R1_FB24_Pos (24U)
8297#define CAN_F19R1_FB24_Msk (0x1UL << CAN_F19R1_FB24_Pos)
8298#define CAN_F19R1_FB24 CAN_F19R1_FB24_Msk
8299#define CAN_F19R1_FB25_Pos (25U)
8300#define CAN_F19R1_FB25_Msk (0x1UL << CAN_F19R1_FB25_Pos)
8301#define CAN_F19R1_FB25 CAN_F19R1_FB25_Msk
8302#define CAN_F19R1_FB26_Pos (26U)
8303#define CAN_F19R1_FB26_Msk (0x1UL << CAN_F19R1_FB26_Pos)
8304#define CAN_F19R1_FB26 CAN_F19R1_FB26_Msk
8305#define CAN_F19R1_FB27_Pos (27U)
8306#define CAN_F19R1_FB27_Msk (0x1UL << CAN_F19R1_FB27_Pos)
8307#define CAN_F19R1_FB27 CAN_F19R1_FB27_Msk
8308#define CAN_F19R1_FB28_Pos (28U)
8309#define CAN_F19R1_FB28_Msk (0x1UL << CAN_F19R1_FB28_Pos)
8310#define CAN_F19R1_FB28 CAN_F19R1_FB28_Msk
8311#define CAN_F19R1_FB29_Pos (29U)
8312#define CAN_F19R1_FB29_Msk (0x1UL << CAN_F19R1_FB29_Pos)
8313#define CAN_F19R1_FB29 CAN_F19R1_FB29_Msk
8314#define CAN_F19R1_FB30_Pos (30U)
8315#define CAN_F19R1_FB30_Msk (0x1UL << CAN_F19R1_FB30_Pos)
8316#define CAN_F19R1_FB30 CAN_F19R1_FB30_Msk
8317#define CAN_F19R1_FB31_Pos (31U)
8318#define CAN_F19R1_FB31_Msk (0x1UL << CAN_F19R1_FB31_Pos)
8319#define CAN_F19R1_FB31 CAN_F19R1_FB31_Msk
8321/******************* Bit definition for CAN_F20R1 register ******************/
8322#define CAN_F20R1_FB0_Pos (0U)
8323#define CAN_F20R1_FB0_Msk (0x1UL << CAN_F20R1_FB0_Pos)
8324#define CAN_F20R1_FB0 CAN_F20R1_FB0_Msk
8325#define CAN_F20R1_FB1_Pos (1U)
8326#define CAN_F20R1_FB1_Msk (0x1UL << CAN_F20R1_FB1_Pos)
8327#define CAN_F20R1_FB1 CAN_F20R1_FB1_Msk
8328#define CAN_F20R1_FB2_Pos (2U)
8329#define CAN_F20R1_FB2_Msk (0x1UL << CAN_F20R1_FB2_Pos)
8330#define CAN_F20R1_FB2 CAN_F20R1_FB2_Msk
8331#define CAN_F20R1_FB3_Pos (3U)
8332#define CAN_F20R1_FB3_Msk (0x1UL << CAN_F20R1_FB3_Pos)
8333#define CAN_F20R1_FB3 CAN_F20R1_FB3_Msk
8334#define CAN_F20R1_FB4_Pos (4U)
8335#define CAN_F20R1_FB4_Msk (0x1UL << CAN_F20R1_FB4_Pos)
8336#define CAN_F20R1_FB4 CAN_F20R1_FB4_Msk
8337#define CAN_F20R1_FB5_Pos (5U)
8338#define CAN_F20R1_FB5_Msk (0x1UL << CAN_F20R1_FB5_Pos)
8339#define CAN_F20R1_FB5 CAN_F20R1_FB5_Msk
8340#define CAN_F20R1_FB6_Pos (6U)
8341#define CAN_F20R1_FB6_Msk (0x1UL << CAN_F20R1_FB6_Pos)
8342#define CAN_F20R1_FB6 CAN_F20R1_FB6_Msk
8343#define CAN_F20R1_FB7_Pos (7U)
8344#define CAN_F20R1_FB7_Msk (0x1UL << CAN_F20R1_FB7_Pos)
8345#define CAN_F20R1_FB7 CAN_F20R1_FB7_Msk
8346#define CAN_F20R1_FB8_Pos (8U)
8347#define CAN_F20R1_FB8_Msk (0x1UL << CAN_F20R1_FB8_Pos)
8348#define CAN_F20R1_FB8 CAN_F20R1_FB8_Msk
8349#define CAN_F20R1_FB9_Pos (9U)
8350#define CAN_F20R1_FB9_Msk (0x1UL << CAN_F20R1_FB9_Pos)
8351#define CAN_F20R1_FB9 CAN_F20R1_FB9_Msk
8352#define CAN_F20R1_FB10_Pos (10U)
8353#define CAN_F20R1_FB10_Msk (0x1UL << CAN_F20R1_FB10_Pos)
8354#define CAN_F20R1_FB10 CAN_F20R1_FB10_Msk
8355#define CAN_F20R1_FB11_Pos (11U)
8356#define CAN_F20R1_FB11_Msk (0x1UL << CAN_F20R1_FB11_Pos)
8357#define CAN_F20R1_FB11 CAN_F20R1_FB11_Msk
8358#define CAN_F20R1_FB12_Pos (12U)
8359#define CAN_F20R1_FB12_Msk (0x1UL << CAN_F20R1_FB12_Pos)
8360#define CAN_F20R1_FB12 CAN_F20R1_FB12_Msk
8361#define CAN_F20R1_FB13_Pos (13U)
8362#define CAN_F20R1_FB13_Msk (0x1UL << CAN_F20R1_FB13_Pos)
8363#define CAN_F20R1_FB13 CAN_F20R1_FB13_Msk
8364#define CAN_F20R1_FB14_Pos (14U)
8365#define CAN_F20R1_FB14_Msk (0x1UL << CAN_F20R1_FB14_Pos)
8366#define CAN_F20R1_FB14 CAN_F20R1_FB14_Msk
8367#define CAN_F20R1_FB15_Pos (15U)
8368#define CAN_F20R1_FB15_Msk (0x1UL << CAN_F20R1_FB15_Pos)
8369#define CAN_F20R1_FB15 CAN_F20R1_FB15_Msk
8370#define CAN_F20R1_FB16_Pos (16U)
8371#define CAN_F20R1_FB16_Msk (0x1UL << CAN_F20R1_FB16_Pos)
8372#define CAN_F20R1_FB16 CAN_F20R1_FB16_Msk
8373#define CAN_F20R1_FB17_Pos (17U)
8374#define CAN_F20R1_FB17_Msk (0x1UL << CAN_F20R1_FB17_Pos)
8375#define CAN_F20R1_FB17 CAN_F20R1_FB17_Msk
8376#define CAN_F20R1_FB18_Pos (18U)
8377#define CAN_F20R1_FB18_Msk (0x1UL << CAN_F20R1_FB18_Pos)
8378#define CAN_F20R1_FB18 CAN_F20R1_FB18_Msk
8379#define CAN_F20R1_FB19_Pos (19U)
8380#define CAN_F20R1_FB19_Msk (0x1UL << CAN_F20R1_FB19_Pos)
8381#define CAN_F20R1_FB19 CAN_F20R1_FB19_Msk
8382#define CAN_F20R1_FB20_Pos (20U)
8383#define CAN_F20R1_FB20_Msk (0x1UL << CAN_F20R1_FB20_Pos)
8384#define CAN_F20R1_FB20 CAN_F20R1_FB20_Msk
8385#define CAN_F20R1_FB21_Pos (21U)
8386#define CAN_F20R1_FB21_Msk (0x1UL << CAN_F20R1_FB21_Pos)
8387#define CAN_F20R1_FB21 CAN_F20R1_FB21_Msk
8388#define CAN_F20R1_FB22_Pos (22U)
8389#define CAN_F20R1_FB22_Msk (0x1UL << CAN_F20R1_FB22_Pos)
8390#define CAN_F20R1_FB22 CAN_F20R1_FB22_Msk
8391#define CAN_F20R1_FB23_Pos (23U)
8392#define CAN_F20R1_FB23_Msk (0x1UL << CAN_F20R1_FB23_Pos)
8393#define CAN_F20R1_FB23 CAN_F20R1_FB23_Msk
8394#define CAN_F20R1_FB24_Pos (24U)
8395#define CAN_F20R1_FB24_Msk (0x1UL << CAN_F20R1_FB24_Pos)
8396#define CAN_F20R1_FB24 CAN_F20R1_FB24_Msk
8397#define CAN_F20R1_FB25_Pos (25U)
8398#define CAN_F20R1_FB25_Msk (0x1UL << CAN_F20R1_FB25_Pos)
8399#define CAN_F20R1_FB25 CAN_F20R1_FB25_Msk
8400#define CAN_F20R1_FB26_Pos (26U)
8401#define CAN_F20R1_FB26_Msk (0x1UL << CAN_F20R1_FB26_Pos)
8402#define CAN_F20R1_FB26 CAN_F20R1_FB26_Msk
8403#define CAN_F20R1_FB27_Pos (27U)
8404#define CAN_F20R1_FB27_Msk (0x1UL << CAN_F20R1_FB27_Pos)
8405#define CAN_F20R1_FB27 CAN_F20R1_FB27_Msk
8406#define CAN_F20R1_FB28_Pos (28U)
8407#define CAN_F20R1_FB28_Msk (0x1UL << CAN_F20R1_FB28_Pos)
8408#define CAN_F20R1_FB28 CAN_F20R1_FB28_Msk
8409#define CAN_F20R1_FB29_Pos (29U)
8410#define CAN_F20R1_FB29_Msk (0x1UL << CAN_F20R1_FB29_Pos)
8411#define CAN_F20R1_FB29 CAN_F20R1_FB29_Msk
8412#define CAN_F20R1_FB30_Pos (30U)
8413#define CAN_F20R1_FB30_Msk (0x1UL << CAN_F20R1_FB30_Pos)
8414#define CAN_F20R1_FB30 CAN_F20R1_FB30_Msk
8415#define CAN_F20R1_FB31_Pos (31U)
8416#define CAN_F20R1_FB31_Msk (0x1UL << CAN_F20R1_FB31_Pos)
8417#define CAN_F20R1_FB31 CAN_F20R1_FB31_Msk
8419/******************* Bit definition for CAN_F21R1 register ******************/
8420#define CAN_F21R1_FB0_Pos (0U)
8421#define CAN_F21R1_FB0_Msk (0x1UL << CAN_F21R1_FB0_Pos)
8422#define CAN_F21R1_FB0 CAN_F21R1_FB0_Msk
8423#define CAN_F21R1_FB1_Pos (1U)
8424#define CAN_F21R1_FB1_Msk (0x1UL << CAN_F21R1_FB1_Pos)
8425#define CAN_F21R1_FB1 CAN_F21R1_FB1_Msk
8426#define CAN_F21R1_FB2_Pos (2U)
8427#define CAN_F21R1_FB2_Msk (0x1UL << CAN_F21R1_FB2_Pos)
8428#define CAN_F21R1_FB2 CAN_F21R1_FB2_Msk
8429#define CAN_F21R1_FB3_Pos (3U)
8430#define CAN_F21R1_FB3_Msk (0x1UL << CAN_F21R1_FB3_Pos)
8431#define CAN_F21R1_FB3 CAN_F21R1_FB3_Msk
8432#define CAN_F21R1_FB4_Pos (4U)
8433#define CAN_F21R1_FB4_Msk (0x1UL << CAN_F21R1_FB4_Pos)
8434#define CAN_F21R1_FB4 CAN_F21R1_FB4_Msk
8435#define CAN_F21R1_FB5_Pos (5U)
8436#define CAN_F21R1_FB5_Msk (0x1UL << CAN_F21R1_FB5_Pos)
8437#define CAN_F21R1_FB5 CAN_F21R1_FB5_Msk
8438#define CAN_F21R1_FB6_Pos (6U)
8439#define CAN_F21R1_FB6_Msk (0x1UL << CAN_F21R1_FB6_Pos)
8440#define CAN_F21R1_FB6 CAN_F21R1_FB6_Msk
8441#define CAN_F21R1_FB7_Pos (7U)
8442#define CAN_F21R1_FB7_Msk (0x1UL << CAN_F21R1_FB7_Pos)
8443#define CAN_F21R1_FB7 CAN_F21R1_FB7_Msk
8444#define CAN_F21R1_FB8_Pos (8U)
8445#define CAN_F21R1_FB8_Msk (0x1UL << CAN_F21R1_FB8_Pos)
8446#define CAN_F21R1_FB8 CAN_F21R1_FB8_Msk
8447#define CAN_F21R1_FB9_Pos (9U)
8448#define CAN_F21R1_FB9_Msk (0x1UL << CAN_F21R1_FB9_Pos)
8449#define CAN_F21R1_FB9 CAN_F21R1_FB9_Msk
8450#define CAN_F21R1_FB10_Pos (10U)
8451#define CAN_F21R1_FB10_Msk (0x1UL << CAN_F21R1_FB10_Pos)
8452#define CAN_F21R1_FB10 CAN_F21R1_FB10_Msk
8453#define CAN_F21R1_FB11_Pos (11U)
8454#define CAN_F21R1_FB11_Msk (0x1UL << CAN_F21R1_FB11_Pos)
8455#define CAN_F21R1_FB11 CAN_F21R1_FB11_Msk
8456#define CAN_F21R1_FB12_Pos (12U)
8457#define CAN_F21R1_FB12_Msk (0x1UL << CAN_F21R1_FB12_Pos)
8458#define CAN_F21R1_FB12 CAN_F21R1_FB12_Msk
8459#define CAN_F21R1_FB13_Pos (13U)
8460#define CAN_F21R1_FB13_Msk (0x1UL << CAN_F21R1_FB13_Pos)
8461#define CAN_F21R1_FB13 CAN_F21R1_FB13_Msk
8462#define CAN_F21R1_FB14_Pos (14U)
8463#define CAN_F21R1_FB14_Msk (0x1UL << CAN_F21R1_FB14_Pos)
8464#define CAN_F21R1_FB14 CAN_F21R1_FB14_Msk
8465#define CAN_F21R1_FB15_Pos (15U)
8466#define CAN_F21R1_FB15_Msk (0x1UL << CAN_F21R1_FB15_Pos)
8467#define CAN_F21R1_FB15 CAN_F21R1_FB15_Msk
8468#define CAN_F21R1_FB16_Pos (16U)
8469#define CAN_F21R1_FB16_Msk (0x1UL << CAN_F21R1_FB16_Pos)
8470#define CAN_F21R1_FB16 CAN_F21R1_FB16_Msk
8471#define CAN_F21R1_FB17_Pos (17U)
8472#define CAN_F21R1_FB17_Msk (0x1UL << CAN_F21R1_FB17_Pos)
8473#define CAN_F21R1_FB17 CAN_F21R1_FB17_Msk
8474#define CAN_F21R1_FB18_Pos (18U)
8475#define CAN_F21R1_FB18_Msk (0x1UL << CAN_F21R1_FB18_Pos)
8476#define CAN_F21R1_FB18 CAN_F21R1_FB18_Msk
8477#define CAN_F21R1_FB19_Pos (19U)
8478#define CAN_F21R1_FB19_Msk (0x1UL << CAN_F21R1_FB19_Pos)
8479#define CAN_F21R1_FB19 CAN_F21R1_FB19_Msk
8480#define CAN_F21R1_FB20_Pos (20U)
8481#define CAN_F21R1_FB20_Msk (0x1UL << CAN_F21R1_FB20_Pos)
8482#define CAN_F21R1_FB20 CAN_F21R1_FB20_Msk
8483#define CAN_F21R1_FB21_Pos (21U)
8484#define CAN_F21R1_FB21_Msk (0x1UL << CAN_F21R1_FB21_Pos)
8485#define CAN_F21R1_FB21 CAN_F21R1_FB21_Msk
8486#define CAN_F21R1_FB22_Pos (22U)
8487#define CAN_F21R1_FB22_Msk (0x1UL << CAN_F21R1_FB22_Pos)
8488#define CAN_F21R1_FB22 CAN_F21R1_FB22_Msk
8489#define CAN_F21R1_FB23_Pos (23U)
8490#define CAN_F21R1_FB23_Msk (0x1UL << CAN_F21R1_FB23_Pos)
8491#define CAN_F21R1_FB23 CAN_F21R1_FB23_Msk
8492#define CAN_F21R1_FB24_Pos (24U)
8493#define CAN_F21R1_FB24_Msk (0x1UL << CAN_F21R1_FB24_Pos)
8494#define CAN_F21R1_FB24 CAN_F21R1_FB24_Msk
8495#define CAN_F21R1_FB25_Pos (25U)
8496#define CAN_F21R1_FB25_Msk (0x1UL << CAN_F21R1_FB25_Pos)
8497#define CAN_F21R1_FB25 CAN_F21R1_FB25_Msk
8498#define CAN_F21R1_FB26_Pos (26U)
8499#define CAN_F21R1_FB26_Msk (0x1UL << CAN_F21R1_FB26_Pos)
8500#define CAN_F21R1_FB26 CAN_F21R1_FB26_Msk
8501#define CAN_F21R1_FB27_Pos (27U)
8502#define CAN_F21R1_FB27_Msk (0x1UL << CAN_F21R1_FB27_Pos)
8503#define CAN_F21R1_FB27 CAN_F21R1_FB27_Msk
8504#define CAN_F21R1_FB28_Pos (28U)
8505#define CAN_F21R1_FB28_Msk (0x1UL << CAN_F21R1_FB28_Pos)
8506#define CAN_F21R1_FB28 CAN_F21R1_FB28_Msk
8507#define CAN_F21R1_FB29_Pos (29U)
8508#define CAN_F21R1_FB29_Msk (0x1UL << CAN_F21R1_FB29_Pos)
8509#define CAN_F21R1_FB29 CAN_F21R1_FB29_Msk
8510#define CAN_F21R1_FB30_Pos (30U)
8511#define CAN_F21R1_FB30_Msk (0x1UL << CAN_F21R1_FB30_Pos)
8512#define CAN_F21R1_FB30 CAN_F21R1_FB30_Msk
8513#define CAN_F21R1_FB31_Pos (31U)
8514#define CAN_F21R1_FB31_Msk (0x1UL << CAN_F21R1_FB31_Pos)
8515#define CAN_F21R1_FB31 CAN_F21R1_FB31_Msk
8517/******************* Bit definition for CAN_F22R1 register ******************/
8518#define CAN_F22R1_FB0_Pos (0U)
8519#define CAN_F22R1_FB0_Msk (0x1UL << CAN_F22R1_FB0_Pos)
8520#define CAN_F22R1_FB0 CAN_F22R1_FB0_Msk
8521#define CAN_F22R1_FB1_Pos (1U)
8522#define CAN_F22R1_FB1_Msk (0x1UL << CAN_F22R1_FB1_Pos)
8523#define CAN_F22R1_FB1 CAN_F22R1_FB1_Msk
8524#define CAN_F22R1_FB2_Pos (2U)
8525#define CAN_F22R1_FB2_Msk (0x1UL << CAN_F22R1_FB2_Pos)
8526#define CAN_F22R1_FB2 CAN_F22R1_FB2_Msk
8527#define CAN_F22R1_FB3_Pos (3U)
8528#define CAN_F22R1_FB3_Msk (0x1UL << CAN_F22R1_FB3_Pos)
8529#define CAN_F22R1_FB3 CAN_F22R1_FB3_Msk
8530#define CAN_F22R1_FB4_Pos (4U)
8531#define CAN_F22R1_FB4_Msk (0x1UL << CAN_F22R1_FB4_Pos)
8532#define CAN_F22R1_FB4 CAN_F22R1_FB4_Msk
8533#define CAN_F22R1_FB5_Pos (5U)
8534#define CAN_F22R1_FB5_Msk (0x1UL << CAN_F22R1_FB5_Pos)
8535#define CAN_F22R1_FB5 CAN_F22R1_FB5_Msk
8536#define CAN_F22R1_FB6_Pos (6U)
8537#define CAN_F22R1_FB6_Msk (0x1UL << CAN_F22R1_FB6_Pos)
8538#define CAN_F22R1_FB6 CAN_F22R1_FB6_Msk
8539#define CAN_F22R1_FB7_Pos (7U)
8540#define CAN_F22R1_FB7_Msk (0x1UL << CAN_F22R1_FB7_Pos)
8541#define CAN_F22R1_FB7 CAN_F22R1_FB7_Msk
8542#define CAN_F22R1_FB8_Pos (8U)
8543#define CAN_F22R1_FB8_Msk (0x1UL << CAN_F22R1_FB8_Pos)
8544#define CAN_F22R1_FB8 CAN_F22R1_FB8_Msk
8545#define CAN_F22R1_FB9_Pos (9U)
8546#define CAN_F22R1_FB9_Msk (0x1UL << CAN_F22R1_FB9_Pos)
8547#define CAN_F22R1_FB9 CAN_F22R1_FB9_Msk
8548#define CAN_F22R1_FB10_Pos (10U)
8549#define CAN_F22R1_FB10_Msk (0x1UL << CAN_F22R1_FB10_Pos)
8550#define CAN_F22R1_FB10 CAN_F22R1_FB10_Msk
8551#define CAN_F22R1_FB11_Pos (11U)
8552#define CAN_F22R1_FB11_Msk (0x1UL << CAN_F22R1_FB11_Pos)
8553#define CAN_F22R1_FB11 CAN_F22R1_FB11_Msk
8554#define CAN_F22R1_FB12_Pos (12U)
8555#define CAN_F22R1_FB12_Msk (0x1UL << CAN_F22R1_FB12_Pos)
8556#define CAN_F22R1_FB12 CAN_F22R1_FB12_Msk
8557#define CAN_F22R1_FB13_Pos (13U)
8558#define CAN_F22R1_FB13_Msk (0x1UL << CAN_F22R1_FB13_Pos)
8559#define CAN_F22R1_FB13 CAN_F22R1_FB13_Msk
8560#define CAN_F22R1_FB14_Pos (14U)
8561#define CAN_F22R1_FB14_Msk (0x1UL << CAN_F22R1_FB14_Pos)
8562#define CAN_F22R1_FB14 CAN_F22R1_FB14_Msk
8563#define CAN_F22R1_FB15_Pos (15U)
8564#define CAN_F22R1_FB15_Msk (0x1UL << CAN_F22R1_FB15_Pos)
8565#define CAN_F22R1_FB15 CAN_F22R1_FB15_Msk
8566#define CAN_F22R1_FB16_Pos (16U)
8567#define CAN_F22R1_FB16_Msk (0x1UL << CAN_F22R1_FB16_Pos)
8568#define CAN_F22R1_FB16 CAN_F22R1_FB16_Msk
8569#define CAN_F22R1_FB17_Pos (17U)
8570#define CAN_F22R1_FB17_Msk (0x1UL << CAN_F22R1_FB17_Pos)
8571#define CAN_F22R1_FB17 CAN_F22R1_FB17_Msk
8572#define CAN_F22R1_FB18_Pos (18U)
8573#define CAN_F22R1_FB18_Msk (0x1UL << CAN_F22R1_FB18_Pos)
8574#define CAN_F22R1_FB18 CAN_F22R1_FB18_Msk
8575#define CAN_F22R1_FB19_Pos (19U)
8576#define CAN_F22R1_FB19_Msk (0x1UL << CAN_F22R1_FB19_Pos)
8577#define CAN_F22R1_FB19 CAN_F22R1_FB19_Msk
8578#define CAN_F22R1_FB20_Pos (20U)
8579#define CAN_F22R1_FB20_Msk (0x1UL << CAN_F22R1_FB20_Pos)
8580#define CAN_F22R1_FB20 CAN_F22R1_FB20_Msk
8581#define CAN_F22R1_FB21_Pos (21U)
8582#define CAN_F22R1_FB21_Msk (0x1UL << CAN_F22R1_FB21_Pos)
8583#define CAN_F22R1_FB21 CAN_F22R1_FB21_Msk
8584#define CAN_F22R1_FB22_Pos (22U)
8585#define CAN_F22R1_FB22_Msk (0x1UL << CAN_F22R1_FB22_Pos)
8586#define CAN_F22R1_FB22 CAN_F22R1_FB22_Msk
8587#define CAN_F22R1_FB23_Pos (23U)
8588#define CAN_F22R1_FB23_Msk (0x1UL << CAN_F22R1_FB23_Pos)
8589#define CAN_F22R1_FB23 CAN_F22R1_FB23_Msk
8590#define CAN_F22R1_FB24_Pos (24U)
8591#define CAN_F22R1_FB24_Msk (0x1UL << CAN_F22R1_FB24_Pos)
8592#define CAN_F22R1_FB24 CAN_F22R1_FB24_Msk
8593#define CAN_F22R1_FB25_Pos (25U)
8594#define CAN_F22R1_FB25_Msk (0x1UL << CAN_F22R1_FB25_Pos)
8595#define CAN_F22R1_FB25 CAN_F22R1_FB25_Msk
8596#define CAN_F22R1_FB26_Pos (26U)
8597#define CAN_F22R1_FB26_Msk (0x1UL << CAN_F22R1_FB26_Pos)
8598#define CAN_F22R1_FB26 CAN_F22R1_FB26_Msk
8599#define CAN_F22R1_FB27_Pos (27U)
8600#define CAN_F22R1_FB27_Msk (0x1UL << CAN_F22R1_FB27_Pos)
8601#define CAN_F22R1_FB27 CAN_F22R1_FB27_Msk
8602#define CAN_F22R1_FB28_Pos (28U)
8603#define CAN_F22R1_FB28_Msk (0x1UL << CAN_F22R1_FB28_Pos)
8604#define CAN_F22R1_FB28 CAN_F22R1_FB28_Msk
8605#define CAN_F22R1_FB29_Pos (29U)
8606#define CAN_F22R1_FB29_Msk (0x1UL << CAN_F22R1_FB29_Pos)
8607#define CAN_F22R1_FB29 CAN_F22R1_FB29_Msk
8608#define CAN_F22R1_FB30_Pos (30U)
8609#define CAN_F22R1_FB30_Msk (0x1UL << CAN_F22R1_FB30_Pos)
8610#define CAN_F22R1_FB30 CAN_F22R1_FB30_Msk
8611#define CAN_F22R1_FB31_Pos (31U)
8612#define CAN_F22R1_FB31_Msk (0x1UL << CAN_F22R1_FB31_Pos)
8613#define CAN_F22R1_FB31 CAN_F22R1_FB31_Msk
8615/******************* Bit definition for CAN_F23R1 register ******************/
8616#define CAN_F23R1_FB0_Pos (0U)
8617#define CAN_F23R1_FB0_Msk (0x1UL << CAN_F23R1_FB0_Pos)
8618#define CAN_F23R1_FB0 CAN_F23R1_FB0_Msk
8619#define CAN_F23R1_FB1_Pos (1U)
8620#define CAN_F23R1_FB1_Msk (0x1UL << CAN_F23R1_FB1_Pos)
8621#define CAN_F23R1_FB1 CAN_F23R1_FB1_Msk
8622#define CAN_F23R1_FB2_Pos (2U)
8623#define CAN_F23R1_FB2_Msk (0x1UL << CAN_F23R1_FB2_Pos)
8624#define CAN_F23R1_FB2 CAN_F23R1_FB2_Msk
8625#define CAN_F23R1_FB3_Pos (3U)
8626#define CAN_F23R1_FB3_Msk (0x1UL << CAN_F23R1_FB3_Pos)
8627#define CAN_F23R1_FB3 CAN_F23R1_FB3_Msk
8628#define CAN_F23R1_FB4_Pos (4U)
8629#define CAN_F23R1_FB4_Msk (0x1UL << CAN_F23R1_FB4_Pos)
8630#define CAN_F23R1_FB4 CAN_F23R1_FB4_Msk
8631#define CAN_F23R1_FB5_Pos (5U)
8632#define CAN_F23R1_FB5_Msk (0x1UL << CAN_F23R1_FB5_Pos)
8633#define CAN_F23R1_FB5 CAN_F23R1_FB5_Msk
8634#define CAN_F23R1_FB6_Pos (6U)
8635#define CAN_F23R1_FB6_Msk (0x1UL << CAN_F23R1_FB6_Pos)
8636#define CAN_F23R1_FB6 CAN_F23R1_FB6_Msk
8637#define CAN_F23R1_FB7_Pos (7U)
8638#define CAN_F23R1_FB7_Msk (0x1UL << CAN_F23R1_FB7_Pos)
8639#define CAN_F23R1_FB7 CAN_F23R1_FB7_Msk
8640#define CAN_F23R1_FB8_Pos (8U)
8641#define CAN_F23R1_FB8_Msk (0x1UL << CAN_F23R1_FB8_Pos)
8642#define CAN_F23R1_FB8 CAN_F23R1_FB8_Msk
8643#define CAN_F23R1_FB9_Pos (9U)
8644#define CAN_F23R1_FB9_Msk (0x1UL << CAN_F23R1_FB9_Pos)
8645#define CAN_F23R1_FB9 CAN_F23R1_FB9_Msk
8646#define CAN_F23R1_FB10_Pos (10U)
8647#define CAN_F23R1_FB10_Msk (0x1UL << CAN_F23R1_FB10_Pos)
8648#define CAN_F23R1_FB10 CAN_F23R1_FB10_Msk
8649#define CAN_F23R1_FB11_Pos (11U)
8650#define CAN_F23R1_FB11_Msk (0x1UL << CAN_F23R1_FB11_Pos)
8651#define CAN_F23R1_FB11 CAN_F23R1_FB11_Msk
8652#define CAN_F23R1_FB12_Pos (12U)
8653#define CAN_F23R1_FB12_Msk (0x1UL << CAN_F23R1_FB12_Pos)
8654#define CAN_F23R1_FB12 CAN_F23R1_FB12_Msk
8655#define CAN_F23R1_FB13_Pos (13U)
8656#define CAN_F23R1_FB13_Msk (0x1UL << CAN_F23R1_FB13_Pos)
8657#define CAN_F23R1_FB13 CAN_F23R1_FB13_Msk
8658#define CAN_F23R1_FB14_Pos (14U)
8659#define CAN_F23R1_FB14_Msk (0x1UL << CAN_F23R1_FB14_Pos)
8660#define CAN_F23R1_FB14 CAN_F23R1_FB14_Msk
8661#define CAN_F23R1_FB15_Pos (15U)
8662#define CAN_F23R1_FB15_Msk (0x1UL << CAN_F23R1_FB15_Pos)
8663#define CAN_F23R1_FB15 CAN_F23R1_FB15_Msk
8664#define CAN_F23R1_FB16_Pos (16U)
8665#define CAN_F23R1_FB16_Msk (0x1UL << CAN_F23R1_FB16_Pos)
8666#define CAN_F23R1_FB16 CAN_F23R1_FB16_Msk
8667#define CAN_F23R1_FB17_Pos (17U)
8668#define CAN_F23R1_FB17_Msk (0x1UL << CAN_F23R1_FB17_Pos)
8669#define CAN_F23R1_FB17 CAN_F23R1_FB17_Msk
8670#define CAN_F23R1_FB18_Pos (18U)
8671#define CAN_F23R1_FB18_Msk (0x1UL << CAN_F23R1_FB18_Pos)
8672#define CAN_F23R1_FB18 CAN_F23R1_FB18_Msk
8673#define CAN_F23R1_FB19_Pos (19U)
8674#define CAN_F23R1_FB19_Msk (0x1UL << CAN_F23R1_FB19_Pos)
8675#define CAN_F23R1_FB19 CAN_F23R1_FB19_Msk
8676#define CAN_F23R1_FB20_Pos (20U)
8677#define CAN_F23R1_FB20_Msk (0x1UL << CAN_F23R1_FB20_Pos)
8678#define CAN_F23R1_FB20 CAN_F23R1_FB20_Msk
8679#define CAN_F23R1_FB21_Pos (21U)
8680#define CAN_F23R1_FB21_Msk (0x1UL << CAN_F23R1_FB21_Pos)
8681#define CAN_F23R1_FB21 CAN_F23R1_FB21_Msk
8682#define CAN_F23R1_FB22_Pos (22U)
8683#define CAN_F23R1_FB22_Msk (0x1UL << CAN_F23R1_FB22_Pos)
8684#define CAN_F23R1_FB22 CAN_F23R1_FB22_Msk
8685#define CAN_F23R1_FB23_Pos (23U)
8686#define CAN_F23R1_FB23_Msk (0x1UL << CAN_F23R1_FB23_Pos)
8687#define CAN_F23R1_FB23 CAN_F23R1_FB23_Msk
8688#define CAN_F23R1_FB24_Pos (24U)
8689#define CAN_F23R1_FB24_Msk (0x1UL << CAN_F23R1_FB24_Pos)
8690#define CAN_F23R1_FB24 CAN_F23R1_FB24_Msk
8691#define CAN_F23R1_FB25_Pos (25U)
8692#define CAN_F23R1_FB25_Msk (0x1UL << CAN_F23R1_FB25_Pos)
8693#define CAN_F23R1_FB25 CAN_F23R1_FB25_Msk
8694#define CAN_F23R1_FB26_Pos (26U)
8695#define CAN_F23R1_FB26_Msk (0x1UL << CAN_F23R1_FB26_Pos)
8696#define CAN_F23R1_FB26 CAN_F23R1_FB26_Msk
8697#define CAN_F23R1_FB27_Pos (27U)
8698#define CAN_F23R1_FB27_Msk (0x1UL << CAN_F23R1_FB27_Pos)
8699#define CAN_F23R1_FB27 CAN_F23R1_FB27_Msk
8700#define CAN_F23R1_FB28_Pos (28U)
8701#define CAN_F23R1_FB28_Msk (0x1UL << CAN_F23R1_FB28_Pos)
8702#define CAN_F23R1_FB28 CAN_F23R1_FB28_Msk
8703#define CAN_F23R1_FB29_Pos (29U)
8704#define CAN_F23R1_FB29_Msk (0x1UL << CAN_F23R1_FB29_Pos)
8705#define CAN_F23R1_FB29 CAN_F23R1_FB29_Msk
8706#define CAN_F23R1_FB30_Pos (30U)
8707#define CAN_F23R1_FB30_Msk (0x1UL << CAN_F23R1_FB30_Pos)
8708#define CAN_F23R1_FB30 CAN_F23R1_FB30_Msk
8709#define CAN_F23R1_FB31_Pos (31U)
8710#define CAN_F23R1_FB31_Msk (0x1UL << CAN_F23R1_FB31_Pos)
8711#define CAN_F23R1_FB31 CAN_F23R1_FB31_Msk
8713/******************* Bit definition for CAN_F24R1 register ******************/
8714#define CAN_F24R1_FB0_Pos (0U)
8715#define CAN_F24R1_FB0_Msk (0x1UL << CAN_F24R1_FB0_Pos)
8716#define CAN_F24R1_FB0 CAN_F24R1_FB0_Msk
8717#define CAN_F24R1_FB1_Pos (1U)
8718#define CAN_F24R1_FB1_Msk (0x1UL << CAN_F24R1_FB1_Pos)
8719#define CAN_F24R1_FB1 CAN_F24R1_FB1_Msk
8720#define CAN_F24R1_FB2_Pos (2U)
8721#define CAN_F24R1_FB2_Msk (0x1UL << CAN_F24R1_FB2_Pos)
8722#define CAN_F24R1_FB2 CAN_F24R1_FB2_Msk
8723#define CAN_F24R1_FB3_Pos (3U)
8724#define CAN_F24R1_FB3_Msk (0x1UL << CAN_F24R1_FB3_Pos)
8725#define CAN_F24R1_FB3 CAN_F24R1_FB3_Msk
8726#define CAN_F24R1_FB4_Pos (4U)
8727#define CAN_F24R1_FB4_Msk (0x1UL << CAN_F24R1_FB4_Pos)
8728#define CAN_F24R1_FB4 CAN_F24R1_FB4_Msk
8729#define CAN_F24R1_FB5_Pos (5U)
8730#define CAN_F24R1_FB5_Msk (0x1UL << CAN_F24R1_FB5_Pos)
8731#define CAN_F24R1_FB5 CAN_F24R1_FB5_Msk
8732#define CAN_F24R1_FB6_Pos (6U)
8733#define CAN_F24R1_FB6_Msk (0x1UL << CAN_F24R1_FB6_Pos)
8734#define CAN_F24R1_FB6 CAN_F24R1_FB6_Msk
8735#define CAN_F24R1_FB7_Pos (7U)
8736#define CAN_F24R1_FB7_Msk (0x1UL << CAN_F24R1_FB7_Pos)
8737#define CAN_F24R1_FB7 CAN_F24R1_FB7_Msk
8738#define CAN_F24R1_FB8_Pos (8U)
8739#define CAN_F24R1_FB8_Msk (0x1UL << CAN_F24R1_FB8_Pos)
8740#define CAN_F24R1_FB8 CAN_F24R1_FB8_Msk
8741#define CAN_F24R1_FB9_Pos (9U)
8742#define CAN_F24R1_FB9_Msk (0x1UL << CAN_F24R1_FB9_Pos)
8743#define CAN_F24R1_FB9 CAN_F24R1_FB9_Msk
8744#define CAN_F24R1_FB10_Pos (10U)
8745#define CAN_F24R1_FB10_Msk (0x1UL << CAN_F24R1_FB10_Pos)
8746#define CAN_F24R1_FB10 CAN_F24R1_FB10_Msk
8747#define CAN_F24R1_FB11_Pos (11U)
8748#define CAN_F24R1_FB11_Msk (0x1UL << CAN_F24R1_FB11_Pos)
8749#define CAN_F24R1_FB11 CAN_F24R1_FB11_Msk
8750#define CAN_F24R1_FB12_Pos (12U)
8751#define CAN_F24R1_FB12_Msk (0x1UL << CAN_F24R1_FB12_Pos)
8752#define CAN_F24R1_FB12 CAN_F24R1_FB12_Msk
8753#define CAN_F24R1_FB13_Pos (13U)
8754#define CAN_F24R1_FB13_Msk (0x1UL << CAN_F24R1_FB13_Pos)
8755#define CAN_F24R1_FB13 CAN_F24R1_FB13_Msk
8756#define CAN_F24R1_FB14_Pos (14U)
8757#define CAN_F24R1_FB14_Msk (0x1UL << CAN_F24R1_FB14_Pos)
8758#define CAN_F24R1_FB14 CAN_F24R1_FB14_Msk
8759#define CAN_F24R1_FB15_Pos (15U)
8760#define CAN_F24R1_FB15_Msk (0x1UL << CAN_F24R1_FB15_Pos)
8761#define CAN_F24R1_FB15 CAN_F24R1_FB15_Msk
8762#define CAN_F24R1_FB16_Pos (16U)
8763#define CAN_F24R1_FB16_Msk (0x1UL << CAN_F24R1_FB16_Pos)
8764#define CAN_F24R1_FB16 CAN_F24R1_FB16_Msk
8765#define CAN_F24R1_FB17_Pos (17U)
8766#define CAN_F24R1_FB17_Msk (0x1UL << CAN_F24R1_FB17_Pos)
8767#define CAN_F24R1_FB17 CAN_F24R1_FB17_Msk
8768#define CAN_F24R1_FB18_Pos (18U)
8769#define CAN_F24R1_FB18_Msk (0x1UL << CAN_F24R1_FB18_Pos)
8770#define CAN_F24R1_FB18 CAN_F24R1_FB18_Msk
8771#define CAN_F24R1_FB19_Pos (19U)
8772#define CAN_F24R1_FB19_Msk (0x1UL << CAN_F24R1_FB19_Pos)
8773#define CAN_F24R1_FB19 CAN_F24R1_FB19_Msk
8774#define CAN_F24R1_FB20_Pos (20U)
8775#define CAN_F24R1_FB20_Msk (0x1UL << CAN_F24R1_FB20_Pos)
8776#define CAN_F24R1_FB20 CAN_F24R1_FB20_Msk
8777#define CAN_F24R1_FB21_Pos (21U)
8778#define CAN_F24R1_FB21_Msk (0x1UL << CAN_F24R1_FB21_Pos)
8779#define CAN_F24R1_FB21 CAN_F24R1_FB21_Msk
8780#define CAN_F24R1_FB22_Pos (22U)
8781#define CAN_F24R1_FB22_Msk (0x1UL << CAN_F24R1_FB22_Pos)
8782#define CAN_F24R1_FB22 CAN_F24R1_FB22_Msk
8783#define CAN_F24R1_FB23_Pos (23U)
8784#define CAN_F24R1_FB23_Msk (0x1UL << CAN_F24R1_FB23_Pos)
8785#define CAN_F24R1_FB23 CAN_F24R1_FB23_Msk
8786#define CAN_F24R1_FB24_Pos (24U)
8787#define CAN_F24R1_FB24_Msk (0x1UL << CAN_F24R1_FB24_Pos)
8788#define CAN_F24R1_FB24 CAN_F24R1_FB24_Msk
8789#define CAN_F24R1_FB25_Pos (25U)
8790#define CAN_F24R1_FB25_Msk (0x1UL << CAN_F24R1_FB25_Pos)
8791#define CAN_F24R1_FB25 CAN_F24R1_FB25_Msk
8792#define CAN_F24R1_FB26_Pos (26U)
8793#define CAN_F24R1_FB26_Msk (0x1UL << CAN_F24R1_FB26_Pos)
8794#define CAN_F24R1_FB26 CAN_F24R1_FB26_Msk
8795#define CAN_F24R1_FB27_Pos (27U)
8796#define CAN_F24R1_FB27_Msk (0x1UL << CAN_F24R1_FB27_Pos)
8797#define CAN_F24R1_FB27 CAN_F24R1_FB27_Msk
8798#define CAN_F24R1_FB28_Pos (28U)
8799#define CAN_F24R1_FB28_Msk (0x1UL << CAN_F24R1_FB28_Pos)
8800#define CAN_F24R1_FB28 CAN_F24R1_FB28_Msk
8801#define CAN_F24R1_FB29_Pos (29U)
8802#define CAN_F24R1_FB29_Msk (0x1UL << CAN_F24R1_FB29_Pos)
8803#define CAN_F24R1_FB29 CAN_F24R1_FB29_Msk
8804#define CAN_F24R1_FB30_Pos (30U)
8805#define CAN_F24R1_FB30_Msk (0x1UL << CAN_F24R1_FB30_Pos)
8806#define CAN_F24R1_FB30 CAN_F24R1_FB30_Msk
8807#define CAN_F24R1_FB31_Pos (31U)
8808#define CAN_F24R1_FB31_Msk (0x1UL << CAN_F24R1_FB31_Pos)
8809#define CAN_F24R1_FB31 CAN_F24R1_FB31_Msk
8811/******************* Bit definition for CAN_F25R1 register ******************/
8812#define CAN_F25R1_FB0_Pos (0U)
8813#define CAN_F25R1_FB0_Msk (0x1UL << CAN_F25R1_FB0_Pos)
8814#define CAN_F25R1_FB0 CAN_F25R1_FB0_Msk
8815#define CAN_F25R1_FB1_Pos (1U)
8816#define CAN_F25R1_FB1_Msk (0x1UL << CAN_F25R1_FB1_Pos)
8817#define CAN_F25R1_FB1 CAN_F25R1_FB1_Msk
8818#define CAN_F25R1_FB2_Pos (2U)
8819#define CAN_F25R1_FB2_Msk (0x1UL << CAN_F25R1_FB2_Pos)
8820#define CAN_F25R1_FB2 CAN_F25R1_FB2_Msk
8821#define CAN_F25R1_FB3_Pos (3U)
8822#define CAN_F25R1_FB3_Msk (0x1UL << CAN_F25R1_FB3_Pos)
8823#define CAN_F25R1_FB3 CAN_F25R1_FB3_Msk
8824#define CAN_F25R1_FB4_Pos (4U)
8825#define CAN_F25R1_FB4_Msk (0x1UL << CAN_F25R1_FB4_Pos)
8826#define CAN_F25R1_FB4 CAN_F25R1_FB4_Msk
8827#define CAN_F25R1_FB5_Pos (5U)
8828#define CAN_F25R1_FB5_Msk (0x1UL << CAN_F25R1_FB5_Pos)
8829#define CAN_F25R1_FB5 CAN_F25R1_FB5_Msk
8830#define CAN_F25R1_FB6_Pos (6U)
8831#define CAN_F25R1_FB6_Msk (0x1UL << CAN_F25R1_FB6_Pos)
8832#define CAN_F25R1_FB6 CAN_F25R1_FB6_Msk
8833#define CAN_F25R1_FB7_Pos (7U)
8834#define CAN_F25R1_FB7_Msk (0x1UL << CAN_F25R1_FB7_Pos)
8835#define CAN_F25R1_FB7 CAN_F25R1_FB7_Msk
8836#define CAN_F25R1_FB8_Pos (8U)
8837#define CAN_F25R1_FB8_Msk (0x1UL << CAN_F25R1_FB8_Pos)
8838#define CAN_F25R1_FB8 CAN_F25R1_FB8_Msk
8839#define CAN_F25R1_FB9_Pos (9U)
8840#define CAN_F25R1_FB9_Msk (0x1UL << CAN_F25R1_FB9_Pos)
8841#define CAN_F25R1_FB9 CAN_F25R1_FB9_Msk
8842#define CAN_F25R1_FB10_Pos (10U)
8843#define CAN_F25R1_FB10_Msk (0x1UL << CAN_F25R1_FB10_Pos)
8844#define CAN_F25R1_FB10 CAN_F25R1_FB10_Msk
8845#define CAN_F25R1_FB11_Pos (11U)
8846#define CAN_F25R1_FB11_Msk (0x1UL << CAN_F25R1_FB11_Pos)
8847#define CAN_F25R1_FB11 CAN_F25R1_FB11_Msk
8848#define CAN_F25R1_FB12_Pos (12U)
8849#define CAN_F25R1_FB12_Msk (0x1UL << CAN_F25R1_FB12_Pos)
8850#define CAN_F25R1_FB12 CAN_F25R1_FB12_Msk
8851#define CAN_F25R1_FB13_Pos (13U)
8852#define CAN_F25R1_FB13_Msk (0x1UL << CAN_F25R1_FB13_Pos)
8853#define CAN_F25R1_FB13 CAN_F25R1_FB13_Msk
8854#define CAN_F25R1_FB14_Pos (14U)
8855#define CAN_F25R1_FB14_Msk (0x1UL << CAN_F25R1_FB14_Pos)
8856#define CAN_F25R1_FB14 CAN_F25R1_FB14_Msk
8857#define CAN_F25R1_FB15_Pos (15U)
8858#define CAN_F25R1_FB15_Msk (0x1UL << CAN_F25R1_FB15_Pos)
8859#define CAN_F25R1_FB15 CAN_F25R1_FB15_Msk
8860#define CAN_F25R1_FB16_Pos (16U)
8861#define CAN_F25R1_FB16_Msk (0x1UL << CAN_F25R1_FB16_Pos)
8862#define CAN_F25R1_FB16 CAN_F25R1_FB16_Msk
8863#define CAN_F25R1_FB17_Pos (17U)
8864#define CAN_F25R1_FB17_Msk (0x1UL << CAN_F25R1_FB17_Pos)
8865#define CAN_F25R1_FB17 CAN_F25R1_FB17_Msk
8866#define CAN_F25R1_FB18_Pos (18U)
8867#define CAN_F25R1_FB18_Msk (0x1UL << CAN_F25R1_FB18_Pos)
8868#define CAN_F25R1_FB18 CAN_F25R1_FB18_Msk
8869#define CAN_F25R1_FB19_Pos (19U)
8870#define CAN_F25R1_FB19_Msk (0x1UL << CAN_F25R1_FB19_Pos)
8871#define CAN_F25R1_FB19 CAN_F25R1_FB19_Msk
8872#define CAN_F25R1_FB20_Pos (20U)
8873#define CAN_F25R1_FB20_Msk (0x1UL << CAN_F25R1_FB20_Pos)
8874#define CAN_F25R1_FB20 CAN_F25R1_FB20_Msk
8875#define CAN_F25R1_FB21_Pos (21U)
8876#define CAN_F25R1_FB21_Msk (0x1UL << CAN_F25R1_FB21_Pos)
8877#define CAN_F25R1_FB21 CAN_F25R1_FB21_Msk
8878#define CAN_F25R1_FB22_Pos (22U)
8879#define CAN_F25R1_FB22_Msk (0x1UL << CAN_F25R1_FB22_Pos)
8880#define CAN_F25R1_FB22 CAN_F25R1_FB22_Msk
8881#define CAN_F25R1_FB23_Pos (23U)
8882#define CAN_F25R1_FB23_Msk (0x1UL << CAN_F25R1_FB23_Pos)
8883#define CAN_F25R1_FB23 CAN_F25R1_FB23_Msk
8884#define CAN_F25R1_FB24_Pos (24U)
8885#define CAN_F25R1_FB24_Msk (0x1UL << CAN_F25R1_FB24_Pos)
8886#define CAN_F25R1_FB24 CAN_F25R1_FB24_Msk
8887#define CAN_F25R1_FB25_Pos (25U)
8888#define CAN_F25R1_FB25_Msk (0x1UL << CAN_F25R1_FB25_Pos)
8889#define CAN_F25R1_FB25 CAN_F25R1_FB25_Msk
8890#define CAN_F25R1_FB26_Pos (26U)
8891#define CAN_F25R1_FB26_Msk (0x1UL << CAN_F25R1_FB26_Pos)
8892#define CAN_F25R1_FB26 CAN_F25R1_FB26_Msk
8893#define CAN_F25R1_FB27_Pos (27U)
8894#define CAN_F25R1_FB27_Msk (0x1UL << CAN_F25R1_FB27_Pos)
8895#define CAN_F25R1_FB27 CAN_F25R1_FB27_Msk
8896#define CAN_F25R1_FB28_Pos (28U)
8897#define CAN_F25R1_FB28_Msk (0x1UL << CAN_F25R1_FB28_Pos)
8898#define CAN_F25R1_FB28 CAN_F25R1_FB28_Msk
8899#define CAN_F25R1_FB29_Pos (29U)
8900#define CAN_F25R1_FB29_Msk (0x1UL << CAN_F25R1_FB29_Pos)
8901#define CAN_F25R1_FB29 CAN_F25R1_FB29_Msk
8902#define CAN_F25R1_FB30_Pos (30U)
8903#define CAN_F25R1_FB30_Msk (0x1UL << CAN_F25R1_FB30_Pos)
8904#define CAN_F25R1_FB30 CAN_F25R1_FB30_Msk
8905#define CAN_F25R1_FB31_Pos (31U)
8906#define CAN_F25R1_FB31_Msk (0x1UL << CAN_F25R1_FB31_Pos)
8907#define CAN_F25R1_FB31 CAN_F25R1_FB31_Msk
8909/******************* Bit definition for CAN_F26R1 register ******************/
8910#define CAN_F26R1_FB0_Pos (0U)
8911#define CAN_F26R1_FB0_Msk (0x1UL << CAN_F26R1_FB0_Pos)
8912#define CAN_F26R1_FB0 CAN_F26R1_FB0_Msk
8913#define CAN_F26R1_FB1_Pos (1U)
8914#define CAN_F26R1_FB1_Msk (0x1UL << CAN_F26R1_FB1_Pos)
8915#define CAN_F26R1_FB1 CAN_F26R1_FB1_Msk
8916#define CAN_F26R1_FB2_Pos (2U)
8917#define CAN_F26R1_FB2_Msk (0x1UL << CAN_F26R1_FB2_Pos)
8918#define CAN_F26R1_FB2 CAN_F26R1_FB2_Msk
8919#define CAN_F26R1_FB3_Pos (3U)
8920#define CAN_F26R1_FB3_Msk (0x1UL << CAN_F26R1_FB3_Pos)
8921#define CAN_F26R1_FB3 CAN_F26R1_FB3_Msk
8922#define CAN_F26R1_FB4_Pos (4U)
8923#define CAN_F26R1_FB4_Msk (0x1UL << CAN_F26R1_FB4_Pos)
8924#define CAN_F26R1_FB4 CAN_F26R1_FB4_Msk
8925#define CAN_F26R1_FB5_Pos (5U)
8926#define CAN_F26R1_FB5_Msk (0x1UL << CAN_F26R1_FB5_Pos)
8927#define CAN_F26R1_FB5 CAN_F26R1_FB5_Msk
8928#define CAN_F26R1_FB6_Pos (6U)
8929#define CAN_F26R1_FB6_Msk (0x1UL << CAN_F26R1_FB6_Pos)
8930#define CAN_F26R1_FB6 CAN_F26R1_FB6_Msk
8931#define CAN_F26R1_FB7_Pos (7U)
8932#define CAN_F26R1_FB7_Msk (0x1UL << CAN_F26R1_FB7_Pos)
8933#define CAN_F26R1_FB7 CAN_F26R1_FB7_Msk
8934#define CAN_F26R1_FB8_Pos (8U)
8935#define CAN_F26R1_FB8_Msk (0x1UL << CAN_F26R1_FB8_Pos)
8936#define CAN_F26R1_FB8 CAN_F26R1_FB8_Msk
8937#define CAN_F26R1_FB9_Pos (9U)
8938#define CAN_F26R1_FB9_Msk (0x1UL << CAN_F26R1_FB9_Pos)
8939#define CAN_F26R1_FB9 CAN_F26R1_FB9_Msk
8940#define CAN_F26R1_FB10_Pos (10U)
8941#define CAN_F26R1_FB10_Msk (0x1UL << CAN_F26R1_FB10_Pos)
8942#define CAN_F26R1_FB10 CAN_F26R1_FB10_Msk
8943#define CAN_F26R1_FB11_Pos (11U)
8944#define CAN_F26R1_FB11_Msk (0x1UL << CAN_F26R1_FB11_Pos)
8945#define CAN_F26R1_FB11 CAN_F26R1_FB11_Msk
8946#define CAN_F26R1_FB12_Pos (12U)
8947#define CAN_F26R1_FB12_Msk (0x1UL << CAN_F26R1_FB12_Pos)
8948#define CAN_F26R1_FB12 CAN_F26R1_FB12_Msk
8949#define CAN_F26R1_FB13_Pos (13U)
8950#define CAN_F26R1_FB13_Msk (0x1UL << CAN_F26R1_FB13_Pos)
8951#define CAN_F26R1_FB13 CAN_F26R1_FB13_Msk
8952#define CAN_F26R1_FB14_Pos (14U)
8953#define CAN_F26R1_FB14_Msk (0x1UL << CAN_F26R1_FB14_Pos)
8954#define CAN_F26R1_FB14 CAN_F26R1_FB14_Msk
8955#define CAN_F26R1_FB15_Pos (15U)
8956#define CAN_F26R1_FB15_Msk (0x1UL << CAN_F26R1_FB15_Pos)
8957#define CAN_F26R1_FB15 CAN_F26R1_FB15_Msk
8958#define CAN_F26R1_FB16_Pos (16U)
8959#define CAN_F26R1_FB16_Msk (0x1UL << CAN_F26R1_FB16_Pos)
8960#define CAN_F26R1_FB16 CAN_F26R1_FB16_Msk
8961#define CAN_F26R1_FB17_Pos (17U)
8962#define CAN_F26R1_FB17_Msk (0x1UL << CAN_F26R1_FB17_Pos)
8963#define CAN_F26R1_FB17 CAN_F26R1_FB17_Msk
8964#define CAN_F26R1_FB18_Pos (18U)
8965#define CAN_F26R1_FB18_Msk (0x1UL << CAN_F26R1_FB18_Pos)
8966#define CAN_F26R1_FB18 CAN_F26R1_FB18_Msk
8967#define CAN_F26R1_FB19_Pos (19U)
8968#define CAN_F26R1_FB19_Msk (0x1UL << CAN_F26R1_FB19_Pos)
8969#define CAN_F26R1_FB19 CAN_F26R1_FB19_Msk
8970#define CAN_F26R1_FB20_Pos (20U)
8971#define CAN_F26R1_FB20_Msk (0x1UL << CAN_F26R1_FB20_Pos)
8972#define CAN_F26R1_FB20 CAN_F26R1_FB20_Msk
8973#define CAN_F26R1_FB21_Pos (21U)
8974#define CAN_F26R1_FB21_Msk (0x1UL << CAN_F26R1_FB21_Pos)
8975#define CAN_F26R1_FB21 CAN_F26R1_FB21_Msk
8976#define CAN_F26R1_FB22_Pos (22U)
8977#define CAN_F26R1_FB22_Msk (0x1UL << CAN_F26R1_FB22_Pos)
8978#define CAN_F26R1_FB22 CAN_F26R1_FB22_Msk
8979#define CAN_F26R1_FB23_Pos (23U)
8980#define CAN_F26R1_FB23_Msk (0x1UL << CAN_F26R1_FB23_Pos)
8981#define CAN_F26R1_FB23 CAN_F26R1_FB23_Msk
8982#define CAN_F26R1_FB24_Pos (24U)
8983#define CAN_F26R1_FB24_Msk (0x1UL << CAN_F26R1_FB24_Pos)
8984#define CAN_F26R1_FB24 CAN_F26R1_FB24_Msk
8985#define CAN_F26R1_FB25_Pos (25U)
8986#define CAN_F26R1_FB25_Msk (0x1UL << CAN_F26R1_FB25_Pos)
8987#define CAN_F26R1_FB25 CAN_F26R1_FB25_Msk
8988#define CAN_F26R1_FB26_Pos (26U)
8989#define CAN_F26R1_FB26_Msk (0x1UL << CAN_F26R1_FB26_Pos)
8990#define CAN_F26R1_FB26 CAN_F26R1_FB26_Msk
8991#define CAN_F26R1_FB27_Pos (27U)
8992#define CAN_F26R1_FB27_Msk (0x1UL << CAN_F26R1_FB27_Pos)
8993#define CAN_F26R1_FB27 CAN_F26R1_FB27_Msk
8994#define CAN_F26R1_FB28_Pos (28U)
8995#define CAN_F26R1_FB28_Msk (0x1UL << CAN_F26R1_FB28_Pos)
8996#define CAN_F26R1_FB28 CAN_F26R1_FB28_Msk
8997#define CAN_F26R1_FB29_Pos (29U)
8998#define CAN_F26R1_FB29_Msk (0x1UL << CAN_F26R1_FB29_Pos)
8999#define CAN_F26R1_FB29 CAN_F26R1_FB29_Msk
9000#define CAN_F26R1_FB30_Pos (30U)
9001#define CAN_F26R1_FB30_Msk (0x1UL << CAN_F26R1_FB30_Pos)
9002#define CAN_F26R1_FB30 CAN_F26R1_FB30_Msk
9003#define CAN_F26R1_FB31_Pos (31U)
9004#define CAN_F26R1_FB31_Msk (0x1UL << CAN_F26R1_FB31_Pos)
9005#define CAN_F26R1_FB31 CAN_F26R1_FB31_Msk
9007/******************* Bit definition for CAN_F27R1 register ******************/
9008#define CAN_F27R1_FB0_Pos (0U)
9009#define CAN_F27R1_FB0_Msk (0x1UL << CAN_F27R1_FB0_Pos)
9010#define CAN_F27R1_FB0 CAN_F27R1_FB0_Msk
9011#define CAN_F27R1_FB1_Pos (1U)
9012#define CAN_F27R1_FB1_Msk (0x1UL << CAN_F27R1_FB1_Pos)
9013#define CAN_F27R1_FB1 CAN_F27R1_FB1_Msk
9014#define CAN_F27R1_FB2_Pos (2U)
9015#define CAN_F27R1_FB2_Msk (0x1UL << CAN_F27R1_FB2_Pos)
9016#define CAN_F27R1_FB2 CAN_F27R1_FB2_Msk
9017#define CAN_F27R1_FB3_Pos (3U)
9018#define CAN_F27R1_FB3_Msk (0x1UL << CAN_F27R1_FB3_Pos)
9019#define CAN_F27R1_FB3 CAN_F27R1_FB3_Msk
9020#define CAN_F27R1_FB4_Pos (4U)
9021#define CAN_F27R1_FB4_Msk (0x1UL << CAN_F27R1_FB4_Pos)
9022#define CAN_F27R1_FB4 CAN_F27R1_FB4_Msk
9023#define CAN_F27R1_FB5_Pos (5U)
9024#define CAN_F27R1_FB5_Msk (0x1UL << CAN_F27R1_FB5_Pos)
9025#define CAN_F27R1_FB5 CAN_F27R1_FB5_Msk
9026#define CAN_F27R1_FB6_Pos (6U)
9027#define CAN_F27R1_FB6_Msk (0x1UL << CAN_F27R1_FB6_Pos)
9028#define CAN_F27R1_FB6 CAN_F27R1_FB6_Msk
9029#define CAN_F27R1_FB7_Pos (7U)
9030#define CAN_F27R1_FB7_Msk (0x1UL << CAN_F27R1_FB7_Pos)
9031#define CAN_F27R1_FB7 CAN_F27R1_FB7_Msk
9032#define CAN_F27R1_FB8_Pos (8U)
9033#define CAN_F27R1_FB8_Msk (0x1UL << CAN_F27R1_FB8_Pos)
9034#define CAN_F27R1_FB8 CAN_F27R1_FB8_Msk
9035#define CAN_F27R1_FB9_Pos (9U)
9036#define CAN_F27R1_FB9_Msk (0x1UL << CAN_F27R1_FB9_Pos)
9037#define CAN_F27R1_FB9 CAN_F27R1_FB9_Msk
9038#define CAN_F27R1_FB10_Pos (10U)
9039#define CAN_F27R1_FB10_Msk (0x1UL << CAN_F27R1_FB10_Pos)
9040#define CAN_F27R1_FB10 CAN_F27R1_FB10_Msk
9041#define CAN_F27R1_FB11_Pos (11U)
9042#define CAN_F27R1_FB11_Msk (0x1UL << CAN_F27R1_FB11_Pos)
9043#define CAN_F27R1_FB11 CAN_F27R1_FB11_Msk
9044#define CAN_F27R1_FB12_Pos (12U)
9045#define CAN_F27R1_FB12_Msk (0x1UL << CAN_F27R1_FB12_Pos)
9046#define CAN_F27R1_FB12 CAN_F27R1_FB12_Msk
9047#define CAN_F27R1_FB13_Pos (13U)
9048#define CAN_F27R1_FB13_Msk (0x1UL << CAN_F27R1_FB13_Pos)
9049#define CAN_F27R1_FB13 CAN_F27R1_FB13_Msk
9050#define CAN_F27R1_FB14_Pos (14U)
9051#define CAN_F27R1_FB14_Msk (0x1UL << CAN_F27R1_FB14_Pos)
9052#define CAN_F27R1_FB14 CAN_F27R1_FB14_Msk
9053#define CAN_F27R1_FB15_Pos (15U)
9054#define CAN_F27R1_FB15_Msk (0x1UL << CAN_F27R1_FB15_Pos)
9055#define CAN_F27R1_FB15 CAN_F27R1_FB15_Msk
9056#define CAN_F27R1_FB16_Pos (16U)
9057#define CAN_F27R1_FB16_Msk (0x1UL << CAN_F27R1_FB16_Pos)
9058#define CAN_F27R1_FB16 CAN_F27R1_FB16_Msk
9059#define CAN_F27R1_FB17_Pos (17U)
9060#define CAN_F27R1_FB17_Msk (0x1UL << CAN_F27R1_FB17_Pos)
9061#define CAN_F27R1_FB17 CAN_F27R1_FB17_Msk
9062#define CAN_F27R1_FB18_Pos (18U)
9063#define CAN_F27R1_FB18_Msk (0x1UL << CAN_F27R1_FB18_Pos)
9064#define CAN_F27R1_FB18 CAN_F27R1_FB18_Msk
9065#define CAN_F27R1_FB19_Pos (19U)
9066#define CAN_F27R1_FB19_Msk (0x1UL << CAN_F27R1_FB19_Pos)
9067#define CAN_F27R1_FB19 CAN_F27R1_FB19_Msk
9068#define CAN_F27R1_FB20_Pos (20U)
9069#define CAN_F27R1_FB20_Msk (0x1UL << CAN_F27R1_FB20_Pos)
9070#define CAN_F27R1_FB20 CAN_F27R1_FB20_Msk
9071#define CAN_F27R1_FB21_Pos (21U)
9072#define CAN_F27R1_FB21_Msk (0x1UL << CAN_F27R1_FB21_Pos)
9073#define CAN_F27R1_FB21 CAN_F27R1_FB21_Msk
9074#define CAN_F27R1_FB22_Pos (22U)
9075#define CAN_F27R1_FB22_Msk (0x1UL << CAN_F27R1_FB22_Pos)
9076#define CAN_F27R1_FB22 CAN_F27R1_FB22_Msk
9077#define CAN_F27R1_FB23_Pos (23U)
9078#define CAN_F27R1_FB23_Msk (0x1UL << CAN_F27R1_FB23_Pos)
9079#define CAN_F27R1_FB23 CAN_F27R1_FB23_Msk
9080#define CAN_F27R1_FB24_Pos (24U)
9081#define CAN_F27R1_FB24_Msk (0x1UL << CAN_F27R1_FB24_Pos)
9082#define CAN_F27R1_FB24 CAN_F27R1_FB24_Msk
9083#define CAN_F27R1_FB25_Pos (25U)
9084#define CAN_F27R1_FB25_Msk (0x1UL << CAN_F27R1_FB25_Pos)
9085#define CAN_F27R1_FB25 CAN_F27R1_FB25_Msk
9086#define CAN_F27R1_FB26_Pos (26U)
9087#define CAN_F27R1_FB26_Msk (0x1UL << CAN_F27R1_FB26_Pos)
9088#define CAN_F27R1_FB26 CAN_F27R1_FB26_Msk
9089#define CAN_F27R1_FB27_Pos (27U)
9090#define CAN_F27R1_FB27_Msk (0x1UL << CAN_F27R1_FB27_Pos)
9091#define CAN_F27R1_FB27 CAN_F27R1_FB27_Msk
9092#define CAN_F27R1_FB28_Pos (28U)
9093#define CAN_F27R1_FB28_Msk (0x1UL << CAN_F27R1_FB28_Pos)
9094#define CAN_F27R1_FB28 CAN_F27R1_FB28_Msk
9095#define CAN_F27R1_FB29_Pos (29U)
9096#define CAN_F27R1_FB29_Msk (0x1UL << CAN_F27R1_FB29_Pos)
9097#define CAN_F27R1_FB29 CAN_F27R1_FB29_Msk
9098#define CAN_F27R1_FB30_Pos (30U)
9099#define CAN_F27R1_FB30_Msk (0x1UL << CAN_F27R1_FB30_Pos)
9100#define CAN_F27R1_FB30 CAN_F27R1_FB30_Msk
9101#define CAN_F27R1_FB31_Pos (31U)
9102#define CAN_F27R1_FB31_Msk (0x1UL << CAN_F27R1_FB31_Pos)
9103#define CAN_F27R1_FB31 CAN_F27R1_FB31_Msk
9105/******************* Bit definition for CAN_F0R2 register *******************/
9106#define CAN_F0R2_FB0_Pos (0U)
9107#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
9108#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
9109#define CAN_F0R2_FB1_Pos (1U)
9110#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
9111#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
9112#define CAN_F0R2_FB2_Pos (2U)
9113#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
9114#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
9115#define CAN_F0R2_FB3_Pos (3U)
9116#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
9117#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
9118#define CAN_F0R2_FB4_Pos (4U)
9119#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
9120#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
9121#define CAN_F0R2_FB5_Pos (5U)
9122#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
9123#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
9124#define CAN_F0R2_FB6_Pos (6U)
9125#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
9126#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
9127#define CAN_F0R2_FB7_Pos (7U)
9128#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
9129#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
9130#define CAN_F0R2_FB8_Pos (8U)
9131#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
9132#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
9133#define CAN_F0R2_FB9_Pos (9U)
9134#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
9135#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
9136#define CAN_F0R2_FB10_Pos (10U)
9137#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
9138#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
9139#define CAN_F0R2_FB11_Pos (11U)
9140#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
9141#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
9142#define CAN_F0R2_FB12_Pos (12U)
9143#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
9144#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
9145#define CAN_F0R2_FB13_Pos (13U)
9146#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
9147#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
9148#define CAN_F0R2_FB14_Pos (14U)
9149#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
9150#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
9151#define CAN_F0R2_FB15_Pos (15U)
9152#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
9153#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
9154#define CAN_F0R2_FB16_Pos (16U)
9155#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
9156#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
9157#define CAN_F0R2_FB17_Pos (17U)
9158#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
9159#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
9160#define CAN_F0R2_FB18_Pos (18U)
9161#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
9162#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
9163#define CAN_F0R2_FB19_Pos (19U)
9164#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
9165#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
9166#define CAN_F0R2_FB20_Pos (20U)
9167#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
9168#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
9169#define CAN_F0R2_FB21_Pos (21U)
9170#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
9171#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
9172#define CAN_F0R2_FB22_Pos (22U)
9173#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
9174#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
9175#define CAN_F0R2_FB23_Pos (23U)
9176#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
9177#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
9178#define CAN_F0R2_FB24_Pos (24U)
9179#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
9180#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
9181#define CAN_F0R2_FB25_Pos (25U)
9182#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
9183#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
9184#define CAN_F0R2_FB26_Pos (26U)
9185#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
9186#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
9187#define CAN_F0R2_FB27_Pos (27U)
9188#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
9189#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
9190#define CAN_F0R2_FB28_Pos (28U)
9191#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
9192#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
9193#define CAN_F0R2_FB29_Pos (29U)
9194#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
9195#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
9196#define CAN_F0R2_FB30_Pos (30U)
9197#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
9198#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
9199#define CAN_F0R2_FB31_Pos (31U)
9200#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
9201#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
9203/******************* Bit definition for CAN_F1R2 register *******************/
9204#define CAN_F1R2_FB0_Pos (0U)
9205#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
9206#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
9207#define CAN_F1R2_FB1_Pos (1U)
9208#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
9209#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
9210#define CAN_F1R2_FB2_Pos (2U)
9211#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
9212#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
9213#define CAN_F1R2_FB3_Pos (3U)
9214#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
9215#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
9216#define CAN_F1R2_FB4_Pos (4U)
9217#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
9218#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
9219#define CAN_F1R2_FB5_Pos (5U)
9220#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
9221#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
9222#define CAN_F1R2_FB6_Pos (6U)
9223#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
9224#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
9225#define CAN_F1R2_FB7_Pos (7U)
9226#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
9227#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
9228#define CAN_F1R2_FB8_Pos (8U)
9229#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
9230#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
9231#define CAN_F1R2_FB9_Pos (9U)
9232#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
9233#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
9234#define CAN_F1R2_FB10_Pos (10U)
9235#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
9236#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
9237#define CAN_F1R2_FB11_Pos (11U)
9238#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
9239#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
9240#define CAN_F1R2_FB12_Pos (12U)
9241#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
9242#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
9243#define CAN_F1R2_FB13_Pos (13U)
9244#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
9245#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
9246#define CAN_F1R2_FB14_Pos (14U)
9247#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
9248#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
9249#define CAN_F1R2_FB15_Pos (15U)
9250#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
9251#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
9252#define CAN_F1R2_FB16_Pos (16U)
9253#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
9254#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
9255#define CAN_F1R2_FB17_Pos (17U)
9256#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
9257#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
9258#define CAN_F1R2_FB18_Pos (18U)
9259#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
9260#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
9261#define CAN_F1R2_FB19_Pos (19U)
9262#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
9263#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
9264#define CAN_F1R2_FB20_Pos (20U)
9265#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
9266#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
9267#define CAN_F1R2_FB21_Pos (21U)
9268#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
9269#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
9270#define CAN_F1R2_FB22_Pos (22U)
9271#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
9272#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
9273#define CAN_F1R2_FB23_Pos (23U)
9274#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
9275#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
9276#define CAN_F1R2_FB24_Pos (24U)
9277#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
9278#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
9279#define CAN_F1R2_FB25_Pos (25U)
9280#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
9281#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
9282#define CAN_F1R2_FB26_Pos (26U)
9283#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
9284#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
9285#define CAN_F1R2_FB27_Pos (27U)
9286#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
9287#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
9288#define CAN_F1R2_FB28_Pos (28U)
9289#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
9290#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
9291#define CAN_F1R2_FB29_Pos (29U)
9292#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
9293#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
9294#define CAN_F1R2_FB30_Pos (30U)
9295#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
9296#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
9297#define CAN_F1R2_FB31_Pos (31U)
9298#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
9299#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
9301/******************* Bit definition for CAN_F2R2 register *******************/
9302#define CAN_F2R2_FB0_Pos (0U)
9303#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
9304#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
9305#define CAN_F2R2_FB1_Pos (1U)
9306#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
9307#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
9308#define CAN_F2R2_FB2_Pos (2U)
9309#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
9310#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
9311#define CAN_F2R2_FB3_Pos (3U)
9312#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
9313#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
9314#define CAN_F2R2_FB4_Pos (4U)
9315#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
9316#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
9317#define CAN_F2R2_FB5_Pos (5U)
9318#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
9319#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
9320#define CAN_F2R2_FB6_Pos (6U)
9321#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
9322#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
9323#define CAN_F2R2_FB7_Pos (7U)
9324#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
9325#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
9326#define CAN_F2R2_FB8_Pos (8U)
9327#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
9328#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
9329#define CAN_F2R2_FB9_Pos (9U)
9330#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
9331#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
9332#define CAN_F2R2_FB10_Pos (10U)
9333#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
9334#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
9335#define CAN_F2R2_FB11_Pos (11U)
9336#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
9337#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
9338#define CAN_F2R2_FB12_Pos (12U)
9339#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
9340#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
9341#define CAN_F2R2_FB13_Pos (13U)
9342#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
9343#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
9344#define CAN_F2R2_FB14_Pos (14U)
9345#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
9346#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
9347#define CAN_F2R2_FB15_Pos (15U)
9348#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
9349#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
9350#define CAN_F2R2_FB16_Pos (16U)
9351#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
9352#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
9353#define CAN_F2R2_FB17_Pos (17U)
9354#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
9355#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
9356#define CAN_F2R2_FB18_Pos (18U)
9357#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
9358#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
9359#define CAN_F2R2_FB19_Pos (19U)
9360#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
9361#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
9362#define CAN_F2R2_FB20_Pos (20U)
9363#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
9364#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
9365#define CAN_F2R2_FB21_Pos (21U)
9366#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
9367#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
9368#define CAN_F2R2_FB22_Pos (22U)
9369#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
9370#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
9371#define CAN_F2R2_FB23_Pos (23U)
9372#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
9373#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
9374#define CAN_F2R2_FB24_Pos (24U)
9375#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
9376#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
9377#define CAN_F2R2_FB25_Pos (25U)
9378#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
9379#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
9380#define CAN_F2R2_FB26_Pos (26U)
9381#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
9382#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
9383#define CAN_F2R2_FB27_Pos (27U)
9384#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
9385#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
9386#define CAN_F2R2_FB28_Pos (28U)
9387#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
9388#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
9389#define CAN_F2R2_FB29_Pos (29U)
9390#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
9391#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
9392#define CAN_F2R2_FB30_Pos (30U)
9393#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
9394#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
9395#define CAN_F2R2_FB31_Pos (31U)
9396#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
9397#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
9399/******************* Bit definition for CAN_F3R2 register *******************/
9400#define CAN_F3R2_FB0_Pos (0U)
9401#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
9402#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
9403#define CAN_F3R2_FB1_Pos (1U)
9404#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
9405#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
9406#define CAN_F3R2_FB2_Pos (2U)
9407#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
9408#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
9409#define CAN_F3R2_FB3_Pos (3U)
9410#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
9411#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
9412#define CAN_F3R2_FB4_Pos (4U)
9413#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
9414#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
9415#define CAN_F3R2_FB5_Pos (5U)
9416#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
9417#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
9418#define CAN_F3R2_FB6_Pos (6U)
9419#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
9420#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
9421#define CAN_F3R2_FB7_Pos (7U)
9422#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
9423#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
9424#define CAN_F3R2_FB8_Pos (8U)
9425#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
9426#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
9427#define CAN_F3R2_FB9_Pos (9U)
9428#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
9429#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
9430#define CAN_F3R2_FB10_Pos (10U)
9431#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
9432#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
9433#define CAN_F3R2_FB11_Pos (11U)
9434#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
9435#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
9436#define CAN_F3R2_FB12_Pos (12U)
9437#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
9438#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
9439#define CAN_F3R2_FB13_Pos (13U)
9440#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
9441#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
9442#define CAN_F3R2_FB14_Pos (14U)
9443#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
9444#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
9445#define CAN_F3R2_FB15_Pos (15U)
9446#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
9447#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
9448#define CAN_F3R2_FB16_Pos (16U)
9449#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
9450#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
9451#define CAN_F3R2_FB17_Pos (17U)
9452#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
9453#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
9454#define CAN_F3R2_FB18_Pos (18U)
9455#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
9456#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
9457#define CAN_F3R2_FB19_Pos (19U)
9458#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
9459#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
9460#define CAN_F3R2_FB20_Pos (20U)
9461#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
9462#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
9463#define CAN_F3R2_FB21_Pos (21U)
9464#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
9465#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
9466#define CAN_F3R2_FB22_Pos (22U)
9467#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
9468#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
9469#define CAN_F3R2_FB23_Pos (23U)
9470#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
9471#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
9472#define CAN_F3R2_FB24_Pos (24U)
9473#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
9474#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
9475#define CAN_F3R2_FB25_Pos (25U)
9476#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
9477#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
9478#define CAN_F3R2_FB26_Pos (26U)
9479#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
9480#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
9481#define CAN_F3R2_FB27_Pos (27U)
9482#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
9483#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
9484#define CAN_F3R2_FB28_Pos (28U)
9485#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
9486#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
9487#define CAN_F3R2_FB29_Pos (29U)
9488#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
9489#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
9490#define CAN_F3R2_FB30_Pos (30U)
9491#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
9492#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
9493#define CAN_F3R2_FB31_Pos (31U)
9494#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
9495#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
9497/******************* Bit definition for CAN_F4R2 register *******************/
9498#define CAN_F4R2_FB0_Pos (0U)
9499#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
9500#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
9501#define CAN_F4R2_FB1_Pos (1U)
9502#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
9503#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
9504#define CAN_F4R2_FB2_Pos (2U)
9505#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
9506#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
9507#define CAN_F4R2_FB3_Pos (3U)
9508#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
9509#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
9510#define CAN_F4R2_FB4_Pos (4U)
9511#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
9512#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
9513#define CAN_F4R2_FB5_Pos (5U)
9514#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
9515#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
9516#define CAN_F4R2_FB6_Pos (6U)
9517#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
9518#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
9519#define CAN_F4R2_FB7_Pos (7U)
9520#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
9521#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
9522#define CAN_F4R2_FB8_Pos (8U)
9523#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
9524#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
9525#define CAN_F4R2_FB9_Pos (9U)
9526#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
9527#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
9528#define CAN_F4R2_FB10_Pos (10U)
9529#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
9530#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
9531#define CAN_F4R2_FB11_Pos (11U)
9532#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
9533#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
9534#define CAN_F4R2_FB12_Pos (12U)
9535#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
9536#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
9537#define CAN_F4R2_FB13_Pos (13U)
9538#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
9539#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
9540#define CAN_F4R2_FB14_Pos (14U)
9541#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
9542#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
9543#define CAN_F4R2_FB15_Pos (15U)
9544#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
9545#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
9546#define CAN_F4R2_FB16_Pos (16U)
9547#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
9548#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
9549#define CAN_F4R2_FB17_Pos (17U)
9550#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
9551#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
9552#define CAN_F4R2_FB18_Pos (18U)
9553#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
9554#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
9555#define CAN_F4R2_FB19_Pos (19U)
9556#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
9557#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
9558#define CAN_F4R2_FB20_Pos (20U)
9559#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
9560#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
9561#define CAN_F4R2_FB21_Pos (21U)
9562#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
9563#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
9564#define CAN_F4R2_FB22_Pos (22U)
9565#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
9566#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
9567#define CAN_F4R2_FB23_Pos (23U)
9568#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
9569#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
9570#define CAN_F4R2_FB24_Pos (24U)
9571#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
9572#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
9573#define CAN_F4R2_FB25_Pos (25U)
9574#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
9575#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
9576#define CAN_F4R2_FB26_Pos (26U)
9577#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
9578#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
9579#define CAN_F4R2_FB27_Pos (27U)
9580#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
9581#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
9582#define CAN_F4R2_FB28_Pos (28U)
9583#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
9584#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
9585#define CAN_F4R2_FB29_Pos (29U)
9586#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
9587#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
9588#define CAN_F4R2_FB30_Pos (30U)
9589#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
9590#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
9591#define CAN_F4R2_FB31_Pos (31U)
9592#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
9593#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
9595/******************* Bit definition for CAN_F5R2 register *******************/
9596#define CAN_F5R2_FB0_Pos (0U)
9597#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
9598#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
9599#define CAN_F5R2_FB1_Pos (1U)
9600#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
9601#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
9602#define CAN_F5R2_FB2_Pos (2U)
9603#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
9604#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
9605#define CAN_F5R2_FB3_Pos (3U)
9606#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
9607#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
9608#define CAN_F5R2_FB4_Pos (4U)
9609#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
9610#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
9611#define CAN_F5R2_FB5_Pos (5U)
9612#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
9613#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
9614#define CAN_F5R2_FB6_Pos (6U)
9615#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
9616#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
9617#define CAN_F5R2_FB7_Pos (7U)
9618#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
9619#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
9620#define CAN_F5R2_FB8_Pos (8U)
9621#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
9622#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
9623#define CAN_F5R2_FB9_Pos (9U)
9624#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
9625#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
9626#define CAN_F5R2_FB10_Pos (10U)
9627#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
9628#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
9629#define CAN_F5R2_FB11_Pos (11U)
9630#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
9631#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
9632#define CAN_F5R2_FB12_Pos (12U)
9633#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
9634#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
9635#define CAN_F5R2_FB13_Pos (13U)
9636#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
9637#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
9638#define CAN_F5R2_FB14_Pos (14U)
9639#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
9640#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
9641#define CAN_F5R2_FB15_Pos (15U)
9642#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
9643#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
9644#define CAN_F5R2_FB16_Pos (16U)
9645#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
9646#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
9647#define CAN_F5R2_FB17_Pos (17U)
9648#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
9649#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
9650#define CAN_F5R2_FB18_Pos (18U)
9651#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
9652#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
9653#define CAN_F5R2_FB19_Pos (19U)
9654#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
9655#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
9656#define CAN_F5R2_FB20_Pos (20U)
9657#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
9658#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
9659#define CAN_F5R2_FB21_Pos (21U)
9660#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
9661#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
9662#define CAN_F5R2_FB22_Pos (22U)
9663#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
9664#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
9665#define CAN_F5R2_FB23_Pos (23U)
9666#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
9667#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
9668#define CAN_F5R2_FB24_Pos (24U)
9669#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
9670#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
9671#define CAN_F5R2_FB25_Pos (25U)
9672#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
9673#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
9674#define CAN_F5R2_FB26_Pos (26U)
9675#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
9676#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
9677#define CAN_F5R2_FB27_Pos (27U)
9678#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
9679#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
9680#define CAN_F5R2_FB28_Pos (28U)
9681#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
9682#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
9683#define CAN_F5R2_FB29_Pos (29U)
9684#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
9685#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
9686#define CAN_F5R2_FB30_Pos (30U)
9687#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
9688#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
9689#define CAN_F5R2_FB31_Pos (31U)
9690#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
9691#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
9693/******************* Bit definition for CAN_F6R2 register *******************/
9694#define CAN_F6R2_FB0_Pos (0U)
9695#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
9696#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
9697#define CAN_F6R2_FB1_Pos (1U)
9698#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
9699#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
9700#define CAN_F6R2_FB2_Pos (2U)
9701#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
9702#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
9703#define CAN_F6R2_FB3_Pos (3U)
9704#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
9705#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
9706#define CAN_F6R2_FB4_Pos (4U)
9707#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
9708#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
9709#define CAN_F6R2_FB5_Pos (5U)
9710#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
9711#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
9712#define CAN_F6R2_FB6_Pos (6U)
9713#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
9714#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
9715#define CAN_F6R2_FB7_Pos (7U)
9716#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
9717#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
9718#define CAN_F6R2_FB8_Pos (8U)
9719#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
9720#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
9721#define CAN_F6R2_FB9_Pos (9U)
9722#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
9723#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
9724#define CAN_F6R2_FB10_Pos (10U)
9725#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
9726#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
9727#define CAN_F6R2_FB11_Pos (11U)
9728#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
9729#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
9730#define CAN_F6R2_FB12_Pos (12U)
9731#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
9732#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
9733#define CAN_F6R2_FB13_Pos (13U)
9734#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
9735#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
9736#define CAN_F6R2_FB14_Pos (14U)
9737#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
9738#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
9739#define CAN_F6R2_FB15_Pos (15U)
9740#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
9741#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
9742#define CAN_F6R2_FB16_Pos (16U)
9743#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
9744#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
9745#define CAN_F6R2_FB17_Pos (17U)
9746#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
9747#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
9748#define CAN_F6R2_FB18_Pos (18U)
9749#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
9750#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
9751#define CAN_F6R2_FB19_Pos (19U)
9752#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
9753#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
9754#define CAN_F6R2_FB20_Pos (20U)
9755#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
9756#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
9757#define CAN_F6R2_FB21_Pos (21U)
9758#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
9759#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
9760#define CAN_F6R2_FB22_Pos (22U)
9761#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
9762#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
9763#define CAN_F6R2_FB23_Pos (23U)
9764#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
9765#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
9766#define CAN_F6R2_FB24_Pos (24U)
9767#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
9768#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
9769#define CAN_F6R2_FB25_Pos (25U)
9770#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
9771#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
9772#define CAN_F6R2_FB26_Pos (26U)
9773#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
9774#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
9775#define CAN_F6R2_FB27_Pos (27U)
9776#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
9777#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
9778#define CAN_F6R2_FB28_Pos (28U)
9779#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
9780#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
9781#define CAN_F6R2_FB29_Pos (29U)
9782#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
9783#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
9784#define CAN_F6R2_FB30_Pos (30U)
9785#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
9786#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
9787#define CAN_F6R2_FB31_Pos (31U)
9788#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
9789#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
9791/******************* Bit definition for CAN_F7R2 register *******************/
9792#define CAN_F7R2_FB0_Pos (0U)
9793#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
9794#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
9795#define CAN_F7R2_FB1_Pos (1U)
9796#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
9797#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
9798#define CAN_F7R2_FB2_Pos (2U)
9799#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
9800#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
9801#define CAN_F7R2_FB3_Pos (3U)
9802#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
9803#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
9804#define CAN_F7R2_FB4_Pos (4U)
9805#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
9806#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
9807#define CAN_F7R2_FB5_Pos (5U)
9808#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
9809#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
9810#define CAN_F7R2_FB6_Pos (6U)
9811#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
9812#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
9813#define CAN_F7R2_FB7_Pos (7U)
9814#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
9815#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
9816#define CAN_F7R2_FB8_Pos (8U)
9817#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
9818#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
9819#define CAN_F7R2_FB9_Pos (9U)
9820#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
9821#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
9822#define CAN_F7R2_FB10_Pos (10U)
9823#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
9824#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
9825#define CAN_F7R2_FB11_Pos (11U)
9826#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
9827#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
9828#define CAN_F7R2_FB12_Pos (12U)
9829#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
9830#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
9831#define CAN_F7R2_FB13_Pos (13U)
9832#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
9833#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
9834#define CAN_F7R2_FB14_Pos (14U)
9835#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
9836#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
9837#define CAN_F7R2_FB15_Pos (15U)
9838#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
9839#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
9840#define CAN_F7R2_FB16_Pos (16U)
9841#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
9842#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
9843#define CAN_F7R2_FB17_Pos (17U)
9844#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
9845#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
9846#define CAN_F7R2_FB18_Pos (18U)
9847#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
9848#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
9849#define CAN_F7R2_FB19_Pos (19U)
9850#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
9851#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
9852#define CAN_F7R2_FB20_Pos (20U)
9853#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
9854#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
9855#define CAN_F7R2_FB21_Pos (21U)
9856#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
9857#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
9858#define CAN_F7R2_FB22_Pos (22U)
9859#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
9860#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
9861#define CAN_F7R2_FB23_Pos (23U)
9862#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
9863#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
9864#define CAN_F7R2_FB24_Pos (24U)
9865#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
9866#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
9867#define CAN_F7R2_FB25_Pos (25U)
9868#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
9869#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
9870#define CAN_F7R2_FB26_Pos (26U)
9871#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
9872#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
9873#define CAN_F7R2_FB27_Pos (27U)
9874#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
9875#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
9876#define CAN_F7R2_FB28_Pos (28U)
9877#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
9878#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
9879#define CAN_F7R2_FB29_Pos (29U)
9880#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
9881#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
9882#define CAN_F7R2_FB30_Pos (30U)
9883#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
9884#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
9885#define CAN_F7R2_FB31_Pos (31U)
9886#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
9887#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
9889/******************* Bit definition for CAN_F8R2 register *******************/
9890#define CAN_F8R2_FB0_Pos (0U)
9891#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
9892#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
9893#define CAN_F8R2_FB1_Pos (1U)
9894#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
9895#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
9896#define CAN_F8R2_FB2_Pos (2U)
9897#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
9898#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
9899#define CAN_F8R2_FB3_Pos (3U)
9900#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
9901#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
9902#define CAN_F8R2_FB4_Pos (4U)
9903#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
9904#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
9905#define CAN_F8R2_FB5_Pos (5U)
9906#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
9907#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
9908#define CAN_F8R2_FB6_Pos (6U)
9909#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
9910#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
9911#define CAN_F8R2_FB7_Pos (7U)
9912#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
9913#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
9914#define CAN_F8R2_FB8_Pos (8U)
9915#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
9916#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
9917#define CAN_F8R2_FB9_Pos (9U)
9918#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
9919#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
9920#define CAN_F8R2_FB10_Pos (10U)
9921#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
9922#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
9923#define CAN_F8R2_FB11_Pos (11U)
9924#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
9925#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
9926#define CAN_F8R2_FB12_Pos (12U)
9927#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
9928#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
9929#define CAN_F8R2_FB13_Pos (13U)
9930#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
9931#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
9932#define CAN_F8R2_FB14_Pos (14U)
9933#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
9934#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
9935#define CAN_F8R2_FB15_Pos (15U)
9936#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
9937#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
9938#define CAN_F8R2_FB16_Pos (16U)
9939#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
9940#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
9941#define CAN_F8R2_FB17_Pos (17U)
9942#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
9943#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
9944#define CAN_F8R2_FB18_Pos (18U)
9945#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
9946#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
9947#define CAN_F8R2_FB19_Pos (19U)
9948#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
9949#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
9950#define CAN_F8R2_FB20_Pos (20U)
9951#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
9952#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
9953#define CAN_F8R2_FB21_Pos (21U)
9954#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
9955#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
9956#define CAN_F8R2_FB22_Pos (22U)
9957#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
9958#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
9959#define CAN_F8R2_FB23_Pos (23U)
9960#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
9961#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
9962#define CAN_F8R2_FB24_Pos (24U)
9963#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
9964#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
9965#define CAN_F8R2_FB25_Pos (25U)
9966#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
9967#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
9968#define CAN_F8R2_FB26_Pos (26U)
9969#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
9970#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
9971#define CAN_F8R2_FB27_Pos (27U)
9972#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
9973#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
9974#define CAN_F8R2_FB28_Pos (28U)
9975#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
9976#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
9977#define CAN_F8R2_FB29_Pos (29U)
9978#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
9979#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
9980#define CAN_F8R2_FB30_Pos (30U)
9981#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
9982#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
9983#define CAN_F8R2_FB31_Pos (31U)
9984#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
9985#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
9987/******************* Bit definition for CAN_F9R2 register *******************/
9988#define CAN_F9R2_FB0_Pos (0U)
9989#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
9990#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
9991#define CAN_F9R2_FB1_Pos (1U)
9992#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
9993#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
9994#define CAN_F9R2_FB2_Pos (2U)
9995#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
9996#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
9997#define CAN_F9R2_FB3_Pos (3U)
9998#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
9999#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
10000#define CAN_F9R2_FB4_Pos (4U)
10001#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
10002#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
10003#define CAN_F9R2_FB5_Pos (5U)
10004#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
10005#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
10006#define CAN_F9R2_FB6_Pos (6U)
10007#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
10008#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
10009#define CAN_F9R2_FB7_Pos (7U)
10010#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
10011#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
10012#define CAN_F9R2_FB8_Pos (8U)
10013#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
10014#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
10015#define CAN_F9R2_FB9_Pos (9U)
10016#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
10017#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
10018#define CAN_F9R2_FB10_Pos (10U)
10019#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
10020#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
10021#define CAN_F9R2_FB11_Pos (11U)
10022#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
10023#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
10024#define CAN_F9R2_FB12_Pos (12U)
10025#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
10026#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
10027#define CAN_F9R2_FB13_Pos (13U)
10028#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
10029#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
10030#define CAN_F9R2_FB14_Pos (14U)
10031#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
10032#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
10033#define CAN_F9R2_FB15_Pos (15U)
10034#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
10035#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
10036#define CAN_F9R2_FB16_Pos (16U)
10037#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
10038#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
10039#define CAN_F9R2_FB17_Pos (17U)
10040#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
10041#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
10042#define CAN_F9R2_FB18_Pos (18U)
10043#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
10044#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
10045#define CAN_F9R2_FB19_Pos (19U)
10046#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
10047#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
10048#define CAN_F9R2_FB20_Pos (20U)
10049#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
10050#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
10051#define CAN_F9R2_FB21_Pos (21U)
10052#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
10053#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
10054#define CAN_F9R2_FB22_Pos (22U)
10055#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
10056#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
10057#define CAN_F9R2_FB23_Pos (23U)
10058#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
10059#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
10060#define CAN_F9R2_FB24_Pos (24U)
10061#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
10062#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
10063#define CAN_F9R2_FB25_Pos (25U)
10064#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
10065#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
10066#define CAN_F9R2_FB26_Pos (26U)
10067#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
10068#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
10069#define CAN_F9R2_FB27_Pos (27U)
10070#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
10071#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
10072#define CAN_F9R2_FB28_Pos (28U)
10073#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
10074#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
10075#define CAN_F9R2_FB29_Pos (29U)
10076#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
10077#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
10078#define CAN_F9R2_FB30_Pos (30U)
10079#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
10080#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
10081#define CAN_F9R2_FB31_Pos (31U)
10082#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
10083#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
10085/******************* Bit definition for CAN_F10R2 register ******************/
10086#define CAN_F10R2_FB0_Pos (0U)
10087#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
10088#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
10089#define CAN_F10R2_FB1_Pos (1U)
10090#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
10091#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
10092#define CAN_F10R2_FB2_Pos (2U)
10093#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
10094#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
10095#define CAN_F10R2_FB3_Pos (3U)
10096#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
10097#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
10098#define CAN_F10R2_FB4_Pos (4U)
10099#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
10100#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
10101#define CAN_F10R2_FB5_Pos (5U)
10102#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
10103#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
10104#define CAN_F10R2_FB6_Pos (6U)
10105#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
10106#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
10107#define CAN_F10R2_FB7_Pos (7U)
10108#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
10109#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
10110#define CAN_F10R2_FB8_Pos (8U)
10111#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
10112#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
10113#define CAN_F10R2_FB9_Pos (9U)
10114#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
10115#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
10116#define CAN_F10R2_FB10_Pos (10U)
10117#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
10118#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
10119#define CAN_F10R2_FB11_Pos (11U)
10120#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
10121#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
10122#define CAN_F10R2_FB12_Pos (12U)
10123#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
10124#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
10125#define CAN_F10R2_FB13_Pos (13U)
10126#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
10127#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
10128#define CAN_F10R2_FB14_Pos (14U)
10129#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
10130#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
10131#define CAN_F10R2_FB15_Pos (15U)
10132#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
10133#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
10134#define CAN_F10R2_FB16_Pos (16U)
10135#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
10136#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
10137#define CAN_F10R2_FB17_Pos (17U)
10138#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
10139#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
10140#define CAN_F10R2_FB18_Pos (18U)
10141#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
10142#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
10143#define CAN_F10R2_FB19_Pos (19U)
10144#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
10145#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
10146#define CAN_F10R2_FB20_Pos (20U)
10147#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
10148#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
10149#define CAN_F10R2_FB21_Pos (21U)
10150#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
10151#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
10152#define CAN_F10R2_FB22_Pos (22U)
10153#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
10154#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
10155#define CAN_F10R2_FB23_Pos (23U)
10156#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
10157#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
10158#define CAN_F10R2_FB24_Pos (24U)
10159#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
10160#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
10161#define CAN_F10R2_FB25_Pos (25U)
10162#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
10163#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
10164#define CAN_F10R2_FB26_Pos (26U)
10165#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
10166#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
10167#define CAN_F10R2_FB27_Pos (27U)
10168#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
10169#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
10170#define CAN_F10R2_FB28_Pos (28U)
10171#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
10172#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
10173#define CAN_F10R2_FB29_Pos (29U)
10174#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
10175#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
10176#define CAN_F10R2_FB30_Pos (30U)
10177#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
10178#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
10179#define CAN_F10R2_FB31_Pos (31U)
10180#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
10181#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
10183/******************* Bit definition for CAN_F11R2 register ******************/
10184#define CAN_F11R2_FB0_Pos (0U)
10185#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
10186#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
10187#define CAN_F11R2_FB1_Pos (1U)
10188#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
10189#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
10190#define CAN_F11R2_FB2_Pos (2U)
10191#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
10192#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
10193#define CAN_F11R2_FB3_Pos (3U)
10194#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
10195#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
10196#define CAN_F11R2_FB4_Pos (4U)
10197#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
10198#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
10199#define CAN_F11R2_FB5_Pos (5U)
10200#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
10201#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
10202#define CAN_F11R2_FB6_Pos (6U)
10203#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
10204#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
10205#define CAN_F11R2_FB7_Pos (7U)
10206#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
10207#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
10208#define CAN_F11R2_FB8_Pos (8U)
10209#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
10210#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
10211#define CAN_F11R2_FB9_Pos (9U)
10212#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
10213#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
10214#define CAN_F11R2_FB10_Pos (10U)
10215#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
10216#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
10217#define CAN_F11R2_FB11_Pos (11U)
10218#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
10219#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
10220#define CAN_F11R2_FB12_Pos (12U)
10221#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
10222#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
10223#define CAN_F11R2_FB13_Pos (13U)
10224#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
10225#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
10226#define CAN_F11R2_FB14_Pos (14U)
10227#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
10228#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
10229#define CAN_F11R2_FB15_Pos (15U)
10230#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
10231#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
10232#define CAN_F11R2_FB16_Pos (16U)
10233#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
10234#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
10235#define CAN_F11R2_FB17_Pos (17U)
10236#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
10237#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
10238#define CAN_F11R2_FB18_Pos (18U)
10239#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
10240#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
10241#define CAN_F11R2_FB19_Pos (19U)
10242#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
10243#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
10244#define CAN_F11R2_FB20_Pos (20U)
10245#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
10246#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
10247#define CAN_F11R2_FB21_Pos (21U)
10248#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
10249#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
10250#define CAN_F11R2_FB22_Pos (22U)
10251#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
10252#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
10253#define CAN_F11R2_FB23_Pos (23U)
10254#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
10255#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
10256#define CAN_F11R2_FB24_Pos (24U)
10257#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
10258#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
10259#define CAN_F11R2_FB25_Pos (25U)
10260#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
10261#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
10262#define CAN_F11R2_FB26_Pos (26U)
10263#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
10264#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
10265#define CAN_F11R2_FB27_Pos (27U)
10266#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
10267#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
10268#define CAN_F11R2_FB28_Pos (28U)
10269#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
10270#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
10271#define CAN_F11R2_FB29_Pos (29U)
10272#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
10273#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
10274#define CAN_F11R2_FB30_Pos (30U)
10275#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
10276#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
10277#define CAN_F11R2_FB31_Pos (31U)
10278#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
10279#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
10281/******************* Bit definition for CAN_F12R2 register ******************/
10282#define CAN_F12R2_FB0_Pos (0U)
10283#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
10284#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
10285#define CAN_F12R2_FB1_Pos (1U)
10286#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
10287#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
10288#define CAN_F12R2_FB2_Pos (2U)
10289#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
10290#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
10291#define CAN_F12R2_FB3_Pos (3U)
10292#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
10293#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
10294#define CAN_F12R2_FB4_Pos (4U)
10295#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
10296#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
10297#define CAN_F12R2_FB5_Pos (5U)
10298#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
10299#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
10300#define CAN_F12R2_FB6_Pos (6U)
10301#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
10302#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
10303#define CAN_F12R2_FB7_Pos (7U)
10304#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
10305#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
10306#define CAN_F12R2_FB8_Pos (8U)
10307#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
10308#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
10309#define CAN_F12R2_FB9_Pos (9U)
10310#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
10311#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
10312#define CAN_F12R2_FB10_Pos (10U)
10313#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
10314#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
10315#define CAN_F12R2_FB11_Pos (11U)
10316#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
10317#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
10318#define CAN_F12R2_FB12_Pos (12U)
10319#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
10320#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
10321#define CAN_F12R2_FB13_Pos (13U)
10322#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
10323#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
10324#define CAN_F12R2_FB14_Pos (14U)
10325#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
10326#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
10327#define CAN_F12R2_FB15_Pos (15U)
10328#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
10329#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
10330#define CAN_F12R2_FB16_Pos (16U)
10331#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
10332#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
10333#define CAN_F12R2_FB17_Pos (17U)
10334#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
10335#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
10336#define CAN_F12R2_FB18_Pos (18U)
10337#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
10338#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
10339#define CAN_F12R2_FB19_Pos (19U)
10340#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
10341#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
10342#define CAN_F12R2_FB20_Pos (20U)
10343#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
10344#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
10345#define CAN_F12R2_FB21_Pos (21U)
10346#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
10347#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
10348#define CAN_F12R2_FB22_Pos (22U)
10349#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
10350#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
10351#define CAN_F12R2_FB23_Pos (23U)
10352#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
10353#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
10354#define CAN_F12R2_FB24_Pos (24U)
10355#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
10356#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
10357#define CAN_F12R2_FB25_Pos (25U)
10358#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
10359#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
10360#define CAN_F12R2_FB26_Pos (26U)
10361#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
10362#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
10363#define CAN_F12R2_FB27_Pos (27U)
10364#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
10365#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
10366#define CAN_F12R2_FB28_Pos (28U)
10367#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
10368#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
10369#define CAN_F12R2_FB29_Pos (29U)
10370#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
10371#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
10372#define CAN_F12R2_FB30_Pos (30U)
10373#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
10374#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
10375#define CAN_F12R2_FB31_Pos (31U)
10376#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
10377#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
10379/******************* Bit definition for CAN_F13R2 register ******************/
10380#define CAN_F13R2_FB0_Pos (0U)
10381#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
10382#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
10383#define CAN_F13R2_FB1_Pos (1U)
10384#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
10385#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
10386#define CAN_F13R2_FB2_Pos (2U)
10387#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
10388#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
10389#define CAN_F13R2_FB3_Pos (3U)
10390#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
10391#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
10392#define CAN_F13R2_FB4_Pos (4U)
10393#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
10394#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
10395#define CAN_F13R2_FB5_Pos (5U)
10396#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
10397#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
10398#define CAN_F13R2_FB6_Pos (6U)
10399#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
10400#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
10401#define CAN_F13R2_FB7_Pos (7U)
10402#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
10403#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
10404#define CAN_F13R2_FB8_Pos (8U)
10405#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
10406#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
10407#define CAN_F13R2_FB9_Pos (9U)
10408#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
10409#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
10410#define CAN_F13R2_FB10_Pos (10U)
10411#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
10412#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
10413#define CAN_F13R2_FB11_Pos (11U)
10414#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
10415#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
10416#define CAN_F13R2_FB12_Pos (12U)
10417#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
10418#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
10419#define CAN_F13R2_FB13_Pos (13U)
10420#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
10421#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
10422#define CAN_F13R2_FB14_Pos (14U)
10423#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
10424#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
10425#define CAN_F13R2_FB15_Pos (15U)
10426#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
10427#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
10428#define CAN_F13R2_FB16_Pos (16U)
10429#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
10430#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
10431#define CAN_F13R2_FB17_Pos (17U)
10432#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
10433#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
10434#define CAN_F13R2_FB18_Pos (18U)
10435#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
10436#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
10437#define CAN_F13R2_FB19_Pos (19U)
10438#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
10439#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
10440#define CAN_F13R2_FB20_Pos (20U)
10441#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
10442#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
10443#define CAN_F13R2_FB21_Pos (21U)
10444#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
10445#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
10446#define CAN_F13R2_FB22_Pos (22U)
10447#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
10448#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
10449#define CAN_F13R2_FB23_Pos (23U)
10450#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
10451#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
10452#define CAN_F13R2_FB24_Pos (24U)
10453#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
10454#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
10455#define CAN_F13R2_FB25_Pos (25U)
10456#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
10457#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
10458#define CAN_F13R2_FB26_Pos (26U)
10459#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
10460#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
10461#define CAN_F13R2_FB27_Pos (27U)
10462#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
10463#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
10464#define CAN_F13R2_FB28_Pos (28U)
10465#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
10466#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
10467#define CAN_F13R2_FB29_Pos (29U)
10468#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
10469#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
10470#define CAN_F13R2_FB30_Pos (30U)
10471#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
10472#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
10473#define CAN_F13R2_FB31_Pos (31U)
10474#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
10475#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
10477/******************* Bit definition for CAN_F14R2 register ******************/
10478#define CAN_F14R2_FB0_Pos (0U)
10479#define CAN_F14R2_FB0_Msk (0x1UL << CAN_F14R2_FB0_Pos)
10480#define CAN_F14R2_FB0 CAN_F14R2_FB0_Msk
10481#define CAN_F14R2_FB1_Pos (1U)
10482#define CAN_F14R2_FB1_Msk (0x1UL << CAN_F14R2_FB1_Pos)
10483#define CAN_F14R2_FB1 CAN_F14R2_FB1_Msk
10484#define CAN_F14R2_FB2_Pos (2U)
10485#define CAN_F14R2_FB2_Msk (0x1UL << CAN_F14R2_FB2_Pos)
10486#define CAN_F14R2_FB2 CAN_F14R2_FB2_Msk
10487#define CAN_F14R2_FB3_Pos (3U)
10488#define CAN_F14R2_FB3_Msk (0x1UL << CAN_F14R2_FB3_Pos)
10489#define CAN_F14R2_FB3 CAN_F14R2_FB3_Msk
10490#define CAN_F14R2_FB4_Pos (4U)
10491#define CAN_F14R2_FB4_Msk (0x1UL << CAN_F14R2_FB4_Pos)
10492#define CAN_F14R2_FB4 CAN_F14R2_FB4_Msk
10493#define CAN_F14R2_FB5_Pos (5U)
10494#define CAN_F14R2_FB5_Msk (0x1UL << CAN_F14R2_FB5_Pos)
10495#define CAN_F14R2_FB5 CAN_F14R2_FB5_Msk
10496#define CAN_F14R2_FB6_Pos (6U)
10497#define CAN_F14R2_FB6_Msk (0x1UL << CAN_F14R2_FB6_Pos)
10498#define CAN_F14R2_FB6 CAN_F14R2_FB6_Msk
10499#define CAN_F14R2_FB7_Pos (7U)
10500#define CAN_F14R2_FB7_Msk (0x1UL << CAN_F14R2_FB7_Pos)
10501#define CAN_F14R2_FB7 CAN_F14R2_FB7_Msk
10502#define CAN_F14R2_FB8_Pos (8U)
10503#define CAN_F14R2_FB8_Msk (0x1UL << CAN_F14R2_FB8_Pos)
10504#define CAN_F14R2_FB8 CAN_F14R2_FB8_Msk
10505#define CAN_F14R2_FB9_Pos (9U)
10506#define CAN_F14R2_FB9_Msk (0x1UL << CAN_F14R2_FB9_Pos)
10507#define CAN_F14R2_FB9 CAN_F14R2_FB9_Msk
10508#define CAN_F14R2_FB10_Pos (10U)
10509#define CAN_F14R2_FB10_Msk (0x1UL << CAN_F14R2_FB10_Pos)
10510#define CAN_F14R2_FB10 CAN_F14R2_FB10_Msk
10511#define CAN_F14R2_FB11_Pos (11U)
10512#define CAN_F14R2_FB11_Msk (0x1UL << CAN_F14R2_FB11_Pos)
10513#define CAN_F14R2_FB11 CAN_F14R2_FB11_Msk
10514#define CAN_F14R2_FB12_Pos (12U)
10515#define CAN_F14R2_FB12_Msk (0x1UL << CAN_F14R2_FB12_Pos)
10516#define CAN_F14R2_FB12 CAN_F14R2_FB12_Msk
10517#define CAN_F14R2_FB13_Pos (13U)
10518#define CAN_F14R2_FB13_Msk (0x1UL << CAN_F14R2_FB13_Pos)
10519#define CAN_F14R2_FB13 CAN_F14R2_FB13_Msk
10520#define CAN_F14R2_FB14_Pos (14U)
10521#define CAN_F14R2_FB14_Msk (0x1UL << CAN_F14R2_FB14_Pos)
10522#define CAN_F14R2_FB14 CAN_F14R2_FB14_Msk
10523#define CAN_F14R2_FB15_Pos (15U)
10524#define CAN_F14R2_FB15_Msk (0x1UL << CAN_F14R2_FB15_Pos)
10525#define CAN_F14R2_FB15 CAN_F14R2_FB15_Msk
10526#define CAN_F14R2_FB16_Pos (16U)
10527#define CAN_F14R2_FB16_Msk (0x1UL << CAN_F14R2_FB16_Pos)
10528#define CAN_F14R2_FB16 CAN_F14R2_FB16_Msk
10529#define CAN_F14R2_FB17_Pos (17U)
10530#define CAN_F14R2_FB17_Msk (0x1UL << CAN_F14R2_FB17_Pos)
10531#define CAN_F14R2_FB17 CAN_F14R2_FB17_Msk
10532#define CAN_F14R2_FB18_Pos (18U)
10533#define CAN_F14R2_FB18_Msk (0x1UL << CAN_F14R2_FB18_Pos)
10534#define CAN_F14R2_FB18 CAN_F14R2_FB18_Msk
10535#define CAN_F14R2_FB19_Pos (19U)
10536#define CAN_F14R2_FB19_Msk (0x1UL << CAN_F14R2_FB19_Pos)
10537#define CAN_F14R2_FB19 CAN_F14R2_FB19_Msk
10538#define CAN_F14R2_FB20_Pos (20U)
10539#define CAN_F14R2_FB20_Msk (0x1UL << CAN_F14R2_FB20_Pos)
10540#define CAN_F14R2_FB20 CAN_F14R2_FB20_Msk
10541#define CAN_F14R2_FB21_Pos (21U)
10542#define CAN_F14R2_FB21_Msk (0x1UL << CAN_F14R2_FB21_Pos)
10543#define CAN_F14R2_FB21 CAN_F14R2_FB21_Msk
10544#define CAN_F14R2_FB22_Pos (22U)
10545#define CAN_F14R2_FB22_Msk (0x1UL << CAN_F14R2_FB22_Pos)
10546#define CAN_F14R2_FB22 CAN_F14R2_FB22_Msk
10547#define CAN_F14R2_FB23_Pos (23U)
10548#define CAN_F14R2_FB23_Msk (0x1UL << CAN_F14R2_FB23_Pos)
10549#define CAN_F14R2_FB23 CAN_F14R2_FB23_Msk
10550#define CAN_F14R2_FB24_Pos (24U)
10551#define CAN_F14R2_FB24_Msk (0x1UL << CAN_F14R2_FB24_Pos)
10552#define CAN_F14R2_FB24 CAN_F14R2_FB24_Msk
10553#define CAN_F14R2_FB25_Pos (25U)
10554#define CAN_F14R2_FB25_Msk (0x1UL << CAN_F14R2_FB25_Pos)
10555#define CAN_F14R2_FB25 CAN_F14R2_FB25_Msk
10556#define CAN_F14R2_FB26_Pos (26U)
10557#define CAN_F14R2_FB26_Msk (0x1UL << CAN_F14R2_FB26_Pos)
10558#define CAN_F14R2_FB26 CAN_F14R2_FB26_Msk
10559#define CAN_F14R2_FB27_Pos (27U)
10560#define CAN_F14R2_FB27_Msk (0x1UL << CAN_F14R2_FB27_Pos)
10561#define CAN_F14R2_FB27 CAN_F14R2_FB27_Msk
10562#define CAN_F14R2_FB28_Pos (28U)
10563#define CAN_F14R2_FB28_Msk (0x1UL << CAN_F14R2_FB28_Pos)
10564#define CAN_F14R2_FB28 CAN_F14R2_FB28_Msk
10565#define CAN_F14R2_FB29_Pos (29U)
10566#define CAN_F14R2_FB29_Msk (0x1UL << CAN_F14R2_FB29_Pos)
10567#define CAN_F14R2_FB29 CAN_F14R2_FB29_Msk
10568#define CAN_F14R2_FB30_Pos (30U)
10569#define CAN_F14R2_FB30_Msk (0x1UL << CAN_F14R2_FB30_Pos)
10570#define CAN_F14R2_FB30 CAN_F14R2_FB30_Msk
10571#define CAN_F14R2_FB31_Pos (31U)
10572#define CAN_F14R2_FB31_Msk (0x1UL << CAN_F14R2_FB31_Pos)
10573#define CAN_F14R2_FB31 CAN_F14R2_FB31_Msk
10575/******************* Bit definition for CAN_F15R2 register ******************/
10576#define CAN_F15R2_FB0_Pos (0U)
10577#define CAN_F15R2_FB0_Msk (0x1UL << CAN_F15R2_FB0_Pos)
10578#define CAN_F15R2_FB0 CAN_F15R2_FB0_Msk
10579#define CAN_F15R2_FB1_Pos (1U)
10580#define CAN_F15R2_FB1_Msk (0x1UL << CAN_F15R2_FB1_Pos)
10581#define CAN_F15R2_FB1 CAN_F15R2_FB1_Msk
10582#define CAN_F15R2_FB2_Pos (2U)
10583#define CAN_F15R2_FB2_Msk (0x1UL << CAN_F15R2_FB2_Pos)
10584#define CAN_F15R2_FB2 CAN_F15R2_FB2_Msk
10585#define CAN_F15R2_FB3_Pos (3U)
10586#define CAN_F15R2_FB3_Msk (0x1UL << CAN_F15R2_FB3_Pos)
10587#define CAN_F15R2_FB3 CAN_F15R2_FB3_Msk
10588#define CAN_F15R2_FB4_Pos (4U)
10589#define CAN_F15R2_FB4_Msk (0x1UL << CAN_F15R2_FB4_Pos)
10590#define CAN_F15R2_FB4 CAN_F15R2_FB4_Msk
10591#define CAN_F15R2_FB5_Pos (5U)
10592#define CAN_F15R2_FB5_Msk (0x1UL << CAN_F15R2_FB5_Pos)
10593#define CAN_F15R2_FB5 CAN_F15R2_FB5_Msk
10594#define CAN_F15R2_FB6_Pos (6U)
10595#define CAN_F15R2_FB6_Msk (0x1UL << CAN_F15R2_FB6_Pos)
10596#define CAN_F15R2_FB6 CAN_F15R2_FB6_Msk
10597#define CAN_F15R2_FB7_Pos (7U)
10598#define CAN_F15R2_FB7_Msk (0x1UL << CAN_F15R2_FB7_Pos)
10599#define CAN_F15R2_FB7 CAN_F15R2_FB7_Msk
10600#define CAN_F15R2_FB8_Pos (8U)
10601#define CAN_F15R2_FB8_Msk (0x1UL << CAN_F15R2_FB8_Pos)
10602#define CAN_F15R2_FB8 CAN_F15R2_FB8_Msk
10603#define CAN_F15R2_FB9_Pos (9U)
10604#define CAN_F15R2_FB9_Msk (0x1UL << CAN_F15R2_FB9_Pos)
10605#define CAN_F15R2_FB9 CAN_F15R2_FB9_Msk
10606#define CAN_F15R2_FB10_Pos (10U)
10607#define CAN_F15R2_FB10_Msk (0x1UL << CAN_F15R2_FB10_Pos)
10608#define CAN_F15R2_FB10 CAN_F15R2_FB10_Msk
10609#define CAN_F15R2_FB11_Pos (11U)
10610#define CAN_F15R2_FB11_Msk (0x1UL << CAN_F15R2_FB11_Pos)
10611#define CAN_F15R2_FB11 CAN_F15R2_FB11_Msk
10612#define CAN_F15R2_FB12_Pos (12U)
10613#define CAN_F15R2_FB12_Msk (0x1UL << CAN_F15R2_FB12_Pos)
10614#define CAN_F15R2_FB12 CAN_F15R2_FB12_Msk
10615#define CAN_F15R2_FB13_Pos (13U)
10616#define CAN_F15R2_FB13_Msk (0x1UL << CAN_F15R2_FB13_Pos)
10617#define CAN_F15R2_FB13 CAN_F15R2_FB13_Msk
10618#define CAN_F15R2_FB14_Pos (14U)
10619#define CAN_F15R2_FB14_Msk (0x1UL << CAN_F15R2_FB14_Pos)
10620#define CAN_F15R2_FB14 CAN_F15R2_FB14_Msk
10621#define CAN_F15R2_FB15_Pos (15U)
10622#define CAN_F15R2_FB15_Msk (0x1UL << CAN_F15R2_FB15_Pos)
10623#define CAN_F15R2_FB15 CAN_F15R2_FB15_Msk
10624#define CAN_F15R2_FB16_Pos (16U)
10625#define CAN_F15R2_FB16_Msk (0x1UL << CAN_F15R2_FB16_Pos)
10626#define CAN_F15R2_FB16 CAN_F15R2_FB16_Msk
10627#define CAN_F15R2_FB17_Pos (17U)
10628#define CAN_F15R2_FB17_Msk (0x1UL << CAN_F15R2_FB17_Pos)
10629#define CAN_F15R2_FB17 CAN_F15R2_FB17_Msk
10630#define CAN_F15R2_FB18_Pos (18U)
10631#define CAN_F15R2_FB18_Msk (0x1UL << CAN_F15R2_FB18_Pos)
10632#define CAN_F15R2_FB18 CAN_F15R2_FB18_Msk
10633#define CAN_F15R2_FB19_Pos (19U)
10634#define CAN_F15R2_FB19_Msk (0x1UL << CAN_F15R2_FB19_Pos)
10635#define CAN_F15R2_FB19 CAN_F15R2_FB19_Msk
10636#define CAN_F15R2_FB20_Pos (20U)
10637#define CAN_F15R2_FB20_Msk (0x1UL << CAN_F15R2_FB20_Pos)
10638#define CAN_F15R2_FB20 CAN_F15R2_FB20_Msk
10639#define CAN_F15R2_FB21_Pos (21U)
10640#define CAN_F15R2_FB21_Msk (0x1UL << CAN_F15R2_FB21_Pos)
10641#define CAN_F15R2_FB21 CAN_F15R2_FB21_Msk
10642#define CAN_F15R2_FB22_Pos (22U)
10643#define CAN_F15R2_FB22_Msk (0x1UL << CAN_F15R2_FB22_Pos)
10644#define CAN_F15R2_FB22 CAN_F15R2_FB22_Msk
10645#define CAN_F15R2_FB23_Pos (23U)
10646#define CAN_F15R2_FB23_Msk (0x1UL << CAN_F15R2_FB23_Pos)
10647#define CAN_F15R2_FB23 CAN_F15R2_FB23_Msk
10648#define CAN_F15R2_FB24_Pos (24U)
10649#define CAN_F15R2_FB24_Msk (0x1UL << CAN_F15R2_FB24_Pos)
10650#define CAN_F15R2_FB24 CAN_F15R2_FB24_Msk
10651#define CAN_F15R2_FB25_Pos (25U)
10652#define CAN_F15R2_FB25_Msk (0x1UL << CAN_F15R2_FB25_Pos)
10653#define CAN_F15R2_FB25 CAN_F15R2_FB25_Msk
10654#define CAN_F15R2_FB26_Pos (26U)
10655#define CAN_F15R2_FB26_Msk (0x1UL << CAN_F15R2_FB26_Pos)
10656#define CAN_F15R2_FB26 CAN_F15R2_FB26_Msk
10657#define CAN_F15R2_FB27_Pos (27U)
10658#define CAN_F15R2_FB27_Msk (0x1UL << CAN_F15R2_FB27_Pos)
10659#define CAN_F15R2_FB27 CAN_F15R2_FB27_Msk
10660#define CAN_F15R2_FB28_Pos (28U)
10661#define CAN_F15R2_FB28_Msk (0x1UL << CAN_F15R2_FB28_Pos)
10662#define CAN_F15R2_FB28 CAN_F15R2_FB28_Msk
10663#define CAN_F15R2_FB29_Pos (29U)
10664#define CAN_F15R2_FB29_Msk (0x1UL << CAN_F15R2_FB29_Pos)
10665#define CAN_F15R2_FB29 CAN_F15R2_FB29_Msk
10666#define CAN_F15R2_FB30_Pos (30U)
10667#define CAN_F15R2_FB30_Msk (0x1UL << CAN_F15R2_FB30_Pos)
10668#define CAN_F15R2_FB30 CAN_F15R2_FB30_Msk
10669#define CAN_F15R2_FB31_Pos (31U)
10670#define CAN_F15R2_FB31_Msk (0x1UL << CAN_F15R2_FB31_Pos)
10671#define CAN_F15R2_FB31 CAN_F15R2_FB31_Msk
10673/******************* Bit definition for CAN_F16R2 register ******************/
10674#define CAN_F16R2_FB0_Pos (0U)
10675#define CAN_F16R2_FB0_Msk (0x1UL << CAN_F16R2_FB0_Pos)
10676#define CAN_F16R2_FB0 CAN_F16R2_FB0_Msk
10677#define CAN_F16R2_FB1_Pos (1U)
10678#define CAN_F16R2_FB1_Msk (0x1UL << CAN_F16R2_FB1_Pos)
10679#define CAN_F16R2_FB1 CAN_F16R2_FB1_Msk
10680#define CAN_F16R2_FB2_Pos (2U)
10681#define CAN_F16R2_FB2_Msk (0x1UL << CAN_F16R2_FB2_Pos)
10682#define CAN_F16R2_FB2 CAN_F16R2_FB2_Msk
10683#define CAN_F16R2_FB3_Pos (3U)
10684#define CAN_F16R2_FB3_Msk (0x1UL << CAN_F16R2_FB3_Pos)
10685#define CAN_F16R2_FB3 CAN_F16R2_FB3_Msk
10686#define CAN_F16R2_FB4_Pos (4U)
10687#define CAN_F16R2_FB4_Msk (0x1UL << CAN_F16R2_FB4_Pos)
10688#define CAN_F16R2_FB4 CAN_F16R2_FB4_Msk
10689#define CAN_F16R2_FB5_Pos (5U)
10690#define CAN_F16R2_FB5_Msk (0x1UL << CAN_F16R2_FB5_Pos)
10691#define CAN_F16R2_FB5 CAN_F16R2_FB5_Msk
10692#define CAN_F16R2_FB6_Pos (6U)
10693#define CAN_F16R2_FB6_Msk (0x1UL << CAN_F16R2_FB6_Pos)
10694#define CAN_F16R2_FB6 CAN_F16R2_FB6_Msk
10695#define CAN_F16R2_FB7_Pos (7U)
10696#define CAN_F16R2_FB7_Msk (0x1UL << CAN_F16R2_FB7_Pos)
10697#define CAN_F16R2_FB7 CAN_F16R2_FB7_Msk
10698#define CAN_F16R2_FB8_Pos (8U)
10699#define CAN_F16R2_FB8_Msk (0x1UL << CAN_F16R2_FB8_Pos)
10700#define CAN_F16R2_FB8 CAN_F16R2_FB8_Msk
10701#define CAN_F16R2_FB9_Pos (9U)
10702#define CAN_F16R2_FB9_Msk (0x1UL << CAN_F16R2_FB9_Pos)
10703#define CAN_F16R2_FB9 CAN_F16R2_FB9_Msk
10704#define CAN_F16R2_FB10_Pos (10U)
10705#define CAN_F16R2_FB10_Msk (0x1UL << CAN_F16R2_FB10_Pos)
10706#define CAN_F16R2_FB10 CAN_F16R2_FB10_Msk
10707#define CAN_F16R2_FB11_Pos (11U)
10708#define CAN_F16R2_FB11_Msk (0x1UL << CAN_F16R2_FB11_Pos)
10709#define CAN_F16R2_FB11 CAN_F16R2_FB11_Msk
10710#define CAN_F16R2_FB12_Pos (12U)
10711#define CAN_F16R2_FB12_Msk (0x1UL << CAN_F16R2_FB12_Pos)
10712#define CAN_F16R2_FB12 CAN_F16R2_FB12_Msk
10713#define CAN_F16R2_FB13_Pos (13U)
10714#define CAN_F16R2_FB13_Msk (0x1UL << CAN_F16R2_FB13_Pos)
10715#define CAN_F16R2_FB13 CAN_F16R2_FB13_Msk
10716#define CAN_F16R2_FB14_Pos (14U)
10717#define CAN_F16R2_FB14_Msk (0x1UL << CAN_F16R2_FB14_Pos)
10718#define CAN_F16R2_FB14 CAN_F16R2_FB14_Msk
10719#define CAN_F16R2_FB15_Pos (15U)
10720#define CAN_F16R2_FB15_Msk (0x1UL << CAN_F16R2_FB15_Pos)
10721#define CAN_F16R2_FB15 CAN_F16R2_FB15_Msk
10722#define CAN_F16R2_FB16_Pos (16U)
10723#define CAN_F16R2_FB16_Msk (0x1UL << CAN_F16R2_FB16_Pos)
10724#define CAN_F16R2_FB16 CAN_F16R2_FB16_Msk
10725#define CAN_F16R2_FB17_Pos (17U)
10726#define CAN_F16R2_FB17_Msk (0x1UL << CAN_F16R2_FB17_Pos)
10727#define CAN_F16R2_FB17 CAN_F16R2_FB17_Msk
10728#define CAN_F16R2_FB18_Pos (18U)
10729#define CAN_F16R2_FB18_Msk (0x1UL << CAN_F16R2_FB18_Pos)
10730#define CAN_F16R2_FB18 CAN_F16R2_FB18_Msk
10731#define CAN_F16R2_FB19_Pos (19U)
10732#define CAN_F16R2_FB19_Msk (0x1UL << CAN_F16R2_FB19_Pos)
10733#define CAN_F16R2_FB19 CAN_F16R2_FB19_Msk
10734#define CAN_F16R2_FB20_Pos (20U)
10735#define CAN_F16R2_FB20_Msk (0x1UL << CAN_F16R2_FB20_Pos)
10736#define CAN_F16R2_FB20 CAN_F16R2_FB20_Msk
10737#define CAN_F16R2_FB21_Pos (21U)
10738#define CAN_F16R2_FB21_Msk (0x1UL << CAN_F16R2_FB21_Pos)
10739#define CAN_F16R2_FB21 CAN_F16R2_FB21_Msk
10740#define CAN_F16R2_FB22_Pos (22U)
10741#define CAN_F16R2_FB22_Msk (0x1UL << CAN_F16R2_FB22_Pos)
10742#define CAN_F16R2_FB22 CAN_F16R2_FB22_Msk
10743#define CAN_F16R2_FB23_Pos (23U)
10744#define CAN_F16R2_FB23_Msk (0x1UL << CAN_F16R2_FB23_Pos)
10745#define CAN_F16R2_FB23 CAN_F16R2_FB23_Msk
10746#define CAN_F16R2_FB24_Pos (24U)
10747#define CAN_F16R2_FB24_Msk (0x1UL << CAN_F16R2_FB24_Pos)
10748#define CAN_F16R2_FB24 CAN_F16R2_FB24_Msk
10749#define CAN_F16R2_FB25_Pos (25U)
10750#define CAN_F16R2_FB25_Msk (0x1UL << CAN_F16R2_FB25_Pos)
10751#define CAN_F16R2_FB25 CAN_F16R2_FB25_Msk
10752#define CAN_F16R2_FB26_Pos (26U)
10753#define CAN_F16R2_FB26_Msk (0x1UL << CAN_F16R2_FB26_Pos)
10754#define CAN_F16R2_FB26 CAN_F16R2_FB26_Msk
10755#define CAN_F16R2_FB27_Pos (27U)
10756#define CAN_F16R2_FB27_Msk (0x1UL << CAN_F16R2_FB27_Pos)
10757#define CAN_F16R2_FB27 CAN_F16R2_FB27_Msk
10758#define CAN_F16R2_FB28_Pos (28U)
10759#define CAN_F16R2_FB28_Msk (0x1UL << CAN_F16R2_FB28_Pos)
10760#define CAN_F16R2_FB28 CAN_F16R2_FB28_Msk
10761#define CAN_F16R2_FB29_Pos (29U)
10762#define CAN_F16R2_FB29_Msk (0x1UL << CAN_F16R2_FB29_Pos)
10763#define CAN_F16R2_FB29 CAN_F16R2_FB29_Msk
10764#define CAN_F16R2_FB30_Pos (30U)
10765#define CAN_F16R2_FB30_Msk (0x1UL << CAN_F16R2_FB30_Pos)
10766#define CAN_F16R2_FB30 CAN_F16R2_FB30_Msk
10767#define CAN_F16R2_FB31_Pos (31U)
10768#define CAN_F16R2_FB31_Msk (0x1UL << CAN_F16R2_FB31_Pos)
10769#define CAN_F16R2_FB31 CAN_F16R2_FB31_Msk
10771/******************* Bit definition for CAN_F17R2 register ******************/
10772#define CAN_F17R2_FB0_Pos (0U)
10773#define CAN_F17R2_FB0_Msk (0x1UL << CAN_F17R2_FB0_Pos)
10774#define CAN_F17R2_FB0 CAN_F17R2_FB0_Msk
10775#define CAN_F17R2_FB1_Pos (1U)
10776#define CAN_F17R2_FB1_Msk (0x1UL << CAN_F17R2_FB1_Pos)
10777#define CAN_F17R2_FB1 CAN_F17R2_FB1_Msk
10778#define CAN_F17R2_FB2_Pos (2U)
10779#define CAN_F17R2_FB2_Msk (0x1UL << CAN_F17R2_FB2_Pos)
10780#define CAN_F17R2_FB2 CAN_F17R2_FB2_Msk
10781#define CAN_F17R2_FB3_Pos (3U)
10782#define CAN_F17R2_FB3_Msk (0x1UL << CAN_F17R2_FB3_Pos)
10783#define CAN_F17R2_FB3 CAN_F17R2_FB3_Msk
10784#define CAN_F17R2_FB4_Pos (4U)
10785#define CAN_F17R2_FB4_Msk (0x1UL << CAN_F17R2_FB4_Pos)
10786#define CAN_F17R2_FB4 CAN_F17R2_FB4_Msk
10787#define CAN_F17R2_FB5_Pos (5U)
10788#define CAN_F17R2_FB5_Msk (0x1UL << CAN_F17R2_FB5_Pos)
10789#define CAN_F17R2_FB5 CAN_F17R2_FB5_Msk
10790#define CAN_F17R2_FB6_Pos (6U)
10791#define CAN_F17R2_FB6_Msk (0x1UL << CAN_F17R2_FB6_Pos)
10792#define CAN_F17R2_FB6 CAN_F17R2_FB6_Msk
10793#define CAN_F17R2_FB7_Pos (7U)
10794#define CAN_F17R2_FB7_Msk (0x1UL << CAN_F17R2_FB7_Pos)
10795#define CAN_F17R2_FB7 CAN_F17R2_FB7_Msk
10796#define CAN_F17R2_FB8_Pos (8U)
10797#define CAN_F17R2_FB8_Msk (0x1UL << CAN_F17R2_FB8_Pos)
10798#define CAN_F17R2_FB8 CAN_F17R2_FB8_Msk
10799#define CAN_F17R2_FB9_Pos (9U)
10800#define CAN_F17R2_FB9_Msk (0x1UL << CAN_F17R2_FB9_Pos)
10801#define CAN_F17R2_FB9 CAN_F17R2_FB9_Msk
10802#define CAN_F17R2_FB10_Pos (10U)
10803#define CAN_F17R2_FB10_Msk (0x1UL << CAN_F17R2_FB10_Pos)
10804#define CAN_F17R2_FB10 CAN_F17R2_FB10_Msk
10805#define CAN_F17R2_FB11_Pos (11U)
10806#define CAN_F17R2_FB11_Msk (0x1UL << CAN_F17R2_FB11_Pos)
10807#define CAN_F17R2_FB11 CAN_F17R2_FB11_Msk
10808#define CAN_F17R2_FB12_Pos (12U)
10809#define CAN_F17R2_FB12_Msk (0x1UL << CAN_F17R2_FB12_Pos)
10810#define CAN_F17R2_FB12 CAN_F17R2_FB12_Msk
10811#define CAN_F17R2_FB13_Pos (13U)
10812#define CAN_F17R2_FB13_Msk (0x1UL << CAN_F17R2_FB13_Pos)
10813#define CAN_F17R2_FB13 CAN_F17R2_FB13_Msk
10814#define CAN_F17R2_FB14_Pos (14U)
10815#define CAN_F17R2_FB14_Msk (0x1UL << CAN_F17R2_FB14_Pos)
10816#define CAN_F17R2_FB14 CAN_F17R2_FB14_Msk
10817#define CAN_F17R2_FB15_Pos (15U)
10818#define CAN_F17R2_FB15_Msk (0x1UL << CAN_F17R2_FB15_Pos)
10819#define CAN_F17R2_FB15 CAN_F17R2_FB15_Msk
10820#define CAN_F17R2_FB16_Pos (16U)
10821#define CAN_F17R2_FB16_Msk (0x1UL << CAN_F17R2_FB16_Pos)
10822#define CAN_F17R2_FB16 CAN_F17R2_FB16_Msk
10823#define CAN_F17R2_FB17_Pos (17U)
10824#define CAN_F17R2_FB17_Msk (0x1UL << CAN_F17R2_FB17_Pos)
10825#define CAN_F17R2_FB17 CAN_F17R2_FB17_Msk
10826#define CAN_F17R2_FB18_Pos (18U)
10827#define CAN_F17R2_FB18_Msk (0x1UL << CAN_F17R2_FB18_Pos)
10828#define CAN_F17R2_FB18 CAN_F17R2_FB18_Msk
10829#define CAN_F17R2_FB19_Pos (19U)
10830#define CAN_F17R2_FB19_Msk (0x1UL << CAN_F17R2_FB19_Pos)
10831#define CAN_F17R2_FB19 CAN_F17R2_FB19_Msk
10832#define CAN_F17R2_FB20_Pos (20U)
10833#define CAN_F17R2_FB20_Msk (0x1UL << CAN_F17R2_FB20_Pos)
10834#define CAN_F17R2_FB20 CAN_F17R2_FB20_Msk
10835#define CAN_F17R2_FB21_Pos (21U)
10836#define CAN_F17R2_FB21_Msk (0x1UL << CAN_F17R2_FB21_Pos)
10837#define CAN_F17R2_FB21 CAN_F17R2_FB21_Msk
10838#define CAN_F17R2_FB22_Pos (22U)
10839#define CAN_F17R2_FB22_Msk (0x1UL << CAN_F17R2_FB22_Pos)
10840#define CAN_F17R2_FB22 CAN_F17R2_FB22_Msk
10841#define CAN_F17R2_FB23_Pos (23U)
10842#define CAN_F17R2_FB23_Msk (0x1UL << CAN_F17R2_FB23_Pos)
10843#define CAN_F17R2_FB23 CAN_F17R2_FB23_Msk
10844#define CAN_F17R2_FB24_Pos (24U)
10845#define CAN_F17R2_FB24_Msk (0x1UL << CAN_F17R2_FB24_Pos)
10846#define CAN_F17R2_FB24 CAN_F17R2_FB24_Msk
10847#define CAN_F17R2_FB25_Pos (25U)
10848#define CAN_F17R2_FB25_Msk (0x1UL << CAN_F17R2_FB25_Pos)
10849#define CAN_F17R2_FB25 CAN_F17R2_FB25_Msk
10850#define CAN_F17R2_FB26_Pos (26U)
10851#define CAN_F17R2_FB26_Msk (0x1UL << CAN_F17R2_FB26_Pos)
10852#define CAN_F17R2_FB26 CAN_F17R2_FB26_Msk
10853#define CAN_F17R2_FB27_Pos (27U)
10854#define CAN_F17R2_FB27_Msk (0x1UL << CAN_F17R2_FB27_Pos)
10855#define CAN_F17R2_FB27 CAN_F17R2_FB27_Msk
10856#define CAN_F17R2_FB28_Pos (28U)
10857#define CAN_F17R2_FB28_Msk (0x1UL << CAN_F17R2_FB28_Pos)
10858#define CAN_F17R2_FB28 CAN_F17R2_FB28_Msk
10859#define CAN_F17R2_FB29_Pos (29U)
10860#define CAN_F17R2_FB29_Msk (0x1UL << CAN_F17R2_FB29_Pos)
10861#define CAN_F17R2_FB29 CAN_F17R2_FB29_Msk
10862#define CAN_F17R2_FB30_Pos (30U)
10863#define CAN_F17R2_FB30_Msk (0x1UL << CAN_F17R2_FB30_Pos)
10864#define CAN_F17R2_FB30 CAN_F17R2_FB30_Msk
10865#define CAN_F17R2_FB31_Pos (31U)
10866#define CAN_F17R2_FB31_Msk (0x1UL << CAN_F17R2_FB31_Pos)
10867#define CAN_F17R2_FB31 CAN_F17R2_FB31_Msk
10869/******************* Bit definition for CAN_F18R2 register ******************/
10870#define CAN_F18R2_FB0_Pos (0U)
10871#define CAN_F18R2_FB0_Msk (0x1UL << CAN_F18R2_FB0_Pos)
10872#define CAN_F18R2_FB0 CAN_F18R2_FB0_Msk
10873#define CAN_F18R2_FB1_Pos (1U)
10874#define CAN_F18R2_FB1_Msk (0x1UL << CAN_F18R2_FB1_Pos)
10875#define CAN_F18R2_FB1 CAN_F18R2_FB1_Msk
10876#define CAN_F18R2_FB2_Pos (2U)
10877#define CAN_F18R2_FB2_Msk (0x1UL << CAN_F18R2_FB2_Pos)
10878#define CAN_F18R2_FB2 CAN_F18R2_FB2_Msk
10879#define CAN_F18R2_FB3_Pos (3U)
10880#define CAN_F18R2_FB3_Msk (0x1UL << CAN_F18R2_FB3_Pos)
10881#define CAN_F18R2_FB3 CAN_F18R2_FB3_Msk
10882#define CAN_F18R2_FB4_Pos (4U)
10883#define CAN_F18R2_FB4_Msk (0x1UL << CAN_F18R2_FB4_Pos)
10884#define CAN_F18R2_FB4 CAN_F18R2_FB4_Msk
10885#define CAN_F18R2_FB5_Pos (5U)
10886#define CAN_F18R2_FB5_Msk (0x1UL << CAN_F18R2_FB5_Pos)
10887#define CAN_F18R2_FB5 CAN_F18R2_FB5_Msk
10888#define CAN_F18R2_FB6_Pos (6U)
10889#define CAN_F18R2_FB6_Msk (0x1UL << CAN_F18R2_FB6_Pos)
10890#define CAN_F18R2_FB6 CAN_F18R2_FB6_Msk
10891#define CAN_F18R2_FB7_Pos (7U)
10892#define CAN_F18R2_FB7_Msk (0x1UL << CAN_F18R2_FB7_Pos)
10893#define CAN_F18R2_FB7 CAN_F18R2_FB7_Msk
10894#define CAN_F18R2_FB8_Pos (8U)
10895#define CAN_F18R2_FB8_Msk (0x1UL << CAN_F18R2_FB8_Pos)
10896#define CAN_F18R2_FB8 CAN_F18R2_FB8_Msk
10897#define CAN_F18R2_FB9_Pos (9U)
10898#define CAN_F18R2_FB9_Msk (0x1UL << CAN_F18R2_FB9_Pos)
10899#define CAN_F18R2_FB9 CAN_F18R2_FB9_Msk
10900#define CAN_F18R2_FB10_Pos (10U)
10901#define CAN_F18R2_FB10_Msk (0x1UL << CAN_F18R2_FB10_Pos)
10902#define CAN_F18R2_FB10 CAN_F18R2_FB10_Msk
10903#define CAN_F18R2_FB11_Pos (11U)
10904#define CAN_F18R2_FB11_Msk (0x1UL << CAN_F18R2_FB11_Pos)
10905#define CAN_F18R2_FB11 CAN_F18R2_FB11_Msk
10906#define CAN_F18R2_FB12_Pos (12U)
10907#define CAN_F18R2_FB12_Msk (0x1UL << CAN_F18R2_FB12_Pos)
10908#define CAN_F18R2_FB12 CAN_F18R2_FB12_Msk
10909#define CAN_F18R2_FB13_Pos (13U)
10910#define CAN_F18R2_FB13_Msk (0x1UL << CAN_F18R2_FB13_Pos)
10911#define CAN_F18R2_FB13 CAN_F18R2_FB13_Msk
10912#define CAN_F18R2_FB14_Pos (14U)
10913#define CAN_F18R2_FB14_Msk (0x1UL << CAN_F18R2_FB14_Pos)
10914#define CAN_F18R2_FB14 CAN_F18R2_FB14_Msk
10915#define CAN_F18R2_FB15_Pos (15U)
10916#define CAN_F18R2_FB15_Msk (0x1UL << CAN_F18R2_FB15_Pos)
10917#define CAN_F18R2_FB15 CAN_F18R2_FB15_Msk
10918#define CAN_F18R2_FB16_Pos (16U)
10919#define CAN_F18R2_FB16_Msk (0x1UL << CAN_F18R2_FB16_Pos)
10920#define CAN_F18R2_FB16 CAN_F18R2_FB16_Msk
10921#define CAN_F18R2_FB17_Pos (17U)
10922#define CAN_F18R2_FB17_Msk (0x1UL << CAN_F18R2_FB17_Pos)
10923#define CAN_F18R2_FB17 CAN_F18R2_FB17_Msk
10924#define CAN_F18R2_FB18_Pos (18U)
10925#define CAN_F18R2_FB18_Msk (0x1UL << CAN_F18R2_FB18_Pos)
10926#define CAN_F18R2_FB18 CAN_F18R2_FB18_Msk
10927#define CAN_F18R2_FB19_Pos (19U)
10928#define CAN_F18R2_FB19_Msk (0x1UL << CAN_F18R2_FB19_Pos)
10929#define CAN_F18R2_FB19 CAN_F18R2_FB19_Msk
10930#define CAN_F18R2_FB20_Pos (20U)
10931#define CAN_F18R2_FB20_Msk (0x1UL << CAN_F18R2_FB20_Pos)
10932#define CAN_F18R2_FB20 CAN_F18R2_FB20_Msk
10933#define CAN_F18R2_FB21_Pos (21U)
10934#define CAN_F18R2_FB21_Msk (0x1UL << CAN_F18R2_FB21_Pos)
10935#define CAN_F18R2_FB21 CAN_F18R2_FB21_Msk
10936#define CAN_F18R2_FB22_Pos (22U)
10937#define CAN_F18R2_FB22_Msk (0x1UL << CAN_F18R2_FB22_Pos)
10938#define CAN_F18R2_FB22 CAN_F18R2_FB22_Msk
10939#define CAN_F18R2_FB23_Pos (23U)
10940#define CAN_F18R2_FB23_Msk (0x1UL << CAN_F18R2_FB23_Pos)
10941#define CAN_F18R2_FB23 CAN_F18R2_FB23_Msk
10942#define CAN_F18R2_FB24_Pos (24U)
10943#define CAN_F18R2_FB24_Msk (0x1UL << CAN_F18R2_FB24_Pos)
10944#define CAN_F18R2_FB24 CAN_F18R2_FB24_Msk
10945#define CAN_F18R2_FB25_Pos (25U)
10946#define CAN_F18R2_FB25_Msk (0x1UL << CAN_F18R2_FB25_Pos)
10947#define CAN_F18R2_FB25 CAN_F18R2_FB25_Msk
10948#define CAN_F18R2_FB26_Pos (26U)
10949#define CAN_F18R2_FB26_Msk (0x1UL << CAN_F18R2_FB26_Pos)
10950#define CAN_F18R2_FB26 CAN_F18R2_FB26_Msk
10951#define CAN_F18R2_FB27_Pos (27U)
10952#define CAN_F18R2_FB27_Msk (0x1UL << CAN_F18R2_FB27_Pos)
10953#define CAN_F18R2_FB27 CAN_F18R2_FB27_Msk
10954#define CAN_F18R2_FB28_Pos (28U)
10955#define CAN_F18R2_FB28_Msk (0x1UL << CAN_F18R2_FB28_Pos)
10956#define CAN_F18R2_FB28 CAN_F18R2_FB28_Msk
10957#define CAN_F18R2_FB29_Pos (29U)
10958#define CAN_F18R2_FB29_Msk (0x1UL << CAN_F18R2_FB29_Pos)
10959#define CAN_F18R2_FB29 CAN_F18R2_FB29_Msk
10960#define CAN_F18R2_FB30_Pos (30U)
10961#define CAN_F18R2_FB30_Msk (0x1UL << CAN_F18R2_FB30_Pos)
10962#define CAN_F18R2_FB30 CAN_F18R2_FB30_Msk
10963#define CAN_F18R2_FB31_Pos (31U)
10964#define CAN_F18R2_FB31_Msk (0x1UL << CAN_F18R2_FB31_Pos)
10965#define CAN_F18R2_FB31 CAN_F18R2_FB31_Msk
10967/******************* Bit definition for CAN_F19R2 register ******************/
10968#define CAN_F19R2_FB0_Pos (0U)
10969#define CAN_F19R2_FB0_Msk (0x1UL << CAN_F19R2_FB0_Pos)
10970#define CAN_F19R2_FB0 CAN_F19R2_FB0_Msk
10971#define CAN_F19R2_FB1_Pos (1U)
10972#define CAN_F19R2_FB1_Msk (0x1UL << CAN_F19R2_FB1_Pos)
10973#define CAN_F19R2_FB1 CAN_F19R2_FB1_Msk
10974#define CAN_F19R2_FB2_Pos (2U)
10975#define CAN_F19R2_FB2_Msk (0x1UL << CAN_F19R2_FB2_Pos)
10976#define CAN_F19R2_FB2 CAN_F19R2_FB2_Msk
10977#define CAN_F19R2_FB3_Pos (3U)
10978#define CAN_F19R2_FB3_Msk (0x1UL << CAN_F19R2_FB3_Pos)
10979#define CAN_F19R2_FB3 CAN_F19R2_FB3_Msk
10980#define CAN_F19R2_FB4_Pos (4U)
10981#define CAN_F19R2_FB4_Msk (0x1UL << CAN_F19R2_FB4_Pos)
10982#define CAN_F19R2_FB4 CAN_F19R2_FB4_Msk
10983#define CAN_F19R2_FB5_Pos (5U)
10984#define CAN_F19R2_FB5_Msk (0x1UL << CAN_F19R2_FB5_Pos)
10985#define CAN_F19R2_FB5 CAN_F19R2_FB5_Msk
10986#define CAN_F19R2_FB6_Pos (6U)
10987#define CAN_F19R2_FB6_Msk (0x1UL << CAN_F19R2_FB6_Pos)
10988#define CAN_F19R2_FB6 CAN_F19R2_FB6_Msk
10989#define CAN_F19R2_FB7_Pos (7U)
10990#define CAN_F19R2_FB7_Msk (0x1UL << CAN_F19R2_FB7_Pos)
10991#define CAN_F19R2_FB7 CAN_F19R2_FB7_Msk
10992#define CAN_F19R2_FB8_Pos (8U)
10993#define CAN_F19R2_FB8_Msk (0x1UL << CAN_F19R2_FB8_Pos)
10994#define CAN_F19R2_FB8 CAN_F19R2_FB8_Msk
10995#define CAN_F19R2_FB9_Pos (9U)
10996#define CAN_F19R2_FB9_Msk (0x1UL << CAN_F19R2_FB9_Pos)
10997#define CAN_F19R2_FB9 CAN_F19R2_FB9_Msk
10998#define CAN_F19R2_FB10_Pos (10U)
10999#define CAN_F19R2_FB10_Msk (0x1UL << CAN_F19R2_FB10_Pos)
11000#define CAN_F19R2_FB10 CAN_F19R2_FB10_Msk
11001#define CAN_F19R2_FB11_Pos (11U)
11002#define CAN_F19R2_FB11_Msk (0x1UL << CAN_F19R2_FB11_Pos)
11003#define CAN_F19R2_FB11 CAN_F19R2_FB11_Msk
11004#define CAN_F19R2_FB12_Pos (12U)
11005#define CAN_F19R2_FB12_Msk (0x1UL << CAN_F19R2_FB12_Pos)
11006#define CAN_F19R2_FB12 CAN_F19R2_FB12_Msk
11007#define CAN_F19R2_FB13_Pos (13U)
11008#define CAN_F19R2_FB13_Msk (0x1UL << CAN_F19R2_FB13_Pos)
11009#define CAN_F19R2_FB13 CAN_F19R2_FB13_Msk
11010#define CAN_F19R2_FB14_Pos (14U)
11011#define CAN_F19R2_FB14_Msk (0x1UL << CAN_F19R2_FB14_Pos)
11012#define CAN_F19R2_FB14 CAN_F19R2_FB14_Msk
11013#define CAN_F19R2_FB15_Pos (15U)
11014#define CAN_F19R2_FB15_Msk (0x1UL << CAN_F19R2_FB15_Pos)
11015#define CAN_F19R2_FB15 CAN_F19R2_FB15_Msk
11016#define CAN_F19R2_FB16_Pos (16U)
11017#define CAN_F19R2_FB16_Msk (0x1UL << CAN_F19R2_FB16_Pos)
11018#define CAN_F19R2_FB16 CAN_F19R2_FB16_Msk
11019#define CAN_F19R2_FB17_Pos (17U)
11020#define CAN_F19R2_FB17_Msk (0x1UL << CAN_F19R2_FB17_Pos)
11021#define CAN_F19R2_FB17 CAN_F19R2_FB17_Msk
11022#define CAN_F19R2_FB18_Pos (18U)
11023#define CAN_F19R2_FB18_Msk (0x1UL << CAN_F19R2_FB18_Pos)
11024#define CAN_F19R2_FB18 CAN_F19R2_FB18_Msk
11025#define CAN_F19R2_FB19_Pos (19U)
11026#define CAN_F19R2_FB19_Msk (0x1UL << CAN_F19R2_FB19_Pos)
11027#define CAN_F19R2_FB19 CAN_F19R2_FB19_Msk
11028#define CAN_F19R2_FB20_Pos (20U)
11029#define CAN_F19R2_FB20_Msk (0x1UL << CAN_F19R2_FB20_Pos)
11030#define CAN_F19R2_FB20 CAN_F19R2_FB20_Msk
11031#define CAN_F19R2_FB21_Pos (21U)
11032#define CAN_F19R2_FB21_Msk (0x1UL << CAN_F19R2_FB21_Pos)
11033#define CAN_F19R2_FB21 CAN_F19R2_FB21_Msk
11034#define CAN_F19R2_FB22_Pos (22U)
11035#define CAN_F19R2_FB22_Msk (0x1UL << CAN_F19R2_FB22_Pos)
11036#define CAN_F19R2_FB22 CAN_F19R2_FB22_Msk
11037#define CAN_F19R2_FB23_Pos (23U)
11038#define CAN_F19R2_FB23_Msk (0x1UL << CAN_F19R2_FB23_Pos)
11039#define CAN_F19R2_FB23 CAN_F19R2_FB23_Msk
11040#define CAN_F19R2_FB24_Pos (24U)
11041#define CAN_F19R2_FB24_Msk (0x1UL << CAN_F19R2_FB24_Pos)
11042#define CAN_F19R2_FB24 CAN_F19R2_FB24_Msk
11043#define CAN_F19R2_FB25_Pos (25U)
11044#define CAN_F19R2_FB25_Msk (0x1UL << CAN_F19R2_FB25_Pos)
11045#define CAN_F19R2_FB25 CAN_F19R2_FB25_Msk
11046#define CAN_F19R2_FB26_Pos (26U)
11047#define CAN_F19R2_FB26_Msk (0x1UL << CAN_F19R2_FB26_Pos)
11048#define CAN_F19R2_FB26 CAN_F19R2_FB26_Msk
11049#define CAN_F19R2_FB27_Pos (27U)
11050#define CAN_F19R2_FB27_Msk (0x1UL << CAN_F19R2_FB27_Pos)
11051#define CAN_F19R2_FB27 CAN_F19R2_FB27_Msk
11052#define CAN_F19R2_FB28_Pos (28U)
11053#define CAN_F19R2_FB28_Msk (0x1UL << CAN_F19R2_FB28_Pos)
11054#define CAN_F19R2_FB28 CAN_F19R2_FB28_Msk
11055#define CAN_F19R2_FB29_Pos (29U)
11056#define CAN_F19R2_FB29_Msk (0x1UL << CAN_F19R2_FB29_Pos)
11057#define CAN_F19R2_FB29 CAN_F19R2_FB29_Msk
11058#define CAN_F19R2_FB30_Pos (30U)
11059#define CAN_F19R2_FB30_Msk (0x1UL << CAN_F19R2_FB30_Pos)
11060#define CAN_F19R2_FB30 CAN_F19R2_FB30_Msk
11061#define CAN_F19R2_FB31_Pos (31U)
11062#define CAN_F19R2_FB31_Msk (0x1UL << CAN_F19R2_FB31_Pos)
11063#define CAN_F19R2_FB31 CAN_F19R2_FB31_Msk
11065/******************* Bit definition for CAN_F20R2 register ******************/
11066#define CAN_F20R2_FB0_Pos (0U)
11067#define CAN_F20R2_FB0_Msk (0x1UL << CAN_F20R2_FB0_Pos)
11068#define CAN_F20R2_FB0 CAN_F20R2_FB0_Msk
11069#define CAN_F20R2_FB1_Pos (1U)
11070#define CAN_F20R2_FB1_Msk (0x1UL << CAN_F20R2_FB1_Pos)
11071#define CAN_F20R2_FB1 CAN_F20R2_FB1_Msk
11072#define CAN_F20R2_FB2_Pos (2U)
11073#define CAN_F20R2_FB2_Msk (0x1UL << CAN_F20R2_FB2_Pos)
11074#define CAN_F20R2_FB2 CAN_F20R2_FB2_Msk
11075#define CAN_F20R2_FB3_Pos (3U)
11076#define CAN_F20R2_FB3_Msk (0x1UL << CAN_F20R2_FB3_Pos)
11077#define CAN_F20R2_FB3 CAN_F20R2_FB3_Msk
11078#define CAN_F20R2_FB4_Pos (4U)
11079#define CAN_F20R2_FB4_Msk (0x1UL << CAN_F20R2_FB4_Pos)
11080#define CAN_F20R2_FB4 CAN_F20R2_FB4_Msk
11081#define CAN_F20R2_FB5_Pos (5U)
11082#define CAN_F20R2_FB5_Msk (0x1UL << CAN_F20R2_FB5_Pos)
11083#define CAN_F20R2_FB5 CAN_F20R2_FB5_Msk
11084#define CAN_F20R2_FB6_Pos (6U)
11085#define CAN_F20R2_FB6_Msk (0x1UL << CAN_F20R2_FB6_Pos)
11086#define CAN_F20R2_FB6 CAN_F20R2_FB6_Msk
11087#define CAN_F20R2_FB7_Pos (7U)
11088#define CAN_F20R2_FB7_Msk (0x1UL << CAN_F20R2_FB7_Pos)
11089#define CAN_F20R2_FB7 CAN_F20R2_FB7_Msk
11090#define CAN_F20R2_FB8_Pos (8U)
11091#define CAN_F20R2_FB8_Msk (0x1UL << CAN_F20R2_FB8_Pos)
11092#define CAN_F20R2_FB8 CAN_F20R2_FB8_Msk
11093#define CAN_F20R2_FB9_Pos (9U)
11094#define CAN_F20R2_FB9_Msk (0x1UL << CAN_F20R2_FB9_Pos)
11095#define CAN_F20R2_FB9 CAN_F20R2_FB9_Msk
11096#define CAN_F20R2_FB10_Pos (10U)
11097#define CAN_F20R2_FB10_Msk (0x1UL << CAN_F20R2_FB10_Pos)
11098#define CAN_F20R2_FB10 CAN_F20R2_FB10_Msk
11099#define CAN_F20R2_FB11_Pos (11U)
11100#define CAN_F20R2_FB11_Msk (0x1UL << CAN_F20R2_FB11_Pos)
11101#define CAN_F20R2_FB11 CAN_F20R2_FB11_Msk
11102#define CAN_F20R2_FB12_Pos (12U)
11103#define CAN_F20R2_FB12_Msk (0x1UL << CAN_F20R2_FB12_Pos)
11104#define CAN_F20R2_FB12 CAN_F20R2_FB12_Msk
11105#define CAN_F20R2_FB13_Pos (13U)
11106#define CAN_F20R2_FB13_Msk (0x1UL << CAN_F20R2_FB13_Pos)
11107#define CAN_F20R2_FB13 CAN_F20R2_FB13_Msk
11108#define CAN_F20R2_FB14_Pos (14U)
11109#define CAN_F20R2_FB14_Msk (0x1UL << CAN_F20R2_FB14_Pos)
11110#define CAN_F20R2_FB14 CAN_F20R2_FB14_Msk
11111#define CAN_F20R2_FB15_Pos (15U)
11112#define CAN_F20R2_FB15_Msk (0x1UL << CAN_F20R2_FB15_Pos)
11113#define CAN_F20R2_FB15 CAN_F20R2_FB15_Msk
11114#define CAN_F20R2_FB16_Pos (16U)
11115#define CAN_F20R2_FB16_Msk (0x1UL << CAN_F20R2_FB16_Pos)
11116#define CAN_F20R2_FB16 CAN_F20R2_FB16_Msk
11117#define CAN_F20R2_FB17_Pos (17U)
11118#define CAN_F20R2_FB17_Msk (0x1UL << CAN_F20R2_FB17_Pos)
11119#define CAN_F20R2_FB17 CAN_F20R2_FB17_Msk
11120#define CAN_F20R2_FB18_Pos (18U)
11121#define CAN_F20R2_FB18_Msk (0x1UL << CAN_F20R2_FB18_Pos)
11122#define CAN_F20R2_FB18 CAN_F20R2_FB18_Msk
11123#define CAN_F20R2_FB19_Pos (19U)
11124#define CAN_F20R2_FB19_Msk (0x1UL << CAN_F20R2_FB19_Pos)
11125#define CAN_F20R2_FB19 CAN_F20R2_FB19_Msk
11126#define CAN_F20R2_FB20_Pos (20U)
11127#define CAN_F20R2_FB20_Msk (0x1UL << CAN_F20R2_FB20_Pos)
11128#define CAN_F20R2_FB20 CAN_F20R2_FB20_Msk
11129#define CAN_F20R2_FB21_Pos (21U)
11130#define CAN_F20R2_FB21_Msk (0x1UL << CAN_F20R2_FB21_Pos)
11131#define CAN_F20R2_FB21 CAN_F20R2_FB21_Msk
11132#define CAN_F20R2_FB22_Pos (22U)
11133#define CAN_F20R2_FB22_Msk (0x1UL << CAN_F20R2_FB22_Pos)
11134#define CAN_F20R2_FB22 CAN_F20R2_FB22_Msk
11135#define CAN_F20R2_FB23_Pos (23U)
11136#define CAN_F20R2_FB23_Msk (0x1UL << CAN_F20R2_FB23_Pos)
11137#define CAN_F20R2_FB23 CAN_F20R2_FB23_Msk
11138#define CAN_F20R2_FB24_Pos (24U)
11139#define CAN_F20R2_FB24_Msk (0x1UL << CAN_F20R2_FB24_Pos)
11140#define CAN_F20R2_FB24 CAN_F20R2_FB24_Msk
11141#define CAN_F20R2_FB25_Pos (25U)
11142#define CAN_F20R2_FB25_Msk (0x1UL << CAN_F20R2_FB25_Pos)
11143#define CAN_F20R2_FB25 CAN_F20R2_FB25_Msk
11144#define CAN_F20R2_FB26_Pos (26U)
11145#define CAN_F20R2_FB26_Msk (0x1UL << CAN_F20R2_FB26_Pos)
11146#define CAN_F20R2_FB26 CAN_F20R2_FB26_Msk
11147#define CAN_F20R2_FB27_Pos (27U)
11148#define CAN_F20R2_FB27_Msk (0x1UL << CAN_F20R2_FB27_Pos)
11149#define CAN_F20R2_FB27 CAN_F20R2_FB27_Msk
11150#define CAN_F20R2_FB28_Pos (28U)
11151#define CAN_F20R2_FB28_Msk (0x1UL << CAN_F20R2_FB28_Pos)
11152#define CAN_F20R2_FB28 CAN_F20R2_FB28_Msk
11153#define CAN_F20R2_FB29_Pos (29U)
11154#define CAN_F20R2_FB29_Msk (0x1UL << CAN_F20R2_FB29_Pos)
11155#define CAN_F20R2_FB29 CAN_F20R2_FB29_Msk
11156#define CAN_F20R2_FB30_Pos (30U)
11157#define CAN_F20R2_FB30_Msk (0x1UL << CAN_F20R2_FB30_Pos)
11158#define CAN_F20R2_FB30 CAN_F20R2_FB30_Msk
11159#define CAN_F20R2_FB31_Pos (31U)
11160#define CAN_F20R2_FB31_Msk (0x1UL << CAN_F20R2_FB31_Pos)
11161#define CAN_F20R2_FB31 CAN_F20R2_FB31_Msk
11163/******************* Bit definition for CAN_F21R2 register ******************/
11164#define CAN_F21R2_FB0_Pos (0U)
11165#define CAN_F21R2_FB0_Msk (0x1UL << CAN_F21R2_FB0_Pos)
11166#define CAN_F21R2_FB0 CAN_F21R2_FB0_Msk
11167#define CAN_F21R2_FB1_Pos (1U)
11168#define CAN_F21R2_FB1_Msk (0x1UL << CAN_F21R2_FB1_Pos)
11169#define CAN_F21R2_FB1 CAN_F21R2_FB1_Msk
11170#define CAN_F21R2_FB2_Pos (2U)
11171#define CAN_F21R2_FB2_Msk (0x1UL << CAN_F21R2_FB2_Pos)
11172#define CAN_F21R2_FB2 CAN_F21R2_FB2_Msk
11173#define CAN_F21R2_FB3_Pos (3U)
11174#define CAN_F21R2_FB3_Msk (0x1UL << CAN_F21R2_FB3_Pos)
11175#define CAN_F21R2_FB3 CAN_F21R2_FB3_Msk
11176#define CAN_F21R2_FB4_Pos (4U)
11177#define CAN_F21R2_FB4_Msk (0x1UL << CAN_F21R2_FB4_Pos)
11178#define CAN_F21R2_FB4 CAN_F21R2_FB4_Msk
11179#define CAN_F21R2_FB5_Pos (5U)
11180#define CAN_F21R2_FB5_Msk (0x1UL << CAN_F21R2_FB5_Pos)
11181#define CAN_F21R2_FB5 CAN_F21R2_FB5_Msk
11182#define CAN_F21R2_FB6_Pos (6U)
11183#define CAN_F21R2_FB6_Msk (0x1UL << CAN_F21R2_FB6_Pos)
11184#define CAN_F21R2_FB6 CAN_F21R2_FB6_Msk
11185#define CAN_F21R2_FB7_Pos (7U)
11186#define CAN_F21R2_FB7_Msk (0x1UL << CAN_F21R2_FB7_Pos)
11187#define CAN_F21R2_FB7 CAN_F21R2_FB7_Msk
11188#define CAN_F21R2_FB8_Pos (8U)
11189#define CAN_F21R2_FB8_Msk (0x1UL << CAN_F21R2_FB8_Pos)
11190#define CAN_F21R2_FB8 CAN_F21R2_FB8_Msk
11191#define CAN_F21R2_FB9_Pos (9U)
11192#define CAN_F21R2_FB9_Msk (0x1UL << CAN_F21R2_FB9_Pos)
11193#define CAN_F21R2_FB9 CAN_F21R2_FB9_Msk
11194#define CAN_F21R2_FB10_Pos (10U)
11195#define CAN_F21R2_FB10_Msk (0x1UL << CAN_F21R2_FB10_Pos)
11196#define CAN_F21R2_FB10 CAN_F21R2_FB10_Msk
11197#define CAN_F21R2_FB11_Pos (11U)
11198#define CAN_F21R2_FB11_Msk (0x1UL << CAN_F21R2_FB11_Pos)
11199#define CAN_F21R2_FB11 CAN_F21R2_FB11_Msk
11200#define CAN_F21R2_FB12_Pos (12U)
11201#define CAN_F21R2_FB12_Msk (0x1UL << CAN_F21R2_FB12_Pos)
11202#define CAN_F21R2_FB12 CAN_F21R2_FB12_Msk
11203#define CAN_F21R2_FB13_Pos (13U)
11204#define CAN_F21R2_FB13_Msk (0x1UL << CAN_F21R2_FB13_Pos)
11205#define CAN_F21R2_FB13 CAN_F21R2_FB13_Msk
11206#define CAN_F21R2_FB14_Pos (14U)
11207#define CAN_F21R2_FB14_Msk (0x1UL << CAN_F21R2_FB14_Pos)
11208#define CAN_F21R2_FB14 CAN_F21R2_FB14_Msk
11209#define CAN_F21R2_FB15_Pos (15U)
11210#define CAN_F21R2_FB15_Msk (0x1UL << CAN_F21R2_FB15_Pos)
11211#define CAN_F21R2_FB15 CAN_F21R2_FB15_Msk
11212#define CAN_F21R2_FB16_Pos (16U)
11213#define CAN_F21R2_FB16_Msk (0x1UL << CAN_F21R2_FB16_Pos)
11214#define CAN_F21R2_FB16 CAN_F21R2_FB16_Msk
11215#define CAN_F21R2_FB17_Pos (17U)
11216#define CAN_F21R2_FB17_Msk (0x1UL << CAN_F21R2_FB17_Pos)
11217#define CAN_F21R2_FB17 CAN_F21R2_FB17_Msk
11218#define CAN_F21R2_FB18_Pos (18U)
11219#define CAN_F21R2_FB18_Msk (0x1UL << CAN_F21R2_FB18_Pos)
11220#define CAN_F21R2_FB18 CAN_F21R2_FB18_Msk
11221#define CAN_F21R2_FB19_Pos (19U)
11222#define CAN_F21R2_FB19_Msk (0x1UL << CAN_F21R2_FB19_Pos)
11223#define CAN_F21R2_FB19 CAN_F21R2_FB19_Msk
11224#define CAN_F21R2_FB20_Pos (20U)
11225#define CAN_F21R2_FB20_Msk (0x1UL << CAN_F21R2_FB20_Pos)
11226#define CAN_F21R2_FB20 CAN_F21R2_FB20_Msk
11227#define CAN_F21R2_FB21_Pos (21U)
11228#define CAN_F21R2_FB21_Msk (0x1UL << CAN_F21R2_FB21_Pos)
11229#define CAN_F21R2_FB21 CAN_F21R2_FB21_Msk
11230#define CAN_F21R2_FB22_Pos (22U)
11231#define CAN_F21R2_FB22_Msk (0x1UL << CAN_F21R2_FB22_Pos)
11232#define CAN_F21R2_FB22 CAN_F21R2_FB22_Msk
11233#define CAN_F21R2_FB23_Pos (23U)
11234#define CAN_F21R2_FB23_Msk (0x1UL << CAN_F21R2_FB23_Pos)
11235#define CAN_F21R2_FB23 CAN_F21R2_FB23_Msk
11236#define CAN_F21R2_FB24_Pos (24U)
11237#define CAN_F21R2_FB24_Msk (0x1UL << CAN_F21R2_FB24_Pos)
11238#define CAN_F21R2_FB24 CAN_F21R2_FB24_Msk
11239#define CAN_F21R2_FB25_Pos (25U)
11240#define CAN_F21R2_FB25_Msk (0x1UL << CAN_F21R2_FB25_Pos)
11241#define CAN_F21R2_FB25 CAN_F21R2_FB25_Msk
11242#define CAN_F21R2_FB26_Pos (26U)
11243#define CAN_F21R2_FB26_Msk (0x1UL << CAN_F21R2_FB26_Pos)
11244#define CAN_F21R2_FB26 CAN_F21R2_FB26_Msk
11245#define CAN_F21R2_FB27_Pos (27U)
11246#define CAN_F21R2_FB27_Msk (0x1UL << CAN_F21R2_FB27_Pos)
11247#define CAN_F21R2_FB27 CAN_F21R2_FB27_Msk
11248#define CAN_F21R2_FB28_Pos (28U)
11249#define CAN_F21R2_FB28_Msk (0x1UL << CAN_F21R2_FB28_Pos)
11250#define CAN_F21R2_FB28 CAN_F21R2_FB28_Msk
11251#define CAN_F21R2_FB29_Pos (29U)
11252#define CAN_F21R2_FB29_Msk (0x1UL << CAN_F21R2_FB29_Pos)
11253#define CAN_F21R2_FB29 CAN_F21R2_FB29_Msk
11254#define CAN_F21R2_FB30_Pos (30U)
11255#define CAN_F21R2_FB30_Msk (0x1UL << CAN_F21R2_FB30_Pos)
11256#define CAN_F21R2_FB30 CAN_F21R2_FB30_Msk
11257#define CAN_F21R2_FB31_Pos (31U)
11258#define CAN_F21R2_FB31_Msk (0x1UL << CAN_F21R2_FB31_Pos)
11259#define CAN_F21R2_FB31 CAN_F21R2_FB31_Msk
11261/******************* Bit definition for CAN_F22R2 register ******************/
11262#define CAN_F22R2_FB0_Pos (0U)
11263#define CAN_F22R2_FB0_Msk (0x1UL << CAN_F22R2_FB0_Pos)
11264#define CAN_F22R2_FB0 CAN_F22R2_FB0_Msk
11265#define CAN_F22R2_FB1_Pos (1U)
11266#define CAN_F22R2_FB1_Msk (0x1UL << CAN_F22R2_FB1_Pos)
11267#define CAN_F22R2_FB1 CAN_F22R2_FB1_Msk
11268#define CAN_F22R2_FB2_Pos (2U)
11269#define CAN_F22R2_FB2_Msk (0x1UL << CAN_F22R2_FB2_Pos)
11270#define CAN_F22R2_FB2 CAN_F22R2_FB2_Msk
11271#define CAN_F22R2_FB3_Pos (3U)
11272#define CAN_F22R2_FB3_Msk (0x1UL << CAN_F22R2_FB3_Pos)
11273#define CAN_F22R2_FB3 CAN_F22R2_FB3_Msk
11274#define CAN_F22R2_FB4_Pos (4U)
11275#define CAN_F22R2_FB4_Msk (0x1UL << CAN_F22R2_FB4_Pos)
11276#define CAN_F22R2_FB4 CAN_F22R2_FB4_Msk
11277#define CAN_F22R2_FB5_Pos (5U)
11278#define CAN_F22R2_FB5_Msk (0x1UL << CAN_F22R2_FB5_Pos)
11279#define CAN_F22R2_FB5 CAN_F22R2_FB5_Msk
11280#define CAN_F22R2_FB6_Pos (6U)
11281#define CAN_F22R2_FB6_Msk (0x1UL << CAN_F22R2_FB6_Pos)
11282#define CAN_F22R2_FB6 CAN_F22R2_FB6_Msk
11283#define CAN_F22R2_FB7_Pos (7U)
11284#define CAN_F22R2_FB7_Msk (0x1UL << CAN_F22R2_FB7_Pos)
11285#define CAN_F22R2_FB7 CAN_F22R2_FB7_Msk
11286#define CAN_F22R2_FB8_Pos (8U)
11287#define CAN_F22R2_FB8_Msk (0x1UL << CAN_F22R2_FB8_Pos)
11288#define CAN_F22R2_FB8 CAN_F22R2_FB8_Msk
11289#define CAN_F22R2_FB9_Pos (9U)
11290#define CAN_F22R2_FB9_Msk (0x1UL << CAN_F22R2_FB9_Pos)
11291#define CAN_F22R2_FB9 CAN_F22R2_FB9_Msk
11292#define CAN_F22R2_FB10_Pos (10U)
11293#define CAN_F22R2_FB10_Msk (0x1UL << CAN_F22R2_FB10_Pos)
11294#define CAN_F22R2_FB10 CAN_F22R2_FB10_Msk
11295#define CAN_F22R2_FB11_Pos (11U)
11296#define CAN_F22R2_FB11_Msk (0x1UL << CAN_F22R2_FB11_Pos)
11297#define CAN_F22R2_FB11 CAN_F22R2_FB11_Msk
11298#define CAN_F22R2_FB12_Pos (12U)
11299#define CAN_F22R2_FB12_Msk (0x1UL << CAN_F22R2_FB12_Pos)
11300#define CAN_F22R2_FB12 CAN_F22R2_FB12_Msk
11301#define CAN_F22R2_FB13_Pos (13U)
11302#define CAN_F22R2_FB13_Msk (0x1UL << CAN_F22R2_FB13_Pos)
11303#define CAN_F22R2_FB13 CAN_F22R2_FB13_Msk
11304#define CAN_F22R2_FB14_Pos (14U)
11305#define CAN_F22R2_FB14_Msk (0x1UL << CAN_F22R2_FB14_Pos)
11306#define CAN_F22R2_FB14 CAN_F22R2_FB14_Msk
11307#define CAN_F22R2_FB15_Pos (15U)
11308#define CAN_F22R2_FB15_Msk (0x1UL << CAN_F22R2_FB15_Pos)
11309#define CAN_F22R2_FB15 CAN_F22R2_FB15_Msk
11310#define CAN_F22R2_FB16_Pos (16U)
11311#define CAN_F22R2_FB16_Msk (0x1UL << CAN_F22R2_FB16_Pos)
11312#define CAN_F22R2_FB16 CAN_F22R2_FB16_Msk
11313#define CAN_F22R2_FB17_Pos (17U)
11314#define CAN_F22R2_FB17_Msk (0x1UL << CAN_F22R2_FB17_Pos)
11315#define CAN_F22R2_FB17 CAN_F22R2_FB17_Msk
11316#define CAN_F22R2_FB18_Pos (18U)
11317#define CAN_F22R2_FB18_Msk (0x1UL << CAN_F22R2_FB18_Pos)
11318#define CAN_F22R2_FB18 CAN_F22R2_FB18_Msk
11319#define CAN_F22R2_FB19_Pos (19U)
11320#define CAN_F22R2_FB19_Msk (0x1UL << CAN_F22R2_FB19_Pos)
11321#define CAN_F22R2_FB19 CAN_F22R2_FB19_Msk
11322#define CAN_F22R2_FB20_Pos (20U)
11323#define CAN_F22R2_FB20_Msk (0x1UL << CAN_F22R2_FB20_Pos)
11324#define CAN_F22R2_FB20 CAN_F22R2_FB20_Msk
11325#define CAN_F22R2_FB21_Pos (21U)
11326#define CAN_F22R2_FB21_Msk (0x1UL << CAN_F22R2_FB21_Pos)
11327#define CAN_F22R2_FB21 CAN_F22R2_FB21_Msk
11328#define CAN_F22R2_FB22_Pos (22U)
11329#define CAN_F22R2_FB22_Msk (0x1UL << CAN_F22R2_FB22_Pos)
11330#define CAN_F22R2_FB22 CAN_F22R2_FB22_Msk
11331#define CAN_F22R2_FB23_Pos (23U)
11332#define CAN_F22R2_FB23_Msk (0x1UL << CAN_F22R2_FB23_Pos)
11333#define CAN_F22R2_FB23 CAN_F22R2_FB23_Msk
11334#define CAN_F22R2_FB24_Pos (24U)
11335#define CAN_F22R2_FB24_Msk (0x1UL << CAN_F22R2_FB24_Pos)
11336#define CAN_F22R2_FB24 CAN_F22R2_FB24_Msk
11337#define CAN_F22R2_FB25_Pos (25U)
11338#define CAN_F22R2_FB25_Msk (0x1UL << CAN_F22R2_FB25_Pos)
11339#define CAN_F22R2_FB25 CAN_F22R2_FB25_Msk
11340#define CAN_F22R2_FB26_Pos (26U)
11341#define CAN_F22R2_FB26_Msk (0x1UL << CAN_F22R2_FB26_Pos)
11342#define CAN_F22R2_FB26 CAN_F22R2_FB26_Msk
11343#define CAN_F22R2_FB27_Pos (27U)
11344#define CAN_F22R2_FB27_Msk (0x1UL << CAN_F22R2_FB27_Pos)
11345#define CAN_F22R2_FB27 CAN_F22R2_FB27_Msk
11346#define CAN_F22R2_FB28_Pos (28U)
11347#define CAN_F22R2_FB28_Msk (0x1UL << CAN_F22R2_FB28_Pos)
11348#define CAN_F22R2_FB28 CAN_F22R2_FB28_Msk
11349#define CAN_F22R2_FB29_Pos (29U)
11350#define CAN_F22R2_FB29_Msk (0x1UL << CAN_F22R2_FB29_Pos)
11351#define CAN_F22R2_FB29 CAN_F22R2_FB29_Msk
11352#define CAN_F22R2_FB30_Pos (30U)
11353#define CAN_F22R2_FB30_Msk (0x1UL << CAN_F22R2_FB30_Pos)
11354#define CAN_F22R2_FB30 CAN_F22R2_FB30_Msk
11355#define CAN_F22R2_FB31_Pos (31U)
11356#define CAN_F22R2_FB31_Msk (0x1UL << CAN_F22R2_FB31_Pos)
11357#define CAN_F22R2_FB31 CAN_F22R2_FB31_Msk
11359/******************* Bit definition for CAN_F23R2 register ******************/
11360#define CAN_F23R2_FB0_Pos (0U)
11361#define CAN_F23R2_FB0_Msk (0x1UL << CAN_F23R2_FB0_Pos)
11362#define CAN_F23R2_FB0 CAN_F23R2_FB0_Msk
11363#define CAN_F23R2_FB1_Pos (1U)
11364#define CAN_F23R2_FB1_Msk (0x1UL << CAN_F23R2_FB1_Pos)
11365#define CAN_F23R2_FB1 CAN_F23R2_FB1_Msk
11366#define CAN_F23R2_FB2_Pos (2U)
11367#define CAN_F23R2_FB2_Msk (0x1UL << CAN_F23R2_FB2_Pos)
11368#define CAN_F23R2_FB2 CAN_F23R2_FB2_Msk
11369#define CAN_F23R2_FB3_Pos (3U)
11370#define CAN_F23R2_FB3_Msk (0x1UL << CAN_F23R2_FB3_Pos)
11371#define CAN_F23R2_FB3 CAN_F23R2_FB3_Msk
11372#define CAN_F23R2_FB4_Pos (4U)
11373#define CAN_F23R2_FB4_Msk (0x1UL << CAN_F23R2_FB4_Pos)
11374#define CAN_F23R2_FB4 CAN_F23R2_FB4_Msk
11375#define CAN_F23R2_FB5_Pos (5U)
11376#define CAN_F23R2_FB5_Msk (0x1UL << CAN_F23R2_FB5_Pos)
11377#define CAN_F23R2_FB5 CAN_F23R2_FB5_Msk
11378#define CAN_F23R2_FB6_Pos (6U)
11379#define CAN_F23R2_FB6_Msk (0x1UL << CAN_F23R2_FB6_Pos)
11380#define CAN_F23R2_FB6 CAN_F23R2_FB6_Msk
11381#define CAN_F23R2_FB7_Pos (7U)
11382#define CAN_F23R2_FB7_Msk (0x1UL << CAN_F23R2_FB7_Pos)
11383#define CAN_F23R2_FB7 CAN_F23R2_FB7_Msk
11384#define CAN_F23R2_FB8_Pos (8U)
11385#define CAN_F23R2_FB8_Msk (0x1UL << CAN_F23R2_FB8_Pos)
11386#define CAN_F23R2_FB8 CAN_F23R2_FB8_Msk
11387#define CAN_F23R2_FB9_Pos (9U)
11388#define CAN_F23R2_FB9_Msk (0x1UL << CAN_F23R2_FB9_Pos)
11389#define CAN_F23R2_FB9 CAN_F23R2_FB9_Msk
11390#define CAN_F23R2_FB10_Pos (10U)
11391#define CAN_F23R2_FB10_Msk (0x1UL << CAN_F23R2_FB10_Pos)
11392#define CAN_F23R2_FB10 CAN_F23R2_FB10_Msk
11393#define CAN_F23R2_FB11_Pos (11U)
11394#define CAN_F23R2_FB11_Msk (0x1UL << CAN_F23R2_FB11_Pos)
11395#define CAN_F23R2_FB11 CAN_F23R2_FB11_Msk
11396#define CAN_F23R2_FB12_Pos (12U)
11397#define CAN_F23R2_FB12_Msk (0x1UL << CAN_F23R2_FB12_Pos)
11398#define CAN_F23R2_FB12 CAN_F23R2_FB12_Msk
11399#define CAN_F23R2_FB13_Pos (13U)
11400#define CAN_F23R2_FB13_Msk (0x1UL << CAN_F23R2_FB13_Pos)
11401#define CAN_F23R2_FB13 CAN_F23R2_FB13_Msk
11402#define CAN_F23R2_FB14_Pos (14U)
11403#define CAN_F23R2_FB14_Msk (0x1UL << CAN_F23R2_FB14_Pos)
11404#define CAN_F23R2_FB14 CAN_F23R2_FB14_Msk
11405#define CAN_F23R2_FB15_Pos (15U)
11406#define CAN_F23R2_FB15_Msk (0x1UL << CAN_F23R2_FB15_Pos)
11407#define CAN_F23R2_FB15 CAN_F23R2_FB15_Msk
11408#define CAN_F23R2_FB16_Pos (16U)
11409#define CAN_F23R2_FB16_Msk (0x1UL << CAN_F23R2_FB16_Pos)
11410#define CAN_F23R2_FB16 CAN_F23R2_FB16_Msk
11411#define CAN_F23R2_FB17_Pos (17U)
11412#define CAN_F23R2_FB17_Msk (0x1UL << CAN_F23R2_FB17_Pos)
11413#define CAN_F23R2_FB17 CAN_F23R2_FB17_Msk
11414#define CAN_F23R2_FB18_Pos (18U)
11415#define CAN_F23R2_FB18_Msk (0x1UL << CAN_F23R2_FB18_Pos)
11416#define CAN_F23R2_FB18 CAN_F23R2_FB18_Msk
11417#define CAN_F23R2_FB19_Pos (19U)
11418#define CAN_F23R2_FB19_Msk (0x1UL << CAN_F23R2_FB19_Pos)
11419#define CAN_F23R2_FB19 CAN_F23R2_FB19_Msk
11420#define CAN_F23R2_FB20_Pos (20U)
11421#define CAN_F23R2_FB20_Msk (0x1UL << CAN_F23R2_FB20_Pos)
11422#define CAN_F23R2_FB20 CAN_F23R2_FB20_Msk
11423#define CAN_F23R2_FB21_Pos (21U)
11424#define CAN_F23R2_FB21_Msk (0x1UL << CAN_F23R2_FB21_Pos)
11425#define CAN_F23R2_FB21 CAN_F23R2_FB21_Msk
11426#define CAN_F23R2_FB22_Pos (22U)
11427#define CAN_F23R2_FB22_Msk (0x1UL << CAN_F23R2_FB22_Pos)
11428#define CAN_F23R2_FB22 CAN_F23R2_FB22_Msk
11429#define CAN_F23R2_FB23_Pos (23U)
11430#define CAN_F23R2_FB23_Msk (0x1UL << CAN_F23R2_FB23_Pos)
11431#define CAN_F23R2_FB23 CAN_F23R2_FB23_Msk
11432#define CAN_F23R2_FB24_Pos (24U)
11433#define CAN_F23R2_FB24_Msk (0x1UL << CAN_F23R2_FB24_Pos)
11434#define CAN_F23R2_FB24 CAN_F23R2_FB24_Msk
11435#define CAN_F23R2_FB25_Pos (25U)
11436#define CAN_F23R2_FB25_Msk (0x1UL << CAN_F23R2_FB25_Pos)
11437#define CAN_F23R2_FB25 CAN_F23R2_FB25_Msk
11438#define CAN_F23R2_FB26_Pos (26U)
11439#define CAN_F23R2_FB26_Msk (0x1UL << CAN_F23R2_FB26_Pos)
11440#define CAN_F23R2_FB26 CAN_F23R2_FB26_Msk
11441#define CAN_F23R2_FB27_Pos (27U)
11442#define CAN_F23R2_FB27_Msk (0x1UL << CAN_F23R2_FB27_Pos)
11443#define CAN_F23R2_FB27 CAN_F23R2_FB27_Msk
11444#define CAN_F23R2_FB28_Pos (28U)
11445#define CAN_F23R2_FB28_Msk (0x1UL << CAN_F23R2_FB28_Pos)
11446#define CAN_F23R2_FB28 CAN_F23R2_FB28_Msk
11447#define CAN_F23R2_FB29_Pos (29U)
11448#define CAN_F23R2_FB29_Msk (0x1UL << CAN_F23R2_FB29_Pos)
11449#define CAN_F23R2_FB29 CAN_F23R2_FB29_Msk
11450#define CAN_F23R2_FB30_Pos (30U)
11451#define CAN_F23R2_FB30_Msk (0x1UL << CAN_F23R2_FB30_Pos)
11452#define CAN_F23R2_FB30 CAN_F23R2_FB30_Msk
11453#define CAN_F23R2_FB31_Pos (31U)
11454#define CAN_F23R2_FB31_Msk (0x1UL << CAN_F23R2_FB31_Pos)
11455#define CAN_F23R2_FB31 CAN_F23R2_FB31_Msk
11457/******************* Bit definition for CAN_F24R2 register ******************/
11458#define CAN_F24R2_FB0_Pos (0U)
11459#define CAN_F24R2_FB0_Msk (0x1UL << CAN_F24R2_FB0_Pos)
11460#define CAN_F24R2_FB0 CAN_F24R2_FB0_Msk
11461#define CAN_F24R2_FB1_Pos (1U)
11462#define CAN_F24R2_FB1_Msk (0x1UL << CAN_F24R2_FB1_Pos)
11463#define CAN_F24R2_FB1 CAN_F24R2_FB1_Msk
11464#define CAN_F24R2_FB2_Pos (2U)
11465#define CAN_F24R2_FB2_Msk (0x1UL << CAN_F24R2_FB2_Pos)
11466#define CAN_F24R2_FB2 CAN_F24R2_FB2_Msk
11467#define CAN_F24R2_FB3_Pos (3U)
11468#define CAN_F24R2_FB3_Msk (0x1UL << CAN_F24R2_FB3_Pos)
11469#define CAN_F24R2_FB3 CAN_F24R2_FB3_Msk
11470#define CAN_F24R2_FB4_Pos (4U)
11471#define CAN_F24R2_FB4_Msk (0x1UL << CAN_F24R2_FB4_Pos)
11472#define CAN_F24R2_FB4 CAN_F24R2_FB4_Msk
11473#define CAN_F24R2_FB5_Pos (5U)
11474#define CAN_F24R2_FB5_Msk (0x1UL << CAN_F24R2_FB5_Pos)
11475#define CAN_F24R2_FB5 CAN_F24R2_FB5_Msk
11476#define CAN_F24R2_FB6_Pos (6U)
11477#define CAN_F24R2_FB6_Msk (0x1UL << CAN_F24R2_FB6_Pos)
11478#define CAN_F24R2_FB6 CAN_F24R2_FB6_Msk
11479#define CAN_F24R2_FB7_Pos (7U)
11480#define CAN_F24R2_FB7_Msk (0x1UL << CAN_F24R2_FB7_Pos)
11481#define CAN_F24R2_FB7 CAN_F24R2_FB7_Msk
11482#define CAN_F24R2_FB8_Pos (8U)
11483#define CAN_F24R2_FB8_Msk (0x1UL << CAN_F24R2_FB8_Pos)
11484#define CAN_F24R2_FB8 CAN_F24R2_FB8_Msk
11485#define CAN_F24R2_FB9_Pos (9U)
11486#define CAN_F24R2_FB9_Msk (0x1UL << CAN_F24R2_FB9_Pos)
11487#define CAN_F24R2_FB9 CAN_F24R2_FB9_Msk
11488#define CAN_F24R2_FB10_Pos (10U)
11489#define CAN_F24R2_FB10_Msk (0x1UL << CAN_F24R2_FB10_Pos)
11490#define CAN_F24R2_FB10 CAN_F24R2_FB10_Msk
11491#define CAN_F24R2_FB11_Pos (11U)
11492#define CAN_F24R2_FB11_Msk (0x1UL << CAN_F24R2_FB11_Pos)
11493#define CAN_F24R2_FB11 CAN_F24R2_FB11_Msk
11494#define CAN_F24R2_FB12_Pos (12U)
11495#define CAN_F24R2_FB12_Msk (0x1UL << CAN_F24R2_FB12_Pos)
11496#define CAN_F24R2_FB12 CAN_F24R2_FB12_Msk
11497#define CAN_F24R2_FB13_Pos (13U)
11498#define CAN_F24R2_FB13_Msk (0x1UL << CAN_F24R2_FB13_Pos)
11499#define CAN_F24R2_FB13 CAN_F24R2_FB13_Msk
11500#define CAN_F24R2_FB14_Pos (14U)
11501#define CAN_F24R2_FB14_Msk (0x1UL << CAN_F24R2_FB14_Pos)
11502#define CAN_F24R2_FB14 CAN_F24R2_FB14_Msk
11503#define CAN_F24R2_FB15_Pos (15U)
11504#define CAN_F24R2_FB15_Msk (0x1UL << CAN_F24R2_FB15_Pos)
11505#define CAN_F24R2_FB15 CAN_F24R2_FB15_Msk
11506#define CAN_F24R2_FB16_Pos (16U)
11507#define CAN_F24R2_FB16_Msk (0x1UL << CAN_F24R2_FB16_Pos)
11508#define CAN_F24R2_FB16 CAN_F24R2_FB16_Msk
11509#define CAN_F24R2_FB17_Pos (17U)
11510#define CAN_F24R2_FB17_Msk (0x1UL << CAN_F24R2_FB17_Pos)
11511#define CAN_F24R2_FB17 CAN_F24R2_FB17_Msk
11512#define CAN_F24R2_FB18_Pos (18U)
11513#define CAN_F24R2_FB18_Msk (0x1UL << CAN_F24R2_FB18_Pos)
11514#define CAN_F24R2_FB18 CAN_F24R2_FB18_Msk
11515#define CAN_F24R2_FB19_Pos (19U)
11516#define CAN_F24R2_FB19_Msk (0x1UL << CAN_F24R2_FB19_Pos)
11517#define CAN_F24R2_FB19 CAN_F24R2_FB19_Msk
11518#define CAN_F24R2_FB20_Pos (20U)
11519#define CAN_F24R2_FB20_Msk (0x1UL << CAN_F24R2_FB20_Pos)
11520#define CAN_F24R2_FB20 CAN_F24R2_FB20_Msk
11521#define CAN_F24R2_FB21_Pos (21U)
11522#define CAN_F24R2_FB21_Msk (0x1UL << CAN_F24R2_FB21_Pos)
11523#define CAN_F24R2_FB21 CAN_F24R2_FB21_Msk
11524#define CAN_F24R2_FB22_Pos (22U)
11525#define CAN_F24R2_FB22_Msk (0x1UL << CAN_F24R2_FB22_Pos)
11526#define CAN_F24R2_FB22 CAN_F24R2_FB22_Msk
11527#define CAN_F24R2_FB23_Pos (23U)
11528#define CAN_F24R2_FB23_Msk (0x1UL << CAN_F24R2_FB23_Pos)
11529#define CAN_F24R2_FB23 CAN_F24R2_FB23_Msk
11530#define CAN_F24R2_FB24_Pos (24U)
11531#define CAN_F24R2_FB24_Msk (0x1UL << CAN_F24R2_FB24_Pos)
11532#define CAN_F24R2_FB24 CAN_F24R2_FB24_Msk
11533#define CAN_F24R2_FB25_Pos (25U)
11534#define CAN_F24R2_FB25_Msk (0x1UL << CAN_F24R2_FB25_Pos)
11535#define CAN_F24R2_FB25 CAN_F24R2_FB25_Msk
11536#define CAN_F24R2_FB26_Pos (26U)
11537#define CAN_F24R2_FB26_Msk (0x1UL << CAN_F24R2_FB26_Pos)
11538#define CAN_F24R2_FB26 CAN_F24R2_FB26_Msk
11539#define CAN_F24R2_FB27_Pos (27U)
11540#define CAN_F24R2_FB27_Msk (0x1UL << CAN_F24R2_FB27_Pos)
11541#define CAN_F24R2_FB27 CAN_F24R2_FB27_Msk
11542#define CAN_F24R2_FB28_Pos (28U)
11543#define CAN_F24R2_FB28_Msk (0x1UL << CAN_F24R2_FB28_Pos)
11544#define CAN_F24R2_FB28 CAN_F24R2_FB28_Msk
11545#define CAN_F24R2_FB29_Pos (29U)
11546#define CAN_F24R2_FB29_Msk (0x1UL << CAN_F24R2_FB29_Pos)
11547#define CAN_F24R2_FB29 CAN_F24R2_FB29_Msk
11548#define CAN_F24R2_FB30_Pos (30U)
11549#define CAN_F24R2_FB30_Msk (0x1UL << CAN_F24R2_FB30_Pos)
11550#define CAN_F24R2_FB30 CAN_F24R2_FB30_Msk
11551#define CAN_F24R2_FB31_Pos (31U)
11552#define CAN_F24R2_FB31_Msk (0x1UL << CAN_F24R2_FB31_Pos)
11553#define CAN_F24R2_FB31 CAN_F24R2_FB31_Msk
11555/******************* Bit definition for CAN_F25R2 register ******************/
11556#define CAN_F25R2_FB0_Pos (0U)
11557#define CAN_F25R2_FB0_Msk (0x1UL << CAN_F25R2_FB0_Pos)
11558#define CAN_F25R2_FB0 CAN_F25R2_FB0_Msk
11559#define CAN_F25R2_FB1_Pos (1U)
11560#define CAN_F25R2_FB1_Msk (0x1UL << CAN_F25R2_FB1_Pos)
11561#define CAN_F25R2_FB1 CAN_F25R2_FB1_Msk
11562#define CAN_F25R2_FB2_Pos (2U)
11563#define CAN_F25R2_FB2_Msk (0x1UL << CAN_F25R2_FB2_Pos)
11564#define CAN_F25R2_FB2 CAN_F25R2_FB2_Msk
11565#define CAN_F25R2_FB3_Pos (3U)
11566#define CAN_F25R2_FB3_Msk (0x1UL << CAN_F25R2_FB3_Pos)
11567#define CAN_F25R2_FB3 CAN_F25R2_FB3_Msk
11568#define CAN_F25R2_FB4_Pos (4U)
11569#define CAN_F25R2_FB4_Msk (0x1UL << CAN_F25R2_FB4_Pos)
11570#define CAN_F25R2_FB4 CAN_F25R2_FB4_Msk
11571#define CAN_F25R2_FB5_Pos (5U)
11572#define CAN_F25R2_FB5_Msk (0x1UL << CAN_F25R2_FB5_Pos)
11573#define CAN_F25R2_FB5 CAN_F25R2_FB5_Msk
11574#define CAN_F25R2_FB6_Pos (6U)
11575#define CAN_F25R2_FB6_Msk (0x1UL << CAN_F25R2_FB6_Pos)
11576#define CAN_F25R2_FB6 CAN_F25R2_FB6_Msk
11577#define CAN_F25R2_FB7_Pos (7U)
11578#define CAN_F25R2_FB7_Msk (0x1UL << CAN_F25R2_FB7_Pos)
11579#define CAN_F25R2_FB7 CAN_F25R2_FB7_Msk
11580#define CAN_F25R2_FB8_Pos (8U)
11581#define CAN_F25R2_FB8_Msk (0x1UL << CAN_F25R2_FB8_Pos)
11582#define CAN_F25R2_FB8 CAN_F25R2_FB8_Msk
11583#define CAN_F25R2_FB9_Pos (9U)
11584#define CAN_F25R2_FB9_Msk (0x1UL << CAN_F25R2_FB9_Pos)
11585#define CAN_F25R2_FB9 CAN_F25R2_FB9_Msk
11586#define CAN_F25R2_FB10_Pos (10U)
11587#define CAN_F25R2_FB10_Msk (0x1UL << CAN_F25R2_FB10_Pos)
11588#define CAN_F25R2_FB10 CAN_F25R2_FB10_Msk
11589#define CAN_F25R2_FB11_Pos (11U)
11590#define CAN_F25R2_FB11_Msk (0x1UL << CAN_F25R2_FB11_Pos)
11591#define CAN_F25R2_FB11 CAN_F25R2_FB11_Msk
11592#define CAN_F25R2_FB12_Pos (12U)
11593#define CAN_F25R2_FB12_Msk (0x1UL << CAN_F25R2_FB12_Pos)
11594#define CAN_F25R2_FB12 CAN_F25R2_FB12_Msk
11595#define CAN_F25R2_FB13_Pos (13U)
11596#define CAN_F25R2_FB13_Msk (0x1UL << CAN_F25R2_FB13_Pos)
11597#define CAN_F25R2_FB13 CAN_F25R2_FB13_Msk
11598#define CAN_F25R2_FB14_Pos (14U)
11599#define CAN_F25R2_FB14_Msk (0x1UL << CAN_F25R2_FB14_Pos)
11600#define CAN_F25R2_FB14 CAN_F25R2_FB14_Msk
11601#define CAN_F25R2_FB15_Pos (15U)
11602#define CAN_F25R2_FB15_Msk (0x1UL << CAN_F25R2_FB15_Pos)
11603#define CAN_F25R2_FB15 CAN_F25R2_FB15_Msk
11604#define CAN_F25R2_FB16_Pos (16U)
11605#define CAN_F25R2_FB16_Msk (0x1UL << CAN_F25R2_FB16_Pos)
11606#define CAN_F25R2_FB16 CAN_F25R2_FB16_Msk
11607#define CAN_F25R2_FB17_Pos (17U)
11608#define CAN_F25R2_FB17_Msk (0x1UL << CAN_F25R2_FB17_Pos)
11609#define CAN_F25R2_FB17 CAN_F25R2_FB17_Msk
11610#define CAN_F25R2_FB18_Pos (18U)
11611#define CAN_F25R2_FB18_Msk (0x1UL << CAN_F25R2_FB18_Pos)
11612#define CAN_F25R2_FB18 CAN_F25R2_FB18_Msk
11613#define CAN_F25R2_FB19_Pos (19U)
11614#define CAN_F25R2_FB19_Msk (0x1UL << CAN_F25R2_FB19_Pos)
11615#define CAN_F25R2_FB19 CAN_F25R2_FB19_Msk
11616#define CAN_F25R2_FB20_Pos (20U)
11617#define CAN_F25R2_FB20_Msk (0x1UL << CAN_F25R2_FB20_Pos)
11618#define CAN_F25R2_FB20 CAN_F25R2_FB20_Msk
11619#define CAN_F25R2_FB21_Pos (21U)
11620#define CAN_F25R2_FB21_Msk (0x1UL << CAN_F25R2_FB21_Pos)
11621#define CAN_F25R2_FB21 CAN_F25R2_FB21_Msk
11622#define CAN_F25R2_FB22_Pos (22U)
11623#define CAN_F25R2_FB22_Msk (0x1UL << CAN_F25R2_FB22_Pos)
11624#define CAN_F25R2_FB22 CAN_F25R2_FB22_Msk
11625#define CAN_F25R2_FB23_Pos (23U)
11626#define CAN_F25R2_FB23_Msk (0x1UL << CAN_F25R2_FB23_Pos)
11627#define CAN_F25R2_FB23 CAN_F25R2_FB23_Msk
11628#define CAN_F25R2_FB24_Pos (24U)
11629#define CAN_F25R2_FB24_Msk (0x1UL << CAN_F25R2_FB24_Pos)
11630#define CAN_F25R2_FB24 CAN_F25R2_FB24_Msk
11631#define CAN_F25R2_FB25_Pos (25U)
11632#define CAN_F25R2_FB25_Msk (0x1UL << CAN_F25R2_FB25_Pos)
11633#define CAN_F25R2_FB25 CAN_F25R2_FB25_Msk
11634#define CAN_F25R2_FB26_Pos (26U)
11635#define CAN_F25R2_FB26_Msk (0x1UL << CAN_F25R2_FB26_Pos)
11636#define CAN_F25R2_FB26 CAN_F25R2_FB26_Msk
11637#define CAN_F25R2_FB27_Pos (27U)
11638#define CAN_F25R2_FB27_Msk (0x1UL << CAN_F25R2_FB27_Pos)
11639#define CAN_F25R2_FB27 CAN_F25R2_FB27_Msk
11640#define CAN_F25R2_FB28_Pos (28U)
11641#define CAN_F25R2_FB28_Msk (0x1UL << CAN_F25R2_FB28_Pos)
11642#define CAN_F25R2_FB28 CAN_F25R2_FB28_Msk
11643#define CAN_F25R2_FB29_Pos (29U)
11644#define CAN_F25R2_FB29_Msk (0x1UL << CAN_F25R2_FB29_Pos)
11645#define CAN_F25R2_FB29 CAN_F25R2_FB29_Msk
11646#define CAN_F25R2_FB30_Pos (30U)
11647#define CAN_F25R2_FB30_Msk (0x1UL << CAN_F25R2_FB30_Pos)
11648#define CAN_F25R2_FB30 CAN_F25R2_FB30_Msk
11649#define CAN_F25R2_FB31_Pos (31U)
11650#define CAN_F25R2_FB31_Msk (0x1UL << CAN_F25R2_FB31_Pos)
11651#define CAN_F25R2_FB31 CAN_F25R2_FB31_Msk
11653/******************* Bit definition for CAN_F26R2 register ******************/
11654#define CAN_F26R2_FB0_Pos (0U)
11655#define CAN_F26R2_FB0_Msk (0x1UL << CAN_F26R2_FB0_Pos)
11656#define CAN_F26R2_FB0 CAN_F26R2_FB0_Msk
11657#define CAN_F26R2_FB1_Pos (1U)
11658#define CAN_F26R2_FB1_Msk (0x1UL << CAN_F26R2_FB1_Pos)
11659#define CAN_F26R2_FB1 CAN_F26R2_FB1_Msk
11660#define CAN_F26R2_FB2_Pos (2U)
11661#define CAN_F26R2_FB2_Msk (0x1UL << CAN_F26R2_FB2_Pos)
11662#define CAN_F26R2_FB2 CAN_F26R2_FB2_Msk
11663#define CAN_F26R2_FB3_Pos (3U)
11664#define CAN_F26R2_FB3_Msk (0x1UL << CAN_F26R2_FB3_Pos)
11665#define CAN_F26R2_FB3 CAN_F26R2_FB3_Msk
11666#define CAN_F26R2_FB4_Pos (4U)
11667#define CAN_F26R2_FB4_Msk (0x1UL << CAN_F26R2_FB4_Pos)
11668#define CAN_F26R2_FB4 CAN_F26R2_FB4_Msk
11669#define CAN_F26R2_FB5_Pos (5U)
11670#define CAN_F26R2_FB5_Msk (0x1UL << CAN_F26R2_FB5_Pos)
11671#define CAN_F26R2_FB5 CAN_F26R2_FB5_Msk
11672#define CAN_F26R2_FB6_Pos (6U)
11673#define CAN_F26R2_FB6_Msk (0x1UL << CAN_F26R2_FB6_Pos)
11674#define CAN_F26R2_FB6 CAN_F26R2_FB6_Msk
11675#define CAN_F26R2_FB7_Pos (7U)
11676#define CAN_F26R2_FB7_Msk (0x1UL << CAN_F26R2_FB7_Pos)
11677#define CAN_F26R2_FB7 CAN_F26R2_FB7_Msk
11678#define CAN_F26R2_FB8_Pos (8U)
11679#define CAN_F26R2_FB8_Msk (0x1UL << CAN_F26R2_FB8_Pos)
11680#define CAN_F26R2_FB8 CAN_F26R2_FB8_Msk
11681#define CAN_F26R2_FB9_Pos (9U)
11682#define CAN_F26R2_FB9_Msk (0x1UL << CAN_F26R2_FB9_Pos)
11683#define CAN_F26R2_FB9 CAN_F26R2_FB9_Msk
11684#define CAN_F26R2_FB10_Pos (10U)
11685#define CAN_F26R2_FB10_Msk (0x1UL << CAN_F26R2_FB10_Pos)
11686#define CAN_F26R2_FB10 CAN_F26R2_FB10_Msk
11687#define CAN_F26R2_FB11_Pos (11U)
11688#define CAN_F26R2_FB11_Msk (0x1UL << CAN_F26R2_FB11_Pos)
11689#define CAN_F26R2_FB11 CAN_F26R2_FB11_Msk
11690#define CAN_F26R2_FB12_Pos (12U)
11691#define CAN_F26R2_FB12_Msk (0x1UL << CAN_F26R2_FB12_Pos)
11692#define CAN_F26R2_FB12 CAN_F26R2_FB12_Msk
11693#define CAN_F26R2_FB13_Pos (13U)
11694#define CAN_F26R2_FB13_Msk (0x1UL << CAN_F26R2_FB13_Pos)
11695#define CAN_F26R2_FB13 CAN_F26R2_FB13_Msk
11696#define CAN_F26R2_FB14_Pos (14U)
11697#define CAN_F26R2_FB14_Msk (0x1UL << CAN_F26R2_FB14_Pos)
11698#define CAN_F26R2_FB14 CAN_F26R2_FB14_Msk
11699#define CAN_F26R2_FB15_Pos (15U)
11700#define CAN_F26R2_FB15_Msk (0x1UL << CAN_F26R2_FB15_Pos)
11701#define CAN_F26R2_FB15 CAN_F26R2_FB15_Msk
11702#define CAN_F26R2_FB16_Pos (16U)
11703#define CAN_F26R2_FB16_Msk (0x1UL << CAN_F26R2_FB16_Pos)
11704#define CAN_F26R2_FB16 CAN_F26R2_FB16_Msk
11705#define CAN_F26R2_FB17_Pos (17U)
11706#define CAN_F26R2_FB17_Msk (0x1UL << CAN_F26R2_FB17_Pos)
11707#define CAN_F26R2_FB17 CAN_F26R2_FB17_Msk
11708#define CAN_F26R2_FB18_Pos (18U)
11709#define CAN_F26R2_FB18_Msk (0x1UL << CAN_F26R2_FB18_Pos)
11710#define CAN_F26R2_FB18 CAN_F26R2_FB18_Msk
11711#define CAN_F26R2_FB19_Pos (19U)
11712#define CAN_F26R2_FB19_Msk (0x1UL << CAN_F26R2_FB19_Pos)
11713#define CAN_F26R2_FB19 CAN_F26R2_FB19_Msk
11714#define CAN_F26R2_FB20_Pos (20U)
11715#define CAN_F26R2_FB20_Msk (0x1UL << CAN_F26R2_FB20_Pos)
11716#define CAN_F26R2_FB20 CAN_F26R2_FB20_Msk
11717#define CAN_F26R2_FB21_Pos (21U)
11718#define CAN_F26R2_FB21_Msk (0x1UL << CAN_F26R2_FB21_Pos)
11719#define CAN_F26R2_FB21 CAN_F26R2_FB21_Msk
11720#define CAN_F26R2_FB22_Pos (22U)
11721#define CAN_F26R2_FB22_Msk (0x1UL << CAN_F26R2_FB22_Pos)
11722#define CAN_F26R2_FB22 CAN_F26R2_FB22_Msk
11723#define CAN_F26R2_FB23_Pos (23U)
11724#define CAN_F26R2_FB23_Msk (0x1UL << CAN_F26R2_FB23_Pos)
11725#define CAN_F26R2_FB23 CAN_F26R2_FB23_Msk
11726#define CAN_F26R2_FB24_Pos (24U)
11727#define CAN_F26R2_FB24_Msk (0x1UL << CAN_F26R2_FB24_Pos)
11728#define CAN_F26R2_FB24 CAN_F26R2_FB24_Msk
11729#define CAN_F26R2_FB25_Pos (25U)
11730#define CAN_F26R2_FB25_Msk (0x1UL << CAN_F26R2_FB25_Pos)
11731#define CAN_F26R2_FB25 CAN_F26R2_FB25_Msk
11732#define CAN_F26R2_FB26_Pos (26U)
11733#define CAN_F26R2_FB26_Msk (0x1UL << CAN_F26R2_FB26_Pos)
11734#define CAN_F26R2_FB26 CAN_F26R2_FB26_Msk
11735#define CAN_F26R2_FB27_Pos (27U)
11736#define CAN_F26R2_FB27_Msk (0x1UL << CAN_F26R2_FB27_Pos)
11737#define CAN_F26R2_FB27 CAN_F26R2_FB27_Msk
11738#define CAN_F26R2_FB28_Pos (28U)
11739#define CAN_F26R2_FB28_Msk (0x1UL << CAN_F26R2_FB28_Pos)
11740#define CAN_F26R2_FB28 CAN_F26R2_FB28_Msk
11741#define CAN_F26R2_FB29_Pos (29U)
11742#define CAN_F26R2_FB29_Msk (0x1UL << CAN_F26R2_FB29_Pos)
11743#define CAN_F26R2_FB29 CAN_F26R2_FB29_Msk
11744#define CAN_F26R2_FB30_Pos (30U)
11745#define CAN_F26R2_FB30_Msk (0x1UL << CAN_F26R2_FB30_Pos)
11746#define CAN_F26R2_FB30 CAN_F26R2_FB30_Msk
11747#define CAN_F26R2_FB31_Pos (31U)
11748#define CAN_F26R2_FB31_Msk (0x1UL << CAN_F26R2_FB31_Pos)
11749#define CAN_F26R2_FB31 CAN_F26R2_FB31_Msk
11751/******************* Bit definition for CAN_F27R2 register ******************/
11752#define CAN_F27R2_FB0_Pos (0U)
11753#define CAN_F27R2_FB0_Msk (0x1UL << CAN_F27R2_FB0_Pos)
11754#define CAN_F27R2_FB0 CAN_F27R2_FB0_Msk
11755#define CAN_F27R2_FB1_Pos (1U)
11756#define CAN_F27R2_FB1_Msk (0x1UL << CAN_F27R2_FB1_Pos)
11757#define CAN_F27R2_FB1 CAN_F27R2_FB1_Msk
11758#define CAN_F27R2_FB2_Pos (2U)
11759#define CAN_F27R2_FB2_Msk (0x1UL << CAN_F27R2_FB2_Pos)
11760#define CAN_F27R2_FB2 CAN_F27R2_FB2_Msk
11761#define CAN_F27R2_FB3_Pos (3U)
11762#define CAN_F27R2_FB3_Msk (0x1UL << CAN_F27R2_FB3_Pos)
11763#define CAN_F27R2_FB3 CAN_F27R2_FB3_Msk
11764#define CAN_F27R2_FB4_Pos (4U)
11765#define CAN_F27R2_FB4_Msk (0x1UL << CAN_F27R2_FB4_Pos)
11766#define CAN_F27R2_FB4 CAN_F27R2_FB4_Msk
11767#define CAN_F27R2_FB5_Pos (5U)
11768#define CAN_F27R2_FB5_Msk (0x1UL << CAN_F27R2_FB5_Pos)
11769#define CAN_F27R2_FB5 CAN_F27R2_FB5_Msk
11770#define CAN_F27R2_FB6_Pos (6U)
11771#define CAN_F27R2_FB6_Msk (0x1UL << CAN_F27R2_FB6_Pos)
11772#define CAN_F27R2_FB6 CAN_F27R2_FB6_Msk
11773#define CAN_F27R2_FB7_Pos (7U)
11774#define CAN_F27R2_FB7_Msk (0x1UL << CAN_F27R2_FB7_Pos)
11775#define CAN_F27R2_FB7 CAN_F27R2_FB7_Msk
11776#define CAN_F27R2_FB8_Pos (8U)
11777#define CAN_F27R2_FB8_Msk (0x1UL << CAN_F27R2_FB8_Pos)
11778#define CAN_F27R2_FB8 CAN_F27R2_FB8_Msk
11779#define CAN_F27R2_FB9_Pos (9U)
11780#define CAN_F27R2_FB9_Msk (0x1UL << CAN_F27R2_FB9_Pos)
11781#define CAN_F27R2_FB9 CAN_F27R2_FB9_Msk
11782#define CAN_F27R2_FB10_Pos (10U)
11783#define CAN_F27R2_FB10_Msk (0x1UL << CAN_F27R2_FB10_Pos)
11784#define CAN_F27R2_FB10 CAN_F27R2_FB10_Msk
11785#define CAN_F27R2_FB11_Pos (11U)
11786#define CAN_F27R2_FB11_Msk (0x1UL << CAN_F27R2_FB11_Pos)
11787#define CAN_F27R2_FB11 CAN_F27R2_FB11_Msk
11788#define CAN_F27R2_FB12_Pos (12U)
11789#define CAN_F27R2_FB12_Msk (0x1UL << CAN_F27R2_FB12_Pos)
11790#define CAN_F27R2_FB12 CAN_F27R2_FB12_Msk
11791#define CAN_F27R2_FB13_Pos (13U)
11792#define CAN_F27R2_FB13_Msk (0x1UL << CAN_F27R2_FB13_Pos)
11793#define CAN_F27R2_FB13 CAN_F27R2_FB13_Msk
11794#define CAN_F27R2_FB14_Pos (14U)
11795#define CAN_F27R2_FB14_Msk (0x1UL << CAN_F27R2_FB14_Pos)
11796#define CAN_F27R2_FB14 CAN_F27R2_FB14_Msk
11797#define CAN_F27R2_FB15_Pos (15U)
11798#define CAN_F27R2_FB15_Msk (0x1UL << CAN_F27R2_FB15_Pos)
11799#define CAN_F27R2_FB15 CAN_F27R2_FB15_Msk
11800#define CAN_F27R2_FB16_Pos (16U)
11801#define CAN_F27R2_FB16_Msk (0x1UL << CAN_F27R2_FB16_Pos)
11802#define CAN_F27R2_FB16 CAN_F27R2_FB16_Msk
11803#define CAN_F27R2_FB17_Pos (17U)
11804#define CAN_F27R2_FB17_Msk (0x1UL << CAN_F27R2_FB17_Pos)
11805#define CAN_F27R2_FB17 CAN_F27R2_FB17_Msk
11806#define CAN_F27R2_FB18_Pos (18U)
11807#define CAN_F27R2_FB18_Msk (0x1UL << CAN_F27R2_FB18_Pos)
11808#define CAN_F27R2_FB18 CAN_F27R2_FB18_Msk
11809#define CAN_F27R2_FB19_Pos (19U)
11810#define CAN_F27R2_FB19_Msk (0x1UL << CAN_F27R2_FB19_Pos)
11811#define CAN_F27R2_FB19 CAN_F27R2_FB19_Msk
11812#define CAN_F27R2_FB20_Pos (20U)
11813#define CAN_F27R2_FB20_Msk (0x1UL << CAN_F27R2_FB20_Pos)
11814#define CAN_F27R2_FB20 CAN_F27R2_FB20_Msk
11815#define CAN_F27R2_FB21_Pos (21U)
11816#define CAN_F27R2_FB21_Msk (0x1UL << CAN_F27R2_FB21_Pos)
11817#define CAN_F27R2_FB21 CAN_F27R2_FB21_Msk
11818#define CAN_F27R2_FB22_Pos (22U)
11819#define CAN_F27R2_FB22_Msk (0x1UL << CAN_F27R2_FB22_Pos)
11820#define CAN_F27R2_FB22 CAN_F27R2_FB22_Msk
11821#define CAN_F27R2_FB23_Pos (23U)
11822#define CAN_F27R2_FB23_Msk (0x1UL << CAN_F27R2_FB23_Pos)
11823#define CAN_F27R2_FB23 CAN_F27R2_FB23_Msk
11824#define CAN_F27R2_FB24_Pos (24U)
11825#define CAN_F27R2_FB24_Msk (0x1UL << CAN_F27R2_FB24_Pos)
11826#define CAN_F27R2_FB24 CAN_F27R2_FB24_Msk
11827#define CAN_F27R2_FB25_Pos (25U)
11828#define CAN_F27R2_FB25_Msk (0x1UL << CAN_F27R2_FB25_Pos)
11829#define CAN_F27R2_FB25 CAN_F27R2_FB25_Msk
11830#define CAN_F27R2_FB26_Pos (26U)
11831#define CAN_F27R2_FB26_Msk (0x1UL << CAN_F27R2_FB26_Pos)
11832#define CAN_F27R2_FB26 CAN_F27R2_FB26_Msk
11833#define CAN_F27R2_FB27_Pos (27U)
11834#define CAN_F27R2_FB27_Msk (0x1UL << CAN_F27R2_FB27_Pos)
11835#define CAN_F27R2_FB27 CAN_F27R2_FB27_Msk
11836#define CAN_F27R2_FB28_Pos (28U)
11837#define CAN_F27R2_FB28_Msk (0x1UL << CAN_F27R2_FB28_Pos)
11838#define CAN_F27R2_FB28 CAN_F27R2_FB28_Msk
11839#define CAN_F27R2_FB29_Pos (29U)
11840#define CAN_F27R2_FB29_Msk (0x1UL << CAN_F27R2_FB29_Pos)
11841#define CAN_F27R2_FB29 CAN_F27R2_FB29_Msk
11842#define CAN_F27R2_FB30_Pos (30U)
11843#define CAN_F27R2_FB30_Msk (0x1UL << CAN_F27R2_FB30_Pos)
11844#define CAN_F27R2_FB30 CAN_F27R2_FB30_Msk
11845#define CAN_F27R2_FB31_Pos (31U)
11846#define CAN_F27R2_FB31_Msk (0x1UL << CAN_F27R2_FB31_Pos)
11847#define CAN_F27R2_FB31 CAN_F27R2_FB31_Msk
11849/******************************************************************************/
11850/* */
11851/* Serial Peripheral Interface */
11852/* */
11853/******************************************************************************/
11854/*
11855 * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
11856 */
11857#define SPI_I2S_SUPPORT
11858#define I2S2_I2S3_CLOCK_FEATURE
11859
11860/******************* Bit definition for SPI_CR1 register ********************/
11861#define SPI_CR1_CPHA_Pos (0U)
11862#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
11863#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
11864#define SPI_CR1_CPOL_Pos (1U)
11865#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
11866#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
11867#define SPI_CR1_MSTR_Pos (2U)
11868#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
11869#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
11871#define SPI_CR1_BR_Pos (3U)
11872#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
11873#define SPI_CR1_BR SPI_CR1_BR_Msk
11874#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
11875#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
11876#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
11878#define SPI_CR1_SPE_Pos (6U)
11879#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
11880#define SPI_CR1_SPE SPI_CR1_SPE_Msk
11881#define SPI_CR1_LSBFIRST_Pos (7U)
11882#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
11883#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
11884#define SPI_CR1_SSI_Pos (8U)
11885#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
11886#define SPI_CR1_SSI SPI_CR1_SSI_Msk
11887#define SPI_CR1_SSM_Pos (9U)
11888#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
11889#define SPI_CR1_SSM SPI_CR1_SSM_Msk
11890#define SPI_CR1_RXONLY_Pos (10U)
11891#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
11892#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
11893#define SPI_CR1_DFF_Pos (11U)
11894#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
11895#define SPI_CR1_DFF SPI_CR1_DFF_Msk
11896#define SPI_CR1_CRCNEXT_Pos (12U)
11897#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
11898#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
11899#define SPI_CR1_CRCEN_Pos (13U)
11900#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
11901#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
11902#define SPI_CR1_BIDIOE_Pos (14U)
11903#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
11904#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
11905#define SPI_CR1_BIDIMODE_Pos (15U)
11906#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
11907#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
11909/******************* Bit definition for SPI_CR2 register ********************/
11910#define SPI_CR2_RXDMAEN_Pos (0U)
11911#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
11912#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
11913#define SPI_CR2_TXDMAEN_Pos (1U)
11914#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
11915#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
11916#define SPI_CR2_SSOE_Pos (2U)
11917#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
11918#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
11919#define SPI_CR2_ERRIE_Pos (5U)
11920#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
11921#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
11922#define SPI_CR2_RXNEIE_Pos (6U)
11923#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
11924#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
11925#define SPI_CR2_TXEIE_Pos (7U)
11926#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
11927#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
11929/******************** Bit definition for SPI_SR register ********************/
11930#define SPI_SR_RXNE_Pos (0U)
11931#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
11932#define SPI_SR_RXNE SPI_SR_RXNE_Msk
11933#define SPI_SR_TXE_Pos (1U)
11934#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
11935#define SPI_SR_TXE SPI_SR_TXE_Msk
11936#define SPI_SR_CHSIDE_Pos (2U)
11937#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
11938#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
11939#define SPI_SR_UDR_Pos (3U)
11940#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
11941#define SPI_SR_UDR SPI_SR_UDR_Msk
11942#define SPI_SR_CRCERR_Pos (4U)
11943#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
11944#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
11945#define SPI_SR_MODF_Pos (5U)
11946#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
11947#define SPI_SR_MODF SPI_SR_MODF_Msk
11948#define SPI_SR_OVR_Pos (6U)
11949#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
11950#define SPI_SR_OVR SPI_SR_OVR_Msk
11951#define SPI_SR_BSY_Pos (7U)
11952#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
11953#define SPI_SR_BSY SPI_SR_BSY_Msk
11955/******************** Bit definition for SPI_DR register ********************/
11956#define SPI_DR_DR_Pos (0U)
11957#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
11958#define SPI_DR_DR SPI_DR_DR_Msk
11960/******************* Bit definition for SPI_CRCPR register ******************/
11961#define SPI_CRCPR_CRCPOLY_Pos (0U)
11962#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
11963#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
11965/****************** Bit definition for SPI_RXCRCR register ******************/
11966#define SPI_RXCRCR_RXCRC_Pos (0U)
11967#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
11968#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
11970/****************** Bit definition for SPI_TXCRCR register ******************/
11971#define SPI_TXCRCR_TXCRC_Pos (0U)
11972#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
11973#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
11975/****************** Bit definition for SPI_I2SCFGR register *****************/
11976#define SPI_I2SCFGR_CHLEN_Pos (0U)
11977#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
11978#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
11980#define SPI_I2SCFGR_DATLEN_Pos (1U)
11981#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
11982#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
11983#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
11984#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
11986#define SPI_I2SCFGR_CKPOL_Pos (3U)
11987#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
11988#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
11990#define SPI_I2SCFGR_I2SSTD_Pos (4U)
11991#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
11992#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
11993#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
11994#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
11996#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
11997#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
11998#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
12000#define SPI_I2SCFGR_I2SCFG_Pos (8U)
12001#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
12002#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
12003#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
12004#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
12006#define SPI_I2SCFGR_I2SE_Pos (10U)
12007#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
12008#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
12009#define SPI_I2SCFGR_I2SMOD_Pos (11U)
12010#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
12011#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
12012/****************** Bit definition for SPI_I2SPR register *******************/
12013#define SPI_I2SPR_I2SDIV_Pos (0U)
12014#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
12015#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
12016#define SPI_I2SPR_ODD_Pos (8U)
12017#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
12018#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
12019#define SPI_I2SPR_MCKOE_Pos (9U)
12020#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
12021#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
12023/******************************************************************************/
12024/* */
12025/* Inter-integrated Circuit Interface */
12026/* */
12027/******************************************************************************/
12028
12029/******************* Bit definition for I2C_CR1 register ********************/
12030#define I2C_CR1_PE_Pos (0U)
12031#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
12032#define I2C_CR1_PE I2C_CR1_PE_Msk
12033#define I2C_CR1_SMBUS_Pos (1U)
12034#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
12035#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
12036#define I2C_CR1_SMBTYPE_Pos (3U)
12037#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
12038#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
12039#define I2C_CR1_ENARP_Pos (4U)
12040#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
12041#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
12042#define I2C_CR1_ENPEC_Pos (5U)
12043#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
12044#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
12045#define I2C_CR1_ENGC_Pos (6U)
12046#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
12047#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
12048#define I2C_CR1_NOSTRETCH_Pos (7U)
12049#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
12050#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
12051#define I2C_CR1_START_Pos (8U)
12052#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
12053#define I2C_CR1_START I2C_CR1_START_Msk
12054#define I2C_CR1_STOP_Pos (9U)
12055#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
12056#define I2C_CR1_STOP I2C_CR1_STOP_Msk
12057#define I2C_CR1_ACK_Pos (10U)
12058#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
12059#define I2C_CR1_ACK I2C_CR1_ACK_Msk
12060#define I2C_CR1_POS_Pos (11U)
12061#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
12062#define I2C_CR1_POS I2C_CR1_POS_Msk
12063#define I2C_CR1_PEC_Pos (12U)
12064#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
12065#define I2C_CR1_PEC I2C_CR1_PEC_Msk
12066#define I2C_CR1_ALERT_Pos (13U)
12067#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
12068#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
12069#define I2C_CR1_SWRST_Pos (15U)
12070#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
12071#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
12073/******************* Bit definition for I2C_CR2 register ********************/
12074#define I2C_CR2_FREQ_Pos (0U)
12075#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
12076#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
12077#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
12078#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
12079#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
12080#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
12081#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
12082#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
12084#define I2C_CR2_ITERREN_Pos (8U)
12085#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
12086#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
12087#define I2C_CR2_ITEVTEN_Pos (9U)
12088#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
12089#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
12090#define I2C_CR2_ITBUFEN_Pos (10U)
12091#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
12092#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
12093#define I2C_CR2_DMAEN_Pos (11U)
12094#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
12095#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
12096#define I2C_CR2_LAST_Pos (12U)
12097#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
12098#define I2C_CR2_LAST I2C_CR2_LAST_Msk
12100/******************* Bit definition for I2C_OAR1 register *******************/
12101#define I2C_OAR1_ADD1_7 0x000000FEU
12102#define I2C_OAR1_ADD8_9 0x00000300U
12104#define I2C_OAR1_ADD0_Pos (0U)
12105#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
12106#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
12107#define I2C_OAR1_ADD1_Pos (1U)
12108#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
12109#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
12110#define I2C_OAR1_ADD2_Pos (2U)
12111#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
12112#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
12113#define I2C_OAR1_ADD3_Pos (3U)
12114#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
12115#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
12116#define I2C_OAR1_ADD4_Pos (4U)
12117#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
12118#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
12119#define I2C_OAR1_ADD5_Pos (5U)
12120#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
12121#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
12122#define I2C_OAR1_ADD6_Pos (6U)
12123#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
12124#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
12125#define I2C_OAR1_ADD7_Pos (7U)
12126#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
12127#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
12128#define I2C_OAR1_ADD8_Pos (8U)
12129#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
12130#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
12131#define I2C_OAR1_ADD9_Pos (9U)
12132#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
12133#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
12135#define I2C_OAR1_ADDMODE_Pos (15U)
12136#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
12137#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
12139/******************* Bit definition for I2C_OAR2 register *******************/
12140#define I2C_OAR2_ENDUAL_Pos (0U)
12141#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
12142#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
12143#define I2C_OAR2_ADD2_Pos (1U)
12144#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
12145#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
12147/******************** Bit definition for I2C_DR register ********************/
12148#define I2C_DR_DR_Pos (0U)
12149#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
12150#define I2C_DR_DR I2C_DR_DR_Msk
12152/******************* Bit definition for I2C_SR1 register ********************/
12153#define I2C_SR1_SB_Pos (0U)
12154#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
12155#define I2C_SR1_SB I2C_SR1_SB_Msk
12156#define I2C_SR1_ADDR_Pos (1U)
12157#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
12158#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
12159#define I2C_SR1_BTF_Pos (2U)
12160#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
12161#define I2C_SR1_BTF I2C_SR1_BTF_Msk
12162#define I2C_SR1_ADD10_Pos (3U)
12163#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
12164#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
12165#define I2C_SR1_STOPF_Pos (4U)
12166#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
12167#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
12168#define I2C_SR1_RXNE_Pos (6U)
12169#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
12170#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
12171#define I2C_SR1_TXE_Pos (7U)
12172#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
12173#define I2C_SR1_TXE I2C_SR1_TXE_Msk
12174#define I2C_SR1_BERR_Pos (8U)
12175#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
12176#define I2C_SR1_BERR I2C_SR1_BERR_Msk
12177#define I2C_SR1_ARLO_Pos (9U)
12178#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
12179#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
12180#define I2C_SR1_AF_Pos (10U)
12181#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
12182#define I2C_SR1_AF I2C_SR1_AF_Msk
12183#define I2C_SR1_OVR_Pos (11U)
12184#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
12185#define I2C_SR1_OVR I2C_SR1_OVR_Msk
12186#define I2C_SR1_PECERR_Pos (12U)
12187#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
12188#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
12189#define I2C_SR1_TIMEOUT_Pos (14U)
12190#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
12191#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
12192#define I2C_SR1_SMBALERT_Pos (15U)
12193#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
12194#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
12196/******************* Bit definition for I2C_SR2 register ********************/
12197#define I2C_SR2_MSL_Pos (0U)
12198#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
12199#define I2C_SR2_MSL I2C_SR2_MSL_Msk
12200#define I2C_SR2_BUSY_Pos (1U)
12201#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
12202#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
12203#define I2C_SR2_TRA_Pos (2U)
12204#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
12205#define I2C_SR2_TRA I2C_SR2_TRA_Msk
12206#define I2C_SR2_GENCALL_Pos (4U)
12207#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
12208#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
12209#define I2C_SR2_SMBDEFAULT_Pos (5U)
12210#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
12211#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
12212#define I2C_SR2_SMBHOST_Pos (6U)
12213#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
12214#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
12215#define I2C_SR2_DUALF_Pos (7U)
12216#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
12217#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
12218#define I2C_SR2_PEC_Pos (8U)
12219#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
12220#define I2C_SR2_PEC I2C_SR2_PEC_Msk
12222/******************* Bit definition for I2C_CCR register ********************/
12223#define I2C_CCR_CCR_Pos (0U)
12224#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
12225#define I2C_CCR_CCR I2C_CCR_CCR_Msk
12226#define I2C_CCR_DUTY_Pos (14U)
12227#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
12228#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
12229#define I2C_CCR_FS_Pos (15U)
12230#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
12231#define I2C_CCR_FS I2C_CCR_FS_Msk
12233/****************** Bit definition for I2C_TRISE register *******************/
12234#define I2C_TRISE_TRISE_Pos (0U)
12235#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
12236#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
12238/******************************************************************************/
12239/* */
12240/* Universal Synchronous Asynchronous Receiver Transmitter */
12241/* */
12242/******************************************************************************/
12243
12244/******************* Bit definition for USART_SR register *******************/
12245#define USART_SR_PE_Pos (0U)
12246#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
12247#define USART_SR_PE USART_SR_PE_Msk
12248#define USART_SR_FE_Pos (1U)
12249#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
12250#define USART_SR_FE USART_SR_FE_Msk
12251#define USART_SR_NE_Pos (2U)
12252#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
12253#define USART_SR_NE USART_SR_NE_Msk
12254#define USART_SR_ORE_Pos (3U)
12255#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
12256#define USART_SR_ORE USART_SR_ORE_Msk
12257#define USART_SR_IDLE_Pos (4U)
12258#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
12259#define USART_SR_IDLE USART_SR_IDLE_Msk
12260#define USART_SR_RXNE_Pos (5U)
12261#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
12262#define USART_SR_RXNE USART_SR_RXNE_Msk
12263#define USART_SR_TC_Pos (6U)
12264#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
12265#define USART_SR_TC USART_SR_TC_Msk
12266#define USART_SR_TXE_Pos (7U)
12267#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
12268#define USART_SR_TXE USART_SR_TXE_Msk
12269#define USART_SR_LBD_Pos (8U)
12270#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
12271#define USART_SR_LBD USART_SR_LBD_Msk
12272#define USART_SR_CTS_Pos (9U)
12273#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
12274#define USART_SR_CTS USART_SR_CTS_Msk
12276/******************* Bit definition for USART_DR register *******************/
12277#define USART_DR_DR_Pos (0U)
12278#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
12279#define USART_DR_DR USART_DR_DR_Msk
12281/****************** Bit definition for USART_BRR register *******************/
12282#define USART_BRR_DIV_Fraction_Pos (0U)
12283#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
12284#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
12285#define USART_BRR_DIV_Mantissa_Pos (4U)
12286#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
12287#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
12289/****************** Bit definition for USART_CR1 register *******************/
12290#define USART_CR1_SBK_Pos (0U)
12291#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
12292#define USART_CR1_SBK USART_CR1_SBK_Msk
12293#define USART_CR1_RWU_Pos (1U)
12294#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
12295#define USART_CR1_RWU USART_CR1_RWU_Msk
12296#define USART_CR1_RE_Pos (2U)
12297#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
12298#define USART_CR1_RE USART_CR1_RE_Msk
12299#define USART_CR1_TE_Pos (3U)
12300#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
12301#define USART_CR1_TE USART_CR1_TE_Msk
12302#define USART_CR1_IDLEIE_Pos (4U)
12303#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
12304#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
12305#define USART_CR1_RXNEIE_Pos (5U)
12306#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
12307#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
12308#define USART_CR1_TCIE_Pos (6U)
12309#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
12310#define USART_CR1_TCIE USART_CR1_TCIE_Msk
12311#define USART_CR1_TXEIE_Pos (7U)
12312#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
12313#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
12314#define USART_CR1_PEIE_Pos (8U)
12315#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
12316#define USART_CR1_PEIE USART_CR1_PEIE_Msk
12317#define USART_CR1_PS_Pos (9U)
12318#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
12319#define USART_CR1_PS USART_CR1_PS_Msk
12320#define USART_CR1_PCE_Pos (10U)
12321#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
12322#define USART_CR1_PCE USART_CR1_PCE_Msk
12323#define USART_CR1_WAKE_Pos (11U)
12324#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
12325#define USART_CR1_WAKE USART_CR1_WAKE_Msk
12326#define USART_CR1_M_Pos (12U)
12327#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
12328#define USART_CR1_M USART_CR1_M_Msk
12329#define USART_CR1_UE_Pos (13U)
12330#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
12331#define USART_CR1_UE USART_CR1_UE_Msk
12333/****************** Bit definition for USART_CR2 register *******************/
12334#define USART_CR2_ADD_Pos (0U)
12335#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
12336#define USART_CR2_ADD USART_CR2_ADD_Msk
12337#define USART_CR2_LBDL_Pos (5U)
12338#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
12339#define USART_CR2_LBDL USART_CR2_LBDL_Msk
12340#define USART_CR2_LBDIE_Pos (6U)
12341#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
12342#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
12343#define USART_CR2_LBCL_Pos (8U)
12344#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
12345#define USART_CR2_LBCL USART_CR2_LBCL_Msk
12346#define USART_CR2_CPHA_Pos (9U)
12347#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
12348#define USART_CR2_CPHA USART_CR2_CPHA_Msk
12349#define USART_CR2_CPOL_Pos (10U)
12350#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
12351#define USART_CR2_CPOL USART_CR2_CPOL_Msk
12352#define USART_CR2_CLKEN_Pos (11U)
12353#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
12354#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
12356#define USART_CR2_STOP_Pos (12U)
12357#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
12358#define USART_CR2_STOP USART_CR2_STOP_Msk
12359#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
12360#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
12362#define USART_CR2_LINEN_Pos (14U)
12363#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
12364#define USART_CR2_LINEN USART_CR2_LINEN_Msk
12366/****************** Bit definition for USART_CR3 register *******************/
12367#define USART_CR3_EIE_Pos (0U)
12368#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
12369#define USART_CR3_EIE USART_CR3_EIE_Msk
12370#define USART_CR3_IREN_Pos (1U)
12371#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
12372#define USART_CR3_IREN USART_CR3_IREN_Msk
12373#define USART_CR3_IRLP_Pos (2U)
12374#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
12375#define USART_CR3_IRLP USART_CR3_IRLP_Msk
12376#define USART_CR3_HDSEL_Pos (3U)
12377#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
12378#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
12379#define USART_CR3_NACK_Pos (4U)
12380#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
12381#define USART_CR3_NACK USART_CR3_NACK_Msk
12382#define USART_CR3_SCEN_Pos (5U)
12383#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
12384#define USART_CR3_SCEN USART_CR3_SCEN_Msk
12385#define USART_CR3_DMAR_Pos (6U)
12386#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
12387#define USART_CR3_DMAR USART_CR3_DMAR_Msk
12388#define USART_CR3_DMAT_Pos (7U)
12389#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
12390#define USART_CR3_DMAT USART_CR3_DMAT_Msk
12391#define USART_CR3_RTSE_Pos (8U)
12392#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
12393#define USART_CR3_RTSE USART_CR3_RTSE_Msk
12394#define USART_CR3_CTSE_Pos (9U)
12395#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
12396#define USART_CR3_CTSE USART_CR3_CTSE_Msk
12397#define USART_CR3_CTSIE_Pos (10U)
12398#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
12399#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
12401/****************** Bit definition for USART_GTPR register ******************/
12402#define USART_GTPR_PSC_Pos (0U)
12403#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
12404#define USART_GTPR_PSC USART_GTPR_PSC_Msk
12405#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
12406#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
12407#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
12408#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
12409#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
12410#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
12411#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
12412#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
12414#define USART_GTPR_GT_Pos (8U)
12415#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
12416#define USART_GTPR_GT USART_GTPR_GT_Msk
12418/******************************************************************************/
12419/* */
12420/* Debug MCU */
12421/* */
12422/******************************************************************************/
12423
12424/**************** Bit definition for DBGMCU_IDCODE register *****************/
12425#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
12426#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
12427#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
12429#define DBGMCU_IDCODE_REV_ID_Pos (16U)
12430#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
12431#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
12432#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos)
12433#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos)
12434#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos)
12435#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos)
12436#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos)
12437#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos)
12438#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos)
12439#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos)
12440#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos)
12441#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos)
12442#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos)
12443#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos)
12444#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos)
12445#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos)
12446#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos)
12447#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos)
12449/****************** Bit definition for DBGMCU_CR register *******************/
12450#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
12451#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
12452#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
12453#define DBGMCU_CR_DBG_STOP_Pos (1U)
12454#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
12455#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
12456#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
12457#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
12458#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
12459#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
12460#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
12461#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
12463#define DBGMCU_CR_TRACE_MODE_Pos (6U)
12464#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
12465#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
12466#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
12467#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
12469#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
12470#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos)
12471#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk
12472#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
12473#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos)
12474#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk
12475#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
12476#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos)
12477#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk
12478#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
12479#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos)
12480#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk
12481#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
12482#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos)
12483#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk
12484#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
12485#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos)
12486#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk
12487#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
12488#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos)
12489#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk
12490#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
12491#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos)
12492#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk
12493#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
12494#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos)
12495#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk
12496#define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
12497#define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM5_STOP_Pos)
12498#define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk
12499#define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
12500#define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM6_STOP_Pos)
12501#define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk
12502#define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
12503#define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM7_STOP_Pos)
12504#define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk
12505#define DBGMCU_CR_DBG_CAN2_STOP_Pos (21U)
12506#define DBGMCU_CR_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN2_STOP_Pos)
12507#define DBGMCU_CR_DBG_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP_Msk
12508#define DBGMCU_CR_DBG_TIM9_STOP_Pos (28U)
12509#define DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM9_STOP_Pos)
12510#define DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk
12511#define DBGMCU_CR_DBG_TIM10_STOP_Pos (29U)
12512#define DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM10_STOP_Pos)
12513#define DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk
12514#define DBGMCU_CR_DBG_TIM11_STOP_Pos (30U)
12515#define DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM11_STOP_Pos)
12516#define DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk
12518/******************************************************************************/
12519/* */
12520/* FLASH and Option Bytes Registers */
12521/* */
12522/******************************************************************************/
12523/******************* Bit definition for FLASH_ACR register ******************/
12524#define FLASH_ACR_LATENCY_Pos (0U)
12525#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
12526#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
12527#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos)
12528#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos)
12529#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos)
12531#define FLASH_ACR_HLFCYA_Pos (3U)
12532#define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos)
12533#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk
12534#define FLASH_ACR_PRFTBE_Pos (4U)
12535#define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos)
12536#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk
12537#define FLASH_ACR_PRFTBS_Pos (5U)
12538#define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos)
12539#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk
12541/****************** Bit definition for FLASH_KEYR register ******************/
12542#define FLASH_KEYR_FKEYR_Pos (0U)
12543#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos)
12544#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk
12546#define RDP_KEY_Pos (0U)
12547#define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos)
12548#define RDP_KEY RDP_KEY_Msk
12549#define FLASH_KEY1_Pos (0U)
12550#define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos)
12551#define FLASH_KEY1 FLASH_KEY1_Msk
12552#define FLASH_KEY2_Pos (0U)
12553#define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos)
12554#define FLASH_KEY2 FLASH_KEY2_Msk
12556/***************** Bit definition for FLASH_OPTKEYR register ****************/
12557#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
12558#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)
12559#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk
12561#define FLASH_OPTKEY1 FLASH_KEY1
12562#define FLASH_OPTKEY2 FLASH_KEY2
12564/****************** Bit definition for FLASH_SR register ********************/
12565#define FLASH_SR_BSY_Pos (0U)
12566#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
12567#define FLASH_SR_BSY FLASH_SR_BSY_Msk
12568#define FLASH_SR_PGERR_Pos (2U)
12569#define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos)
12570#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk
12571#define FLASH_SR_WRPRTERR_Pos (4U)
12572#define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos)
12573#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk
12574#define FLASH_SR_EOP_Pos (5U)
12575#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
12576#define FLASH_SR_EOP FLASH_SR_EOP_Msk
12578/******************* Bit definition for FLASH_CR register *******************/
12579#define FLASH_CR_PG_Pos (0U)
12580#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
12581#define FLASH_CR_PG FLASH_CR_PG_Msk
12582#define FLASH_CR_PER_Pos (1U)
12583#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)
12584#define FLASH_CR_PER FLASH_CR_PER_Msk
12585#define FLASH_CR_MER_Pos (2U)
12586#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
12587#define FLASH_CR_MER FLASH_CR_MER_Msk
12588#define FLASH_CR_OPTPG_Pos (4U)
12589#define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos)
12590#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk
12591#define FLASH_CR_OPTER_Pos (5U)
12592#define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos)
12593#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk
12594#define FLASH_CR_STRT_Pos (6U)
12595#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
12596#define FLASH_CR_STRT FLASH_CR_STRT_Msk
12597#define FLASH_CR_LOCK_Pos (7U)
12598#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
12599#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
12600#define FLASH_CR_OPTWRE_Pos (9U)
12601#define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos)
12602#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk
12603#define FLASH_CR_ERRIE_Pos (10U)
12604#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
12605#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
12606#define FLASH_CR_EOPIE_Pos (12U)
12607#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
12608#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
12610/******************* Bit definition for FLASH_AR register *******************/
12611#define FLASH_AR_FAR_Pos (0U)
12612#define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)
12613#define FLASH_AR_FAR FLASH_AR_FAR_Msk
12615/****************** Bit definition for FLASH_OBR register *******************/
12616#define FLASH_OBR_OPTERR_Pos (0U)
12617#define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos)
12618#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk
12619#define FLASH_OBR_RDPRT_Pos (1U)
12620#define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos)
12621#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk
12623#define FLASH_OBR_IWDG_SW_Pos (2U)
12624#define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos)
12625#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk
12626#define FLASH_OBR_nRST_STOP_Pos (3U)
12627#define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos)
12628#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk
12629#define FLASH_OBR_nRST_STDBY_Pos (4U)
12630#define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos)
12631#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk
12632#define FLASH_OBR_USER_Pos (2U)
12633#define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos)
12634#define FLASH_OBR_USER FLASH_OBR_USER_Msk
12635#define FLASH_OBR_DATA0_Pos (10U)
12636#define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos)
12637#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk
12638#define FLASH_OBR_DATA1_Pos (18U)
12639#define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos)
12640#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk
12642/****************** Bit definition for FLASH_WRPR register ******************/
12643#define FLASH_WRPR_WRP_Pos (0U)
12644#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos)
12645#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk
12647/*----------------------------------------------------------------------------*/
12648
12649/****************** Bit definition for FLASH_RDP register *******************/
12650#define FLASH_RDP_RDP_Pos (0U)
12651#define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos)
12652#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk
12653#define FLASH_RDP_nRDP_Pos (8U)
12654#define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos)
12655#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk
12657/****************** Bit definition for FLASH_USER register ******************/
12658#define FLASH_USER_USER_Pos (16U)
12659#define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos)
12660#define FLASH_USER_USER FLASH_USER_USER_Msk
12661#define FLASH_USER_nUSER_Pos (24U)
12662#define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos)
12663#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk
12665/****************** Bit definition for FLASH_Data0 register *****************/
12666#define FLASH_DATA0_DATA0_Pos (0U)
12667#define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos)
12668#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk
12669#define FLASH_DATA0_nDATA0_Pos (8U)
12670#define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos)
12671#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk
12673/****************** Bit definition for FLASH_Data1 register *****************/
12674#define FLASH_DATA1_DATA1_Pos (16U)
12675#define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos)
12676#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk
12677#define FLASH_DATA1_nDATA1_Pos (24U)
12678#define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos)
12679#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk
12681/****************** Bit definition for FLASH_WRP0 register ******************/
12682#define FLASH_WRP0_WRP0_Pos (0U)
12683#define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos)
12684#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk
12685#define FLASH_WRP0_nWRP0_Pos (8U)
12686#define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos)
12687#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk
12689/****************** Bit definition for FLASH_WRP1 register ******************/
12690#define FLASH_WRP1_WRP1_Pos (16U)
12691#define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos)
12692#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk
12693#define FLASH_WRP1_nWRP1_Pos (24U)
12694#define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos)
12695#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk
12697/****************** Bit definition for FLASH_WRP2 register ******************/
12698#define FLASH_WRP2_WRP2_Pos (0U)
12699#define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos)
12700#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk
12701#define FLASH_WRP2_nWRP2_Pos (8U)
12702#define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos)
12703#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk
12705/****************** Bit definition for FLASH_WRP3 register ******************/
12706#define FLASH_WRP3_WRP3_Pos (16U)
12707#define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos)
12708#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk
12709#define FLASH_WRP3_nWRP3_Pos (24U)
12710#define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos)
12711#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk
12713/******************************************************************************/
12714/* Ethernet MAC Registers bits definitions */
12715/******************************************************************************/
12716/* Bit definition for Ethernet MAC Control Register register */
12717#define ETH_MACCR_WD_Pos (23U)
12718#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
12719#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
12720#define ETH_MACCR_JD_Pos (22U)
12721#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
12722#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
12723#define ETH_MACCR_IFG_Pos (17U)
12724#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
12725#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
12726#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
12727#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
12728#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
12729#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
12730#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
12731#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
12732#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
12733#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
12734#define ETH_MACCR_CSD_Pos (16U)
12735#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
12736#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
12737#define ETH_MACCR_FES_Pos (14U)
12738#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
12739#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
12740#define ETH_MACCR_ROD_Pos (13U)
12741#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
12742#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
12743#define ETH_MACCR_LM_Pos (12U)
12744#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
12745#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
12746#define ETH_MACCR_DM_Pos (11U)
12747#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
12748#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
12749#define ETH_MACCR_IPCO_Pos (10U)
12750#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
12751#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
12752#define ETH_MACCR_RD_Pos (9U)
12753#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
12754#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
12755#define ETH_MACCR_APCS_Pos (7U)
12756#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
12757#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
12758#define ETH_MACCR_BL_Pos (5U)
12759#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
12760#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
12761 a transmission attempt during retries after a collision: 0 =< r <2^k */
12762#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
12763#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
12764#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
12765#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
12766#define ETH_MACCR_DC_Pos (4U)
12767#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
12768#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
12769#define ETH_MACCR_TE_Pos (3U)
12770#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
12771#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
12772#define ETH_MACCR_RE_Pos (2U)
12773#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
12774#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
12775
12776/* Bit definition for Ethernet MAC Frame Filter Register */
12777#define ETH_MACFFR_RA_Pos (31U)
12778#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
12779#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
12780#define ETH_MACFFR_HPF_Pos (10U)
12781#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
12782#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
12783#define ETH_MACFFR_SAF_Pos (9U)
12784#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
12785#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
12786#define ETH_MACFFR_SAIF_Pos (8U)
12787#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
12788#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
12789#define ETH_MACFFR_PCF_Pos (6U)
12790#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
12791#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
12792#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
12793#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
12794#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
12795#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
12796#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
12797#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
12798#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
12799#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
12800#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
12801#define ETH_MACFFR_BFD_Pos (5U)
12802#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
12803#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
12804#define ETH_MACFFR_PAM_Pos (4U)
12805#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
12806#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
12807#define ETH_MACFFR_DAIF_Pos (3U)
12808#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
12809#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
12810#define ETH_MACFFR_HM_Pos (2U)
12811#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
12812#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
12813#define ETH_MACFFR_HU_Pos (1U)
12814#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
12815#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
12816#define ETH_MACFFR_PM_Pos (0U)
12817#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
12818#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
12819
12820/* Bit definition for Ethernet MAC Hash Table High Register */
12821#define ETH_MACHTHR_HTH_Pos (0U)
12822#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
12823#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
12824
12825/* Bit definition for Ethernet MAC Hash Table Low Register */
12826#define ETH_MACHTLR_HTL_Pos (0U)
12827#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
12828#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
12829
12830/* Bit definition for Ethernet MAC MII Address Register */
12831#define ETH_MACMIIAR_PA_Pos (11U)
12832#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
12833#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
12834#define ETH_MACMIIAR_MR_Pos (6U)
12835#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
12836#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
12837#define ETH_MACMIIAR_CR_Pos (2U)
12838#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
12839#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
12840#define ETH_MACMIIAR_CR_DIV42 0x00000000U /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
12841#define ETH_MACMIIAR_CR_DIV16_Pos (3U)
12842#define ETH_MACMIIAR_CR_DIV16_Msk (0x1UL << ETH_MACMIIAR_CR_DIV16_Pos)
12843#define ETH_MACMIIAR_CR_DIV16 ETH_MACMIIAR_CR_DIV16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
12844#define ETH_MACMIIAR_CR_DIV26_Pos (2U)
12845#define ETH_MACMIIAR_CR_DIV26_Msk (0x3UL << ETH_MACMIIAR_CR_DIV26_Pos)
12846#define ETH_MACMIIAR_CR_DIV26 ETH_MACMIIAR_CR_DIV26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
12847#define ETH_MACMIIAR_MW_Pos (1U)
12848#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
12849#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
12850#define ETH_MACMIIAR_MB_Pos (0U)
12851#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
12852#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
12853
12854/* Bit definition for Ethernet MAC MII Data Register */
12855#define ETH_MACMIIDR_MD_Pos (0U)
12856#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
12857#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
12858
12859/* Bit definition for Ethernet MAC Flow Control Register */
12860#define ETH_MACFCR_PT_Pos (16U)
12861#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
12862#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
12863#define ETH_MACFCR_ZQPD_Pos (7U)
12864#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
12865#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
12866#define ETH_MACFCR_PLT_Pos (4U)
12867#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
12868#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
12869#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
12870#define ETH_MACFCR_PLT_Minus28_Pos (4U)
12871#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
12872#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
12873#define ETH_MACFCR_PLT_Minus144_Pos (5U)
12874#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
12875#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
12876#define ETH_MACFCR_PLT_Minus256_Pos (4U)
12877#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
12878#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
12879#define ETH_MACFCR_UPFD_Pos (3U)
12880#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
12881#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
12882#define ETH_MACFCR_RFCE_Pos (2U)
12883#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
12884#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
12885#define ETH_MACFCR_TFCE_Pos (1U)
12886#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
12887#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
12888#define ETH_MACFCR_FCBBPA_Pos (0U)
12889#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
12890#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
12891
12892/* Bit definition for Ethernet MAC VLAN Tag Register */
12893#define ETH_MACVLANTR_VLANTC_Pos (16U)
12894#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
12895#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
12896#define ETH_MACVLANTR_VLANTI_Pos (0U)
12897#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
12898#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
12899
12900/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
12901#define ETH_MACRWUFFR_D_Pos (0U)
12902#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
12903#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
12904/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
12905 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
12906/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
12907 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
12908 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
12909 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
12910 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
12911 RSVD - Filter1 Command - RSVD - Filter0 Command
12912 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
12913 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
12914 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
12915
12916/* Bit definition for Ethernet MAC PMT Control and Status Register */
12917#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
12918#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
12919#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
12920#define ETH_MACPMTCSR_GU_Pos (9U)
12921#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
12922#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
12923#define ETH_MACPMTCSR_WFR_Pos (6U)
12924#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
12925#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
12926#define ETH_MACPMTCSR_MPR_Pos (5U)
12927#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
12928#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
12929#define ETH_MACPMTCSR_WFE_Pos (2U)
12930#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
12931#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
12932#define ETH_MACPMTCSR_MPE_Pos (1U)
12933#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
12934#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
12935#define ETH_MACPMTCSR_PD_Pos (0U)
12936#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
12937#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
12938
12939/* Bit definition for Ethernet MAC Status Register */
12940#define ETH_MACSR_TSTS_Pos (9U)
12941#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
12942#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
12943#define ETH_MACSR_MMCTS_Pos (6U)
12944#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
12945#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
12946#define ETH_MACSR_MMMCRS_Pos (5U)
12947#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
12948#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
12949#define ETH_MACSR_MMCS_Pos (4U)
12950#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
12951#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
12952#define ETH_MACSR_PMTS_Pos (3U)
12953#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
12954#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
12955
12956/* Bit definition for Ethernet MAC Interrupt Mask Register */
12957#define ETH_MACIMR_TSTIM_Pos (9U)
12958#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
12959#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
12960#define ETH_MACIMR_PMTIM_Pos (3U)
12961#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
12962#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
12963
12964/* Bit definition for Ethernet MAC Address0 High Register */
12965#define ETH_MACA0HR_MACA0H_Pos (0U)
12966#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
12967#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
12968
12969/* Bit definition for Ethernet MAC Address0 Low Register */
12970#define ETH_MACA0LR_MACA0L_Pos (0U)
12971#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
12972#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
12973
12974/* Bit definition for Ethernet MAC Address1 High Register */
12975#define ETH_MACA1HR_AE_Pos (31U)
12976#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
12977#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
12978#define ETH_MACA1HR_SA_Pos (30U)
12979#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
12980#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
12981#define ETH_MACA1HR_MBC_Pos (24U)
12982#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
12983#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
12984#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
12985#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
12986#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
12987#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
12988#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
12989#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
12990#define ETH_MACA1HR_MACA1H_Pos (0U)
12991#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
12992#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
12993
12994/* Bit definition for Ethernet MAC Address1 Low Register */
12995#define ETH_MACA1LR_MACA1L_Pos (0U)
12996#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
12997#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
12998
12999/* Bit definition for Ethernet MAC Address2 High Register */
13000#define ETH_MACA2HR_AE_Pos (31U)
13001#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
13002#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
13003#define ETH_MACA2HR_SA_Pos (30U)
13004#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
13005#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
13006#define ETH_MACA2HR_MBC_Pos (24U)
13007#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
13008#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
13009#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13010#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13011#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13012#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13013#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13014#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
13015#define ETH_MACA2HR_MACA2H_Pos (0U)
13016#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
13017#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
13018
13019/* Bit definition for Ethernet MAC Address2 Low Register */
13020#define ETH_MACA2LR_MACA2L_Pos (0U)
13021#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
13022#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
13023
13024/* Bit definition for Ethernet MAC Address3 High Register */
13025#define ETH_MACA3HR_AE_Pos (31U)
13026#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
13027#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
13028#define ETH_MACA3HR_SA_Pos (30U)
13029#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
13030#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
13031#define ETH_MACA3HR_MBC_Pos (24U)
13032#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
13033#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
13034#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13035#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13036#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13037#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13038#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13039#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
13040#define ETH_MACA3HR_MACA3H_Pos (0U)
13041#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
13042#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
13043
13044/* Bit definition for Ethernet MAC Address3 Low Register */
13045#define ETH_MACA3LR_MACA3L_Pos (0U)
13046#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
13047#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
13048
13049/******************************************************************************/
13050/* Ethernet MMC Registers bits definition */
13051/******************************************************************************/
13052
13053/* Bit definition for Ethernet MMC Contol Register */
13054#define ETH_MMCCR_MCF_Pos (3U)
13055#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
13056#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
13057#define ETH_MMCCR_ROR_Pos (2U)
13058#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
13059#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
13060#define ETH_MMCCR_CSR_Pos (1U)
13061#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
13062#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
13063#define ETH_MMCCR_CR_Pos (0U)
13064#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
13065#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
13066
13067/* Bit definition for Ethernet MMC Receive Interrupt Register */
13068#define ETH_MMCRIR_RGUFS_Pos (17U)
13069#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
13070#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
13071#define ETH_MMCRIR_RFAES_Pos (6U)
13072#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
13073#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
13074#define ETH_MMCRIR_RFCES_Pos (5U)
13075#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
13076#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
13077
13078/* Bit definition for Ethernet MMC Transmit Interrupt Register */
13079#define ETH_MMCTIR_TGFS_Pos (21U)
13080#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
13081#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
13082#define ETH_MMCTIR_TGFMSCS_Pos (15U)
13083#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
13084#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
13085#define ETH_MMCTIR_TGFSCS_Pos (14U)
13086#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
13087#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
13088
13089/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
13090#define ETH_MMCRIMR_RGUFM_Pos (17U)
13091#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
13092#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
13093#define ETH_MMCRIMR_RFAEM_Pos (6U)
13094#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
13095#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
13096#define ETH_MMCRIMR_RFCEM_Pos (5U)
13097#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
13098#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
13099
13100/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
13101#define ETH_MMCTIMR_TGFM_Pos (21U)
13102#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
13103#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
13104#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
13105#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
13106#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
13107#define ETH_MMCTIMR_TGFSCM_Pos (14U)
13108#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
13109#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
13110
13111/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
13112#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
13113#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
13114#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
13115
13116/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
13117#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
13118#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
13119#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
13120
13121/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
13122#define ETH_MMCTGFCR_TGFC_Pos (0U)
13123#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
13124#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
13125
13126/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
13127#define ETH_MMCRFCECR_RFCEC_Pos (0U)
13128#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
13129#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
13130
13131/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
13132#define ETH_MMCRFAECR_RFAEC_Pos (0U)
13133#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
13134#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
13135
13136/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
13137#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
13138#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
13139#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
13140
13141/******************************************************************************/
13142/* Ethernet PTP Registers bits definition */
13143/******************************************************************************/
13144
13145/* Bit definition for Ethernet PTP Time Stamp Contol Register */
13146#define ETH_PTPTSCR_TSARU_Pos (5U)
13147#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
13148#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
13149#define ETH_PTPTSCR_TSITE_Pos (4U)
13150#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
13151#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
13152#define ETH_PTPTSCR_TSSTU_Pos (3U)
13153#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
13154#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
13155#define ETH_PTPTSCR_TSSTI_Pos (2U)
13156#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
13157#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
13158#define ETH_PTPTSCR_TSFCU_Pos (1U)
13159#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
13160#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
13161#define ETH_PTPTSCR_TSE_Pos (0U)
13162#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
13163#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
13164
13165/* Bit definition for Ethernet PTP Sub-Second Increment Register */
13166#define ETH_PTPSSIR_STSSI_Pos (0U)
13167#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
13168#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
13169
13170/* Bit definition for Ethernet PTP Time Stamp High Register */
13171#define ETH_PTPTSHR_STS_Pos (0U)
13172#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
13173#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
13174
13175/* Bit definition for Ethernet PTP Time Stamp Low Register */
13176#define ETH_PTPTSLR_STPNS_Pos (31U)
13177#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
13178#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
13179#define ETH_PTPTSLR_STSS_Pos (0U)
13180#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
13181#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
13182
13183/* Bit definition for Ethernet PTP Time Stamp High Update Register */
13184#define ETH_PTPTSHUR_TSUS_Pos (0U)
13185#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
13186#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
13187
13188/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
13189#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
13190#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
13191#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
13192#define ETH_PTPTSLUR_TSUSS_Pos (0U)
13193#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
13194#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
13195
13196/* Bit definition for Ethernet PTP Time Stamp Addend Register */
13197#define ETH_PTPTSAR_TSA_Pos (0U)
13198#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
13199#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
13200
13201/* Bit definition for Ethernet PTP Target Time High Register */
13202#define ETH_PTPTTHR_TTSH_Pos (0U)
13203#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
13204#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
13205
13206/* Bit definition for Ethernet PTP Target Time Low Register */
13207#define ETH_PTPTTLR_TTSL_Pos (0U)
13208#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
13209#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
13210
13211/******************************************************************************/
13212/* Ethernet DMA Registers bits definition */
13213/******************************************************************************/
13214
13215/* Bit definition for Ethernet DMA Bus Mode Register */
13216#define ETH_DMABMR_AAB_Pos (25U)
13217#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
13218#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
13219#define ETH_DMABMR_FPM_Pos (24U)
13220#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
13221#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
13222#define ETH_DMABMR_USP_Pos (23U)
13223#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
13224#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
13225#define ETH_DMABMR_RDP_Pos (17U)
13226#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
13227#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
13228#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
13229#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
13230#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
13231#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
13232#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
13233#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
13234#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
13235#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
13236#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
13237#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
13238#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
13239#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
13240#define ETH_DMABMR_FB_Pos (16U)
13241#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
13242#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
13243#define ETH_DMABMR_RTPR_Pos (14U)
13244#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
13245#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
13246#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
13247#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
13248#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
13249#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
13250#define ETH_DMABMR_PBL_Pos (8U)
13251#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
13252#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
13253#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
13254#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
13255#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
13256#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
13257#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
13258#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
13259#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
13260#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
13261#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
13262#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
13263#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
13264#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
13265#define ETH_DMABMR_DSL_Pos (2U)
13266#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
13267#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
13268#define ETH_DMABMR_DA_Pos (1U)
13269#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
13270#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
13271#define ETH_DMABMR_SR_Pos (0U)
13272#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
13273#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
13274
13275/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
13276#define ETH_DMATPDR_TPD_Pos (0U)
13277#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
13278#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
13279
13280/* Bit definition for Ethernet DMA Receive Poll Demand Register */
13281#define ETH_DMARPDR_RPD_Pos (0U)
13282#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
13283#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
13284
13285/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
13286#define ETH_DMARDLAR_SRL_Pos (0U)
13287#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
13288#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
13289
13290/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
13291#define ETH_DMATDLAR_STL_Pos (0U)
13292#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
13293#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
13294
13295/* Bit definition for Ethernet DMA Status Register */
13296#define ETH_DMASR_TSTS_Pos (29U)
13297#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
13298#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
13299#define ETH_DMASR_PMTS_Pos (28U)
13300#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
13301#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
13302#define ETH_DMASR_MMCS_Pos (27U)
13303#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
13304#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
13305#define ETH_DMASR_EBS_Pos (23U)
13306#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
13307#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
13308 /* combination with EBS[2:0] for GetFlagStatus function */
13309#define ETH_DMASR_EBS_DescAccess_Pos (25U)
13310#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
13311#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
13312#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
13313#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
13314#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
13315#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
13316#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
13317#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
13318#define ETH_DMASR_TPS_Pos (20U)
13319#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
13320#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
13321#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
13322#define ETH_DMASR_TPS_Fetching_Pos (20U)
13323#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
13324#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
13325#define ETH_DMASR_TPS_Waiting_Pos (21U)
13326#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
13327#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
13328#define ETH_DMASR_TPS_Reading_Pos (20U)
13329#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
13330#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
13331#define ETH_DMASR_TPS_Suspended_Pos (21U)
13332#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
13333#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
13334#define ETH_DMASR_TPS_Closing_Pos (20U)
13335#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
13336#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
13337#define ETH_DMASR_RPS_Pos (17U)
13338#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
13339#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
13340#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
13341#define ETH_DMASR_RPS_Fetching_Pos (17U)
13342#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
13343#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
13344#define ETH_DMASR_RPS_Waiting_Pos (17U)
13345#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
13346#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
13347#define ETH_DMASR_RPS_Suspended_Pos (19U)
13348#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
13349#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
13350#define ETH_DMASR_RPS_Closing_Pos (17U)
13351#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
13352#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
13353#define ETH_DMASR_RPS_Queuing_Pos (17U)
13354#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
13355#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
13356#define ETH_DMASR_NIS_Pos (16U)
13357#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
13358#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
13359#define ETH_DMASR_AIS_Pos (15U)
13360#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
13361#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
13362#define ETH_DMASR_ERS_Pos (14U)
13363#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
13364#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
13365#define ETH_DMASR_FBES_Pos (13U)
13366#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
13367#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
13368#define ETH_DMASR_ETS_Pos (10U)
13369#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
13370#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
13371#define ETH_DMASR_RWTS_Pos (9U)
13372#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
13373#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
13374#define ETH_DMASR_RPSS_Pos (8U)
13375#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
13376#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
13377#define ETH_DMASR_RBUS_Pos (7U)
13378#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
13379#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
13380#define ETH_DMASR_RS_Pos (6U)
13381#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
13382#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
13383#define ETH_DMASR_TUS_Pos (5U)
13384#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
13385#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
13386#define ETH_DMASR_ROS_Pos (4U)
13387#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
13388#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
13389#define ETH_DMASR_TJTS_Pos (3U)
13390#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
13391#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
13392#define ETH_DMASR_TBUS_Pos (2U)
13393#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
13394#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
13395#define ETH_DMASR_TPSS_Pos (1U)
13396#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
13397#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
13398#define ETH_DMASR_TS_Pos (0U)
13399#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
13400#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
13401
13402/* Bit definition for Ethernet DMA Operation Mode Register */
13403#define ETH_DMAOMR_DTCEFD_Pos (26U)
13404#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
13405#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
13406#define ETH_DMAOMR_RSF_Pos (25U)
13407#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
13408#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
13409#define ETH_DMAOMR_DFRF_Pos (24U)
13410#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
13411#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
13412#define ETH_DMAOMR_TSF_Pos (21U)
13413#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
13414#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
13415#define ETH_DMAOMR_FTF_Pos (20U)
13416#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
13417#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
13418#define ETH_DMAOMR_TTC_Pos (14U)
13419#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
13420#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
13421#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
13422#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
13423#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
13424#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
13425#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
13426#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
13427#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
13428#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
13429#define ETH_DMAOMR_ST_Pos (13U)
13430#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
13431#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
13432#define ETH_DMAOMR_FEF_Pos (7U)
13433#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
13434#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
13435#define ETH_DMAOMR_FUGF_Pos (6U)
13436#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
13437#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
13438#define ETH_DMAOMR_RTC_Pos (3U)
13439#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
13440#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
13441#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
13442#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
13443#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
13444#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
13445#define ETH_DMAOMR_OSF_Pos (2U)
13446#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
13447#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
13448#define ETH_DMAOMR_SR_Pos (1U)
13449#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
13450#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
13451
13452/* Bit definition for Ethernet DMA Interrupt Enable Register */
13453#define ETH_DMAIER_NISE_Pos (16U)
13454#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
13455#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
13456#define ETH_DMAIER_AISE_Pos (15U)
13457#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
13458#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
13459#define ETH_DMAIER_ERIE_Pos (14U)
13460#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
13461#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
13462#define ETH_DMAIER_FBEIE_Pos (13U)
13463#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
13464#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
13465#define ETH_DMAIER_ETIE_Pos (10U)
13466#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
13467#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
13468#define ETH_DMAIER_RWTIE_Pos (9U)
13469#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
13470#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
13471#define ETH_DMAIER_RPSIE_Pos (8U)
13472#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
13473#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
13474#define ETH_DMAIER_RBUIE_Pos (7U)
13475#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
13476#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
13477#define ETH_DMAIER_RIE_Pos (6U)
13478#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
13479#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
13480#define ETH_DMAIER_TUIE_Pos (5U)
13481#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
13482#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
13483#define ETH_DMAIER_ROIE_Pos (4U)
13484#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
13485#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
13486#define ETH_DMAIER_TJTIE_Pos (3U)
13487#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
13488#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
13489#define ETH_DMAIER_TBUIE_Pos (2U)
13490#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
13491#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
13492#define ETH_DMAIER_TPSIE_Pos (1U)
13493#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
13494#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
13495#define ETH_DMAIER_TIE_Pos (0U)
13496#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
13497#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
13498
13499/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
13500#define ETH_DMAMFBOCR_OFOC_Pos (28U)
13501#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
13502#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
13503#define ETH_DMAMFBOCR_MFA_Pos (17U)
13504#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
13505#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
13506#define ETH_DMAMFBOCR_OMFC_Pos (16U)
13507#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
13508#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
13509#define ETH_DMAMFBOCR_MFC_Pos (0U)
13510#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
13511#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
13512
13513/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
13514#define ETH_DMACHTDR_HTDAP_Pos (0U)
13515#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
13516#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
13517
13518/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
13519#define ETH_DMACHRDR_HRDAP_Pos (0U)
13520#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
13521#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
13522
13523/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
13524#define ETH_DMACHTBAR_HTBAP_Pos (0U)
13525#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
13526#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
13527
13528/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
13529#define ETH_DMACHRBAR_HRBAP_Pos (0U)
13530#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
13531#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
13532
13533/******************************************************************************/
13534/* */
13535/* USB_OTG */
13536/* */
13537/******************************************************************************/
13538/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
13539#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
13540#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
13541#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
13542#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
13543#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
13544#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
13545#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
13546#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
13547#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
13548#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
13549#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
13550#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
13551#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
13552#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
13553#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
13554#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
13555#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
13556#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
13557#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
13558#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
13559#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
13560#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
13561#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
13562#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
13563#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
13564#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
13565#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
13566#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
13567#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
13568#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk
13570/******************** Bit definition for USB_OTG_HCFG register ********************/
13571
13572#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
13573#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
13574#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
13575#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
13576#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
13577#define USB_OTG_HCFG_FSLSS_Pos (2U)
13578#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
13579#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
13581/******************** Bit definition for USB_OTG_DCFG register ********************/
13582
13583#define USB_OTG_DCFG_DSPD_Pos (0U)
13584#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
13585#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
13586#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
13587#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
13588#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
13589#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
13590#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
13592#define USB_OTG_DCFG_DAD_Pos (4U)
13593#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
13594#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
13595#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
13596#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
13597#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
13598#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
13599#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
13600#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
13601#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
13603#define USB_OTG_DCFG_PFIVL_Pos (11U)
13604#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
13605#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
13606#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
13607#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
13609#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
13610#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13611#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
13612#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13613#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13615/******************** Bit definition for USB_OTG_PCGCR register ********************/
13616#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
13617#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
13618#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
13619#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
13620#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
13621#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
13622#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
13623#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
13624#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
13626/******************** Bit definition for USB_OTG_GOTGINT register ********************/
13627#define USB_OTG_GOTGINT_SEDET_Pos (2U)
13628#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
13629#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
13630#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
13631#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
13632#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
13633#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
13634#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
13635#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
13636#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
13637#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
13638#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
13639#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
13640#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
13641#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
13642#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
13643#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
13644#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
13646/******************** Bit definition for USB_OTG_DCTL register ********************/
13647#define USB_OTG_DCTL_RWUSIG_Pos (0U)
13648#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
13649#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
13650#define USB_OTG_DCTL_SDIS_Pos (1U)
13651#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
13652#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
13653#define USB_OTG_DCTL_GINSTS_Pos (2U)
13654#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
13655#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
13656#define USB_OTG_DCTL_GONSTS_Pos (3U)
13657#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
13658#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
13660#define USB_OTG_DCTL_TCTL_Pos (4U)
13661#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
13662#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
13663#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
13664#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
13665#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
13666#define USB_OTG_DCTL_SGINAK_Pos (7U)
13667#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
13668#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
13669#define USB_OTG_DCTL_CGINAK_Pos (8U)
13670#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
13671#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
13672#define USB_OTG_DCTL_SGONAK_Pos (9U)
13673#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
13674#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
13675#define USB_OTG_DCTL_CGONAK_Pos (10U)
13676#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
13677#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
13678#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
13679#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
13680#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
13682/******************** Bit definition for USB_OTG_HFIR register ********************/
13683#define USB_OTG_HFIR_FRIVL_Pos (0U)
13684#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
13685#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
13687/******************** Bit definition for USB_OTG_HFNUM register ********************/
13688#define USB_OTG_HFNUM_FRNUM_Pos (0U)
13689#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
13690#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
13691#define USB_OTG_HFNUM_FTREM_Pos (16U)
13692#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
13693#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
13695/******************** Bit definition for USB_OTG_DSTS register ********************/
13696#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
13697#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
13698#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
13700#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
13701#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
13702#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
13703#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
13704#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
13705#define USB_OTG_DSTS_EERR_Pos (3U)
13706#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
13707#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
13708#define USB_OTG_DSTS_FNSOF_Pos (8U)
13709#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
13710#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
13712/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
13713#define USB_OTG_GAHBCFG_GINT_Pos (0U)
13714#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
13715#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
13716#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
13717#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13718#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
13719#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13720#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13721#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13722#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13723#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13724#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
13725#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
13726#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
13727#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
13728#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
13729#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
13730#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
13731#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
13732#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
13734/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
13735
13736#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
13737#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13738#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
13739#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13740#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13741#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13742#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
13743#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
13744#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
13745#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
13746#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
13747#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
13748#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
13749#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
13750#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
13751#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
13752#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
13753#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
13754#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
13755#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
13756#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
13757#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
13758#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
13759#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
13760#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
13761#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
13762#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
13763#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
13764#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
13765#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
13766#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
13767#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
13768#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
13769#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
13770#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
13771#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
13772#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
13773#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
13774#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
13775#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
13776#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
13777#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
13778#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
13779#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
13780#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
13781#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
13782#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
13783#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
13784#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
13785#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
13786#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
13787#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
13788#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
13789#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
13790#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
13791#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
13792#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
13793#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
13794#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
13795#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
13796#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
13798/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
13799#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
13800#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
13801#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
13802#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
13803#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
13804#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
13805#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
13806#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
13807#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
13808#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
13809#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
13810#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
13811#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
13812#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
13813#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
13816#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
13817#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13818#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
13819#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13820#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13821#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13822#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13823#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13824#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
13825#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
13826#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
13827#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
13828#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
13829#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
13831/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
13832#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
13833#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
13834#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
13835#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
13836#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
13837#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
13838#define USB_OTG_DIEPMSK_TOM_Pos (3U)
13839#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
13840#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
13841#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
13842#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
13843#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
13844#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
13845#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
13846#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
13847#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
13848#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
13849#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
13850#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
13851#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
13852#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
13853#define USB_OTG_DIEPMSK_BIM_Pos (9U)
13854#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
13855#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
13857/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
13858#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
13859#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
13860#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
13861#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
13862#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13863#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
13864#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13865#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13866#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13867#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13868#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13869#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13870#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13871#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13873#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
13874#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13875#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
13876#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13877#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13878#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13879#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13880#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13881#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13882#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13883#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13885/******************** Bit definition for USB_OTG_HAINT register ********************/
13886#define USB_OTG_HAINT_HAINT_Pos (0U)
13887#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
13888#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
13890/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
13891#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
13892#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
13893#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
13894#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
13895#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
13896#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
13897#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
13898#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
13899#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
13900#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
13901#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
13902#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
13903#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
13904#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
13905#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
13906#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
13907#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
13908#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
13909#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
13910#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
13911#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
13912#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
13913#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
13914#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
13915#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
13916#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
13917#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
13918#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
13919#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
13920#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
13921#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
13922#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
13923#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
13924#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
13925#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
13926#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
13927/******************** Bit definition for USB_OTG_GINTSTS register ********************/
13928#define USB_OTG_GINTSTS_CMOD_Pos (0U)
13929#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
13930#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
13931#define USB_OTG_GINTSTS_MMIS_Pos (1U)
13932#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
13933#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
13934#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
13935#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
13936#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
13937#define USB_OTG_GINTSTS_SOF_Pos (3U)
13938#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
13939#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
13940#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
13941#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
13942#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
13943#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
13944#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
13945#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
13946#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
13947#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
13948#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
13949#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
13950#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
13951#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
13952#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
13953#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
13954#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
13955#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
13956#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
13957#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
13958#define USB_OTG_GINTSTS_USBRST_Pos (12U)
13959#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
13960#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
13961#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
13962#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
13963#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
13964#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
13965#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
13966#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
13967#define USB_OTG_GINTSTS_EOPF_Pos (15U)
13968#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
13969#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
13970#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
13971#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
13972#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
13973#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
13974#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
13975#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
13976#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
13977#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
13978#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
13979#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
13980#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
13981#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
13982#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
13983#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
13984#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
13985#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
13986#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
13987#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
13988#define USB_OTG_GINTSTS_HCINT_Pos (25U)
13989#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
13990#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
13991#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
13992#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
13993#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
13994#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
13995#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
13996#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
13997#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
13998#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
13999#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
14000#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
14001#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
14002#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
14003#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
14004#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
14005#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
14007/******************** Bit definition for USB_OTG_GINTMSK register ********************/
14008#define USB_OTG_GINTMSK_MMISM_Pos (1U)
14009#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
14010#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
14011#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
14012#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
14013#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
14014#define USB_OTG_GINTMSK_SOFM_Pos (3U)
14015#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
14016#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
14017#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
14018#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
14019#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
14020#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
14021#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
14022#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
14023#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
14024#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
14025#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
14026#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
14027#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
14028#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
14029#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
14030#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
14031#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
14032#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
14033#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
14034#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
14035#define USB_OTG_GINTMSK_USBRST_Pos (12U)
14036#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
14037#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
14038#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
14039#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
14040#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
14041#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
14042#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
14043#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
14044#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
14045#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
14046#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
14047#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
14048#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
14049#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
14050#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
14051#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
14052#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
14053#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
14054#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
14055#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
14056#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
14057#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
14058#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
14059#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
14060#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
14061#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
14062#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
14063#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
14064#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
14065#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
14066#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
14067#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
14068#define USB_OTG_GINTMSK_HCIM_Pos (25U)
14069#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
14070#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
14071#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
14072#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
14073#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
14074#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
14075#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
14076#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
14077#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
14078#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
14079#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
14080#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
14081#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
14082#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
14083#define USB_OTG_GINTMSK_WUIM_Pos (31U)
14084#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
14085#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
14087/******************** Bit definition for USB_OTG_DAINT register ********************/
14088#define USB_OTG_DAINT_IEPINT_Pos (0U)
14089#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
14090#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
14091#define USB_OTG_DAINT_OEPINT_Pos (16U)
14092#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
14093#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
14095/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
14096#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
14097#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
14098#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
14100/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
14101#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
14102#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
14103#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
14104#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
14105#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
14106#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
14107#define USB_OTG_GRXSTSP_DPID_Pos (15U)
14108#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
14109#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
14110#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
14111#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
14112#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
14114/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
14115#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
14116#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
14117#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
14118#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
14119#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
14120#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
14122/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
14123#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
14124#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
14125#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
14127/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
14128#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
14129#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
14130#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
14132/******************** Bit definition for OTG register ********************/
14133#define USB_OTG_NPTXFSA_Pos (0U)
14134#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
14135#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
14136#define USB_OTG_NPTXFD_Pos (16U)
14137#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
14138#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
14139#define USB_OTG_TX0FSA_Pos (0U)
14140#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
14141#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
14142#define USB_OTG_TX0FD_Pos (16U)
14143#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
14144#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
14146/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
14147#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
14148#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
14149#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
14151/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
14152#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
14153#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
14154#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
14156#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
14157#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14158#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
14159#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14160#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14161#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14162#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14163#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14164#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14165#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14166#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14168#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
14169#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14170#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
14171#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14172#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14173#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14174#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14175#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14176#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14177#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14179/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
14180#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
14181#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
14182#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
14183#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
14184#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
14185#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
14187#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
14188#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14189#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
14190#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14191#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14192#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14193#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14194#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14195#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14196#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14197#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14198#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14199#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
14200#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
14201#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
14203#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
14204#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14205#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
14206#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14207#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14208#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14209#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14210#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14211#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14212#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14213#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14214#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14215#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
14216#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
14217#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
14219/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
14220#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
14221#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
14222#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
14224/******************** Bit definition for USB_OTG_DEACHINT register ********************/
14225#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
14226#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
14227#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
14228#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
14229#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
14230#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
14232/******************** Bit definition for USB_OTG_GCCFG register ********************/
14233#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
14234#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
14235#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
14236#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
14237#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
14238#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk
14239#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
14240#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
14241#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk
14242#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
14243#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
14244#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk
14246/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
14247#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
14248#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
14249#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
14250#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
14251#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
14252#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
14254/******************** Bit definition for USB_OTG_CID register ********************/
14255#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
14256#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
14257#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
14259/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
14260#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
14261#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
14262#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
14263#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
14264#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
14265#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
14266#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
14267#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
14268#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
14269#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
14270#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
14271#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
14272#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
14273#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
14274#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
14275#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
14276#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
14277#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
14278#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
14279#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
14280#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
14281#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
14282#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
14283#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
14284#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
14285#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
14286#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
14288/******************** Bit definition for USB_OTG_HPRT register ********************/
14289#define USB_OTG_HPRT_PCSTS_Pos (0U)
14290#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
14291#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
14292#define USB_OTG_HPRT_PCDET_Pos (1U)
14293#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
14294#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
14295#define USB_OTG_HPRT_PENA_Pos (2U)
14296#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
14297#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
14298#define USB_OTG_HPRT_PENCHNG_Pos (3U)
14299#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
14300#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
14301#define USB_OTG_HPRT_POCA_Pos (4U)
14302#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
14303#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
14304#define USB_OTG_HPRT_POCCHNG_Pos (5U)
14305#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
14306#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
14307#define USB_OTG_HPRT_PRES_Pos (6U)
14308#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
14309#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
14310#define USB_OTG_HPRT_PSUSP_Pos (7U)
14311#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
14312#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
14313#define USB_OTG_HPRT_PRST_Pos (8U)
14314#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
14315#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
14317#define USB_OTG_HPRT_PLSTS_Pos (10U)
14318#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
14319#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
14320#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
14321#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
14322#define USB_OTG_HPRT_PPWR_Pos (12U)
14323#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
14324#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
14326#define USB_OTG_HPRT_PTCTL_Pos (13U)
14327#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
14328#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
14329#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
14330#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
14331#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
14332#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
14334#define USB_OTG_HPRT_PSPD_Pos (17U)
14335#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
14336#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
14337#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
14338#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
14340/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
14341#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
14342#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
14343#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
14344#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
14345#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
14346#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
14347#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
14348#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
14349#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
14350#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
14351#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
14352#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
14353#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
14354#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
14355#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
14356#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
14357#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
14358#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
14359#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
14360#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
14361#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
14362#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
14363#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
14364#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
14365#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
14366#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
14367#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
14368#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
14369#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
14370#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
14371#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
14372#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
14373#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
14375/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
14376#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
14377#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
14378#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
14379#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
14380#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
14381#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
14383/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
14384#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
14385#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
14386#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
14387#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
14388#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
14389#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
14390#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
14391#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
14392#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
14393#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
14394#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
14395#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
14397#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
14398#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14399#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
14400#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14401#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14402#define USB_OTG_DIEPCTL_STALL_Pos (21U)
14403#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
14404#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
14406#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
14407#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14408#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
14409#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14410#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14411#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14412#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14413#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
14414#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
14415#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
14416#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
14417#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
14418#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
14419#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
14420#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
14421#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
14422#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
14423#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
14424#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
14425#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
14426#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
14427#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
14428#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
14429#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
14430#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
14432/******************** Bit definition for USB_OTG_HCCHAR register ********************/
14433#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
14434#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
14435#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
14437#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
14438#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
14439#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
14440#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
14441#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
14442#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
14443#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
14444#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
14445#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
14446#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
14447#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
14448#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
14449#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
14451#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
14452#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
14453#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
14454#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
14455#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
14457#define USB_OTG_HCCHAR_MC_Pos (20U)
14458#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
14459#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
14460#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
14461#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
14463#define USB_OTG_HCCHAR_DAD_Pos (22U)
14464#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
14465#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
14466#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
14467#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
14468#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
14469#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
14470#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
14471#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
14472#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
14473#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
14474#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
14475#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
14476#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
14477#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
14478#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
14479#define USB_OTG_HCCHAR_CHENA_Pos (31U)
14480#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
14481#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
14483/******************** Bit definition for USB_OTG_HCSPLT register ********************/
14484
14485#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
14486#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
14487#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
14488#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14489#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14490#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14491#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14492#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14493#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14494#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14496#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
14497#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
14498#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
14499#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14500#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14501#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14502#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14503#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14504#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14505#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14507#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
14508#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14509#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
14510#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14511#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14512#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
14513#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
14514#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
14515#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
14516#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
14517#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
14519/******************** Bit definition for USB_OTG_HCINT register ********************/
14520#define USB_OTG_HCINT_XFRC_Pos (0U)
14521#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
14522#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
14523#define USB_OTG_HCINT_CHH_Pos (1U)
14524#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
14525#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
14526#define USB_OTG_HCINT_AHBERR_Pos (2U)
14527#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
14528#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
14529#define USB_OTG_HCINT_STALL_Pos (3U)
14530#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
14531#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
14532#define USB_OTG_HCINT_NAK_Pos (4U)
14533#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
14534#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
14535#define USB_OTG_HCINT_ACK_Pos (5U)
14536#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
14537#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
14538#define USB_OTG_HCINT_NYET_Pos (6U)
14539#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
14540#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
14541#define USB_OTG_HCINT_TXERR_Pos (7U)
14542#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
14543#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
14544#define USB_OTG_HCINT_BBERR_Pos (8U)
14545#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
14546#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
14547#define USB_OTG_HCINT_FRMOR_Pos (9U)
14548#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
14549#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
14550#define USB_OTG_HCINT_DTERR_Pos (10U)
14551#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
14552#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
14554/******************** Bit definition for USB_OTG_DIEPINT register ********************/
14555#define USB_OTG_DIEPINT_XFRC_Pos (0U)
14556#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
14557#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
14558#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
14559#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
14560#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
14561#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
14562#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
14563#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
14564#define USB_OTG_DIEPINT_TOC_Pos (3U)
14565#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
14566#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
14567#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
14568#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
14569#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
14570#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
14571#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
14572#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
14573#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
14574#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
14575#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
14576#define USB_OTG_DIEPINT_TXFE_Pos (7U)
14577#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
14578#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
14579#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
14580#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
14581#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
14582#define USB_OTG_DIEPINT_BNA_Pos (9U)
14583#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
14584#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
14585#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
14586#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
14587#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
14588#define USB_OTG_DIEPINT_BERR_Pos (12U)
14589#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
14590#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
14591#define USB_OTG_DIEPINT_NAK_Pos (13U)
14592#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
14593#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
14595/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
14596#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
14597#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
14598#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
14599#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
14600#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
14601#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
14602#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
14603#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
14604#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
14605#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
14606#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
14607#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
14608#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
14609#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
14610#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
14611#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
14612#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
14613#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
14614#define USB_OTG_HCINTMSK_NYET_Pos (6U)
14615#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
14616#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
14617#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
14618#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
14619#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
14620#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
14621#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
14622#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
14623#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
14624#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
14625#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
14626#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
14627#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
14628#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
14630/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
14631
14632#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
14633#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
14634#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
14635#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
14636#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
14637#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
14638#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
14639#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
14640#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
14641/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
14642#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
14643#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
14644#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
14645#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
14646#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
14647#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
14648#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
14649#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
14650#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
14651#define USB_OTG_HCTSIZ_DPID_Pos (29U)
14652#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
14653#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
14654#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
14655#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
14657/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
14658#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
14659#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
14660#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
14662/******************** Bit definition for USB_OTG_HCDMA register ********************/
14663#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
14664#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
14665#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
14667/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
14668#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
14669#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
14670#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
14672/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
14673#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
14674#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
14675#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
14676#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
14677#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
14678#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
14680/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
14681
14682#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
14683#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
14684#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
14685#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
14686#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
14687#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
14688#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
14689#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
14690#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
14691#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
14692#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
14693#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
14694#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
14695#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
14696#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
14697#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
14698#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14699#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
14700#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14701#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14702#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
14703#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
14704#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
14705#define USB_OTG_DOEPCTL_STALL_Pos (21U)
14706#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
14707#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
14708#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
14709#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
14710#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
14711#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
14712#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
14713#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
14714#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
14715#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
14716#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
14717#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
14718#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
14719#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
14721/******************** Bit definition for USB_OTG_DOEPINT register ********************/
14722#define USB_OTG_DOEPINT_XFRC_Pos (0U)
14723#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
14724#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
14725#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
14726#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
14727#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
14728#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
14729#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
14730#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
14731#define USB_OTG_DOEPINT_STUP_Pos (3U)
14732#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
14733#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
14734#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
14735#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
14736#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
14737#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
14738#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
14739#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
14740#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
14741#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
14742#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
14743#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
14744#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
14745#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
14746#define USB_OTG_DOEPINT_NAK_Pos (13U)
14747#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
14748#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
14749#define USB_OTG_DOEPINT_NYET_Pos (14U)
14750#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
14751#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
14752#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
14753#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
14754#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
14755/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
14756
14757#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
14758#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
14759#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
14760#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
14761#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
14762#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
14764#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
14765#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14766#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
14767#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14768#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14770/******************** Bit definition for PCGCCTL register ********************/
14771#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
14772#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
14773#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
14774#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
14775#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
14776#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
14777#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
14778#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
14779#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
14781/* Legacy define */
14782/******************** Bit definition for OTG register ********************/
14783#define USB_OTG_CHNUM_Pos (0U)
14784#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
14785#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
14786#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
14787#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
14788#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
14789#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
14790#define USB_OTG_BCNT_Pos (4U)
14791#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
14792#define USB_OTG_BCNT USB_OTG_BCNT_Msk
14794#define USB_OTG_DPID_Pos (15U)
14795#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
14796#define USB_OTG_DPID USB_OTG_DPID_Msk
14797#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
14798#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
14800#define USB_OTG_PKTSTS_Pos (17U)
14801#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
14802#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
14803#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
14804#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
14805#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
14806#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
14808#define USB_OTG_EPNUM_Pos (0U)
14809#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
14810#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
14811#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
14812#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
14813#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
14814#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
14816#define USB_OTG_FRMNUM_Pos (21U)
14817#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
14818#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
14819#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
14820#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
14821#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
14822#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
14836/****************************** ADC Instances *********************************/
14837#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
14838 ((INSTANCE) == ADC2))
14839
14840#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
14841
14842#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14843
14844#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14845
14846/****************************** CAN Instances *********************************/
14847#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
14848 ((INSTANCE) == CAN2))
14849
14850/****************************** CRC Instances *********************************/
14851#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14852
14853/****************************** DAC Instances *********************************/
14854#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14855
14856/****************************** DMA Instances *********************************/
14857#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
14858 ((INSTANCE) == DMA1_Channel2) || \
14859 ((INSTANCE) == DMA1_Channel3) || \
14860 ((INSTANCE) == DMA1_Channel4) || \
14861 ((INSTANCE) == DMA1_Channel5) || \
14862 ((INSTANCE) == DMA1_Channel6) || \
14863 ((INSTANCE) == DMA1_Channel7) || \
14864 ((INSTANCE) == DMA2_Channel1) || \
14865 ((INSTANCE) == DMA2_Channel2) || \
14866 ((INSTANCE) == DMA2_Channel3) || \
14867 ((INSTANCE) == DMA2_Channel4) || \
14868 ((INSTANCE) == DMA2_Channel5))
14869
14870/******************************* GPIO Instances *******************************/
14871#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14872 ((INSTANCE) == GPIOB) || \
14873 ((INSTANCE) == GPIOC) || \
14874 ((INSTANCE) == GPIOD) || \
14875 ((INSTANCE) == GPIOE))
14876
14877/**************************** GPIO Alternate Function Instances ***************/
14878#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
14879
14880/**************************** GPIO Lock Instances *****************************/
14881#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
14882
14883/******************************** I2C Instances *******************************/
14884#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14885 ((INSTANCE) == I2C2))
14886
14887/******************************* SMBUS Instances ******************************/
14888#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
14889
14890/******************************** I2S Instances *******************************/
14891#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
14892 ((INSTANCE) == SPI3))
14893
14894/****************************** IWDG Instances ********************************/
14895#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
14896
14897/******************************** SPI Instances *******************************/
14898#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14899 ((INSTANCE) == SPI2) || \
14900 ((INSTANCE) == SPI3))
14901
14902/****************************** START TIM Instances ***************************/
14903/****************************** TIM Instances *********************************/
14904#define IS_TIM_INSTANCE(INSTANCE)\
14905 (((INSTANCE) == TIM1) || \
14906 ((INSTANCE) == TIM2) || \
14907 ((INSTANCE) == TIM3) || \
14908 ((INSTANCE) == TIM4) || \
14909 ((INSTANCE) == TIM5) || \
14910 ((INSTANCE) == TIM6) || \
14911 ((INSTANCE) == TIM7))
14912
14913#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
14914
14915#define IS_TIM_CC1_INSTANCE(INSTANCE)\
14916 (((INSTANCE) == TIM1) || \
14917 ((INSTANCE) == TIM2) || \
14918 ((INSTANCE) == TIM3) || \
14919 ((INSTANCE) == TIM4) || \
14920 ((INSTANCE) == TIM5))
14921
14922#define IS_TIM_CC2_INSTANCE(INSTANCE)\
14923 (((INSTANCE) == TIM1) || \
14924 ((INSTANCE) == TIM2) || \
14925 ((INSTANCE) == TIM3) || \
14926 ((INSTANCE) == TIM4) || \
14927 ((INSTANCE) == TIM5))
14928
14929#define IS_TIM_CC3_INSTANCE(INSTANCE)\
14930 (((INSTANCE) == TIM1) || \
14931 ((INSTANCE) == TIM2) || \
14932 ((INSTANCE) == TIM3) || \
14933 ((INSTANCE) == TIM4) || \
14934 ((INSTANCE) == TIM5))
14935
14936#define IS_TIM_CC4_INSTANCE(INSTANCE)\
14937 (((INSTANCE) == TIM1) || \
14938 ((INSTANCE) == TIM2) || \
14939 ((INSTANCE) == TIM3) || \
14940 ((INSTANCE) == TIM4) || \
14941 ((INSTANCE) == TIM5))
14942
14943#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
14944 (((INSTANCE) == TIM1) || \
14945 ((INSTANCE) == TIM2) || \
14946 ((INSTANCE) == TIM3) || \
14947 ((INSTANCE) == TIM4) || \
14948 ((INSTANCE) == TIM5))
14949
14950#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
14951 (((INSTANCE) == TIM1) || \
14952 ((INSTANCE) == TIM2) || \
14953 ((INSTANCE) == TIM3) || \
14954 ((INSTANCE) == TIM4) || \
14955 ((INSTANCE) == TIM5))
14956
14957#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
14958 (((INSTANCE) == TIM1) || \
14959 ((INSTANCE) == TIM2) || \
14960 ((INSTANCE) == TIM3) || \
14961 ((INSTANCE) == TIM4) || \
14962 ((INSTANCE) == TIM5))
14963
14964#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
14965 (((INSTANCE) == TIM1) || \
14966 ((INSTANCE) == TIM2) || \
14967 ((INSTANCE) == TIM3) || \
14968 ((INSTANCE) == TIM4) || \
14969 ((INSTANCE) == TIM5))
14970
14971#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
14972 (((INSTANCE) == TIM1) || \
14973 ((INSTANCE) == TIM2) || \
14974 ((INSTANCE) == TIM3) || \
14975 ((INSTANCE) == TIM4) || \
14976 ((INSTANCE) == TIM5))
14977
14978#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
14979 (((INSTANCE) == TIM1) || \
14980 ((INSTANCE) == TIM2) || \
14981 ((INSTANCE) == TIM3) || \
14982 ((INSTANCE) == TIM4) || \
14983 ((INSTANCE) == TIM5))
14984
14985#define IS_TIM_XOR_INSTANCE(INSTANCE)\
14986 (((INSTANCE) == TIM1) || \
14987 ((INSTANCE) == TIM2) || \
14988 ((INSTANCE) == TIM3) || \
14989 ((INSTANCE) == TIM4) || \
14990 ((INSTANCE) == TIM5))
14991
14992#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
14993 (((INSTANCE) == TIM1) || \
14994 ((INSTANCE) == TIM2) || \
14995 ((INSTANCE) == TIM3) || \
14996 ((INSTANCE) == TIM4) || \
14997 ((INSTANCE) == TIM5) || \
14998 ((INSTANCE) == TIM6) || \
14999 ((INSTANCE) == TIM7))
15000
15001#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
15002 (((INSTANCE) == TIM1) || \
15003 ((INSTANCE) == TIM2) || \
15004 ((INSTANCE) == TIM3) || \
15005 ((INSTANCE) == TIM4) || \
15006 ((INSTANCE) == TIM5))
15007
15008#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
15009 (((INSTANCE) == TIM1) || \
15010 ((INSTANCE) == TIM2) || \
15011 ((INSTANCE) == TIM3) || \
15012 ((INSTANCE) == TIM4) || \
15013 ((INSTANCE) == TIM5))
15014
15015#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
15016 ((INSTANCE) == TIM1)
15017
15018#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15019 ((((INSTANCE) == TIM1) && \
15020 (((CHANNEL) == TIM_CHANNEL_1) || \
15021 ((CHANNEL) == TIM_CHANNEL_2) || \
15022 ((CHANNEL) == TIM_CHANNEL_3) || \
15023 ((CHANNEL) == TIM_CHANNEL_4))) \
15024 || \
15025 (((INSTANCE) == TIM2) && \
15026 (((CHANNEL) == TIM_CHANNEL_1) || \
15027 ((CHANNEL) == TIM_CHANNEL_2) || \
15028 ((CHANNEL) == TIM_CHANNEL_3) || \
15029 ((CHANNEL) == TIM_CHANNEL_4))) \
15030 || \
15031 (((INSTANCE) == TIM3) && \
15032 (((CHANNEL) == TIM_CHANNEL_1) || \
15033 ((CHANNEL) == TIM_CHANNEL_2) || \
15034 ((CHANNEL) == TIM_CHANNEL_3) || \
15035 ((CHANNEL) == TIM_CHANNEL_4))) \
15036 || \
15037 (((INSTANCE) == TIM4) && \
15038 (((CHANNEL) == TIM_CHANNEL_1) || \
15039 ((CHANNEL) == TIM_CHANNEL_2) || \
15040 ((CHANNEL) == TIM_CHANNEL_3) || \
15041 ((CHANNEL) == TIM_CHANNEL_4))) \
15042 || \
15043 (((INSTANCE) == TIM5) && \
15044 (((CHANNEL) == TIM_CHANNEL_1) || \
15045 ((CHANNEL) == TIM_CHANNEL_2) || \
15046 ((CHANNEL) == TIM_CHANNEL_3) || \
15047 ((CHANNEL) == TIM_CHANNEL_4))))
15048
15049#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15050 (((INSTANCE) == TIM1) && \
15051 (((CHANNEL) == TIM_CHANNEL_1) || \
15052 ((CHANNEL) == TIM_CHANNEL_2) || \
15053 ((CHANNEL) == TIM_CHANNEL_3)))
15054
15055#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
15056 (((INSTANCE) == TIM1) || \
15057 ((INSTANCE) == TIM2) || \
15058 ((INSTANCE) == TIM3) || \
15059 ((INSTANCE) == TIM4) || \
15060 ((INSTANCE) == TIM5))
15061
15062#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
15063 ((INSTANCE) == TIM1)
15064
15065#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
15066 (((INSTANCE) == TIM1) || \
15067 ((INSTANCE) == TIM2) || \
15068 ((INSTANCE) == TIM3) || \
15069 ((INSTANCE) == TIM4) || \
15070 ((INSTANCE) == TIM5))
15071
15072#define IS_TIM_DMA_INSTANCE(INSTANCE)\
15073 (((INSTANCE) == TIM1) || \
15074 ((INSTANCE) == TIM2) || \
15075 ((INSTANCE) == TIM3) || \
15076 ((INSTANCE) == TIM4) || \
15077 ((INSTANCE) == TIM5) || \
15078 ((INSTANCE) == TIM6) || \
15079 ((INSTANCE) == TIM7))
15080
15081#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
15082 (((INSTANCE) == TIM1) || \
15083 ((INSTANCE) == TIM2) || \
15084 ((INSTANCE) == TIM3) || \
15085 ((INSTANCE) == TIM4) || \
15086 ((INSTANCE) == TIM5))
15087
15088#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
15089 ((INSTANCE) == TIM1)
15090
15091#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15092 ((INSTANCE) == TIM2) || \
15093 ((INSTANCE) == TIM3) || \
15094 ((INSTANCE) == TIM4) || \
15095 ((INSTANCE) == TIM5))
15096
15097#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15098 ((INSTANCE) == TIM2) || \
15099 ((INSTANCE) == TIM3) || \
15100 ((INSTANCE) == TIM4) || \
15101 ((INSTANCE) == TIM5))
15102
15103#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
15104
15105/****************************** END TIM Instances *****************************/
15106
15107
15108/******************** USART Instances : Synchronous mode **********************/
15109#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15110 ((INSTANCE) == USART2) || \
15111 ((INSTANCE) == USART3))
15112
15113/******************** UART Instances : Asynchronous mode **********************/
15114#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15115 ((INSTANCE) == USART2) || \
15116 ((INSTANCE) == USART3) || \
15117 ((INSTANCE) == UART4) || \
15118 ((INSTANCE) == UART5))
15119
15120/******************** UART Instances : Half-Duplex mode **********************/
15121#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15122 ((INSTANCE) == USART2) || \
15123 ((INSTANCE) == USART3) || \
15124 ((INSTANCE) == UART4) || \
15125 ((INSTANCE) == UART5))
15126
15127/******************** UART Instances : LIN mode **********************/
15128#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15129 ((INSTANCE) == USART2) || \
15130 ((INSTANCE) == USART3) || \
15131 ((INSTANCE) == UART4) || \
15132 ((INSTANCE) == UART5))
15133
15134/****************** UART Instances : Hardware Flow control ********************/
15135#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15136 ((INSTANCE) == USART2) || \
15137 ((INSTANCE) == USART3))
15138
15139/********************* UART Instances : Smard card mode ***********************/
15140#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15141 ((INSTANCE) == USART2) || \
15142 ((INSTANCE) == USART3))
15143
15144/*********************** UART Instances : IRDA mode ***************************/
15145#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15146 ((INSTANCE) == USART2) || \
15147 ((INSTANCE) == USART3) || \
15148 ((INSTANCE) == UART4) || \
15149 ((INSTANCE) == UART5))
15150
15151/***************** UART Instances : Multi-Processor mode **********************/
15152#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15153 ((INSTANCE) == USART2) || \
15154 ((INSTANCE) == USART3) || \
15155 ((INSTANCE) == UART4) || \
15156 ((INSTANCE) == UART5))
15157
15158/***************** UART Instances : DMA mode available **********************/
15159#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15160 ((INSTANCE) == USART2) || \
15161 ((INSTANCE) == USART3) || \
15162 ((INSTANCE) == UART4))
15163
15164/****************************** RTC Instances *********************************/
15165#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
15166
15167/**************************** WWDG Instances *****************************/
15168#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15169
15170
15171/*********************** PCD Instances ****************************************/
15172#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
15173
15174/*********************** HCD Instances ****************************************/
15175#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
15176
15177/****************************** ETH Instances ********************************/
15178#define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH)
15179
15180#define RCC_HSE_MIN 3000000U
15181#define RCC_HSE_MAX 25000000U
15182
15183#define RCC_MAX_FREQUENCY 72000000U
15184
15188/******************************************************************************/
15189/* For a painless codes migration between the STM32F1xx device product */
15190/* lines, the aliases defined below are put in place to overcome the */
15191/* differences in the interrupt handlers and IRQn definitions. */
15192/* No need to update developed interrupt code when moving across */
15193/* product lines within the same STM32F1 Family */
15194/******************************************************************************/
15195
15196/* Aliases for __IRQn */
15197#define ADC1_IRQn ADC1_2_IRQn
15198#define USB_LP_IRQn CAN1_RX0_IRQn
15199#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
15200#define USB_HP_IRQn CAN1_TX_IRQn
15201#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
15202#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
15203#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
15204#define CEC_IRQn OTG_FS_WKUP_IRQn
15205#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
15206#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
15207#define TIM9_IRQn TIM1_BRK_IRQn
15208#define TIM11_IRQn TIM1_TRG_COM_IRQn
15209#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
15210#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
15211#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
15212#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
15213#define TIM10_IRQn TIM1_UP_IRQn
15214#define TIM6_DAC_IRQn TIM6_IRQn
15215
15216
15217/* Aliases for __IRQHandler */
15218#define ADC1_IRQHandler ADC1_2_IRQHandler
15219#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
15220#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
15221#define USB_HP_IRQHandler CAN1_TX_IRQHandler
15222#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
15223#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
15224#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
15225#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
15226#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
15227#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
15228#define TIM9_IRQHandler TIM1_BRK_IRQHandler
15229#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
15230#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
15231#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
15232#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
15233#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
15234#define TIM10_IRQHandler TIM1_UP_IRQHandler
15235#define TIM6_DAC_IRQHandler TIM6_IRQHandler
15236
15237
15247#ifdef __cplusplus
15248 }
15249#endif /* __cplusplus */
15250
15251#endif /* __STM32F107xC_H */
15252
15253
15254
15255 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
core_cm3.h
CMSIS Cortex-M3 Core Peripheral Access Layer Header File.
__IO
#define __IO
Definition core_cm3.h:170
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f107xc.h:70
PendSV_IRQn
@ PendSV_IRQn
Definition stm32f107xc.h:79
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition stm32f107xc.h:138
EXTI2_IRQn
@ EXTI2_IRQn
Definition stm32f107xc.h:91
DMA2_Channel4_IRQn
@ DMA2_Channel4_IRQn
Definition stm32f107xc.h:135
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition stm32f107xc.h:105
ADC1_2_IRQn
@ ADC1_2_IRQn
Definition stm32f107xc.h:101
DMA1_Channel2_IRQn
@ DMA1_Channel2_IRQn
Definition stm32f107xc.h:95
TAMPER_IRQn
@ TAMPER_IRQn
Definition stm32f107xc.h:85
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition stm32f107xc.h:115
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition stm32f107xc.h:116
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition stm32f107xc.h:74
TIM4_IRQn
@ TIM4_IRQn
Definition stm32f107xc.h:113
TIM2_IRQn
@ TIM2_IRQn
Definition stm32f107xc.h:111
DMA1_Channel1_IRQn
@ DMA1_Channel1_IRQn
Definition stm32f107xc.h:94
DMA1_Channel3_IRQn
@ DMA1_Channel3_IRQn
Definition stm32f107xc.h:96
USART2_IRQn
@ USART2_IRQn
Definition stm32f107xc.h:121
SVCall_IRQn
@ SVCall_IRQn
Definition stm32f107xc.h:77
SPI3_IRQn
@ SPI3_IRQn
Definition stm32f107xc.h:127
SPI2_IRQn
@ SPI2_IRQn
Definition stm32f107xc.h:119
TIM1_BRK_IRQn
@ TIM1_BRK_IRQn
Definition stm32f107xc.h:107
TIM7_IRQn
@ TIM7_IRQn
Definition stm32f107xc.h:131
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition stm32f107xc.h:142
RCC_IRQn
@ RCC_IRQn
Definition stm32f107xc.h:88
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition stm32f107xc.h:117
DMA1_Channel7_IRQn
@ DMA1_Channel7_IRQn
Definition stm32f107xc.h:100
UsageFault_IRQn
@ UsageFault_IRQn
Definition stm32f107xc.h:76
SysTick_IRQn
@ SysTick_IRQn
Definition stm32f107xc.h:80
TIM1_UP_IRQn
@ TIM1_UP_IRQn
Definition stm32f107xc.h:108
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition stm32f107xc.h:140
BusFault_IRQn
@ BusFault_IRQn
Definition stm32f107xc.h:75
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition stm32f107xc.h:78
FLASH_IRQn
@ FLASH_IRQn
Definition stm32f107xc.h:87
WWDG_IRQn
@ WWDG_IRQn
Definition stm32f107xc.h:83
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition stm32f107xc.h:114
TIM3_IRQn
@ TIM3_IRQn
Definition stm32f107xc.h:112
TIM6_IRQn
@ TIM6_IRQn
Definition stm32f107xc.h:130
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition stm32f107xc.h:102
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition stm32f107xc.h:123
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition stm32f107xc.h:106
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition stm32f107xc.h:143
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition stm32f107xc.h:125
DMA1_Channel6_IRQn
@ DMA1_Channel6_IRQn
Definition stm32f107xc.h:99
SPI1_IRQn
@ SPI1_IRQn
Definition stm32f107xc.h:118
PVD_IRQn
@ PVD_IRQn
Definition stm32f107xc.h:84
HardFault_IRQn
@ HardFault_IRQn
Definition stm32f107xc.h:73
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition stm32f107xc.h:141
EXTI0_IRQn
@ EXTI0_IRQn
Definition stm32f107xc.h:89
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition stm32f107xc.h:103
EXTI4_IRQn
@ EXTI4_IRQn
Definition stm32f107xc.h:93
DMA2_Channel1_IRQn
@ DMA2_Channel1_IRQn
Definition stm32f107xc.h:132
DMA1_Channel5_IRQn
@ DMA1_Channel5_IRQn
Definition stm32f107xc.h:98
DMA2_Channel5_IRQn
@ DMA2_Channel5_IRQn
Definition stm32f107xc.h:136
TIM1_TRG_COM_IRQn
@ TIM1_TRG_COM_IRQn
Definition stm32f107xc.h:109
UART5_IRQn
@ UART5_IRQn
Definition stm32f107xc.h:129
DMA2_Channel2_IRQn
@ DMA2_Channel2_IRQn
Definition stm32f107xc.h:133
ETH_IRQn
@ ETH_IRQn
Definition stm32f107xc.h:137
USART1_IRQn
@ USART1_IRQn
Definition stm32f107xc.h:120
DMA2_Channel3_IRQn
@ DMA2_Channel3_IRQn
Definition stm32f107xc.h:134
RTC_IRQn
@ RTC_IRQn
Definition stm32f107xc.h:86
EXTI3_IRQn
@ EXTI3_IRQn
Definition stm32f107xc.h:92
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition stm32f107xc.h:72
UART4_IRQn
@ UART4_IRQn
Definition stm32f107xc.h:128
DMA1_Channel4_IRQn
@ DMA1_Channel4_IRQn
Definition stm32f107xc.h:97
EXTI1_IRQn
@ EXTI1_IRQn
Definition stm32f107xc.h:90
TIM5_IRQn
@ TIM5_IRQn
Definition stm32f107xc.h:126
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition stm32f107xc.h:110
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition stm32f107xc.h:139
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition stm32f107xc.h:104
USART3_IRQn
@ USART3_IRQn
Definition stm32f107xc.h:122
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition stm32f107xc.h:124
ADC_Common_TypeDef
Definition stm32f107xc.h:187
ADC_Common_TypeDef::CR1
__IO uint32_t CR1
Definition stm32f107xc.h:189
ADC_Common_TypeDef::DR
__IO uint32_t DR
Definition stm32f107xc.h:192
ADC_Common_TypeDef::CR2
__IO uint32_t CR2
Definition stm32f107xc.h:190
ADC_Common_TypeDef::SR
__IO uint32_t SR
Definition stm32f107xc.h:188
ADC_TypeDef
Analog to Digital Converter
Definition stm32f107xc.h:163
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition stm32f107xc.h:175
ADC_TypeDef::CR2
__IO uint32_t CR2
Definition stm32f107xc.h:166
ADC_TypeDef::HTR
__IO uint32_t HTR
Definition stm32f107xc.h:173
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition stm32f107xc.h:181
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition stm32f107xc.h:177
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition stm32f107xc.h:178
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition stm32f107xc.h:176
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition stm32f107xc.h:167
ADC_TypeDef::DR
__IO uint32_t DR
Definition stm32f107xc.h:183
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition stm32f107xc.h:180
ADC_TypeDef::CR1
__IO uint32_t CR1
Definition stm32f107xc.h:165
ADC_TypeDef::JOFR4
__IO uint32_t JOFR4
Definition stm32f107xc.h:172
ADC_TypeDef::SR
__IO uint32_t SR
Definition stm32f107xc.h:164
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition stm32f107xc.h:168
ADC_TypeDef::JOFR1
__IO uint32_t JOFR1
Definition stm32f107xc.h:169
ADC_TypeDef::JOFR2
__IO uint32_t JOFR2
Definition stm32f107xc.h:170
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition stm32f107xc.h:179
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition stm32f107xc.h:182
ADC_TypeDef::JOFR3
__IO uint32_t JOFR3
Definition stm32f107xc.h:171
ADC_TypeDef::LTR
__IO uint32_t LTR
Definition stm32f107xc.h:174
AFIO_TypeDef
Alternate Function I/O.
Definition stm32f107xc.h:517
BKP_TypeDef
Backup Registers
Definition stm32f107xc.h:200
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition stm32f107xc.h:267
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition stm32f107xc.h:268
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition stm32f107xc.h:269
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition stm32f107xc.h:271
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition stm32f107xc.h:270
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition stm32f107xc.h:279
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition stm32f107xc.h:281
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition stm32f107xc.h:280
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition stm32f107xc.h:255
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition stm32f107xc.h:256
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition stm32f107xc.h:257
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition stm32f107xc.h:258
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition stm32f107xc.h:259
CAN_TypeDef
Controller Area Network.
Definition stm32f107xc.h:289
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition stm32f107xc.h:290
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition stm32f107xc.h:302
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition stm32f107xc.h:308
CAN_TypeDef::IER
__IO uint32_t IER
Definition stm32f107xc.h:295
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition stm32f107xc.h:294
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition stm32f107xc.h:296
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32f107xc.h:304
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition stm32f107xc.h:309
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition stm32f107xc.h:305
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition stm32f107xc.h:292
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition stm32f107xc.h:297
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition stm32f107xc.h:293
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition stm32f107xc.h:307
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition stm32f107xc.h:303
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32f107xc.h:306
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition stm32f107xc.h:291
CRC_TypeDef
CRC calculation unit.
Definition stm32f107xc.h:319
CRC_TypeDef::DR
__IO uint32_t DR
Definition stm32f107xc.h:320
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition stm32f107xc.h:322
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition stm32f107xc.h:323
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition stm32f107xc.h:321
CRC_TypeDef::CR
__IO uint32_t CR
Definition stm32f107xc.h:324
DAC_TypeDef
Digital to Analog Converter.
Definition stm32f107xc.h:332
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition stm32f107xc.h:343
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition stm32f107xc.h:345
DAC_TypeDef::CR
__IO uint32_t CR
Definition stm32f107xc.h:333
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition stm32f107xc.h:337
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition stm32f107xc.h:340
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition stm32f107xc.h:334
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition stm32f107xc.h:344
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition stm32f107xc.h:336
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition stm32f107xc.h:339
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition stm32f107xc.h:338
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition stm32f107xc.h:342
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition stm32f107xc.h:335
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition stm32f107xc.h:341
DBGMCU_TypeDef
Debug MCU.
Definition stm32f107xc.h:353
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition stm32f107xc.h:354
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition stm32f107xc.h:355
DMA_Channel_TypeDef
DMA Controller.
Definition stm32f107xc.h:363
DMA_TypeDef
Definition stm32f107xc.h:371
ETH_TypeDef
Ethernet MAC.
Definition stm32f107xc.h:383
EXTI_TypeDef
External Interrupt/Event Controller.
Definition stm32f107xc.h:455
EXTI_TypeDef::PR
__IO uint32_t PR
Definition stm32f107xc.h:461
EXTI_TypeDef::IMR
__IO uint32_t IMR
Definition stm32f107xc.h:456
EXTI_TypeDef::SWIER
__IO uint32_t SWIER
Definition stm32f107xc.h:460
EXTI_TypeDef::EMR
__IO uint32_t EMR
Definition stm32f107xc.h:457
EXTI_TypeDef::RTSR
__IO uint32_t RTSR
Definition stm32f107xc.h:458
EXTI_TypeDef::FTSR
__IO uint32_t FTSR
Definition stm32f107xc.h:459
FLASH_TypeDef
FLASH Registers.
Definition stm32f107xc.h:469
FLASH_TypeDef::SR
__IO uint32_t SR
Definition stm32f107xc.h:473
FLASH_TypeDef::CR
__IO uint32_t CR
Definition stm32f107xc.h:474
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition stm32f107xc.h:472
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition stm32f107xc.h:471
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition stm32f107xc.h:470
GPIO_TypeDef
General Purpose I/O.
Definition stm32f107xc.h:502
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition stm32f107xc.h:506
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition stm32f107xc.h:509
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition stm32f107xc.h:507
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition stm32f107xc.h:505
I2C_TypeDef
Inter Integrated Circuit Interface.
Definition stm32f107xc.h:529
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition stm32f107xc.h:531
I2C_TypeDef::CCR
__IO uint32_t CCR
Definition stm32f107xc.h:537
I2C_TypeDef::DR
__IO uint32_t DR
Definition stm32f107xc.h:534
I2C_TypeDef::SR1
__IO uint32_t SR1
Definition stm32f107xc.h:535
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition stm32f107xc.h:533
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition stm32f107xc.h:530
I2C_TypeDef::TRISE
__IO uint32_t TRISE
Definition stm32f107xc.h:538
I2C_TypeDef::SR2
__IO uint32_t SR2
Definition stm32f107xc.h:536
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition stm32f107xc.h:532
IWDG_TypeDef
Independent WATCHDOG.
Definition stm32f107xc.h:546
IWDG_TypeDef::PR
__IO uint32_t PR
Definition stm32f107xc.h:548
IWDG_TypeDef::KR
__IO uint32_t KR
Definition stm32f107xc.h:547
IWDG_TypeDef::SR
__IO uint32_t SR
Definition stm32f107xc.h:550
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition stm32f107xc.h:549
OB_TypeDef
Option Bytes Registers.
Definition stm32f107xc.h:486
PWR_TypeDef
Power Control.
Definition stm32f107xc.h:558
PWR_TypeDef::CSR
__IO uint32_t CSR
Definition stm32f107xc.h:560
PWR_TypeDef::CR
__IO uint32_t CR
Definition stm32f107xc.h:559
RCC_TypeDef
Reset and Clock Control.
Definition stm32f107xc.h:568
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition stm32f107xc.h:577
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition stm32f107xc.h:570
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition stm32f107xc.h:572
RCC_TypeDef::APB1RSTR
__IO uint32_t APB1RSTR
Definition stm32f107xc.h:573
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition stm32f107xc.h:575
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition stm32f107xc.h:578
RCC_TypeDef::CR
__IO uint32_t CR
Definition stm32f107xc.h:569
RCC_TypeDef::CIR
__IO uint32_t CIR
Definition stm32f107xc.h:571
RCC_TypeDef::APB1ENR
__IO uint32_t APB1ENR
Definition stm32f107xc.h:576
RTC_TypeDef
Real-Time Clock.
Definition stm32f107xc.h:590
SPI_TypeDef
Serial Peripheral Interface.
Definition stm32f107xc.h:608
SPI_TypeDef::DR
__IO uint32_t DR
Definition stm32f107xc.h:612
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition stm32f107xc.h:615
SPI_TypeDef::SR
__IO uint32_t SR
Definition stm32f107xc.h:611
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition stm32f107xc.h:610
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
Definition stm32f107xc.h:616
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition stm32f107xc.h:613
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition stm32f107xc.h:614
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition stm32f107xc.h:609
SPI_TypeDef::I2SPR
__IO uint32_t I2SPR
Definition stm32f107xc.h:617
TIM_TypeDef
TIM Timers.
Definition stm32f107xc.h:624
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition stm32f107xc.h:630
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition stm32f107xc.h:638
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition stm32f107xc.h:631
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition stm32f107xc.h:642
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition stm32f107xc.h:628
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition stm32f107xc.h:639
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition stm32f107xc.h:641
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition stm32f107xc.h:627
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition stm32f107xc.h:636
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition stm32f107xc.h:626
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition stm32f107xc.h:634
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition stm32f107xc.h:643
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition stm32f107xc.h:625
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition stm32f107xc.h:632
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition stm32f107xc.h:640
TIM_TypeDef::OR
__IO uint32_t OR
Definition stm32f107xc.h:645
TIM_TypeDef::SR
__IO uint32_t SR
Definition stm32f107xc.h:629
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition stm32f107xc.h:635
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition stm32f107xc.h:637
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition stm32f107xc.h:633
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition stm32f107xc.h:644
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32f107xc.h:654
USART_TypeDef::DR
__IO uint32_t DR
Definition stm32f107xc.h:656
USART_TypeDef::CR1
__IO uint32_t CR1
Definition stm32f107xc.h:658
USART_TypeDef::BRR
__IO uint32_t BRR
Definition stm32f107xc.h:657
USART_TypeDef::SR
__IO uint32_t SR
Definition stm32f107xc.h:655
USART_TypeDef::CR2
__IO uint32_t CR2
Definition stm32f107xc.h:659
USART_TypeDef::GTPR
__IO uint32_t GTPR
Definition stm32f107xc.h:661
USART_TypeDef::CR3
__IO uint32_t CR3
Definition stm32f107xc.h:660
USB_OTG_DeviceTypeDef
__device_Registers
Definition stm32f107xc.h:696
USB_OTG_DeviceTypeDef::DVBUSDIS
__IO uint32_t DVBUSDIS
Definition stm32f107xc.h:707
USB_OTG_DeviceTypeDef::DCTL
__IO uint32_t DCTL
Definition stm32f107xc.h:698
USB_OTG_DeviceTypeDef::DSTS
__IO uint32_t DSTS
Definition stm32f107xc.h:699
USB_OTG_DeviceTypeDef::DAINTMSK
__IO uint32_t DAINTMSK
Definition stm32f107xc.h:704
USB_OTG_DeviceTypeDef::Reserved20
uint32_t Reserved20
Definition stm32f107xc.h:705
USB_OTG_DeviceTypeDef::Reserved40
uint32_t Reserved40
Definition stm32f107xc.h:713
USB_OTG_DeviceTypeDef::DAINT
__IO uint32_t DAINT
Definition stm32f107xc.h:703
USB_OTG_DeviceTypeDef::DIEPEMPMSK
__IO uint32_t DIEPEMPMSK
Definition stm32f107xc.h:710
USB_OTG_DeviceTypeDef::DINEP1MSK
__IO uint32_t DINEP1MSK
Definition stm32f107xc.h:714
USB_OTG_DeviceTypeDef::Reserved9
uint32_t Reserved9
Definition stm32f107xc.h:706
USB_OTG_DeviceTypeDef::DVBUSPULSE
__IO uint32_t DVBUSPULSE
Definition stm32f107xc.h:708
USB_OTG_DeviceTypeDef::DEACHINT
__IO uint32_t DEACHINT
Definition stm32f107xc.h:711
USB_OTG_DeviceTypeDef::Reserved0C
uint32_t Reserved0C
Definition stm32f107xc.h:700
USB_OTG_DeviceTypeDef::DIEPMSK
__IO uint32_t DIEPMSK
Definition stm32f107xc.h:701
USB_OTG_DeviceTypeDef::DCFG
__IO uint32_t DCFG
Definition stm32f107xc.h:697
USB_OTG_DeviceTypeDef::DOUTEP1MSK
__IO uint32_t DOUTEP1MSK
Definition stm32f107xc.h:716
USB_OTG_DeviceTypeDef::DEACHMSK
__IO uint32_t DEACHMSK
Definition stm32f107xc.h:712
USB_OTG_DeviceTypeDef::DOEPMSK
__IO uint32_t DOEPMSK
Definition stm32f107xc.h:702
USB_OTG_DeviceTypeDef::DTHRCTL
__IO uint32_t DTHRCTL
Definition stm32f107xc.h:709
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition stm32f107xc.h:670
USB_OTG_GlobalTypeDef::GRXSTSP
__IO uint32_t GRXSTSP
Definition stm32f107xc.h:679
USB_OTG_GlobalTypeDef::GOTGINT
__IO uint32_t GOTGINT
Definition stm32f107xc.h:672
USB_OTG_GlobalTypeDef::GINTSTS
__IO uint32_t GINTSTS
Definition stm32f107xc.h:676
USB_OTG_GlobalTypeDef::GUSBCFG
__IO uint32_t GUSBCFG
Definition stm32f107xc.h:674
USB_OTG_GlobalTypeDef::GAHBCFG
__IO uint32_t GAHBCFG
Definition stm32f107xc.h:673
USB_OTG_GlobalTypeDef::GINTMSK
__IO uint32_t GINTMSK
Definition stm32f107xc.h:677
USB_OTG_GlobalTypeDef::GOTGCTL
__IO uint32_t GOTGCTL
Definition stm32f107xc.h:671
USB_OTG_GlobalTypeDef::CID
__IO uint32_t CID
Definition stm32f107xc.h:685
USB_OTG_GlobalTypeDef::GRSTCTL
__IO uint32_t GRSTCTL
Definition stm32f107xc.h:675
USB_OTG_GlobalTypeDef::GRXSTSR
__IO uint32_t GRXSTSR
Definition stm32f107xc.h:678
USB_OTG_GlobalTypeDef::HNPTXSTS
__IO uint32_t HNPTXSTS
Definition stm32f107xc.h:682
USB_OTG_GlobalTypeDef::GCCFG
__IO uint32_t GCCFG
Definition stm32f107xc.h:684
USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ
__IO uint32_t DIEPTXF0_HNPTXFSIZ
Definition stm32f107xc.h:681
USB_OTG_GlobalTypeDef::HPTXFSIZ
__IO uint32_t HPTXFSIZ
Definition stm32f107xc.h:687
USB_OTG_GlobalTypeDef::GRXFSIZ
__IO uint32_t GRXFSIZ
Definition stm32f107xc.h:680
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition stm32f107xc.h:770
USB_OTG_HostChannelTypeDef::HCTSIZ
__IO uint32_t HCTSIZ
Definition stm32f107xc.h:775
USB_OTG_HostChannelTypeDef::HCSPLT
__IO uint32_t HCSPLT
Definition stm32f107xc.h:772
USB_OTG_HostChannelTypeDef::HCDMA
__IO uint32_t HCDMA
Definition stm32f107xc.h:776
USB_OTG_HostChannelTypeDef::HCINT
__IO uint32_t HCINT
Definition stm32f107xc.h:773
USB_OTG_HostChannelTypeDef::HCCHAR
__IO uint32_t HCCHAR
Definition stm32f107xc.h:771
USB_OTG_HostChannelTypeDef::HCINTMSK
__IO uint32_t HCINTMSK
Definition stm32f107xc.h:774
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition stm32f107xc.h:755
USB_OTG_HostTypeDef::Reserved40C
uint32_t Reserved40C
Definition stm32f107xc.h:759
USB_OTG_HostTypeDef::HFIR
__IO uint32_t HFIR
Definition stm32f107xc.h:757
USB_OTG_HostTypeDef::HAINTMSK
__IO uint32_t HAINTMSK
Definition stm32f107xc.h:762
USB_OTG_HostTypeDef::HCFG
__IO uint32_t HCFG
Definition stm32f107xc.h:756
USB_OTG_HostTypeDef::HFNUM
__IO uint32_t HFNUM
Definition stm32f107xc.h:758
USB_OTG_HostTypeDef::HPTXSTS
__IO uint32_t HPTXSTS
Definition stm32f107xc.h:760
USB_OTG_HostTypeDef::HAINT
__IO uint32_t HAINT
Definition stm32f107xc.h:761
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition stm32f107xc.h:724
USB_OTG_INEndpointTypeDef::DTXFSTS
__IO uint32_t DTXFSTS
Definition stm32f107xc.h:731
USB_OTG_INEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition stm32f107xc.h:728
USB_OTG_INEndpointTypeDef::Reserved18
uint32_t Reserved18
Definition stm32f107xc.h:732
USB_OTG_INEndpointTypeDef::DIEPCTL
__IO uint32_t DIEPCTL
Definition stm32f107xc.h:725
USB_OTG_INEndpointTypeDef::DIEPDMA
__IO uint32_t DIEPDMA
Definition stm32f107xc.h:730
USB_OTG_INEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition stm32f107xc.h:726
USB_OTG_INEndpointTypeDef::DIEPTSIZ
__IO uint32_t DIEPTSIZ
Definition stm32f107xc.h:729
USB_OTG_INEndpointTypeDef::DIEPINT
__IO uint32_t DIEPINT
Definition stm32f107xc.h:727
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition stm32f107xc.h:740
USB_OTG_OUTEndpointTypeDef::DOEPINT
__IO uint32_t DOEPINT
Definition stm32f107xc.h:743
USB_OTG_OUTEndpointTypeDef::DOEPDMA
__IO uint32_t DOEPDMA
Definition stm32f107xc.h:746
USB_OTG_OUTEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition stm32f107xc.h:744
USB_OTG_OUTEndpointTypeDef::DOEPTSIZ
__IO uint32_t DOEPTSIZ
Definition stm32f107xc.h:745
USB_OTG_OUTEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition stm32f107xc.h:742
USB_OTG_OUTEndpointTypeDef::DOEPCTL
__IO uint32_t DOEPCTL
Definition stm32f107xc.h:741
WWDG_TypeDef
Window WATCHDOG.
Definition stm32f107xc.h:785
WWDG_TypeDef::SR
__IO uint32_t SR
Definition stm32f107xc.h:788
WWDG_TypeDef::CR
__IO uint32_t CR
Definition stm32f107xc.h:786
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition stm32f107xc.h:787