mikroSDK Reference Manual
stm32f1xx_hal_rcc_ex.h
Go to the documentation of this file.
1
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F1xx_HAL_RCC_EX_H
22#define __STM32F1xx_HAL_RCC_EX_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f1xx_hal_def.h"
30
43#if defined(STM32F105xC) || defined(STM32F107xC)
44
45/* Alias word address of PLLI2SON bit */
46#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos
47#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U)))
48/* Alias word address of PLL2ON bit */
49#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos
50#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U)))
51
52#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */
53#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */
54
55#endif /* STM32F105xC || STM32F107xC */
56
57
58#define CR_REG_INDEX ((uint8_t)1)
59
68#if defined(STM32F105xC) || defined(STM32F107xC)
69#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
70 ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
71#endif /* STM32F105xC || STM32F107xC */
72
73#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
74 || defined(STM32F100xE)
75#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \
76 ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \
77 ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \
78 ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \
79 ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
80 ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
81 ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
82 ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
83
84#else
85#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
86#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
87
88#if defined(STM32F105xC) || defined(STM32F107xC)
89#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
90 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
91 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
92 ((__MUL__) == RCC_PLL_MUL6_5))
93
94#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
95 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
96 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
97 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
98 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
99
100#else
101#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
102 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
103 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
104 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
105 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
106 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
107 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
108 ((__MUL__) == RCC_PLL_MUL16))
109
110#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
111 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
112 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
113
114#endif /* STM32F105xC || STM32F107xC*/
115
116#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \
117 ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
118
119#if defined(STM32F105xC) || defined(STM32F107xC)
120#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
121
122#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
123
124#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
125
126#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \
127 ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \
128 ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \
129 ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \
130 ((__MUL__) == RCC_PLLI2S_MUL20))
131
132#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \
133 ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \
134 ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \
135 ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \
136 ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
137 ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
138 ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
139 ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
140
141#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
142 ((__PLL__) == RCC_PLL2_ON))
143
144#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \
145 ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \
146 ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \
147 ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \
148 ((__MUL__) == RCC_PLL2_MUL20))
149
150#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
151 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
152 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
153 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
154 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
155 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
156
157#elif defined(STM32F103xE) || defined(STM32F103xG)
158
159#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
160
161#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
162
163#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
164 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
165 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
166 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
167 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
168 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
169
170
171#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
172 || defined(STM32F103xB)
173
174#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
175 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
176 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
177 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
178
179#else
180
181#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
182 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
183 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
184
185#endif /* STM32F105xC || STM32F107xC */
186
187#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
188 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
189
190#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
191
192#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
193
198/* Exported types ------------------------------------------------------------*/
199
204#if defined(STM32F105xC) || defined(STM32F107xC)
208typedef struct
209{
210 uint32_t PLL2State;
213 uint32_t PLL2MUL;
216#if defined(STM32F105xC) || defined(STM32F107xC)
217 uint32_t HSEPrediv2Value;
220#endif /* STM32F105xC || STM32F107xC */
221} RCC_PLL2InitTypeDef;
222
223#endif /* STM32F105xC || STM32F107xC */
224
228typedef struct
229{
230 uint32_t OscillatorType;
233#if defined(STM32F105xC) || defined(STM32F107xC)
234 uint32_t Prediv1Source;
236#endif /* STM32F105xC || STM32F107xC */
237
238 uint32_t HSEState;
241 uint32_t HSEPredivValue;
244 uint32_t LSEState;
247 uint32_t HSIState;
250 uint32_t HSICalibrationValue;
253 uint32_t LSIState;
256 RCC_PLLInitTypeDef PLL;
258#if defined(STM32F105xC) || defined(STM32F107xC)
259 RCC_PLL2InitTypeDef PLL2;
260#endif /* STM32F105xC || STM32F107xC */
261} RCC_OscInitTypeDef;
262
263#if defined(STM32F105xC) || defined(STM32F107xC)
267typedef struct
268{
269 uint32_t PLLI2SMUL;
272#if defined(STM32F105xC) || defined(STM32F107xC)
273 uint32_t HSEPrediv2Value;
276#endif /* STM32F105xC || STM32F107xC */
277} RCC_PLLI2SInitTypeDef;
278#endif /* STM32F105xC || STM32F107xC */
279
283typedef struct
284{
285 uint32_t PeriphClockSelection;
288 uint32_t RTCClockSelection;
291 uint32_t AdcClockSelection;
294#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
295 || defined(STM32F107xC)
296 uint32_t I2s2ClockSelection;
299 uint32_t I2s3ClockSelection;
302#if defined(STM32F105xC) || defined(STM32F107xC)
303 RCC_PLLI2SInitTypeDef PLLI2S;
306#endif /* STM32F105xC || STM32F107xC */
307#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
308
309#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
310 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
311 || defined(STM32F105xC) || defined(STM32F107xC)
312 uint32_t UsbClockSelection;
315#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
316} RCC_PeriphCLKInitTypeDef;
317
322/* Exported constants --------------------------------------------------------*/
323
331#define RCC_PERIPHCLK_RTC 0x00000001U
332#define RCC_PERIPHCLK_ADC 0x00000002U
333#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\
334 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
335#define RCC_PERIPHCLK_I2S2 0x00000004U
336#define RCC_PERIPHCLK_I2S3 0x00000008U
337#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
338#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
339 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
340 || defined(STM32F105xC) || defined(STM32F107xC)
341#define RCC_PERIPHCLK_USB 0x00000010U
342#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
343
351#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
352#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
353#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
354#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
355
360#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
361 || defined(STM32F107xC)
365#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U
366#if defined(STM32F105xC) || defined(STM32F107xC)
367#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
368#endif /* STM32F105xC || STM32F107xC */
369
377#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U
378#if defined(STM32F105xC) || defined(STM32F107xC)
379#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
380#endif /* STM32F105xC || STM32F107xC */
381
386#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
387
388#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
389 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
390
394#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
395#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U
396
401#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
402
403
404#if defined(STM32F105xC) || defined(STM32F107xC)
408#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
409#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U
410
419#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8
420#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9
421#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10
422#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11
423#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12
424#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13
425#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14
426#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16
427#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20
432#endif /* STM32F105xC || STM32F107xC */
433
434#if defined(STM32F105xC) || defined(STM32F107xC)
439#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
440#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
441
445#endif /* STM32F105xC || STM32F107xC */
446
451#define RCC_HSE_PREDIV_DIV1 0x00000000U
452
453#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
454 || defined(STM32F100xE)
455#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
456#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
457#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
458#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
459#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
460#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
461#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
462#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
463#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
464#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
465#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
466#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
467#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
468#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
469#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
470#else
471#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
472#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
473
478#if defined(STM32F105xC) || defined(STM32F107xC)
483#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1
484#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2
485#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3
486#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4
487#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5
488#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6
489#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7
490#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8
491#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9
492#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10
493#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11
494#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12
495#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13
496#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14
497#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15
498#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16
507#define RCC_PLL2_NONE 0x00000000U
508#define RCC_PLL2_OFF 0x00000001U
509#define RCC_PLL2_ON 0x00000002U
510
519#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8
520#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9
521#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10
522#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11
523#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12
524#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13
525#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14
526#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16
527#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20
533#endif /* STM32F105xC || STM32F107xC */
534
539#if defined(STM32F105xC) || defined(STM32F107xC)
540#else
541#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
542#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
543#endif /* STM32F105xC || STM32F107xC */
544#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
545#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
546#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
547#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
548#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
549#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
550#if defined(STM32F105xC) || defined(STM32F107xC)
551#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
552#else
553#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
554#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
555#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
556#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
557#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
558#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
559#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
560#endif /* STM32F105xC || STM32F107xC */
561
569#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
570#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
571#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
572#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
573#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
574#if defined(STM32F105xC) || defined(STM32F107xC)
575#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
576#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
577#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
578#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
579#endif /* STM32F105xC || STM32F107xC*/
584#if defined(STM32F105xC) || defined(STM32F107xC)
588#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
589#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
601/* Flags in the CR register */
602#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos))
603#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos))
607#endif /* STM32F105xC || STM32F107xC*/
608
613/* Exported macro ------------------------------------------------------------*/
626#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
627 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
628 || defined (STM32F100xE)
629#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
630 __IO uint32_t tmpreg; \
631 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
632 /* Delay after an RCC peripheral clock enabling */ \
633 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
634 UNUSED(tmpreg); \
635 } while(0U)
636
637#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
638#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
639
640#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
641 || defined(STM32F103xG) || defined (STM32F100xE)
642#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
643 __IO uint32_t tmpreg; \
644 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
645 /* Delay after an RCC peripheral clock enabling */ \
646 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
647 UNUSED(tmpreg); \
648 } while(0U)
649
650#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
651#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
652
653#if defined(STM32F103xE) || defined(STM32F103xG)
654#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
655 __IO uint32_t tmpreg; \
656 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
657 /* Delay after an RCC peripheral clock enabling */ \
658 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
659 UNUSED(tmpreg); \
660 } while(0U)
661
662
663#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
664#endif /* STM32F103xE || STM32F103xG */
665
666#if defined(STM32F105xC) || defined(STM32F107xC)
667#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
668 __IO uint32_t tmpreg; \
669 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
670 /* Delay after an RCC peripheral clock enabling */ \
671 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
672 UNUSED(tmpreg); \
673 } while(0U)
674
675
676#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
677#endif /* STM32F105xC || STM32F107xC*/
678
679#if defined(STM32F107xC)
680#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
681 __IO uint32_t tmpreg; \
682 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
683 /* Delay after an RCC peripheral clock enabling */ \
684 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
685 UNUSED(tmpreg); \
686 } while(0U)
687
688#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
689 __IO uint32_t tmpreg; \
690 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
691 /* Delay after an RCC peripheral clock enabling */ \
692 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
693 UNUSED(tmpreg); \
694 } while(0U)
695
696#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
697 __IO uint32_t tmpreg; \
698 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
699 /* Delay after an RCC peripheral clock enabling */ \
700 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
701 UNUSED(tmpreg); \
702 } while(0U)
703
704#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
705#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
706#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
707
711#define __HAL_RCC_ETH_CLK_ENABLE() do { \
712 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
713 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
714 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
715 } while(0U)
719#define __HAL_RCC_ETH_CLK_DISABLE() do { \
720 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
721 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
722 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
723 } while(0U)
724
725#endif /* STM32F107xC*/
726
739#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
740 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
741 || defined (STM32F100xE)
742#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
743#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
744#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
745#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
746 || defined(STM32F103xG) || defined (STM32F100xE)
747#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
748#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
749#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
750#if defined(STM32F103xE) || defined(STM32F103xG)
751#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
752#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
753#endif /* STM32F103xE || STM32F103xG */
754#if defined(STM32F105xC) || defined(STM32F107xC)
755#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
756#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
757#endif /* STM32F105xC || STM32F107xC*/
758#if defined(STM32F107xC)
759#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
760#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
761#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
762#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
763#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
764#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
765#endif /* STM32F107xC*/
766
779#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
780 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
781#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
782 __IO uint32_t tmpreg; \
783 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
784 /* Delay after an RCC peripheral clock enabling */ \
785 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
786 UNUSED(tmpreg); \
787 } while(0U)
788
789#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
790#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
791
792#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
793 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
794 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
795 || defined(STM32F105xC) || defined(STM32F107xC)
796#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
797 __IO uint32_t tmpreg; \
798 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
799 /* Delay after an RCC peripheral clock enabling */ \
800 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
801 UNUSED(tmpreg); \
802 } while(0U)
803
804#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
805 __IO uint32_t tmpreg; \
806 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
807 /* Delay after an RCC peripheral clock enabling */ \
808 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
809 UNUSED(tmpreg); \
810 } while(0U)
811
812#define __HAL_RCC_USART3_CLK_ENABLE() do { \
813 __IO uint32_t tmpreg; \
814 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
815 /* Delay after an RCC peripheral clock enabling */ \
816 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
817 UNUSED(tmpreg); \
818 } while(0U)
819
820#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
821 __IO uint32_t tmpreg; \
822 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
823 /* Delay after an RCC peripheral clock enabling */ \
824 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
825 UNUSED(tmpreg); \
826 } while(0U)
827
828#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
829#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
830#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
831#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
832#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
833
834#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
835 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
836#define __HAL_RCC_USB_CLK_ENABLE() do { \
837 __IO uint32_t tmpreg; \
838 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
839 /* Delay after an RCC peripheral clock enabling */ \
840 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
841 UNUSED(tmpreg); \
842 } while(0U)
843
844#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
845#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
846
847#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
848 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
849#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
850 __IO uint32_t tmpreg; \
851 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
852 /* Delay after an RCC peripheral clock enabling */ \
853 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
854 UNUSED(tmpreg); \
855 } while(0U)
856
857#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
858 __IO uint32_t tmpreg; \
859 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
860 /* Delay after an RCC peripheral clock enabling */ \
861 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
862 UNUSED(tmpreg); \
863 } while(0U)
864
865#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
866 __IO uint32_t tmpreg; \
867 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
868 /* Delay after an RCC peripheral clock enabling */ \
869 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
870 UNUSED(tmpreg); \
871 } while(0U)
872
873#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
874 __IO uint32_t tmpreg; \
875 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
876 /* Delay after an RCC peripheral clock enabling */ \
877 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
878 UNUSED(tmpreg); \
879 } while(0U)
880
881#define __HAL_RCC_UART4_CLK_ENABLE() do { \
882 __IO uint32_t tmpreg; \
883 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
884 /* Delay after an RCC peripheral clock enabling */ \
885 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
886 UNUSED(tmpreg); \
887 } while(0U)
888
889#define __HAL_RCC_UART5_CLK_ENABLE() do { \
890 __IO uint32_t tmpreg; \
891 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
892 /* Delay after an RCC peripheral clock enabling */ \
893 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
894 UNUSED(tmpreg); \
895 } while(0U)
896
897#define __HAL_RCC_DAC_CLK_ENABLE() do { \
898 __IO uint32_t tmpreg; \
899 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
900 /* Delay after an RCC peripheral clock enabling */ \
901 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
902 UNUSED(tmpreg); \
903 } while(0U)
904
905#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
906#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
907#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
908#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
909#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
910#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
911#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
912#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
913
914#if defined(STM32F100xB) || defined (STM32F100xE)
915#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
916 __IO uint32_t tmpreg; \
917 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
918 /* Delay after an RCC peripheral clock enabling */ \
919 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
920 UNUSED(tmpreg); \
921 } while(0U)
922
923#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
924 __IO uint32_t tmpreg; \
925 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
926 /* Delay after an RCC peripheral clock enabling */ \
927 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
928 UNUSED(tmpreg); \
929 } while(0U)
930
931#define __HAL_RCC_DAC_CLK_ENABLE() do { \
932 __IO uint32_t tmpreg; \
933 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
934 /* Delay after an RCC peripheral clock enabling */ \
935 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
936 UNUSED(tmpreg); \
937 } while(0U)
938
939#define __HAL_RCC_CEC_CLK_ENABLE() do { \
940 __IO uint32_t tmpreg; \
941 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
942 /* Delay after an RCC peripheral clock enabling */ \
943 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
944 UNUSED(tmpreg); \
945 } while(0U)
946
947#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
948#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
949#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
950#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
951#endif /* STM32F100xB || STM32F100xE */
952
953#ifdef STM32F100xE
954#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
955 __IO uint32_t tmpreg; \
956 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
957 /* Delay after an RCC peripheral clock enabling */ \
958 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
959 UNUSED(tmpreg); \
960 } while(0U)
961
962#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
963 __IO uint32_t tmpreg; \
964 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
965 /* Delay after an RCC peripheral clock enabling */ \
966 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
967 UNUSED(tmpreg); \
968 } while(0U)
969
970#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
971 __IO uint32_t tmpreg; \
972 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
973 /* Delay after an RCC peripheral clock enabling */ \
974 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
975 UNUSED(tmpreg); \
976 } while(0U)
977
978#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
979 __IO uint32_t tmpreg; \
980 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
981 /* Delay after an RCC peripheral clock enabling */ \
982 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
983 UNUSED(tmpreg); \
984 } while(0U)
985
986#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
987 __IO uint32_t tmpreg; \
988 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
989 /* Delay after an RCC peripheral clock enabling */ \
990 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
991 UNUSED(tmpreg); \
992 } while(0U)
993
994#define __HAL_RCC_UART4_CLK_ENABLE() do { \
995 __IO uint32_t tmpreg; \
996 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
997 /* Delay after an RCC peripheral clock enabling */ \
998 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
999 UNUSED(tmpreg); \
1000 } while(0U)
1001
1002#define __HAL_RCC_UART5_CLK_ENABLE() do { \
1003 __IO uint32_t tmpreg; \
1004 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1005 /* Delay after an RCC peripheral clock enabling */ \
1006 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1007 UNUSED(tmpreg); \
1008 } while(0U)
1009
1010#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
1011#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1012#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1013#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1014#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1015#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
1016#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
1017#endif /* STM32F100xE */
1018
1019#if defined(STM32F105xC) || defined(STM32F107xC)
1020#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
1021 __IO uint32_t tmpreg; \
1022 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1023 /* Delay after an RCC peripheral clock enabling */ \
1024 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1025 UNUSED(tmpreg); \
1026 } while(0U)
1027
1028#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1029#endif /* STM32F105xC || STM32F107xC */
1030
1031#if defined(STM32F101xG) || defined(STM32F103xG)
1032#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
1033 __IO uint32_t tmpreg; \
1034 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1035 /* Delay after an RCC peripheral clock enabling */ \
1036 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1037 UNUSED(tmpreg); \
1038 } while(0U)
1039
1040#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
1041 __IO uint32_t tmpreg; \
1042 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1043 /* Delay after an RCC peripheral clock enabling */ \
1044 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1045 UNUSED(tmpreg); \
1046 } while(0U)
1047
1048#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1049 __IO uint32_t tmpreg; \
1050 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1051 /* Delay after an RCC peripheral clock enabling */ \
1052 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1053 UNUSED(tmpreg); \
1054 } while(0U)
1055
1056#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1057#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1058#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1059#endif /* STM32F101xG || STM32F103xG*/
1060
1073#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
1074 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
1075#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
1076#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
1077#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1078#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
1079 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
1080 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
1081 || defined(STM32F105xC) || defined(STM32F107xC)
1082#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
1083#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
1084#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
1085#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
1086#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
1087#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
1088#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
1089#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
1090#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1091#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
1092 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
1093#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
1094#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
1095#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
1096#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
1097 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1098#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1099#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
1100#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1101#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1102#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1103#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1104#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1105#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1106#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1107#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1108#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1109#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1110#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1111#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1112#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
1113#if defined(STM32F100xB) || defined (STM32F100xE)
1114#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1115#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1116#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1117#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1118#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1119#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1120#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
1121#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
1122#endif /* STM32F100xB || STM32F100xE */
1123#ifdef STM32F100xE
1124#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1125#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
1126#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1127#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1128#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1129#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1130#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1131#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1132#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1133#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1134#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1135#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1136#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1137#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1138#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1139#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
1140#endif /* STM32F100xE */
1141#if defined(STM32F105xC) || defined(STM32F107xC)
1142#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1143#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1144#endif /* STM32F105xC || STM32F107xC */
1145#if defined(STM32F101xG) || defined(STM32F103xG)
1146#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1147#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1148#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1149#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1150#endif /* STM32F101xG || STM32F103xG*/
1151
1164#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
1165 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
1166 || defined(STM32F103xG)
1167#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
1168 __IO uint32_t tmpreg; \
1169 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1170 /* Delay after an RCC peripheral clock enabling */ \
1171 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1172 UNUSED(tmpreg); \
1173 } while(0U)
1174
1175#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
1176#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
1177
1178#if defined(STM32F100xB) || defined(STM32F100xE)
1179#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
1180 __IO uint32_t tmpreg; \
1181 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
1182 /* Delay after an RCC peripheral clock enabling */ \
1183 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
1184 UNUSED(tmpreg); \
1185 } while(0U)
1186
1187#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
1188 __IO uint32_t tmpreg; \
1189 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
1190 /* Delay after an RCC peripheral clock enabling */ \
1191 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
1192 UNUSED(tmpreg); \
1193 } while(0U)
1194
1195#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
1196 __IO uint32_t tmpreg; \
1197 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
1198 /* Delay after an RCC peripheral clock enabling */ \
1199 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
1200 UNUSED(tmpreg); \
1201 } while(0U)
1202
1203#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
1204#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
1205#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
1206#endif /* STM32F100xB || STM32F100xE */
1207
1208#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
1209 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
1210 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
1211 || defined(STM32F107xC)
1212#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
1213 __IO uint32_t tmpreg; \
1214 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
1215 /* Delay after an RCC peripheral clock enabling */ \
1216 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
1217 UNUSED(tmpreg); \
1218 } while(0U)
1219
1220#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
1221#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1222
1223#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
1224 || defined(STM32F103xG)
1225#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1226 __IO uint32_t tmpreg; \
1227 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1228 /* Delay after an RCC peripheral clock enabling */ \
1229 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1230 UNUSED(tmpreg); \
1231 } while(0U)
1232
1233#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1234 __IO uint32_t tmpreg; \
1235 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1236 /* Delay after an RCC peripheral clock enabling */ \
1237 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1238 UNUSED(tmpreg); \
1239 } while(0U)
1240
1241#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
1242#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
1243#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
1244
1245#if defined(STM32F103xE) || defined(STM32F103xG)
1246#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
1247 __IO uint32_t tmpreg; \
1248 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1249 /* Delay after an RCC peripheral clock enabling */ \
1250 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1251 UNUSED(tmpreg); \
1252 } while(0U)
1253
1254#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
1255 __IO uint32_t tmpreg; \
1256 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1257 /* Delay after an RCC peripheral clock enabling */ \
1258 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1259 UNUSED(tmpreg); \
1260 } while(0U)
1261
1262#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
1263#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
1264#endif /* STM32F103xE || STM32F103xG */
1265
1266#if defined(STM32F100xE)
1267#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1268 __IO uint32_t tmpreg; \
1269 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1270 /* Delay after an RCC peripheral clock enabling */ \
1271 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1272 UNUSED(tmpreg); \
1273 } while(0U)
1274
1275#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1276 __IO uint32_t tmpreg; \
1277 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1278 /* Delay after an RCC peripheral clock enabling */ \
1279 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1280 UNUSED(tmpreg); \
1281 } while(0U)
1282
1283#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
1284#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
1285#endif /* STM32F100xE */
1286
1287#if defined(STM32F101xG) || defined(STM32F103xG)
1288#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
1289 __IO uint32_t tmpreg; \
1290 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1291 /* Delay after an RCC peripheral clock enabling */ \
1292 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1293 UNUSED(tmpreg); \
1294 } while(0U)
1295
1296#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
1297 __IO uint32_t tmpreg; \
1298 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1299 /* Delay after an RCC peripheral clock enabling */ \
1300 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1301 UNUSED(tmpreg); \
1302 } while(0U)
1303
1304#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
1305 __IO uint32_t tmpreg; \
1306 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1307 /* Delay after an RCC peripheral clock enabling */ \
1308 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1309 UNUSED(tmpreg); \
1310 } while(0U)
1311
1312#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
1313#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1314#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
1315#endif /* STM32F101xG || STM32F103xG */
1316
1329#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
1330 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
1331 || defined(STM32F103xG)
1332#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
1333#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
1334#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
1335#if defined(STM32F100xB) || defined(STM32F100xE)
1336#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
1337#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
1338#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
1339#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
1340#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
1341#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
1342#endif /* STM32F100xB || STM32F100xE */
1343#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
1344 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
1345 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
1346 || defined(STM32F107xC)
1347#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
1348#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
1349#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1350#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
1351 || defined(STM32F103xG)
1352#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
1353#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
1354#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
1355#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
1356#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
1357#if defined(STM32F103xE) || defined(STM32F103xG)
1358#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
1359#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
1360#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
1361#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
1362#endif /* STM32F103xE || STM32F103xG */
1363#if defined(STM32F100xE)
1364#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
1365#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
1366#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
1367#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
1368#endif /* STM32F100xE */
1369#if defined(STM32F101xG) || defined(STM32F103xG)
1370#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
1371#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
1372#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
1373#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
1374#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
1375#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
1376#endif /* STM32F101xG || STM32F103xG */
1377
1382#if defined(STM32F105xC) || defined(STM32F107xC)
1387#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
1388#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
1389#if defined(STM32F107xC)
1390#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
1391#endif /* STM32F107xC */
1392
1393#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
1394#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
1395#if defined(STM32F107xC)
1396#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
1397#endif /* STM32F107xC */
1398
1402#endif /* STM32F105xC || STM32F107xC */
1403
1409#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
1410 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
1411#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
1412
1413#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
1414#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1415
1416#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
1417 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
1418 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
1419 || defined(STM32F105xC) || defined(STM32F107xC)
1420#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
1421#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
1422#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1423#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
1424
1425#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
1426#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
1427#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1428#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
1429#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1430
1431#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
1432 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
1433#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
1434#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
1435#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
1436
1437#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
1438 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1439#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
1440#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1441#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1442#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1443#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1444#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1445#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1446
1447#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
1448#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1449#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1450#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1451#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1452#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1453#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1454#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
1455
1456#if defined(STM32F100xB) || defined (STM32F100xE)
1457#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1458#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1459#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1460#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
1461
1462#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1463#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1464#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1465#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
1466#endif /* STM32F100xB || STM32F100xE */
1467
1468#if defined (STM32F100xE)
1469#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
1470#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1471#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1472#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1473#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1474#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1475#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1476
1477#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
1478#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1479#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1480#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1481#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1482#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1483#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1484#endif /* STM32F100xE */
1485
1486#if defined(STM32F105xC) || defined(STM32F107xC)
1487#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
1488
1489#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
1490#endif /* STM32F105xC || STM32F107xC */
1491
1492#if defined(STM32F101xG) || defined(STM32F103xG)
1493#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1494#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1495#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1496
1497#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1498#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1499#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1500#endif /* STM32F101xG || STM32F103xG */
1501
1511#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
1512 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
1513 || defined(STM32F103xG)
1514#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
1515
1516#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
1517#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
1518
1519#if defined(STM32F100xB) || defined(STM32F100xE)
1520#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
1521#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
1522#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
1523
1524#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
1525#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
1526#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
1527#endif /* STM32F100xB || STM32F100xE */
1528
1529#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
1530 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
1531 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
1532 || defined(STM32F107xC)
1533#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
1534
1535#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
1536#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1537
1538#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
1539 || defined(STM32F103xG)
1540#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
1541#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
1542
1543#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
1544#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
1545#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
1546
1547#if defined(STM32F103xE) || defined(STM32F103xG)
1548#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
1549#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
1550
1551#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
1552#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
1553#endif /* STM32F103xE || STM32F103xG */
1554
1555#if defined(STM32F100xE)
1556#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
1557#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
1558
1559#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
1560#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
1561#endif /* STM32F100xE */
1562
1563#if defined(STM32F101xG) || defined(STM32F103xG)
1564#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
1565#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
1566#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
1567
1568#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
1569#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
1570#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
1571#endif /* STM32F101xG || STM32F103xG*/
1572
1581#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
1582 || defined(STM32F100xE)
1591#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
1592#else
1601#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
1602 MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
1603
1604#endif /* STM32F105xC || STM32F107xC */
1605
1606#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
1607 || defined(STM32F100xE)
1611#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
1612
1613#else
1617#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
1618
1619#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
1620
1625#if defined(STM32F105xC) || defined(STM32F107xC)
1636#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
1637
1641#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
1642
1659#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
1660 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
1661
1666#endif /* STM32F105xC || STM32F107xC */
1667
1673#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
1674 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
1681#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
1682 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
1683
1689#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
1690
1691#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
1692
1693#if defined(STM32F105xC) || defined(STM32F107xC)
1694
1701#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
1702 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
1703
1709#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
1710
1711#endif /* STM32F105xC || STM32F107xC */
1712
1721#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
1722 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
1723
1731#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
1732
1737#if defined(STM32F105xC) || defined(STM32F107xC)
1738
1751#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
1752 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
1753
1757#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
1758
1773#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)
1774
1779#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)
1780
1797#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
1798 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
1799
1815#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
1816 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
1817
1823#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
1824
1831#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
1832 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
1833
1839#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
1840
1845#endif /* STM32F105xC || STM32F107xC */
1850/* Exported functions --------------------------------------------------------*/
1859HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1860void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1861uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
1862
1867#if defined(STM32F105xC) || defined(STM32F107xC)
1871HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
1872HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
1873
1881HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
1882HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
1883
1887#endif /* STM32F105xC || STM32F107xC */
1888
1901#ifdef __cplusplus
1902}
1903#endif
1904
1905#endif /* __STM32F1xx_HAL_RCC_EX_H */
1906
1907/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1908
stm32f1xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f1xx_hal_def.h:40
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition stm32f1xx_hal_rcc_ex.h:229
RCC_OscInitTypeDef::HSIState
uint32_t HSIState
Definition stm32f1xx_hal_rcc_ex.h:247
RCC_OscInitTypeDef::HSEPredivValue
uint32_t HSEPredivValue
Definition stm32f1xx_hal_rcc_ex.h:241
RCC_OscInitTypeDef::LSEState
uint32_t LSEState
Definition stm32f1xx_hal_rcc_ex.h:244
RCC_OscInitTypeDef::HSEState
uint32_t HSEState
Definition stm32f1xx_hal_rcc_ex.h:238
RCC_OscInitTypeDef::LSIState
uint32_t LSIState
Definition stm32f1xx_hal_rcc_ex.h:253
RCC_OscInitTypeDef::HSICalibrationValue
uint32_t HSICalibrationValue
Definition stm32f1xx_hal_rcc_ex.h:250
RCC_OscInitTypeDef::PLL
RCC_PLLInitTypeDef PLL
Definition stm32f1xx_hal_rcc_ex.h:256
RCC_OscInitTypeDef::OscillatorType
uint32_t OscillatorType
Definition stm32f1xx_hal_rcc_ex.h:230
RCC_PLL2InitTypeDef
PLL2 Clock structure definition.
Definition stm32h7xx_hal_rcc_ex.h:48
RCC_PLLI2SInitTypeDef
PLLI2S Clock structure definition
Definition stm32f2xx_hal_rcc_ex.h:47
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition stm32f1xx_hal_rcc.h:50
RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition stm32f1xx_hal_rcc_ex.h:284
RCC_PeriphCLKInitTypeDef::PeriphClockSelection
uint32_t PeriphClockSelection
Definition stm32f1xx_hal_rcc_ex.h:285
RCC_PeriphCLKInitTypeDef::AdcClockSelection
uint32_t AdcClockSelection
Definition stm32f1xx_hal_rcc_ex.h:291
RCC_PeriphCLKInitTypeDef::RTCClockSelection
uint32_t RTCClockSelection
Definition stm32f1xx_hal_rcc_ex.h:288