34#ifndef __STM32F207xx_H
35#define __STM32F207xx_H
48#define __CM3_REV 0x0200U
49#define __MPU_PRESENT 1U
50#define __NVIC_PRIO_BITS 4U
51#define __Vendor_SysTickConfig 0U
257 uint32_t RESERVED0[88];
260 uint32_t RESERVED1[12];
269 uint32_t RESERVED5[8];
293 __IO uint32_t SWTRIGR;
294 __IO uint32_t DHR12R1;
295 __IO uint32_t DHR12L1;
296 __IO uint32_t DHR8R1;
297 __IO uint32_t DHR12R2;
298 __IO uint32_t DHR12L2;
299 __IO uint32_t DHR8R2;
300 __IO uint32_t DHR12RD;
301 __IO uint32_t DHR12LD;
302 __IO uint32_t DHR8RD;
314 __IO uint32_t IDCODE;
369 __IO uint32_t MACFFR;
370 __IO uint32_t MACHTHR;
371 __IO uint32_t MACHTLR;
372 __IO uint32_t MACMIIAR;
373 __IO uint32_t MACMIIDR;
374 __IO uint32_t MACFCR;
375 __IO uint32_t MACVLANTR;
376 uint32_t RESERVED0[2];
377 __IO uint32_t MACRWUFFR;
378 __IO uint32_t MACPMTCSR;
380 __IO uint32_t MACDBGR;
382 __IO uint32_t MACIMR;
383 __IO uint32_t MACA0HR;
384 __IO uint32_t MACA0LR;
385 __IO uint32_t MACA1HR;
386 __IO uint32_t MACA1LR;
387 __IO uint32_t MACA2HR;
388 __IO uint32_t MACA2LR;
389 __IO uint32_t MACA3HR;
390 __IO uint32_t MACA3LR;
391 uint32_t RESERVED2[40];
393 __IO uint32_t MMCRIR;
394 __IO uint32_t MMCTIR;
395 __IO uint32_t MMCRIMR;
396 __IO uint32_t MMCTIMR;
397 uint32_t RESERVED3[14];
398 __IO uint32_t MMCTGFSCCR;
399 __IO uint32_t MMCTGFMSCCR;
400 uint32_t RESERVED4[5];
401 __IO uint32_t MMCTGFCR;
402 uint32_t RESERVED5[10];
403 __IO uint32_t MMCRFCECR;
404 __IO uint32_t MMCRFAECR;
405 uint32_t RESERVED6[10];
406 __IO uint32_t MMCRGUFCR;
407 uint32_t RESERVED7[334];
408 __IO uint32_t PTPTSCR;
409 __IO uint32_t PTPSSIR;
410 __IO uint32_t PTPTSHR;
411 __IO uint32_t PTPTSLR;
412 __IO uint32_t PTPTSHUR;
413 __IO uint32_t PTPTSLUR;
414 __IO uint32_t PTPTSAR;
415 __IO uint32_t PTPTTHR;
416 __IO uint32_t PTPTTLR;
417 __IO uint32_t RESERVED8;
418 __IO uint32_t PTPTSSR;
419 uint32_t RESERVED9[565];
420 __IO uint32_t DMABMR;
421 __IO uint32_t DMATPDR;
422 __IO uint32_t DMARPDR;
423 __IO uint32_t DMARDLAR;
424 __IO uint32_t DMATDLAR;
426 __IO uint32_t DMAOMR;
427 __IO uint32_t DMAIER;
428 __IO uint32_t DMAMFBOCR;
429 __IO uint32_t DMARSWTR;
430 uint32_t RESERVED10[8];
431 __IO uint32_t DMACHTDR;
432 __IO uint32_t DMACHRDR;
433 __IO uint32_t DMACHTBAR;
434 __IO uint32_t DMACHRBAR;
459 __IO uint32_t OPTKEYR;
546 uint32_t RESERVED[2];
603 __IO uint32_t APB1RSTR;
604 __IO uint32_t APB2RSTR;
605 uint32_t RESERVED1[2];
610 __IO uint32_t APB1ENR;
611 __IO uint32_t APB2ENR;
612 uint32_t RESERVED3[2];
619 uint32_t RESERVED5[2];
622 uint32_t RESERVED6[2];
699 uint32_t RESERVED0[2];
701 uint32_t RESERVED1[13];
716 __IO uint32_t RXCRCR;
717 __IO uint32_t TXCRCR;
718 __IO uint32_t I2SCFGR;
795 __IO uint32_t GOTGCTL;
796 __IO uint32_t GOTGINT;
797 __IO uint32_t GAHBCFG;
798 __IO uint32_t GUSBCFG;
799 __IO uint32_t GRSTCTL;
800 __IO uint32_t GINTSTS;
801 __IO uint32_t GINTMSK;
802 __IO uint32_t GRXSTSR;
803 __IO uint32_t GRXSTSP;
804 __IO uint32_t GRXFSIZ;
805 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
806 __IO uint32_t HNPTXSTS;
807 uint32_t Reserved30[2];
810 uint32_t Reserved40[48];
811 __IO uint32_t HPTXFSIZ;
812 __IO uint32_t DIEPTXF[0x0F];
827 __IO uint32_t DIEPMSK;
828 __IO uint32_t DOEPMSK;
830 __IO uint32_t DAINTMSK;
833 __IO uint32_t DVBUSDIS;
834 __IO uint32_t DVBUSPULSE;
835 __IO uint32_t DTHRCTL;
836 __IO uint32_t DIEPEMPMSK;
837 __IO uint32_t DEACHINT;
838 __IO uint32_t DEACHMSK;
840 __IO uint32_t DINEP1MSK;
841 uint32_t Reserved44[15];
842 __IO uint32_t DOUTEP1MSK;
852 __IO uint32_t DIEPCTL;
854 __IO uint32_t DIEPINT;
856 __IO uint32_t DIEPTSIZ;
857 __IO uint32_t DIEPDMA;
858 __IO uint32_t DTXFSTS;
869 __IO uint32_t DOEPCTL;
871 __IO uint32_t DOEPINT;
873 __IO uint32_t DOEPTSIZ;
874 __IO uint32_t DOEPDMA;
875 uint32_t Reserved18[2];
888 uint32_t Reserved40C;
889 __IO uint32_t HPTXSTS;
891 __IO uint32_t HAINTMSK;
901 __IO uint32_t HCCHAR;
902 __IO uint32_t HCSPLT;
904 __IO uint32_t HCINTMSK;
905 __IO uint32_t HCTSIZ;
907 uint32_t Reserved[2];
915#define FLASH_BASE 0x08000000UL
916#define SRAM1_BASE 0x20000000UL
917#define SRAM2_BASE 0x2001C000UL
918#define PERIPH_BASE 0x40000000UL
919#define BKPSRAM_BASE 0x40024000UL
920#define FSMC_R_BASE 0xA0000000UL
921#define SRAM1_BB_BASE 0x22000000UL
922#define SRAM2_BB_BASE 0x22380000UL
923#define PERIPH_BB_BASE 0x42000000UL
924#define BKPSRAM_BB_BASE 0x42480000UL
925#define FLASH_END 0x080FFFFFUL
926#define FLASH_OTP_BASE 0x1FFF7800UL
927#define FLASH_OTP_END 0x1FFF7A0FUL
930#define SRAM_BASE SRAM1_BASE
931#define SRAM_BB_BASE SRAM1_BB_BASE
935#define APB1PERIPH_BASE PERIPH_BASE
936#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
937#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
938#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
941#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
942#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
943#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
944#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
945#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
946#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
947#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
948#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
949#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
950#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
951#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
952#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
953#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
954#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
955#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
956#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
957#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
958#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
959#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
960#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
961#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
962#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
963#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
964#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
965#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
968#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
969#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
970#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
971#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
972#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
973#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
974#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
975#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
977#define ADC_BASE ADC123_COMMON_BASE
979#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
980#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
981#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
982#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
983#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
984#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
985#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
988#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
989#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
990#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
991#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
992#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
993#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
994#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
995#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
996#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
997#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
998#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
999#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1000#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1001#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1002#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1003#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1004#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1005#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1006#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1007#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1008#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1009#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1010#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1011#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1012#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1013#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1014#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1015#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1016#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1017#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1018#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
1019#define ETH_MAC_BASE (ETH_BASE)
1020#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
1021#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
1022#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
1025#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1026#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1029#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)
1030#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)
1031#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL)
1032#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL)
1035#define DBGMCU_BASE 0xE0042000UL
1038#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1039#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1041#define USB_OTG_GLOBAL_BASE 0x000UL
1042#define USB_OTG_DEVICE_BASE 0x800UL
1043#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
1044#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
1045#define USB_OTG_EP_REG_SIZE 0x20UL
1046#define USB_OTG_HOST_BASE 0x400UL
1047#define USB_OTG_HOST_PORT_BASE 0x440UL
1048#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
1049#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
1050#define USB_OTG_PCGCCTL_BASE 0xE00UL
1051#define USB_OTG_FIFO_BASE 0x1000UL
1052#define USB_OTG_FIFO_SIZE 0x1000UL
1055#define UID_BASE 0x1FFF7A10UL
1056#define FLASHSIZE_BASE 0x1FFF7A22UL
1065#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1066#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1067#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1068#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1069#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1070#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1071#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1072#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1073#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1074#define RTC ((RTC_TypeDef *) RTC_BASE)
1075#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1076#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1077#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1078#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1079#define USART2 ((USART_TypeDef *) USART2_BASE)
1080#define USART3 ((USART_TypeDef *) USART3_BASE)
1081#define UART4 ((USART_TypeDef *) UART4_BASE)
1082#define UART5 ((USART_TypeDef *) UART5_BASE)
1083#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1084#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1085#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1086#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1087#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1088#define PWR ((PWR_TypeDef *) PWR_BASE)
1089#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1090#define DAC ((DAC_TypeDef *) DAC_BASE)
1091#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1092#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1093#define USART1 ((USART_TypeDef *) USART1_BASE)
1094#define USART6 ((USART_TypeDef *) USART6_BASE)
1095#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1096#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1097#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1098#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1100#define ADC ADC123_COMMON
1101#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1102#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1103#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1104#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1105#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1106#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1107#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1108#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1109#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1110#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1111#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1112#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1113#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1114#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1115#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1116#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1117#define CRC ((CRC_TypeDef *) CRC_BASE)
1118#define RCC ((RCC_TypeDef *) RCC_BASE)
1119#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1120#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1121#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1122#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1123#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1124#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1125#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1126#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1127#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1128#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1129#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1130#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1131#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1132#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1133#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1134#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1135#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1136#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1137#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1138#define ETH ((ETH_TypeDef *) ETH_BASE)
1139#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1140#define RNG ((RNG_TypeDef *) RNG_BASE)
1141#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1142#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1143#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1144#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1146#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1148#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1149#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1162#define LSI_STARTUP_TIME 40U
1181#define ADC_SR_AWD_Pos (0U)
1182#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1183#define ADC_SR_AWD ADC_SR_AWD_Msk
1184#define ADC_SR_EOC_Pos (1U)
1185#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1186#define ADC_SR_EOC ADC_SR_EOC_Msk
1187#define ADC_SR_JEOC_Pos (2U)
1188#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1189#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1190#define ADC_SR_JSTRT_Pos (3U)
1191#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1192#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1193#define ADC_SR_STRT_Pos (4U)
1194#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1195#define ADC_SR_STRT ADC_SR_STRT_Msk
1196#define ADC_SR_OVR_Pos (5U)
1197#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1198#define ADC_SR_OVR ADC_SR_OVR_Msk
1201#define ADC_CR1_AWDCH_Pos (0U)
1202#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1203#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1204#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1205#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1206#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1207#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1208#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1209#define ADC_CR1_EOCIE_Pos (5U)
1210#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1211#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1212#define ADC_CR1_AWDIE_Pos (6U)
1213#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1214#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1215#define ADC_CR1_JEOCIE_Pos (7U)
1216#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1217#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1218#define ADC_CR1_SCAN_Pos (8U)
1219#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1220#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1221#define ADC_CR1_AWDSGL_Pos (9U)
1222#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1223#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1224#define ADC_CR1_JAUTO_Pos (10U)
1225#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1226#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1227#define ADC_CR1_DISCEN_Pos (11U)
1228#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1229#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1230#define ADC_CR1_JDISCEN_Pos (12U)
1231#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1232#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1233#define ADC_CR1_DISCNUM_Pos (13U)
1234#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1235#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1236#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1237#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1238#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1239#define ADC_CR1_JAWDEN_Pos (22U)
1240#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1241#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1242#define ADC_CR1_AWDEN_Pos (23U)
1243#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1244#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1245#define ADC_CR1_RES_Pos (24U)
1246#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1247#define ADC_CR1_RES ADC_CR1_RES_Msk
1248#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1249#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1250#define ADC_CR1_OVRIE_Pos (26U)
1251#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1252#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1255#define ADC_CR2_ADON_Pos (0U)
1256#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1257#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1258#define ADC_CR2_CONT_Pos (1U)
1259#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1260#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1261#define ADC_CR2_DMA_Pos (8U)
1262#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1263#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1264#define ADC_CR2_DDS_Pos (9U)
1265#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1266#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1267#define ADC_CR2_EOCS_Pos (10U)
1268#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1269#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1270#define ADC_CR2_ALIGN_Pos (11U)
1271#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1272#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1273#define ADC_CR2_JEXTSEL_Pos (16U)
1274#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1275#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1276#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1277#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1278#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1279#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1280#define ADC_CR2_JEXTEN_Pos (20U)
1281#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1282#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1283#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1284#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1285#define ADC_CR2_JSWSTART_Pos (22U)
1286#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1287#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1288#define ADC_CR2_EXTSEL_Pos (24U)
1289#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1290#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1291#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1292#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1293#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1294#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1295#define ADC_CR2_EXTEN_Pos (28U)
1296#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1297#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1298#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1299#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1300#define ADC_CR2_SWSTART_Pos (30U)
1301#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1302#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1305#define ADC_SMPR1_SMP10_Pos (0U)
1306#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1307#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1308#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1309#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1310#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1311#define ADC_SMPR1_SMP11_Pos (3U)
1312#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1313#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1314#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1315#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1316#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1317#define ADC_SMPR1_SMP12_Pos (6U)
1318#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1319#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1320#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1321#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1322#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1323#define ADC_SMPR1_SMP13_Pos (9U)
1324#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1325#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1326#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1327#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1328#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1329#define ADC_SMPR1_SMP14_Pos (12U)
1330#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1331#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1332#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1333#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1334#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1335#define ADC_SMPR1_SMP15_Pos (15U)
1336#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1337#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1338#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1339#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1340#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1341#define ADC_SMPR1_SMP16_Pos (18U)
1342#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1343#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1344#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1345#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1346#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1347#define ADC_SMPR1_SMP17_Pos (21U)
1348#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1349#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1350#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1351#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1352#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1353#define ADC_SMPR1_SMP18_Pos (24U)
1354#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1355#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1356#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1357#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1358#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1361#define ADC_SMPR2_SMP0_Pos (0U)
1362#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1363#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1364#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1365#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1366#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1367#define ADC_SMPR2_SMP1_Pos (3U)
1368#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1369#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1370#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1371#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1372#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1373#define ADC_SMPR2_SMP2_Pos (6U)
1374#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1375#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1376#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1377#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1378#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1379#define ADC_SMPR2_SMP3_Pos (9U)
1380#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1381#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1382#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1383#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1384#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1385#define ADC_SMPR2_SMP4_Pos (12U)
1386#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1387#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1388#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1389#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1390#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1391#define ADC_SMPR2_SMP5_Pos (15U)
1392#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1393#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1394#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1395#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1396#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1397#define ADC_SMPR2_SMP6_Pos (18U)
1398#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1399#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1400#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1401#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1402#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1403#define ADC_SMPR2_SMP7_Pos (21U)
1404#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1405#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1406#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1407#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1408#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1409#define ADC_SMPR2_SMP8_Pos (24U)
1410#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1411#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1412#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1413#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1414#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1415#define ADC_SMPR2_SMP9_Pos (27U)
1416#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1417#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1418#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1419#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1420#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1423#define ADC_JOFR1_JOFFSET1_Pos (0U)
1424#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1425#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1428#define ADC_JOFR2_JOFFSET2_Pos (0U)
1429#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1430#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1433#define ADC_JOFR3_JOFFSET3_Pos (0U)
1434#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1435#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1438#define ADC_JOFR4_JOFFSET4_Pos (0U)
1439#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1440#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1443#define ADC_HTR_HT_Pos (0U)
1444#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1445#define ADC_HTR_HT ADC_HTR_HT_Msk
1448#define ADC_LTR_LT_Pos (0U)
1449#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1450#define ADC_LTR_LT ADC_LTR_LT_Msk
1453#define ADC_SQR1_SQ13_Pos (0U)
1454#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1455#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1456#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1457#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1458#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1459#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1460#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1461#define ADC_SQR1_SQ14_Pos (5U)
1462#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1463#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1464#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1465#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1466#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1467#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1468#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1469#define ADC_SQR1_SQ15_Pos (10U)
1470#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1471#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1472#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1473#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1474#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1475#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1476#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1477#define ADC_SQR1_SQ16_Pos (15U)
1478#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1479#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1480#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1481#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1482#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1483#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1484#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1485#define ADC_SQR1_L_Pos (20U)
1486#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1487#define ADC_SQR1_L ADC_SQR1_L_Msk
1488#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1489#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1490#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1491#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1494#define ADC_SQR2_SQ7_Pos (0U)
1495#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1496#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1497#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1498#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1499#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1500#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1501#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1502#define ADC_SQR2_SQ8_Pos (5U)
1503#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1504#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1505#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1506#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1507#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1508#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1509#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1510#define ADC_SQR2_SQ9_Pos (10U)
1511#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1512#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1513#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1514#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1515#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1516#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1517#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1518#define ADC_SQR2_SQ10_Pos (15U)
1519#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1520#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1521#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1522#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1523#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1524#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1525#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1526#define ADC_SQR2_SQ11_Pos (20U)
1527#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1528#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1529#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1530#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1531#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1532#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1533#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1534#define ADC_SQR2_SQ12_Pos (25U)
1535#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1536#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1537#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1538#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1539#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1540#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1541#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1544#define ADC_SQR3_SQ1_Pos (0U)
1545#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1546#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1547#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1548#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1549#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1550#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1551#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1552#define ADC_SQR3_SQ2_Pos (5U)
1553#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1554#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1555#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1556#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1557#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1558#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1559#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1560#define ADC_SQR3_SQ3_Pos (10U)
1561#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1562#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1563#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1564#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1565#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1566#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1567#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1568#define ADC_SQR3_SQ4_Pos (15U)
1569#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1570#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1571#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1572#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1573#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1574#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1575#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1576#define ADC_SQR3_SQ5_Pos (20U)
1577#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1578#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1579#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1580#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1581#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1582#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1583#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1584#define ADC_SQR3_SQ6_Pos (25U)
1585#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1586#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1587#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1588#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1589#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1590#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1591#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1594#define ADC_JSQR_JSQ1_Pos (0U)
1595#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1596#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1597#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1598#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1599#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1600#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1601#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1602#define ADC_JSQR_JSQ2_Pos (5U)
1603#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1604#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1605#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1606#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1607#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1608#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1609#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1610#define ADC_JSQR_JSQ3_Pos (10U)
1611#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1612#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1613#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1614#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1615#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1616#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1617#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1618#define ADC_JSQR_JSQ4_Pos (15U)
1619#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1620#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1621#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1622#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1623#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1624#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1625#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1626#define ADC_JSQR_JL_Pos (20U)
1627#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1628#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1629#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1630#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1633#define ADC_JDR1_JDATA_Pos (0U)
1634#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1635#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1638#define ADC_JDR2_JDATA_Pos (0U)
1639#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1640#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1643#define ADC_JDR3_JDATA_Pos (0U)
1644#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1645#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1648#define ADC_JDR4_JDATA_Pos (0U)
1649#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1650#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1653#define ADC_DR_DATA_Pos (0U)
1654#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1655#define ADC_DR_DATA ADC_DR_DATA_Msk
1656#define ADC_DR_ADC2DATA_Pos (16U)
1657#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1658#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1661#define ADC_CSR_AWD1_Pos (0U)
1662#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1663#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1664#define ADC_CSR_EOC1_Pos (1U)
1665#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1666#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1667#define ADC_CSR_JEOC1_Pos (2U)
1668#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1669#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1670#define ADC_CSR_JSTRT1_Pos (3U)
1671#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1672#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1673#define ADC_CSR_STRT1_Pos (4U)
1674#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1675#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1676#define ADC_CSR_OVR1_Pos (5U)
1677#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1678#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1679#define ADC_CSR_AWD2_Pos (8U)
1680#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1681#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1682#define ADC_CSR_EOC2_Pos (9U)
1683#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1684#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1685#define ADC_CSR_JEOC2_Pos (10U)
1686#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1687#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
1688#define ADC_CSR_JSTRT2_Pos (11U)
1689#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
1690#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
1691#define ADC_CSR_STRT2_Pos (12U)
1692#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
1693#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
1694#define ADC_CSR_OVR2_Pos (13U)
1695#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
1696#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
1697#define ADC_CSR_AWD3_Pos (16U)
1698#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
1699#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
1700#define ADC_CSR_EOC3_Pos (17U)
1701#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
1702#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
1703#define ADC_CSR_JEOC3_Pos (18U)
1704#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
1705#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
1706#define ADC_CSR_JSTRT3_Pos (19U)
1707#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
1708#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
1709#define ADC_CSR_STRT3_Pos (20U)
1710#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
1711#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
1712#define ADC_CSR_OVR3_Pos (21U)
1713#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
1714#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
1717#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1718#define ADC_CSR_DOVR2 ADC_CSR_OVR2
1719#define ADC_CSR_DOVR3 ADC_CSR_OVR3
1722#define ADC_CCR_MULTI_Pos (0U)
1723#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1724#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1725#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1726#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1727#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1728#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1729#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1730#define ADC_CCR_DELAY_Pos (8U)
1731#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1732#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1733#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1734#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1735#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1736#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1737#define ADC_CCR_DDS_Pos (13U)
1738#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1739#define ADC_CCR_DDS ADC_CCR_DDS_Msk
1740#define ADC_CCR_DMA_Pos (14U)
1741#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1742#define ADC_CCR_DMA ADC_CCR_DMA_Msk
1743#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1744#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1745#define ADC_CCR_ADCPRE_Pos (16U)
1746#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1747#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1748#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1749#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1750#define ADC_CCR_VBATE_Pos (22U)
1751#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1752#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1753#define ADC_CCR_TSVREFE_Pos (23U)
1754#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1755#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1758#define ADC_CDR_DATA1_Pos (0U)
1759#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1760#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1761#define ADC_CDR_DATA2_Pos (16U)
1762#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1763#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1766#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1767#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1776#define CAN_MCR_INRQ_Pos (0U)
1777#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1778#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1779#define CAN_MCR_SLEEP_Pos (1U)
1780#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1781#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1782#define CAN_MCR_TXFP_Pos (2U)
1783#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1784#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1785#define CAN_MCR_RFLM_Pos (3U)
1786#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1787#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1788#define CAN_MCR_NART_Pos (4U)
1789#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1790#define CAN_MCR_NART CAN_MCR_NART_Msk
1791#define CAN_MCR_AWUM_Pos (5U)
1792#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1793#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1794#define CAN_MCR_ABOM_Pos (6U)
1795#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1796#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1797#define CAN_MCR_TTCM_Pos (7U)
1798#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1799#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1800#define CAN_MCR_RESET_Pos (15U)
1801#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1802#define CAN_MCR_RESET CAN_MCR_RESET_Msk
1803#define CAN_MCR_DBF_Pos (16U)
1804#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
1805#define CAN_MCR_DBF CAN_MCR_DBF_Msk
1807#define CAN_MSR_INAK_Pos (0U)
1808#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1809#define CAN_MSR_INAK CAN_MSR_INAK_Msk
1810#define CAN_MSR_SLAK_Pos (1U)
1811#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
1812#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
1813#define CAN_MSR_ERRI_Pos (2U)
1814#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
1815#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
1816#define CAN_MSR_WKUI_Pos (3U)
1817#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
1818#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
1819#define CAN_MSR_SLAKI_Pos (4U)
1820#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
1821#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
1822#define CAN_MSR_TXM_Pos (8U)
1823#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
1824#define CAN_MSR_TXM CAN_MSR_TXM_Msk
1825#define CAN_MSR_RXM_Pos (9U)
1826#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
1827#define CAN_MSR_RXM CAN_MSR_RXM_Msk
1828#define CAN_MSR_SAMP_Pos (10U)
1829#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
1830#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
1831#define CAN_MSR_RX_Pos (11U)
1832#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
1833#define CAN_MSR_RX CAN_MSR_RX_Msk
1836#define CAN_TSR_RQCP0_Pos (0U)
1837#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
1838#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
1839#define CAN_TSR_TXOK0_Pos (1U)
1840#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
1841#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
1842#define CAN_TSR_ALST0_Pos (2U)
1843#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
1844#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
1845#define CAN_TSR_TERR0_Pos (3U)
1846#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
1847#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
1848#define CAN_TSR_ABRQ0_Pos (7U)
1849#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
1850#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
1851#define CAN_TSR_RQCP1_Pos (8U)
1852#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
1853#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
1854#define CAN_TSR_TXOK1_Pos (9U)
1855#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
1856#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
1857#define CAN_TSR_ALST1_Pos (10U)
1858#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
1859#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
1860#define CAN_TSR_TERR1_Pos (11U)
1861#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
1862#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
1863#define CAN_TSR_ABRQ1_Pos (15U)
1864#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
1865#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
1866#define CAN_TSR_RQCP2_Pos (16U)
1867#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
1868#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
1869#define CAN_TSR_TXOK2_Pos (17U)
1870#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
1871#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
1872#define CAN_TSR_ALST2_Pos (18U)
1873#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
1874#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
1875#define CAN_TSR_TERR2_Pos (19U)
1876#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
1877#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
1878#define CAN_TSR_ABRQ2_Pos (23U)
1879#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
1880#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
1881#define CAN_TSR_CODE_Pos (24U)
1882#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
1883#define CAN_TSR_CODE CAN_TSR_CODE_Msk
1885#define CAN_TSR_TME_Pos (26U)
1886#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
1887#define CAN_TSR_TME CAN_TSR_TME_Msk
1888#define CAN_TSR_TME0_Pos (26U)
1889#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
1890#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
1891#define CAN_TSR_TME1_Pos (27U)
1892#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
1893#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
1894#define CAN_TSR_TME2_Pos (28U)
1895#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
1896#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
1898#define CAN_TSR_LOW_Pos (29U)
1899#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
1900#define CAN_TSR_LOW CAN_TSR_LOW_Msk
1901#define CAN_TSR_LOW0_Pos (29U)
1902#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
1903#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
1904#define CAN_TSR_LOW1_Pos (30U)
1905#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
1906#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
1907#define CAN_TSR_LOW2_Pos (31U)
1908#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
1909#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
1912#define CAN_RF0R_FMP0_Pos (0U)
1913#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
1914#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
1915#define CAN_RF0R_FULL0_Pos (3U)
1916#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
1917#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
1918#define CAN_RF0R_FOVR0_Pos (4U)
1919#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
1920#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
1921#define CAN_RF0R_RFOM0_Pos (5U)
1922#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
1923#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
1926#define CAN_RF1R_FMP1_Pos (0U)
1927#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
1928#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
1929#define CAN_RF1R_FULL1_Pos (3U)
1930#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
1931#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
1932#define CAN_RF1R_FOVR1_Pos (4U)
1933#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
1934#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
1935#define CAN_RF1R_RFOM1_Pos (5U)
1936#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
1937#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
1940#define CAN_IER_TMEIE_Pos (0U)
1941#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
1942#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
1943#define CAN_IER_FMPIE0_Pos (1U)
1944#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
1945#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
1946#define CAN_IER_FFIE0_Pos (2U)
1947#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
1948#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
1949#define CAN_IER_FOVIE0_Pos (3U)
1950#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
1951#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
1952#define CAN_IER_FMPIE1_Pos (4U)
1953#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
1954#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
1955#define CAN_IER_FFIE1_Pos (5U)
1956#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
1957#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
1958#define CAN_IER_FOVIE1_Pos (6U)
1959#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
1960#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
1961#define CAN_IER_EWGIE_Pos (8U)
1962#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
1963#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
1964#define CAN_IER_EPVIE_Pos (9U)
1965#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
1966#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
1967#define CAN_IER_BOFIE_Pos (10U)
1968#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
1969#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
1970#define CAN_IER_LECIE_Pos (11U)
1971#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
1972#define CAN_IER_LECIE CAN_IER_LECIE_Msk
1973#define CAN_IER_ERRIE_Pos (15U)
1974#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
1975#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
1976#define CAN_IER_WKUIE_Pos (16U)
1977#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
1978#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
1979#define CAN_IER_SLKIE_Pos (17U)
1980#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
1981#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
1984#define CAN_ESR_EWGF_Pos (0U)
1985#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
1986#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
1987#define CAN_ESR_EPVF_Pos (1U)
1988#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
1989#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
1990#define CAN_ESR_BOFF_Pos (2U)
1991#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
1992#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
1994#define CAN_ESR_LEC_Pos (4U)
1995#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
1996#define CAN_ESR_LEC CAN_ESR_LEC_Msk
1997#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
1998#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
1999#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2001#define CAN_ESR_TEC_Pos (16U)
2002#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2003#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2004#define CAN_ESR_REC_Pos (24U)
2005#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2006#define CAN_ESR_REC CAN_ESR_REC_Msk
2009#define CAN_BTR_BRP_Pos (0U)
2010#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2011#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2012#define CAN_BTR_TS1_Pos (16U)
2013#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2014#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2015#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2016#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2017#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2018#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2019#define CAN_BTR_TS2_Pos (20U)
2020#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2021#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2022#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2023#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2024#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2025#define CAN_BTR_SJW_Pos (24U)
2026#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2027#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2028#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2029#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2030#define CAN_BTR_LBKM_Pos (30U)
2031#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2032#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2033#define CAN_BTR_SILM_Pos (31U)
2034#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2035#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2040#define CAN_TI0R_TXRQ_Pos (0U)
2041#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2042#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2043#define CAN_TI0R_RTR_Pos (1U)
2044#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2045#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2046#define CAN_TI0R_IDE_Pos (2U)
2047#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2048#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2049#define CAN_TI0R_EXID_Pos (3U)
2050#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2051#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2052#define CAN_TI0R_STID_Pos (21U)
2053#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2054#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2057#define CAN_TDT0R_DLC_Pos (0U)
2058#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2059#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2060#define CAN_TDT0R_TGT_Pos (8U)
2061#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2062#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2063#define CAN_TDT0R_TIME_Pos (16U)
2064#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2065#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2068#define CAN_TDL0R_DATA0_Pos (0U)
2069#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2070#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2071#define CAN_TDL0R_DATA1_Pos (8U)
2072#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2073#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2074#define CAN_TDL0R_DATA2_Pos (16U)
2075#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2076#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2077#define CAN_TDL0R_DATA3_Pos (24U)
2078#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2079#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2082#define CAN_TDH0R_DATA4_Pos (0U)
2083#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2084#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2085#define CAN_TDH0R_DATA5_Pos (8U)
2086#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2087#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2088#define CAN_TDH0R_DATA6_Pos (16U)
2089#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2090#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2091#define CAN_TDH0R_DATA7_Pos (24U)
2092#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2093#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2096#define CAN_TI1R_TXRQ_Pos (0U)
2097#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2098#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2099#define CAN_TI1R_RTR_Pos (1U)
2100#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2101#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2102#define CAN_TI1R_IDE_Pos (2U)
2103#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2104#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2105#define CAN_TI1R_EXID_Pos (3U)
2106#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2107#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2108#define CAN_TI1R_STID_Pos (21U)
2109#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2110#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2113#define CAN_TDT1R_DLC_Pos (0U)
2114#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2115#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2116#define CAN_TDT1R_TGT_Pos (8U)
2117#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2118#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2119#define CAN_TDT1R_TIME_Pos (16U)
2120#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2121#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2124#define CAN_TDL1R_DATA0_Pos (0U)
2125#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2126#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2127#define CAN_TDL1R_DATA1_Pos (8U)
2128#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2129#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2130#define CAN_TDL1R_DATA2_Pos (16U)
2131#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2132#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2133#define CAN_TDL1R_DATA3_Pos (24U)
2134#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2135#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2138#define CAN_TDH1R_DATA4_Pos (0U)
2139#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2140#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2141#define CAN_TDH1R_DATA5_Pos (8U)
2142#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2143#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2144#define CAN_TDH1R_DATA6_Pos (16U)
2145#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2146#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2147#define CAN_TDH1R_DATA7_Pos (24U)
2148#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2149#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2152#define CAN_TI2R_TXRQ_Pos (0U)
2153#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2154#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2155#define CAN_TI2R_RTR_Pos (1U)
2156#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2157#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2158#define CAN_TI2R_IDE_Pos (2U)
2159#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2160#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2161#define CAN_TI2R_EXID_Pos (3U)
2162#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2163#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2164#define CAN_TI2R_STID_Pos (21U)
2165#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2166#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2169#define CAN_TDT2R_DLC_Pos (0U)
2170#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2171#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2172#define CAN_TDT2R_TGT_Pos (8U)
2173#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2174#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2175#define CAN_TDT2R_TIME_Pos (16U)
2176#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2177#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2180#define CAN_TDL2R_DATA0_Pos (0U)
2181#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2182#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2183#define CAN_TDL2R_DATA1_Pos (8U)
2184#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2185#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2186#define CAN_TDL2R_DATA2_Pos (16U)
2187#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2188#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2189#define CAN_TDL2R_DATA3_Pos (24U)
2190#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2191#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2194#define CAN_TDH2R_DATA4_Pos (0U)
2195#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2196#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2197#define CAN_TDH2R_DATA5_Pos (8U)
2198#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2199#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2200#define CAN_TDH2R_DATA6_Pos (16U)
2201#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2202#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2203#define CAN_TDH2R_DATA7_Pos (24U)
2204#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2205#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2208#define CAN_RI0R_RTR_Pos (1U)
2209#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2210#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2211#define CAN_RI0R_IDE_Pos (2U)
2212#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2213#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2214#define CAN_RI0R_EXID_Pos (3U)
2215#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2216#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2217#define CAN_RI0R_STID_Pos (21U)
2218#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2219#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2222#define CAN_RDT0R_DLC_Pos (0U)
2223#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2224#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2225#define CAN_RDT0R_FMI_Pos (8U)
2226#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2227#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2228#define CAN_RDT0R_TIME_Pos (16U)
2229#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2230#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2233#define CAN_RDL0R_DATA0_Pos (0U)
2234#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2235#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2236#define CAN_RDL0R_DATA1_Pos (8U)
2237#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2238#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2239#define CAN_RDL0R_DATA2_Pos (16U)
2240#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2241#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2242#define CAN_RDL0R_DATA3_Pos (24U)
2243#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2244#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2247#define CAN_RDH0R_DATA4_Pos (0U)
2248#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2249#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2250#define CAN_RDH0R_DATA5_Pos (8U)
2251#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2252#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2253#define CAN_RDH0R_DATA6_Pos (16U)
2254#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2255#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2256#define CAN_RDH0R_DATA7_Pos (24U)
2257#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2258#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2261#define CAN_RI1R_RTR_Pos (1U)
2262#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2263#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2264#define CAN_RI1R_IDE_Pos (2U)
2265#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2266#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2267#define CAN_RI1R_EXID_Pos (3U)
2268#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2269#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2270#define CAN_RI1R_STID_Pos (21U)
2271#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2272#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2275#define CAN_RDT1R_DLC_Pos (0U)
2276#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2277#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2278#define CAN_RDT1R_FMI_Pos (8U)
2279#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2280#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2281#define CAN_RDT1R_TIME_Pos (16U)
2282#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2283#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2286#define CAN_RDL1R_DATA0_Pos (0U)
2287#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2288#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2289#define CAN_RDL1R_DATA1_Pos (8U)
2290#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2291#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2292#define CAN_RDL1R_DATA2_Pos (16U)
2293#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2294#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2295#define CAN_RDL1R_DATA3_Pos (24U)
2296#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2297#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2300#define CAN_RDH1R_DATA4_Pos (0U)
2301#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2302#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2303#define CAN_RDH1R_DATA5_Pos (8U)
2304#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2305#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2306#define CAN_RDH1R_DATA6_Pos (16U)
2307#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2308#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2309#define CAN_RDH1R_DATA7_Pos (24U)
2310#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2311#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2315#define CAN_FMR_FINIT_Pos (0U)
2316#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2317#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2318#define CAN_FMR_CAN2SB_Pos (8U)
2319#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2320#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2323#define CAN_FM1R_FBM_Pos (0U)
2324#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2325#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2326#define CAN_FM1R_FBM0_Pos (0U)
2327#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2328#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2329#define CAN_FM1R_FBM1_Pos (1U)
2330#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2331#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2332#define CAN_FM1R_FBM2_Pos (2U)
2333#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2334#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2335#define CAN_FM1R_FBM3_Pos (3U)
2336#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2337#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2338#define CAN_FM1R_FBM4_Pos (4U)
2339#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2340#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2341#define CAN_FM1R_FBM5_Pos (5U)
2342#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2343#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2344#define CAN_FM1R_FBM6_Pos (6U)
2345#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2346#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2347#define CAN_FM1R_FBM7_Pos (7U)
2348#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2349#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2350#define CAN_FM1R_FBM8_Pos (8U)
2351#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2352#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2353#define CAN_FM1R_FBM9_Pos (9U)
2354#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2355#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2356#define CAN_FM1R_FBM10_Pos (10U)
2357#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2358#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2359#define CAN_FM1R_FBM11_Pos (11U)
2360#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2361#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2362#define CAN_FM1R_FBM12_Pos (12U)
2363#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2364#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2365#define CAN_FM1R_FBM13_Pos (13U)
2366#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2367#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2368#define CAN_FM1R_FBM14_Pos (14U)
2369#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2370#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2371#define CAN_FM1R_FBM15_Pos (15U)
2372#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2373#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2374#define CAN_FM1R_FBM16_Pos (16U)
2375#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2376#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2377#define CAN_FM1R_FBM17_Pos (17U)
2378#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2379#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2380#define CAN_FM1R_FBM18_Pos (18U)
2381#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2382#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2383#define CAN_FM1R_FBM19_Pos (19U)
2384#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2385#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2386#define CAN_FM1R_FBM20_Pos (20U)
2387#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2388#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2389#define CAN_FM1R_FBM21_Pos (21U)
2390#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2391#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2392#define CAN_FM1R_FBM22_Pos (22U)
2393#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2394#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2395#define CAN_FM1R_FBM23_Pos (23U)
2396#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2397#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2398#define CAN_FM1R_FBM24_Pos (24U)
2399#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2400#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2401#define CAN_FM1R_FBM25_Pos (25U)
2402#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2403#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2404#define CAN_FM1R_FBM26_Pos (26U)
2405#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2406#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2407#define CAN_FM1R_FBM27_Pos (27U)
2408#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2409#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2412#define CAN_FS1R_FSC_Pos (0U)
2413#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2414#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2415#define CAN_FS1R_FSC0_Pos (0U)
2416#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2417#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2418#define CAN_FS1R_FSC1_Pos (1U)
2419#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2420#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2421#define CAN_FS1R_FSC2_Pos (2U)
2422#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2423#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2424#define CAN_FS1R_FSC3_Pos (3U)
2425#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2426#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2427#define CAN_FS1R_FSC4_Pos (4U)
2428#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2429#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2430#define CAN_FS1R_FSC5_Pos (5U)
2431#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2432#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2433#define CAN_FS1R_FSC6_Pos (6U)
2434#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2435#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2436#define CAN_FS1R_FSC7_Pos (7U)
2437#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2438#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2439#define CAN_FS1R_FSC8_Pos (8U)
2440#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2441#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2442#define CAN_FS1R_FSC9_Pos (9U)
2443#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2444#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2445#define CAN_FS1R_FSC10_Pos (10U)
2446#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2447#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2448#define CAN_FS1R_FSC11_Pos (11U)
2449#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2450#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2451#define CAN_FS1R_FSC12_Pos (12U)
2452#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2453#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2454#define CAN_FS1R_FSC13_Pos (13U)
2455#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2456#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2457#define CAN_FS1R_FSC14_Pos (14U)
2458#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2459#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2460#define CAN_FS1R_FSC15_Pos (15U)
2461#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2462#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2463#define CAN_FS1R_FSC16_Pos (16U)
2464#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2465#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2466#define CAN_FS1R_FSC17_Pos (17U)
2467#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2468#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2469#define CAN_FS1R_FSC18_Pos (18U)
2470#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2471#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2472#define CAN_FS1R_FSC19_Pos (19U)
2473#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2474#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2475#define CAN_FS1R_FSC20_Pos (20U)
2476#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2477#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2478#define CAN_FS1R_FSC21_Pos (21U)
2479#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2480#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2481#define CAN_FS1R_FSC22_Pos (22U)
2482#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2483#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2484#define CAN_FS1R_FSC23_Pos (23U)
2485#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2486#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2487#define CAN_FS1R_FSC24_Pos (24U)
2488#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2489#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2490#define CAN_FS1R_FSC25_Pos (25U)
2491#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2492#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2493#define CAN_FS1R_FSC26_Pos (26U)
2494#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2495#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2496#define CAN_FS1R_FSC27_Pos (27U)
2497#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2498#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2501#define CAN_FFA1R_FFA_Pos (0U)
2502#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2503#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2504#define CAN_FFA1R_FFA0_Pos (0U)
2505#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2506#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2507#define CAN_FFA1R_FFA1_Pos (1U)
2508#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2509#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2510#define CAN_FFA1R_FFA2_Pos (2U)
2511#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2512#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2513#define CAN_FFA1R_FFA3_Pos (3U)
2514#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2515#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2516#define CAN_FFA1R_FFA4_Pos (4U)
2517#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2518#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2519#define CAN_FFA1R_FFA5_Pos (5U)
2520#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2521#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2522#define CAN_FFA1R_FFA6_Pos (6U)
2523#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2524#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2525#define CAN_FFA1R_FFA7_Pos (7U)
2526#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2527#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2528#define CAN_FFA1R_FFA8_Pos (8U)
2529#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2530#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2531#define CAN_FFA1R_FFA9_Pos (9U)
2532#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2533#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2534#define CAN_FFA1R_FFA10_Pos (10U)
2535#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2536#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2537#define CAN_FFA1R_FFA11_Pos (11U)
2538#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2539#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2540#define CAN_FFA1R_FFA12_Pos (12U)
2541#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2542#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2543#define CAN_FFA1R_FFA13_Pos (13U)
2544#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2545#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2546#define CAN_FFA1R_FFA14_Pos (14U)
2547#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2548#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2549#define CAN_FFA1R_FFA15_Pos (15U)
2550#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2551#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2552#define CAN_FFA1R_FFA16_Pos (16U)
2553#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2554#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2555#define CAN_FFA1R_FFA17_Pos (17U)
2556#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2557#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2558#define CAN_FFA1R_FFA18_Pos (18U)
2559#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2560#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2561#define CAN_FFA1R_FFA19_Pos (19U)
2562#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2563#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2564#define CAN_FFA1R_FFA20_Pos (20U)
2565#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2566#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2567#define CAN_FFA1R_FFA21_Pos (21U)
2568#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2569#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2570#define CAN_FFA1R_FFA22_Pos (22U)
2571#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2572#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2573#define CAN_FFA1R_FFA23_Pos (23U)
2574#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2575#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2576#define CAN_FFA1R_FFA24_Pos (24U)
2577#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2578#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2579#define CAN_FFA1R_FFA25_Pos (25U)
2580#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2581#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2582#define CAN_FFA1R_FFA26_Pos (26U)
2583#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2584#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2585#define CAN_FFA1R_FFA27_Pos (27U)
2586#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2587#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2590#define CAN_FA1R_FACT_Pos (0U)
2591#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2592#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2593#define CAN_FA1R_FACT0_Pos (0U)
2594#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2595#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2596#define CAN_FA1R_FACT1_Pos (1U)
2597#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2598#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2599#define CAN_FA1R_FACT2_Pos (2U)
2600#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2601#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2602#define CAN_FA1R_FACT3_Pos (3U)
2603#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2604#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2605#define CAN_FA1R_FACT4_Pos (4U)
2606#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2607#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2608#define CAN_FA1R_FACT5_Pos (5U)
2609#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2610#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2611#define CAN_FA1R_FACT6_Pos (6U)
2612#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2613#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2614#define CAN_FA1R_FACT7_Pos (7U)
2615#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2616#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2617#define CAN_FA1R_FACT8_Pos (8U)
2618#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2619#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2620#define CAN_FA1R_FACT9_Pos (9U)
2621#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2622#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2623#define CAN_FA1R_FACT10_Pos (10U)
2624#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2625#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2626#define CAN_FA1R_FACT11_Pos (11U)
2627#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2628#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2629#define CAN_FA1R_FACT12_Pos (12U)
2630#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2631#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2632#define CAN_FA1R_FACT13_Pos (13U)
2633#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2634#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2635#define CAN_FA1R_FACT14_Pos (14U)
2636#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2637#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2638#define CAN_FA1R_FACT15_Pos (15U)
2639#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2640#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2641#define CAN_FA1R_FACT16_Pos (16U)
2642#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2643#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2644#define CAN_FA1R_FACT17_Pos (17U)
2645#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2646#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2647#define CAN_FA1R_FACT18_Pos (18U)
2648#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2649#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2650#define CAN_FA1R_FACT19_Pos (19U)
2651#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2652#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2653#define CAN_FA1R_FACT20_Pos (20U)
2654#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2655#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2656#define CAN_FA1R_FACT21_Pos (21U)
2657#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2658#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2659#define CAN_FA1R_FACT22_Pos (22U)
2660#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2661#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2662#define CAN_FA1R_FACT23_Pos (23U)
2663#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2664#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2665#define CAN_FA1R_FACT24_Pos (24U)
2666#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2667#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2668#define CAN_FA1R_FACT25_Pos (25U)
2669#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2670#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2671#define CAN_FA1R_FACT26_Pos (26U)
2672#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2673#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2674#define CAN_FA1R_FACT27_Pos (27U)
2675#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2676#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2679#define CAN_F0R1_FB0_Pos (0U)
2680#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2681#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2682#define CAN_F0R1_FB1_Pos (1U)
2683#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2684#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2685#define CAN_F0R1_FB2_Pos (2U)
2686#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2687#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2688#define CAN_F0R1_FB3_Pos (3U)
2689#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2690#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2691#define CAN_F0R1_FB4_Pos (4U)
2692#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2693#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2694#define CAN_F0R1_FB5_Pos (5U)
2695#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2696#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2697#define CAN_F0R1_FB6_Pos (6U)
2698#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2699#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2700#define CAN_F0R1_FB7_Pos (7U)
2701#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2702#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2703#define CAN_F0R1_FB8_Pos (8U)
2704#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2705#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2706#define CAN_F0R1_FB9_Pos (9U)
2707#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2708#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2709#define CAN_F0R1_FB10_Pos (10U)
2710#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2711#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2712#define CAN_F0R1_FB11_Pos (11U)
2713#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2714#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2715#define CAN_F0R1_FB12_Pos (12U)
2716#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2717#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2718#define CAN_F0R1_FB13_Pos (13U)
2719#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2720#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2721#define CAN_F0R1_FB14_Pos (14U)
2722#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2723#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2724#define CAN_F0R1_FB15_Pos (15U)
2725#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2726#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2727#define CAN_F0R1_FB16_Pos (16U)
2728#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2729#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2730#define CAN_F0R1_FB17_Pos (17U)
2731#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2732#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2733#define CAN_F0R1_FB18_Pos (18U)
2734#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2735#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2736#define CAN_F0R1_FB19_Pos (19U)
2737#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2738#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2739#define CAN_F0R1_FB20_Pos (20U)
2740#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2741#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2742#define CAN_F0R1_FB21_Pos (21U)
2743#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2744#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2745#define CAN_F0R1_FB22_Pos (22U)
2746#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2747#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2748#define CAN_F0R1_FB23_Pos (23U)
2749#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2750#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2751#define CAN_F0R1_FB24_Pos (24U)
2752#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2753#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2754#define CAN_F0R1_FB25_Pos (25U)
2755#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2756#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2757#define CAN_F0R1_FB26_Pos (26U)
2758#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2759#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2760#define CAN_F0R1_FB27_Pos (27U)
2761#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2762#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2763#define CAN_F0R1_FB28_Pos (28U)
2764#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2765#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2766#define CAN_F0R1_FB29_Pos (29U)
2767#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2768#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2769#define CAN_F0R1_FB30_Pos (30U)
2770#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2771#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2772#define CAN_F0R1_FB31_Pos (31U)
2773#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2774#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2777#define CAN_F1R1_FB0_Pos (0U)
2778#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2779#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2780#define CAN_F1R1_FB1_Pos (1U)
2781#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2782#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2783#define CAN_F1R1_FB2_Pos (2U)
2784#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2785#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2786#define CAN_F1R1_FB3_Pos (3U)
2787#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2788#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2789#define CAN_F1R1_FB4_Pos (4U)
2790#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2791#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2792#define CAN_F1R1_FB5_Pos (5U)
2793#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2794#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2795#define CAN_F1R1_FB6_Pos (6U)
2796#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2797#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2798#define CAN_F1R1_FB7_Pos (7U)
2799#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2800#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2801#define CAN_F1R1_FB8_Pos (8U)
2802#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2803#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2804#define CAN_F1R1_FB9_Pos (9U)
2805#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2806#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2807#define CAN_F1R1_FB10_Pos (10U)
2808#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2809#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2810#define CAN_F1R1_FB11_Pos (11U)
2811#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2812#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2813#define CAN_F1R1_FB12_Pos (12U)
2814#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2815#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2816#define CAN_F1R1_FB13_Pos (13U)
2817#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2818#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2819#define CAN_F1R1_FB14_Pos (14U)
2820#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2821#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2822#define CAN_F1R1_FB15_Pos (15U)
2823#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2824#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2825#define CAN_F1R1_FB16_Pos (16U)
2826#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2827#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2828#define CAN_F1R1_FB17_Pos (17U)
2829#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2830#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2831#define CAN_F1R1_FB18_Pos (18U)
2832#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2833#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2834#define CAN_F1R1_FB19_Pos (19U)
2835#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2836#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2837#define CAN_F1R1_FB20_Pos (20U)
2838#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2839#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2840#define CAN_F1R1_FB21_Pos (21U)
2841#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2842#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2843#define CAN_F1R1_FB22_Pos (22U)
2844#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2845#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2846#define CAN_F1R1_FB23_Pos (23U)
2847#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2848#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2849#define CAN_F1R1_FB24_Pos (24U)
2850#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2851#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2852#define CAN_F1R1_FB25_Pos (25U)
2853#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2854#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2855#define CAN_F1R1_FB26_Pos (26U)
2856#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2857#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2858#define CAN_F1R1_FB27_Pos (27U)
2859#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
2860#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
2861#define CAN_F1R1_FB28_Pos (28U)
2862#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
2863#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
2864#define CAN_F1R1_FB29_Pos (29U)
2865#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
2866#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
2867#define CAN_F1R1_FB30_Pos (30U)
2868#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
2869#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
2870#define CAN_F1R1_FB31_Pos (31U)
2871#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
2872#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
2875#define CAN_F2R1_FB0_Pos (0U)
2876#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
2877#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
2878#define CAN_F2R1_FB1_Pos (1U)
2879#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
2880#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
2881#define CAN_F2R1_FB2_Pos (2U)
2882#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
2883#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
2884#define CAN_F2R1_FB3_Pos (3U)
2885#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
2886#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
2887#define CAN_F2R1_FB4_Pos (4U)
2888#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
2889#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
2890#define CAN_F2R1_FB5_Pos (5U)
2891#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
2892#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
2893#define CAN_F2R1_FB6_Pos (6U)
2894#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
2895#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
2896#define CAN_F2R1_FB7_Pos (7U)
2897#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
2898#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
2899#define CAN_F2R1_FB8_Pos (8U)
2900#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
2901#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
2902#define CAN_F2R1_FB9_Pos (9U)
2903#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
2904#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
2905#define CAN_F2R1_FB10_Pos (10U)
2906#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
2907#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
2908#define CAN_F2R1_FB11_Pos (11U)
2909#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
2910#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
2911#define CAN_F2R1_FB12_Pos (12U)
2912#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
2913#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
2914#define CAN_F2R1_FB13_Pos (13U)
2915#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
2916#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
2917#define CAN_F2R1_FB14_Pos (14U)
2918#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
2919#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
2920#define CAN_F2R1_FB15_Pos (15U)
2921#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
2922#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
2923#define CAN_F2R1_FB16_Pos (16U)
2924#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
2925#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
2926#define CAN_F2R1_FB17_Pos (17U)
2927#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
2928#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
2929#define CAN_F2R1_FB18_Pos (18U)
2930#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
2931#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
2932#define CAN_F2R1_FB19_Pos (19U)
2933#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
2934#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
2935#define CAN_F2R1_FB20_Pos (20U)
2936#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
2937#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
2938#define CAN_F2R1_FB21_Pos (21U)
2939#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
2940#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
2941#define CAN_F2R1_FB22_Pos (22U)
2942#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
2943#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
2944#define CAN_F2R1_FB23_Pos (23U)
2945#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
2946#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
2947#define CAN_F2R1_FB24_Pos (24U)
2948#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
2949#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
2950#define CAN_F2R1_FB25_Pos (25U)
2951#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
2952#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
2953#define CAN_F2R1_FB26_Pos (26U)
2954#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
2955#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
2956#define CAN_F2R1_FB27_Pos (27U)
2957#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
2958#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
2959#define CAN_F2R1_FB28_Pos (28U)
2960#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
2961#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
2962#define CAN_F2R1_FB29_Pos (29U)
2963#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
2964#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
2965#define CAN_F2R1_FB30_Pos (30U)
2966#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
2967#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
2968#define CAN_F2R1_FB31_Pos (31U)
2969#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
2970#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
2973#define CAN_F3R1_FB0_Pos (0U)
2974#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
2975#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
2976#define CAN_F3R1_FB1_Pos (1U)
2977#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
2978#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
2979#define CAN_F3R1_FB2_Pos (2U)
2980#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
2981#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
2982#define CAN_F3R1_FB3_Pos (3U)
2983#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
2984#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
2985#define CAN_F3R1_FB4_Pos (4U)
2986#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
2987#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
2988#define CAN_F3R1_FB5_Pos (5U)
2989#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
2990#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
2991#define CAN_F3R1_FB6_Pos (6U)
2992#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
2993#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
2994#define CAN_F3R1_FB7_Pos (7U)
2995#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
2996#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
2997#define CAN_F3R1_FB8_Pos (8U)
2998#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
2999#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3000#define CAN_F3R1_FB9_Pos (9U)
3001#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3002#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3003#define CAN_F3R1_FB10_Pos (10U)
3004#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3005#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3006#define CAN_F3R1_FB11_Pos (11U)
3007#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3008#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3009#define CAN_F3R1_FB12_Pos (12U)
3010#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3011#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3012#define CAN_F3R1_FB13_Pos (13U)
3013#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3014#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3015#define CAN_F3R1_FB14_Pos (14U)
3016#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3017#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3018#define CAN_F3R1_FB15_Pos (15U)
3019#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3020#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3021#define CAN_F3R1_FB16_Pos (16U)
3022#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3023#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3024#define CAN_F3R1_FB17_Pos (17U)
3025#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3026#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3027#define CAN_F3R1_FB18_Pos (18U)
3028#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3029#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3030#define CAN_F3R1_FB19_Pos (19U)
3031#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3032#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3033#define CAN_F3R1_FB20_Pos (20U)
3034#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3035#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3036#define CAN_F3R1_FB21_Pos (21U)
3037#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3038#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3039#define CAN_F3R1_FB22_Pos (22U)
3040#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3041#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3042#define CAN_F3R1_FB23_Pos (23U)
3043#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3044#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3045#define CAN_F3R1_FB24_Pos (24U)
3046#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3047#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3048#define CAN_F3R1_FB25_Pos (25U)
3049#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3050#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3051#define CAN_F3R1_FB26_Pos (26U)
3052#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3053#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3054#define CAN_F3R1_FB27_Pos (27U)
3055#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3056#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3057#define CAN_F3R1_FB28_Pos (28U)
3058#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3059#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3060#define CAN_F3R1_FB29_Pos (29U)
3061#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3062#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3063#define CAN_F3R1_FB30_Pos (30U)
3064#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3065#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3066#define CAN_F3R1_FB31_Pos (31U)
3067#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3068#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3071#define CAN_F4R1_FB0_Pos (0U)
3072#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3073#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3074#define CAN_F4R1_FB1_Pos (1U)
3075#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3076#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3077#define CAN_F4R1_FB2_Pos (2U)
3078#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3079#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3080#define CAN_F4R1_FB3_Pos (3U)
3081#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3082#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3083#define CAN_F4R1_FB4_Pos (4U)
3084#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3085#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3086#define CAN_F4R1_FB5_Pos (5U)
3087#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3088#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3089#define CAN_F4R1_FB6_Pos (6U)
3090#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3091#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3092#define CAN_F4R1_FB7_Pos (7U)
3093#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3094#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3095#define CAN_F4R1_FB8_Pos (8U)
3096#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3097#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3098#define CAN_F4R1_FB9_Pos (9U)
3099#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3100#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3101#define CAN_F4R1_FB10_Pos (10U)
3102#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3103#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3104#define CAN_F4R1_FB11_Pos (11U)
3105#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3106#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3107#define CAN_F4R1_FB12_Pos (12U)
3108#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3109#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3110#define CAN_F4R1_FB13_Pos (13U)
3111#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3112#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3113#define CAN_F4R1_FB14_Pos (14U)
3114#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3115#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3116#define CAN_F4R1_FB15_Pos (15U)
3117#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3118#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3119#define CAN_F4R1_FB16_Pos (16U)
3120#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3121#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3122#define CAN_F4R1_FB17_Pos (17U)
3123#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3124#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3125#define CAN_F4R1_FB18_Pos (18U)
3126#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3127#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3128#define CAN_F4R1_FB19_Pos (19U)
3129#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3130#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3131#define CAN_F4R1_FB20_Pos (20U)
3132#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3133#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3134#define CAN_F4R1_FB21_Pos (21U)
3135#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3136#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3137#define CAN_F4R1_FB22_Pos (22U)
3138#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3139#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3140#define CAN_F4R1_FB23_Pos (23U)
3141#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3142#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3143#define CAN_F4R1_FB24_Pos (24U)
3144#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3145#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3146#define CAN_F4R1_FB25_Pos (25U)
3147#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3148#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3149#define CAN_F4R1_FB26_Pos (26U)
3150#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3151#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3152#define CAN_F4R1_FB27_Pos (27U)
3153#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3154#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3155#define CAN_F4R1_FB28_Pos (28U)
3156#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3157#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3158#define CAN_F4R1_FB29_Pos (29U)
3159#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3160#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3161#define CAN_F4R1_FB30_Pos (30U)
3162#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3163#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3164#define CAN_F4R1_FB31_Pos (31U)
3165#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3166#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3169#define CAN_F5R1_FB0_Pos (0U)
3170#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3171#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3172#define CAN_F5R1_FB1_Pos (1U)
3173#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3174#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3175#define CAN_F5R1_FB2_Pos (2U)
3176#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3177#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3178#define CAN_F5R1_FB3_Pos (3U)
3179#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3180#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3181#define CAN_F5R1_FB4_Pos (4U)
3182#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3183#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3184#define CAN_F5R1_FB5_Pos (5U)
3185#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3186#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3187#define CAN_F5R1_FB6_Pos (6U)
3188#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3189#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3190#define CAN_F5R1_FB7_Pos (7U)
3191#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3192#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3193#define CAN_F5R1_FB8_Pos (8U)
3194#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3195#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3196#define CAN_F5R1_FB9_Pos (9U)
3197#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3198#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3199#define CAN_F5R1_FB10_Pos (10U)
3200#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3201#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3202#define CAN_F5R1_FB11_Pos (11U)
3203#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3204#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3205#define CAN_F5R1_FB12_Pos (12U)
3206#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3207#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3208#define CAN_F5R1_FB13_Pos (13U)
3209#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3210#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3211#define CAN_F5R1_FB14_Pos (14U)
3212#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3213#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3214#define CAN_F5R1_FB15_Pos (15U)
3215#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3216#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3217#define CAN_F5R1_FB16_Pos (16U)
3218#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3219#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3220#define CAN_F5R1_FB17_Pos (17U)
3221#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3222#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3223#define CAN_F5R1_FB18_Pos (18U)
3224#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3225#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3226#define CAN_F5R1_FB19_Pos (19U)
3227#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3228#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3229#define CAN_F5R1_FB20_Pos (20U)
3230#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3231#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3232#define CAN_F5R1_FB21_Pos (21U)
3233#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3234#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3235#define CAN_F5R1_FB22_Pos (22U)
3236#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3237#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3238#define CAN_F5R1_FB23_Pos (23U)
3239#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3240#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3241#define CAN_F5R1_FB24_Pos (24U)
3242#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3243#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3244#define CAN_F5R1_FB25_Pos (25U)
3245#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3246#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3247#define CAN_F5R1_FB26_Pos (26U)
3248#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3249#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3250#define CAN_F5R1_FB27_Pos (27U)
3251#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3252#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3253#define CAN_F5R1_FB28_Pos (28U)
3254#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3255#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3256#define CAN_F5R1_FB29_Pos (29U)
3257#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3258#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3259#define CAN_F5R1_FB30_Pos (30U)
3260#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3261#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3262#define CAN_F5R1_FB31_Pos (31U)
3263#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3264#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3267#define CAN_F6R1_FB0_Pos (0U)
3268#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3269#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3270#define CAN_F6R1_FB1_Pos (1U)
3271#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3272#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3273#define CAN_F6R1_FB2_Pos (2U)
3274#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3275#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3276#define CAN_F6R1_FB3_Pos (3U)
3277#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3278#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3279#define CAN_F6R1_FB4_Pos (4U)
3280#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3281#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3282#define CAN_F6R1_FB5_Pos (5U)
3283#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3284#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3285#define CAN_F6R1_FB6_Pos (6U)
3286#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3287#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3288#define CAN_F6R1_FB7_Pos (7U)
3289#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3290#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3291#define CAN_F6R1_FB8_Pos (8U)
3292#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3293#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3294#define CAN_F6R1_FB9_Pos (9U)
3295#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3296#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3297#define CAN_F6R1_FB10_Pos (10U)
3298#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3299#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3300#define CAN_F6R1_FB11_Pos (11U)
3301#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3302#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3303#define CAN_F6R1_FB12_Pos (12U)
3304#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3305#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3306#define CAN_F6R1_FB13_Pos (13U)
3307#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3308#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3309#define CAN_F6R1_FB14_Pos (14U)
3310#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3311#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3312#define CAN_F6R1_FB15_Pos (15U)
3313#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3314#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3315#define CAN_F6R1_FB16_Pos (16U)
3316#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3317#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3318#define CAN_F6R1_FB17_Pos (17U)
3319#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3320#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3321#define CAN_F6R1_FB18_Pos (18U)
3322#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3323#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3324#define CAN_F6R1_FB19_Pos (19U)
3325#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3326#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3327#define CAN_F6R1_FB20_Pos (20U)
3328#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3329#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3330#define CAN_F6R1_FB21_Pos (21U)
3331#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3332#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3333#define CAN_F6R1_FB22_Pos (22U)
3334#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3335#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3336#define CAN_F6R1_FB23_Pos (23U)
3337#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3338#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3339#define CAN_F6R1_FB24_Pos (24U)
3340#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3341#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3342#define CAN_F6R1_FB25_Pos (25U)
3343#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3344#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3345#define CAN_F6R1_FB26_Pos (26U)
3346#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3347#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3348#define CAN_F6R1_FB27_Pos (27U)
3349#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3350#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3351#define CAN_F6R1_FB28_Pos (28U)
3352#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3353#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3354#define CAN_F6R1_FB29_Pos (29U)
3355#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3356#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3357#define CAN_F6R1_FB30_Pos (30U)
3358#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3359#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3360#define CAN_F6R1_FB31_Pos (31U)
3361#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3362#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3365#define CAN_F7R1_FB0_Pos (0U)
3366#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3367#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3368#define CAN_F7R1_FB1_Pos (1U)
3369#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3370#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3371#define CAN_F7R1_FB2_Pos (2U)
3372#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3373#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3374#define CAN_F7R1_FB3_Pos (3U)
3375#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3376#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3377#define CAN_F7R1_FB4_Pos (4U)
3378#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3379#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3380#define CAN_F7R1_FB5_Pos (5U)
3381#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3382#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3383#define CAN_F7R1_FB6_Pos (6U)
3384#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3385#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3386#define CAN_F7R1_FB7_Pos (7U)
3387#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3388#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3389#define CAN_F7R1_FB8_Pos (8U)
3390#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3391#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3392#define CAN_F7R1_FB9_Pos (9U)
3393#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3394#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3395#define CAN_F7R1_FB10_Pos (10U)
3396#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3397#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3398#define CAN_F7R1_FB11_Pos (11U)
3399#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3400#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3401#define CAN_F7R1_FB12_Pos (12U)
3402#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3403#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3404#define CAN_F7R1_FB13_Pos (13U)
3405#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3406#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3407#define CAN_F7R1_FB14_Pos (14U)
3408#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3409#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3410#define CAN_F7R1_FB15_Pos (15U)
3411#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3412#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3413#define CAN_F7R1_FB16_Pos (16U)
3414#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3415#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3416#define CAN_F7R1_FB17_Pos (17U)
3417#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3418#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3419#define CAN_F7R1_FB18_Pos (18U)
3420#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3421#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3422#define CAN_F7R1_FB19_Pos (19U)
3423#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3424#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3425#define CAN_F7R1_FB20_Pos (20U)
3426#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3427#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3428#define CAN_F7R1_FB21_Pos (21U)
3429#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3430#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3431#define CAN_F7R1_FB22_Pos (22U)
3432#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3433#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3434#define CAN_F7R1_FB23_Pos (23U)
3435#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3436#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3437#define CAN_F7R1_FB24_Pos (24U)
3438#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3439#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3440#define CAN_F7R1_FB25_Pos (25U)
3441#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3442#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3443#define CAN_F7R1_FB26_Pos (26U)
3444#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3445#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3446#define CAN_F7R1_FB27_Pos (27U)
3447#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3448#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3449#define CAN_F7R1_FB28_Pos (28U)
3450#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3451#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3452#define CAN_F7R1_FB29_Pos (29U)
3453#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3454#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3455#define CAN_F7R1_FB30_Pos (30U)
3456#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3457#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3458#define CAN_F7R1_FB31_Pos (31U)
3459#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3460#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3463#define CAN_F8R1_FB0_Pos (0U)
3464#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3465#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3466#define CAN_F8R1_FB1_Pos (1U)
3467#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3468#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3469#define CAN_F8R1_FB2_Pos (2U)
3470#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3471#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3472#define CAN_F8R1_FB3_Pos (3U)
3473#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3474#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3475#define CAN_F8R1_FB4_Pos (4U)
3476#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3477#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3478#define CAN_F8R1_FB5_Pos (5U)
3479#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3480#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3481#define CAN_F8R1_FB6_Pos (6U)
3482#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3483#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3484#define CAN_F8R1_FB7_Pos (7U)
3485#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3486#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3487#define CAN_F8R1_FB8_Pos (8U)
3488#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3489#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3490#define CAN_F8R1_FB9_Pos (9U)
3491#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3492#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3493#define CAN_F8R1_FB10_Pos (10U)
3494#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3495#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3496#define CAN_F8R1_FB11_Pos (11U)
3497#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3498#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3499#define CAN_F8R1_FB12_Pos (12U)
3500#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3501#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3502#define CAN_F8R1_FB13_Pos (13U)
3503#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3504#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3505#define CAN_F8R1_FB14_Pos (14U)
3506#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3507#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3508#define CAN_F8R1_FB15_Pos (15U)
3509#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3510#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3511#define CAN_F8R1_FB16_Pos (16U)
3512#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3513#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3514#define CAN_F8R1_FB17_Pos (17U)
3515#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3516#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3517#define CAN_F8R1_FB18_Pos (18U)
3518#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3519#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3520#define CAN_F8R1_FB19_Pos (19U)
3521#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3522#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3523#define CAN_F8R1_FB20_Pos (20U)
3524#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3525#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3526#define CAN_F8R1_FB21_Pos (21U)
3527#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3528#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3529#define CAN_F8R1_FB22_Pos (22U)
3530#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3531#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3532#define CAN_F8R1_FB23_Pos (23U)
3533#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3534#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3535#define CAN_F8R1_FB24_Pos (24U)
3536#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3537#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3538#define CAN_F8R1_FB25_Pos (25U)
3539#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3540#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3541#define CAN_F8R1_FB26_Pos (26U)
3542#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3543#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3544#define CAN_F8R1_FB27_Pos (27U)
3545#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3546#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3547#define CAN_F8R1_FB28_Pos (28U)
3548#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3549#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3550#define CAN_F8R1_FB29_Pos (29U)
3551#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3552#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3553#define CAN_F8R1_FB30_Pos (30U)
3554#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3555#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3556#define CAN_F8R1_FB31_Pos (31U)
3557#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3558#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3561#define CAN_F9R1_FB0_Pos (0U)
3562#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3563#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3564#define CAN_F9R1_FB1_Pos (1U)
3565#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3566#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3567#define CAN_F9R1_FB2_Pos (2U)
3568#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3569#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3570#define CAN_F9R1_FB3_Pos (3U)
3571#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3572#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3573#define CAN_F9R1_FB4_Pos (4U)
3574#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3575#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3576#define CAN_F9R1_FB5_Pos (5U)
3577#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3578#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3579#define CAN_F9R1_FB6_Pos (6U)
3580#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3581#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3582#define CAN_F9R1_FB7_Pos (7U)
3583#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3584#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3585#define CAN_F9R1_FB8_Pos (8U)
3586#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3587#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3588#define CAN_F9R1_FB9_Pos (9U)
3589#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3590#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3591#define CAN_F9R1_FB10_Pos (10U)
3592#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3593#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3594#define CAN_F9R1_FB11_Pos (11U)
3595#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3596#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3597#define CAN_F9R1_FB12_Pos (12U)
3598#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3599#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3600#define CAN_F9R1_FB13_Pos (13U)
3601#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3602#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3603#define CAN_F9R1_FB14_Pos (14U)
3604#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3605#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3606#define CAN_F9R1_FB15_Pos (15U)
3607#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3608#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3609#define CAN_F9R1_FB16_Pos (16U)
3610#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3611#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3612#define CAN_F9R1_FB17_Pos (17U)
3613#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3614#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3615#define CAN_F9R1_FB18_Pos (18U)
3616#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3617#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3618#define CAN_F9R1_FB19_Pos (19U)
3619#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3620#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3621#define CAN_F9R1_FB20_Pos (20U)
3622#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3623#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3624#define CAN_F9R1_FB21_Pos (21U)
3625#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3626#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3627#define CAN_F9R1_FB22_Pos (22U)
3628#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3629#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3630#define CAN_F9R1_FB23_Pos (23U)
3631#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3632#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3633#define CAN_F9R1_FB24_Pos (24U)
3634#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3635#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3636#define CAN_F9R1_FB25_Pos (25U)
3637#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3638#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3639#define CAN_F9R1_FB26_Pos (26U)
3640#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3641#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3642#define CAN_F9R1_FB27_Pos (27U)
3643#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3644#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3645#define CAN_F9R1_FB28_Pos (28U)
3646#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3647#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3648#define CAN_F9R1_FB29_Pos (29U)
3649#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3650#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3651#define CAN_F9R1_FB30_Pos (30U)
3652#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3653#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3654#define CAN_F9R1_FB31_Pos (31U)
3655#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3656#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3659#define CAN_F10R1_FB0_Pos (0U)
3660#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3661#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3662#define CAN_F10R1_FB1_Pos (1U)
3663#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3664#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3665#define CAN_F10R1_FB2_Pos (2U)
3666#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3667#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3668#define CAN_F10R1_FB3_Pos (3U)
3669#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3670#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3671#define CAN_F10R1_FB4_Pos (4U)
3672#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3673#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3674#define CAN_F10R1_FB5_Pos (5U)
3675#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3676#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3677#define CAN_F10R1_FB6_Pos (6U)
3678#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3679#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3680#define CAN_F10R1_FB7_Pos (7U)
3681#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3682#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3683#define CAN_F10R1_FB8_Pos (8U)
3684#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3685#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3686#define CAN_F10R1_FB9_Pos (9U)
3687#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3688#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3689#define CAN_F10R1_FB10_Pos (10U)
3690#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3691#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3692#define CAN_F10R1_FB11_Pos (11U)
3693#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3694#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3695#define CAN_F10R1_FB12_Pos (12U)
3696#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3697#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3698#define CAN_F10R1_FB13_Pos (13U)
3699#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3700#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3701#define CAN_F10R1_FB14_Pos (14U)
3702#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3703#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3704#define CAN_F10R1_FB15_Pos (15U)
3705#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3706#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3707#define CAN_F10R1_FB16_Pos (16U)
3708#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3709#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3710#define CAN_F10R1_FB17_Pos (17U)
3711#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3712#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3713#define CAN_F10R1_FB18_Pos (18U)
3714#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3715#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3716#define CAN_F10R1_FB19_Pos (19U)
3717#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3718#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3719#define CAN_F10R1_FB20_Pos (20U)
3720#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3721#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3722#define CAN_F10R1_FB21_Pos (21U)
3723#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3724#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3725#define CAN_F10R1_FB22_Pos (22U)
3726#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3727#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3728#define CAN_F10R1_FB23_Pos (23U)
3729#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3730#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3731#define CAN_F10R1_FB24_Pos (24U)
3732#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3733#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3734#define CAN_F10R1_FB25_Pos (25U)
3735#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3736#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3737#define CAN_F10R1_FB26_Pos (26U)
3738#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3739#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3740#define CAN_F10R1_FB27_Pos (27U)
3741#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3742#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3743#define CAN_F10R1_FB28_Pos (28U)
3744#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3745#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3746#define CAN_F10R1_FB29_Pos (29U)
3747#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3748#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3749#define CAN_F10R1_FB30_Pos (30U)
3750#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3751#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3752#define CAN_F10R1_FB31_Pos (31U)
3753#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3754#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3757#define CAN_F11R1_FB0_Pos (0U)
3758#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3759#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3760#define CAN_F11R1_FB1_Pos (1U)
3761#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3762#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3763#define CAN_F11R1_FB2_Pos (2U)
3764#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3765#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3766#define CAN_F11R1_FB3_Pos (3U)
3767#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3768#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3769#define CAN_F11R1_FB4_Pos (4U)
3770#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3771#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3772#define CAN_F11R1_FB5_Pos (5U)
3773#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3774#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3775#define CAN_F11R1_FB6_Pos (6U)
3776#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3777#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3778#define CAN_F11R1_FB7_Pos (7U)
3779#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3780#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3781#define CAN_F11R1_FB8_Pos (8U)
3782#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3783#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3784#define CAN_F11R1_FB9_Pos (9U)
3785#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3786#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3787#define CAN_F11R1_FB10_Pos (10U)
3788#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3789#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3790#define CAN_F11R1_FB11_Pos (11U)
3791#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3792#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3793#define CAN_F11R1_FB12_Pos (12U)
3794#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3795#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3796#define CAN_F11R1_FB13_Pos (13U)
3797#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3798#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3799#define CAN_F11R1_FB14_Pos (14U)
3800#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3801#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3802#define CAN_F11R1_FB15_Pos (15U)
3803#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3804#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3805#define CAN_F11R1_FB16_Pos (16U)
3806#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3807#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3808#define CAN_F11R1_FB17_Pos (17U)
3809#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3810#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3811#define CAN_F11R1_FB18_Pos (18U)
3812#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3813#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3814#define CAN_F11R1_FB19_Pos (19U)
3815#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3816#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3817#define CAN_F11R1_FB20_Pos (20U)
3818#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3819#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3820#define CAN_F11R1_FB21_Pos (21U)
3821#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3822#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3823#define CAN_F11R1_FB22_Pos (22U)
3824#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3825#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3826#define CAN_F11R1_FB23_Pos (23U)
3827#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3828#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3829#define CAN_F11R1_FB24_Pos (24U)
3830#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3831#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3832#define CAN_F11R1_FB25_Pos (25U)
3833#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3834#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3835#define CAN_F11R1_FB26_Pos (26U)
3836#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3837#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3838#define CAN_F11R1_FB27_Pos (27U)
3839#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3840#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3841#define CAN_F11R1_FB28_Pos (28U)
3842#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3843#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3844#define CAN_F11R1_FB29_Pos (29U)
3845#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3846#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3847#define CAN_F11R1_FB30_Pos (30U)
3848#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3849#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3850#define CAN_F11R1_FB31_Pos (31U)
3851#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3852#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3855#define CAN_F12R1_FB0_Pos (0U)
3856#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3857#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3858#define CAN_F12R1_FB1_Pos (1U)
3859#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
3860#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
3861#define CAN_F12R1_FB2_Pos (2U)
3862#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
3863#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
3864#define CAN_F12R1_FB3_Pos (3U)
3865#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
3866#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
3867#define CAN_F12R1_FB4_Pos (4U)
3868#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
3869#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
3870#define CAN_F12R1_FB5_Pos (5U)
3871#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
3872#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
3873#define CAN_F12R1_FB6_Pos (6U)
3874#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
3875#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
3876#define CAN_F12R1_FB7_Pos (7U)
3877#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
3878#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
3879#define CAN_F12R1_FB8_Pos (8U)
3880#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
3881#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
3882#define CAN_F12R1_FB9_Pos (9U)
3883#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
3884#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
3885#define CAN_F12R1_FB10_Pos (10U)
3886#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
3887#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
3888#define CAN_F12R1_FB11_Pos (11U)
3889#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
3890#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
3891#define CAN_F12R1_FB12_Pos (12U)
3892#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
3893#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
3894#define CAN_F12R1_FB13_Pos (13U)
3895#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
3896#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
3897#define CAN_F12R1_FB14_Pos (14U)
3898#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
3899#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
3900#define CAN_F12R1_FB15_Pos (15U)
3901#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
3902#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
3903#define CAN_F12R1_FB16_Pos (16U)
3904#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
3905#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
3906#define CAN_F12R1_FB17_Pos (17U)
3907#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
3908#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
3909#define CAN_F12R1_FB18_Pos (18U)
3910#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
3911#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
3912#define CAN_F12R1_FB19_Pos (19U)
3913#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
3914#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
3915#define CAN_F12R1_FB20_Pos (20U)
3916#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
3917#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
3918#define CAN_F12R1_FB21_Pos (21U)
3919#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
3920#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
3921#define CAN_F12R1_FB22_Pos (22U)
3922#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
3923#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
3924#define CAN_F12R1_FB23_Pos (23U)
3925#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
3926#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
3927#define CAN_F12R1_FB24_Pos (24U)
3928#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
3929#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
3930#define CAN_F12R1_FB25_Pos (25U)
3931#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
3932#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
3933#define CAN_F12R1_FB26_Pos (26U)
3934#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
3935#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
3936#define CAN_F12R1_FB27_Pos (27U)
3937#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
3938#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
3939#define CAN_F12R1_FB28_Pos (28U)
3940#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
3941#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
3942#define CAN_F12R1_FB29_Pos (29U)
3943#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
3944#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
3945#define CAN_F12R1_FB30_Pos (30U)
3946#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
3947#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
3948#define CAN_F12R1_FB31_Pos (31U)
3949#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
3950#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
3953#define CAN_F13R1_FB0_Pos (0U)
3954#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
3955#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
3956#define CAN_F13R1_FB1_Pos (1U)
3957#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
3958#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
3959#define CAN_F13R1_FB2_Pos (2U)
3960#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
3961#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
3962#define CAN_F13R1_FB3_Pos (3U)
3963#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
3964#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
3965#define CAN_F13R1_FB4_Pos (4U)
3966#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
3967#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
3968#define CAN_F13R1_FB5_Pos (5U)
3969#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
3970#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
3971#define CAN_F13R1_FB6_Pos (6U)
3972#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
3973#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
3974#define CAN_F13R1_FB7_Pos (7U)
3975#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
3976#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
3977#define CAN_F13R1_FB8_Pos (8U)
3978#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
3979#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
3980#define CAN_F13R1_FB9_Pos (9U)
3981#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
3982#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
3983#define CAN_F13R1_FB10_Pos (10U)
3984#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
3985#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
3986#define CAN_F13R1_FB11_Pos (11U)
3987#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
3988#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
3989#define CAN_F13R1_FB12_Pos (12U)
3990#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
3991#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
3992#define CAN_F13R1_FB13_Pos (13U)
3993#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
3994#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
3995#define CAN_F13R1_FB14_Pos (14U)
3996#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
3997#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
3998#define CAN_F13R1_FB15_Pos (15U)
3999#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4000#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4001#define CAN_F13R1_FB16_Pos (16U)
4002#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4003#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4004#define CAN_F13R1_FB17_Pos (17U)
4005#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4006#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4007#define CAN_F13R1_FB18_Pos (18U)
4008#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4009#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4010#define CAN_F13R1_FB19_Pos (19U)
4011#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4012#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4013#define CAN_F13R1_FB20_Pos (20U)
4014#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4015#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4016#define CAN_F13R1_FB21_Pos (21U)
4017#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4018#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4019#define CAN_F13R1_FB22_Pos (22U)
4020#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4021#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4022#define CAN_F13R1_FB23_Pos (23U)
4023#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4024#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4025#define CAN_F13R1_FB24_Pos (24U)
4026#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4027#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4028#define CAN_F13R1_FB25_Pos (25U)
4029#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4030#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4031#define CAN_F13R1_FB26_Pos (26U)
4032#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4033#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4034#define CAN_F13R1_FB27_Pos (27U)
4035#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4036#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4037#define CAN_F13R1_FB28_Pos (28U)
4038#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4039#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4040#define CAN_F13R1_FB29_Pos (29U)
4041#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4042#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4043#define CAN_F13R1_FB30_Pos (30U)
4044#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4045#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4046#define CAN_F13R1_FB31_Pos (31U)
4047#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4048#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4051#define CAN_F0R2_FB0_Pos (0U)
4052#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4053#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4054#define CAN_F0R2_FB1_Pos (1U)
4055#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4056#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4057#define CAN_F0R2_FB2_Pos (2U)
4058#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4059#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4060#define CAN_F0R2_FB3_Pos (3U)
4061#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4062#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4063#define CAN_F0R2_FB4_Pos (4U)
4064#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4065#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4066#define CAN_F0R2_FB5_Pos (5U)
4067#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4068#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4069#define CAN_F0R2_FB6_Pos (6U)
4070#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4071#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4072#define CAN_F0R2_FB7_Pos (7U)
4073#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4074#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4075#define CAN_F0R2_FB8_Pos (8U)
4076#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4077#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4078#define CAN_F0R2_FB9_Pos (9U)
4079#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4080#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4081#define CAN_F0R2_FB10_Pos (10U)
4082#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4083#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4084#define CAN_F0R2_FB11_Pos (11U)
4085#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4086#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4087#define CAN_F0R2_FB12_Pos (12U)
4088#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4089#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4090#define CAN_F0R2_FB13_Pos (13U)
4091#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4092#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4093#define CAN_F0R2_FB14_Pos (14U)
4094#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4095#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4096#define CAN_F0R2_FB15_Pos (15U)
4097#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4098#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4099#define CAN_F0R2_FB16_Pos (16U)
4100#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4101#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4102#define CAN_F0R2_FB17_Pos (17U)
4103#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4104#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4105#define CAN_F0R2_FB18_Pos (18U)
4106#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4107#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4108#define CAN_F0R2_FB19_Pos (19U)
4109#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4110#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4111#define CAN_F0R2_FB20_Pos (20U)
4112#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4113#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4114#define CAN_F0R2_FB21_Pos (21U)
4115#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4116#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4117#define CAN_F0R2_FB22_Pos (22U)
4118#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4119#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4120#define CAN_F0R2_FB23_Pos (23U)
4121#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4122#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4123#define CAN_F0R2_FB24_Pos (24U)
4124#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4125#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4126#define CAN_F0R2_FB25_Pos (25U)
4127#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4128#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4129#define CAN_F0R2_FB26_Pos (26U)
4130#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4131#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4132#define CAN_F0R2_FB27_Pos (27U)
4133#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4134#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4135#define CAN_F0R2_FB28_Pos (28U)
4136#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4137#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4138#define CAN_F0R2_FB29_Pos (29U)
4139#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4140#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4141#define CAN_F0R2_FB30_Pos (30U)
4142#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4143#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4144#define CAN_F0R2_FB31_Pos (31U)
4145#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4146#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4149#define CAN_F1R2_FB0_Pos (0U)
4150#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4151#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4152#define CAN_F1R2_FB1_Pos (1U)
4153#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4154#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4155#define CAN_F1R2_FB2_Pos (2U)
4156#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4157#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4158#define CAN_F1R2_FB3_Pos (3U)
4159#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4160#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4161#define CAN_F1R2_FB4_Pos (4U)
4162#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4163#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4164#define CAN_F1R2_FB5_Pos (5U)
4165#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4166#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4167#define CAN_F1R2_FB6_Pos (6U)
4168#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4169#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4170#define CAN_F1R2_FB7_Pos (7U)
4171#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4172#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4173#define CAN_F1R2_FB8_Pos (8U)
4174#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4175#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4176#define CAN_F1R2_FB9_Pos (9U)
4177#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4178#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4179#define CAN_F1R2_FB10_Pos (10U)
4180#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4181#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4182#define CAN_F1R2_FB11_Pos (11U)
4183#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4184#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4185#define CAN_F1R2_FB12_Pos (12U)
4186#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4187#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4188#define CAN_F1R2_FB13_Pos (13U)
4189#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4190#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4191#define CAN_F1R2_FB14_Pos (14U)
4192#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4193#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4194#define CAN_F1R2_FB15_Pos (15U)
4195#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4196#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4197#define CAN_F1R2_FB16_Pos (16U)
4198#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4199#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4200#define CAN_F1R2_FB17_Pos (17U)
4201#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4202#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4203#define CAN_F1R2_FB18_Pos (18U)
4204#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4205#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4206#define CAN_F1R2_FB19_Pos (19U)
4207#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4208#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4209#define CAN_F1R2_FB20_Pos (20U)
4210#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4211#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4212#define CAN_F1R2_FB21_Pos (21U)
4213#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4214#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4215#define CAN_F1R2_FB22_Pos (22U)
4216#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4217#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4218#define CAN_F1R2_FB23_Pos (23U)
4219#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4220#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4221#define CAN_F1R2_FB24_Pos (24U)
4222#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4223#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4224#define CAN_F1R2_FB25_Pos (25U)
4225#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4226#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4227#define CAN_F1R2_FB26_Pos (26U)
4228#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4229#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4230#define CAN_F1R2_FB27_Pos (27U)
4231#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4232#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4233#define CAN_F1R2_FB28_Pos (28U)
4234#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4235#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4236#define CAN_F1R2_FB29_Pos (29U)
4237#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4238#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4239#define CAN_F1R2_FB30_Pos (30U)
4240#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4241#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4242#define CAN_F1R2_FB31_Pos (31U)
4243#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4244#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4247#define CAN_F2R2_FB0_Pos (0U)
4248#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4249#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4250#define CAN_F2R2_FB1_Pos (1U)
4251#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4252#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4253#define CAN_F2R2_FB2_Pos (2U)
4254#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4255#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4256#define CAN_F2R2_FB3_Pos (3U)
4257#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4258#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4259#define CAN_F2R2_FB4_Pos (4U)
4260#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4261#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4262#define CAN_F2R2_FB5_Pos (5U)
4263#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4264#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4265#define CAN_F2R2_FB6_Pos (6U)
4266#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4267#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4268#define CAN_F2R2_FB7_Pos (7U)
4269#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4270#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4271#define CAN_F2R2_FB8_Pos (8U)
4272#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4273#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4274#define CAN_F2R2_FB9_Pos (9U)
4275#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4276#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4277#define CAN_F2R2_FB10_Pos (10U)
4278#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4279#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4280#define CAN_F2R2_FB11_Pos (11U)
4281#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4282#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4283#define CAN_F2R2_FB12_Pos (12U)
4284#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4285#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4286#define CAN_F2R2_FB13_Pos (13U)
4287#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4288#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4289#define CAN_F2R2_FB14_Pos (14U)
4290#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4291#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4292#define CAN_F2R2_FB15_Pos (15U)
4293#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4294#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4295#define CAN_F2R2_FB16_Pos (16U)
4296#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4297#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4298#define CAN_F2R2_FB17_Pos (17U)
4299#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4300#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4301#define CAN_F2R2_FB18_Pos (18U)
4302#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4303#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4304#define CAN_F2R2_FB19_Pos (19U)
4305#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4306#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4307#define CAN_F2R2_FB20_Pos (20U)
4308#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4309#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4310#define CAN_F2R2_FB21_Pos (21U)
4311#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4312#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4313#define CAN_F2R2_FB22_Pos (22U)
4314#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4315#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4316#define CAN_F2R2_FB23_Pos (23U)
4317#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4318#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4319#define CAN_F2R2_FB24_Pos (24U)
4320#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4321#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4322#define CAN_F2R2_FB25_Pos (25U)
4323#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4324#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4325#define CAN_F2R2_FB26_Pos (26U)
4326#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4327#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4328#define CAN_F2R2_FB27_Pos (27U)
4329#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4330#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4331#define CAN_F2R2_FB28_Pos (28U)
4332#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4333#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4334#define CAN_F2R2_FB29_Pos (29U)
4335#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4336#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4337#define CAN_F2R2_FB30_Pos (30U)
4338#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4339#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4340#define CAN_F2R2_FB31_Pos (31U)
4341#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4342#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4345#define CAN_F3R2_FB0_Pos (0U)
4346#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4347#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4348#define CAN_F3R2_FB1_Pos (1U)
4349#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4350#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4351#define CAN_F3R2_FB2_Pos (2U)
4352#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4353#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4354#define CAN_F3R2_FB3_Pos (3U)
4355#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4356#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4357#define CAN_F3R2_FB4_Pos (4U)
4358#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4359#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4360#define CAN_F3R2_FB5_Pos (5U)
4361#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4362#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4363#define CAN_F3R2_FB6_Pos (6U)
4364#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4365#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4366#define CAN_F3R2_FB7_Pos (7U)
4367#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4368#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4369#define CAN_F3R2_FB8_Pos (8U)
4370#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4371#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4372#define CAN_F3R2_FB9_Pos (9U)
4373#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4374#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4375#define CAN_F3R2_FB10_Pos (10U)
4376#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4377#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4378#define CAN_F3R2_FB11_Pos (11U)
4379#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4380#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4381#define CAN_F3R2_FB12_Pos (12U)
4382#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4383#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4384#define CAN_F3R2_FB13_Pos (13U)
4385#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4386#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4387#define CAN_F3R2_FB14_Pos (14U)
4388#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4389#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4390#define CAN_F3R2_FB15_Pos (15U)
4391#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4392#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4393#define CAN_F3R2_FB16_Pos (16U)
4394#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4395#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4396#define CAN_F3R2_FB17_Pos (17U)
4397#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4398#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4399#define CAN_F3R2_FB18_Pos (18U)
4400#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4401#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4402#define CAN_F3R2_FB19_Pos (19U)
4403#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4404#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4405#define CAN_F3R2_FB20_Pos (20U)
4406#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4407#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4408#define CAN_F3R2_FB21_Pos (21U)
4409#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4410#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4411#define CAN_F3R2_FB22_Pos (22U)
4412#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4413#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4414#define CAN_F3R2_FB23_Pos (23U)
4415#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4416#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4417#define CAN_F3R2_FB24_Pos (24U)
4418#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4419#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4420#define CAN_F3R2_FB25_Pos (25U)
4421#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4422#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4423#define CAN_F3R2_FB26_Pos (26U)
4424#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4425#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4426#define CAN_F3R2_FB27_Pos (27U)
4427#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4428#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4429#define CAN_F3R2_FB28_Pos (28U)
4430#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4431#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4432#define CAN_F3R2_FB29_Pos (29U)
4433#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4434#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4435#define CAN_F3R2_FB30_Pos (30U)
4436#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4437#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4438#define CAN_F3R2_FB31_Pos (31U)
4439#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4440#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4443#define CAN_F4R2_FB0_Pos (0U)
4444#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4445#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4446#define CAN_F4R2_FB1_Pos (1U)
4447#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4448#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4449#define CAN_F4R2_FB2_Pos (2U)
4450#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4451#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4452#define CAN_F4R2_FB3_Pos (3U)
4453#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4454#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4455#define CAN_F4R2_FB4_Pos (4U)
4456#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4457#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4458#define CAN_F4R2_FB5_Pos (5U)
4459#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4460#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4461#define CAN_F4R2_FB6_Pos (6U)
4462#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4463#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4464#define CAN_F4R2_FB7_Pos (7U)
4465#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4466#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4467#define CAN_F4R2_FB8_Pos (8U)
4468#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4469#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4470#define CAN_F4R2_FB9_Pos (9U)
4471#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4472#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4473#define CAN_F4R2_FB10_Pos (10U)
4474#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4475#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4476#define CAN_F4R2_FB11_Pos (11U)
4477#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4478#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4479#define CAN_F4R2_FB12_Pos (12U)
4480#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4481#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4482#define CAN_F4R2_FB13_Pos (13U)
4483#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4484#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4485#define CAN_F4R2_FB14_Pos (14U)
4486#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4487#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4488#define CAN_F4R2_FB15_Pos (15U)
4489#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4490#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4491#define CAN_F4R2_FB16_Pos (16U)
4492#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4493#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4494#define CAN_F4R2_FB17_Pos (17U)
4495#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4496#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4497#define CAN_F4R2_FB18_Pos (18U)
4498#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4499#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4500#define CAN_F4R2_FB19_Pos (19U)
4501#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4502#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4503#define CAN_F4R2_FB20_Pos (20U)
4504#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4505#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4506#define CAN_F4R2_FB21_Pos (21U)
4507#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4508#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4509#define CAN_F4R2_FB22_Pos (22U)
4510#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4511#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4512#define CAN_F4R2_FB23_Pos (23U)
4513#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4514#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4515#define CAN_F4R2_FB24_Pos (24U)
4516#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4517#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4518#define CAN_F4R2_FB25_Pos (25U)
4519#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4520#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4521#define CAN_F4R2_FB26_Pos (26U)
4522#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4523#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4524#define CAN_F4R2_FB27_Pos (27U)
4525#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4526#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4527#define CAN_F4R2_FB28_Pos (28U)
4528#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4529#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4530#define CAN_F4R2_FB29_Pos (29U)
4531#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4532#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4533#define CAN_F4R2_FB30_Pos (30U)
4534#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4535#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4536#define CAN_F4R2_FB31_Pos (31U)
4537#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4538#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4541#define CAN_F5R2_FB0_Pos (0U)
4542#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4543#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4544#define CAN_F5R2_FB1_Pos (1U)
4545#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4546#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4547#define CAN_F5R2_FB2_Pos (2U)
4548#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4549#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4550#define CAN_F5R2_FB3_Pos (3U)
4551#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4552#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4553#define CAN_F5R2_FB4_Pos (4U)
4554#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4555#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4556#define CAN_F5R2_FB5_Pos (5U)
4557#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4558#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4559#define CAN_F5R2_FB6_Pos (6U)
4560#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4561#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4562#define CAN_F5R2_FB7_Pos (7U)
4563#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4564#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4565#define CAN_F5R2_FB8_Pos (8U)
4566#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4567#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4568#define CAN_F5R2_FB9_Pos (9U)
4569#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4570#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4571#define CAN_F5R2_FB10_Pos (10U)
4572#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4573#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4574#define CAN_F5R2_FB11_Pos (11U)
4575#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4576#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4577#define CAN_F5R2_FB12_Pos (12U)
4578#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4579#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4580#define CAN_F5R2_FB13_Pos (13U)
4581#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4582#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4583#define CAN_F5R2_FB14_Pos (14U)
4584#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4585#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4586#define CAN_F5R2_FB15_Pos (15U)
4587#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4588#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4589#define CAN_F5R2_FB16_Pos (16U)
4590#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4591#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4592#define CAN_F5R2_FB17_Pos (17U)
4593#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4594#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4595#define CAN_F5R2_FB18_Pos (18U)
4596#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4597#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4598#define CAN_F5R2_FB19_Pos (19U)
4599#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4600#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4601#define CAN_F5R2_FB20_Pos (20U)
4602#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4603#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4604#define CAN_F5R2_FB21_Pos (21U)
4605#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4606#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4607#define CAN_F5R2_FB22_Pos (22U)
4608#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4609#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4610#define CAN_F5R2_FB23_Pos (23U)
4611#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4612#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4613#define CAN_F5R2_FB24_Pos (24U)
4614#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4615#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4616#define CAN_F5R2_FB25_Pos (25U)
4617#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4618#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4619#define CAN_F5R2_FB26_Pos (26U)
4620#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4621#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4622#define CAN_F5R2_FB27_Pos (27U)
4623#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4624#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4625#define CAN_F5R2_FB28_Pos (28U)
4626#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4627#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4628#define CAN_F5R2_FB29_Pos (29U)
4629#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4630#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4631#define CAN_F5R2_FB30_Pos (30U)
4632#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4633#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4634#define CAN_F5R2_FB31_Pos (31U)
4635#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4636#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4639#define CAN_F6R2_FB0_Pos (0U)
4640#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4641#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4642#define CAN_F6R2_FB1_Pos (1U)
4643#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4644#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4645#define CAN_F6R2_FB2_Pos (2U)
4646#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4647#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4648#define CAN_F6R2_FB3_Pos (3U)
4649#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4650#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4651#define CAN_F6R2_FB4_Pos (4U)
4652#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4653#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4654#define CAN_F6R2_FB5_Pos (5U)
4655#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4656#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4657#define CAN_F6R2_FB6_Pos (6U)
4658#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4659#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4660#define CAN_F6R2_FB7_Pos (7U)
4661#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4662#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4663#define CAN_F6R2_FB8_Pos (8U)
4664#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4665#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4666#define CAN_F6R2_FB9_Pos (9U)
4667#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4668#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4669#define CAN_F6R2_FB10_Pos (10U)
4670#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4671#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4672#define CAN_F6R2_FB11_Pos (11U)
4673#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4674#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4675#define CAN_F6R2_FB12_Pos (12U)
4676#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4677#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4678#define CAN_F6R2_FB13_Pos (13U)
4679#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4680#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4681#define CAN_F6R2_FB14_Pos (14U)
4682#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4683#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4684#define CAN_F6R2_FB15_Pos (15U)
4685#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4686#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4687#define CAN_F6R2_FB16_Pos (16U)
4688#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4689#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4690#define CAN_F6R2_FB17_Pos (17U)
4691#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4692#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4693#define CAN_F6R2_FB18_Pos (18U)
4694#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4695#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4696#define CAN_F6R2_FB19_Pos (19U)
4697#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4698#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4699#define CAN_F6R2_FB20_Pos (20U)
4700#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4701#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4702#define CAN_F6R2_FB21_Pos (21U)
4703#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4704#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4705#define CAN_F6R2_FB22_Pos (22U)
4706#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4707#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4708#define CAN_F6R2_FB23_Pos (23U)
4709#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4710#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4711#define CAN_F6R2_FB24_Pos (24U)
4712#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4713#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4714#define CAN_F6R2_FB25_Pos (25U)
4715#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4716#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4717#define CAN_F6R2_FB26_Pos (26U)
4718#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4719#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4720#define CAN_F6R2_FB27_Pos (27U)
4721#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4722#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4723#define CAN_F6R2_FB28_Pos (28U)
4724#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4725#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4726#define CAN_F6R2_FB29_Pos (29U)
4727#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4728#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4729#define CAN_F6R2_FB30_Pos (30U)
4730#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4731#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4732#define CAN_F6R2_FB31_Pos (31U)
4733#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4734#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4737#define CAN_F7R2_FB0_Pos (0U)
4738#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4739#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4740#define CAN_F7R2_FB1_Pos (1U)
4741#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4742#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4743#define CAN_F7R2_FB2_Pos (2U)
4744#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4745#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4746#define CAN_F7R2_FB3_Pos (3U)
4747#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4748#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4749#define CAN_F7R2_FB4_Pos (4U)
4750#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4751#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4752#define CAN_F7R2_FB5_Pos (5U)
4753#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4754#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4755#define CAN_F7R2_FB6_Pos (6U)
4756#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4757#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4758#define CAN_F7R2_FB7_Pos (7U)
4759#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4760#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4761#define CAN_F7R2_FB8_Pos (8U)
4762#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4763#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4764#define CAN_F7R2_FB9_Pos (9U)
4765#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4766#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4767#define CAN_F7R2_FB10_Pos (10U)
4768#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4769#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4770#define CAN_F7R2_FB11_Pos (11U)
4771#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4772#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4773#define CAN_F7R2_FB12_Pos (12U)
4774#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4775#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4776#define CAN_F7R2_FB13_Pos (13U)
4777#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4778#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4779#define CAN_F7R2_FB14_Pos (14U)
4780#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4781#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4782#define CAN_F7R2_FB15_Pos (15U)
4783#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4784#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4785#define CAN_F7R2_FB16_Pos (16U)
4786#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4787#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4788#define CAN_F7R2_FB17_Pos (17U)
4789#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4790#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4791#define CAN_F7R2_FB18_Pos (18U)
4792#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4793#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4794#define CAN_F7R2_FB19_Pos (19U)
4795#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4796#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4797#define CAN_F7R2_FB20_Pos (20U)
4798#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4799#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4800#define CAN_F7R2_FB21_Pos (21U)
4801#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4802#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4803#define CAN_F7R2_FB22_Pos (22U)
4804#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4805#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4806#define CAN_F7R2_FB23_Pos (23U)
4807#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4808#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4809#define CAN_F7R2_FB24_Pos (24U)
4810#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4811#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4812#define CAN_F7R2_FB25_Pos (25U)
4813#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4814#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4815#define CAN_F7R2_FB26_Pos (26U)
4816#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4817#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4818#define CAN_F7R2_FB27_Pos (27U)
4819#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4820#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4821#define CAN_F7R2_FB28_Pos (28U)
4822#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4823#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4824#define CAN_F7R2_FB29_Pos (29U)
4825#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4826#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4827#define CAN_F7R2_FB30_Pos (30U)
4828#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4829#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4830#define CAN_F7R2_FB31_Pos (31U)
4831#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4832#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4835#define CAN_F8R2_FB0_Pos (0U)
4836#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4837#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4838#define CAN_F8R2_FB1_Pos (1U)
4839#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4840#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4841#define CAN_F8R2_FB2_Pos (2U)
4842#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4843#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4844#define CAN_F8R2_FB3_Pos (3U)
4845#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4846#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4847#define CAN_F8R2_FB4_Pos (4U)
4848#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4849#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4850#define CAN_F8R2_FB5_Pos (5U)
4851#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4852#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4853#define CAN_F8R2_FB6_Pos (6U)
4854#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4855#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4856#define CAN_F8R2_FB7_Pos (7U)
4857#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4858#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4859#define CAN_F8R2_FB8_Pos (8U)
4860#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
4861#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
4862#define CAN_F8R2_FB9_Pos (9U)
4863#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
4864#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
4865#define CAN_F8R2_FB10_Pos (10U)
4866#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
4867#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
4868#define CAN_F8R2_FB11_Pos (11U)
4869#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
4870#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
4871#define CAN_F8R2_FB12_Pos (12U)
4872#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
4873#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
4874#define CAN_F8R2_FB13_Pos (13U)
4875#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
4876#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
4877#define CAN_F8R2_FB14_Pos (14U)
4878#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
4879#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
4880#define CAN_F8R2_FB15_Pos (15U)
4881#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
4882#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
4883#define CAN_F8R2_FB16_Pos (16U)
4884#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
4885#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
4886#define CAN_F8R2_FB17_Pos (17U)
4887#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
4888#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
4889#define CAN_F8R2_FB18_Pos (18U)
4890#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
4891#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
4892#define CAN_F8R2_FB19_Pos (19U)
4893#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
4894#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
4895#define CAN_F8R2_FB20_Pos (20U)
4896#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
4897#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
4898#define CAN_F8R2_FB21_Pos (21U)
4899#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
4900#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
4901#define CAN_F8R2_FB22_Pos (22U)
4902#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
4903#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
4904#define CAN_F8R2_FB23_Pos (23U)
4905#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
4906#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
4907#define CAN_F8R2_FB24_Pos (24U)
4908#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
4909#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
4910#define CAN_F8R2_FB25_Pos (25U)
4911#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
4912#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
4913#define CAN_F8R2_FB26_Pos (26U)
4914#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
4915#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
4916#define CAN_F8R2_FB27_Pos (27U)
4917#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
4918#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
4919#define CAN_F8R2_FB28_Pos (28U)
4920#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
4921#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
4922#define CAN_F8R2_FB29_Pos (29U)
4923#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
4924#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
4925#define CAN_F8R2_FB30_Pos (30U)
4926#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
4927#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
4928#define CAN_F8R2_FB31_Pos (31U)
4929#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
4930#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
4933#define CAN_F9R2_FB0_Pos (0U)
4934#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
4935#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
4936#define CAN_F9R2_FB1_Pos (1U)
4937#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
4938#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
4939#define CAN_F9R2_FB2_Pos (2U)
4940#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
4941#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
4942#define CAN_F9R2_FB3_Pos (3U)
4943#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
4944#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
4945#define CAN_F9R2_FB4_Pos (4U)
4946#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
4947#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
4948#define CAN_F9R2_FB5_Pos (5U)
4949#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
4950#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
4951#define CAN_F9R2_FB6_Pos (6U)
4952#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
4953#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
4954#define CAN_F9R2_FB7_Pos (7U)
4955#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
4956#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
4957#define CAN_F9R2_FB8_Pos (8U)
4958#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
4959#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
4960#define CAN_F9R2_FB9_Pos (9U)
4961#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
4962#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
4963#define CAN_F9R2_FB10_Pos (10U)
4964#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
4965#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
4966#define CAN_F9R2_FB11_Pos (11U)
4967#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
4968#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
4969#define CAN_F9R2_FB12_Pos (12U)
4970#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
4971#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
4972#define CAN_F9R2_FB13_Pos (13U)
4973#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
4974#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
4975#define CAN_F9R2_FB14_Pos (14U)
4976#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
4977#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
4978#define CAN_F9R2_FB15_Pos (15U)
4979#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
4980#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
4981#define CAN_F9R2_FB16_Pos (16U)
4982#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
4983#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
4984#define CAN_F9R2_FB17_Pos (17U)
4985#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
4986#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
4987#define CAN_F9R2_FB18_Pos (18U)
4988#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
4989#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
4990#define CAN_F9R2_FB19_Pos (19U)
4991#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
4992#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
4993#define CAN_F9R2_FB20_Pos (20U)
4994#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
4995#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
4996#define CAN_F9R2_FB21_Pos (21U)
4997#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
4998#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
4999#define CAN_F9R2_FB22_Pos (22U)
5000#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5001#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5002#define CAN_F9R2_FB23_Pos (23U)
5003#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5004#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5005#define CAN_F9R2_FB24_Pos (24U)
5006#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5007#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5008#define CAN_F9R2_FB25_Pos (25U)
5009#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5010#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5011#define CAN_F9R2_FB26_Pos (26U)
5012#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5013#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5014#define CAN_F9R2_FB27_Pos (27U)
5015#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5016#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5017#define CAN_F9R2_FB28_Pos (28U)
5018#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5019#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5020#define CAN_F9R2_FB29_Pos (29U)
5021#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5022#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5023#define CAN_F9R2_FB30_Pos (30U)
5024#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5025#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5026#define CAN_F9R2_FB31_Pos (31U)
5027#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5028#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5031#define CAN_F10R2_FB0_Pos (0U)
5032#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5033#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5034#define CAN_F10R2_FB1_Pos (1U)
5035#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5036#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5037#define CAN_F10R2_FB2_Pos (2U)
5038#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5039#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5040#define CAN_F10R2_FB3_Pos (3U)
5041#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5042#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5043#define CAN_F10R2_FB4_Pos (4U)
5044#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5045#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5046#define CAN_F10R2_FB5_Pos (5U)
5047#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5048#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5049#define CAN_F10R2_FB6_Pos (6U)
5050#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5051#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5052#define CAN_F10R2_FB7_Pos (7U)
5053#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5054#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5055#define CAN_F10R2_FB8_Pos (8U)
5056#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5057#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5058#define CAN_F10R2_FB9_Pos (9U)
5059#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5060#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5061#define CAN_F10R2_FB10_Pos (10U)
5062#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5063#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5064#define CAN_F10R2_FB11_Pos (11U)
5065#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5066#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5067#define CAN_F10R2_FB12_Pos (12U)
5068#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5069#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5070#define CAN_F10R2_FB13_Pos (13U)
5071#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5072#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5073#define CAN_F10R2_FB14_Pos (14U)
5074#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5075#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5076#define CAN_F10R2_FB15_Pos (15U)
5077#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5078#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5079#define CAN_F10R2_FB16_Pos (16U)
5080#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5081#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5082#define CAN_F10R2_FB17_Pos (17U)
5083#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5084#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5085#define CAN_F10R2_FB18_Pos (18U)
5086#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5087#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5088#define CAN_F10R2_FB19_Pos (19U)
5089#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5090#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5091#define CAN_F10R2_FB20_Pos (20U)
5092#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5093#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5094#define CAN_F10R2_FB21_Pos (21U)
5095#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5096#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5097#define CAN_F10R2_FB22_Pos (22U)
5098#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5099#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5100#define CAN_F10R2_FB23_Pos (23U)
5101#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5102#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5103#define CAN_F10R2_FB24_Pos (24U)
5104#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5105#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5106#define CAN_F10R2_FB25_Pos (25U)
5107#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5108#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5109#define CAN_F10R2_FB26_Pos (26U)
5110#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5111#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5112#define CAN_F10R2_FB27_Pos (27U)
5113#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5114#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5115#define CAN_F10R2_FB28_Pos (28U)
5116#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5117#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5118#define CAN_F10R2_FB29_Pos (29U)
5119#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5120#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5121#define CAN_F10R2_FB30_Pos (30U)
5122#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5123#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5124#define CAN_F10R2_FB31_Pos (31U)
5125#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5126#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5129#define CAN_F11R2_FB0_Pos (0U)
5130#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5131#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5132#define CAN_F11R2_FB1_Pos (1U)
5133#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5134#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5135#define CAN_F11R2_FB2_Pos (2U)
5136#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5137#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5138#define CAN_F11R2_FB3_Pos (3U)
5139#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5140#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5141#define CAN_F11R2_FB4_Pos (4U)
5142#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5143#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5144#define CAN_F11R2_FB5_Pos (5U)
5145#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5146#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5147#define CAN_F11R2_FB6_Pos (6U)
5148#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5149#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5150#define CAN_F11R2_FB7_Pos (7U)
5151#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5152#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5153#define CAN_F11R2_FB8_Pos (8U)
5154#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5155#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5156#define CAN_F11R2_FB9_Pos (9U)
5157#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5158#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5159#define CAN_F11R2_FB10_Pos (10U)
5160#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5161#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5162#define CAN_F11R2_FB11_Pos (11U)
5163#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5164#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5165#define CAN_F11R2_FB12_Pos (12U)
5166#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5167#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5168#define CAN_F11R2_FB13_Pos (13U)
5169#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5170#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5171#define CAN_F11R2_FB14_Pos (14U)
5172#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5173#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5174#define CAN_F11R2_FB15_Pos (15U)
5175#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5176#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5177#define CAN_F11R2_FB16_Pos (16U)
5178#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5179#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5180#define CAN_F11R2_FB17_Pos (17U)
5181#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5182#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5183#define CAN_F11R2_FB18_Pos (18U)
5184#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5185#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5186#define CAN_F11R2_FB19_Pos (19U)
5187#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5188#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5189#define CAN_F11R2_FB20_Pos (20U)
5190#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5191#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5192#define CAN_F11R2_FB21_Pos (21U)
5193#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5194#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5195#define CAN_F11R2_FB22_Pos (22U)
5196#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5197#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5198#define CAN_F11R2_FB23_Pos (23U)
5199#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5200#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5201#define CAN_F11R2_FB24_Pos (24U)
5202#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5203#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5204#define CAN_F11R2_FB25_Pos (25U)
5205#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5206#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5207#define CAN_F11R2_FB26_Pos (26U)
5208#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5209#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5210#define CAN_F11R2_FB27_Pos (27U)
5211#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5212#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5213#define CAN_F11R2_FB28_Pos (28U)
5214#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5215#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5216#define CAN_F11R2_FB29_Pos (29U)
5217#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5218#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5219#define CAN_F11R2_FB30_Pos (30U)
5220#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5221#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5222#define CAN_F11R2_FB31_Pos (31U)
5223#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5224#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5227#define CAN_F12R2_FB0_Pos (0U)
5228#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5229#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5230#define CAN_F12R2_FB1_Pos (1U)
5231#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5232#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5233#define CAN_F12R2_FB2_Pos (2U)
5234#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5235#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5236#define CAN_F12R2_FB3_Pos (3U)
5237#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5238#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5239#define CAN_F12R2_FB4_Pos (4U)
5240#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5241#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5242#define CAN_F12R2_FB5_Pos (5U)
5243#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5244#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5245#define CAN_F12R2_FB6_Pos (6U)
5246#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5247#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5248#define CAN_F12R2_FB7_Pos (7U)
5249#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5250#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5251#define CAN_F12R2_FB8_Pos (8U)
5252#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5253#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5254#define CAN_F12R2_FB9_Pos (9U)
5255#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5256#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5257#define CAN_F12R2_FB10_Pos (10U)
5258#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5259#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5260#define CAN_F12R2_FB11_Pos (11U)
5261#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5262#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5263#define CAN_F12R2_FB12_Pos (12U)
5264#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5265#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5266#define CAN_F12R2_FB13_Pos (13U)
5267#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5268#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5269#define CAN_F12R2_FB14_Pos (14U)
5270#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5271#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5272#define CAN_F12R2_FB15_Pos (15U)
5273#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5274#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5275#define CAN_F12R2_FB16_Pos (16U)
5276#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5277#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5278#define CAN_F12R2_FB17_Pos (17U)
5279#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5280#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5281#define CAN_F12R2_FB18_Pos (18U)
5282#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5283#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5284#define CAN_F12R2_FB19_Pos (19U)
5285#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5286#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5287#define CAN_F12R2_FB20_Pos (20U)
5288#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5289#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5290#define CAN_F12R2_FB21_Pos (21U)
5291#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5292#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5293#define CAN_F12R2_FB22_Pos (22U)
5294#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5295#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5296#define CAN_F12R2_FB23_Pos (23U)
5297#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5298#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5299#define CAN_F12R2_FB24_Pos (24U)
5300#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5301#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5302#define CAN_F12R2_FB25_Pos (25U)
5303#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5304#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5305#define CAN_F12R2_FB26_Pos (26U)
5306#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5307#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5308#define CAN_F12R2_FB27_Pos (27U)
5309#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5310#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5311#define CAN_F12R2_FB28_Pos (28U)
5312#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5313#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5314#define CAN_F12R2_FB29_Pos (29U)
5315#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5316#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5317#define CAN_F12R2_FB30_Pos (30U)
5318#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5319#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5320#define CAN_F12R2_FB31_Pos (31U)
5321#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5322#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5325#define CAN_F13R2_FB0_Pos (0U)
5326#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5327#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5328#define CAN_F13R2_FB1_Pos (1U)
5329#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5330#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5331#define CAN_F13R2_FB2_Pos (2U)
5332#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5333#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5334#define CAN_F13R2_FB3_Pos (3U)
5335#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5336#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5337#define CAN_F13R2_FB4_Pos (4U)
5338#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5339#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5340#define CAN_F13R2_FB5_Pos (5U)
5341#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5342#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5343#define CAN_F13R2_FB6_Pos (6U)
5344#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5345#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5346#define CAN_F13R2_FB7_Pos (7U)
5347#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5348#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5349#define CAN_F13R2_FB8_Pos (8U)
5350#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5351#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5352#define CAN_F13R2_FB9_Pos (9U)
5353#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5354#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5355#define CAN_F13R2_FB10_Pos (10U)
5356#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5357#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5358#define CAN_F13R2_FB11_Pos (11U)
5359#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5360#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5361#define CAN_F13R2_FB12_Pos (12U)
5362#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5363#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5364#define CAN_F13R2_FB13_Pos (13U)
5365#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5366#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5367#define CAN_F13R2_FB14_Pos (14U)
5368#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5369#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5370#define CAN_F13R2_FB15_Pos (15U)
5371#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5372#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5373#define CAN_F13R2_FB16_Pos (16U)
5374#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5375#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5376#define CAN_F13R2_FB17_Pos (17U)
5377#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5378#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5379#define CAN_F13R2_FB18_Pos (18U)
5380#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5381#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5382#define CAN_F13R2_FB19_Pos (19U)
5383#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5384#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5385#define CAN_F13R2_FB20_Pos (20U)
5386#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5387#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5388#define CAN_F13R2_FB21_Pos (21U)
5389#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5390#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5391#define CAN_F13R2_FB22_Pos (22U)
5392#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5393#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5394#define CAN_F13R2_FB23_Pos (23U)
5395#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5396#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5397#define CAN_F13R2_FB24_Pos (24U)
5398#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5399#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5400#define CAN_F13R2_FB25_Pos (25U)
5401#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5402#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5403#define CAN_F13R2_FB26_Pos (26U)
5404#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5405#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5406#define CAN_F13R2_FB27_Pos (27U)
5407#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5408#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5409#define CAN_F13R2_FB28_Pos (28U)
5410#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5411#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5412#define CAN_F13R2_FB29_Pos (29U)
5413#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5414#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5415#define CAN_F13R2_FB30_Pos (30U)
5416#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5417#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5418#define CAN_F13R2_FB31_Pos (31U)
5419#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5420#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5428#define CRC_DR_DR_Pos (0U)
5429#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5430#define CRC_DR_DR CRC_DR_DR_Msk
5434#define CRC_IDR_IDR_Pos (0U)
5435#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5436#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5440#define CRC_CR_RESET_Pos (0U)
5441#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5442#define CRC_CR_RESET CRC_CR_RESET_Msk
5450#define DAC_CR_EN1_Pos (0U)
5451#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5452#define DAC_CR_EN1 DAC_CR_EN1_Msk
5453#define DAC_CR_BOFF1_Pos (1U)
5454#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5455#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5456#define DAC_CR_TEN1_Pos (2U)
5457#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5458#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5460#define DAC_CR_TSEL1_Pos (3U)
5461#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5462#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5463#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5464#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5465#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5467#define DAC_CR_WAVE1_Pos (6U)
5468#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5469#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5470#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5471#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5473#define DAC_CR_MAMP1_Pos (8U)
5474#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5475#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5476#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5477#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5478#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5479#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5481#define DAC_CR_DMAEN1_Pos (12U)
5482#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5483#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5484#define DAC_CR_DMAUDRIE1_Pos (13U)
5485#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5486#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5487#define DAC_CR_EN2_Pos (16U)
5488#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5489#define DAC_CR_EN2 DAC_CR_EN2_Msk
5490#define DAC_CR_BOFF2_Pos (17U)
5491#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5492#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5493#define DAC_CR_TEN2_Pos (18U)
5494#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5495#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5497#define DAC_CR_TSEL2_Pos (19U)
5498#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5499#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5500#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5501#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5502#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5504#define DAC_CR_WAVE2_Pos (22U)
5505#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5506#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5507#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5508#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5510#define DAC_CR_MAMP2_Pos (24U)
5511#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5512#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5513#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5514#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5515#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5516#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5518#define DAC_CR_DMAEN2_Pos (28U)
5519#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5520#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5521#define DAC_CR_DMAUDRIE2_Pos (29U)
5522#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5523#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5526#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5527#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5528#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5529#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5530#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5531#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5534#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5535#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5536#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5539#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5540#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5541#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5544#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5545#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5546#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5549#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5550#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5551#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5554#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5555#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5556#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5559#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5560#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5561#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5564#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5565#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5566#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5567#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5568#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5569#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5572#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5573#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5574#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5575#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5576#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5577#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5580#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5581#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5582#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5583#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5584#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5585#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5588#define DAC_DOR1_DACC1DOR_Pos (0U)
5589#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5590#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5593#define DAC_DOR2_DACC2DOR_Pos (0U)
5594#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5595#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5598#define DAC_SR_DMAUDR1_Pos (13U)
5599#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5600#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5601#define DAC_SR_DMAUDR2_Pos (29U)
5602#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5603#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5617#define DCMI_CR_CAPTURE_Pos (0U)
5618#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
5619#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5620#define DCMI_CR_CM_Pos (1U)
5621#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
5622#define DCMI_CR_CM DCMI_CR_CM_Msk
5623#define DCMI_CR_CROP_Pos (2U)
5624#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
5625#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5626#define DCMI_CR_JPEG_Pos (3U)
5627#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
5628#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5629#define DCMI_CR_ESS_Pos (4U)
5630#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
5631#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5632#define DCMI_CR_PCKPOL_Pos (5U)
5633#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
5634#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5635#define DCMI_CR_HSPOL_Pos (6U)
5636#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
5637#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5638#define DCMI_CR_VSPOL_Pos (7U)
5639#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
5640#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5641#define DCMI_CR_FCRC_0 0x00000100U
5642#define DCMI_CR_FCRC_1 0x00000200U
5643#define DCMI_CR_EDM_0 0x00000400U
5644#define DCMI_CR_EDM_1 0x00000800U
5645#define DCMI_CR_CRE_Pos (12U)
5646#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
5647#define DCMI_CR_CRE DCMI_CR_CRE_Msk
5648#define DCMI_CR_ENABLE_Pos (14U)
5649#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
5650#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5653#define DCMI_SR_HSYNC_Pos (0U)
5654#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
5655#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5656#define DCMI_SR_VSYNC_Pos (1U)
5657#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
5658#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5659#define DCMI_SR_FNE_Pos (2U)
5660#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
5661#define DCMI_SR_FNE DCMI_SR_FNE_Msk
5664#define DCMI_RIS_FRAME_RIS_Pos (0U)
5665#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
5666#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5667#define DCMI_RIS_OVR_RIS_Pos (1U)
5668#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
5669#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5670#define DCMI_RIS_ERR_RIS_Pos (2U)
5671#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
5672#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5673#define DCMI_RIS_VSYNC_RIS_Pos (3U)
5674#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
5675#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5676#define DCMI_RIS_LINE_RIS_Pos (4U)
5677#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
5678#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5680#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5681#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5682#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5683#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5684#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5687#define DCMI_IER_FRAME_IE_Pos (0U)
5688#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
5689#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5690#define DCMI_IER_OVR_IE_Pos (1U)
5691#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
5692#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5693#define DCMI_IER_ERR_IE_Pos (2U)
5694#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
5695#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5696#define DCMI_IER_VSYNC_IE_Pos (3U)
5697#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
5698#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5699#define DCMI_IER_LINE_IE_Pos (4U)
5700#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
5701#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5703#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5706#define DCMI_MIS_FRAME_MIS_Pos (0U)
5707#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
5708#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5709#define DCMI_MIS_OVR_MIS_Pos (1U)
5710#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
5711#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5712#define DCMI_MIS_ERR_MIS_Pos (2U)
5713#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
5714#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5715#define DCMI_MIS_VSYNC_MIS_Pos (3U)
5716#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
5717#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5718#define DCMI_MIS_LINE_MIS_Pos (4U)
5719#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
5720#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5723#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5724#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5725#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5726#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5727#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5730#define DCMI_ICR_FRAME_ISC_Pos (0U)
5731#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
5732#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5733#define DCMI_ICR_OVR_ISC_Pos (1U)
5734#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
5735#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5736#define DCMI_ICR_ERR_ISC_Pos (2U)
5737#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
5738#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5739#define DCMI_ICR_VSYNC_ISC_Pos (3U)
5740#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
5741#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5742#define DCMI_ICR_LINE_ISC_Pos (4U)
5743#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
5744#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5747#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5750#define DCMI_ESCR_FSC_Pos (0U)
5751#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
5752#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5753#define DCMI_ESCR_LSC_Pos (8U)
5754#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
5755#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5756#define DCMI_ESCR_LEC_Pos (16U)
5757#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
5758#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5759#define DCMI_ESCR_FEC_Pos (24U)
5760#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
5761#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5764#define DCMI_ESUR_FSU_Pos (0U)
5765#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
5766#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5767#define DCMI_ESUR_LSU_Pos (8U)
5768#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
5769#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5770#define DCMI_ESUR_LEU_Pos (16U)
5771#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
5772#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5773#define DCMI_ESUR_FEU_Pos (24U)
5774#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
5775#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5778#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5779#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
5780#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5781#define DCMI_CWSTRT_VST_Pos (16U)
5782#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
5783#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5786#define DCMI_CWSIZE_CAPCNT_Pos (0U)
5787#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
5788#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5789#define DCMI_CWSIZE_VLINE_Pos (16U)
5790#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
5791#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5794#define DCMI_DR_BYTE0_Pos (0U)
5795#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
5796#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5797#define DCMI_DR_BYTE1_Pos (8U)
5798#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
5799#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5800#define DCMI_DR_BYTE2_Pos (16U)
5801#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
5802#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5803#define DCMI_DR_BYTE3_Pos (24U)
5804#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
5805#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5813#define DMA_SxCR_CHSEL_Pos (25U)
5814#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
5815#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5816#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
5817#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
5818#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
5819#define DMA_SxCR_MBURST_Pos (23U)
5820#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
5821#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5822#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
5823#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
5824#define DMA_SxCR_PBURST_Pos (21U)
5825#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
5826#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5827#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
5828#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
5829#define DMA_SxCR_CT_Pos (19U)
5830#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
5831#define DMA_SxCR_CT DMA_SxCR_CT_Msk
5832#define DMA_SxCR_DBM_Pos (18U)
5833#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
5834#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5835#define DMA_SxCR_PL_Pos (16U)
5836#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
5837#define DMA_SxCR_PL DMA_SxCR_PL_Msk
5838#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
5839#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
5840#define DMA_SxCR_PINCOS_Pos (15U)
5841#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
5842#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5843#define DMA_SxCR_MSIZE_Pos (13U)
5844#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
5845#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5846#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
5847#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
5848#define DMA_SxCR_PSIZE_Pos (11U)
5849#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
5850#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5851#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
5852#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
5853#define DMA_SxCR_MINC_Pos (10U)
5854#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
5855#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
5856#define DMA_SxCR_PINC_Pos (9U)
5857#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
5858#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
5859#define DMA_SxCR_CIRC_Pos (8U)
5860#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
5861#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
5862#define DMA_SxCR_DIR_Pos (6U)
5863#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
5864#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
5865#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
5866#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
5867#define DMA_SxCR_PFCTRL_Pos (5U)
5868#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
5869#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
5870#define DMA_SxCR_TCIE_Pos (4U)
5871#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
5872#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
5873#define DMA_SxCR_HTIE_Pos (3U)
5874#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
5875#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
5876#define DMA_SxCR_TEIE_Pos (2U)
5877#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
5878#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
5879#define DMA_SxCR_DMEIE_Pos (1U)
5880#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
5881#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
5882#define DMA_SxCR_EN_Pos (0U)
5883#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
5884#define DMA_SxCR_EN DMA_SxCR_EN_Msk
5887#define DMA_SxCR_ACK_Pos (20U)
5888#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
5889#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
5892#define DMA_SxNDT_Pos (0U)
5893#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
5894#define DMA_SxNDT DMA_SxNDT_Msk
5895#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
5896#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
5897#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
5898#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
5899#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
5900#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
5901#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
5902#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
5903#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
5904#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
5905#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
5906#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
5907#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
5908#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
5909#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
5910#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
5913#define DMA_SxFCR_FEIE_Pos (7U)
5914#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
5915#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
5916#define DMA_SxFCR_FS_Pos (3U)
5917#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
5918#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
5919#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
5920#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
5921#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
5922#define DMA_SxFCR_DMDIS_Pos (2U)
5923#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
5924#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
5925#define DMA_SxFCR_FTH_Pos (0U)
5926#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
5927#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
5928#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
5929#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
5932#define DMA_LISR_TCIF3_Pos (27U)
5933#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
5934#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
5935#define DMA_LISR_HTIF3_Pos (26U)
5936#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
5937#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
5938#define DMA_LISR_TEIF3_Pos (25U)
5939#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
5940#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
5941#define DMA_LISR_DMEIF3_Pos (24U)
5942#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
5943#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
5944#define DMA_LISR_FEIF3_Pos (22U)
5945#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
5946#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
5947#define DMA_LISR_TCIF2_Pos (21U)
5948#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
5949#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
5950#define DMA_LISR_HTIF2_Pos (20U)
5951#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
5952#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
5953#define DMA_LISR_TEIF2_Pos (19U)
5954#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
5955#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
5956#define DMA_LISR_DMEIF2_Pos (18U)
5957#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
5958#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
5959#define DMA_LISR_FEIF2_Pos (16U)
5960#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
5961#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
5962#define DMA_LISR_TCIF1_Pos (11U)
5963#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
5964#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
5965#define DMA_LISR_HTIF1_Pos (10U)
5966#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
5967#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
5968#define DMA_LISR_TEIF1_Pos (9U)
5969#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
5970#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
5971#define DMA_LISR_DMEIF1_Pos (8U)
5972#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
5973#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
5974#define DMA_LISR_FEIF1_Pos (6U)
5975#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
5976#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
5977#define DMA_LISR_TCIF0_Pos (5U)
5978#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
5979#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
5980#define DMA_LISR_HTIF0_Pos (4U)
5981#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
5982#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
5983#define DMA_LISR_TEIF0_Pos (3U)
5984#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
5985#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
5986#define DMA_LISR_DMEIF0_Pos (2U)
5987#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
5988#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
5989#define DMA_LISR_FEIF0_Pos (0U)
5990#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
5991#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
5994#define DMA_HISR_TCIF7_Pos (27U)
5995#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
5996#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
5997#define DMA_HISR_HTIF7_Pos (26U)
5998#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
5999#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6000#define DMA_HISR_TEIF7_Pos (25U)
6001#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6002#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6003#define DMA_HISR_DMEIF7_Pos (24U)
6004#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6005#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6006#define DMA_HISR_FEIF7_Pos (22U)
6007#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6008#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6009#define DMA_HISR_TCIF6_Pos (21U)
6010#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6011#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6012#define DMA_HISR_HTIF6_Pos (20U)
6013#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6014#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6015#define DMA_HISR_TEIF6_Pos (19U)
6016#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6017#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6018#define DMA_HISR_DMEIF6_Pos (18U)
6019#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6020#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6021#define DMA_HISR_FEIF6_Pos (16U)
6022#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6023#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6024#define DMA_HISR_TCIF5_Pos (11U)
6025#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6026#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6027#define DMA_HISR_HTIF5_Pos (10U)
6028#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6029#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6030#define DMA_HISR_TEIF5_Pos (9U)
6031#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6032#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6033#define DMA_HISR_DMEIF5_Pos (8U)
6034#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6035#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6036#define DMA_HISR_FEIF5_Pos (6U)
6037#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6038#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6039#define DMA_HISR_TCIF4_Pos (5U)
6040#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6041#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6042#define DMA_HISR_HTIF4_Pos (4U)
6043#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6044#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6045#define DMA_HISR_TEIF4_Pos (3U)
6046#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6047#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6048#define DMA_HISR_DMEIF4_Pos (2U)
6049#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6050#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6051#define DMA_HISR_FEIF4_Pos (0U)
6052#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6053#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6056#define DMA_LIFCR_CTCIF3_Pos (27U)
6057#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6058#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6059#define DMA_LIFCR_CHTIF3_Pos (26U)
6060#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6061#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6062#define DMA_LIFCR_CTEIF3_Pos (25U)
6063#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6064#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6065#define DMA_LIFCR_CDMEIF3_Pos (24U)
6066#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6067#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6068#define DMA_LIFCR_CFEIF3_Pos (22U)
6069#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6070#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6071#define DMA_LIFCR_CTCIF2_Pos (21U)
6072#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6073#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6074#define DMA_LIFCR_CHTIF2_Pos (20U)
6075#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6076#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6077#define DMA_LIFCR_CTEIF2_Pos (19U)
6078#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6079#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6080#define DMA_LIFCR_CDMEIF2_Pos (18U)
6081#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6082#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6083#define DMA_LIFCR_CFEIF2_Pos (16U)
6084#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6085#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6086#define DMA_LIFCR_CTCIF1_Pos (11U)
6087#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6088#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6089#define DMA_LIFCR_CHTIF1_Pos (10U)
6090#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6091#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6092#define DMA_LIFCR_CTEIF1_Pos (9U)
6093#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6094#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6095#define DMA_LIFCR_CDMEIF1_Pos (8U)
6096#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6097#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6098#define DMA_LIFCR_CFEIF1_Pos (6U)
6099#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6100#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6101#define DMA_LIFCR_CTCIF0_Pos (5U)
6102#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6103#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6104#define DMA_LIFCR_CHTIF0_Pos (4U)
6105#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6106#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6107#define DMA_LIFCR_CTEIF0_Pos (3U)
6108#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6109#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6110#define DMA_LIFCR_CDMEIF0_Pos (2U)
6111#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6112#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6113#define DMA_LIFCR_CFEIF0_Pos (0U)
6114#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6115#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6118#define DMA_HIFCR_CTCIF7_Pos (27U)
6119#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6120#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6121#define DMA_HIFCR_CHTIF7_Pos (26U)
6122#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6123#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6124#define DMA_HIFCR_CTEIF7_Pos (25U)
6125#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6126#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6127#define DMA_HIFCR_CDMEIF7_Pos (24U)
6128#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6129#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6130#define DMA_HIFCR_CFEIF7_Pos (22U)
6131#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6132#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6133#define DMA_HIFCR_CTCIF6_Pos (21U)
6134#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6135#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6136#define DMA_HIFCR_CHTIF6_Pos (20U)
6137#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6138#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6139#define DMA_HIFCR_CTEIF6_Pos (19U)
6140#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6141#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6142#define DMA_HIFCR_CDMEIF6_Pos (18U)
6143#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6144#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6145#define DMA_HIFCR_CFEIF6_Pos (16U)
6146#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6147#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6148#define DMA_HIFCR_CTCIF5_Pos (11U)
6149#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6150#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6151#define DMA_HIFCR_CHTIF5_Pos (10U)
6152#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6153#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6154#define DMA_HIFCR_CTEIF5_Pos (9U)
6155#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6156#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6157#define DMA_HIFCR_CDMEIF5_Pos (8U)
6158#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6159#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6160#define DMA_HIFCR_CFEIF5_Pos (6U)
6161#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6162#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6163#define DMA_HIFCR_CTCIF4_Pos (5U)
6164#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6165#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6166#define DMA_HIFCR_CHTIF4_Pos (4U)
6167#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6168#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6169#define DMA_HIFCR_CTEIF4_Pos (3U)
6170#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6171#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6172#define DMA_HIFCR_CDMEIF4_Pos (2U)
6173#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6174#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6175#define DMA_HIFCR_CFEIF4_Pos (0U)
6176#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6177#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6180#define DMA_SxPAR_PA_Pos (0U)
6181#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6182#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6185#define DMA_SxM0AR_M0A_Pos (0U)
6186#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6187#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6190#define DMA_SxM1AR_M1A_Pos (0U)
6191#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6192#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6200#define EXTI_IMR_MR0_Pos (0U)
6201#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6202#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6203#define EXTI_IMR_MR1_Pos (1U)
6204#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6205#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6206#define EXTI_IMR_MR2_Pos (2U)
6207#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6208#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6209#define EXTI_IMR_MR3_Pos (3U)
6210#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6211#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6212#define EXTI_IMR_MR4_Pos (4U)
6213#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6214#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6215#define EXTI_IMR_MR5_Pos (5U)
6216#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6217#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6218#define EXTI_IMR_MR6_Pos (6U)
6219#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6220#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6221#define EXTI_IMR_MR7_Pos (7U)
6222#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6223#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6224#define EXTI_IMR_MR8_Pos (8U)
6225#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6226#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6227#define EXTI_IMR_MR9_Pos (9U)
6228#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6229#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6230#define EXTI_IMR_MR10_Pos (10U)
6231#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6232#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6233#define EXTI_IMR_MR11_Pos (11U)
6234#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6235#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6236#define EXTI_IMR_MR12_Pos (12U)
6237#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6238#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6239#define EXTI_IMR_MR13_Pos (13U)
6240#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6241#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6242#define EXTI_IMR_MR14_Pos (14U)
6243#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6244#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6245#define EXTI_IMR_MR15_Pos (15U)
6246#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6247#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6248#define EXTI_IMR_MR16_Pos (16U)
6249#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6250#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6251#define EXTI_IMR_MR17_Pos (17U)
6252#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6253#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6254#define EXTI_IMR_MR18_Pos (18U)
6255#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6256#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6257#define EXTI_IMR_MR19_Pos (19U)
6258#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6259#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6260#define EXTI_IMR_MR20_Pos (20U)
6261#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6262#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6263#define EXTI_IMR_MR21_Pos (21U)
6264#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6265#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6266#define EXTI_IMR_MR22_Pos (22U)
6267#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6268#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6271#define EXTI_IMR_IM0 EXTI_IMR_MR0
6272#define EXTI_IMR_IM1 EXTI_IMR_MR1
6273#define EXTI_IMR_IM2 EXTI_IMR_MR2
6274#define EXTI_IMR_IM3 EXTI_IMR_MR3
6275#define EXTI_IMR_IM4 EXTI_IMR_MR4
6276#define EXTI_IMR_IM5 EXTI_IMR_MR5
6277#define EXTI_IMR_IM6 EXTI_IMR_MR6
6278#define EXTI_IMR_IM7 EXTI_IMR_MR7
6279#define EXTI_IMR_IM8 EXTI_IMR_MR8
6280#define EXTI_IMR_IM9 EXTI_IMR_MR9
6281#define EXTI_IMR_IM10 EXTI_IMR_MR10
6282#define EXTI_IMR_IM11 EXTI_IMR_MR11
6283#define EXTI_IMR_IM12 EXTI_IMR_MR12
6284#define EXTI_IMR_IM13 EXTI_IMR_MR13
6285#define EXTI_IMR_IM14 EXTI_IMR_MR14
6286#define EXTI_IMR_IM15 EXTI_IMR_MR15
6287#define EXTI_IMR_IM16 EXTI_IMR_MR16
6288#define EXTI_IMR_IM17 EXTI_IMR_MR17
6289#define EXTI_IMR_IM18 EXTI_IMR_MR18
6290#define EXTI_IMR_IM19 EXTI_IMR_MR19
6291#define EXTI_IMR_IM20 EXTI_IMR_MR20
6292#define EXTI_IMR_IM21 EXTI_IMR_MR21
6293#define EXTI_IMR_IM22 EXTI_IMR_MR22
6294#define EXTI_IMR_IM_Pos (0U)
6295#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
6296#define EXTI_IMR_IM EXTI_IMR_IM_Msk
6299#define EXTI_EMR_MR0_Pos (0U)
6300#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6301#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6302#define EXTI_EMR_MR1_Pos (1U)
6303#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6304#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6305#define EXTI_EMR_MR2_Pos (2U)
6306#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6307#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6308#define EXTI_EMR_MR3_Pos (3U)
6309#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6310#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6311#define EXTI_EMR_MR4_Pos (4U)
6312#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6313#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6314#define EXTI_EMR_MR5_Pos (5U)
6315#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6316#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6317#define EXTI_EMR_MR6_Pos (6U)
6318#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6319#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6320#define EXTI_EMR_MR7_Pos (7U)
6321#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6322#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6323#define EXTI_EMR_MR8_Pos (8U)
6324#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6325#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6326#define EXTI_EMR_MR9_Pos (9U)
6327#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6328#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6329#define EXTI_EMR_MR10_Pos (10U)
6330#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6331#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6332#define EXTI_EMR_MR11_Pos (11U)
6333#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6334#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6335#define EXTI_EMR_MR12_Pos (12U)
6336#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6337#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6338#define EXTI_EMR_MR13_Pos (13U)
6339#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6340#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6341#define EXTI_EMR_MR14_Pos (14U)
6342#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6343#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6344#define EXTI_EMR_MR15_Pos (15U)
6345#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6346#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6347#define EXTI_EMR_MR16_Pos (16U)
6348#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6349#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6350#define EXTI_EMR_MR17_Pos (17U)
6351#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6352#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6353#define EXTI_EMR_MR18_Pos (18U)
6354#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6355#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6356#define EXTI_EMR_MR19_Pos (19U)
6357#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6358#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6359#define EXTI_EMR_MR20_Pos (20U)
6360#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6361#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6362#define EXTI_EMR_MR21_Pos (21U)
6363#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6364#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6365#define EXTI_EMR_MR22_Pos (22U)
6366#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6367#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6370#define EXTI_EMR_EM0 EXTI_EMR_MR0
6371#define EXTI_EMR_EM1 EXTI_EMR_MR1
6372#define EXTI_EMR_EM2 EXTI_EMR_MR2
6373#define EXTI_EMR_EM3 EXTI_EMR_MR3
6374#define EXTI_EMR_EM4 EXTI_EMR_MR4
6375#define EXTI_EMR_EM5 EXTI_EMR_MR5
6376#define EXTI_EMR_EM6 EXTI_EMR_MR6
6377#define EXTI_EMR_EM7 EXTI_EMR_MR7
6378#define EXTI_EMR_EM8 EXTI_EMR_MR8
6379#define EXTI_EMR_EM9 EXTI_EMR_MR9
6380#define EXTI_EMR_EM10 EXTI_EMR_MR10
6381#define EXTI_EMR_EM11 EXTI_EMR_MR11
6382#define EXTI_EMR_EM12 EXTI_EMR_MR12
6383#define EXTI_EMR_EM13 EXTI_EMR_MR13
6384#define EXTI_EMR_EM14 EXTI_EMR_MR14
6385#define EXTI_EMR_EM15 EXTI_EMR_MR15
6386#define EXTI_EMR_EM16 EXTI_EMR_MR16
6387#define EXTI_EMR_EM17 EXTI_EMR_MR17
6388#define EXTI_EMR_EM18 EXTI_EMR_MR18
6389#define EXTI_EMR_EM19 EXTI_EMR_MR19
6390#define EXTI_EMR_EM20 EXTI_EMR_MR20
6391#define EXTI_EMR_EM21 EXTI_EMR_MR21
6392#define EXTI_EMR_EM22 EXTI_EMR_MR22
6395#define EXTI_RTSR_TR0_Pos (0U)
6396#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6397#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6398#define EXTI_RTSR_TR1_Pos (1U)
6399#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6400#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6401#define EXTI_RTSR_TR2_Pos (2U)
6402#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6403#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6404#define EXTI_RTSR_TR3_Pos (3U)
6405#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6406#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6407#define EXTI_RTSR_TR4_Pos (4U)
6408#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6409#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6410#define EXTI_RTSR_TR5_Pos (5U)
6411#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6412#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6413#define EXTI_RTSR_TR6_Pos (6U)
6414#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6415#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6416#define EXTI_RTSR_TR7_Pos (7U)
6417#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6418#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6419#define EXTI_RTSR_TR8_Pos (8U)
6420#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6421#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6422#define EXTI_RTSR_TR9_Pos (9U)
6423#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6424#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6425#define EXTI_RTSR_TR10_Pos (10U)
6426#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6427#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6428#define EXTI_RTSR_TR11_Pos (11U)
6429#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6430#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6431#define EXTI_RTSR_TR12_Pos (12U)
6432#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6433#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6434#define EXTI_RTSR_TR13_Pos (13U)
6435#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6436#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6437#define EXTI_RTSR_TR14_Pos (14U)
6438#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6439#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6440#define EXTI_RTSR_TR15_Pos (15U)
6441#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6442#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6443#define EXTI_RTSR_TR16_Pos (16U)
6444#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6445#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6446#define EXTI_RTSR_TR17_Pos (17U)
6447#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6448#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6449#define EXTI_RTSR_TR18_Pos (18U)
6450#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6451#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6452#define EXTI_RTSR_TR19_Pos (19U)
6453#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6454#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6455#define EXTI_RTSR_TR20_Pos (20U)
6456#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6457#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6458#define EXTI_RTSR_TR21_Pos (21U)
6459#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6460#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6461#define EXTI_RTSR_TR22_Pos (22U)
6462#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6463#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6466#define EXTI_FTSR_TR0_Pos (0U)
6467#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6468#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6469#define EXTI_FTSR_TR1_Pos (1U)
6470#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6471#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6472#define EXTI_FTSR_TR2_Pos (2U)
6473#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6474#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6475#define EXTI_FTSR_TR3_Pos (3U)
6476#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6477#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6478#define EXTI_FTSR_TR4_Pos (4U)
6479#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6480#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6481#define EXTI_FTSR_TR5_Pos (5U)
6482#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6483#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6484#define EXTI_FTSR_TR6_Pos (6U)
6485#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6486#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6487#define EXTI_FTSR_TR7_Pos (7U)
6488#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6489#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6490#define EXTI_FTSR_TR8_Pos (8U)
6491#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6492#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6493#define EXTI_FTSR_TR9_Pos (9U)
6494#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6495#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6496#define EXTI_FTSR_TR10_Pos (10U)
6497#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6498#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6499#define EXTI_FTSR_TR11_Pos (11U)
6500#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6501#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6502#define EXTI_FTSR_TR12_Pos (12U)
6503#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6504#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6505#define EXTI_FTSR_TR13_Pos (13U)
6506#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6507#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6508#define EXTI_FTSR_TR14_Pos (14U)
6509#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6510#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6511#define EXTI_FTSR_TR15_Pos (15U)
6512#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6513#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6514#define EXTI_FTSR_TR16_Pos (16U)
6515#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6516#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6517#define EXTI_FTSR_TR17_Pos (17U)
6518#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6519#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6520#define EXTI_FTSR_TR18_Pos (18U)
6521#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6522#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6523#define EXTI_FTSR_TR19_Pos (19U)
6524#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
6525#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
6526#define EXTI_FTSR_TR20_Pos (20U)
6527#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
6528#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
6529#define EXTI_FTSR_TR21_Pos (21U)
6530#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
6531#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
6532#define EXTI_FTSR_TR22_Pos (22U)
6533#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
6534#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
6537#define EXTI_SWIER_SWIER0_Pos (0U)
6538#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
6539#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
6540#define EXTI_SWIER_SWIER1_Pos (1U)
6541#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
6542#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
6543#define EXTI_SWIER_SWIER2_Pos (2U)
6544#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
6545#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
6546#define EXTI_SWIER_SWIER3_Pos (3U)
6547#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
6548#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
6549#define EXTI_SWIER_SWIER4_Pos (4U)
6550#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
6551#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
6552#define EXTI_SWIER_SWIER5_Pos (5U)
6553#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
6554#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
6555#define EXTI_SWIER_SWIER6_Pos (6U)
6556#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
6557#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
6558#define EXTI_SWIER_SWIER7_Pos (7U)
6559#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
6560#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
6561#define EXTI_SWIER_SWIER8_Pos (8U)
6562#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
6563#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
6564#define EXTI_SWIER_SWIER9_Pos (9U)
6565#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
6566#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
6567#define EXTI_SWIER_SWIER10_Pos (10U)
6568#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
6569#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
6570#define EXTI_SWIER_SWIER11_Pos (11U)
6571#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
6572#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
6573#define EXTI_SWIER_SWIER12_Pos (12U)
6574#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
6575#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
6576#define EXTI_SWIER_SWIER13_Pos (13U)
6577#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
6578#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
6579#define EXTI_SWIER_SWIER14_Pos (14U)
6580#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
6581#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
6582#define EXTI_SWIER_SWIER15_Pos (15U)
6583#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
6584#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
6585#define EXTI_SWIER_SWIER16_Pos (16U)
6586#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
6587#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
6588#define EXTI_SWIER_SWIER17_Pos (17U)
6589#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
6590#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
6591#define EXTI_SWIER_SWIER18_Pos (18U)
6592#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
6593#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
6594#define EXTI_SWIER_SWIER19_Pos (19U)
6595#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
6596#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
6597#define EXTI_SWIER_SWIER20_Pos (20U)
6598#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
6599#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
6600#define EXTI_SWIER_SWIER21_Pos (21U)
6601#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
6602#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
6603#define EXTI_SWIER_SWIER22_Pos (22U)
6604#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
6605#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
6608#define EXTI_PR_PR0_Pos (0U)
6609#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
6610#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
6611#define EXTI_PR_PR1_Pos (1U)
6612#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
6613#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
6614#define EXTI_PR_PR2_Pos (2U)
6615#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
6616#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
6617#define EXTI_PR_PR3_Pos (3U)
6618#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
6619#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
6620#define EXTI_PR_PR4_Pos (4U)
6621#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
6622#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
6623#define EXTI_PR_PR5_Pos (5U)
6624#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
6625#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
6626#define EXTI_PR_PR6_Pos (6U)
6627#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
6628#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
6629#define EXTI_PR_PR7_Pos (7U)
6630#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
6631#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
6632#define EXTI_PR_PR8_Pos (8U)
6633#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
6634#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
6635#define EXTI_PR_PR9_Pos (9U)
6636#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
6637#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
6638#define EXTI_PR_PR10_Pos (10U)
6639#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
6640#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
6641#define EXTI_PR_PR11_Pos (11U)
6642#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
6643#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
6644#define EXTI_PR_PR12_Pos (12U)
6645#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
6646#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
6647#define EXTI_PR_PR13_Pos (13U)
6648#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
6649#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
6650#define EXTI_PR_PR14_Pos (14U)
6651#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
6652#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
6653#define EXTI_PR_PR15_Pos (15U)
6654#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
6655#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
6656#define EXTI_PR_PR16_Pos (16U)
6657#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
6658#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
6659#define EXTI_PR_PR17_Pos (17U)
6660#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
6661#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
6662#define EXTI_PR_PR18_Pos (18U)
6663#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
6664#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
6665#define EXTI_PR_PR19_Pos (19U)
6666#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
6667#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
6668#define EXTI_PR_PR20_Pos (20U)
6669#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
6670#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
6671#define EXTI_PR_PR21_Pos (21U)
6672#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
6673#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
6674#define EXTI_PR_PR22_Pos (22U)
6675#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
6676#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
6684#define FLASH_ACR_LATENCY_Pos (0U)
6685#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
6686#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6687#define FLASH_ACR_LATENCY_0WS 0x00000000U
6688#define FLASH_ACR_LATENCY_1WS 0x00000001U
6689#define FLASH_ACR_LATENCY_2WS 0x00000002U
6690#define FLASH_ACR_LATENCY_3WS 0x00000003U
6691#define FLASH_ACR_LATENCY_4WS 0x00000004U
6692#define FLASH_ACR_LATENCY_5WS 0x00000005U
6693#define FLASH_ACR_LATENCY_6WS 0x00000006U
6694#define FLASH_ACR_LATENCY_7WS 0x00000007U
6696#define FLASH_ACR_PRFTEN_Pos (8U)
6697#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
6698#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6699#define FLASH_ACR_ICEN_Pos (9U)
6700#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
6701#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6702#define FLASH_ACR_DCEN_Pos (10U)
6703#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
6704#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6705#define FLASH_ACR_ICRST_Pos (11U)
6706#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
6707#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6708#define FLASH_ACR_DCRST_Pos (12U)
6709#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
6710#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6711#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6712#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
6713#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6714#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6715#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
6716#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6719#define FLASH_SR_EOP_Pos (0U)
6720#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6721#define FLASH_SR_EOP FLASH_SR_EOP_Msk
6722#define FLASH_SR_SOP_Pos (1U)
6723#define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos)
6724#define FLASH_SR_SOP FLASH_SR_SOP_Msk
6725#define FLASH_SR_WRPERR_Pos (4U)
6726#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
6727#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6728#define FLASH_SR_PGAERR_Pos (5U)
6729#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
6730#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6731#define FLASH_SR_PGPERR_Pos (6U)
6732#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
6733#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6734#define FLASH_SR_PGSERR_Pos (7U)
6735#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
6736#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6737#define FLASH_SR_BSY_Pos (16U)
6738#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6739#define FLASH_SR_BSY FLASH_SR_BSY_Msk
6742#define FLASH_CR_PG_Pos (0U)
6743#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6744#define FLASH_CR_PG FLASH_CR_PG_Msk
6745#define FLASH_CR_SER_Pos (1U)
6746#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
6747#define FLASH_CR_SER FLASH_CR_SER_Msk
6748#define FLASH_CR_MER_Pos (2U)
6749#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
6750#define FLASH_CR_MER FLASH_CR_MER_Msk
6751#define FLASH_CR_SNB_Pos (3U)
6752#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
6753#define FLASH_CR_SNB FLASH_CR_SNB_Msk
6754#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
6755#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
6756#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
6757#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
6758#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
6759#define FLASH_CR_PSIZE_Pos (8U)
6760#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
6761#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6762#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
6763#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
6764#define FLASH_CR_STRT_Pos (16U)
6765#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6766#define FLASH_CR_STRT FLASH_CR_STRT_Msk
6767#define FLASH_CR_EOPIE_Pos (24U)
6768#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6769#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6770#define FLASH_CR_LOCK_Pos (31U)
6771#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6772#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6775#define FLASH_OPTCR_OPTLOCK_Pos (0U)
6776#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
6777#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6778#define FLASH_OPTCR_OPTSTRT_Pos (1U)
6779#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
6780#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6781#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6782#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6783#define FLASH_OPTCR_BOR_LEV_Pos (2U)
6784#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
6785#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6787#define FLASH_OPTCR_WDG_SW_Pos (5U)
6788#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
6789#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6790#define FLASH_OPTCR_nRST_STOP_Pos (6U)
6791#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
6792#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6793#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6794#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
6795#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6796#define FLASH_OPTCR_RDP_Pos (8U)
6797#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
6798#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6799#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
6800#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
6801#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
6802#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
6803#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
6804#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
6805#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
6806#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
6807#define FLASH_OPTCR_nWRP_Pos (16U)
6808#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
6809#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6810#define FLASH_OPTCR_nWRP_0 (0x001UL << FLASH_OPTCR_nWRP_Pos)
6811#define FLASH_OPTCR_nWRP_1 (0x002UL << FLASH_OPTCR_nWRP_Pos)
6812#define FLASH_OPTCR_nWRP_2 (0x004UL << FLASH_OPTCR_nWRP_Pos)
6813#define FLASH_OPTCR_nWRP_3 (0x008UL << FLASH_OPTCR_nWRP_Pos)
6814#define FLASH_OPTCR_nWRP_4 (0x010UL << FLASH_OPTCR_nWRP_Pos)
6815#define FLASH_OPTCR_nWRP_5 (0x020UL << FLASH_OPTCR_nWRP_Pos)
6816#define FLASH_OPTCR_nWRP_6 (0x040UL << FLASH_OPTCR_nWRP_Pos)
6817#define FLASH_OPTCR_nWRP_7 (0x080UL << FLASH_OPTCR_nWRP_Pos)
6818#define FLASH_OPTCR_nWRP_8 (0x100UL << FLASH_OPTCR_nWRP_Pos)
6819#define FLASH_OPTCR_nWRP_9 (0x200UL << FLASH_OPTCR_nWRP_Pos)
6820#define FLASH_OPTCR_nWRP_10 (0x400UL << FLASH_OPTCR_nWRP_Pos)
6821#define FLASH_OPTCR_nWRP_11 (0x800UL << FLASH_OPTCR_nWRP_Pos)
6829#define FSMC_BCR1_MBKEN_Pos (0U)
6830#define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)
6831#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk
6832#define FSMC_BCR1_MUXEN_Pos (1U)
6833#define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)
6834#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk
6836#define FSMC_BCR1_MTYP_Pos (2U)
6837#define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)
6838#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk
6839#define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)
6840#define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)
6842#define FSMC_BCR1_MWID_Pos (4U)
6843#define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)
6844#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk
6845#define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)
6846#define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)
6848#define FSMC_BCR1_FACCEN_Pos (6U)
6849#define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)
6850#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk
6851#define FSMC_BCR1_BURSTEN_Pos (8U)
6852#define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)
6853#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk
6854#define FSMC_BCR1_WAITPOL_Pos (9U)
6855#define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)
6856#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk
6857#define FSMC_BCR1_WRAPMOD_Pos (10U)
6858#define FSMC_BCR1_WRAPMOD_Msk (0x1UL << FSMC_BCR1_WRAPMOD_Pos)
6859#define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk
6860#define FSMC_BCR1_WAITCFG_Pos (11U)
6861#define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)
6862#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk
6863#define FSMC_BCR1_WREN_Pos (12U)
6864#define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)
6865#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk
6866#define FSMC_BCR1_WAITEN_Pos (13U)
6867#define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)
6868#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk
6869#define FSMC_BCR1_EXTMOD_Pos (14U)
6870#define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)
6871#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk
6872#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
6873#define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
6874#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk
6875#define FSMC_BCR1_CBURSTRW_Pos (19U)
6876#define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
6877#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk
6880#define FSMC_BCR2_MBKEN_Pos (0U)
6881#define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)
6882#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk
6883#define FSMC_BCR2_MUXEN_Pos (1U)
6884#define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)
6885#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk
6887#define FSMC_BCR2_MTYP_Pos (2U)
6888#define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)
6889#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk
6890#define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)
6891#define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)
6893#define FSMC_BCR2_MWID_Pos (4U)
6894#define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)
6895#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk
6896#define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)
6897#define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)
6899#define FSMC_BCR2_FACCEN_Pos (6U)
6900#define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)
6901#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk
6902#define FSMC_BCR2_BURSTEN_Pos (8U)
6903#define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)
6904#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk
6905#define FSMC_BCR2_WAITPOL_Pos (9U)
6906#define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)
6907#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk
6908#define FSMC_BCR2_WRAPMOD_Pos (10U)
6909#define FSMC_BCR2_WRAPMOD_Msk (0x1UL << FSMC_BCR2_WRAPMOD_Pos)
6910#define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk
6911#define FSMC_BCR2_WAITCFG_Pos (11U)
6912#define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)
6913#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk
6914#define FSMC_BCR2_WREN_Pos (12U)
6915#define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)
6916#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk
6917#define FSMC_BCR2_WAITEN_Pos (13U)
6918#define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)
6919#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk
6920#define FSMC_BCR2_EXTMOD_Pos (14U)
6921#define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)
6922#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk
6923#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
6924#define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
6925#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk
6926#define FSMC_BCR2_CBURSTRW_Pos (19U)
6927#define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
6928#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk
6931#define FSMC_BCR3_MBKEN_Pos (0U)
6932#define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)
6933#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk
6934#define FSMC_BCR3_MUXEN_Pos (1U)
6935#define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)
6936#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk
6938#define FSMC_BCR3_MTYP_Pos (2U)
6939#define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)
6940#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk
6941#define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)
6942#define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)
6944#define FSMC_BCR3_MWID_Pos (4U)
6945#define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)
6946#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk
6947#define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)
6948#define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)
6950#define FSMC_BCR3_FACCEN_Pos (6U)
6951#define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)
6952#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk
6953#define FSMC_BCR3_BURSTEN_Pos (8U)
6954#define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)
6955#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk
6956#define FSMC_BCR3_WAITPOL_Pos (9U)
6957#define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)
6958#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk
6959#define FSMC_BCR3_WRAPMOD_Pos (10U)
6960#define FSMC_BCR3_WRAPMOD_Msk (0x1UL << FSMC_BCR3_WRAPMOD_Pos)
6961#define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk
6962#define FSMC_BCR3_WAITCFG_Pos (11U)
6963#define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)
6964#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk
6965#define FSMC_BCR3_WREN_Pos (12U)
6966#define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)
6967#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk
6968#define FSMC_BCR3_WAITEN_Pos (13U)
6969#define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)
6970#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk
6971#define FSMC_BCR3_EXTMOD_Pos (14U)
6972#define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)
6973#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk
6974#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
6975#define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
6976#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk
6977#define FSMC_BCR3_CBURSTRW_Pos (19U)
6978#define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
6979#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk
6982#define FSMC_BCR4_MBKEN_Pos (0U)
6983#define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)
6984#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk
6985#define FSMC_BCR4_MUXEN_Pos (1U)
6986#define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)
6987#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk
6989#define FSMC_BCR4_MTYP_Pos (2U)
6990#define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)
6991#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk
6992#define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)
6993#define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)
6995#define FSMC_BCR4_MWID_Pos (4U)
6996#define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)
6997#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk
6998#define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)
6999#define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)
7001#define FSMC_BCR4_FACCEN_Pos (6U)
7002#define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)
7003#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk
7004#define FSMC_BCR4_BURSTEN_Pos (8U)
7005#define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)
7006#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk
7007#define FSMC_BCR4_WAITPOL_Pos (9U)
7008#define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)
7009#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk
7010#define FSMC_BCR4_WRAPMOD_Pos (10U)
7011#define FSMC_BCR4_WRAPMOD_Msk (0x1UL << FSMC_BCR4_WRAPMOD_Pos)
7012#define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk
7013#define FSMC_BCR4_WAITCFG_Pos (11U)
7014#define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)
7015#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk
7016#define FSMC_BCR4_WREN_Pos (12U)
7017#define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)
7018#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk
7019#define FSMC_BCR4_WAITEN_Pos (13U)
7020#define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)
7021#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk
7022#define FSMC_BCR4_EXTMOD_Pos (14U)
7023#define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)
7024#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk
7025#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
7026#define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
7027#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk
7028#define FSMC_BCR4_CBURSTRW_Pos (19U)
7029#define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
7030#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk
7033#define FSMC_BTR1_ADDSET_Pos (0U)
7034#define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)
7035#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk
7036#define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)
7037#define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)
7038#define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)
7039#define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)
7041#define FSMC_BTR1_ADDHLD_Pos (4U)
7042#define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)
7043#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk
7044#define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)
7045#define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)
7046#define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)
7047#define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)
7049#define FSMC_BTR1_DATAST_Pos (8U)
7050#define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)
7051#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk
7052#define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)
7053#define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)
7054#define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)
7055#define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)
7056#define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)
7057#define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)
7058#define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)
7059#define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)
7061#define FSMC_BTR1_BUSTURN_Pos (16U)
7062#define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)
7063#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk
7064#define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)
7065#define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)
7066#define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)
7067#define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)
7069#define FSMC_BTR1_CLKDIV_Pos (20U)
7070#define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)
7071#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk
7072#define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)
7073#define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)
7074#define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)
7075#define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)
7077#define FSMC_BTR1_DATLAT_Pos (24U)
7078#define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)
7079#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk
7080#define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)
7081#define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)
7082#define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)
7083#define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)
7085#define FSMC_BTR1_ACCMOD_Pos (28U)
7086#define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)
7087#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk
7088#define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)
7089#define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)
7092#define FSMC_BTR2_ADDSET_Pos (0U)
7093#define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)
7094#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk
7095#define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)
7096#define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)
7097#define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)
7098#define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)
7100#define FSMC_BTR2_ADDHLD_Pos (4U)
7101#define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)
7102#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk
7103#define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)
7104#define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)
7105#define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)
7106#define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)
7108#define FSMC_BTR2_DATAST_Pos (8U)
7109#define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)
7110#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk
7111#define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)
7112#define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)
7113#define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)
7114#define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)
7115#define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)
7116#define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)
7117#define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)
7118#define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)
7120#define FSMC_BTR2_BUSTURN_Pos (16U)
7121#define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)
7122#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk
7123#define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)
7124#define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)
7125#define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)
7126#define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)
7128#define FSMC_BTR2_CLKDIV_Pos (20U)
7129#define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)
7130#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk
7131#define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)
7132#define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)
7133#define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)
7134#define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)
7136#define FSMC_BTR2_DATLAT_Pos (24U)
7137#define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)
7138#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk
7139#define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)
7140#define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)
7141#define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)
7142#define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)
7144#define FSMC_BTR2_ACCMOD_Pos (28U)
7145#define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)
7146#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk
7147#define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)
7148#define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)
7151#define FSMC_BTR3_ADDSET_Pos (0U)
7152#define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)
7153#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk
7154#define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)
7155#define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)
7156#define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)
7157#define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)
7159#define FSMC_BTR3_ADDHLD_Pos (4U)
7160#define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)
7161#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk
7162#define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)
7163#define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)
7164#define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)
7165#define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)
7167#define FSMC_BTR3_DATAST_Pos (8U)
7168#define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)
7169#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk
7170#define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)
7171#define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)
7172#define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)
7173#define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)
7174#define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)
7175#define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)
7176#define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)
7177#define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)
7179#define FSMC_BTR3_BUSTURN_Pos (16U)
7180#define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)
7181#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk
7182#define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)
7183#define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)
7184#define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)
7185#define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)
7187#define FSMC_BTR3_CLKDIV_Pos (20U)
7188#define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)
7189#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk
7190#define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)
7191#define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)
7192#define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)
7193#define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)
7195#define FSMC_BTR3_DATLAT_Pos (24U)
7196#define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)
7197#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk
7198#define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)
7199#define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)
7200#define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)
7201#define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)
7203#define FSMC_BTR3_ACCMOD_Pos (28U)
7204#define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)
7205#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk
7206#define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)
7207#define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)
7210#define FSMC_BTR4_ADDSET_Pos (0U)
7211#define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)
7212#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk
7213#define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)
7214#define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)
7215#define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)
7216#define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)
7218#define FSMC_BTR4_ADDHLD_Pos (4U)
7219#define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)
7220#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk
7221#define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)
7222#define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)
7223#define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)
7224#define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)
7226#define FSMC_BTR4_DATAST_Pos (8U)
7227#define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)
7228#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk
7229#define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)
7230#define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)
7231#define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)
7232#define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)
7233#define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)
7234#define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)
7235#define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)
7236#define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)
7238#define FSMC_BTR4_BUSTURN_Pos (16U)
7239#define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)
7240#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk
7241#define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)
7242#define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)
7243#define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)
7244#define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)
7246#define FSMC_BTR4_CLKDIV_Pos (20U)
7247#define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)
7248#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk
7249#define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)
7250#define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)
7251#define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)
7252#define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)
7254#define FSMC_BTR4_DATLAT_Pos (24U)
7255#define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)
7256#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk
7257#define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)
7258#define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)
7259#define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)
7260#define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)
7262#define FSMC_BTR4_ACCMOD_Pos (28U)
7263#define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)
7264#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk
7265#define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)
7266#define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)
7269#define FSMC_BWTR1_ADDSET_Pos (0U)
7270#define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)
7271#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk
7272#define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)
7273#define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)
7274#define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)
7275#define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)
7277#define FSMC_BWTR1_ADDHLD_Pos (4U)
7278#define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
7279#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk
7280#define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
7281#define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
7282#define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
7283#define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
7285#define FSMC_BWTR1_DATAST_Pos (8U)
7286#define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)
7287#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk
7288#define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)
7289#define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)
7290#define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)
7291#define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)
7292#define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)
7293#define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)
7294#define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)
7295#define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)
7297#define FSMC_BWTR1_BUSTURN_Pos (16U)
7298#define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
7299#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk
7300#define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
7301#define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
7302#define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
7303#define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
7305#define FSMC_BWTR1_ACCMOD_Pos (28U)
7306#define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
7307#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk
7308#define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
7309#define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
7312#define FSMC_BWTR2_ADDSET_Pos (0U)
7313#define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)
7314#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk
7315#define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)
7316#define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)
7317#define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)
7318#define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)
7320#define FSMC_BWTR2_ADDHLD_Pos (4U)
7321#define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
7322#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk
7323#define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
7324#define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
7325#define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
7326#define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
7328#define FSMC_BWTR2_DATAST_Pos (8U)
7329#define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)
7330#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk
7331#define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)
7332#define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)
7333#define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)
7334#define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)
7335#define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)
7336#define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)
7337#define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)
7338#define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)
7340#define FSMC_BWTR2_BUSTURN_Pos (16U)
7341#define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
7342#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk
7343#define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
7344#define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
7345#define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
7346#define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
7348#define FSMC_BWTR2_ACCMOD_Pos (28U)
7349#define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
7350#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk
7351#define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
7352#define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
7355#define FSMC_BWTR3_ADDSET_Pos (0U)
7356#define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)
7357#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk
7358#define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)
7359#define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)
7360#define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)
7361#define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)
7363#define FSMC_BWTR3_ADDHLD_Pos (4U)
7364#define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
7365#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk
7366#define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
7367#define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
7368#define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
7369#define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
7371#define FSMC_BWTR3_DATAST_Pos (8U)
7372#define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)
7373#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk
7374#define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)
7375#define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)
7376#define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)
7377#define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)
7378#define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)
7379#define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)
7380#define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)
7381#define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)
7383#define FSMC_BWTR3_BUSTURN_Pos (16U)
7384#define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
7385#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk
7386#define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
7387#define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
7388#define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
7389#define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
7391#define FSMC_BWTR3_ACCMOD_Pos (28U)
7392#define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
7393#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk
7394#define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
7395#define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
7398#define FSMC_BWTR4_ADDSET_Pos (0U)
7399#define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)
7400#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk
7401#define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)
7402#define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)
7403#define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)
7404#define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)
7406#define FSMC_BWTR4_ADDHLD_Pos (4U)
7407#define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
7408#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk
7409#define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
7410#define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
7411#define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
7412#define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
7414#define FSMC_BWTR4_DATAST_Pos (8U)
7415#define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)
7416#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk
7417#define FSMC_BWTR4_DATAST_0 (0x01UL << FSMC_BWTR4_DATAST_Pos)
7418#define FSMC_BWTR4_DATAST_1 (0x02UL << FSMC_BWTR4_DATAST_Pos)
7419#define FSMC_BWTR4_DATAST_2 (0x04UL << FSMC_BWTR4_DATAST_Pos)
7420#define FSMC_BWTR4_DATAST_3 (0x08UL << FSMC_BWTR4_DATAST_Pos)
7421#define FSMC_BWTR4_DATAST_4 (0x10UL << FSMC_BWTR4_DATAST_Pos)
7422#define FSMC_BWTR4_DATAST_5 (0x20UL << FSMC_BWTR4_DATAST_Pos)
7423#define FSMC_BWTR4_DATAST_6 (0x40UL << FSMC_BWTR4_DATAST_Pos)
7424#define FSMC_BWTR4_DATAST_7 (0x80UL << FSMC_BWTR4_DATAST_Pos)
7426#define FSMC_BWTR4_BUSTURN_Pos (16U)
7427#define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
7428#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk
7429#define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
7430#define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
7431#define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
7432#define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
7434#define FSMC_BWTR4_ACCMOD_Pos (28U)
7435#define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
7436#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk
7437#define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
7438#define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
7441#define FSMC_PCR2_PWAITEN_Pos (1U)
7442#define FSMC_PCR2_PWAITEN_Msk (0x1UL << FSMC_PCR2_PWAITEN_Pos)
7443#define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk
7444#define FSMC_PCR2_PBKEN_Pos (2U)
7445#define FSMC_PCR2_PBKEN_Msk (0x1UL << FSMC_PCR2_PBKEN_Pos)
7446#define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk
7447#define FSMC_PCR2_PTYP_Pos (3U)
7448#define FSMC_PCR2_PTYP_Msk (0x1UL << FSMC_PCR2_PTYP_Pos)
7449#define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk
7451#define FSMC_PCR2_PWID_Pos (4U)
7452#define FSMC_PCR2_PWID_Msk (0x3UL << FSMC_PCR2_PWID_Pos)
7453#define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk
7454#define FSMC_PCR2_PWID_0 (0x1UL << FSMC_PCR2_PWID_Pos)
7455#define FSMC_PCR2_PWID_1 (0x2UL << FSMC_PCR2_PWID_Pos)
7457#define FSMC_PCR2_ECCEN_Pos (6U)
7458#define FSMC_PCR2_ECCEN_Msk (0x1UL << FSMC_PCR2_ECCEN_Pos)
7459#define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk
7461#define FSMC_PCR2_TCLR_Pos (9U)
7462#define FSMC_PCR2_TCLR_Msk (0xFUL << FSMC_PCR2_TCLR_Pos)
7463#define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk
7464#define FSMC_PCR2_TCLR_0 (0x1UL << FSMC_PCR2_TCLR_Pos)
7465#define FSMC_PCR2_TCLR_1 (0x2UL << FSMC_PCR2_TCLR_Pos)
7466#define FSMC_PCR2_TCLR_2 (0x4UL << FSMC_PCR2_TCLR_Pos)
7467#define FSMC_PCR2_TCLR_3 (0x8UL << FSMC_PCR2_TCLR_Pos)
7469#define FSMC_PCR2_TAR_Pos (13U)
7470#define FSMC_PCR2_TAR_Msk (0xFUL << FSMC_PCR2_TAR_Pos)
7471#define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk
7472#define FSMC_PCR2_TAR_0 (0x1UL << FSMC_PCR2_TAR_Pos)
7473#define FSMC_PCR2_TAR_1 (0x2UL << FSMC_PCR2_TAR_Pos)
7474#define FSMC_PCR2_TAR_2 (0x4UL << FSMC_PCR2_TAR_Pos)
7475#define FSMC_PCR2_TAR_3 (0x8UL << FSMC_PCR2_TAR_Pos)
7477#define FSMC_PCR2_ECCPS_Pos (17U)
7478#define FSMC_PCR2_ECCPS_Msk (0x7UL << FSMC_PCR2_ECCPS_Pos)
7479#define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk
7480#define FSMC_PCR2_ECCPS_0 (0x1UL << FSMC_PCR2_ECCPS_Pos)
7481#define FSMC_PCR2_ECCPS_1 (0x2UL << FSMC_PCR2_ECCPS_Pos)
7482#define FSMC_PCR2_ECCPS_2 (0x4UL << FSMC_PCR2_ECCPS_Pos)
7485#define FSMC_PCR3_PWAITEN_Pos (1U)
7486#define FSMC_PCR3_PWAITEN_Msk (0x1UL << FSMC_PCR3_PWAITEN_Pos)
7487#define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk
7488#define FSMC_PCR3_PBKEN_Pos (2U)
7489#define FSMC_PCR3_PBKEN_Msk (0x1UL << FSMC_PCR3_PBKEN_Pos)
7490#define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk
7491#define FSMC_PCR3_PTYP_Pos (3U)
7492#define FSMC_PCR3_PTYP_Msk (0x1UL << FSMC_PCR3_PTYP_Pos)
7493#define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk
7495#define FSMC_PCR3_PWID_Pos (4U)
7496#define FSMC_PCR3_PWID_Msk (0x3UL << FSMC_PCR3_PWID_Pos)
7497#define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk
7498#define FSMC_PCR3_PWID_0 (0x1UL << FSMC_PCR3_PWID_Pos)
7499#define FSMC_PCR3_PWID_1 (0x2UL << FSMC_PCR3_PWID_Pos)
7501#define FSMC_PCR3_ECCEN_Pos (6U)
7502#define FSMC_PCR3_ECCEN_Msk (0x1UL << FSMC_PCR3_ECCEN_Pos)
7503#define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk
7505#define FSMC_PCR3_TCLR_Pos (9U)
7506#define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos)
7507#define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk
7508#define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos)
7509#define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos)
7510#define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos)
7511#define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos)
7513#define FSMC_PCR3_TAR_Pos (13U)
7514#define FSMC_PCR3_TAR_Msk (0xFUL << FSMC_PCR3_TAR_Pos)
7515#define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk
7516#define FSMC_PCR3_TAR_0 (0x1UL << FSMC_PCR3_TAR_Pos)
7517#define FSMC_PCR3_TAR_1 (0x2UL << FSMC_PCR3_TAR_Pos)
7518#define FSMC_PCR3_TAR_2 (0x4UL << FSMC_PCR3_TAR_Pos)
7519#define FSMC_PCR3_TAR_3 (0x8UL << FSMC_PCR3_TAR_Pos)
7521#define FSMC_PCR3_ECCPS_Pos (17U)
7522#define FSMC_PCR3_ECCPS_Msk (0x7UL << FSMC_PCR3_ECCPS_Pos)
7523#define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk
7524#define FSMC_PCR3_ECCPS_0 (0x1UL << FSMC_PCR3_ECCPS_Pos)
7525#define FSMC_PCR3_ECCPS_1 (0x2UL << FSMC_PCR3_ECCPS_Pos)
7526#define FSMC_PCR3_ECCPS_2 (0x4UL << FSMC_PCR3_ECCPS_Pos)
7529#define FSMC_PCR4_PWAITEN_Pos (1U)
7530#define FSMC_PCR4_PWAITEN_Msk (0x1UL << FSMC_PCR4_PWAITEN_Pos)
7531#define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk
7532#define FSMC_PCR4_PBKEN_Pos (2U)
7533#define FSMC_PCR4_PBKEN_Msk (0x1UL << FSMC_PCR4_PBKEN_Pos)
7534#define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk
7535#define FSMC_PCR4_PTYP_Pos (3U)
7536#define FSMC_PCR4_PTYP_Msk (0x1UL << FSMC_PCR4_PTYP_Pos)
7537#define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk
7539#define FSMC_PCR4_PWID_Pos (4U)
7540#define FSMC_PCR4_PWID_Msk (0x3UL << FSMC_PCR4_PWID_Pos)
7541#define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk
7542#define FSMC_PCR4_PWID_0 (0x1UL << FSMC_PCR4_PWID_Pos)
7543#define FSMC_PCR4_PWID_1 (0x2UL << FSMC_PCR4_PWID_Pos)
7545#define FSMC_PCR4_ECCEN_Pos (6U)
7546#define FSMC_PCR4_ECCEN_Msk (0x1UL << FSMC_PCR4_ECCEN_Pos)
7547#define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk
7549#define FSMC_PCR4_TCLR_Pos (9U)
7550#define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos)
7551#define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk
7552#define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos)
7553#define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos)
7554#define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos)
7555#define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos)
7557#define FSMC_PCR4_TAR_Pos (13U)
7558#define FSMC_PCR4_TAR_Msk (0xFUL << FSMC_PCR4_TAR_Pos)
7559#define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk
7560#define FSMC_PCR4_TAR_0 (0x1UL << FSMC_PCR4_TAR_Pos)
7561#define FSMC_PCR4_TAR_1 (0x2UL << FSMC_PCR4_TAR_Pos)
7562#define FSMC_PCR4_TAR_2 (0x4UL << FSMC_PCR4_TAR_Pos)
7563#define FSMC_PCR4_TAR_3 (0x8UL << FSMC_PCR4_TAR_Pos)
7565#define FSMC_PCR4_ECCPS_Pos (17U)
7566#define FSMC_PCR4_ECCPS_Msk (0x7UL << FSMC_PCR4_ECCPS_Pos)
7567#define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk
7568#define FSMC_PCR4_ECCPS_0 (0x1UL << FSMC_PCR4_ECCPS_Pos)
7569#define FSMC_PCR4_ECCPS_1 (0x2UL << FSMC_PCR4_ECCPS_Pos)
7570#define FSMC_PCR4_ECCPS_2 (0x4UL << FSMC_PCR4_ECCPS_Pos)
7573#define FSMC_SR2_IRS_Pos (0U)
7574#define FSMC_SR2_IRS_Msk (0x1UL << FSMC_SR2_IRS_Pos)
7575#define FSMC_SR2_IRS FSMC_SR2_IRS_Msk
7576#define FSMC_SR2_ILS_Pos (1U)
7577#define FSMC_SR2_ILS_Msk (0x1UL << FSMC_SR2_ILS_Pos)
7578#define FSMC_SR2_ILS FSMC_SR2_ILS_Msk
7579#define FSMC_SR2_IFS_Pos (2U)
7580#define FSMC_SR2_IFS_Msk (0x1UL << FSMC_SR2_IFS_Pos)
7581#define FSMC_SR2_IFS FSMC_SR2_IFS_Msk
7582#define FSMC_SR2_IREN_Pos (3U)
7583#define FSMC_SR2_IREN_Msk (0x1UL << FSMC_SR2_IREN_Pos)
7584#define FSMC_SR2_IREN FSMC_SR2_IREN_Msk
7585#define FSMC_SR2_ILEN_Pos (4U)
7586#define FSMC_SR2_ILEN_Msk (0x1UL << FSMC_SR2_ILEN_Pos)
7587#define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk
7588#define FSMC_SR2_IFEN_Pos (5U)
7589#define FSMC_SR2_IFEN_Msk (0x1UL << FSMC_SR2_IFEN_Pos)
7590#define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk
7591#define FSMC_SR2_FEMPT_Pos (6U)
7592#define FSMC_SR2_FEMPT_Msk (0x1UL << FSMC_SR2_FEMPT_Pos)
7593#define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk
7596#define FSMC_SR3_IRS_Pos (0U)
7597#define FSMC_SR3_IRS_Msk (0x1UL << FSMC_SR3_IRS_Pos)
7598#define FSMC_SR3_IRS FSMC_SR3_IRS_Msk
7599#define FSMC_SR3_ILS_Pos (1U)
7600#define FSMC_SR3_ILS_Msk (0x1UL << FSMC_SR3_ILS_Pos)
7601#define FSMC_SR3_ILS FSMC_SR3_ILS_Msk
7602#define FSMC_SR3_IFS_Pos (2U)
7603#define FSMC_SR3_IFS_Msk (0x1UL << FSMC_SR3_IFS_Pos)
7604#define FSMC_SR3_IFS FSMC_SR3_IFS_Msk
7605#define FSMC_SR3_IREN_Pos (3U)
7606#define FSMC_SR3_IREN_Msk (0x1UL << FSMC_SR3_IREN_Pos)
7607#define FSMC_SR3_IREN FSMC_SR3_IREN_Msk
7608#define FSMC_SR3_ILEN_Pos (4U)
7609#define FSMC_SR3_ILEN_Msk (0x1UL << FSMC_SR3_ILEN_Pos)
7610#define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk
7611#define FSMC_SR3_IFEN_Pos (5U)
7612#define FSMC_SR3_IFEN_Msk (0x1UL << FSMC_SR3_IFEN_Pos)
7613#define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk
7614#define FSMC_SR3_FEMPT_Pos (6U)
7615#define FSMC_SR3_FEMPT_Msk (0x1UL << FSMC_SR3_FEMPT_Pos)
7616#define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk
7619#define FSMC_SR4_IRS_Pos (0U)
7620#define FSMC_SR4_IRS_Msk (0x1UL << FSMC_SR4_IRS_Pos)
7621#define FSMC_SR4_IRS FSMC_SR4_IRS_Msk
7622#define FSMC_SR4_ILS_Pos (1U)
7623#define FSMC_SR4_ILS_Msk (0x1UL << FSMC_SR4_ILS_Pos)
7624#define FSMC_SR4_ILS FSMC_SR4_ILS_Msk
7625#define FSMC_SR4_IFS_Pos (2U)
7626#define FSMC_SR4_IFS_Msk (0x1UL << FSMC_SR4_IFS_Pos)
7627#define FSMC_SR4_IFS FSMC_SR4_IFS_Msk
7628#define FSMC_SR4_IREN_Pos (3U)
7629#define FSMC_SR4_IREN_Msk (0x1UL << FSMC_SR4_IREN_Pos)
7630#define FSMC_SR4_IREN FSMC_SR4_IREN_Msk
7631#define FSMC_SR4_ILEN_Pos (4U)
7632#define FSMC_SR4_ILEN_Msk (0x1UL << FSMC_SR4_ILEN_Pos)
7633#define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk
7634#define FSMC_SR4_IFEN_Pos (5U)
7635#define FSMC_SR4_IFEN_Msk (0x1UL << FSMC_SR4_IFEN_Pos)
7636#define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk
7637#define FSMC_SR4_FEMPT_Pos (6U)
7638#define FSMC_SR4_FEMPT_Msk (0x1UL << FSMC_SR4_FEMPT_Pos)
7639#define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk
7642#define FSMC_PMEM2_MEMSET2_Pos (0U)
7643#define FSMC_PMEM2_MEMSET2_Msk (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)
7644#define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk
7645#define FSMC_PMEM2_MEMSET2_0 (0x01UL << FSMC_PMEM2_MEMSET2_Pos)
7646#define FSMC_PMEM2_MEMSET2_1 (0x02UL << FSMC_PMEM2_MEMSET2_Pos)
7647#define FSMC_PMEM2_MEMSET2_2 (0x04UL << FSMC_PMEM2_MEMSET2_Pos)
7648#define FSMC_PMEM2_MEMSET2_3 (0x08UL << FSMC_PMEM2_MEMSET2_Pos)
7649#define FSMC_PMEM2_MEMSET2_4 (0x10UL << FSMC_PMEM2_MEMSET2_Pos)
7650#define FSMC_PMEM2_MEMSET2_5 (0x20UL << FSMC_PMEM2_MEMSET2_Pos)
7651#define FSMC_PMEM2_MEMSET2_6 (0x40UL << FSMC_PMEM2_MEMSET2_Pos)
7652#define FSMC_PMEM2_MEMSET2_7 (0x80UL << FSMC_PMEM2_MEMSET2_Pos)
7654#define FSMC_PMEM2_MEMWAIT2_Pos (8U)
7655#define FSMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)
7656#define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk
7657#define FSMC_PMEM2_MEMWAIT2_0 (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)
7658#define FSMC_PMEM2_MEMWAIT2_1 (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)
7659#define FSMC_PMEM2_MEMWAIT2_2 (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)
7660#define FSMC_PMEM2_MEMWAIT2_3 (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)
7661#define FSMC_PMEM2_MEMWAIT2_4 (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)
7662#define FSMC_PMEM2_MEMWAIT2_5 (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)
7663#define FSMC_PMEM2_MEMWAIT2_6 (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)
7664#define FSMC_PMEM2_MEMWAIT2_7 (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)
7666#define FSMC_PMEM2_MEMHOLD2_Pos (16U)
7667#define FSMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)
7668#define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk
7669#define FSMC_PMEM2_MEMHOLD2_0 (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)
7670#define FSMC_PMEM2_MEMHOLD2_1 (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)
7671#define FSMC_PMEM2_MEMHOLD2_2 (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)
7672#define FSMC_PMEM2_MEMHOLD2_3 (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)
7673#define FSMC_PMEM2_MEMHOLD2_4 (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)
7674#define FSMC_PMEM2_MEMHOLD2_5 (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)
7675#define FSMC_PMEM2_MEMHOLD2_6 (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)
7676#define FSMC_PMEM2_MEMHOLD2_7 (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)
7678#define FSMC_PMEM2_MEMHIZ2_Pos (24U)
7679#define FSMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)
7680#define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk
7681#define FSMC_PMEM2_MEMHIZ2_0 (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)
7682#define FSMC_PMEM2_MEMHIZ2_1 (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)
7683#define FSMC_PMEM2_MEMHIZ2_2 (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)
7684#define FSMC_PMEM2_MEMHIZ2_3 (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)
7685#define FSMC_PMEM2_MEMHIZ2_4 (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)
7686#define FSMC_PMEM2_MEMHIZ2_5 (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)
7687#define FSMC_PMEM2_MEMHIZ2_6 (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)
7688#define FSMC_PMEM2_MEMHIZ2_7 (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)
7691#define FSMC_PMEM3_MEMSET3_Pos (0U)
7692#define FSMC_PMEM3_MEMSET3_Msk (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)
7693#define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk
7694#define FSMC_PMEM3_MEMSET3_0 (0x01UL << FSMC_PMEM3_MEMSET3_Pos)
7695#define FSMC_PMEM3_MEMSET3_1 (0x02UL << FSMC_PMEM3_MEMSET3_Pos)
7696#define FSMC_PMEM3_MEMSET3_2 (0x04UL << FSMC_PMEM3_MEMSET3_Pos)
7697#define FSMC_PMEM3_MEMSET3_3 (0x08UL << FSMC_PMEM3_MEMSET3_Pos)
7698#define FSMC_PMEM3_MEMSET3_4 (0x10UL << FSMC_PMEM3_MEMSET3_Pos)
7699#define FSMC_PMEM3_MEMSET3_5 (0x20UL << FSMC_PMEM3_MEMSET3_Pos)
7700#define FSMC_PMEM3_MEMSET3_6 (0x40UL << FSMC_PMEM3_MEMSET3_Pos)
7701#define FSMC_PMEM3_MEMSET3_7 (0x80UL << FSMC_PMEM3_MEMSET3_Pos)
7703#define FSMC_PMEM3_MEMWAIT3_Pos (8U)
7704#define FSMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)
7705#define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk
7706#define FSMC_PMEM3_MEMWAIT3_0 (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)
7707#define FSMC_PMEM3_MEMWAIT3_1 (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)
7708#define FSMC_PMEM3_MEMWAIT3_2 (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)
7709#define FSMC_PMEM3_MEMWAIT3_3 (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)
7710#define FSMC_PMEM3_MEMWAIT3_4 (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)
7711#define FSMC_PMEM3_MEMWAIT3_5 (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)
7712#define FSMC_PMEM3_MEMWAIT3_6 (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)
7713#define FSMC_PMEM3_MEMWAIT3_7 (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)
7715#define FSMC_PMEM3_MEMHOLD3_Pos (16U)
7716#define FSMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)
7717#define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk
7718#define FSMC_PMEM3_MEMHOLD3_0 (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)
7719#define FSMC_PMEM3_MEMHOLD3_1 (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)
7720#define FSMC_PMEM3_MEMHOLD3_2 (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)
7721#define FSMC_PMEM3_MEMHOLD3_3 (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)
7722#define FSMC_PMEM3_MEMHOLD3_4 (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)
7723#define FSMC_PMEM3_MEMHOLD3_5 (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)
7724#define FSMC_PMEM3_MEMHOLD3_6 (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)
7725#define FSMC_PMEM3_MEMHOLD3_7 (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)
7727#define FSMC_PMEM3_MEMHIZ3_Pos (24U)
7728#define FSMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)
7729#define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk
7730#define FSMC_PMEM3_MEMHIZ3_0 (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)
7731#define FSMC_PMEM3_MEMHIZ3_1 (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)
7732#define FSMC_PMEM3_MEMHIZ3_2 (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)
7733#define FSMC_PMEM3_MEMHIZ3_3 (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)
7734#define FSMC_PMEM3_MEMHIZ3_4 (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)
7735#define FSMC_PMEM3_MEMHIZ3_5 (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)
7736#define FSMC_PMEM3_MEMHIZ3_6 (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)
7737#define FSMC_PMEM3_MEMHIZ3_7 (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)
7740#define FSMC_PMEM4_MEMSET4_Pos (0U)
7741#define FSMC_PMEM4_MEMSET4_Msk (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)
7742#define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk
7743#define FSMC_PMEM4_MEMSET4_0 (0x01UL << FSMC_PMEM4_MEMSET4_Pos)
7744#define FSMC_PMEM4_MEMSET4_1 (0x02UL << FSMC_PMEM4_MEMSET4_Pos)
7745#define FSMC_PMEM4_MEMSET4_2 (0x04UL << FSMC_PMEM4_MEMSET4_Pos)
7746#define FSMC_PMEM4_MEMSET4_3 (0x08UL << FSMC_PMEM4_MEMSET4_Pos)
7747#define FSMC_PMEM4_MEMSET4_4 (0x10UL << FSMC_PMEM4_MEMSET4_Pos)
7748#define FSMC_PMEM4_MEMSET4_5 (0x20UL << FSMC_PMEM4_MEMSET4_Pos)
7749#define FSMC_PMEM4_MEMSET4_6 (0x40UL << FSMC_PMEM4_MEMSET4_Pos)
7750#define FSMC_PMEM4_MEMSET4_7 (0x80UL << FSMC_PMEM4_MEMSET4_Pos)
7752#define FSMC_PMEM4_MEMWAIT4_Pos (8U)
7753#define FSMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)
7754#define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk
7755#define FSMC_PMEM4_MEMWAIT4_0 (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)
7756#define FSMC_PMEM4_MEMWAIT4_1 (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)
7757#define FSMC_PMEM4_MEMWAIT4_2 (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)
7758#define FSMC_PMEM4_MEMWAIT4_3 (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)
7759#define FSMC_PMEM4_MEMWAIT4_4 (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)
7760#define FSMC_PMEM4_MEMWAIT4_5 (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)
7761#define FSMC_PMEM4_MEMWAIT4_6 (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)
7762#define FSMC_PMEM4_MEMWAIT4_7 (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)
7764#define FSMC_PMEM4_MEMHOLD4_Pos (16U)
7765#define FSMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)
7766#define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk
7767#define FSMC_PMEM4_MEMHOLD4_0 (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)
7768#define FSMC_PMEM4_MEMHOLD4_1 (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)
7769#define FSMC_PMEM4_MEMHOLD4_2 (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)
7770#define FSMC_PMEM4_MEMHOLD4_3 (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)
7771#define FSMC_PMEM4_MEMHOLD4_4 (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)
7772#define FSMC_PMEM4_MEMHOLD4_5 (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)
7773#define FSMC_PMEM4_MEMHOLD4_6 (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)
7774#define FSMC_PMEM4_MEMHOLD4_7 (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)
7776#define FSMC_PMEM4_MEMHIZ4_Pos (24U)
7777#define FSMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)
7778#define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk
7779#define FSMC_PMEM4_MEMHIZ4_0 (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)
7780#define FSMC_PMEM4_MEMHIZ4_1 (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)
7781#define FSMC_PMEM4_MEMHIZ4_2 (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)
7782#define FSMC_PMEM4_MEMHIZ4_3 (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)
7783#define FSMC_PMEM4_MEMHIZ4_4 (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)
7784#define FSMC_PMEM4_MEMHIZ4_5 (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)
7785#define FSMC_PMEM4_MEMHIZ4_6 (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)
7786#define FSMC_PMEM4_MEMHIZ4_7 (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)
7789#define FSMC_PATT2_ATTSET2_Pos (0U)
7790#define FSMC_PATT2_ATTSET2_Msk (0xFFUL << FSMC_PATT2_ATTSET2_Pos)
7791#define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk
7792#define FSMC_PATT2_ATTSET2_0 (0x01UL << FSMC_PATT2_ATTSET2_Pos)
7793#define FSMC_PATT2_ATTSET2_1 (0x02UL << FSMC_PATT2_ATTSET2_Pos)
7794#define FSMC_PATT2_ATTSET2_2 (0x04UL << FSMC_PATT2_ATTSET2_Pos)
7795#define FSMC_PATT2_ATTSET2_3 (0x08UL << FSMC_PATT2_ATTSET2_Pos)
7796#define FSMC_PATT2_ATTSET2_4 (0x10UL << FSMC_PATT2_ATTSET2_Pos)
7797#define FSMC_PATT2_ATTSET2_5 (0x20UL << FSMC_PATT2_ATTSET2_Pos)
7798#define FSMC_PATT2_ATTSET2_6 (0x40UL << FSMC_PATT2_ATTSET2_Pos)
7799#define FSMC_PATT2_ATTSET2_7 (0x80UL << FSMC_PATT2_ATTSET2_Pos)
7801#define FSMC_PATT2_ATTWAIT2_Pos (8U)
7802#define FSMC_PATT2_ATTWAIT2_Msk (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)
7803#define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk
7804#define FSMC_PATT2_ATTWAIT2_0 (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)
7805#define FSMC_PATT2_ATTWAIT2_1 (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)
7806#define FSMC_PATT2_ATTWAIT2_2 (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)
7807#define FSMC_PATT2_ATTWAIT2_3 (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)
7808#define FSMC_PATT2_ATTWAIT2_4 (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)
7809#define FSMC_PATT2_ATTWAIT2_5 (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)
7810#define FSMC_PATT2_ATTWAIT2_6 (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)
7811#define FSMC_PATT2_ATTWAIT2_7 (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)
7813#define FSMC_PATT2_ATTHOLD2_Pos (16U)
7814#define FSMC_PATT2_ATTHOLD2_Msk (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)
7815#define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk
7816#define FSMC_PATT2_ATTHOLD2_0 (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)
7817#define FSMC_PATT2_ATTHOLD2_1 (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)
7818#define FSMC_PATT2_ATTHOLD2_2 (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)
7819#define FSMC_PATT2_ATTHOLD2_3 (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)
7820#define FSMC_PATT2_ATTHOLD2_4 (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)
7821#define FSMC_PATT2_ATTHOLD2_5 (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)
7822#define FSMC_PATT2_ATTHOLD2_6 (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)
7823#define FSMC_PATT2_ATTHOLD2_7 (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)
7825#define FSMC_PATT2_ATTHIZ2_Pos (24U)
7826#define FSMC_PATT2_ATTHIZ2_Msk (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)
7827#define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk
7828#define FSMC_PATT2_ATTHIZ2_0 (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)
7829#define FSMC_PATT2_ATTHIZ2_1 (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)
7830#define FSMC_PATT2_ATTHIZ2_2 (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)
7831#define FSMC_PATT2_ATTHIZ2_3 (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)
7832#define FSMC_PATT2_ATTHIZ2_4 (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)
7833#define FSMC_PATT2_ATTHIZ2_5 (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)
7834#define FSMC_PATT2_ATTHIZ2_6 (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)
7835#define FSMC_PATT2_ATTHIZ2_7 (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)
7838#define FSMC_PATT3_ATTSET3_Pos (0U)
7839#define FSMC_PATT3_ATTSET3_Msk (0xFFUL << FSMC_PATT3_ATTSET3_Pos)
7840#define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk
7841#define FSMC_PATT3_ATTSET3_0 (0x01UL << FSMC_PATT3_ATTSET3_Pos)
7842#define FSMC_PATT3_ATTSET3_1 (0x02UL << FSMC_PATT3_ATTSET3_Pos)
7843#define FSMC_PATT3_ATTSET3_2 (0x04UL << FSMC_PATT3_ATTSET3_Pos)
7844#define FSMC_PATT3_ATTSET3_3 (0x08UL << FSMC_PATT3_ATTSET3_Pos)
7845#define FSMC_PATT3_ATTSET3_4 (0x10UL << FSMC_PATT3_ATTSET3_Pos)
7846#define FSMC_PATT3_ATTSET3_5 (0x20UL << FSMC_PATT3_ATTSET3_Pos)
7847#define FSMC_PATT3_ATTSET3_6 (0x40UL << FSMC_PATT3_ATTSET3_Pos)
7848#define FSMC_PATT3_ATTSET3_7 (0x80UL << FSMC_PATT3_ATTSET3_Pos)
7850#define FSMC_PATT3_ATTWAIT3_Pos (8U)
7851#define FSMC_PATT3_ATTWAIT3_Msk (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)
7852#define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk
7853#define FSMC_PATT3_ATTWAIT3_0 (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)
7854#define FSMC_PATT3_ATTWAIT3_1 (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)
7855#define FSMC_PATT3_ATTWAIT3_2 (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)
7856#define FSMC_PATT3_ATTWAIT3_3 (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)
7857#define FSMC_PATT3_ATTWAIT3_4 (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)
7858#define FSMC_PATT3_ATTWAIT3_5 (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)
7859#define FSMC_PATT3_ATTWAIT3_6 (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)
7860#define FSMC_PATT3_ATTWAIT3_7 (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)
7862#define FSMC_PATT3_ATTHOLD3_Pos (16U)
7863#define FSMC_PATT3_ATTHOLD3_Msk (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)
7864#define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk
7865#define FSMC_PATT3_ATTHOLD3_0 (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)
7866#define FSMC_PATT3_ATTHOLD3_1 (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)
7867#define FSMC_PATT3_ATTHOLD3_2 (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)
7868#define FSMC_PATT3_ATTHOLD3_3 (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)
7869#define FSMC_PATT3_ATTHOLD3_4 (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)
7870#define FSMC_PATT3_ATTHOLD3_5 (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)
7871#define FSMC_PATT3_ATTHOLD3_6 (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)
7872#define FSMC_PATT3_ATTHOLD3_7 (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)
7874#define FSMC_PATT3_ATTHIZ3_Pos (24U)
7875#define FSMC_PATT3_ATTHIZ3_Msk (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)
7876#define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk
7877#define FSMC_PATT3_ATTHIZ3_0 (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)
7878#define FSMC_PATT3_ATTHIZ3_1 (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)
7879#define FSMC_PATT3_ATTHIZ3_2 (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)
7880#define FSMC_PATT3_ATTHIZ3_3 (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)
7881#define FSMC_PATT3_ATTHIZ3_4 (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)
7882#define FSMC_PATT3_ATTHIZ3_5 (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)
7883#define FSMC_PATT3_ATTHIZ3_6 (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)
7884#define FSMC_PATT3_ATTHIZ3_7 (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)
7887#define FSMC_PATT4_ATTSET4_Pos (0U)
7888#define FSMC_PATT4_ATTSET4_Msk (0xFFUL << FSMC_PATT4_ATTSET4_Pos)
7889#define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk
7890#define FSMC_PATT4_ATTSET4_0 (0x01UL << FSMC_PATT4_ATTSET4_Pos)
7891#define FSMC_PATT4_ATTSET4_1 (0x02UL << FSMC_PATT4_ATTSET4_Pos)
7892#define FSMC_PATT4_ATTSET4_2 (0x04UL << FSMC_PATT4_ATTSET4_Pos)
7893#define FSMC_PATT4_ATTSET4_3 (0x08UL << FSMC_PATT4_ATTSET4_Pos)
7894#define FSMC_PATT4_ATTSET4_4 (0x10UL << FSMC_PATT4_ATTSET4_Pos)
7895#define FSMC_PATT4_ATTSET4_5 (0x20UL << FSMC_PATT4_ATTSET4_Pos)
7896#define FSMC_PATT4_ATTSET4_6 (0x40UL << FSMC_PATT4_ATTSET4_Pos)
7897#define FSMC_PATT4_ATTSET4_7 (0x80UL << FSMC_PATT4_ATTSET4_Pos)
7899#define FSMC_PATT4_ATTWAIT4_Pos (8U)
7900#define FSMC_PATT4_ATTWAIT4_Msk (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)
7901#define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk
7902#define FSMC_PATT4_ATTWAIT4_0 (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)
7903#define FSMC_PATT4_ATTWAIT4_1 (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)
7904#define FSMC_PATT4_ATTWAIT4_2 (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)
7905#define FSMC_PATT4_ATTWAIT4_3 (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)
7906#define FSMC_PATT4_ATTWAIT4_4 (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)
7907#define FSMC_PATT4_ATTWAIT4_5 (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)
7908#define FSMC_PATT4_ATTWAIT4_6 (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)
7909#define FSMC_PATT4_ATTWAIT4_7 (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)
7911#define FSMC_PATT4_ATTHOLD4_Pos (16U)
7912#define FSMC_PATT4_ATTHOLD4_Msk (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)
7913#define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk
7914#define FSMC_PATT4_ATTHOLD4_0 (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)
7915#define FSMC_PATT4_ATTHOLD4_1 (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)
7916#define FSMC_PATT4_ATTHOLD4_2 (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)
7917#define FSMC_PATT4_ATTHOLD4_3 (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)
7918#define FSMC_PATT4_ATTHOLD4_4 (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)
7919#define FSMC_PATT4_ATTHOLD4_5 (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)
7920#define FSMC_PATT4_ATTHOLD4_6 (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)
7921#define FSMC_PATT4_ATTHOLD4_7 (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)
7923#define FSMC_PATT4_ATTHIZ4_Pos (24U)
7924#define FSMC_PATT4_ATTHIZ4_Msk (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)
7925#define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk
7926#define FSMC_PATT4_ATTHIZ4_0 (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)
7927#define FSMC_PATT4_ATTHIZ4_1 (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)
7928#define FSMC_PATT4_ATTHIZ4_2 (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)
7929#define FSMC_PATT4_ATTHIZ4_3 (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)
7930#define FSMC_PATT4_ATTHIZ4_4 (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)
7931#define FSMC_PATT4_ATTHIZ4_5 (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)
7932#define FSMC_PATT4_ATTHIZ4_6 (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)
7933#define FSMC_PATT4_ATTHIZ4_7 (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)
7936#define FSMC_PIO4_IOSET4_Pos (0U)
7937#define FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos)
7938#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk
7939#define FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos)
7940#define FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos)
7941#define FSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos)
7942#define FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos)
7943#define FSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos)
7944#define FSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos)
7945#define FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos)
7946#define FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos)
7948#define FSMC_PIO4_IOWAIT4_Pos (8U)
7949#define FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)
7950#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk
7951#define FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos)
7952#define FSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos)
7953#define FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos)
7954#define FSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos)
7955#define FSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos)
7956#define FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos)
7957#define FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos)
7958#define FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos)
7960#define FSMC_PIO4_IOHOLD4_Pos (16U)
7961#define FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)
7962#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk
7963#define FSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos)
7964#define FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos)
7965#define FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos)
7966#define FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos)
7967#define FSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos)
7968#define FSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos)
7969#define FSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos)
7970#define FSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos)
7972#define FSMC_PIO4_IOHIZ4_Pos (24U)
7973#define FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)
7974#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk
7975#define FSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos)
7976#define FSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos)
7977#define FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos)
7978#define FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos)
7979#define FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos)
7980#define FSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos)
7981#define FSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos)
7982#define FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos)
7985#define FSMC_ECCR2_ECC2_Pos (0U)
7986#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)
7987#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk
7990#define FSMC_ECCR3_ECC3_Pos (0U)
7991#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)
7992#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk
8000#define GPIO_MODER_MODE0 0x00000003U
8001#define GPIO_MODER_MODE0_0 0x00000001U
8002#define GPIO_MODER_MODE0_1 0x00000002U
8003#define GPIO_MODER_MODE1 0x0000000CU
8004#define GPIO_MODER_MODE1_0 0x00000004U
8005#define GPIO_MODER_MODE1_1 0x00000008U
8006#define GPIO_MODER_MODE2 0x00000030U
8007#define GPIO_MODER_MODE2_0 0x00000010U
8008#define GPIO_MODER_MODE2_1 0x00000020U
8009#define GPIO_MODER_MODE3 0x000000C0U
8010#define GPIO_MODER_MODE3_0 0x00000040U
8011#define GPIO_MODER_MODE3_1 0x00000080U
8012#define GPIO_MODER_MODE4 0x00000300U
8013#define GPIO_MODER_MODE4_0 0x00000100U
8014#define GPIO_MODER_MODE4_1 0x00000200U
8015#define GPIO_MODER_MODE5 0x00000C00U
8016#define GPIO_MODER_MODE5_0 0x00000400U
8017#define GPIO_MODER_MODE5_1 0x00000800U
8018#define GPIO_MODER_MODE6 0x00003000U
8019#define GPIO_MODER_MODE6_0 0x00001000U
8020#define GPIO_MODER_MODE6_1 0x00002000U
8021#define GPIO_MODER_MODE7 0x0000C000U
8022#define GPIO_MODER_MODE7_0 0x00004000U
8023#define GPIO_MODER_MODE7_1 0x00008000U
8024#define GPIO_MODER_MODE8 0x00030000U
8025#define GPIO_MODER_MODE8_0 0x00010000U
8026#define GPIO_MODER_MODE8_1 0x00020000U
8027#define GPIO_MODER_MODE9 0x000C0000U
8028#define GPIO_MODER_MODE9_0 0x00040000U
8029#define GPIO_MODER_MODE9_1 0x00080000U
8030#define GPIO_MODER_MODE10 0x00300000U
8031#define GPIO_MODER_MODE10_0 0x00100000U
8032#define GPIO_MODER_MODE10_1 0x00200000U
8033#define GPIO_MODER_MODE11 0x00C00000U
8034#define GPIO_MODER_MODE11_0 0x00400000U
8035#define GPIO_MODER_MODE11_1 0x00800000U
8036#define GPIO_MODER_MODE12 0x03000000U
8037#define GPIO_MODER_MODE12_0 0x01000000U
8038#define GPIO_MODER_MODE12_1 0x02000000U
8039#define GPIO_MODER_MODE13 0x0C000000U
8040#define GPIO_MODER_MODE13_0 0x04000000U
8041#define GPIO_MODER_MODE13_1 0x08000000U
8042#define GPIO_MODER_MODE14 0x30000000U
8043#define GPIO_MODER_MODE14_0 0x10000000U
8044#define GPIO_MODER_MODE14_1 0x20000000U
8045#define GPIO_MODER_MODE15 0xC0000000U
8046#define GPIO_MODER_MODE15_0 0x40000000U
8047#define GPIO_MODER_MODE15_1 0x80000000U
8050#define GPIO_MODER_MODER0_Pos (0U)
8051#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
8052#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8053#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
8054#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
8055#define GPIO_MODER_MODER1_Pos (2U)
8056#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
8057#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8058#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
8059#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
8060#define GPIO_MODER_MODER2_Pos (4U)
8061#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
8062#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8063#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
8064#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
8065#define GPIO_MODER_MODER3_Pos (6U)
8066#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
8067#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8068#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
8069#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
8070#define GPIO_MODER_MODER4_Pos (8U)
8071#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
8072#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8073#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
8074#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
8075#define GPIO_MODER_MODER5_Pos (10U)
8076#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
8077#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8078#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
8079#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
8080#define GPIO_MODER_MODER6_Pos (12U)
8081#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
8082#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8083#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
8084#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
8085#define GPIO_MODER_MODER7_Pos (14U)
8086#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
8087#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8088#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
8089#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
8090#define GPIO_MODER_MODER8_Pos (16U)
8091#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
8092#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8093#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
8094#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
8095#define GPIO_MODER_MODER9_Pos (18U)
8096#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
8097#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8098#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
8099#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
8100#define GPIO_MODER_MODER10_Pos (20U)
8101#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
8102#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8103#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
8104#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
8105#define GPIO_MODER_MODER11_Pos (22U)
8106#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
8107#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8108#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
8109#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
8110#define GPIO_MODER_MODER12_Pos (24U)
8111#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
8112#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8113#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
8114#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
8115#define GPIO_MODER_MODER13_Pos (26U)
8116#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
8117#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8118#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
8119#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
8120#define GPIO_MODER_MODER14_Pos (28U)
8121#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
8122#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8123#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
8124#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
8125#define GPIO_MODER_MODER15_Pos (30U)
8126#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
8127#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8128#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
8129#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
8132#define GPIO_OTYPER_OT0 0x00000001U
8133#define GPIO_OTYPER_OT1 0x00000002U
8134#define GPIO_OTYPER_OT2 0x00000004U
8135#define GPIO_OTYPER_OT3 0x00000008U
8136#define GPIO_OTYPER_OT4 0x00000010U
8137#define GPIO_OTYPER_OT5 0x00000020U
8138#define GPIO_OTYPER_OT6 0x00000040U
8139#define GPIO_OTYPER_OT7 0x00000080U
8140#define GPIO_OTYPER_OT8 0x00000100U
8141#define GPIO_OTYPER_OT9 0x00000200U
8142#define GPIO_OTYPER_OT10 0x00000400U
8143#define GPIO_OTYPER_OT11 0x00000800U
8144#define GPIO_OTYPER_OT12 0x00001000U
8145#define GPIO_OTYPER_OT13 0x00002000U
8146#define GPIO_OTYPER_OT14 0x00004000U
8147#define GPIO_OTYPER_OT15 0x00008000U
8150#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8151#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8152#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8153#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8154#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8155#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8156#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8157#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8158#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8159#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8160#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8161#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8162#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8163#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8164#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8165#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8168#define GPIO_OSPEEDR_OSPEED0 0x00000003U
8169#define GPIO_OSPEEDR_OSPEED0_0 0x00000001U
8170#define GPIO_OSPEEDR_OSPEED0_1 0x00000002U
8171#define GPIO_OSPEEDR_OSPEED1 0x0000000CU
8172#define GPIO_OSPEEDR_OSPEED1_0 0x00000004U
8173#define GPIO_OSPEEDR_OSPEED1_1 0x00000008U
8174#define GPIO_OSPEEDR_OSPEED2 0x00000030U
8175#define GPIO_OSPEEDR_OSPEED2_0 0x00000010U
8176#define GPIO_OSPEEDR_OSPEED2_1 0x00000020U
8177#define GPIO_OSPEEDR_OSPEED3 0x000000C0U
8178#define GPIO_OSPEEDR_OSPEED3_0 0x00000040U
8179#define GPIO_OSPEEDR_OSPEED3_1 0x00000080U
8180#define GPIO_OSPEEDR_OSPEED4 0x00000300U
8181#define GPIO_OSPEEDR_OSPEED4_0 0x00000100U
8182#define GPIO_OSPEEDR_OSPEED4_1 0x00000200U
8183#define GPIO_OSPEEDR_OSPEED5 0x00000C00U
8184#define GPIO_OSPEEDR_OSPEED5_0 0x00000400U
8185#define GPIO_OSPEEDR_OSPEED5_1 0x00000800U
8186#define GPIO_OSPEEDR_OSPEED6 0x00003000U
8187#define GPIO_OSPEEDR_OSPEED6_0 0x00001000U
8188#define GPIO_OSPEEDR_OSPEED6_1 0x00002000U
8189#define GPIO_OSPEEDR_OSPEED7 0x0000C000U
8190#define GPIO_OSPEEDR_OSPEED7_0 0x00004000U
8191#define GPIO_OSPEEDR_OSPEED7_1 0x00008000U
8192#define GPIO_OSPEEDR_OSPEED8 0x00030000U
8193#define GPIO_OSPEEDR_OSPEED8_0 0x00010000U
8194#define GPIO_OSPEEDR_OSPEED8_1 0x00020000U
8195#define GPIO_OSPEEDR_OSPEED9 0x000C0000U
8196#define GPIO_OSPEEDR_OSPEED9_0 0x00040000U
8197#define GPIO_OSPEEDR_OSPEED9_1 0x00080000U
8198#define GPIO_OSPEEDR_OSPEED10 0x00300000U
8199#define GPIO_OSPEEDR_OSPEED10_0 0x00100000U
8200#define GPIO_OSPEEDR_OSPEED10_1 0x00200000U
8201#define GPIO_OSPEEDR_OSPEED11 0x00C00000U
8202#define GPIO_OSPEEDR_OSPEED11_0 0x00400000U
8203#define GPIO_OSPEEDR_OSPEED11_1 0x00800000U
8204#define GPIO_OSPEEDR_OSPEED12 0x03000000U
8205#define GPIO_OSPEEDR_OSPEED12_0 0x01000000U
8206#define GPIO_OSPEEDR_OSPEED12_1 0x02000000U
8207#define GPIO_OSPEEDR_OSPEED13 0x0C000000U
8208#define GPIO_OSPEEDR_OSPEED13_0 0x04000000U
8209#define GPIO_OSPEEDR_OSPEED13_1 0x08000000U
8210#define GPIO_OSPEEDR_OSPEED14 0x30000000U
8211#define GPIO_OSPEEDR_OSPEED14_0 0x10000000U
8212#define GPIO_OSPEEDR_OSPEED14_1 0x20000000U
8213#define GPIO_OSPEEDR_OSPEED15 0xC0000000U
8214#define GPIO_OSPEEDR_OSPEED15_0 0x40000000U
8215#define GPIO_OSPEEDR_OSPEED15_1 0x80000000U
8218#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8219#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8220#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8221#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8222#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8223#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8224#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8225#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8226#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8227#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8228#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8229#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8230#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8231#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8232#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8233#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8234#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8235#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8236#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8237#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8238#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8239#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8240#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8241#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8242#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8243#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8244#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8245#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8246#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8247#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8248#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8249#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8250#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8251#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8252#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8253#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8254#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8255#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8256#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8257#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8258#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8259#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8260#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8261#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8262#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8263#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8264#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8265#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8268#define GPIO_PUPDR_PUPD0 0x00000003U
8269#define GPIO_PUPDR_PUPD0_0 0x00000001U
8270#define GPIO_PUPDR_PUPD0_1 0x00000002U
8271#define GPIO_PUPDR_PUPD1 0x0000000CU
8272#define GPIO_PUPDR_PUPD1_0 0x00000004U
8273#define GPIO_PUPDR_PUPD1_1 0x00000008U
8274#define GPIO_PUPDR_PUPD2 0x00000030U
8275#define GPIO_PUPDR_PUPD2_0 0x00000010U
8276#define GPIO_PUPDR_PUPD2_1 0x00000020U
8277#define GPIO_PUPDR_PUPD3 0x000000C0U
8278#define GPIO_PUPDR_PUPD3_0 0x00000040U
8279#define GPIO_PUPDR_PUPD3_1 0x00000080U
8280#define GPIO_PUPDR_PUPD4 0x00000300U
8281#define GPIO_PUPDR_PUPD4_0 0x00000100U
8282#define GPIO_PUPDR_PUPD4_1 0x00000200U
8283#define GPIO_PUPDR_PUPD5 0x00000C00U
8284#define GPIO_PUPDR_PUPD5_0 0x00000400U
8285#define GPIO_PUPDR_PUPD5_1 0x00000800U
8286#define GPIO_PUPDR_PUPD6 0x00003000U
8287#define GPIO_PUPDR_PUPD6_0 0x00001000U
8288#define GPIO_PUPDR_PUPD6_1 0x00002000U
8289#define GPIO_PUPDR_PUPD7 0x0000C000U
8290#define GPIO_PUPDR_PUPD7_0 0x00004000U
8291#define GPIO_PUPDR_PUPD7_1 0x00008000U
8292#define GPIO_PUPDR_PUPD8 0x00030000U
8293#define GPIO_PUPDR_PUPD8_0 0x00010000U
8294#define GPIO_PUPDR_PUPD8_1 0x00020000U
8295#define GPIO_PUPDR_PUPD9 0x000C0000U
8296#define GPIO_PUPDR_PUPD9_0 0x00040000U
8297#define GPIO_PUPDR_PUPD9_1 0x00080000U
8298#define GPIO_PUPDR_PUPD10 0x00300000U
8299#define GPIO_PUPDR_PUPD10_0 0x00100000U
8300#define GPIO_PUPDR_PUPD10_1 0x00200000U
8301#define GPIO_PUPDR_PUPD11 0x00C00000U
8302#define GPIO_PUPDR_PUPD11_0 0x00400000U
8303#define GPIO_PUPDR_PUPD11_1 0x00800000U
8304#define GPIO_PUPDR_PUPD12 0x03000000U
8305#define GPIO_PUPDR_PUPD12_0 0x01000000U
8306#define GPIO_PUPDR_PUPD12_1 0x02000000U
8307#define GPIO_PUPDR_PUPD13 0x0C000000U
8308#define GPIO_PUPDR_PUPD13_0 0x04000000U
8309#define GPIO_PUPDR_PUPD13_1 0x08000000U
8310#define GPIO_PUPDR_PUPD14 0x30000000U
8311#define GPIO_PUPDR_PUPD14_0 0x10000000U
8312#define GPIO_PUPDR_PUPD14_1 0x20000000U
8313#define GPIO_PUPDR_PUPD15 0xC0000000U
8314#define GPIO_PUPDR_PUPD15_0 0x40000000U
8315#define GPIO_PUPDR_PUPD15_1 0x80000000U
8318#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8319#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8320#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8321#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8322#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8323#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8324#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8325#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8326#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8327#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8328#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8329#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8330#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8331#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8332#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8333#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8334#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8335#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8336#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8337#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8338#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8339#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8340#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8341#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8342#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8343#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8344#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8345#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8346#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8347#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8348#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8349#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8350#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8351#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8352#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8353#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8354#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8355#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8356#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8357#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8358#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8359#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8360#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8361#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8362#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8363#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8364#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8365#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8368#define GPIO_IDR_ID0 0x00000001U
8369#define GPIO_IDR_ID1 0x00000002U
8370#define GPIO_IDR_ID2 0x00000004U
8371#define GPIO_IDR_ID3 0x00000008U
8372#define GPIO_IDR_ID4 0x00000010U
8373#define GPIO_IDR_ID5 0x00000020U
8374#define GPIO_IDR_ID6 0x00000040U
8375#define GPIO_IDR_ID7 0x00000080U
8376#define GPIO_IDR_ID8 0x00000100U
8377#define GPIO_IDR_ID9 0x00000200U
8378#define GPIO_IDR_ID10 0x00000400U
8379#define GPIO_IDR_ID11 0x00000800U
8380#define GPIO_IDR_ID12 0x00001000U
8381#define GPIO_IDR_ID13 0x00002000U
8382#define GPIO_IDR_ID14 0x00004000U
8383#define GPIO_IDR_ID15 0x00008000U
8386#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8387#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8388#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8389#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8390#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8391#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8392#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8393#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8394#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8395#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8396#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8397#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8398#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8399#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8400#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8401#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8404#define GPIO_ODR_OD0 0x00000001U
8405#define GPIO_ODR_OD1 0x00000002U
8406#define GPIO_ODR_OD2 0x00000004U
8407#define GPIO_ODR_OD3 0x00000008U
8408#define GPIO_ODR_OD4 0x00000010U
8409#define GPIO_ODR_OD5 0x00000020U
8410#define GPIO_ODR_OD6 0x00000040U
8411#define GPIO_ODR_OD7 0x00000080U
8412#define GPIO_ODR_OD8 0x00000100U
8413#define GPIO_ODR_OD9 0x00000200U
8414#define GPIO_ODR_OD10 0x00000400U
8415#define GPIO_ODR_OD11 0x00000800U
8416#define GPIO_ODR_OD12 0x00001000U
8417#define GPIO_ODR_OD13 0x00002000U
8418#define GPIO_ODR_OD14 0x00004000U
8419#define GPIO_ODR_OD15 0x00008000U
8422#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8423#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8424#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8425#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8426#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8427#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8428#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8429#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8430#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8431#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8432#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8433#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8434#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8435#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8436#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8437#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8440#define GPIO_BSRR_BS0 0x00000001U
8441#define GPIO_BSRR_BS1 0x00000002U
8442#define GPIO_BSRR_BS2 0x00000004U
8443#define GPIO_BSRR_BS3 0x00000008U
8444#define GPIO_BSRR_BS4 0x00000010U
8445#define GPIO_BSRR_BS5 0x00000020U
8446#define GPIO_BSRR_BS6 0x00000040U
8447#define GPIO_BSRR_BS7 0x00000080U
8448#define GPIO_BSRR_BS8 0x00000100U
8449#define GPIO_BSRR_BS9 0x00000200U
8450#define GPIO_BSRR_BS10 0x00000400U
8451#define GPIO_BSRR_BS11 0x00000800U
8452#define GPIO_BSRR_BS12 0x00001000U
8453#define GPIO_BSRR_BS13 0x00002000U
8454#define GPIO_BSRR_BS14 0x00004000U
8455#define GPIO_BSRR_BS15 0x00008000U
8456#define GPIO_BSRR_BR0 0x00010000U
8457#define GPIO_BSRR_BR1 0x00020000U
8458#define GPIO_BSRR_BR2 0x00040000U
8459#define GPIO_BSRR_BR3 0x00080000U
8460#define GPIO_BSRR_BR4 0x00100000U
8461#define GPIO_BSRR_BR5 0x00200000U
8462#define GPIO_BSRR_BR6 0x00400000U
8463#define GPIO_BSRR_BR7 0x00800000U
8464#define GPIO_BSRR_BR8 0x01000000U
8465#define GPIO_BSRR_BR9 0x02000000U
8466#define GPIO_BSRR_BR10 0x04000000U
8467#define GPIO_BSRR_BR11 0x08000000U
8468#define GPIO_BSRR_BR12 0x10000000U
8469#define GPIO_BSRR_BR13 0x20000000U
8470#define GPIO_BSRR_BR14 0x40000000U
8471#define GPIO_BSRR_BR15 0x80000000U
8474#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8475#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8476#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8477#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8478#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8479#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8480#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8481#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8482#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8483#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8484#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8485#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8486#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8487#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8488#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8489#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8490#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8491#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8492#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8493#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8494#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8495#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8496#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8497#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8498#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8499#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8500#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8501#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8502#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8503#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8504#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8505#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8508#define GPIO_LCKR_LCK0_Pos (0U)
8509#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8510#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8511#define GPIO_LCKR_LCK1_Pos (1U)
8512#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8513#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8514#define GPIO_LCKR_LCK2_Pos (2U)
8515#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8516#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8517#define GPIO_LCKR_LCK3_Pos (3U)
8518#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8519#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8520#define GPIO_LCKR_LCK4_Pos (4U)
8521#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8522#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8523#define GPIO_LCKR_LCK5_Pos (5U)
8524#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8525#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8526#define GPIO_LCKR_LCK6_Pos (6U)
8527#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8528#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8529#define GPIO_LCKR_LCK7_Pos (7U)
8530#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8531#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8532#define GPIO_LCKR_LCK8_Pos (8U)
8533#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8534#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8535#define GPIO_LCKR_LCK9_Pos (9U)
8536#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8537#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8538#define GPIO_LCKR_LCK10_Pos (10U)
8539#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8540#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8541#define GPIO_LCKR_LCK11_Pos (11U)
8542#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8543#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8544#define GPIO_LCKR_LCK12_Pos (12U)
8545#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8546#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8547#define GPIO_LCKR_LCK13_Pos (13U)
8548#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8549#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8550#define GPIO_LCKR_LCK14_Pos (14U)
8551#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8552#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8553#define GPIO_LCKR_LCK15_Pos (15U)
8554#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8555#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8556#define GPIO_LCKR_LCKK_Pos (16U)
8557#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8558#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8561#define GPIO_AFRL_AFSEL0 0x0000000FU
8562#define GPIO_AFRL_AFSEL0_0 0x00000001U
8563#define GPIO_AFRL_AFSEL0_1 0x00000002U
8564#define GPIO_AFRL_AFSEL0_2 0x00000004U
8565#define GPIO_AFRL_AFSEL0_3 0x00000008U
8566#define GPIO_AFRL_AFSEL1 0x000000F0U
8567#define GPIO_AFRL_AFSEL1_0 0x00000010U
8568#define GPIO_AFRL_AFSEL1_1 0x00000020U
8569#define GPIO_AFRL_AFSEL1_2 0x00000040U
8570#define GPIO_AFRL_AFSEL1_3 0x00000080U
8571#define GPIO_AFRL_AFSEL2 0x00000F00U
8572#define GPIO_AFRL_AFSEL2_0 0x00000100U
8573#define GPIO_AFRL_AFSEL2_1 0x00000200U
8574#define GPIO_AFRL_AFSEL2_2 0x00000400U
8575#define GPIO_AFRL_AFSEL2_3 0x00000800U
8576#define GPIO_AFRL_AFSEL3 0x0000F000U
8577#define GPIO_AFRL_AFSEL3_0 0x00001000U
8578#define GPIO_AFRL_AFSEL3_1 0x00002000U
8579#define GPIO_AFRL_AFSEL3_2 0x00004000U
8580#define GPIO_AFRL_AFSEL3_3 0x00008000U
8581#define GPIO_AFRL_AFSEL4 0x000F0000U
8582#define GPIO_AFRL_AFSEL4_0 0x00010000U
8583#define GPIO_AFRL_AFSEL4_1 0x00020000U
8584#define GPIO_AFRL_AFSEL4_2 0x00040000U
8585#define GPIO_AFRL_AFSEL4_3 0x00080000U
8586#define GPIO_AFRL_AFSEL5 0x00F00000U
8587#define GPIO_AFRL_AFSEL5_0 0x00100000U
8588#define GPIO_AFRL_AFSEL5_1 0x00200000U
8589#define GPIO_AFRL_AFSEL5_2 0x00400000U
8590#define GPIO_AFRL_AFSEL5_3 0x00800000U
8591#define GPIO_AFRL_AFSEL6 0x0F000000U
8592#define GPIO_AFRL_AFSEL6_0 0x01000000U
8593#define GPIO_AFRL_AFSEL6_1 0x02000000U
8594#define GPIO_AFRL_AFSEL6_2 0x04000000U
8595#define GPIO_AFRL_AFSEL6_3 0x08000000U
8596#define GPIO_AFRL_AFSEL7 0xF0000000U
8597#define GPIO_AFRL_AFSEL7_0 0x10000000U
8598#define GPIO_AFRL_AFSEL7_1 0x20000000U
8599#define GPIO_AFRL_AFSEL7_2 0x40000000U
8600#define GPIO_AFRL_AFSEL7_3 0x80000000U
8603#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8604#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8605#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8606#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8607#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8608#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8609#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8610#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8611#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8612#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8613#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8614#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8615#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8616#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8617#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8618#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8619#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8620#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8621#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8622#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8623#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8624#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8625#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8626#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8627#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8628#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8629#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8630#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
8631#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
8632#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
8633#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8634#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
8635#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
8636#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
8637#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
8638#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8639#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
8640#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
8641#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
8642#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
8645#define GPIO_AFRH_AFSEL8 0x0000000FU
8646#define GPIO_AFRH_AFSEL8_0 0x00000001U
8647#define GPIO_AFRH_AFSEL8_1 0x00000002U
8648#define GPIO_AFRH_AFSEL8_2 0x00000004U
8649#define GPIO_AFRH_AFSEL8_3 0x00000008U
8650#define GPIO_AFRH_AFSEL9 0x000000F0U
8651#define GPIO_AFRH_AFSEL9_0 0x00000010U
8652#define GPIO_AFRH_AFSEL9_1 0x00000020U
8653#define GPIO_AFRH_AFSEL9_2 0x00000040U
8654#define GPIO_AFRH_AFSEL9_3 0x00000080U
8655#define GPIO_AFRH_AFSEL10 0x00000F00U
8656#define GPIO_AFRH_AFSEL10_0 0x00000100U
8657#define GPIO_AFRH_AFSEL10_1 0x00000200U
8658#define GPIO_AFRH_AFSEL10_2 0x00000400U
8659#define GPIO_AFRH_AFSEL10_3 0x00000800U
8660#define GPIO_AFRH_AFSEL11 0x0000F000U
8661#define GPIO_AFRH_AFSEL11_0 0x00001000U
8662#define GPIO_AFRH_AFSEL11_1 0x00002000U
8663#define GPIO_AFRH_AFSEL11_2 0x00004000U
8664#define GPIO_AFRH_AFSEL11_3 0x00008000U
8665#define GPIO_AFRH_AFSEL12 0x000F0000U
8666#define GPIO_AFRH_AFSEL12_0 0x00010000U
8667#define GPIO_AFRH_AFSEL12_1 0x00020000U
8668#define GPIO_AFRH_AFSEL12_2 0x00040000U
8669#define GPIO_AFRH_AFSEL12_3 0x00080000U
8670#define GPIO_AFRH_AFSEL13 0x00F00000U
8671#define GPIO_AFRH_AFSEL13_0 0x00100000U
8672#define GPIO_AFRH_AFSEL13_1 0x00200000U
8673#define GPIO_AFRH_AFSEL13_2 0x00400000U
8674#define GPIO_AFRH_AFSEL13_3 0x00800000U
8675#define GPIO_AFRH_AFSEL14 0x0F000000U
8676#define GPIO_AFRH_AFSEL14_0 0x01000000U
8677#define GPIO_AFRH_AFSEL14_1 0x02000000U
8678#define GPIO_AFRH_AFSEL14_2 0x04000000U
8679#define GPIO_AFRH_AFSEL14_3 0x08000000U
8680#define GPIO_AFRH_AFSEL15 0xF0000000U
8681#define GPIO_AFRH_AFSEL15_0 0x10000000U
8682#define GPIO_AFRH_AFSEL15_1 0x20000000U
8683#define GPIO_AFRH_AFSEL15_2 0x40000000U
8684#define GPIO_AFRH_AFSEL15_3 0x80000000U
8687#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8688#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
8689#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
8690#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
8691#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
8692#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8693#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
8694#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
8695#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
8696#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
8697#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8698#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
8699#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
8700#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
8701#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
8702#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8703#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
8704#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
8705#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
8706#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
8707#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8708#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
8709#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
8710#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
8711#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
8712#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8713#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
8714#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
8715#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
8716#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
8717#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8718#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
8719#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
8720#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
8721#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
8722#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8723#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
8724#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
8725#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
8726#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
8735#define I2C_CR1_PE_Pos (0U)
8736#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
8737#define I2C_CR1_PE I2C_CR1_PE_Msk
8738#define I2C_CR1_SMBUS_Pos (1U)
8739#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
8740#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
8741#define I2C_CR1_SMBTYPE_Pos (3U)
8742#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
8743#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
8744#define I2C_CR1_ENARP_Pos (4U)
8745#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
8746#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
8747#define I2C_CR1_ENPEC_Pos (5U)
8748#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
8749#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
8750#define I2C_CR1_ENGC_Pos (6U)
8751#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
8752#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
8753#define I2C_CR1_NOSTRETCH_Pos (7U)
8754#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
8755#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
8756#define I2C_CR1_START_Pos (8U)
8757#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
8758#define I2C_CR1_START I2C_CR1_START_Msk
8759#define I2C_CR1_STOP_Pos (9U)
8760#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
8761#define I2C_CR1_STOP I2C_CR1_STOP_Msk
8762#define I2C_CR1_ACK_Pos (10U)
8763#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
8764#define I2C_CR1_ACK I2C_CR1_ACK_Msk
8765#define I2C_CR1_POS_Pos (11U)
8766#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
8767#define I2C_CR1_POS I2C_CR1_POS_Msk
8768#define I2C_CR1_PEC_Pos (12U)
8769#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
8770#define I2C_CR1_PEC I2C_CR1_PEC_Msk
8771#define I2C_CR1_ALERT_Pos (13U)
8772#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
8773#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
8774#define I2C_CR1_SWRST_Pos (15U)
8775#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
8776#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
8779#define I2C_CR2_FREQ_Pos (0U)
8780#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
8781#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
8782#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
8783#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
8784#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
8785#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
8786#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
8787#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
8789#define I2C_CR2_ITERREN_Pos (8U)
8790#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
8791#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
8792#define I2C_CR2_ITEVTEN_Pos (9U)
8793#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
8794#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
8795#define I2C_CR2_ITBUFEN_Pos (10U)
8796#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
8797#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
8798#define I2C_CR2_DMAEN_Pos (11U)
8799#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
8800#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
8801#define I2C_CR2_LAST_Pos (12U)
8802#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
8803#define I2C_CR2_LAST I2C_CR2_LAST_Msk
8806#define I2C_OAR1_ADD1_7 0x000000FEU
8807#define I2C_OAR1_ADD8_9 0x00000300U
8809#define I2C_OAR1_ADD0_Pos (0U)
8810#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
8811#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
8812#define I2C_OAR1_ADD1_Pos (1U)
8813#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
8814#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
8815#define I2C_OAR1_ADD2_Pos (2U)
8816#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
8817#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
8818#define I2C_OAR1_ADD3_Pos (3U)
8819#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
8820#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
8821#define I2C_OAR1_ADD4_Pos (4U)
8822#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
8823#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
8824#define I2C_OAR1_ADD5_Pos (5U)
8825#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
8826#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
8827#define I2C_OAR1_ADD6_Pos (6U)
8828#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
8829#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
8830#define I2C_OAR1_ADD7_Pos (7U)
8831#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
8832#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
8833#define I2C_OAR1_ADD8_Pos (8U)
8834#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
8835#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
8836#define I2C_OAR1_ADD9_Pos (9U)
8837#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
8838#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
8840#define I2C_OAR1_ADDMODE_Pos (15U)
8841#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
8842#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
8845#define I2C_OAR2_ENDUAL_Pos (0U)
8846#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
8847#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
8848#define I2C_OAR2_ADD2_Pos (1U)
8849#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
8850#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
8853#define I2C_DR_DR_Pos (0U)
8854#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
8855#define I2C_DR_DR I2C_DR_DR_Msk
8858#define I2C_SR1_SB_Pos (0U)
8859#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
8860#define I2C_SR1_SB I2C_SR1_SB_Msk
8861#define I2C_SR1_ADDR_Pos (1U)
8862#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
8863#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
8864#define I2C_SR1_BTF_Pos (2U)
8865#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
8866#define I2C_SR1_BTF I2C_SR1_BTF_Msk
8867#define I2C_SR1_ADD10_Pos (3U)
8868#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
8869#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
8870#define I2C_SR1_STOPF_Pos (4U)
8871#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
8872#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
8873#define I2C_SR1_RXNE_Pos (6U)
8874#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
8875#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
8876#define I2C_SR1_TXE_Pos (7U)
8877#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
8878#define I2C_SR1_TXE I2C_SR1_TXE_Msk
8879#define I2C_SR1_BERR_Pos (8U)
8880#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
8881#define I2C_SR1_BERR I2C_SR1_BERR_Msk
8882#define I2C_SR1_ARLO_Pos (9U)
8883#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
8884#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
8885#define I2C_SR1_AF_Pos (10U)
8886#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
8887#define I2C_SR1_AF I2C_SR1_AF_Msk
8888#define I2C_SR1_OVR_Pos (11U)
8889#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
8890#define I2C_SR1_OVR I2C_SR1_OVR_Msk
8891#define I2C_SR1_PECERR_Pos (12U)
8892#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
8893#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
8894#define I2C_SR1_TIMEOUT_Pos (14U)
8895#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
8896#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
8897#define I2C_SR1_SMBALERT_Pos (15U)
8898#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
8899#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
8902#define I2C_SR2_MSL_Pos (0U)
8903#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
8904#define I2C_SR2_MSL I2C_SR2_MSL_Msk
8905#define I2C_SR2_BUSY_Pos (1U)
8906#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
8907#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
8908#define I2C_SR2_TRA_Pos (2U)
8909#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
8910#define I2C_SR2_TRA I2C_SR2_TRA_Msk
8911#define I2C_SR2_GENCALL_Pos (4U)
8912#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
8913#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
8914#define I2C_SR2_SMBDEFAULT_Pos (5U)
8915#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
8916#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
8917#define I2C_SR2_SMBHOST_Pos (6U)
8918#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
8919#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
8920#define I2C_SR2_DUALF_Pos (7U)
8921#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
8922#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
8923#define I2C_SR2_PEC_Pos (8U)
8924#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
8925#define I2C_SR2_PEC I2C_SR2_PEC_Msk
8928#define I2C_CCR_CCR_Pos (0U)
8929#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
8930#define I2C_CCR_CCR I2C_CCR_CCR_Msk
8931#define I2C_CCR_DUTY_Pos (14U)
8932#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
8933#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
8934#define I2C_CCR_FS_Pos (15U)
8935#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
8936#define I2C_CCR_FS I2C_CCR_FS_Msk
8939#define I2C_TRISE_TRISE_Pos (0U)
8940#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
8941#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
8949#define IWDG_KR_KEY_Pos (0U)
8950#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
8951#define IWDG_KR_KEY IWDG_KR_KEY_Msk
8954#define IWDG_PR_PR_Pos (0U)
8955#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
8956#define IWDG_PR_PR IWDG_PR_PR_Msk
8957#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
8958#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
8959#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
8962#define IWDG_RLR_RL_Pos (0U)
8963#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
8964#define IWDG_RLR_RL IWDG_RLR_RL_Msk
8967#define IWDG_SR_PVU_Pos (0U)
8968#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
8969#define IWDG_SR_PVU IWDG_SR_PVU_Msk
8970#define IWDG_SR_RVU_Pos (1U)
8971#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
8972#define IWDG_SR_RVU IWDG_SR_RVU_Msk
8980#define PWR_CR_LPDS_Pos (0U)
8981#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
8982#define PWR_CR_LPDS PWR_CR_LPDS_Msk
8983#define PWR_CR_PDDS_Pos (1U)
8984#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
8985#define PWR_CR_PDDS PWR_CR_PDDS_Msk
8986#define PWR_CR_CWUF_Pos (2U)
8987#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
8988#define PWR_CR_CWUF PWR_CR_CWUF_Msk
8989#define PWR_CR_CSBF_Pos (3U)
8990#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
8991#define PWR_CR_CSBF PWR_CR_CSBF_Msk
8992#define PWR_CR_PVDE_Pos (4U)
8993#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
8994#define PWR_CR_PVDE PWR_CR_PVDE_Msk
8996#define PWR_CR_PLS_Pos (5U)
8997#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
8998#define PWR_CR_PLS PWR_CR_PLS_Msk
8999#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
9000#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
9001#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
9004#define PWR_CR_PLS_LEV0 0x00000000U
9005#define PWR_CR_PLS_LEV1 0x00000020U
9006#define PWR_CR_PLS_LEV2 0x00000040U
9007#define PWR_CR_PLS_LEV3 0x00000060U
9008#define PWR_CR_PLS_LEV4 0x00000080U
9009#define PWR_CR_PLS_LEV5 0x000000A0U
9010#define PWR_CR_PLS_LEV6 0x000000C0U
9011#define PWR_CR_PLS_LEV7 0x000000E0U
9013#define PWR_CR_DBP_Pos (8U)
9014#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
9015#define PWR_CR_DBP PWR_CR_DBP_Msk
9016#define PWR_CR_FPDS_Pos (9U)
9017#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
9018#define PWR_CR_FPDS PWR_CR_FPDS_Msk
9021#define PWR_CSR_WUF_Pos (0U)
9022#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
9023#define PWR_CSR_WUF PWR_CSR_WUF_Msk
9024#define PWR_CSR_SBF_Pos (1U)
9025#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
9026#define PWR_CSR_SBF PWR_CSR_SBF_Msk
9027#define PWR_CSR_PVDO_Pos (2U)
9028#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
9029#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
9030#define PWR_CSR_BRR_Pos (3U)
9031#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
9032#define PWR_CSR_BRR PWR_CSR_BRR_Msk
9033#define PWR_CSR_EWUP_Pos (8U)
9034#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
9035#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
9036#define PWR_CSR_BRE_Pos (9U)
9037#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
9038#define PWR_CSR_BRE PWR_CSR_BRE_Msk
9046#define RCC_CR_HSION_Pos (0U)
9047#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
9048#define RCC_CR_HSION RCC_CR_HSION_Msk
9049#define RCC_CR_HSIRDY_Pos (1U)
9050#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
9051#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9053#define RCC_CR_HSITRIM_Pos (3U)
9054#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
9055#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9056#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
9057#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
9058#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
9059#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
9060#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
9062#define RCC_CR_HSICAL_Pos (8U)
9063#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
9064#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9065#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
9066#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
9067#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
9068#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
9069#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
9070#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
9071#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
9072#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
9074#define RCC_CR_HSEON_Pos (16U)
9075#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
9076#define RCC_CR_HSEON RCC_CR_HSEON_Msk
9077#define RCC_CR_HSERDY_Pos (17U)
9078#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
9079#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9080#define RCC_CR_HSEBYP_Pos (18U)
9081#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
9082#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9083#define RCC_CR_CSSON_Pos (19U)
9084#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
9085#define RCC_CR_CSSON RCC_CR_CSSON_Msk
9086#define RCC_CR_PLLON_Pos (24U)
9087#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
9088#define RCC_CR_PLLON RCC_CR_PLLON_Msk
9089#define RCC_CR_PLLRDY_Pos (25U)
9090#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
9091#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9092#define RCC_CR_PLLI2SON_Pos (26U)
9093#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
9094#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9095#define RCC_CR_PLLI2SRDY_Pos (27U)
9096#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
9097#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9100#define RCC_PLLCFGR_PLLM_Pos (0U)
9101#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
9102#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9103#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
9104#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
9105#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
9106#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
9107#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
9108#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
9110#define RCC_PLLCFGR_PLLN_Pos (6U)
9111#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
9112#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9113#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
9114#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
9115#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
9116#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
9117#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
9118#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
9119#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
9120#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
9121#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
9123#define RCC_PLLCFGR_PLLP_Pos (16U)
9124#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
9125#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9126#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
9127#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
9129#define RCC_PLLCFGR_PLLSRC_Pos (22U)
9130#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
9131#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9132#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9133#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
9134#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9135#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9137#define RCC_PLLCFGR_PLLQ_Pos (24U)
9138#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
9139#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9140#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
9141#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
9142#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
9143#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
9147#define RCC_CFGR_SW_Pos (0U)
9148#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
9149#define RCC_CFGR_SW RCC_CFGR_SW_Msk
9150#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
9151#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
9153#define RCC_CFGR_SW_HSI 0x00000000U
9154#define RCC_CFGR_SW_HSE 0x00000001U
9155#define RCC_CFGR_SW_PLL 0x00000002U
9158#define RCC_CFGR_SWS_Pos (2U)
9159#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
9160#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
9161#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
9162#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
9164#define RCC_CFGR_SWS_HSI 0x00000000U
9165#define RCC_CFGR_SWS_HSE 0x00000004U
9166#define RCC_CFGR_SWS_PLL 0x00000008U
9169#define RCC_CFGR_HPRE_Pos (4U)
9170#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
9171#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
9172#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
9173#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
9174#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
9175#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
9177#define RCC_CFGR_HPRE_DIV1 0x00000000U
9178#define RCC_CFGR_HPRE_DIV2 0x00000080U
9179#define RCC_CFGR_HPRE_DIV4 0x00000090U
9180#define RCC_CFGR_HPRE_DIV8 0x000000A0U
9181#define RCC_CFGR_HPRE_DIV16 0x000000B0U
9182#define RCC_CFGR_HPRE_DIV64 0x000000C0U
9183#define RCC_CFGR_HPRE_DIV128 0x000000D0U
9184#define RCC_CFGR_HPRE_DIV256 0x000000E0U
9185#define RCC_CFGR_HPRE_DIV512 0x000000F0U
9188#define RCC_CFGR_PPRE1_Pos (10U)
9189#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
9190#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
9191#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
9192#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
9193#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
9195#define RCC_CFGR_PPRE1_DIV1 0x00000000U
9196#define RCC_CFGR_PPRE1_DIV2 0x00001000U
9197#define RCC_CFGR_PPRE1_DIV4 0x00001400U
9198#define RCC_CFGR_PPRE1_DIV8 0x00001800U
9199#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
9202#define RCC_CFGR_PPRE2_Pos (13U)
9203#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
9204#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
9205#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
9206#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
9207#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
9209#define RCC_CFGR_PPRE2_DIV1 0x00000000U
9210#define RCC_CFGR_PPRE2_DIV2 0x00008000U
9211#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
9212#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
9213#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
9216#define RCC_CFGR_RTCPRE_Pos (16U)
9217#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
9218#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9219#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
9220#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
9221#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
9222#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
9223#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
9226#define RCC_CFGR_MCO1_Pos (21U)
9227#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
9228#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9229#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
9230#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
9232#define RCC_CFGR_I2SSRC_Pos (23U)
9233#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
9234#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
9236#define RCC_CFGR_MCO1PRE_Pos (24U)
9237#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
9238#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9239#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
9240#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
9241#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
9243#define RCC_CFGR_MCO2PRE_Pos (27U)
9244#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
9245#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9246#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
9247#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
9248#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
9250#define RCC_CFGR_MCO2_Pos (30U)
9251#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
9252#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9253#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
9254#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
9257#define RCC_CIR_LSIRDYF_Pos (0U)
9258#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
9259#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9260#define RCC_CIR_LSERDYF_Pos (1U)
9261#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
9262#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9263#define RCC_CIR_HSIRDYF_Pos (2U)
9264#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
9265#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9266#define RCC_CIR_HSERDYF_Pos (3U)
9267#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
9268#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9269#define RCC_CIR_PLLRDYF_Pos (4U)
9270#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
9271#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9272#define RCC_CIR_PLLI2SRDYF_Pos (5U)
9273#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
9274#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9276#define RCC_CIR_CSSF_Pos (7U)
9277#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
9278#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9279#define RCC_CIR_LSIRDYIE_Pos (8U)
9280#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
9281#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9282#define RCC_CIR_LSERDYIE_Pos (9U)
9283#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
9284#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9285#define RCC_CIR_HSIRDYIE_Pos (10U)
9286#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
9287#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9288#define RCC_CIR_HSERDYIE_Pos (11U)
9289#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
9290#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9291#define RCC_CIR_PLLRDYIE_Pos (12U)
9292#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
9293#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9294#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9295#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
9296#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9298#define RCC_CIR_LSIRDYC_Pos (16U)
9299#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
9300#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9301#define RCC_CIR_LSERDYC_Pos (17U)
9302#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
9303#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9304#define RCC_CIR_HSIRDYC_Pos (18U)
9305#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
9306#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9307#define RCC_CIR_HSERDYC_Pos (19U)
9308#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
9309#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9310#define RCC_CIR_PLLRDYC_Pos (20U)
9311#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
9312#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9313#define RCC_CIR_PLLI2SRDYC_Pos (21U)
9314#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
9315#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9317#define RCC_CIR_CSSC_Pos (23U)
9318#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
9319#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9322#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9323#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
9324#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9325#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9326#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
9327#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9328#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9329#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
9330#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9331#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9332#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
9333#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9334#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9335#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
9336#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9337#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
9338#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
9339#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
9340#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
9341#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
9342#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
9343#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9344#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
9345#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9346#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
9347#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
9348#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
9349#define RCC_AHB1RSTR_CRCRST_Pos (12U)
9350#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
9351#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9352#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9353#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
9354#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9355#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9356#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
9357#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9358#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
9359#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
9360#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
9361#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
9362#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
9363#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
9366#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
9367#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
9368#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
9369#define RCC_AHB2RSTR_RNGRST_Pos (6U)
9370#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
9371#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9372#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9373#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
9374#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9378#define RCC_AHB3RSTR_FSMCRST_Pos (0U)
9379#define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
9380#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
9383#define RCC_APB1RSTR_TIM2RST_Pos (0U)
9384#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
9385#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9386#define RCC_APB1RSTR_TIM3RST_Pos (1U)
9387#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
9388#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9389#define RCC_APB1RSTR_TIM4RST_Pos (2U)
9390#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
9391#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9392#define RCC_APB1RSTR_TIM5RST_Pos (3U)
9393#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
9394#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9395#define RCC_APB1RSTR_TIM6RST_Pos (4U)
9396#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
9397#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9398#define RCC_APB1RSTR_TIM7RST_Pos (5U)
9399#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
9400#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9401#define RCC_APB1RSTR_TIM12RST_Pos (6U)
9402#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
9403#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9404#define RCC_APB1RSTR_TIM13RST_Pos (7U)
9405#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
9406#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9407#define RCC_APB1RSTR_TIM14RST_Pos (8U)
9408#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
9409#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9410#define RCC_APB1RSTR_WWDGRST_Pos (11U)
9411#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
9412#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9413#define RCC_APB1RSTR_SPI2RST_Pos (14U)
9414#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
9415#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9416#define RCC_APB1RSTR_SPI3RST_Pos (15U)
9417#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
9418#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9419#define RCC_APB1RSTR_USART2RST_Pos (17U)
9420#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
9421#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9422#define RCC_APB1RSTR_USART3RST_Pos (18U)
9423#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
9424#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9425#define RCC_APB1RSTR_UART4RST_Pos (19U)
9426#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
9427#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
9428#define RCC_APB1RSTR_UART5RST_Pos (20U)
9429#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
9430#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
9431#define RCC_APB1RSTR_I2C1RST_Pos (21U)
9432#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
9433#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9434#define RCC_APB1RSTR_I2C2RST_Pos (22U)
9435#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
9436#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9437#define RCC_APB1RSTR_I2C3RST_Pos (23U)
9438#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
9439#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9440#define RCC_APB1RSTR_CAN1RST_Pos (25U)
9441#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
9442#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9443#define RCC_APB1RSTR_CAN2RST_Pos (26U)
9444#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
9445#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
9446#define RCC_APB1RSTR_PWRRST_Pos (28U)
9447#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
9448#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9449#define RCC_APB1RSTR_DACRST_Pos (29U)
9450#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
9451#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
9454#define RCC_APB2RSTR_TIM1RST_Pos (0U)
9455#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
9456#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9457#define RCC_APB2RSTR_TIM8RST_Pos (1U)
9458#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
9459#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9460#define RCC_APB2RSTR_USART1RST_Pos (4U)
9461#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
9462#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9463#define RCC_APB2RSTR_USART6RST_Pos (5U)
9464#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
9465#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9466#define RCC_APB2RSTR_ADCRST_Pos (8U)
9467#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
9468#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9469#define RCC_APB2RSTR_SDIORST_Pos (11U)
9470#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
9471#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
9472#define RCC_APB2RSTR_SPI1RST_Pos (12U)
9473#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
9474#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9475#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9476#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
9477#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9478#define RCC_APB2RSTR_TIM9RST_Pos (16U)
9479#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
9480#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9481#define RCC_APB2RSTR_TIM10RST_Pos (17U)
9482#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
9483#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9484#define RCC_APB2RSTR_TIM11RST_Pos (18U)
9485#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
9486#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9489#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
9492#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9493#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
9494#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9495#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9496#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
9497#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9498#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9499#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
9500#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9501#define RCC_AHB1ENR_GPIODEN_Pos (3U)
9502#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
9503#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9504#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9505#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
9506#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9507#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
9508#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
9509#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
9510#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
9511#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
9512#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
9513#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
9514#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
9515#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
9516#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
9517#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
9518#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
9519#define RCC_AHB1ENR_CRCEN_Pos (12U)
9520#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
9521#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9522#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
9523#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
9524#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
9525#define RCC_AHB1ENR_DMA1EN_Pos (21U)
9526#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
9527#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9528#define RCC_AHB1ENR_DMA2EN_Pos (22U)
9529#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
9530#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9532#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
9533#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
9534#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
9535#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
9536#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
9537#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
9538#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
9539#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
9540#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
9541#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
9542#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
9543#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
9544#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
9545#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
9546#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
9547#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
9548#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
9549#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
9552#define RCC_AHB2ENR_DCMIEN_Pos (0U)
9553#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
9554#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
9555#define RCC_AHB2ENR_RNGEN_Pos (6U)
9556#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
9557#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9558#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
9559#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
9560#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
9564#define RCC_AHB3ENR_FSMCEN_Pos (0U)
9565#define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
9566#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
9569#define RCC_APB1ENR_TIM2EN_Pos (0U)
9570#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
9571#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
9572#define RCC_APB1ENR_TIM3EN_Pos (1U)
9573#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
9574#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
9575#define RCC_APB1ENR_TIM4EN_Pos (2U)
9576#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
9577#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
9578#define RCC_APB1ENR_TIM5EN_Pos (3U)
9579#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
9580#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
9581#define RCC_APB1ENR_TIM6EN_Pos (4U)
9582#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
9583#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
9584#define RCC_APB1ENR_TIM7EN_Pos (5U)
9585#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
9586#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
9587#define RCC_APB1ENR_TIM12EN_Pos (6U)
9588#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
9589#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
9590#define RCC_APB1ENR_TIM13EN_Pos (7U)
9591#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
9592#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
9593#define RCC_APB1ENR_TIM14EN_Pos (8U)
9594#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
9595#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
9596#define RCC_APB1ENR_WWDGEN_Pos (11U)
9597#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
9598#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
9599#define RCC_APB1ENR_SPI2EN_Pos (14U)
9600#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
9601#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
9602#define RCC_APB1ENR_SPI3EN_Pos (15U)
9603#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
9604#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
9605#define RCC_APB1ENR_USART2EN_Pos (17U)
9606#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
9607#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
9608#define RCC_APB1ENR_USART3EN_Pos (18U)
9609#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
9610#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
9611#define RCC_APB1ENR_UART4EN_Pos (19U)
9612#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
9613#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
9614#define RCC_APB1ENR_UART5EN_Pos (20U)
9615#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
9616#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
9617#define RCC_APB1ENR_I2C1EN_Pos (21U)
9618#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
9619#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
9620#define RCC_APB1ENR_I2C2EN_Pos (22U)
9621#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
9622#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
9623#define RCC_APB1ENR_I2C3EN_Pos (23U)
9624#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
9625#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
9626#define RCC_APB1ENR_CAN1EN_Pos (25U)
9627#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
9628#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
9629#define RCC_APB1ENR_CAN2EN_Pos (26U)
9630#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
9631#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
9632#define RCC_APB1ENR_PWREN_Pos (28U)
9633#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
9634#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
9635#define RCC_APB1ENR_DACEN_Pos (29U)
9636#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
9637#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
9640#define RCC_APB2ENR_TIM1EN_Pos (0U)
9641#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
9642#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
9643#define RCC_APB2ENR_TIM8EN_Pos (1U)
9644#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
9645#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
9646#define RCC_APB2ENR_USART1EN_Pos (4U)
9647#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
9648#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
9649#define RCC_APB2ENR_USART6EN_Pos (5U)
9650#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
9651#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
9652#define RCC_APB2ENR_ADC1EN_Pos (8U)
9653#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
9654#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
9655#define RCC_APB2ENR_ADC2EN_Pos (9U)
9656#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
9657#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
9658#define RCC_APB2ENR_ADC3EN_Pos (10U)
9659#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
9660#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
9661#define RCC_APB2ENR_SDIOEN_Pos (11U)
9662#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
9663#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
9664#define RCC_APB2ENR_SPI1EN_Pos (12U)
9665#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
9666#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
9667#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
9668#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
9669#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
9670#define RCC_APB2ENR_TIM9EN_Pos (16U)
9671#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
9672#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
9673#define RCC_APB2ENR_TIM10EN_Pos (17U)
9674#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
9675#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
9676#define RCC_APB2ENR_TIM11EN_Pos (18U)
9677#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
9678#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
9681#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
9682#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
9683#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
9684#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
9685#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
9686#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
9687#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
9688#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
9689#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
9690#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
9691#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
9692#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
9693#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
9694#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
9695#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
9696#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
9697#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
9698#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
9699#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
9700#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
9701#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
9702#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
9703#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
9704#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
9705#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
9706#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
9707#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
9708#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
9709#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
9710#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
9711#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
9712#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
9713#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
9714#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
9715#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
9716#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
9717#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
9718#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
9719#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
9720#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
9721#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
9722#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
9723#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
9724#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
9725#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
9726#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
9727#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
9728#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
9729#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
9730#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
9731#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
9732#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
9733#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
9734#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
9735#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
9736#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
9737#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
9738#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
9739#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
9740#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
9741#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
9742#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
9743#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
9744#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
9745#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
9746#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
9749#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
9750#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
9751#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
9752#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
9753#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
9754#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
9755#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
9756#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
9757#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
9761#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
9762#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
9763#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
9766#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
9767#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
9768#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
9769#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
9770#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
9771#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
9772#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
9773#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
9774#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
9775#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
9776#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
9777#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
9778#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
9779#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
9780#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
9781#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
9782#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
9783#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
9784#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
9785#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
9786#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
9787#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
9788#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
9789#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
9790#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
9791#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
9792#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
9793#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
9794#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
9795#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
9796#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
9797#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
9798#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
9799#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
9800#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
9801#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
9802#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
9803#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
9804#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
9805#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
9806#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
9807#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
9808#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
9809#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
9810#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
9811#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
9812#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
9813#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
9814#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
9815#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
9816#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
9817#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
9818#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
9819#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
9820#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
9821#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
9822#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
9823#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
9824#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
9825#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
9826#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
9827#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
9828#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
9829#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
9830#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
9831#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
9832#define RCC_APB1LPENR_DACLPEN_Pos (29U)
9833#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
9834#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
9837#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
9838#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
9839#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
9840#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
9841#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
9842#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
9843#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
9844#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
9845#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
9846#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
9847#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
9848#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
9849#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
9850#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
9851#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
9852#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
9853#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
9854#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
9855#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
9856#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
9857#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
9858#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
9859#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
9860#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
9861#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
9862#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
9863#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
9864#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
9865#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
9866#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
9867#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
9868#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
9869#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
9870#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
9871#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
9872#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
9873#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
9874#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
9875#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
9878#define RCC_BDCR_LSEON_Pos (0U)
9879#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
9880#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
9881#define RCC_BDCR_LSERDY_Pos (1U)
9882#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
9883#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
9884#define RCC_BDCR_LSEBYP_Pos (2U)
9885#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
9886#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
9888#define RCC_BDCR_RTCSEL_Pos (8U)
9889#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
9890#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
9891#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
9892#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
9894#define RCC_BDCR_RTCEN_Pos (15U)
9895#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
9896#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
9897#define RCC_BDCR_BDRST_Pos (16U)
9898#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
9899#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
9902#define RCC_CSR_LSION_Pos (0U)
9903#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
9904#define RCC_CSR_LSION RCC_CSR_LSION_Msk
9905#define RCC_CSR_LSIRDY_Pos (1U)
9906#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
9907#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
9908#define RCC_CSR_RMVF_Pos (24U)
9909#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
9910#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
9911#define RCC_CSR_BORRSTF_Pos (25U)
9912#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
9913#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
9914#define RCC_CSR_PINRSTF_Pos (26U)
9915#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
9916#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
9917#define RCC_CSR_PORRSTF_Pos (27U)
9918#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
9919#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
9920#define RCC_CSR_SFTRSTF_Pos (28U)
9921#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
9922#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
9923#define RCC_CSR_IWDGRSTF_Pos (29U)
9924#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
9925#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
9926#define RCC_CSR_WWDGRSTF_Pos (30U)
9927#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
9928#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
9929#define RCC_CSR_LPWRRSTF_Pos (31U)
9930#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
9931#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
9933#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
9934#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
9937#define RCC_SSCGR_MODPER_Pos (0U)
9938#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
9939#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
9940#define RCC_SSCGR_INCSTEP_Pos (13U)
9941#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
9942#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
9943#define RCC_SSCGR_SPREADSEL_Pos (30U)
9944#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
9945#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
9946#define RCC_SSCGR_SSCGEN_Pos (31U)
9947#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
9948#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
9951#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
9952#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
9953#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
9954#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
9955#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
9956#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
9957#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
9958#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
9959#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
9960#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
9961#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
9962#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
9964#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
9965#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
9966#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
9967#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
9968#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
9969#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
9977#define RNG_CR_RNGEN_Pos (2U)
9978#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
9979#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
9980#define RNG_CR_IE_Pos (3U)
9981#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
9982#define RNG_CR_IE RNG_CR_IE_Msk
9985#define RNG_SR_DRDY_Pos (0U)
9986#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
9987#define RNG_SR_DRDY RNG_SR_DRDY_Msk
9988#define RNG_SR_CECS_Pos (1U)
9989#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
9990#define RNG_SR_CECS RNG_SR_CECS_Msk
9991#define RNG_SR_SECS_Pos (2U)
9992#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
9993#define RNG_SR_SECS RNG_SR_SECS_Msk
9994#define RNG_SR_CEIS_Pos (5U)
9995#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
9996#define RNG_SR_CEIS RNG_SR_CEIS_Msk
9997#define RNG_SR_SEIS_Pos (6U)
9998#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
9999#define RNG_SR_SEIS RNG_SR_SEIS_Msk
10007#define RTC_TR_PM_Pos (22U)
10008#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
10009#define RTC_TR_PM RTC_TR_PM_Msk
10010#define RTC_TR_HT_Pos (20U)
10011#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
10012#define RTC_TR_HT RTC_TR_HT_Msk
10013#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
10014#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
10015#define RTC_TR_HU_Pos (16U)
10016#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
10017#define RTC_TR_HU RTC_TR_HU_Msk
10018#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
10019#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
10020#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
10021#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
10022#define RTC_TR_MNT_Pos (12U)
10023#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
10024#define RTC_TR_MNT RTC_TR_MNT_Msk
10025#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
10026#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
10027#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
10028#define RTC_TR_MNU_Pos (8U)
10029#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
10030#define RTC_TR_MNU RTC_TR_MNU_Msk
10031#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
10032#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
10033#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
10034#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
10035#define RTC_TR_ST_Pos (4U)
10036#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
10037#define RTC_TR_ST RTC_TR_ST_Msk
10038#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
10039#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
10040#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
10041#define RTC_TR_SU_Pos (0U)
10042#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
10043#define RTC_TR_SU RTC_TR_SU_Msk
10044#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
10045#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
10046#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
10047#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
10050#define RTC_DR_YT_Pos (20U)
10051#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
10052#define RTC_DR_YT RTC_DR_YT_Msk
10053#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
10054#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
10055#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
10056#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
10057#define RTC_DR_YU_Pos (16U)
10058#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
10059#define RTC_DR_YU RTC_DR_YU_Msk
10060#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
10061#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
10062#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
10063#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
10064#define RTC_DR_WDU_Pos (13U)
10065#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
10066#define RTC_DR_WDU RTC_DR_WDU_Msk
10067#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
10068#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
10069#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
10070#define RTC_DR_MT_Pos (12U)
10071#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
10072#define RTC_DR_MT RTC_DR_MT_Msk
10073#define RTC_DR_MU_Pos (8U)
10074#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
10075#define RTC_DR_MU RTC_DR_MU_Msk
10076#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
10077#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
10078#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
10079#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
10080#define RTC_DR_DT_Pos (4U)
10081#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
10082#define RTC_DR_DT RTC_DR_DT_Msk
10083#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
10084#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
10085#define RTC_DR_DU_Pos (0U)
10086#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
10087#define RTC_DR_DU RTC_DR_DU_Msk
10088#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
10089#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
10090#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
10091#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
10094#define RTC_CR_COE_Pos (23U)
10095#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
10096#define RTC_CR_COE RTC_CR_COE_Msk
10097#define RTC_CR_OSEL_Pos (21U)
10098#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
10099#define RTC_CR_OSEL RTC_CR_OSEL_Msk
10100#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
10101#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
10102#define RTC_CR_POL_Pos (20U)
10103#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
10104#define RTC_CR_POL RTC_CR_POL_Msk
10105#define RTC_CR_BKP_Pos (18U)
10106#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
10107#define RTC_CR_BKP RTC_CR_BKP_Msk
10108#define RTC_CR_SUB1H_Pos (17U)
10109#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
10110#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10111#define RTC_CR_ADD1H_Pos (16U)
10112#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
10113#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10114#define RTC_CR_TSIE_Pos (15U)
10115#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
10116#define RTC_CR_TSIE RTC_CR_TSIE_Msk
10117#define RTC_CR_WUTIE_Pos (14U)
10118#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
10119#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10120#define RTC_CR_ALRBIE_Pos (13U)
10121#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
10122#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10123#define RTC_CR_ALRAIE_Pos (12U)
10124#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
10125#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10126#define RTC_CR_TSE_Pos (11U)
10127#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
10128#define RTC_CR_TSE RTC_CR_TSE_Msk
10129#define RTC_CR_WUTE_Pos (10U)
10130#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
10131#define RTC_CR_WUTE RTC_CR_WUTE_Msk
10132#define RTC_CR_ALRBE_Pos (9U)
10133#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
10134#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10135#define RTC_CR_ALRAE_Pos (8U)
10136#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
10137#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10138#define RTC_CR_DCE_Pos (7U)
10139#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
10140#define RTC_CR_DCE RTC_CR_DCE_Msk
10141#define RTC_CR_FMT_Pos (6U)
10142#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
10143#define RTC_CR_FMT RTC_CR_FMT_Msk
10144#define RTC_CR_REFCKON_Pos (4U)
10145#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
10146#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10147#define RTC_CR_TSEDGE_Pos (3U)
10148#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
10149#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10150#define RTC_CR_WUCKSEL_Pos (0U)
10151#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
10152#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10153#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
10154#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
10155#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
10158#define RTC_CR_BCK RTC_CR_BKP
10161#define RTC_ISR_TAMP1F_Pos (13U)
10162#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
10163#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10164#define RTC_ISR_TSOVF_Pos (12U)
10165#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
10166#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10167#define RTC_ISR_TSF_Pos (11U)
10168#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
10169#define RTC_ISR_TSF RTC_ISR_TSF_Msk
10170#define RTC_ISR_WUTF_Pos (10U)
10171#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
10172#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10173#define RTC_ISR_ALRBF_Pos (9U)
10174#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
10175#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10176#define RTC_ISR_ALRAF_Pos (8U)
10177#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
10178#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10179#define RTC_ISR_INIT_Pos (7U)
10180#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
10181#define RTC_ISR_INIT RTC_ISR_INIT_Msk
10182#define RTC_ISR_INITF_Pos (6U)
10183#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
10184#define RTC_ISR_INITF RTC_ISR_INITF_Msk
10185#define RTC_ISR_RSF_Pos (5U)
10186#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
10187#define RTC_ISR_RSF RTC_ISR_RSF_Msk
10188#define RTC_ISR_INITS_Pos (4U)
10189#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
10190#define RTC_ISR_INITS RTC_ISR_INITS_Msk
10191#define RTC_ISR_WUTWF_Pos (2U)
10192#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
10193#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10194#define RTC_ISR_ALRBWF_Pos (1U)
10195#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
10196#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10197#define RTC_ISR_ALRAWF_Pos (0U)
10198#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
10199#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10202#define RTC_PRER_PREDIV_A_Pos (16U)
10203#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
10204#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10205#define RTC_PRER_PREDIV_S_Pos (0U)
10206#define RTC_PRER_PREDIV_S_Msk (0x1FFFUL << RTC_PRER_PREDIV_S_Pos)
10207#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10210#define RTC_WUTR_WUT_Pos (0U)
10211#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
10212#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10215#define RTC_CALIBR_DCS_Pos (7U)
10216#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
10217#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
10218#define RTC_CALIBR_DC_Pos (0U)
10219#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
10220#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
10223#define RTC_ALRMAR_MSK4_Pos (31U)
10224#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
10225#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10226#define RTC_ALRMAR_WDSEL_Pos (30U)
10227#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
10228#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10229#define RTC_ALRMAR_DT_Pos (28U)
10230#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
10231#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10232#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
10233#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
10234#define RTC_ALRMAR_DU_Pos (24U)
10235#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
10236#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10237#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
10238#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
10239#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
10240#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
10241#define RTC_ALRMAR_MSK3_Pos (23U)
10242#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
10243#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10244#define RTC_ALRMAR_PM_Pos (22U)
10245#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
10246#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10247#define RTC_ALRMAR_HT_Pos (20U)
10248#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
10249#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10250#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
10251#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
10252#define RTC_ALRMAR_HU_Pos (16U)
10253#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
10254#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10255#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
10256#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
10257#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
10258#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
10259#define RTC_ALRMAR_MSK2_Pos (15U)
10260#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
10261#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10262#define RTC_ALRMAR_MNT_Pos (12U)
10263#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
10264#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10265#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
10266#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
10267#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
10268#define RTC_ALRMAR_MNU_Pos (8U)
10269#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
10270#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10271#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
10272#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
10273#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
10274#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
10275#define RTC_ALRMAR_MSK1_Pos (7U)
10276#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
10277#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10278#define RTC_ALRMAR_ST_Pos (4U)
10279#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
10280#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10281#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
10282#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
10283#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
10284#define RTC_ALRMAR_SU_Pos (0U)
10285#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
10286#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10287#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
10288#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
10289#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
10290#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
10293#define RTC_ALRMBR_MSK4_Pos (31U)
10294#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
10295#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10296#define RTC_ALRMBR_WDSEL_Pos (30U)
10297#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
10298#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10299#define RTC_ALRMBR_DT_Pos (28U)
10300#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
10301#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10302#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
10303#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
10304#define RTC_ALRMBR_DU_Pos (24U)
10305#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
10306#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10307#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
10308#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
10309#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
10310#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
10311#define RTC_ALRMBR_MSK3_Pos (23U)
10312#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
10313#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10314#define RTC_ALRMBR_PM_Pos (22U)
10315#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
10316#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10317#define RTC_ALRMBR_HT_Pos (20U)
10318#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
10319#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10320#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
10321#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
10322#define RTC_ALRMBR_HU_Pos (16U)
10323#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
10324#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10325#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
10326#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
10327#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
10328#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
10329#define RTC_ALRMBR_MSK2_Pos (15U)
10330#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
10331#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10332#define RTC_ALRMBR_MNT_Pos (12U)
10333#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
10334#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10335#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
10336#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
10337#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
10338#define RTC_ALRMBR_MNU_Pos (8U)
10339#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
10340#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10341#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
10342#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
10343#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
10344#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
10345#define RTC_ALRMBR_MSK1_Pos (7U)
10346#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
10347#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10348#define RTC_ALRMBR_ST_Pos (4U)
10349#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
10350#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10351#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
10352#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
10353#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
10354#define RTC_ALRMBR_SU_Pos (0U)
10355#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
10356#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10357#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
10358#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
10359#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
10360#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
10363#define RTC_WPR_KEY_Pos (0U)
10364#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
10365#define RTC_WPR_KEY RTC_WPR_KEY_Msk
10368#define RTC_TSTR_PM_Pos (22U)
10369#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
10370#define RTC_TSTR_PM RTC_TSTR_PM_Msk
10371#define RTC_TSTR_HT_Pos (20U)
10372#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
10373#define RTC_TSTR_HT RTC_TSTR_HT_Msk
10374#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
10375#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
10376#define RTC_TSTR_HU_Pos (16U)
10377#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
10378#define RTC_TSTR_HU RTC_TSTR_HU_Msk
10379#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
10380#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
10381#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
10382#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
10383#define RTC_TSTR_MNT_Pos (12U)
10384#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
10385#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10386#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
10387#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
10388#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
10389#define RTC_TSTR_MNU_Pos (8U)
10390#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
10391#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10392#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
10393#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
10394#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
10395#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
10396#define RTC_TSTR_ST_Pos (4U)
10397#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
10398#define RTC_TSTR_ST RTC_TSTR_ST_Msk
10399#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
10400#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
10401#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
10402#define RTC_TSTR_SU_Pos (0U)
10403#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
10404#define RTC_TSTR_SU RTC_TSTR_SU_Msk
10405#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
10406#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
10407#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
10408#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
10411#define RTC_TSDR_WDU_Pos (13U)
10412#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
10413#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10414#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
10415#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
10416#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
10417#define RTC_TSDR_MT_Pos (12U)
10418#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
10419#define RTC_TSDR_MT RTC_TSDR_MT_Msk
10420#define RTC_TSDR_MU_Pos (8U)
10421#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
10422#define RTC_TSDR_MU RTC_TSDR_MU_Msk
10423#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
10424#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
10425#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
10426#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
10427#define RTC_TSDR_DT_Pos (4U)
10428#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
10429#define RTC_TSDR_DT RTC_TSDR_DT_Msk
10430#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
10431#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
10432#define RTC_TSDR_DU_Pos (0U)
10433#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
10434#define RTC_TSDR_DU RTC_TSDR_DU_Msk
10435#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
10436#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
10437#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
10438#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
10441#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
10442#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
10443#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
10444#define RTC_TAFCR_TSINSEL_Pos (17U)
10445#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
10446#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
10447#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
10448#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
10449#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
10450#define RTC_TAFCR_TAMPIE_Pos (2U)
10451#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
10452#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
10453#define RTC_TAFCR_TAMP1TRG_Pos (1U)
10454#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
10455#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
10456#define RTC_TAFCR_TAMP1E_Pos (0U)
10457#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
10458#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
10461#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
10464#define RTC_BKP0R_Pos (0U)
10465#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
10466#define RTC_BKP0R RTC_BKP0R_Msk
10469#define RTC_BKP1R_Pos (0U)
10470#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
10471#define RTC_BKP1R RTC_BKP1R_Msk
10474#define RTC_BKP2R_Pos (0U)
10475#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
10476#define RTC_BKP2R RTC_BKP2R_Msk
10479#define RTC_BKP3R_Pos (0U)
10480#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
10481#define RTC_BKP3R RTC_BKP3R_Msk
10484#define RTC_BKP4R_Pos (0U)
10485#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
10486#define RTC_BKP4R RTC_BKP4R_Msk
10489#define RTC_BKP5R_Pos (0U)
10490#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
10491#define RTC_BKP5R RTC_BKP5R_Msk
10494#define RTC_BKP6R_Pos (0U)
10495#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
10496#define RTC_BKP6R RTC_BKP6R_Msk
10499#define RTC_BKP7R_Pos (0U)
10500#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
10501#define RTC_BKP7R RTC_BKP7R_Msk
10504#define RTC_BKP8R_Pos (0U)
10505#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
10506#define RTC_BKP8R RTC_BKP8R_Msk
10509#define RTC_BKP9R_Pos (0U)
10510#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
10511#define RTC_BKP9R RTC_BKP9R_Msk
10514#define RTC_BKP10R_Pos (0U)
10515#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
10516#define RTC_BKP10R RTC_BKP10R_Msk
10519#define RTC_BKP11R_Pos (0U)
10520#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
10521#define RTC_BKP11R RTC_BKP11R_Msk
10524#define RTC_BKP12R_Pos (0U)
10525#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
10526#define RTC_BKP12R RTC_BKP12R_Msk
10529#define RTC_BKP13R_Pos (0U)
10530#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
10531#define RTC_BKP13R RTC_BKP13R_Msk
10534#define RTC_BKP14R_Pos (0U)
10535#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
10536#define RTC_BKP14R RTC_BKP14R_Msk
10539#define RTC_BKP15R_Pos (0U)
10540#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
10541#define RTC_BKP15R RTC_BKP15R_Msk
10544#define RTC_BKP16R_Pos (0U)
10545#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
10546#define RTC_BKP16R RTC_BKP16R_Msk
10549#define RTC_BKP17R_Pos (0U)
10550#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
10551#define RTC_BKP17R RTC_BKP17R_Msk
10554#define RTC_BKP18R_Pos (0U)
10555#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
10556#define RTC_BKP18R RTC_BKP18R_Msk
10559#define RTC_BKP19R_Pos (0U)
10560#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
10561#define RTC_BKP19R RTC_BKP19R_Msk
10564#define RTC_BKP_NUMBER 0x000000014U
10572#define SDIO_POWER_PWRCTRL_Pos (0U)
10573#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
10574#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
10575#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
10576#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
10579#define SDIO_CLKCR_CLKDIV_Pos (0U)
10580#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
10581#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
10582#define SDIO_CLKCR_CLKEN_Pos (8U)
10583#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
10584#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
10585#define SDIO_CLKCR_PWRSAV_Pos (9U)
10586#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
10587#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
10588#define SDIO_CLKCR_BYPASS_Pos (10U)
10589#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
10590#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
10592#define SDIO_CLKCR_WIDBUS_Pos (11U)
10593#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
10594#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
10595#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
10596#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
10598#define SDIO_CLKCR_NEGEDGE_Pos (13U)
10599#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
10600#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
10601#define SDIO_CLKCR_HWFC_EN_Pos (14U)
10602#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
10603#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
10606#define SDIO_ARG_CMDARG_Pos (0U)
10607#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
10608#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
10611#define SDIO_CMD_CMDINDEX_Pos (0U)
10612#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
10613#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
10615#define SDIO_CMD_WAITRESP_Pos (6U)
10616#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
10617#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
10618#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
10619#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
10621#define SDIO_CMD_WAITINT_Pos (8U)
10622#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
10623#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
10624#define SDIO_CMD_WAITPEND_Pos (9U)
10625#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
10626#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
10627#define SDIO_CMD_CPSMEN_Pos (10U)
10628#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
10629#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
10630#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
10631#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
10632#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
10633#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
10634#define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
10635#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk
10636#define SDIO_CMD_NIEN_Pos (13U)
10637#define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)
10638#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk
10639#define SDIO_CMD_CEATACMD_Pos (14U)
10640#define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)
10641#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk
10644#define SDIO_RESPCMD_RESPCMD_Pos (0U)
10645#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
10646#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
10649#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
10650#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
10651#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
10654#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
10655#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
10656#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
10659#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
10660#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
10661#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
10664#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
10665#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
10666#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
10669#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
10670#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
10671#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
10674#define SDIO_DTIMER_DATATIME_Pos (0U)
10675#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
10676#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
10679#define SDIO_DLEN_DATALENGTH_Pos (0U)
10680#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
10681#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
10684#define SDIO_DCTRL_DTEN_Pos (0U)
10685#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
10686#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
10687#define SDIO_DCTRL_DTDIR_Pos (1U)
10688#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
10689#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
10690#define SDIO_DCTRL_DTMODE_Pos (2U)
10691#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
10692#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
10693#define SDIO_DCTRL_DMAEN_Pos (3U)
10694#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
10695#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
10697#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
10698#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
10699#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
10700#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
10701#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
10702#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
10703#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
10705#define SDIO_DCTRL_RWSTART_Pos (8U)
10706#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
10707#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
10708#define SDIO_DCTRL_RWSTOP_Pos (9U)
10709#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
10710#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
10711#define SDIO_DCTRL_RWMOD_Pos (10U)
10712#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
10713#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
10714#define SDIO_DCTRL_SDIOEN_Pos (11U)
10715#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
10716#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
10719#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
10720#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
10721#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
10724#define SDIO_STA_CCRCFAIL_Pos (0U)
10725#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
10726#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
10727#define SDIO_STA_DCRCFAIL_Pos (1U)
10728#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
10729#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
10730#define SDIO_STA_CTIMEOUT_Pos (2U)
10731#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
10732#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
10733#define SDIO_STA_DTIMEOUT_Pos (3U)
10734#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
10735#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
10736#define SDIO_STA_TXUNDERR_Pos (4U)
10737#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
10738#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
10739#define SDIO_STA_RXOVERR_Pos (5U)
10740#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
10741#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
10742#define SDIO_STA_CMDREND_Pos (6U)
10743#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
10744#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
10745#define SDIO_STA_CMDSENT_Pos (7U)
10746#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
10747#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
10748#define SDIO_STA_DATAEND_Pos (8U)
10749#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
10750#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
10751#define SDIO_STA_STBITERR_Pos (9U)
10752#define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)
10753#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk
10754#define SDIO_STA_DBCKEND_Pos (10U)
10755#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
10756#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
10757#define SDIO_STA_CMDACT_Pos (11U)
10758#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
10759#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
10760#define SDIO_STA_TXACT_Pos (12U)
10761#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
10762#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
10763#define SDIO_STA_RXACT_Pos (13U)
10764#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
10765#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
10766#define SDIO_STA_TXFIFOHE_Pos (14U)
10767#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
10768#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
10769#define SDIO_STA_RXFIFOHF_Pos (15U)
10770#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
10771#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
10772#define SDIO_STA_TXFIFOF_Pos (16U)
10773#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
10774#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
10775#define SDIO_STA_RXFIFOF_Pos (17U)
10776#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
10777#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
10778#define SDIO_STA_TXFIFOE_Pos (18U)
10779#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
10780#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
10781#define SDIO_STA_RXFIFOE_Pos (19U)
10782#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
10783#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
10784#define SDIO_STA_TXDAVL_Pos (20U)
10785#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
10786#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
10787#define SDIO_STA_RXDAVL_Pos (21U)
10788#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
10789#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
10790#define SDIO_STA_SDIOIT_Pos (22U)
10791#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
10792#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
10793#define SDIO_STA_CEATAEND_Pos (23U)
10794#define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)
10795#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk
10798#define SDIO_ICR_CCRCFAILC_Pos (0U)
10799#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
10800#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
10801#define SDIO_ICR_DCRCFAILC_Pos (1U)
10802#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
10803#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
10804#define SDIO_ICR_CTIMEOUTC_Pos (2U)
10805#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
10806#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
10807#define SDIO_ICR_DTIMEOUTC_Pos (3U)
10808#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
10809#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
10810#define SDIO_ICR_TXUNDERRC_Pos (4U)
10811#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
10812#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
10813#define SDIO_ICR_RXOVERRC_Pos (5U)
10814#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
10815#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
10816#define SDIO_ICR_CMDRENDC_Pos (6U)
10817#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
10818#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
10819#define SDIO_ICR_CMDSENTC_Pos (7U)
10820#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
10821#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
10822#define SDIO_ICR_DATAENDC_Pos (8U)
10823#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
10824#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
10825#define SDIO_ICR_STBITERRC_Pos (9U)
10826#define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)
10827#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk
10828#define SDIO_ICR_DBCKENDC_Pos (10U)
10829#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
10830#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
10831#define SDIO_ICR_SDIOITC_Pos (22U)
10832#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
10833#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
10834#define SDIO_ICR_CEATAENDC_Pos (23U)
10835#define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)
10836#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk
10839#define SDIO_MASK_CCRCFAILIE_Pos (0U)
10840#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
10841#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
10842#define SDIO_MASK_DCRCFAILIE_Pos (1U)
10843#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
10844#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
10845#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
10846#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
10847#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
10848#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
10849#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
10850#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
10851#define SDIO_MASK_TXUNDERRIE_Pos (4U)
10852#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
10853#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
10854#define SDIO_MASK_RXOVERRIE_Pos (5U)
10855#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
10856#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
10857#define SDIO_MASK_CMDRENDIE_Pos (6U)
10858#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
10859#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
10860#define SDIO_MASK_CMDSENTIE_Pos (7U)
10861#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
10862#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
10863#define SDIO_MASK_DATAENDIE_Pos (8U)
10864#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
10865#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
10866#define SDIO_MASK_STBITERRIE_Pos (9U)
10867#define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)
10868#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk
10869#define SDIO_MASK_DBCKENDIE_Pos (10U)
10870#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
10871#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
10872#define SDIO_MASK_CMDACTIE_Pos (11U)
10873#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
10874#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
10875#define SDIO_MASK_TXACTIE_Pos (12U)
10876#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
10877#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
10878#define SDIO_MASK_RXACTIE_Pos (13U)
10879#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
10880#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
10881#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
10882#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
10883#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
10884#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
10885#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
10886#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
10887#define SDIO_MASK_TXFIFOFIE_Pos (16U)
10888#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
10889#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
10890#define SDIO_MASK_RXFIFOFIE_Pos (17U)
10891#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
10892#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
10893#define SDIO_MASK_TXFIFOEIE_Pos (18U)
10894#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
10895#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
10896#define SDIO_MASK_RXFIFOEIE_Pos (19U)
10897#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
10898#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
10899#define SDIO_MASK_TXDAVLIE_Pos (20U)
10900#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
10901#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
10902#define SDIO_MASK_RXDAVLIE_Pos (21U)
10903#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
10904#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
10905#define SDIO_MASK_SDIOITIE_Pos (22U)
10906#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
10907#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
10908#define SDIO_MASK_CEATAENDIE_Pos (23U)
10909#define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
10910#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk
10913#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
10914#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
10915#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
10918#define SDIO_FIFO_FIFODATA_Pos (0U)
10919#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
10920#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
10928#define SPI_CR1_CPHA_Pos (0U)
10929#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
10930#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
10931#define SPI_CR1_CPOL_Pos (1U)
10932#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
10933#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
10934#define SPI_CR1_MSTR_Pos (2U)
10935#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
10936#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
10938#define SPI_CR1_BR_Pos (3U)
10939#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
10940#define SPI_CR1_BR SPI_CR1_BR_Msk
10941#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
10942#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
10943#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
10945#define SPI_CR1_SPE_Pos (6U)
10946#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
10947#define SPI_CR1_SPE SPI_CR1_SPE_Msk
10948#define SPI_CR1_LSBFIRST_Pos (7U)
10949#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
10950#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
10951#define SPI_CR1_SSI_Pos (8U)
10952#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
10953#define SPI_CR1_SSI SPI_CR1_SSI_Msk
10954#define SPI_CR1_SSM_Pos (9U)
10955#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
10956#define SPI_CR1_SSM SPI_CR1_SSM_Msk
10957#define SPI_CR1_RXONLY_Pos (10U)
10958#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
10959#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
10960#define SPI_CR1_DFF_Pos (11U)
10961#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
10962#define SPI_CR1_DFF SPI_CR1_DFF_Msk
10963#define SPI_CR1_CRCNEXT_Pos (12U)
10964#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
10965#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
10966#define SPI_CR1_CRCEN_Pos (13U)
10967#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
10968#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
10969#define SPI_CR1_BIDIOE_Pos (14U)
10970#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
10971#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
10972#define SPI_CR1_BIDIMODE_Pos (15U)
10973#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
10974#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
10977#define SPI_CR2_RXDMAEN_Pos (0U)
10978#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
10979#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
10980#define SPI_CR2_TXDMAEN_Pos (1U)
10981#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
10982#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
10983#define SPI_CR2_SSOE_Pos (2U)
10984#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
10985#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
10986#define SPI_CR2_FRF_Pos (4U)
10987#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
10988#define SPI_CR2_FRF SPI_CR2_FRF_Msk
10989#define SPI_CR2_ERRIE_Pos (5U)
10990#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
10991#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
10992#define SPI_CR2_RXNEIE_Pos (6U)
10993#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
10994#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
10995#define SPI_CR2_TXEIE_Pos (7U)
10996#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
10997#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
11000#define SPI_SR_RXNE_Pos (0U)
11001#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
11002#define SPI_SR_RXNE SPI_SR_RXNE_Msk
11003#define SPI_SR_TXE_Pos (1U)
11004#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
11005#define SPI_SR_TXE SPI_SR_TXE_Msk
11006#define SPI_SR_CHSIDE_Pos (2U)
11007#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
11008#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
11009#define SPI_SR_UDR_Pos (3U)
11010#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
11011#define SPI_SR_UDR SPI_SR_UDR_Msk
11012#define SPI_SR_CRCERR_Pos (4U)
11013#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
11014#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
11015#define SPI_SR_MODF_Pos (5U)
11016#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
11017#define SPI_SR_MODF SPI_SR_MODF_Msk
11018#define SPI_SR_OVR_Pos (6U)
11019#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
11020#define SPI_SR_OVR SPI_SR_OVR_Msk
11021#define SPI_SR_BSY_Pos (7U)
11022#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
11023#define SPI_SR_BSY SPI_SR_BSY_Msk
11024#define SPI_SR_FRE_Pos (8U)
11025#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
11026#define SPI_SR_FRE SPI_SR_FRE_Msk
11029#define SPI_DR_DR_Pos (0U)
11030#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
11031#define SPI_DR_DR SPI_DR_DR_Msk
11034#define SPI_CRCPR_CRCPOLY_Pos (0U)
11035#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
11036#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
11039#define SPI_RXCRCR_RXCRC_Pos (0U)
11040#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
11041#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
11044#define SPI_TXCRCR_TXCRC_Pos (0U)
11045#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
11046#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
11049#define SPI_I2SCFGR_CHLEN_Pos (0U)
11050#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
11051#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
11053#define SPI_I2SCFGR_DATLEN_Pos (1U)
11054#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
11055#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
11056#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
11057#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
11059#define SPI_I2SCFGR_CKPOL_Pos (3U)
11060#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
11061#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
11063#define SPI_I2SCFGR_I2SSTD_Pos (4U)
11064#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
11065#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
11066#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
11067#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
11069#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
11070#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
11071#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
11073#define SPI_I2SCFGR_I2SCFG_Pos (8U)
11074#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
11075#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
11076#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
11077#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
11079#define SPI_I2SCFGR_I2SE_Pos (10U)
11080#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
11081#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
11082#define SPI_I2SCFGR_I2SMOD_Pos (11U)
11083#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
11084#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
11087#define SPI_I2SPR_I2SDIV_Pos (0U)
11088#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
11089#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
11090#define SPI_I2SPR_ODD_Pos (8U)
11091#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
11092#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
11093#define SPI_I2SPR_MCKOE_Pos (9U)
11094#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
11095#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
11103#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
11104#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11105#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
11106#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11107#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11109#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
11110#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
11111#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
11114#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
11115#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
11116#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
11117#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
11118#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
11119#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
11120#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
11121#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
11122#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
11123#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
11124#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
11125#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
11129#define SYSCFG_EXTICR1_EXTI0_PA 0x00000000U
11130#define SYSCFG_EXTICR1_EXTI0_PB 0x00000001U
11131#define SYSCFG_EXTICR1_EXTI0_PC 0x00000002U
11132#define SYSCFG_EXTICR1_EXTI0_PD 0x00000003U
11133#define SYSCFG_EXTICR1_EXTI0_PE 0x00000004U
11134#define SYSCFG_EXTICR1_EXTI0_PF 0x00000005U
11135#define SYSCFG_EXTICR1_EXTI0_PG 0x00000006U
11136#define SYSCFG_EXTICR1_EXTI0_PH 0x00000007U
11137#define SYSCFG_EXTICR1_EXTI0_PI 0x00000008U
11141#define SYSCFG_EXTICR1_EXTI1_PA 0x00000000U
11142#define SYSCFG_EXTICR1_EXTI1_PB 0x00000010U
11143#define SYSCFG_EXTICR1_EXTI1_PC 0x00000020U
11144#define SYSCFG_EXTICR1_EXTI1_PD 0x00000030U
11145#define SYSCFG_EXTICR1_EXTI1_PE 0x00000040U
11146#define SYSCFG_EXTICR1_EXTI1_PF 0x00000050U
11147#define SYSCFG_EXTICR1_EXTI1_PG 0x00000060U
11148#define SYSCFG_EXTICR1_EXTI1_PH 0x00000070U
11149#define SYSCFG_EXTICR1_EXTI1_PI 0x00000080U
11153#define SYSCFG_EXTICR1_EXTI2_PA 0x00000000U
11154#define SYSCFG_EXTICR1_EXTI2_PB 0x00000100U
11155#define SYSCFG_EXTICR1_EXTI2_PC 0x00000200U
11156#define SYSCFG_EXTICR1_EXTI2_PD 0x00000300U
11157#define SYSCFG_EXTICR1_EXTI2_PE 0x00000400U
11158#define SYSCFG_EXTICR1_EXTI2_PF 0x00000500U
11159#define SYSCFG_EXTICR1_EXTI2_PG 0x00000600U
11160#define SYSCFG_EXTICR1_EXTI2_PH 0x00000700U
11161#define SYSCFG_EXTICR1_EXTI2_PI 0x00000800U
11165#define SYSCFG_EXTICR1_EXTI3_PA 0x00000000U
11166#define SYSCFG_EXTICR1_EXTI3_PB 0x00001000U
11167#define SYSCFG_EXTICR1_EXTI3_PC 0x00002000U
11168#define SYSCFG_EXTICR1_EXTI3_PD 0x00003000U
11169#define SYSCFG_EXTICR1_EXTI3_PE 0x00004000U
11170#define SYSCFG_EXTICR1_EXTI3_PF 0x00005000U
11171#define SYSCFG_EXTICR1_EXTI3_PG 0x00006000U
11172#define SYSCFG_EXTICR1_EXTI3_PH 0x00007000U
11173#define SYSCFG_EXTICR1_EXTI3_PI 0x00008000U
11176#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
11177#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
11178#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
11179#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
11180#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
11181#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
11182#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
11183#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
11184#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
11185#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
11186#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
11187#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
11191#define SYSCFG_EXTICR2_EXTI4_PA 0x00000000U
11192#define SYSCFG_EXTICR2_EXTI4_PB 0x00000001U
11193#define SYSCFG_EXTICR2_EXTI4_PC 0x00000002U
11194#define SYSCFG_EXTICR2_EXTI4_PD 0x00000003U
11195#define SYSCFG_EXTICR2_EXTI4_PE 0x00000004U
11196#define SYSCFG_EXTICR2_EXTI4_PF 0x00000005U
11197#define SYSCFG_EXTICR2_EXTI4_PG 0x00000006U
11198#define SYSCFG_EXTICR2_EXTI4_PH 0x00000007U
11199#define SYSCFG_EXTICR2_EXTI4_PI 0x00000008U
11203#define SYSCFG_EXTICR2_EXTI5_PA 0x00000000U
11204#define SYSCFG_EXTICR2_EXTI5_PB 0x00000010U
11205#define SYSCFG_EXTICR2_EXTI5_PC 0x00000020U
11206#define SYSCFG_EXTICR2_EXTI5_PD 0x00000030U
11207#define SYSCFG_EXTICR2_EXTI5_PE 0x00000040U
11208#define SYSCFG_EXTICR2_EXTI5_PF 0x00000050U
11209#define SYSCFG_EXTICR2_EXTI5_PG 0x00000060U
11210#define SYSCFG_EXTICR2_EXTI5_PH 0x00000070U
11211#define SYSCFG_EXTICR2_EXTI5_PI 0x00000080U
11215#define SYSCFG_EXTICR2_EXTI6_PA 0x00000000U
11216#define SYSCFG_EXTICR2_EXTI6_PB 0x00000100U
11217#define SYSCFG_EXTICR2_EXTI6_PC 0x00000200U
11218#define SYSCFG_EXTICR2_EXTI6_PD 0x00000300U
11219#define SYSCFG_EXTICR2_EXTI6_PE 0x00000400U
11220#define SYSCFG_EXTICR2_EXTI6_PF 0x00000500U
11221#define SYSCFG_EXTICR2_EXTI6_PG 0x00000600U
11222#define SYSCFG_EXTICR2_EXTI6_PH 0x00000700U
11223#define SYSCFG_EXTICR2_EXTI6_PI 0x00000800U
11227#define SYSCFG_EXTICR2_EXTI7_PA 0x00000000U
11228#define SYSCFG_EXTICR2_EXTI7_PB 0x00001000U
11229#define SYSCFG_EXTICR2_EXTI7_PC 0x00002000U
11230#define SYSCFG_EXTICR2_EXTI7_PD 0x00003000U
11231#define SYSCFG_EXTICR2_EXTI7_PE 0x00004000U
11232#define SYSCFG_EXTICR2_EXTI7_PF 0x00005000U
11233#define SYSCFG_EXTICR2_EXTI7_PG 0x00006000U
11234#define SYSCFG_EXTICR2_EXTI7_PH 0x00007000U
11235#define SYSCFG_EXTICR2_EXTI7_PI 0x00008000U
11238#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
11239#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
11240#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
11241#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
11242#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
11243#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
11244#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
11245#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
11246#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
11247#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
11248#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
11249#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
11254#define SYSCFG_EXTICR3_EXTI8_PA 0x00000000U
11255#define SYSCFG_EXTICR3_EXTI8_PB 0x00000001U
11256#define SYSCFG_EXTICR3_EXTI8_PC 0x00000002U
11257#define SYSCFG_EXTICR3_EXTI8_PD 0x00000003U
11258#define SYSCFG_EXTICR3_EXTI8_PE 0x00000004U
11259#define SYSCFG_EXTICR3_EXTI8_PF 0x00000005U
11260#define SYSCFG_EXTICR3_EXTI8_PG 0x00000006U
11261#define SYSCFG_EXTICR3_EXTI8_PH 0x00000007U
11262#define SYSCFG_EXTICR3_EXTI8_PI 0x00000008U
11266#define SYSCFG_EXTICR3_EXTI9_PA 0x00000000U
11267#define SYSCFG_EXTICR3_EXTI9_PB 0x00000010U
11268#define SYSCFG_EXTICR3_EXTI9_PC 0x00000020U
11269#define SYSCFG_EXTICR3_EXTI9_PD 0x00000030U
11270#define SYSCFG_EXTICR3_EXTI9_PE 0x00000040U
11271#define SYSCFG_EXTICR3_EXTI9_PF 0x00000050U
11272#define SYSCFG_EXTICR3_EXTI9_PG 0x00000060U
11273#define SYSCFG_EXTICR3_EXTI9_PH 0x00000070U
11274#define SYSCFG_EXTICR3_EXTI9_PI 0x00000080U
11278#define SYSCFG_EXTICR3_EXTI10_PA 0x00000000U
11279#define SYSCFG_EXTICR3_EXTI10_PB 0x00000100U
11280#define SYSCFG_EXTICR3_EXTI10_PC 0x00000200U
11281#define SYSCFG_EXTICR3_EXTI10_PD 0x00000300U
11282#define SYSCFG_EXTICR3_EXTI10_PE 0x00000400U
11283#define SYSCFG_EXTICR3_EXTI10_PF 0x00000500U
11284#define SYSCFG_EXTICR3_EXTI10_PG 0x00000600U
11285#define SYSCFG_EXTICR3_EXTI10_PH 0x00000700U
11286#define SYSCFG_EXTICR3_EXTI10_PI 0x00000800U
11290#define SYSCFG_EXTICR3_EXTI11_PA 0x00000000U
11291#define SYSCFG_EXTICR3_EXTI11_PB 0x00001000U
11292#define SYSCFG_EXTICR3_EXTI11_PC 0x00002000U
11293#define SYSCFG_EXTICR3_EXTI11_PD 0x00003000U
11294#define SYSCFG_EXTICR3_EXTI11_PE 0x00004000U
11295#define SYSCFG_EXTICR3_EXTI11_PF 0x00005000U
11296#define SYSCFG_EXTICR3_EXTI11_PG 0x00006000U
11297#define SYSCFG_EXTICR3_EXTI11_PH 0x00007000U
11298#define SYSCFG_EXTICR3_EXTI11_PI 0x00008000U
11301#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
11302#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
11303#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
11304#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
11305#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
11306#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
11307#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
11308#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
11309#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
11310#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
11311#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
11312#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
11316#define SYSCFG_EXTICR4_EXTI12_PA 0x00000000U
11317#define SYSCFG_EXTICR4_EXTI12_PB 0x00000001U
11318#define SYSCFG_EXTICR4_EXTI12_PC 0x00000002U
11319#define SYSCFG_EXTICR4_EXTI12_PD 0x00000003U
11320#define SYSCFG_EXTICR4_EXTI12_PE 0x00000004U
11321#define SYSCFG_EXTICR4_EXTI12_PF 0x00000005U
11322#define SYSCFG_EXTICR4_EXTI12_PG 0x00000006U
11323#define SYSCFG_EXTICR3_EXTI12_PH 0x00000007U
11327#define SYSCFG_EXTICR4_EXTI13_PA 0x00000000U
11328#define SYSCFG_EXTICR4_EXTI13_PB 0x00000010U
11329#define SYSCFG_EXTICR4_EXTI13_PC 0x00000020U
11330#define SYSCFG_EXTICR4_EXTI13_PD 0x00000030U
11331#define SYSCFG_EXTICR4_EXTI13_PE 0x00000040U
11332#define SYSCFG_EXTICR4_EXTI13_PF 0x00000050U
11333#define SYSCFG_EXTICR4_EXTI13_PG 0x00000060U
11334#define SYSCFG_EXTICR3_EXTI13_PH 0x00000070U
11338#define SYSCFG_EXTICR4_EXTI14_PA 0x00000000U
11339#define SYSCFG_EXTICR4_EXTI14_PB 0x00000100U
11340#define SYSCFG_EXTICR4_EXTI14_PC 0x00000200U
11341#define SYSCFG_EXTICR4_EXTI14_PD 0x00000300U
11342#define SYSCFG_EXTICR4_EXTI14_PE 0x00000400U
11343#define SYSCFG_EXTICR4_EXTI14_PF 0x00000500U
11344#define SYSCFG_EXTICR4_EXTI14_PG 0x00000600U
11345#define SYSCFG_EXTICR3_EXTI14_PH 0x00000700U
11349#define SYSCFG_EXTICR4_EXTI15_PA 0x00000000U
11350#define SYSCFG_EXTICR4_EXTI15_PB 0x00001000U
11351#define SYSCFG_EXTICR4_EXTI15_PC 0x00002000U
11352#define SYSCFG_EXTICR4_EXTI15_PD 0x00003000U
11353#define SYSCFG_EXTICR4_EXTI15_PE 0x00004000U
11354#define SYSCFG_EXTICR4_EXTI15_PF 0x00005000U
11355#define SYSCFG_EXTICR4_EXTI15_PG 0x00006000U
11356#define SYSCFG_EXTICR3_EXTI15_PH 0x00007000U
11359#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
11360#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
11361#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
11362#define SYSCFG_CMPCR_READY_Pos (8U)
11363#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
11364#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
11372#define TIM_CR1_CEN_Pos (0U)
11373#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
11374#define TIM_CR1_CEN TIM_CR1_CEN_Msk
11375#define TIM_CR1_UDIS_Pos (1U)
11376#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
11377#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
11378#define TIM_CR1_URS_Pos (2U)
11379#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
11380#define TIM_CR1_URS TIM_CR1_URS_Msk
11381#define TIM_CR1_OPM_Pos (3U)
11382#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
11383#define TIM_CR1_OPM TIM_CR1_OPM_Msk
11384#define TIM_CR1_DIR_Pos (4U)
11385#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
11386#define TIM_CR1_DIR TIM_CR1_DIR_Msk
11388#define TIM_CR1_CMS_Pos (5U)
11389#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
11390#define TIM_CR1_CMS TIM_CR1_CMS_Msk
11391#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
11392#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
11394#define TIM_CR1_ARPE_Pos (7U)
11395#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
11396#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
11398#define TIM_CR1_CKD_Pos (8U)
11399#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
11400#define TIM_CR1_CKD TIM_CR1_CKD_Msk
11401#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
11402#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
11405#define TIM_CR2_CCPC_Pos (0U)
11406#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
11407#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
11408#define TIM_CR2_CCUS_Pos (2U)
11409#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
11410#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
11411#define TIM_CR2_CCDS_Pos (3U)
11412#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
11413#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
11415#define TIM_CR2_MMS_Pos (4U)
11416#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
11417#define TIM_CR2_MMS TIM_CR2_MMS_Msk
11418#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
11419#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
11420#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
11422#define TIM_CR2_TI1S_Pos (7U)
11423#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
11424#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
11425#define TIM_CR2_OIS1_Pos (8U)
11426#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
11427#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
11428#define TIM_CR2_OIS1N_Pos (9U)
11429#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
11430#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
11431#define TIM_CR2_OIS2_Pos (10U)
11432#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
11433#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
11434#define TIM_CR2_OIS2N_Pos (11U)
11435#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
11436#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
11437#define TIM_CR2_OIS3_Pos (12U)
11438#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
11439#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
11440#define TIM_CR2_OIS3N_Pos (13U)
11441#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
11442#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
11443#define TIM_CR2_OIS4_Pos (14U)
11444#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
11445#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
11448#define TIM_SMCR_SMS_Pos (0U)
11449#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
11450#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
11451#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
11452#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
11453#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
11455#define TIM_SMCR_TS_Pos (4U)
11456#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
11457#define TIM_SMCR_TS TIM_SMCR_TS_Msk
11458#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
11459#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
11460#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
11462#define TIM_SMCR_MSM_Pos (7U)
11463#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
11464#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
11466#define TIM_SMCR_ETF_Pos (8U)
11467#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
11468#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
11469#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
11470#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
11471#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
11472#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
11474#define TIM_SMCR_ETPS_Pos (12U)
11475#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
11476#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
11477#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
11478#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
11480#define TIM_SMCR_ECE_Pos (14U)
11481#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
11482#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
11483#define TIM_SMCR_ETP_Pos (15U)
11484#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
11485#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
11488#define TIM_DIER_UIE_Pos (0U)
11489#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
11490#define TIM_DIER_UIE TIM_DIER_UIE_Msk
11491#define TIM_DIER_CC1IE_Pos (1U)
11492#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
11493#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
11494#define TIM_DIER_CC2IE_Pos (2U)
11495#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
11496#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
11497#define TIM_DIER_CC3IE_Pos (3U)
11498#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
11499#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
11500#define TIM_DIER_CC4IE_Pos (4U)
11501#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
11502#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
11503#define TIM_DIER_COMIE_Pos (5U)
11504#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
11505#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
11506#define TIM_DIER_TIE_Pos (6U)
11507#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
11508#define TIM_DIER_TIE TIM_DIER_TIE_Msk
11509#define TIM_DIER_BIE_Pos (7U)
11510#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
11511#define TIM_DIER_BIE TIM_DIER_BIE_Msk
11512#define TIM_DIER_UDE_Pos (8U)
11513#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
11514#define TIM_DIER_UDE TIM_DIER_UDE_Msk
11515#define TIM_DIER_CC1DE_Pos (9U)
11516#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
11517#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
11518#define TIM_DIER_CC2DE_Pos (10U)
11519#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
11520#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
11521#define TIM_DIER_CC3DE_Pos (11U)
11522#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
11523#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
11524#define TIM_DIER_CC4DE_Pos (12U)
11525#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
11526#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
11527#define TIM_DIER_COMDE_Pos (13U)
11528#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
11529#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
11530#define TIM_DIER_TDE_Pos (14U)
11531#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
11532#define TIM_DIER_TDE TIM_DIER_TDE_Msk
11535#define TIM_SR_UIF_Pos (0U)
11536#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
11537#define TIM_SR_UIF TIM_SR_UIF_Msk
11538#define TIM_SR_CC1IF_Pos (1U)
11539#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
11540#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
11541#define TIM_SR_CC2IF_Pos (2U)
11542#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
11543#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
11544#define TIM_SR_CC3IF_Pos (3U)
11545#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
11546#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
11547#define TIM_SR_CC4IF_Pos (4U)
11548#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
11549#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
11550#define TIM_SR_COMIF_Pos (5U)
11551#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
11552#define TIM_SR_COMIF TIM_SR_COMIF_Msk
11553#define TIM_SR_TIF_Pos (6U)
11554#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
11555#define TIM_SR_TIF TIM_SR_TIF_Msk
11556#define TIM_SR_BIF_Pos (7U)
11557#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
11558#define TIM_SR_BIF TIM_SR_BIF_Msk
11559#define TIM_SR_CC1OF_Pos (9U)
11560#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
11561#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
11562#define TIM_SR_CC2OF_Pos (10U)
11563#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
11564#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
11565#define TIM_SR_CC3OF_Pos (11U)
11566#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
11567#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
11568#define TIM_SR_CC4OF_Pos (12U)
11569#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
11570#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
11573#define TIM_EGR_UG_Pos (0U)
11574#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
11575#define TIM_EGR_UG TIM_EGR_UG_Msk
11576#define TIM_EGR_CC1G_Pos (1U)
11577#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
11578#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
11579#define TIM_EGR_CC2G_Pos (2U)
11580#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
11581#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
11582#define TIM_EGR_CC3G_Pos (3U)
11583#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
11584#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
11585#define TIM_EGR_CC4G_Pos (4U)
11586#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
11587#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
11588#define TIM_EGR_COMG_Pos (5U)
11589#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
11590#define TIM_EGR_COMG TIM_EGR_COMG_Msk
11591#define TIM_EGR_TG_Pos (6U)
11592#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
11593#define TIM_EGR_TG TIM_EGR_TG_Msk
11594#define TIM_EGR_BG_Pos (7U)
11595#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
11596#define TIM_EGR_BG TIM_EGR_BG_Msk
11599#define TIM_CCMR1_CC1S_Pos (0U)
11600#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
11601#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
11602#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
11603#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
11605#define TIM_CCMR1_OC1FE_Pos (2U)
11606#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
11607#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
11608#define TIM_CCMR1_OC1PE_Pos (3U)
11609#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
11610#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
11612#define TIM_CCMR1_OC1M_Pos (4U)
11613#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
11614#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
11615#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
11616#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
11617#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
11619#define TIM_CCMR1_OC1CE_Pos (7U)
11620#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
11621#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
11623#define TIM_CCMR1_CC2S_Pos (8U)
11624#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
11625#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
11626#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
11627#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
11629#define TIM_CCMR1_OC2FE_Pos (10U)
11630#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
11631#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
11632#define TIM_CCMR1_OC2PE_Pos (11U)
11633#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
11634#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
11636#define TIM_CCMR1_OC2M_Pos (12U)
11637#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
11638#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
11639#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
11640#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
11641#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
11643#define TIM_CCMR1_OC2CE_Pos (15U)
11644#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
11645#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
11649#define TIM_CCMR1_IC1PSC_Pos (2U)
11650#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
11651#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
11652#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
11653#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
11655#define TIM_CCMR1_IC1F_Pos (4U)
11656#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
11657#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
11658#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
11659#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
11660#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
11661#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
11663#define TIM_CCMR1_IC2PSC_Pos (10U)
11664#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
11665#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
11666#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
11667#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
11669#define TIM_CCMR1_IC2F_Pos (12U)
11670#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
11671#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
11672#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
11673#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
11674#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
11675#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
11678#define TIM_CCMR2_CC3S_Pos (0U)
11679#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
11680#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
11681#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
11682#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
11684#define TIM_CCMR2_OC3FE_Pos (2U)
11685#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
11686#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
11687#define TIM_CCMR2_OC3PE_Pos (3U)
11688#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
11689#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
11691#define TIM_CCMR2_OC3M_Pos (4U)
11692#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
11693#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
11694#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
11695#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
11696#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
11698#define TIM_CCMR2_OC3CE_Pos (7U)
11699#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
11700#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
11702#define TIM_CCMR2_CC4S_Pos (8U)
11703#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
11704#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
11705#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
11706#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
11708#define TIM_CCMR2_OC4FE_Pos (10U)
11709#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
11710#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
11711#define TIM_CCMR2_OC4PE_Pos (11U)
11712#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
11713#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
11715#define TIM_CCMR2_OC4M_Pos (12U)
11716#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
11717#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
11718#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
11719#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
11720#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
11722#define TIM_CCMR2_OC4CE_Pos (15U)
11723#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
11724#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
11728#define TIM_CCMR2_IC3PSC_Pos (2U)
11729#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
11730#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
11731#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
11732#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
11734#define TIM_CCMR2_IC3F_Pos (4U)
11735#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
11736#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
11737#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
11738#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
11739#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
11740#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
11742#define TIM_CCMR2_IC4PSC_Pos (10U)
11743#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
11744#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
11745#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
11746#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
11748#define TIM_CCMR2_IC4F_Pos (12U)
11749#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
11750#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
11751#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
11752#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
11753#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
11754#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
11757#define TIM_CCER_CC1E_Pos (0U)
11758#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
11759#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
11760#define TIM_CCER_CC1P_Pos (1U)
11761#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
11762#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
11763#define TIM_CCER_CC1NE_Pos (2U)
11764#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
11765#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
11766#define TIM_CCER_CC1NP_Pos (3U)
11767#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
11768#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
11769#define TIM_CCER_CC2E_Pos (4U)
11770#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
11771#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
11772#define TIM_CCER_CC2P_Pos (5U)
11773#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
11774#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
11775#define TIM_CCER_CC2NE_Pos (6U)
11776#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
11777#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
11778#define TIM_CCER_CC2NP_Pos (7U)
11779#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
11780#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
11781#define TIM_CCER_CC3E_Pos (8U)
11782#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
11783#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
11784#define TIM_CCER_CC3P_Pos (9U)
11785#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
11786#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
11787#define TIM_CCER_CC3NE_Pos (10U)
11788#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
11789#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
11790#define TIM_CCER_CC3NP_Pos (11U)
11791#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
11792#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
11793#define TIM_CCER_CC4E_Pos (12U)
11794#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
11795#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
11796#define TIM_CCER_CC4P_Pos (13U)
11797#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
11798#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
11799#define TIM_CCER_CC4NP_Pos (15U)
11800#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
11801#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
11804#define TIM_CNT_CNT_Pos (0U)
11805#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
11806#define TIM_CNT_CNT TIM_CNT_CNT_Msk
11809#define TIM_PSC_PSC_Pos (0U)
11810#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
11811#define TIM_PSC_PSC TIM_PSC_PSC_Msk
11814#define TIM_ARR_ARR_Pos (0U)
11815#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
11816#define TIM_ARR_ARR TIM_ARR_ARR_Msk
11819#define TIM_RCR_REP_Pos (0U)
11820#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
11821#define TIM_RCR_REP TIM_RCR_REP_Msk
11824#define TIM_CCR1_CCR1_Pos (0U)
11825#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
11826#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
11829#define TIM_CCR2_CCR2_Pos (0U)
11830#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
11831#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
11834#define TIM_CCR3_CCR3_Pos (0U)
11835#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
11836#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
11839#define TIM_CCR4_CCR4_Pos (0U)
11840#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
11841#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
11844#define TIM_BDTR_DTG_Pos (0U)
11845#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
11846#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
11847#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
11848#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
11849#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
11850#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
11851#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
11852#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
11853#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
11854#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
11856#define TIM_BDTR_LOCK_Pos (8U)
11857#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
11858#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
11859#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
11860#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
11862#define TIM_BDTR_OSSI_Pos (10U)
11863#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
11864#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
11865#define TIM_BDTR_OSSR_Pos (11U)
11866#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
11867#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
11868#define TIM_BDTR_BKE_Pos (12U)
11869#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
11870#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
11871#define TIM_BDTR_BKP_Pos (13U)
11872#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
11873#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
11874#define TIM_BDTR_AOE_Pos (14U)
11875#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
11876#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
11877#define TIM_BDTR_MOE_Pos (15U)
11878#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
11879#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
11882#define TIM_DCR_DBA_Pos (0U)
11883#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
11884#define TIM_DCR_DBA TIM_DCR_DBA_Msk
11885#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
11886#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
11887#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
11888#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
11889#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
11891#define TIM_DCR_DBL_Pos (8U)
11892#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
11893#define TIM_DCR_DBL TIM_DCR_DBL_Msk
11894#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
11895#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
11896#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
11897#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
11898#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
11901#define TIM_DMAR_DMAB_Pos (0U)
11902#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
11903#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
11906#define TIM_OR_TI1_RMP_Pos (0U)
11907#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
11908#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
11909#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
11910#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
11911#define TIM_OR_TI4_RMP_Pos (6U)
11912#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
11913#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
11914#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
11915#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
11916#define TIM_OR_ITR1_RMP_Pos (10U)
11917#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
11918#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
11919#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
11920#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
11928#define USART_SR_PE_Pos (0U)
11929#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
11930#define USART_SR_PE USART_SR_PE_Msk
11931#define USART_SR_FE_Pos (1U)
11932#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
11933#define USART_SR_FE USART_SR_FE_Msk
11934#define USART_SR_NE_Pos (2U)
11935#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
11936#define USART_SR_NE USART_SR_NE_Msk
11937#define USART_SR_ORE_Pos (3U)
11938#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
11939#define USART_SR_ORE USART_SR_ORE_Msk
11940#define USART_SR_IDLE_Pos (4U)
11941#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
11942#define USART_SR_IDLE USART_SR_IDLE_Msk
11943#define USART_SR_RXNE_Pos (5U)
11944#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
11945#define USART_SR_RXNE USART_SR_RXNE_Msk
11946#define USART_SR_TC_Pos (6U)
11947#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
11948#define USART_SR_TC USART_SR_TC_Msk
11949#define USART_SR_TXE_Pos (7U)
11950#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
11951#define USART_SR_TXE USART_SR_TXE_Msk
11952#define USART_SR_LBD_Pos (8U)
11953#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
11954#define USART_SR_LBD USART_SR_LBD_Msk
11955#define USART_SR_CTS_Pos (9U)
11956#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
11957#define USART_SR_CTS USART_SR_CTS_Msk
11960#define USART_DR_DR_Pos (0U)
11961#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
11962#define USART_DR_DR USART_DR_DR_Msk
11965#define USART_BRR_DIV_Fraction_Pos (0U)
11966#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
11967#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
11968#define USART_BRR_DIV_Mantissa_Pos (4U)
11969#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
11970#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
11973#define USART_CR1_SBK_Pos (0U)
11974#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
11975#define USART_CR1_SBK USART_CR1_SBK_Msk
11976#define USART_CR1_RWU_Pos (1U)
11977#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
11978#define USART_CR1_RWU USART_CR1_RWU_Msk
11979#define USART_CR1_RE_Pos (2U)
11980#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
11981#define USART_CR1_RE USART_CR1_RE_Msk
11982#define USART_CR1_TE_Pos (3U)
11983#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
11984#define USART_CR1_TE USART_CR1_TE_Msk
11985#define USART_CR1_IDLEIE_Pos (4U)
11986#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
11987#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
11988#define USART_CR1_RXNEIE_Pos (5U)
11989#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
11990#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
11991#define USART_CR1_TCIE_Pos (6U)
11992#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
11993#define USART_CR1_TCIE USART_CR1_TCIE_Msk
11994#define USART_CR1_TXEIE_Pos (7U)
11995#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
11996#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
11997#define USART_CR1_PEIE_Pos (8U)
11998#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
11999#define USART_CR1_PEIE USART_CR1_PEIE_Msk
12000#define USART_CR1_PS_Pos (9U)
12001#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
12002#define USART_CR1_PS USART_CR1_PS_Msk
12003#define USART_CR1_PCE_Pos (10U)
12004#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
12005#define USART_CR1_PCE USART_CR1_PCE_Msk
12006#define USART_CR1_WAKE_Pos (11U)
12007#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
12008#define USART_CR1_WAKE USART_CR1_WAKE_Msk
12009#define USART_CR1_M_Pos (12U)
12010#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
12011#define USART_CR1_M USART_CR1_M_Msk
12012#define USART_CR1_UE_Pos (13U)
12013#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
12014#define USART_CR1_UE USART_CR1_UE_Msk
12015#define USART_CR1_OVER8_Pos (15U)
12016#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
12017#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
12020#define USART_CR2_ADD_Pos (0U)
12021#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
12022#define USART_CR2_ADD USART_CR2_ADD_Msk
12023#define USART_CR2_LBDL_Pos (5U)
12024#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
12025#define USART_CR2_LBDL USART_CR2_LBDL_Msk
12026#define USART_CR2_LBDIE_Pos (6U)
12027#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
12028#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
12029#define USART_CR2_LBCL_Pos (8U)
12030#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
12031#define USART_CR2_LBCL USART_CR2_LBCL_Msk
12032#define USART_CR2_CPHA_Pos (9U)
12033#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
12034#define USART_CR2_CPHA USART_CR2_CPHA_Msk
12035#define USART_CR2_CPOL_Pos (10U)
12036#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
12037#define USART_CR2_CPOL USART_CR2_CPOL_Msk
12038#define USART_CR2_CLKEN_Pos (11U)
12039#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
12040#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
12042#define USART_CR2_STOP_Pos (12U)
12043#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
12044#define USART_CR2_STOP USART_CR2_STOP_Msk
12045#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
12046#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
12048#define USART_CR2_LINEN_Pos (14U)
12049#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
12050#define USART_CR2_LINEN USART_CR2_LINEN_Msk
12053#define USART_CR3_EIE_Pos (0U)
12054#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
12055#define USART_CR3_EIE USART_CR3_EIE_Msk
12056#define USART_CR3_IREN_Pos (1U)
12057#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
12058#define USART_CR3_IREN USART_CR3_IREN_Msk
12059#define USART_CR3_IRLP_Pos (2U)
12060#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
12061#define USART_CR3_IRLP USART_CR3_IRLP_Msk
12062#define USART_CR3_HDSEL_Pos (3U)
12063#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
12064#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
12065#define USART_CR3_NACK_Pos (4U)
12066#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
12067#define USART_CR3_NACK USART_CR3_NACK_Msk
12068#define USART_CR3_SCEN_Pos (5U)
12069#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
12070#define USART_CR3_SCEN USART_CR3_SCEN_Msk
12071#define USART_CR3_DMAR_Pos (6U)
12072#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
12073#define USART_CR3_DMAR USART_CR3_DMAR_Msk
12074#define USART_CR3_DMAT_Pos (7U)
12075#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
12076#define USART_CR3_DMAT USART_CR3_DMAT_Msk
12077#define USART_CR3_RTSE_Pos (8U)
12078#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
12079#define USART_CR3_RTSE USART_CR3_RTSE_Msk
12080#define USART_CR3_CTSE_Pos (9U)
12081#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
12082#define USART_CR3_CTSE USART_CR3_CTSE_Msk
12083#define USART_CR3_CTSIE_Pos (10U)
12084#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
12085#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
12086#define USART_CR3_ONEBIT_Pos (11U)
12087#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
12088#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
12091#define USART_GTPR_PSC_Pos (0U)
12092#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
12093#define USART_GTPR_PSC USART_GTPR_PSC_Msk
12094#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
12095#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
12096#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
12097#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
12098#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
12099#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
12100#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
12101#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
12103#define USART_GTPR_GT_Pos (8U)
12104#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
12105#define USART_GTPR_GT USART_GTPR_GT_Msk
12113#define WWDG_CR_T_Pos (0U)
12114#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
12115#define WWDG_CR_T WWDG_CR_T_Msk
12116#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
12117#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
12118#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
12119#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
12120#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
12121#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
12122#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
12125#define WWDG_CR_T0 WWDG_CR_T_0
12126#define WWDG_CR_T1 WWDG_CR_T_1
12127#define WWDG_CR_T2 WWDG_CR_T_2
12128#define WWDG_CR_T3 WWDG_CR_T_3
12129#define WWDG_CR_T4 WWDG_CR_T_4
12130#define WWDG_CR_T5 WWDG_CR_T_5
12131#define WWDG_CR_T6 WWDG_CR_T_6
12132#define WWDG_CR_WDGA_Pos (7U)
12133#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
12134#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
12137#define WWDG_CFR_W_Pos (0U)
12138#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
12139#define WWDG_CFR_W WWDG_CFR_W_Msk
12140#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
12141#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
12142#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
12143#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
12144#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
12145#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
12146#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
12149#define WWDG_CFR_W0 WWDG_CFR_W_0
12150#define WWDG_CFR_W1 WWDG_CFR_W_1
12151#define WWDG_CFR_W2 WWDG_CFR_W_2
12152#define WWDG_CFR_W3 WWDG_CFR_W_3
12153#define WWDG_CFR_W4 WWDG_CFR_W_4
12154#define WWDG_CFR_W5 WWDG_CFR_W_5
12155#define WWDG_CFR_W6 WWDG_CFR_W_6
12157#define WWDG_CFR_WDGTB_Pos (7U)
12158#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
12159#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
12160#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
12161#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
12164#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
12165#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
12167#define WWDG_CFR_EWI_Pos (9U)
12168#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
12169#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
12172#define WWDG_SR_EWIF_Pos (0U)
12173#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
12174#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
12182#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
12183#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
12184#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
12185#define DBGMCU_IDCODE_REV_ID_Pos (16U)
12186#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
12187#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
12190#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
12191#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
12192#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
12193#define DBGMCU_CR_DBG_STOP_Pos (1U)
12194#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
12195#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
12196#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
12197#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
12198#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
12199#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
12200#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
12201#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
12203#define DBGMCU_CR_TRACE_MODE_Pos (6U)
12204#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
12205#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
12206#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
12207#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
12210#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
12211#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
12212#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
12213#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
12214#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
12215#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
12216#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
12217#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
12218#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
12219#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
12220#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
12221#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
12222#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
12223#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
12224#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
12225#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
12226#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
12227#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
12228#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
12229#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
12230#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
12231#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
12232#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
12233#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
12234#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
12235#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
12236#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
12237#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
12238#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
12239#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
12240#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
12241#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
12242#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
12243#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
12244#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
12245#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
12246#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
12247#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
12248#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
12249#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
12250#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
12251#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
12252#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
12253#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
12254#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
12255#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
12256#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
12257#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
12258#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
12259#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
12260#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
12262#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
12265#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
12266#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
12267#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
12268#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
12269#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
12270#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
12271#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
12272#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
12273#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
12274#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
12275#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
12276#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
12277#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
12278#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
12279#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
12287#define ETH_MACCR_WD_Pos (23U)
12288#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
12289#define ETH_MACCR_WD ETH_MACCR_WD_Msk
12290#define ETH_MACCR_JD_Pos (22U)
12291#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
12292#define ETH_MACCR_JD ETH_MACCR_JD_Msk
12293#define ETH_MACCR_IFG_Pos (17U)
12294#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
12295#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk
12296#define ETH_MACCR_IFG_96Bit 0x00000000U
12297#define ETH_MACCR_IFG_88Bit 0x00020000U
12298#define ETH_MACCR_IFG_80Bit 0x00040000U
12299#define ETH_MACCR_IFG_72Bit 0x00060000U
12300#define ETH_MACCR_IFG_64Bit 0x00080000U
12301#define ETH_MACCR_IFG_56Bit 0x000A0000U
12302#define ETH_MACCR_IFG_48Bit 0x000C0000U
12303#define ETH_MACCR_IFG_40Bit 0x000E0000U
12304#define ETH_MACCR_CSD_Pos (16U)
12305#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
12306#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk
12307#define ETH_MACCR_FES_Pos (14U)
12308#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
12309#define ETH_MACCR_FES ETH_MACCR_FES_Msk
12310#define ETH_MACCR_ROD_Pos (13U)
12311#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
12312#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk
12313#define ETH_MACCR_LM_Pos (12U)
12314#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
12315#define ETH_MACCR_LM ETH_MACCR_LM_Msk
12316#define ETH_MACCR_DM_Pos (11U)
12317#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
12318#define ETH_MACCR_DM ETH_MACCR_DM_Msk
12319#define ETH_MACCR_IPCO_Pos (10U)
12320#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
12321#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk
12322#define ETH_MACCR_RD_Pos (9U)
12323#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
12324#define ETH_MACCR_RD ETH_MACCR_RD_Msk
12325#define ETH_MACCR_APCS_Pos (7U)
12326#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
12327#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk
12328#define ETH_MACCR_BL_Pos (5U)
12329#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
12330#define ETH_MACCR_BL ETH_MACCR_BL_Msk
12332#define ETH_MACCR_BL_10 0x00000000U
12333#define ETH_MACCR_BL_8 0x00000020U
12334#define ETH_MACCR_BL_4 0x00000040U
12335#define ETH_MACCR_BL_1 0x00000060U
12336#define ETH_MACCR_DC_Pos (4U)
12337#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
12338#define ETH_MACCR_DC ETH_MACCR_DC_Msk
12339#define ETH_MACCR_TE_Pos (3U)
12340#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
12341#define ETH_MACCR_TE ETH_MACCR_TE_Msk
12342#define ETH_MACCR_RE_Pos (2U)
12343#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
12344#define ETH_MACCR_RE ETH_MACCR_RE_Msk
12347#define ETH_MACFFR_RA_Pos (31U)
12348#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
12349#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk
12350#define ETH_MACFFR_HPF_Pos (10U)
12351#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
12352#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk
12353#define ETH_MACFFR_SAF_Pos (9U)
12354#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
12355#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk
12356#define ETH_MACFFR_SAIF_Pos (8U)
12357#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
12358#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk
12359#define ETH_MACFFR_PCF_Pos (6U)
12360#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
12361#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk
12362#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
12363#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
12364#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk
12365#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
12366#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
12367#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk
12368#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
12369#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
12370#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk
12371#define ETH_MACFFR_BFD_Pos (5U)
12372#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
12373#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk
12374#define ETH_MACFFR_PAM_Pos (4U)
12375#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
12376#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk
12377#define ETH_MACFFR_DAIF_Pos (3U)
12378#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
12379#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk
12380#define ETH_MACFFR_HM_Pos (2U)
12381#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
12382#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk
12383#define ETH_MACFFR_HU_Pos (1U)
12384#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
12385#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk
12386#define ETH_MACFFR_PM_Pos (0U)
12387#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
12388#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk
12391#define ETH_MACHTHR_HTH_Pos (0U)
12392#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
12393#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk
12396#define ETH_MACHTLR_HTL_Pos (0U)
12397#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
12398#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk
12401#define ETH_MACMIIAR_PA_Pos (11U)
12402#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
12403#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk
12404#define ETH_MACMIIAR_MR_Pos (6U)
12405#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
12406#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk
12407#define ETH_MACMIIAR_CR_Pos (2U)
12408#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
12409#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk
12410#define ETH_MACMIIAR_CR_Div42 0x00000000U
12411#define ETH_MACMIIAR_CR_Div62_Pos (2U)
12412#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
12413#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk
12414#define ETH_MACMIIAR_CR_Div16_Pos (3U)
12415#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
12416#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk
12417#define ETH_MACMIIAR_CR_Div26_Pos (2U)
12418#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
12419#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk
12420#define ETH_MACMIIAR_MW_Pos (1U)
12421#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
12422#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk
12423#define ETH_MACMIIAR_MB_Pos (0U)
12424#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
12425#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk
12428#define ETH_MACMIIDR_MD_Pos (0U)
12429#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
12430#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk
12433#define ETH_MACFCR_PT_Pos (16U)
12434#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
12435#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk
12436#define ETH_MACFCR_ZQPD_Pos (7U)
12437#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
12438#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk
12439#define ETH_MACFCR_PLT_Pos (4U)
12440#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
12441#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk
12442#define ETH_MACFCR_PLT_Minus4 0x00000000U
12443#define ETH_MACFCR_PLT_Minus28_Pos (4U)
12444#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
12445#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk
12446#define ETH_MACFCR_PLT_Minus144_Pos (5U)
12447#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
12448#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk
12449#define ETH_MACFCR_PLT_Minus256_Pos (4U)
12450#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
12451#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk
12452#define ETH_MACFCR_UPFD_Pos (3U)
12453#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
12454#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk
12455#define ETH_MACFCR_RFCE_Pos (2U)
12456#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
12457#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk
12458#define ETH_MACFCR_TFCE_Pos (1U)
12459#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
12460#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk
12461#define ETH_MACFCR_FCBBPA_Pos (0U)
12462#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
12463#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk
12466#define ETH_MACVLANTR_VLANTC_Pos (16U)
12467#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
12468#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk
12469#define ETH_MACVLANTR_VLANTI_Pos (0U)
12470#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
12471#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk
12474#define ETH_MACRWUFFR_D_Pos (0U)
12475#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
12476#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk
12490#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
12491#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
12492#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk
12493#define ETH_MACPMTCSR_GU_Pos (9U)
12494#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
12495#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk
12496#define ETH_MACPMTCSR_WFR_Pos (6U)
12497#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
12498#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk
12499#define ETH_MACPMTCSR_MPR_Pos (5U)
12500#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
12501#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk
12502#define ETH_MACPMTCSR_WFE_Pos (2U)
12503#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
12504#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk
12505#define ETH_MACPMTCSR_MPE_Pos (1U)
12506#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
12507#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk
12508#define ETH_MACPMTCSR_PD_Pos (0U)
12509#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
12510#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk
12513#define ETH_MACDBGR_TFF_Pos (25U)
12514#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
12515#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk
12516#define ETH_MACDBGR_TFNE_Pos (24U)
12517#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
12518#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk
12519#define ETH_MACDBGR_TFWA_Pos (22U)
12520#define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)
12521#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk
12522#define ETH_MACDBGR_TFRS_Pos (20U)
12523#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
12524#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk
12525#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
12526#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
12527#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk
12528#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
12529#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
12530#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk
12531#define ETH_MACDBGR_TFRS_READ_Pos (20U)
12532#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
12533#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk
12534#define ETH_MACDBGR_TFRS_IDLE 0x00000000U
12535#define ETH_MACDBGR_MTP_Pos (19U)
12536#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
12537#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk
12538#define ETH_MACDBGR_MTFCS_Pos (17U)
12539#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
12540#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk
12541#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
12542#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
12543#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk
12544#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
12545#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
12546#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk
12547#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
12548#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
12549#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk
12550#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U
12551#define ETH_MACDBGR_MMTEA_Pos (16U)
12552#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
12553#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk
12554#define ETH_MACDBGR_RFFL_Pos (8U)
12555#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
12556#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk
12557#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
12558#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
12559#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk
12560#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
12561#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
12562#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk
12563#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
12564#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
12565#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk
12566#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U
12567#define ETH_MACDBGR_RFRCS_Pos (5U)
12568#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
12569#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk
12570#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
12571#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
12572#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk
12573#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
12574#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
12575#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk
12576#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
12577#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
12578#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk
12579#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U
12580#define ETH_MACDBGR_RFWRA_Pos (4U)
12581#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
12582#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk
12583#define ETH_MACDBGR_MSFRWCS_Pos (1U)
12584#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
12585#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk
12586#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
12587#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
12588#define ETH_MACDBGR_MMRPEA_Pos (0U)
12589#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
12590#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk
12593#define ETH_MACSR_TSTS_Pos (9U)
12594#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
12595#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk
12596#define ETH_MACSR_MMCTS_Pos (6U)
12597#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
12598#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk
12599#define ETH_MACSR_MMMCRS_Pos (5U)
12600#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
12601#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk
12602#define ETH_MACSR_MMCS_Pos (4U)
12603#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
12604#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk
12605#define ETH_MACSR_PMTS_Pos (3U)
12606#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
12607#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk
12610#define ETH_MACIMR_TSTIM_Pos (9U)
12611#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
12612#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk
12613#define ETH_MACIMR_PMTIM_Pos (3U)
12614#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
12615#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk
12618#define ETH_MACA0HR_MACA0H_Pos (0U)
12619#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
12620#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk
12623#define ETH_MACA0LR_MACA0L_Pos (0U)
12624#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
12625#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk
12628#define ETH_MACA1HR_AE_Pos (31U)
12629#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
12630#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk
12631#define ETH_MACA1HR_SA_Pos (30U)
12632#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
12633#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk
12634#define ETH_MACA1HR_MBC_Pos (24U)
12635#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
12636#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk
12637#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U
12638#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U
12639#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U
12640#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U
12641#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U
12642#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U
12643#define ETH_MACA1HR_MACA1H_Pos (0U)
12644#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
12645#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk
12648#define ETH_MACA1LR_MACA1L_Pos (0U)
12649#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
12650#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk
12653#define ETH_MACA2HR_AE_Pos (31U)
12654#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
12655#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk
12656#define ETH_MACA2HR_SA_Pos (30U)
12657#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
12658#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk
12659#define ETH_MACA2HR_MBC_Pos (24U)
12660#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
12661#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk
12662#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U
12663#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U
12664#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U
12665#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U
12666#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U
12667#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U
12668#define ETH_MACA2HR_MACA2H_Pos (0U)
12669#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
12670#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk
12673#define ETH_MACA2LR_MACA2L_Pos (0U)
12674#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
12675#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk
12678#define ETH_MACA3HR_AE_Pos (31U)
12679#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
12680#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk
12681#define ETH_MACA3HR_SA_Pos (30U)
12682#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
12683#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk
12684#define ETH_MACA3HR_MBC_Pos (24U)
12685#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
12686#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk
12687#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U
12688#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U
12689#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U
12690#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U
12691#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U
12692#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U
12693#define ETH_MACA3HR_MACA3H_Pos (0U)
12694#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
12695#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk
12698#define ETH_MACA3LR_MACA3L_Pos (0U)
12699#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
12700#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk
12707#define ETH_MMCCR_MCFHP_Pos (5U)
12708#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
12709#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk
12710#define ETH_MMCCR_MCP_Pos (4U)
12711#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
12712#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk
12713#define ETH_MMCCR_MCF_Pos (3U)
12714#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
12715#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk
12716#define ETH_MMCCR_ROR_Pos (2U)
12717#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
12718#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk
12719#define ETH_MMCCR_CSR_Pos (1U)
12720#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
12721#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk
12722#define ETH_MMCCR_CR_Pos (0U)
12723#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
12724#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk
12727#define ETH_MMCRIR_RGUFS_Pos (17U)
12728#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
12729#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk
12730#define ETH_MMCRIR_RFAES_Pos (6U)
12731#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
12732#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk
12733#define ETH_MMCRIR_RFCES_Pos (5U)
12734#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
12735#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk
12738#define ETH_MMCTIR_TGFS_Pos (21U)
12739#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
12740#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk
12741#define ETH_MMCTIR_TGFMSCS_Pos (15U)
12742#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
12743#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk
12744#define ETH_MMCTIR_TGFSCS_Pos (14U)
12745#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
12746#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk
12749#define ETH_MMCRIMR_RGUFM_Pos (17U)
12750#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
12751#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk
12752#define ETH_MMCRIMR_RFAEM_Pos (6U)
12753#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
12754#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk
12755#define ETH_MMCRIMR_RFCEM_Pos (5U)
12756#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
12757#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk
12760#define ETH_MMCTIMR_TGFM_Pos (21U)
12761#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
12762#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk
12763#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
12764#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
12765#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk
12766#define ETH_MMCTIMR_TGFSCM_Pos (14U)
12767#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
12768#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk
12771#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
12772#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
12773#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk
12776#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
12777#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
12778#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk
12781#define ETH_MMCTGFCR_TGFC_Pos (0U)
12782#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
12783#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk
12786#define ETH_MMCRFCECR_RFCEC_Pos (0U)
12787#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
12788#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk
12791#define ETH_MMCRFAECR_RFAEC_Pos (0U)
12792#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
12793#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk
12796#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
12797#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
12798#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk
12805#define ETH_PTPTSCR_TSCNT_Pos (16U)
12806#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
12807#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk
12808#define ETH_PTPTSSR_TSSMRME_Pos (15U)
12809#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos)
12810#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk
12811#define ETH_PTPTSSR_TSSEME_Pos (14U)
12812#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos)
12813#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk
12814#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
12815#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos)
12816#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk
12817#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
12818#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos)
12819#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk
12820#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
12821#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos)
12822#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk
12823#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
12824#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos)
12825#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk
12826#define ETH_PTPTSSR_TSSSR_Pos (9U)
12827#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos)
12828#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk
12829#define ETH_PTPTSSR_TSSARFE_Pos (8U)
12830#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos)
12831#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk
12833#define ETH_PTPTSCR_TSARU_Pos (5U)
12834#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
12835#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk
12836#define ETH_PTPTSCR_TSITE_Pos (4U)
12837#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
12838#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk
12839#define ETH_PTPTSCR_TSSTU_Pos (3U)
12840#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
12841#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk
12842#define ETH_PTPTSCR_TSSTI_Pos (2U)
12843#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
12844#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk
12845#define ETH_PTPTSCR_TSFCU_Pos (1U)
12846#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
12847#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk
12848#define ETH_PTPTSCR_TSE_Pos (0U)
12849#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
12850#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk
12853#define ETH_PTPSSIR_STSSI_Pos (0U)
12854#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
12855#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk
12858#define ETH_PTPTSHR_STS_Pos (0U)
12859#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
12860#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk
12863#define ETH_PTPTSLR_STPNS_Pos (31U)
12864#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
12865#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk
12866#define ETH_PTPTSLR_STSS_Pos (0U)
12867#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
12868#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk
12871#define ETH_PTPTSHUR_TSUS_Pos (0U)
12872#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
12873#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk
12876#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
12877#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
12878#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk
12879#define ETH_PTPTSLUR_TSUSS_Pos (0U)
12880#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
12881#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk
12884#define ETH_PTPTSAR_TSA_Pos (0U)
12885#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
12886#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk
12889#define ETH_PTPTTHR_TTSH_Pos (0U)
12890#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
12891#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk
12894#define ETH_PTPTTLR_TTSL_Pos (0U)
12895#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
12896#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk
12899#define ETH_PTPTSSR_TSTTR_Pos (5U)
12900#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
12901#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk
12902#define ETH_PTPTSSR_TSSO_Pos (4U)
12903#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
12904#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk
12911#define ETH_DMABMR_AAB_Pos (25U)
12912#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
12913#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk
12914#define ETH_DMABMR_FPM_Pos (24U)
12915#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
12916#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk
12917#define ETH_DMABMR_USP_Pos (23U)
12918#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
12919#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk
12920#define ETH_DMABMR_RDP_Pos (17U)
12921#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
12922#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk
12923#define ETH_DMABMR_RDP_1Beat 0x00020000U
12924#define ETH_DMABMR_RDP_2Beat 0x00040000U
12925#define ETH_DMABMR_RDP_4Beat 0x00080000U
12926#define ETH_DMABMR_RDP_8Beat 0x00100000U
12927#define ETH_DMABMR_RDP_16Beat 0x00200000U
12928#define ETH_DMABMR_RDP_32Beat 0x00400000U
12929#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U
12930#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U
12931#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U
12932#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U
12933#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U
12934#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U
12935#define ETH_DMABMR_FB_Pos (16U)
12936#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
12937#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk
12938#define ETH_DMABMR_RTPR_Pos (14U)
12939#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
12940#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk
12941#define ETH_DMABMR_RTPR_1_1 0x00000000U
12942#define ETH_DMABMR_RTPR_2_1 0x00004000U
12943#define ETH_DMABMR_RTPR_3_1 0x00008000U
12944#define ETH_DMABMR_RTPR_4_1 0x0000C000U
12945#define ETH_DMABMR_PBL_Pos (8U)
12946#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
12947#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk
12948#define ETH_DMABMR_PBL_1Beat 0x00000100U
12949#define ETH_DMABMR_PBL_2Beat 0x00000200U
12950#define ETH_DMABMR_PBL_4Beat 0x00000400U
12951#define ETH_DMABMR_PBL_8Beat 0x00000800U
12952#define ETH_DMABMR_PBL_16Beat 0x00001000U
12953#define ETH_DMABMR_PBL_32Beat 0x00002000U
12954#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U
12955#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U
12956#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U
12957#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U
12958#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U
12959#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U
12960#define ETH_DMABMR_EDE_Pos (7U)
12961#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
12962#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk
12963#define ETH_DMABMR_DSL_Pos (2U)
12964#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
12965#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk
12966#define ETH_DMABMR_DA_Pos (1U)
12967#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
12968#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk
12969#define ETH_DMABMR_SR_Pos (0U)
12970#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
12971#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk
12974#define ETH_DMATPDR_TPD_Pos (0U)
12975#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
12976#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk
12979#define ETH_DMARPDR_RPD_Pos (0U)
12980#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
12981#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk
12984#define ETH_DMARDLAR_SRL_Pos (0U)
12985#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
12986#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk
12989#define ETH_DMATDLAR_STL_Pos (0U)
12990#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
12991#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk
12994#define ETH_DMASR_TSTS_Pos (29U)
12995#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
12996#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk
12997#define ETH_DMASR_PMTS_Pos (28U)
12998#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
12999#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk
13000#define ETH_DMASR_MMCS_Pos (27U)
13001#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
13002#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk
13003#define ETH_DMASR_EBS_Pos (23U)
13004#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
13005#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk
13007#define ETH_DMASR_EBS_DescAccess_Pos (25U)
13008#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
13009#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk
13010#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
13011#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
13012#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk
13013#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
13014#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
13015#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk
13016#define ETH_DMASR_TPS_Pos (20U)
13017#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
13018#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk
13019#define ETH_DMASR_TPS_Stopped 0x00000000U
13020#define ETH_DMASR_TPS_Fetching_Pos (20U)
13021#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
13022#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk
13023#define ETH_DMASR_TPS_Waiting_Pos (21U)
13024#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
13025#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk
13026#define ETH_DMASR_TPS_Reading_Pos (20U)
13027#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
13028#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk
13029#define ETH_DMASR_TPS_Suspended_Pos (21U)
13030#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
13031#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk
13032#define ETH_DMASR_TPS_Closing_Pos (20U)
13033#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
13034#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk
13035#define ETH_DMASR_RPS_Pos (17U)
13036#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
13037#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk
13038#define ETH_DMASR_RPS_Stopped 0x00000000U
13039#define ETH_DMASR_RPS_Fetching_Pos (17U)
13040#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
13041#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk
13042#define ETH_DMASR_RPS_Waiting_Pos (17U)
13043#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
13044#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk
13045#define ETH_DMASR_RPS_Suspended_Pos (19U)
13046#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
13047#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk
13048#define ETH_DMASR_RPS_Closing_Pos (17U)
13049#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
13050#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk
13051#define ETH_DMASR_RPS_Queuing_Pos (17U)
13052#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
13053#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk
13054#define ETH_DMASR_NIS_Pos (16U)
13055#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
13056#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk
13057#define ETH_DMASR_AIS_Pos (15U)
13058#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
13059#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk
13060#define ETH_DMASR_ERS_Pos (14U)
13061#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
13062#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk
13063#define ETH_DMASR_FBES_Pos (13U)
13064#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
13065#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk
13066#define ETH_DMASR_ETS_Pos (10U)
13067#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
13068#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk
13069#define ETH_DMASR_RWTS_Pos (9U)
13070#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
13071#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk
13072#define ETH_DMASR_RPSS_Pos (8U)
13073#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
13074#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk
13075#define ETH_DMASR_RBUS_Pos (7U)
13076#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
13077#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk
13078#define ETH_DMASR_RS_Pos (6U)
13079#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
13080#define ETH_DMASR_RS ETH_DMASR_RS_Msk
13081#define ETH_DMASR_TUS_Pos (5U)
13082#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
13083#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk
13084#define ETH_DMASR_ROS_Pos (4U)
13085#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
13086#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk
13087#define ETH_DMASR_TJTS_Pos (3U)
13088#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
13089#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk
13090#define ETH_DMASR_TBUS_Pos (2U)
13091#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
13092#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk
13093#define ETH_DMASR_TPSS_Pos (1U)
13094#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
13095#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk
13096#define ETH_DMASR_TS_Pos (0U)
13097#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
13098#define ETH_DMASR_TS ETH_DMASR_TS_Msk
13101#define ETH_DMAOMR_DTCEFD_Pos (26U)
13102#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
13103#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk
13104#define ETH_DMAOMR_RSF_Pos (25U)
13105#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
13106#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk
13107#define ETH_DMAOMR_DFRF_Pos (24U)
13108#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
13109#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk
13110#define ETH_DMAOMR_TSF_Pos (21U)
13111#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
13112#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk
13113#define ETH_DMAOMR_FTF_Pos (20U)
13114#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
13115#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk
13116#define ETH_DMAOMR_TTC_Pos (14U)
13117#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
13118#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk
13119#define ETH_DMAOMR_TTC_64Bytes 0x00000000U
13120#define ETH_DMAOMR_TTC_128Bytes 0x00004000U
13121#define ETH_DMAOMR_TTC_192Bytes 0x00008000U
13122#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U
13123#define ETH_DMAOMR_TTC_40Bytes 0x00010000U
13124#define ETH_DMAOMR_TTC_32Bytes 0x00014000U
13125#define ETH_DMAOMR_TTC_24Bytes 0x00018000U
13126#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U
13127#define ETH_DMAOMR_ST_Pos (13U)
13128#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
13129#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk
13130#define ETH_DMAOMR_FEF_Pos (7U)
13131#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
13132#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk
13133#define ETH_DMAOMR_FUGF_Pos (6U)
13134#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
13135#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk
13136#define ETH_DMAOMR_RTC_Pos (3U)
13137#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
13138#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk
13139#define ETH_DMAOMR_RTC_64Bytes 0x00000000U
13140#define ETH_DMAOMR_RTC_32Bytes 0x00000008U
13141#define ETH_DMAOMR_RTC_96Bytes 0x00000010U
13142#define ETH_DMAOMR_RTC_128Bytes 0x00000018U
13143#define ETH_DMAOMR_OSF_Pos (2U)
13144#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
13145#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk
13146#define ETH_DMAOMR_SR_Pos (1U)
13147#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
13148#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk
13151#define ETH_DMAIER_NISE_Pos (16U)
13152#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
13153#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk
13154#define ETH_DMAIER_AISE_Pos (15U)
13155#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
13156#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk
13157#define ETH_DMAIER_ERIE_Pos (14U)
13158#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
13159#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk
13160#define ETH_DMAIER_FBEIE_Pos (13U)
13161#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
13162#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk
13163#define ETH_DMAIER_ETIE_Pos (10U)
13164#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
13165#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk
13166#define ETH_DMAIER_RWTIE_Pos (9U)
13167#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
13168#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk
13169#define ETH_DMAIER_RPSIE_Pos (8U)
13170#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
13171#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk
13172#define ETH_DMAIER_RBUIE_Pos (7U)
13173#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
13174#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk
13175#define ETH_DMAIER_RIE_Pos (6U)
13176#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
13177#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk
13178#define ETH_DMAIER_TUIE_Pos (5U)
13179#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
13180#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk
13181#define ETH_DMAIER_ROIE_Pos (4U)
13182#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
13183#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk
13184#define ETH_DMAIER_TJTIE_Pos (3U)
13185#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
13186#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk
13187#define ETH_DMAIER_TBUIE_Pos (2U)
13188#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
13189#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk
13190#define ETH_DMAIER_TPSIE_Pos (1U)
13191#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
13192#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk
13193#define ETH_DMAIER_TIE_Pos (0U)
13194#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
13195#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk
13198#define ETH_DMAMFBOCR_OFOC_Pos (28U)
13199#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
13200#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk
13201#define ETH_DMAMFBOCR_MFA_Pos (17U)
13202#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
13203#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk
13204#define ETH_DMAMFBOCR_OMFC_Pos (16U)
13205#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
13206#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk
13207#define ETH_DMAMFBOCR_MFC_Pos (0U)
13208#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
13209#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk
13212#define ETH_DMACHTDR_HTDAP_Pos (0U)
13213#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
13214#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk
13217#define ETH_DMACHRDR_HRDAP_Pos (0U)
13218#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
13219#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk
13222#define ETH_DMACHTBAR_HTBAP_Pos (0U)
13223#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
13224#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk
13227#define ETH_DMACHRBAR_HRBAP_Pos (0U)
13228#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
13229#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk
13237#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
13238#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
13239#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
13240#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
13241#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
13242#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
13243#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
13244#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
13245#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
13246#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
13247#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
13248#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
13249#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
13250#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
13251#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
13252#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
13253#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
13254#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
13255#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
13256#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
13257#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
13258#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
13259#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
13260#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
13261#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
13262#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
13263#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
13264#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
13265#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
13266#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk
13270#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
13271#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
13272#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
13273#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
13274#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
13275#define USB_OTG_HCFG_FSLSS_Pos (2U)
13276#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
13277#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
13281#define USB_OTG_DCFG_DSPD_Pos (0U)
13282#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
13283#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
13284#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
13285#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
13286#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
13287#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
13288#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
13290#define USB_OTG_DCFG_DAD_Pos (4U)
13291#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
13292#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
13293#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
13294#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
13295#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
13296#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
13297#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
13298#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
13299#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
13301#define USB_OTG_DCFG_PFIVL_Pos (11U)
13302#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
13303#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
13304#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
13305#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
13307#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
13308#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
13309#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
13311#define USB_OTG_DCFG_ERRATIM_Pos (15U)
13312#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
13313#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
13315#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
13316#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13317#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
13318#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13319#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13322#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
13323#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
13324#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
13325#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
13326#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
13327#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
13328#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
13329#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
13330#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
13333#define USB_OTG_GOTGINT_SEDET_Pos (2U)
13334#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
13335#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
13336#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
13337#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
13338#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
13339#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
13340#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
13341#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
13342#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
13343#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
13344#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
13345#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
13346#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
13347#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
13348#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
13349#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
13350#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
13353#define USB_OTG_DCTL_RWUSIG_Pos (0U)
13354#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
13355#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
13356#define USB_OTG_DCTL_SDIS_Pos (1U)
13357#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
13358#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
13359#define USB_OTG_DCTL_GINSTS_Pos (2U)
13360#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
13361#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
13362#define USB_OTG_DCTL_GONSTS_Pos (3U)
13363#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
13364#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
13366#define USB_OTG_DCTL_TCTL_Pos (4U)
13367#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
13368#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
13369#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
13370#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
13371#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
13372#define USB_OTG_DCTL_SGINAK_Pos (7U)
13373#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
13374#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
13375#define USB_OTG_DCTL_CGINAK_Pos (8U)
13376#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
13377#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
13378#define USB_OTG_DCTL_SGONAK_Pos (9U)
13379#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
13380#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
13381#define USB_OTG_DCTL_CGONAK_Pos (10U)
13382#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
13383#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
13384#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
13385#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
13386#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
13389#define USB_OTG_HFIR_FRIVL_Pos (0U)
13390#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
13391#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
13394#define USB_OTG_HFNUM_FRNUM_Pos (0U)
13395#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
13396#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
13397#define USB_OTG_HFNUM_FTREM_Pos (16U)
13398#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
13399#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
13402#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
13403#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
13404#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
13406#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
13407#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
13408#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
13409#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
13410#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
13411#define USB_OTG_DSTS_EERR_Pos (3U)
13412#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
13413#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
13414#define USB_OTG_DSTS_FNSOF_Pos (8U)
13415#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
13416#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
13419#define USB_OTG_GAHBCFG_GINT_Pos (0U)
13420#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
13421#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
13422#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
13423#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13424#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
13425#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13426#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13427#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13428#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13429#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13430#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
13431#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
13432#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
13433#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
13434#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
13435#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
13436#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
13437#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
13438#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
13442#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
13443#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13444#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
13445#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13446#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13447#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13448#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
13449#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
13450#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
13451#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
13452#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
13453#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
13454#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
13455#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
13456#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
13457#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
13458#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
13459#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
13460#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
13461#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
13462#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
13463#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
13464#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
13465#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
13466#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
13467#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
13468#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
13469#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
13470#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
13471#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
13472#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
13473#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
13474#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
13475#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
13476#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
13477#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
13478#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
13479#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
13480#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
13481#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
13482#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
13483#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
13484#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
13485#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
13486#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
13487#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
13488#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
13489#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
13490#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
13491#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
13492#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
13493#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
13494#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
13495#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
13496#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
13497#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
13498#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
13499#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
13500#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
13501#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
13502#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
13505#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
13506#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
13507#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
13508#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
13509#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
13510#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
13511#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
13512#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
13513#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
13514#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
13515#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
13516#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
13517#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
13518#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
13519#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
13522#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
13523#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13524#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
13525#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13526#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13527#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13528#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13529#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13530#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
13531#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
13532#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
13533#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
13534#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
13535#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
13538#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
13539#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
13540#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
13541#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
13542#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
13543#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
13544#define USB_OTG_DIEPMSK_TOM_Pos (3U)
13545#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
13546#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
13547#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
13548#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
13549#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
13550#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
13551#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
13552#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
13553#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
13554#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
13555#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
13556#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
13557#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
13558#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
13559#define USB_OTG_DIEPMSK_BIM_Pos (9U)
13560#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
13561#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
13564#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
13565#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
13566#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
13567#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
13568#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13569#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
13570#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13571#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13572#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13573#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13574#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13575#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13576#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13577#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13579#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
13580#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13581#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
13582#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13583#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13584#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13585#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13586#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13587#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13588#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13589#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13592#define USB_OTG_HAINT_HAINT_Pos (0U)
13593#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
13594#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
13597#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
13598#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
13599#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
13600#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
13601#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
13602#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
13603#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
13604#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
13605#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
13606#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
13607#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
13608#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
13609#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
13610#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
13611#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
13612#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
13613#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
13614#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
13615#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
13616#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
13617#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
13618#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
13619#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
13620#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
13621#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
13622#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
13623#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
13624#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
13625#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
13626#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
13627#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
13628#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
13629#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
13630#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
13631#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
13632#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
13634#define USB_OTG_GINTSTS_CMOD_Pos (0U)
13635#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
13636#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
13637#define USB_OTG_GINTSTS_MMIS_Pos (1U)
13638#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
13639#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
13640#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
13641#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
13642#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
13643#define USB_OTG_GINTSTS_SOF_Pos (3U)
13644#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
13645#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
13646#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
13647#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
13648#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
13649#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
13650#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
13651#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
13652#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
13653#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
13654#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
13655#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
13656#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
13657#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
13658#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
13659#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
13660#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
13661#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
13662#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
13663#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
13664#define USB_OTG_GINTSTS_USBRST_Pos (12U)
13665#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
13666#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
13667#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
13668#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
13669#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
13670#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
13671#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
13672#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
13673#define USB_OTG_GINTSTS_EOPF_Pos (15U)
13674#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
13675#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
13676#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
13677#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
13678#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
13679#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
13680#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
13681#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
13682#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
13683#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
13684#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
13685#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
13686#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
13687#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
13688#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
13689#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
13690#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
13691#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
13692#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
13693#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
13694#define USB_OTG_GINTSTS_HCINT_Pos (25U)
13695#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
13696#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
13697#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
13698#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
13699#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
13700#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
13701#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
13702#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
13703#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
13704#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
13705#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
13706#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
13707#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
13708#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
13709#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
13710#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
13711#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
13714#define USB_OTG_GINTMSK_MMISM_Pos (1U)
13715#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
13716#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
13717#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
13718#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
13719#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
13720#define USB_OTG_GINTMSK_SOFM_Pos (3U)
13721#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
13722#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
13723#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
13724#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
13725#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
13726#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
13727#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
13728#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
13729#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
13730#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
13731#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
13732#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
13733#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
13734#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
13735#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
13736#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
13737#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
13738#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
13739#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
13740#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
13741#define USB_OTG_GINTMSK_USBRST_Pos (12U)
13742#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
13743#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
13744#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
13745#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
13746#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
13747#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
13748#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
13749#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
13750#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
13751#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
13752#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
13753#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
13754#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
13755#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
13756#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
13757#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
13758#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
13759#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
13760#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
13761#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
13762#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
13763#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
13764#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
13765#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
13766#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
13767#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
13768#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
13769#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
13770#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
13771#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
13772#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
13773#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
13774#define USB_OTG_GINTMSK_HCIM_Pos (25U)
13775#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
13776#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
13777#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
13778#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
13779#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
13780#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
13781#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
13782#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
13783#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
13784#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
13785#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
13786#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
13787#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
13788#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
13789#define USB_OTG_GINTMSK_WUIM_Pos (31U)
13790#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
13791#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
13794#define USB_OTG_DAINT_IEPINT_Pos (0U)
13795#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
13796#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
13797#define USB_OTG_DAINT_OEPINT_Pos (16U)
13798#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
13799#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
13802#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
13803#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
13804#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
13807#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
13808#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
13809#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
13810#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
13811#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
13812#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
13813#define USB_OTG_GRXSTSP_DPID_Pos (15U)
13814#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
13815#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
13816#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
13817#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
13818#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
13821#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
13822#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
13823#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
13824#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
13825#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
13826#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
13829#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
13830#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
13831#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
13834#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
13835#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
13836#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
13839#define USB_OTG_NPTXFSA_Pos (0U)
13840#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
13841#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
13842#define USB_OTG_NPTXFD_Pos (16U)
13843#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
13844#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
13845#define USB_OTG_TX0FSA_Pos (0U)
13846#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
13847#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
13848#define USB_OTG_TX0FD_Pos (16U)
13849#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
13850#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
13853#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
13854#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
13855#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
13858#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
13859#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
13860#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
13862#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
13863#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13864#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
13865#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13866#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13867#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13868#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13869#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13870#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13871#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13872#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
13874#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
13875#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13876#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
13877#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13878#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13879#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13880#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13881#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13882#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13883#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
13886#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
13887#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
13888#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
13889#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
13890#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
13891#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
13893#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
13894#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13895#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
13896#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13897#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13898#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13899#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13900#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13901#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13902#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13903#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13904#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
13905#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
13906#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
13907#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
13909#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
13910#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13911#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
13912#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13913#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13914#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13915#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13916#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13917#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13918#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13919#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13920#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
13921#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
13922#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
13923#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
13926#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
13927#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
13928#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
13931#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
13932#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
13933#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
13934#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
13935#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
13936#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
13939#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
13940#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
13941#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
13942#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
13943#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
13944#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk
13945#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
13946#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
13947#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk
13948#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
13949#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
13950#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk
13951#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
13952#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
13953#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk
13954#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
13955#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
13956#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk
13959#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
13960#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
13961#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
13962#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
13963#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
13964#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
13967#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
13968#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
13969#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
13972#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
13973#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
13974#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
13975#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
13976#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
13977#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
13978#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
13979#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
13980#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
13981#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
13982#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
13983#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
13984#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
13985#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
13986#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
13987#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
13988#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
13989#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
13990#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
13991#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
13992#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
13993#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
13994#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
13995#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
13996#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
13997#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
13998#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
14001#define USB_OTG_HPRT_PCSTS_Pos (0U)
14002#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
14003#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
14004#define USB_OTG_HPRT_PCDET_Pos (1U)
14005#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
14006#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
14007#define USB_OTG_HPRT_PENA_Pos (2U)
14008#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
14009#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
14010#define USB_OTG_HPRT_PENCHNG_Pos (3U)
14011#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
14012#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
14013#define USB_OTG_HPRT_POCA_Pos (4U)
14014#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
14015#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
14016#define USB_OTG_HPRT_POCCHNG_Pos (5U)
14017#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
14018#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
14019#define USB_OTG_HPRT_PRES_Pos (6U)
14020#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
14021#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
14022#define USB_OTG_HPRT_PSUSP_Pos (7U)
14023#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
14024#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
14025#define USB_OTG_HPRT_PRST_Pos (8U)
14026#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
14027#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
14029#define USB_OTG_HPRT_PLSTS_Pos (10U)
14030#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
14031#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
14032#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
14033#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
14034#define USB_OTG_HPRT_PPWR_Pos (12U)
14035#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
14036#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
14038#define USB_OTG_HPRT_PTCTL_Pos (13U)
14039#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
14040#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
14041#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
14042#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
14043#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
14044#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
14046#define USB_OTG_HPRT_PSPD_Pos (17U)
14047#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
14048#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
14049#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
14050#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
14053#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
14054#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
14055#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
14056#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
14057#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
14058#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
14059#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
14060#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
14061#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
14062#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
14063#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
14064#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
14065#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
14066#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
14067#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
14068#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
14069#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
14070#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
14071#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
14072#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
14073#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
14074#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
14075#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
14076#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
14077#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
14078#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
14079#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
14080#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
14081#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
14082#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
14083#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
14084#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
14085#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
14088#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
14089#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
14090#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
14091#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
14092#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
14093#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
14096#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
14097#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
14098#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
14099#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
14100#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
14101#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
14102#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
14103#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
14104#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
14105#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
14106#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
14107#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
14109#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
14110#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14111#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
14112#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14113#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14114#define USB_OTG_DIEPCTL_STALL_Pos (21U)
14115#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
14116#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
14118#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
14119#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14120#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
14121#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14122#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14123#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14124#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14125#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
14126#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
14127#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
14128#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
14129#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
14130#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
14131#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
14132#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
14133#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
14134#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
14135#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
14136#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
14137#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
14138#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
14139#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
14140#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
14141#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
14142#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
14145#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
14146#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
14147#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
14149#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
14150#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
14151#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
14152#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
14153#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
14154#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
14155#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
14156#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
14157#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
14158#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
14159#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
14160#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
14161#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
14163#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
14164#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
14165#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
14166#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
14167#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
14169#define USB_OTG_HCCHAR_MC_Pos (20U)
14170#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
14171#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
14172#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
14173#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
14175#define USB_OTG_HCCHAR_DAD_Pos (22U)
14176#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
14177#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
14178#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
14179#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
14180#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
14181#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
14182#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
14183#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
14184#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
14185#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
14186#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
14187#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
14188#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
14189#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
14190#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
14191#define USB_OTG_HCCHAR_CHENA_Pos (31U)
14192#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
14193#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
14197#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
14198#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
14199#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
14200#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14201#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14202#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14203#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14204#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14205#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14206#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14208#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
14209#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
14210#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
14211#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14212#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14213#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14214#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14215#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14216#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14217#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14219#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
14220#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14221#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
14222#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14223#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14224#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
14225#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
14226#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
14227#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
14228#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
14229#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
14232#define USB_OTG_HCINT_XFRC_Pos (0U)
14233#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
14234#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
14235#define USB_OTG_HCINT_CHH_Pos (1U)
14236#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
14237#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
14238#define USB_OTG_HCINT_AHBERR_Pos (2U)
14239#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
14240#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
14241#define USB_OTG_HCINT_STALL_Pos (3U)
14242#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
14243#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
14244#define USB_OTG_HCINT_NAK_Pos (4U)
14245#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
14246#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
14247#define USB_OTG_HCINT_ACK_Pos (5U)
14248#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
14249#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
14250#define USB_OTG_HCINT_NYET_Pos (6U)
14251#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
14252#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
14253#define USB_OTG_HCINT_TXERR_Pos (7U)
14254#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
14255#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
14256#define USB_OTG_HCINT_BBERR_Pos (8U)
14257#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
14258#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
14259#define USB_OTG_HCINT_FRMOR_Pos (9U)
14260#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
14261#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
14262#define USB_OTG_HCINT_DTERR_Pos (10U)
14263#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
14264#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
14267#define USB_OTG_DIEPINT_XFRC_Pos (0U)
14268#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
14269#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
14270#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
14271#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
14272#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
14273#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
14274#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
14275#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
14276#define USB_OTG_DIEPINT_TOC_Pos (3U)
14277#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
14278#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
14279#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
14280#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
14281#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
14282#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
14283#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
14284#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
14285#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
14286#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
14287#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
14288#define USB_OTG_DIEPINT_TXFE_Pos (7U)
14289#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
14290#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
14291#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
14292#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
14293#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
14294#define USB_OTG_DIEPINT_BNA_Pos (9U)
14295#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
14296#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
14297#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
14298#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
14299#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
14300#define USB_OTG_DIEPINT_BERR_Pos (12U)
14301#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
14302#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
14303#define USB_OTG_DIEPINT_NAK_Pos (13U)
14304#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
14305#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
14308#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
14309#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
14310#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
14311#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
14312#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
14313#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
14314#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
14315#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
14316#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
14317#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
14318#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
14319#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
14320#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
14321#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
14322#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
14323#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
14324#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
14325#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
14326#define USB_OTG_HCINTMSK_NYET_Pos (6U)
14327#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
14328#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
14329#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
14330#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
14331#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
14332#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
14333#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
14334#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
14335#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
14336#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
14337#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
14338#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
14339#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
14340#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
14344#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
14345#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
14346#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
14347#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
14348#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
14349#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
14350#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
14351#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
14352#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
14354#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
14355#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
14356#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
14357#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
14358#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
14359#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
14360#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
14361#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
14362#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
14363#define USB_OTG_HCTSIZ_DPID_Pos (29U)
14364#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
14365#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
14366#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
14367#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
14370#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
14371#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
14372#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
14375#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
14376#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
14377#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
14380#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
14381#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
14382#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
14385#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
14386#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
14387#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
14388#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
14389#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
14390#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
14394#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
14395#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
14396#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
14397#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
14398#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
14399#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
14400#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
14401#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
14402#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
14403#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
14404#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
14405#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
14406#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
14407#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
14408#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
14409#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
14410#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14411#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
14412#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14413#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14414#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
14415#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
14416#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
14417#define USB_OTG_DOEPCTL_STALL_Pos (21U)
14418#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
14419#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
14420#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
14421#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
14422#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
14423#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
14424#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
14425#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
14426#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
14427#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
14428#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
14429#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
14430#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
14431#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
14434#define USB_OTG_DOEPINT_XFRC_Pos (0U)
14435#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
14436#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
14437#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
14438#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
14439#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
14440#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
14441#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
14442#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
14443#define USB_OTG_DOEPINT_STUP_Pos (3U)
14444#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
14445#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
14446#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
14447#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
14448#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
14449#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
14450#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
14451#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
14452#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
14453#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
14454#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
14455#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
14456#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
14457#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
14458#define USB_OTG_DOEPINT_NAK_Pos (13U)
14459#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
14460#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
14461#define USB_OTG_DOEPINT_NYET_Pos (14U)
14462#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
14463#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
14464#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
14465#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
14466#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
14469#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
14470#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
14471#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
14472#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
14473#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
14474#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
14476#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
14477#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14478#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
14479#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14480#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14483#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
14484#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
14485#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
14486#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
14487#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
14488#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
14489#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
14490#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
14491#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
14495#define USB_OTG_CHNUM_Pos (0U)
14496#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
14497#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
14498#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
14499#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
14500#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
14501#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
14502#define USB_OTG_BCNT_Pos (4U)
14503#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
14504#define USB_OTG_BCNT USB_OTG_BCNT_Msk
14506#define USB_OTG_DPID_Pos (15U)
14507#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
14508#define USB_OTG_DPID USB_OTG_DPID_Msk
14509#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
14510#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
14512#define USB_OTG_PKTSTS_Pos (17U)
14513#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
14514#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
14515#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
14516#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
14517#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
14518#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
14520#define USB_OTG_EPNUM_Pos (0U)
14521#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
14522#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
14523#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
14524#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
14525#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
14526#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
14528#define USB_OTG_FRMNUM_Pos (21U)
14529#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
14530#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
14531#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
14532#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
14533#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
14534#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
14548#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
14549 ((INSTANCE) == ADC2) || \
14550 ((INSTANCE) == ADC3))
14552#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14554#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
14557#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
14558 ((INSTANCE) == CAN2))
14561#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14564#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14567#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
14570#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
14571 ((INSTANCE) == DMA1_Stream1) || \
14572 ((INSTANCE) == DMA1_Stream2) || \
14573 ((INSTANCE) == DMA1_Stream3) || \
14574 ((INSTANCE) == DMA1_Stream4) || \
14575 ((INSTANCE) == DMA1_Stream5) || \
14576 ((INSTANCE) == DMA1_Stream6) || \
14577 ((INSTANCE) == DMA1_Stream7) || \
14578 ((INSTANCE) == DMA2_Stream0) || \
14579 ((INSTANCE) == DMA2_Stream1) || \
14580 ((INSTANCE) == DMA2_Stream2) || \
14581 ((INSTANCE) == DMA2_Stream3) || \
14582 ((INSTANCE) == DMA2_Stream4) || \
14583 ((INSTANCE) == DMA2_Stream5) || \
14584 ((INSTANCE) == DMA2_Stream6) || \
14585 ((INSTANCE) == DMA2_Stream7))
14588#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14589 ((INSTANCE) == GPIOB) || \
14590 ((INSTANCE) == GPIOC) || \
14591 ((INSTANCE) == GPIOD) || \
14592 ((INSTANCE) == GPIOE) || \
14593 ((INSTANCE) == GPIOF) || \
14594 ((INSTANCE) == GPIOG) || \
14595 ((INSTANCE) == GPIOH) || \
14596 ((INSTANCE) == GPIOI))
14599#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
14602#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14603 ((INSTANCE) == I2C2) || \
14604 ((INSTANCE) == I2C3))
14607#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
14610#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
14611 ((INSTANCE) == SPI3))
14614#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
14617#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
14620#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14621 ((INSTANCE) == SPI2) || \
14622 ((INSTANCE) == SPI3))
14625#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14626 ((INSTANCE) == TIM2) || \
14627 ((INSTANCE) == TIM3) || \
14628 ((INSTANCE) == TIM4) || \
14629 ((INSTANCE) == TIM5) || \
14630 ((INSTANCE) == TIM6) || \
14631 ((INSTANCE) == TIM7) || \
14632 ((INSTANCE) == TIM8) || \
14633 ((INSTANCE) == TIM9) || \
14634 ((INSTANCE) == TIM10) || \
14635 ((INSTANCE) == TIM11) || \
14636 ((INSTANCE) == TIM12) || \
14637 ((INSTANCE) == TIM13) || \
14638 ((INSTANCE) == TIM14))
14641#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14642 ((INSTANCE) == TIM2) || \
14643 ((INSTANCE) == TIM3) || \
14644 ((INSTANCE) == TIM4) || \
14645 ((INSTANCE) == TIM5) || \
14646 ((INSTANCE) == TIM8) || \
14647 ((INSTANCE) == TIM9) || \
14648 ((INSTANCE) == TIM10) || \
14649 ((INSTANCE) == TIM11) || \
14650 ((INSTANCE) == TIM12) || \
14651 ((INSTANCE) == TIM13) || \
14652 ((INSTANCE) == TIM14))
14655#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14656 ((INSTANCE) == TIM2) || \
14657 ((INSTANCE) == TIM3) || \
14658 ((INSTANCE) == TIM4) || \
14659 ((INSTANCE) == TIM5) || \
14660 ((INSTANCE) == TIM8) || \
14661 ((INSTANCE) == TIM9) || \
14662 ((INSTANCE) == TIM12))
14665#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14666 ((INSTANCE) == TIM2) || \
14667 ((INSTANCE) == TIM3) || \
14668 ((INSTANCE) == TIM4) || \
14669 ((INSTANCE) == TIM5) || \
14670 ((INSTANCE) == TIM8))
14673#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14674 ((INSTANCE) == TIM2) || \
14675 ((INSTANCE) == TIM3) || \
14676 ((INSTANCE) == TIM4) || \
14677 ((INSTANCE) == TIM5) || \
14678 ((INSTANCE) == TIM8))
14681#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14682 ((INSTANCE) == TIM8))
14685#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14686 ((INSTANCE) == TIM2) || \
14687 ((INSTANCE) == TIM3) || \
14688 ((INSTANCE) == TIM4) || \
14689 ((INSTANCE) == TIM5) || \
14690 ((INSTANCE) == TIM8))
14693#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14694 ((INSTANCE) == TIM2) || \
14695 ((INSTANCE) == TIM3) || \
14696 ((INSTANCE) == TIM4) || \
14697 ((INSTANCE) == TIM5) || \
14698 ((INSTANCE) == TIM6) || \
14699 ((INSTANCE) == TIM7) || \
14700 ((INSTANCE) == TIM8))
14703#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14704 ((INSTANCE) == TIM2) || \
14705 ((INSTANCE) == TIM3) || \
14706 ((INSTANCE) == TIM4) || \
14707 ((INSTANCE) == TIM5) || \
14708 ((INSTANCE) == TIM8))
14711#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14712 ((INSTANCE) == TIM2) || \
14713 ((INSTANCE) == TIM3) || \
14714 ((INSTANCE) == TIM4) || \
14715 ((INSTANCE) == TIM5) || \
14716 ((INSTANCE) == TIM8))
14719#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14720 ((INSTANCE) == TIM2) || \
14721 ((INSTANCE) == TIM3) || \
14722 ((INSTANCE) == TIM4) || \
14723 ((INSTANCE) == TIM5) || \
14724 ((INSTANCE) == TIM8))
14727#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14728 ((INSTANCE) == TIM2) || \
14729 ((INSTANCE) == TIM3) || \
14730 ((INSTANCE) == TIM4) || \
14731 ((INSTANCE) == TIM5) || \
14732 ((INSTANCE) == TIM6) || \
14733 ((INSTANCE) == TIM7) || \
14734 ((INSTANCE) == TIM8) || \
14735 ((INSTANCE) == TIM9) || \
14736 ((INSTANCE) == TIM12))
14739#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14740 ((INSTANCE) == TIM2) || \
14741 ((INSTANCE) == TIM3) || \
14742 ((INSTANCE) == TIM4) || \
14743 ((INSTANCE) == TIM5) || \
14744 ((INSTANCE) == TIM8) || \
14745 ((INSTANCE) == TIM9) || \
14746 ((INSTANCE) == TIM12))
14749#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
14750 ((INSTANCE) == TIM5))
14753#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14754 ((INSTANCE) == TIM2) || \
14755 ((INSTANCE) == TIM3) || \
14756 ((INSTANCE) == TIM4) || \
14757 ((INSTANCE) == TIM5) || \
14758 ((INSTANCE) == TIM8))
14761#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
14762 ((INSTANCE) == TIM5) || \
14763 ((INSTANCE) == TIM11))
14766#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
14767 ((((INSTANCE) == TIM1) && \
14768 (((CHANNEL) == TIM_CHANNEL_1) || \
14769 ((CHANNEL) == TIM_CHANNEL_2) || \
14770 ((CHANNEL) == TIM_CHANNEL_3) || \
14771 ((CHANNEL) == TIM_CHANNEL_4))) \
14773 (((INSTANCE) == TIM2) && \
14774 (((CHANNEL) == TIM_CHANNEL_1) || \
14775 ((CHANNEL) == TIM_CHANNEL_2) || \
14776 ((CHANNEL) == TIM_CHANNEL_3) || \
14777 ((CHANNEL) == TIM_CHANNEL_4))) \
14779 (((INSTANCE) == TIM3) && \
14780 (((CHANNEL) == TIM_CHANNEL_1) || \
14781 ((CHANNEL) == TIM_CHANNEL_2) || \
14782 ((CHANNEL) == TIM_CHANNEL_3) || \
14783 ((CHANNEL) == TIM_CHANNEL_4))) \
14785 (((INSTANCE) == TIM4) && \
14786 (((CHANNEL) == TIM_CHANNEL_1) || \
14787 ((CHANNEL) == TIM_CHANNEL_2) || \
14788 ((CHANNEL) == TIM_CHANNEL_3) || \
14789 ((CHANNEL) == TIM_CHANNEL_4))) \
14791 (((INSTANCE) == TIM5) && \
14792 (((CHANNEL) == TIM_CHANNEL_1) || \
14793 ((CHANNEL) == TIM_CHANNEL_2) || \
14794 ((CHANNEL) == TIM_CHANNEL_3) || \
14795 ((CHANNEL) == TIM_CHANNEL_4))) \
14797 (((INSTANCE) == TIM8) && \
14798 (((CHANNEL) == TIM_CHANNEL_1) || \
14799 ((CHANNEL) == TIM_CHANNEL_2) || \
14800 ((CHANNEL) == TIM_CHANNEL_3) || \
14801 ((CHANNEL) == TIM_CHANNEL_4))) \
14803 (((INSTANCE) == TIM9) && \
14804 (((CHANNEL) == TIM_CHANNEL_1) || \
14805 ((CHANNEL) == TIM_CHANNEL_2))) \
14807 (((INSTANCE) == TIM10) && \
14808 (((CHANNEL) == TIM_CHANNEL_1))) \
14810 (((INSTANCE) == TIM11) && \
14811 (((CHANNEL) == TIM_CHANNEL_1))) \
14813 (((INSTANCE) == TIM12) && \
14814 (((CHANNEL) == TIM_CHANNEL_1) || \
14815 ((CHANNEL) == TIM_CHANNEL_2))) \
14817 (((INSTANCE) == TIM13) && \
14818 (((CHANNEL) == TIM_CHANNEL_1))) \
14820 (((INSTANCE) == TIM14) && \
14821 (((CHANNEL) == TIM_CHANNEL_1))))
14824#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
14825 ((((INSTANCE) == TIM1) && \
14826 (((CHANNEL) == TIM_CHANNEL_1) || \
14827 ((CHANNEL) == TIM_CHANNEL_2) || \
14828 ((CHANNEL) == TIM_CHANNEL_3))) \
14830 (((INSTANCE) == TIM8) && \
14831 (((CHANNEL) == TIM_CHANNEL_1) || \
14832 ((CHANNEL) == TIM_CHANNEL_2) || \
14833 ((CHANNEL) == TIM_CHANNEL_3))))
14836#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14837 ((INSTANCE) == TIM2) || \
14838 ((INSTANCE) == TIM3) || \
14839 ((INSTANCE) == TIM4) || \
14840 ((INSTANCE) == TIM5) || \
14841 ((INSTANCE) == TIM8))
14844#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14845 ((INSTANCE) == TIM2) || \
14846 ((INSTANCE) == TIM3) || \
14847 ((INSTANCE) == TIM4) || \
14848 ((INSTANCE) == TIM5) || \
14849 ((INSTANCE) == TIM8) || \
14850 ((INSTANCE) == TIM9) || \
14851 ((INSTANCE) == TIM10)|| \
14852 ((INSTANCE) == TIM11)|| \
14853 ((INSTANCE) == TIM12)|| \
14854 ((INSTANCE) == TIM13)|| \
14855 ((INSTANCE) == TIM14))
14858#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14859 ((INSTANCE) == TIM8))
14862#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14863 ((INSTANCE) == TIM2) || \
14864 ((INSTANCE) == TIM3) || \
14865 ((INSTANCE) == TIM4) || \
14866 ((INSTANCE) == TIM5) || \
14867 ((INSTANCE) == TIM8))
14870#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14871 ((INSTANCE) == TIM2) || \
14872 ((INSTANCE) == TIM3) || \
14873 ((INSTANCE) == TIM4) || \
14874 ((INSTANCE) == TIM5) || \
14875 ((INSTANCE) == TIM8) || \
14876 ((INSTANCE) == TIM9) || \
14877 ((INSTANCE) == TIM12))
14880#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14881 ((INSTANCE) == TIM2) || \
14882 ((INSTANCE) == TIM3) || \
14883 ((INSTANCE) == TIM4) || \
14884 ((INSTANCE) == TIM5) || \
14885 ((INSTANCE) == TIM8))
14888#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14889 ((INSTANCE) == TIM2) || \
14890 ((INSTANCE) == TIM3) || \
14891 ((INSTANCE) == TIM4) || \
14892 ((INSTANCE) == TIM5) || \
14893 ((INSTANCE) == TIM8) || \
14894 ((INSTANCE) == TIM9) || \
14895 ((INSTANCE) == TIM12))
14898#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14899 ((INSTANCE) == TIM2) || \
14900 ((INSTANCE) == TIM3) || \
14901 ((INSTANCE) == TIM4) || \
14902 ((INSTANCE) == TIM5) || \
14903 ((INSTANCE) == TIM8) || \
14904 ((INSTANCE) == TIM9) || \
14905 ((INSTANCE) == TIM12))
14909#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14910 ((INSTANCE) == TIM8))
14913#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14914 ((INSTANCE) == TIM2) || \
14915 ((INSTANCE) == TIM3) || \
14916 ((INSTANCE) == TIM4) || \
14917 ((INSTANCE) == TIM5) || \
14918 ((INSTANCE) == TIM8))
14921#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14922 ((INSTANCE) == TIM8))
14925#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14926 ((INSTANCE) == TIM8))
14929#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14930 ((INSTANCE) == USART2) || \
14931 ((INSTANCE) == USART3) || \
14932 ((INSTANCE) == USART6))
14935#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14936 ((INSTANCE) == USART2) || \
14937 ((INSTANCE) == USART3) || \
14938 ((INSTANCE) == UART4) || \
14939 ((INSTANCE) == UART5) || \
14940 ((INSTANCE) == USART6))
14943#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14944 ((INSTANCE) == USART2) || \
14945 ((INSTANCE) == USART3) || \
14946 ((INSTANCE) == USART6))
14949#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14950 ((INSTANCE) == USART2) || \
14951 ((INSTANCE) == USART3) || \
14952 ((INSTANCE) == USART6))
14955#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14956 ((INSTANCE) == USART2) || \
14957 ((INSTANCE) == USART3) || \
14958 ((INSTANCE) == UART4) || \
14959 ((INSTANCE) == UART5) || \
14960 ((INSTANCE) == USART6))
14963#define IS_UART_HALFDUPLEX_INSTANCE IS_UART_INSTANCE
14964#define IS_UART_LIN_INSTANCE IS_UART_INSTANCE
14967#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
14968 ((INSTANCE) == USB_OTG_HS))
14971#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
14972 ((INSTANCE) == USB_OTG_HS))
14975#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
14978#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
14981#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
14984#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
14985#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U
14986#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U
14987#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U
14989#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
14990#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U
14991#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U
14992#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U
CMSIS Cortex-M3 Core Peripheral Access Layer Header File.
#define __IO
Definition core_cm3.h:170
IRQn_Type
STM32F2XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f207xx.h:66
@ PendSV_IRQn
Definition stm32f207xx.h:75
@ ETH_WKUP_IRQn
Definition stm32f207xx.h:140
@ EXTI2_IRQn
Definition stm32f207xx.h:86
@ DMA1_Stream2_IRQn
Definition stm32f207xx.h:91
@ CAN1_SCE_IRQn
Definition stm32f207xx.h:100
@ SDIO_IRQn
Definition stm32f207xx.h:127
@ RTC_WKUP_IRQn
Definition stm32f207xx.h:81
@ OTG_HS_EP1_IN_IRQn
Definition stm32f207xx.h:153
@ DMA2_Stream0_IRQn
Definition stm32f207xx.h:134
@ DMA2_Stream6_IRQn
Definition stm32f207xx.h:147
@ I2C1_ER_IRQn
Definition stm32f207xx.h:110
@ I2C2_EV_IRQn
Definition stm32f207xx.h:111
@ MemoryManagement_IRQn
Definition stm32f207xx.h:70
@ TIM4_IRQn
Definition stm32f207xx.h:108
@ TIM2_IRQn
Definition stm32f207xx.h:106
@ DMA2_Stream7_IRQn
Definition stm32f207xx.h:148
@ TIM8_BRK_TIM12_IRQn
Definition stm32f207xx.h:121
@ USART2_IRQn
Definition stm32f207xx.h:116
@ DMA2_Stream3_IRQn
Definition stm32f207xx.h:137
@ SVCall_IRQn
Definition stm32f207xx.h:73
@ ADC_IRQn
Definition stm32f207xx.h:96
@ SPI3_IRQn
Definition stm32f207xx.h:129
@ SPI2_IRQn
Definition stm32f207xx.h:114
@ TIM7_IRQn
Definition stm32f207xx.h:133
@ CAN2_SCE_IRQn
Definition stm32f207xx.h:144
@ RCC_IRQn
Definition stm32f207xx.h:83
@ TIM6_DAC_IRQn
Definition stm32f207xx.h:132
@ OTG_HS_EP1_OUT_IRQn
Definition stm32f207xx.h:152
@ I2C2_ER_IRQn
Definition stm32f207xx.h:112
@ TIM8_CC_IRQn
Definition stm32f207xx.h:124
@ UsageFault_IRQn
Definition stm32f207xx.h:72
@ SysTick_IRQn
Definition stm32f207xx.h:76
@ I2C3_ER_IRQn
Definition stm32f207xx.h:151
@ FSMC_IRQn
Definition stm32f207xx.h:126
@ I2C3_EV_IRQn
Definition stm32f207xx.h:150
@ CAN2_RX0_IRQn
Definition stm32f207xx.h:142
@ BusFault_IRQn
Definition stm32f207xx.h:71
@ DebugMonitor_IRQn
Definition stm32f207xx.h:74
@ RNG_IRQn
Definition stm32f207xx.h:157
@ FLASH_IRQn
Definition stm32f207xx.h:82
@ DMA2_Stream5_IRQn
Definition stm32f207xx.h:146
@ WWDG_IRQn
Definition stm32f207xx.h:78
@ I2C1_EV_IRQn
Definition stm32f207xx.h:109
@ TIM3_IRQn
Definition stm32f207xx.h:107
@ DMA2_Stream1_IRQn
Definition stm32f207xx.h:135
@ CAN1_TX_IRQn
Definition stm32f207xx.h:97
@ OTG_HS_WKUP_IRQn
Definition stm32f207xx.h:154
@ DMA1_Stream0_IRQn
Definition stm32f207xx.h:89
@ EXTI15_10_IRQn
Definition stm32f207xx.h:118
@ TIM1_UP_TIM10_IRQn
Definition stm32f207xx.h:103
@ EXTI9_5_IRQn
Definition stm32f207xx.h:101
@ DMA1_Stream1_IRQn
Definition stm32f207xx.h:90
@ OTG_FS_IRQn
Definition stm32f207xx.h:145
@ OTG_FS_WKUP_IRQn
Definition stm32f207xx.h:120
@ TIM8_UP_TIM13_IRQn
Definition stm32f207xx.h:122
@ USART6_IRQn
Definition stm32f207xx.h:149
@ SPI1_IRQn
Definition stm32f207xx.h:113
@ OTG_HS_IRQn
Definition stm32f207xx.h:155
@ PVD_IRQn
Definition stm32f207xx.h:79
@ HardFault_IRQn
Definition stm32f207xx.h:69
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f207xx.h:104
@ TIM1_BRK_TIM9_IRQn
Definition stm32f207xx.h:102
@ CAN2_RX1_IRQn
Definition stm32f207xx.h:143
@ EXTI0_IRQn
Definition stm32f207xx.h:84
@ CAN1_RX0_IRQn
Definition stm32f207xx.h:98
@ EXTI4_IRQn
Definition stm32f207xx.h:88
@ DMA2_Stream2_IRQn
Definition stm32f207xx.h:136
@ TAMP_STAMP_IRQn
Definition stm32f207xx.h:80
@ UART5_IRQn
Definition stm32f207xx.h:131
@ DMA1_Stream5_IRQn
Definition stm32f207xx.h:94
@ DCMI_IRQn
Definition stm32f207xx.h:156
@ ETH_IRQn
Definition stm32f207xx.h:139
@ USART1_IRQn
Definition stm32f207xx.h:115
@ EXTI3_IRQn
Definition stm32f207xx.h:87
@ NonMaskableInt_IRQn
Definition stm32f207xx.h:68
@ UART4_IRQn
Definition stm32f207xx.h:130
@ TIM8_TRG_COM_TIM14_IRQn
Definition stm32f207xx.h:123
@ EXTI1_IRQn
Definition stm32f207xx.h:85
@ DMA2_Stream4_IRQn
Definition stm32f207xx.h:138
@ TIM5_IRQn
Definition stm32f207xx.h:128
@ DMA1_Stream7_IRQn
Definition stm32f207xx.h:125
@ DMA1_Stream4_IRQn
Definition stm32f207xx.h:93
@ DMA1_Stream6_IRQn
Definition stm32f207xx.h:95
@ TIM1_CC_IRQn
Definition stm32f207xx.h:105
@ CAN2_TX_IRQn
Definition stm32f207xx.h:141
@ CAN1_RX1_IRQn
Definition stm32f207xx.h:99
@ DMA1_Stream3_IRQn
Definition stm32f207xx.h:92
@ USART3_IRQn
Definition stm32f207xx.h:117
@ RTC_Alarm_IRQn
Definition stm32f207xx.h:119
Definition stm32f107xc.h:187
__IO uint32_t CDR
Definition stm32f207xx.h:204
__IO uint32_t CSR
Definition stm32f207xx.h:202
__IO uint32_t CCR
Definition stm32f207xx.h:203
Analog to Digital Converter
Definition stm32f107xc.h:163
Controller Area Network FIFOMailBox.
Definition stm32f107xc.h:267
Controller Area Network FilterRegister.
Definition stm32f107xc.h:279
Controller Area Network TxMailBox.
Definition stm32f107xc.h:255
Controller Area Network.
Definition stm32f107xc.h:289
CRC calculation unit.
Definition stm32f107xc.h:319
Digital to Analog Converter.
Definition stm32f107xc.h:332
__IO uint32_t SR
Definition stm32f207xx.h:305
Debug MCU.
Definition stm32f107xc.h:353
__IO uint32_t APB2FZ
Definition stm32f207xx.h:317
__IO uint32_t APB1FZ
Definition stm32f207xx.h:316
DCMI.
Definition stm32f207xx.h:325
__IO uint32_t ICR
Definition stm32f207xx.h:331
__IO uint32_t CWSIZER
Definition stm32f207xx.h:335
__IO uint32_t SR
Definition stm32f207xx.h:327
__IO uint32_t DR
Definition stm32f207xx.h:336
__IO uint32_t CR
Definition stm32f207xx.h:326
__IO uint32_t CWSTRTR
Definition stm32f207xx.h:334
__IO uint32_t ESCR
Definition stm32f207xx.h:332
__IO uint32_t IER
Definition stm32f207xx.h:329
__IO uint32_t MISR
Definition stm32f207xx.h:330
__IO uint32_t RISR
Definition stm32f207xx.h:328
__IO uint32_t ESUR
Definition stm32f207xx.h:333
DMA Controller.
Definition stm32f207xx.h:344
__IO uint32_t M1AR
Definition stm32f207xx.h:349
__IO uint32_t NDTR
Definition stm32f207xx.h:346
__IO uint32_t M0AR
Definition stm32f207xx.h:348
__IO uint32_t FCR
Definition stm32f207xx.h:350
__IO uint32_t PAR
Definition stm32f207xx.h:347
__IO uint32_t CR
Definition stm32f207xx.h:345
Definition stm32f107xc.h:371
__IO uint32_t HISR
Definition stm32f207xx.h:356
__IO uint32_t LIFCR
Definition stm32f207xx.h:357
__IO uint32_t HIFCR
Definition stm32f207xx.h:358
__IO uint32_t LISR
Definition stm32f207xx.h:355
Ethernet MAC.
Definition stm32f107xc.h:383
External Interrupt/Event Controller.
Definition stm32f107xc.h:455
FLASH Registers.
Definition stm32f107xc.h:469
__IO uint32_t OPTCR
Definition stm32f207xx.h:462
Flexible Static Memory Controller Bank1E.
Definition stm32f207xx.h:480
Flexible Static Memory Controller.
Definition stm32f207xx.h:471
Flexible Static Memory Controller Bank2.
Definition stm32f207xx.h:489
__IO uint32_t SR2
Definition stm32f207xx.h:491
__IO uint32_t PCR3
Definition stm32f207xx.h:498
uint32_t RESERVED2
Definition stm32f207xx.h:497
__IO uint32_t ECCR2
Definition stm32f207xx.h:495
__IO uint32_t ECCR3
Definition stm32f207xx.h:503
__IO uint32_t SR3
Definition stm32f207xx.h:499
__IO uint32_t PATT3
Definition stm32f207xx.h:501
uint32_t RESERVED0
Definition stm32f207xx.h:494
__IO uint32_t PMEM3
Definition stm32f207xx.h:500
__IO uint32_t PATT2
Definition stm32f207xx.h:493
__IO uint32_t PMEM2
Definition stm32f207xx.h:492
__IO uint32_t PCR2
Definition stm32f207xx.h:490
uint32_t RESERVED1
Definition stm32f207xx.h:496
uint32_t RESERVED3
Definition stm32f207xx.h:502
Flexible Static Memory Controller Bank4.
Definition stm32f207xx.h:511
__IO uint32_t PCR4
Definition stm32f207xx.h:512
__IO uint32_t SR4
Definition stm32f207xx.h:513
__IO uint32_t PATT4
Definition stm32f207xx.h:515
__IO uint32_t PMEM4
Definition stm32f207xx.h:514
__IO uint32_t PIO4
Definition stm32f207xx.h:516
General Purpose I/O.
Definition stm32f107xc.h:502
__IO uint32_t OSPEEDR
Definition stm32f207xx.h:528
__IO uint32_t PUPDR
Definition stm32f207xx.h:529
__IO uint32_t OTYPER
Definition stm32f207xx.h:527
__IO uint32_t MODER
Definition stm32f207xx.h:526
Inter Integrated Circuit Interface.
Definition stm32f107xc.h:529
Independent WATCHDOG.
Definition stm32f107xc.h:546
Power Control.
Definition stm32f107xc.h:558
Reset and Clock Control.
Definition stm32f107xc.h:568
uint32_t RESERVED4
Definition stm32f207xx.h:616
__IO uint32_t AHB2LPENR
Definition stm32f207xx.h:614
__IO uint32_t PLLCFGR
Definition stm32f207xx.h:596
__IO uint32_t AHB2RSTR
Definition stm32f207xx.h:600
__IO uint32_t AHB3RSTR
Definition stm32f207xx.h:601
__IO uint32_t SSCGR
Definition stm32f207xx.h:623
__IO uint32_t APB1LPENR
Definition stm32f207xx.h:617
uint32_t RESERVED0
Definition stm32f207xx.h:602
__IO uint32_t APB2LPENR
Definition stm32f207xx.h:618
__IO uint32_t AHB1LPENR
Definition stm32f207xx.h:613
uint32_t RESERVED2
Definition stm32f207xx.h:609
__IO uint32_t AHB3LPENR
Definition stm32f207xx.h:615
__IO uint32_t PLLI2SCFGR
Definition stm32f207xx.h:624
__IO uint32_t AHB3ENR
Definition stm32f207xx.h:608
__IO uint32_t AHB1RSTR
Definition stm32f207xx.h:599
__IO uint32_t AHB2ENR
Definition stm32f207xx.h:607
__IO uint32_t AHB1ENR
Definition stm32f207xx.h:606
RNG.
Definition stm32f207xx.h:782
__IO uint32_t SR
Definition stm32f207xx.h:784
__IO uint32_t DR
Definition stm32f207xx.h:785
__IO uint32_t CR
Definition stm32f207xx.h:783
Real-Time Clock.
Definition stm32f107xc.h:590
uint32_t RESERVED7
Definition stm32f207xx.h:653
__IO uint32_t BKP8R
Definition stm32f207xx.h:662
__IO uint32_t BKP5R
Definition stm32f207xx.h:659
uint32_t RESERVED5
Definition stm32f207xx.h:651
__IO uint32_t BKP13R
Definition stm32f207xx.h:667
__IO uint32_t BKP18R
Definition stm32f207xx.h:672
__IO uint32_t BKP16R
Definition stm32f207xx.h:670
__IO uint32_t TSTR
Definition stm32f207xx.h:646
__IO uint32_t CALIBR
Definition stm32f207xx.h:640
__IO uint32_t TR
Definition stm32f207xx.h:634
__IO uint32_t TAFCR
Definition stm32f207xx.h:650
uint32_t RESERVED4
Definition stm32f207xx.h:649
__IO uint32_t BKP1R
Definition stm32f207xx.h:655
__IO uint32_t ISR
Definition stm32f207xx.h:637
__IO uint32_t PRER
Definition stm32f207xx.h:638
__IO uint32_t BKP10R
Definition stm32f207xx.h:664
__IO uint32_t BKP4R
Definition stm32f207xx.h:658
__IO uint32_t BKP12R
Definition stm32f207xx.h:666
__IO uint32_t CR
Definition stm32f207xx.h:636
uint32_t RESERVED1
Definition stm32f207xx.h:644
__IO uint32_t BKP6R
Definition stm32f207xx.h:660
__IO uint32_t BKP15R
Definition stm32f207xx.h:669
__IO uint32_t DR
Definition stm32f207xx.h:635
__IO uint32_t BKP11R
Definition stm32f207xx.h:665
__IO uint32_t BKP17R
Definition stm32f207xx.h:671
__IO uint32_t ALRMBR
Definition stm32f207xx.h:642
__IO uint32_t BKP7R
Definition stm32f207xx.h:661
__IO uint32_t BKP19R
Definition stm32f207xx.h:673
__IO uint32_t TSDR
Definition stm32f207xx.h:647
__IO uint32_t BKP2R
Definition stm32f207xx.h:656
__IO uint32_t BKP0R
Definition stm32f207xx.h:654
uint32_t RESERVED3
Definition stm32f207xx.h:648
__IO uint32_t BKP9R
Definition stm32f207xx.h:663
__IO uint32_t BKP3R
Definition stm32f207xx.h:657
__IO uint32_t WPR
Definition stm32f207xx.h:643
__IO uint32_t ALRMAR
Definition stm32f207xx.h:641
__IO uint32_t WUTR
Definition stm32f207xx.h:639
__IO uint32_t BKP14R
Definition stm32f207xx.h:668
uint32_t RESERVED6
Definition stm32f207xx.h:652
uint32_t RESERVED2
Definition stm32f207xx.h:645
SD host Interface.
Definition stm32f207xx.h:682
__IO const uint32_t RESP4
Definition stm32f207xx.h:691
__IO uint32_t ARG
Definition stm32f207xx.h:685
__IO const uint32_t FIFOCNT
Definition stm32f207xx.h:700
__IO const uint32_t STA
Definition stm32f207xx.h:696
__IO const uint32_t RESP3
Definition stm32f207xx.h:690
__IO const uint32_t RESP1
Definition stm32f207xx.h:688
__IO uint32_t DTIMER
Definition stm32f207xx.h:692
__IO uint32_t POWER
Definition stm32f207xx.h:683
__IO uint32_t DCTRL
Definition stm32f207xx.h:694
__IO const uint32_t DCOUNT
Definition stm32f207xx.h:695
__IO uint32_t MASK
Definition stm32f207xx.h:698
__IO uint32_t DLEN
Definition stm32f207xx.h:693
__IO uint32_t FIFO
Definition stm32f207xx.h:702
__IO uint32_t CMD
Definition stm32f207xx.h:686
__IO const uint32_t RESPCMD
Definition stm32f207xx.h:687
__IO uint32_t ICR
Definition stm32f207xx.h:697
__IO uint32_t CLKCR
Definition stm32f207xx.h:684
__IO const uint32_t RESP2
Definition stm32f207xx.h:689
Serial Peripheral Interface.
Definition stm32f107xc.h:608
System configuration controller.
Definition stm32f207xx.h:542
__IO uint32_t MEMRMP
Definition stm32f207xx.h:543
__IO uint32_t PMC
Definition stm32f207xx.h:544
__IO uint32_t CMPCR
Definition stm32f207xx.h:547
TIM Timers.
Definition stm32f107xc.h:624
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32f107xc.h:654
__device_Registers
Definition stm32f107xc.h:696
__USB_OTG_Core_register
Definition stm32f107xc.h:670
__Host_Channel_Specific_Registers
Definition stm32f107xc.h:770
__Host_Mode_Register_Structures
Definition stm32f107xc.h:755
__IN_Endpoint-Specific_Register
Definition stm32f107xc.h:724
__OUT_Endpoint-Specific_Registers
Definition stm32f107xc.h:740
Window WATCHDOG.
Definition stm32f107xc.h:785
CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.