stm32h7xx__hal__rcc__ex_8h_source.html

/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef STM32H7xx_HAL_RCC_EX_H

#define STM32H7xx_HAL_RCC_EX_H


#ifdef __cplusplus

 extern "C" {

#endif


/* Includes ------------------------------------------------------------------*/

#include "stm32h7xx_hal_def.h"


/* Exported types ------------------------------------------------------------*/


typedef struct

{


  uint32_t PLL2M;

  uint32_t PLL2N;

  uint32_t PLL2P;

  uint32_t PLL2Q;

  uint32_t PLL2R;

  uint32_t PLL2RGE;

  uint32_t PLL2VCOSEL;

  uint32_t PLL2FRACN;

}RCC_PLL2InitTypeDef;


typedef struct

{


  uint32_t PLL3M;

  uint32_t PLL3N;

  uint32_t PLL3P;

  uint32_t PLL3Q;

  uint32_t PLL3R;

  uint32_t PLL3RGE;

  uint32_t PLL3VCOSEL;

  uint32_t PLL3FRACN;

}RCC_PLL3InitTypeDef;


typedef struct

{

  uint32_t PLL1_P_Frequency;

  uint32_t PLL1_Q_Frequency;

  uint32_t PLL1_R_Frequency;

}PLL1_ClocksTypeDef;


typedef struct

{

  uint32_t PLL2_P_Frequency;

  uint32_t PLL2_Q_Frequency;

  uint32_t PLL2_R_Frequency;

}PLL2_ClocksTypeDef;


typedef struct

{

  uint32_t PLL3_P_Frequency;

  uint32_t PLL3_Q_Frequency;

  uint32_t PLL3_R_Frequency;

}PLL3_ClocksTypeDef;


typedef struct

{

  uint32_t PeriphClockSelection;

  RCC_PLL2InitTypeDef PLL2;

  RCC_PLL3InitTypeDef PLL3;

  uint32_t FmcClockSelection;

#if defined(QUADSPI)

  uint32_t QspiClockSelection;

#endif /* QUADSPI */


#if defined(OCTOSPI1) || defined(OCTOSPI2)

  uint32_t OspiClockSelection;

#endif /*(OCTOSPI1) || (OCTOSPI2)*/


#if defined(DSI)

  uint32_t DsiClockSelection;

#endif /* DSI */


  uint32_t SdmmcClockSelection;

  uint32_t CkperClockSelection;

  uint32_t Sai1ClockSelection;

#if defined(SAI3)

  uint32_t Sai23ClockSelection;

#endif /* SAI3 */


#if defined(RCC_CDCCIP1R_SAI2ASEL)

  uint32_t Sai2AClockSelection;

#endif /* RCC_CDCCIP1R_SAI2ASEL */


#if defined(RCC_CDCCIP1R_SAI2BSEL)

  uint32_t Sai2BClockSelection;

#endif /* RCC_CDCCIP1R_SAI2BSEL */


  uint32_t Spi123ClockSelection;

  uint32_t Spi45ClockSelection;

  uint32_t SpdifrxClockSelection;

  uint32_t Dfsdm1ClockSelection;

#if defined(DFSDM2_BASE)

  uint32_t Dfsdm2ClockSelection;

#endif /* DFSDM2_BASE */


#if defined(FDCAN1) || defined(FDCAN2)

  uint32_t FdcanClockSelection;

#endif /*FDCAN1 || FDCAN2*/


  uint32_t Swpmi1ClockSelection;

  uint32_t Usart234578ClockSelection;

  uint32_t Usart16ClockSelection;

   uint32_t RngClockSelection;

#if defined(I2C5)

   uint32_t I2c1235ClockSelection;

#else

   uint32_t I2c123ClockSelection;

#endif /*I2C5*/


  uint32_t UsbClockSelection;

  uint32_t CecClockSelection;

  uint32_t Lptim1ClockSelection;

  uint32_t Lpuart1ClockSelection;

  uint32_t I2c4ClockSelection;

  uint32_t Lptim2ClockSelection;

  uint32_t Lptim345ClockSelection;

  uint32_t AdcClockSelection;

#if defined(SAI4)

  uint32_t Sai4AClockSelection;

  uint32_t Sai4BClockSelection;

#endif /* SAI4 */


  uint32_t Spi6ClockSelection;

  uint32_t RTCClockSelection;

#if defined(HRTIM1)

  uint32_t Hrtim1ClockSelection;

#endif /* HRTIM1 */


  uint32_t TIMPresSelection;

}RCC_PeriphCLKInitTypeDef;


#if defined(I2C5)

#define I2c123ClockSelection I2c1235ClockSelection

#else

#define I2c1235ClockSelection I2c123ClockSelection

#endif /*I2C5*/


typedef struct

{

  uint32_t Prescaler;

  uint32_t Source;

  uint32_t Polarity;

  uint32_t ReloadValue;

  uint32_t ErrorLimitValue;

  uint32_t HSI48CalibrationValue;

}RCC_CRSInitTypeDef;


typedef struct

{

  uint32_t ReloadValue;

  uint32_t HSI48CalibrationValue;

  uint32_t FreqErrorCapture;

  uint32_t FreqErrorDirection;

}RCC_CRSSynchroInfoTypeDef;


/* Exported constants --------------------------------------------------------*/

#if defined(UART9) && defined(USART10)

#define RCC_PERIPHCLK_USART16910       (0x00000001U)

#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16910

#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16910

#define RCC_PERIPHCLK_UART9            RCC_PERIPHCLK_USART16910

#define RCC_PERIPHCLK_USART10          RCC_PERIPHCLK_USART16910

/*alias*/

#define RCC_PERIPHCLK_USART16          RCC_PERIPHCLK_USART16910

#else

#define RCC_PERIPHCLK_USART16          (0x00000001U)

#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16

#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16

/* alias */

#define RCC_PERIPHCLK_USART16910       RCC_PERIPHCLK_USART16

#endif /* UART9 && USART10*/

#define RCC_PERIPHCLK_USART234578      (0x00000002U)

#define RCC_PERIPHCLK_USART2           RCC_PERIPHCLK_USART234578

#define RCC_PERIPHCLK_USART3           RCC_PERIPHCLK_USART234578

#define RCC_PERIPHCLK_UART4            RCC_PERIPHCLK_USART234578

#define RCC_PERIPHCLK_UART5            RCC_PERIPHCLK_USART234578

#define RCC_PERIPHCLK_UART7            RCC_PERIPHCLK_USART234578

#define RCC_PERIPHCLK_UART8            RCC_PERIPHCLK_USART234578

#define RCC_PERIPHCLK_LPUART1          (0x00000004U)

#if defined(I2C5)

#define RCC_PERIPHCLK_I2C1235          (0x00000008U)

#define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C1235

#define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C1235

#define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C1235

/* alias */

#define RCC_PERIPHCLK_I2C123           RCC_PERIPHCLK_I2C1235

#else

#define RCC_PERIPHCLK_I2C123           (0x00000008U)

#define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C123

#define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C123

#define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C123

#endif /*I2C5*/

#define RCC_PERIPHCLK_I2C4             (0x00000010U)

#if defined(I2C5)

#define RCC_PERIPHCLK_I2C5             RCC_PERIPHCLK_I2C1235

#endif /*I2C5*/

#define RCC_PERIPHCLK_LPTIM1           (0x00000020U)

#define RCC_PERIPHCLK_LPTIM2           (0x00000040U)

#define RCC_PERIPHCLK_LPTIM345         (0x00000080U)

#define RCC_PERIPHCLK_LPTIM3           RCC_PERIPHCLK_LPTIM345

#if defined(LPTIM4)

#define RCC_PERIPHCLK_LPTIM4           RCC_PERIPHCLK_LPTIM345

#endif /*LPTIM4*/

#if defined(LPTIM5)

#define RCC_PERIPHCLK_LPTIM5           RCC_PERIPHCLK_LPTIM345

#endif /*LPTIM5*/

#define RCC_PERIPHCLK_SAI1             (0x00000100U)

#if defined(SAI3)

#define RCC_PERIPHCLK_SAI23            (0x00000200U)

#define RCC_PERIPHCLK_SAI2             RCC_PERIPHCLK_SAI23

#define RCC_PERIPHCLK_SAI3             RCC_PERIPHCLK_SAI23

#endif /* SAI3 */

#if defined(RCC_CDCCIP1R_SAI2ASEL_0)

#define RCC_PERIPHCLK_SAI2A            (0x00000200U)

#endif /* RCC_CDCCIP1R_SAI2ASEL_0 */

#if defined(RCC_CDCCIP1R_SAI2BSEL_0)

#define RCC_PERIPHCLK_SAI2B            (0x00000400U)

#endif /* RCC_CDCCIP1R_SAI2BSEL_0 */

#if defined(SAI4)

#define RCC_PERIPHCLK_SAI4A            (0x00000400U)

#define RCC_PERIPHCLK_SAI4B            (0x00000800U)

#endif /* SAI4 */

#define RCC_PERIPHCLK_SPI123           (0x00001000U)

#define RCC_PERIPHCLK_SPI1             RCC_PERIPHCLK_SPI123

#define RCC_PERIPHCLK_SPI2             RCC_PERIPHCLK_SPI123

#define RCC_PERIPHCLK_SPI3             RCC_PERIPHCLK_SPI123

#define RCC_PERIPHCLK_SPI45            (0x00002000U)

#define RCC_PERIPHCLK_SPI4             RCC_PERIPHCLK_SPI45

#define RCC_PERIPHCLK_SPI5             RCC_PERIPHCLK_SPI45

#define RCC_PERIPHCLK_SPI6             (0x00004000U)

#define RCC_PERIPHCLK_FDCAN            (0x00008000U)

#define RCC_PERIPHCLK_SDMMC            (0x00010000U)

#define RCC_PERIPHCLK_RNG              (0x00020000U)

#define RCC_PERIPHCLK_USB              (0x00040000U)

#define RCC_PERIPHCLK_ADC              (0x00080000U)

#define RCC_PERIPHCLK_SWPMI1           (0x00100000U)

#define RCC_PERIPHCLK_DFSDM1           (0x00200000U)

#if defined(DFSDM2_BASE)

#define RCC_PERIPHCLK_DFSDM2           (0x00000800U)

#endif /* DFSDM2 */

#define RCC_PERIPHCLK_RTC              (0x00400000U)

#define RCC_PERIPHCLK_CEC              (0x00800000U)

#define RCC_PERIPHCLK_FMC              (0x01000000U)

#if defined(QUADSPI)

#define RCC_PERIPHCLK_QSPI             (0x02000000U)

#endif /* QUADSPI */

#if defined(OCTOSPI1) || defined(OCTOSPI2)

#define RCC_PERIPHCLK_OSPI             (0x02000000U)

#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

#define RCC_PERIPHCLK_DSI              (0x04000000U)

#define RCC_PERIPHCLK_SPDIFRX          (0x08000000U)

#if defined(HRTIM1)

#define RCC_PERIPHCLK_HRTIM1           (0x10000000U)

#endif /* HRTIM1 */

#if defined(LTDC)

#define RCC_PERIPHCLK_LTDC             (0x20000000U)

#endif /* LTDC */

#define RCC_PERIPHCLK_TIM              (0x40000000U)

#define RCC_PERIPHCLK_CKPER            (0x80000000U)


#define RCC_PLL2_DIVP                RCC_PLLCFGR_DIVP2EN

#define RCC_PLL2_DIVQ                RCC_PLLCFGR_DIVQ2EN

#define RCC_PLL2_DIVR                RCC_PLLCFGR_DIVR2EN


#define RCC_PLL3_DIVP                RCC_PLLCFGR_DIVP3EN

#define RCC_PLL3_DIVQ                RCC_PLLCFGR_DIVQ3EN

#define RCC_PLL3_DIVR                RCC_PLLCFGR_DIVR3EN


#define RCC_PLL2VCIRANGE_0                RCC_PLLCFGR_PLL2RGE_0

#define RCC_PLL2VCIRANGE_1                RCC_PLLCFGR_PLL2RGE_1

#define RCC_PLL2VCIRANGE_2                RCC_PLLCFGR_PLL2RGE_2

#define RCC_PLL2VCIRANGE_3                RCC_PLLCFGR_PLL2RGE_3

#define RCC_PLL2VCOWIDE                 (0x00000000U)

#define RCC_PLL2VCOMEDIUM               RCC_PLLCFGR_PLL2VCOSEL


#define RCC_PLL3VCIRANGE_0                RCC_PLLCFGR_PLL3RGE_0

#define RCC_PLL3VCIRANGE_1                RCC_PLLCFGR_PLL3RGE_1

#define RCC_PLL3VCIRANGE_2                RCC_PLLCFGR_PLL3RGE_2

#define RCC_PLL3VCIRANGE_3                RCC_PLLCFGR_PLL3RGE_3

#define RCC_PLL3VCOWIDE                 (0x00000000U)

#define RCC_PLL3VCOMEDIUM               RCC_PLLCFGR_PLL3VCOSEL


#if defined(RCC_D2CCIP2R_USART16SEL)

#define RCC_USART16CLKSOURCE_D2PCLK2    (0x00000000U)

/* alias */

#define RCC_USART16CLKSOURCE_PCLK2        RCC_USART16CLKSOURCE_D2PCLK2

#define RCC_USART16CLKSOURCE_PLL2         RCC_D2CCIP2R_USART16SEL_0

#define RCC_USART16CLKSOURCE_PLL3         RCC_D2CCIP2R_USART16SEL_1

#define RCC_USART16CLKSOURCE_HSI         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)

#define RCC_USART16CLKSOURCE_CSI          RCC_D2CCIP2R_USART16SEL_2

#define RCC_USART16CLKSOURCE_LSE         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)


#elif defined(RCC_CDCCIP2R_USART16910SEL)

#define RCC_USART16910CLKSOURCE_CDPCLK2   (0x00000000U)

/* alias */

#define RCC_USART16910CLKSOURCE_D2PCLK2   RCC_USART16910CLKSOURCE_CDPCLK2

#define RCC_USART16910CLKSOURCE_PLL2      RCC_CDCCIP2R_USART16910SEL_0

#define RCC_USART16910CLKSOURCE_PLL3      RCC_CDCCIP2R_USART16910SEL_1

#define RCC_USART16910CLKSOURCE_HSI      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)

#define RCC_USART16910CLKSOURCE_CSI       RCC_CDCCIP2R_USART16910SEL_2

#define RCC_USART16910CLKSOURCE_LSE      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)


/*  Aliases */

#define RCC_USART16CLKSOURCE_CDPCLK2     RCC_USART16910CLKSOURCE_CDPCLK2

#define RCC_USART16CLKSOURCE_PCLK2       RCC_USART16CLKSOURCE_CDPCLK2

#define RCC_USART16CLKSOURCE_D2PCLK2     RCC_USART16CLKSOURCE_CDPCLK2

#define RCC_USART16CLKSOURCE_PLL2        RCC_USART16910CLKSOURCE_PLL2

#define RCC_USART16CLKSOURCE_PLL3        RCC_USART16910CLKSOURCE_PLL3

#define RCC_USART16CLKSOURCE_HSI         RCC_USART16910CLKSOURCE_HSI

#define RCC_USART16CLKSOURCE_CSI         RCC_USART16910CLKSOURCE_CSI

#define RCC_USART16CLKSOURCE_LSE         RCC_USART16910CLKSOURCE_LSE


#else  /* RCC_D2CCIP2R_USART16910SEL */

#define RCC_USART16910CLKSOURCE_D2PCLK2   (0x00000000U)

#define RCC_USART16910CLKSOURCE_PLL2      RCC_D2CCIP2R_USART16910SEL_0

#define RCC_USART16910CLKSOURCE_PLL3      RCC_D2CCIP2R_USART16910SEL_1

#define RCC_USART16910CLKSOURCE_HSI      (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)

#define RCC_USART16910CLKSOURCE_CSI       RCC_D2CCIP2R_USART16910SEL_2

#define RCC_USART16910CLKSOURCE_LSE      (RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)


/*  Aliases */

#define RCC_USART16CLKSOURCE_D2PCLK2     RCC_USART16910CLKSOURCE_D2PCLK2

#define RCC_USART16CLKSOURCE_PCLK2       RCC_USART16910CLKSOURCE_D2PCLK2

#define RCC_USART16CLKSOURCE_PLL2        RCC_USART16910CLKSOURCE_PLL2

#define RCC_USART16CLKSOURCE_PLL3        RCC_USART16910CLKSOURCE_PLL3

#define RCC_USART16CLKSOURCE_HSI         RCC_USART16910CLKSOURCE_HSI

#define RCC_USART16CLKSOURCE_CSI         RCC_USART16910CLKSOURCE_CSI

#define RCC_USART16CLKSOURCE_LSE         RCC_USART16910CLKSOURCE_LSE

#endif /* RCC_D2CCIP2R_USART16SEL */

#define RCC_USART1CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

#define RCC_USART1CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

#define RCC_USART1CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

#define RCC_USART1CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

#define RCC_USART1CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

#define RCC_USART1CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

#define RCC_USART6CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

#define RCC_USART6CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

#define RCC_USART6CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

#define RCC_USART6CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

#define RCC_USART6CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

#define RCC_USART6CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE


#if defined(UART9)

#define RCC_UART9CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

#define RCC_UART9CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

#define RCC_UART9CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

#define RCC_UART9CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

#define RCC_UART9CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

#define RCC_UART9CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

#endif /* UART9 */


#if defined(USART10)

#define RCC_USART10CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

#define RCC_USART10CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

#define RCC_USART10CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

#define RCC_USART10CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

#define RCC_USART10CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

#define RCC_USART10CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

#endif /* USART10 */


#if defined(RCC_D2CCIP2R_USART28SEL)

#define RCC_USART234578CLKSOURCE_D2PCLK1    (0x00000000U)

/* alias */

#define RCC_USART234578CLKSOURCE_PCLK1      RCC_USART234578CLKSOURCE_D2PCLK1

#define RCC_USART234578CLKSOURCE_PLL2       RCC_D2CCIP2R_USART28SEL_0

#define RCC_USART234578CLKSOURCE_PLL3       RCC_D2CCIP2R_USART28SEL_1

#define RCC_USART234578CLKSOURCE_HSI        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

#define RCC_USART234578CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2

#define RCC_USART234578CLKSOURCE_LSE        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

#else

#define RCC_USART234578CLKSOURCE_CDPCLK1   (0x00000000U)

/* alias */

#define RCC_USART234578CLKSOURCE_PCLK1     RCC_USART234578CLKSOURCE_CDPCLK1

#define RCC_USART234578CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_CDPCLK1

#define RCC_USART234578CLKSOURCE_PLL2      RCC_CDCCIP2R_USART234578SEL_0

#define RCC_USART234578CLKSOURCE_PLL3      RCC_CDCCIP2R_USART234578SEL_1

#define RCC_USART234578CLKSOURCE_HSI      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)

#define RCC_USART234578CLKSOURCE_CSI       RCC_CDCCIP2R_USART234578SEL_2

#define RCC_USART234578CLKSOURCE_LSE      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)

#endif /* RCC_D2CCIP2R_USART28SEL */

#define RCC_USART2CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

#define RCC_USART2CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

#define RCC_USART2CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

#define RCC_USART2CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

#define RCC_USART2CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

#define RCC_USART2CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE


#define RCC_USART3CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

#define RCC_USART3CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

#define RCC_USART3CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

#define RCC_USART3CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

#define RCC_USART3CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

#define RCC_USART3CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE


#define RCC_UART4CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

#define RCC_UART4CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

#define RCC_UART4CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

#define RCC_UART4CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

#define RCC_UART4CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

#define RCC_UART4CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE


#define RCC_UART5CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

#define RCC_UART5CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

#define RCC_UART5CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

#define RCC_UART5CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

#define RCC_UART5CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

#define RCC_UART5CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE


#define RCC_UART7CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

#define RCC_UART7CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

#define RCC_UART7CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

#define RCC_UART7CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

#define RCC_UART7CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

#define RCC_UART7CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE


#define RCC_UART8CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

#define RCC_UART8CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

#define RCC_UART8CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

#define RCC_UART8CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

#define RCC_UART8CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

#define RCC_UART8CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE


#if defined(RCC_D3CCIPR_LPUART1SEL)

#define RCC_LPUART1CLKSOURCE_D3PCLK1    (0x00000000U)

/* alias */

#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_D3PCLK1

#define RCC_LPUART1CLKSOURCE_PLL2      RCC_D3CCIPR_LPUART1SEL_0

#define RCC_LPUART1CLKSOURCE_PLL3      RCC_D3CCIPR_LPUART1SEL_1

#define RCC_LPUART1CLKSOURCE_HSI       (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)

#define RCC_LPUART1CLKSOURCE_CSI        RCC_D3CCIPR_LPUART1SEL_2

#define RCC_LPUART1CLKSOURCE_LSE       (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)

#else

#define RCC_LPUART1CLKSOURCE_SRDPCLK4   (0x00000000U)

/* alias*/

#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_SRDPCLK4

#define RCC_LPUART1CLKSOURCE_D3PCLK1   RCC_LPUART1CLKSOURCE_SRDPCLK4

#define RCC_LPUART1CLKSOURCE_PLL2      RCC_SRDCCIPR_LPUART1SEL_0

#define RCC_LPUART1CLKSOURCE_PLL3      RCC_SRDCCIPR_LPUART1SEL_1

#define RCC_LPUART1CLKSOURCE_HSI       (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)

#define RCC_LPUART1CLKSOURCE_CSI        RCC_SRDCCIPR_LPUART1SEL_2

#define RCC_LPUART1CLKSOURCE_LSE       (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)

#endif /* RCC_D3CCIPR_LPUART1SEL */

#if defined (RCC_D2CCIP2R_I2C123SEL)

#define RCC_I2C123CLKSOURCE_D2PCLK1      (0x00000000U)

#define RCC_I2C123CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0

#define RCC_I2C123CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1

#define RCC_I2C123CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

/* aliases */

#define RCC_I2C1235CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

#define RCC_I2C1235CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

#define RCC_I2C1235CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

#define RCC_I2C1235CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

#elif defined(RCC_CDCCIP2R_I2C123SEL)

#define RCC_I2C123CLKSOURCE_CDPCLK1      (0x00000000U)

/* alias */

#define RCC_I2C123CLKSOURCE_D2PCLK1      RCC_I2C123CLKSOURCE_CDPCLK1

#define RCC_I2C123CLKSOURCE_PLL3         RCC_CDCCIP2R_I2C123SEL_0

#define RCC_I2C123CLKSOURCE_HSI          RCC_CDCCIP2R_I2C123SEL_1

#define RCC_I2C123CLKSOURCE_CSI         (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)

/* aliases */

#define RCC_I2C1235CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

#define RCC_I2C1235CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

#define RCC_I2C1235CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

#define RCC_I2C1235CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

#elif defined(I2C5)

#define RCC_I2C1235CLKSOURCE_D2PCLK1      (0x00000000U)

#define RCC_I2C1235CLKSOURCE_PLL3        RCC_D2CCIP2R_I2C1235SEL_0

#define RCC_I2C1235CLKSOURCE_HSI         RCC_D2CCIP2R_I2C1235SEL_1

#define RCC_I2C1235CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)

/* aliases */

#define RCC_I2C123CLKSOURCE_D2PCLK1      RCC_I2C1235CLKSOURCE_D2PCLK1

#define RCC_I2C123CLKSOURCE_PLL3         RCC_I2C1235CLKSOURCE_PLL3

#define RCC_I2C123CLKSOURCE_HSI          RCC_I2C1235CLKSOURCE_HSI

#define RCC_I2C123CLKSOURCE_CSI          RCC_I2C1235CLKSOURCE_CSI

#endif /* RCC_D2CCIP2R_I2C123SEL */

#if defined(I2C5)

#define RCC_I2C1CLKSOURCE_D2PCLK1     RCC_I2C1235CLKSOURCE_D2PCLK1

#define RCC_I2C1CLKSOURCE_PLL3        RCC_I2C1235CLKSOURCE_PLL3

#define RCC_I2C1CLKSOURCE_HSI         RCC_I2C1235CLKSOURCE_HSI

#define RCC_I2C1CLKSOURCE_CSI         RCC_I2C1235CLKSOURCE_CSI

#else

#define RCC_I2C1CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

#define RCC_I2C1CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

#define RCC_I2C1CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

#define RCC_I2C1CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

#endif /*I2C5*/


#if defined(I2C5)

#define RCC_I2C2CLKSOURCE_D2PCLK1     RCC_I2C1235CLKSOURCE_D2PCLK1

#define RCC_I2C2CLKSOURCE_PLL3        RCC_I2C1235CLKSOURCE_PLL3

#define RCC_I2C2CLKSOURCE_HSI         RCC_I2C1235CLKSOURCE_HSI

#define RCC_I2C2CLKSOURCE_CSI         RCC_I2C1235CLKSOURCE_CSI

#else

#define RCC_I2C2CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

#define RCC_I2C2CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

#define RCC_I2C2CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

#define RCC_I2C2CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

#endif /*I2C5*/


#if defined(I2C5)

#define RCC_I2C3CLKSOURCE_D2PCLK1     RCC_I2C1235CLKSOURCE_D2PCLK1

#define RCC_I2C3CLKSOURCE_PLL3        RCC_I2C1235CLKSOURCE_PLL3

#define RCC_I2C3CLKSOURCE_HSI         RCC_I2C1235CLKSOURCE_HSI

#define RCC_I2C3CLKSOURCE_CSI         RCC_I2C1235CLKSOURCE_CSI

#else

#define RCC_I2C3CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

#define RCC_I2C3CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

#define RCC_I2C3CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

#define RCC_I2C3CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

#endif /*I2C5*/


#if defined(RCC_D3CCIPR_I2C4SEL)

#define RCC_I2C4CLKSOURCE_D3PCLK1      (0x00000000U)

#define RCC_I2C4CLKSOURCE_PLL3         RCC_D3CCIPR_I2C4SEL_0

#define RCC_I2C4CLKSOURCE_HSI          RCC_D3CCIPR_I2C4SEL_1

#define RCC_I2C4CLKSOURCE_CSI         (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)

#else

#define RCC_I2C4CLKSOURCE_SRDPCLK4     (0x00000000U)

/* alias */

#define RCC_I2C4CLKSOURCE_D3PCLK1     RCC_I2C4CLKSOURCE_SRDPCLK4

#define RCC_I2C4CLKSOURCE_PLL3         RCC_SRDCCIPR_I2C4SEL_0

#define RCC_I2C4CLKSOURCE_HSI          RCC_SRDCCIPR_I2C4SEL_1

#define RCC_I2C4CLKSOURCE_CSI         (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)

#endif /* RCC_D3CCIPR_I2C4SEL */


#if defined(I2C5)

#define RCC_I2C5CLKSOURCE_D2PCLK1      RCC_I2C1235CLKSOURCE_D2PCLK1

#define RCC_I2C5CLKSOURCE_PLL3         RCC_I2C1235CLKSOURCE_PLL3

#define RCC_I2C5CLKSOURCE_HSI          RCC_I2C1235CLKSOURCE_HSI

#define RCC_I2C5CLKSOURCE_CSI          RCC_I2C1235CLKSOURCE_CSI


#endif /*I2C5*/


#if defined(RCC_D2CCIP2R_RNGSEL)

#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)

#define RCC_RNGCLKSOURCE_PLL           RCC_D2CCIP2R_RNGSEL_0

#define RCC_RNGCLKSOURCE_LSE           RCC_D2CCIP2R_RNGSEL_1

#define RCC_RNGCLKSOURCE_LSI           RCC_D2CCIP2R_RNGSEL

#else

#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)

#define RCC_RNGCLKSOURCE_PLL           RCC_CDCCIP2R_RNGSEL_0

#define RCC_RNGCLKSOURCE_LSE           RCC_CDCCIP2R_RNGSEL_1

#define RCC_RNGCLKSOURCE_LSI           RCC_CDCCIP2R_RNGSEL

#endif /* RCC_D2CCIP2R_RNGSEL */


#if defined(HRTIM1)


#define RCC_HRTIM1CLK_TIMCLK                (0x00000000U)

#define RCC_HRTIM1CLK_CPUCLK                RCC_CFGR_HRTIMSEL


#endif /*HRTIM1*/


#if defined(RCC_D2CCIP2R_USBSEL)

#define RCC_USBCLKSOURCE_PLL                  RCC_D2CCIP2R_USBSEL_0

#define RCC_USBCLKSOURCE_PLL3                 RCC_D2CCIP2R_USBSEL_1

#define RCC_USBCLKSOURCE_HSI48                RCC_D2CCIP2R_USBSEL

#else

#define RCC_USBCLKSOURCE_PLL                  RCC_CDCCIP2R_USBSEL_0

#define RCC_USBCLKSOURCE_PLL3                 RCC_CDCCIP2R_USBSEL_1

#define RCC_USBCLKSOURCE_HSI48                RCC_CDCCIP2R_USBSEL

#endif /* RCC_D2CCIP2R_USBSEL */


#if defined(RCC_D2CCIP1R_SAI1SEL)

#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)

#define RCC_SAI1CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI1SEL_0

#define RCC_SAI1CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI1SEL_1

#define RCC_SAI1CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)

#define RCC_SAI1CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI1SEL_2

#else

#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)

#define RCC_SAI1CLKSOURCE_PLL2         RCC_CDCCIP1R_SAI1SEL_0

#define RCC_SAI1CLKSOURCE_PLL3         RCC_CDCCIP1R_SAI1SEL_1

#define RCC_SAI1CLKSOURCE_PIN         (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)

#define RCC_SAI1CLKSOURCE_CLKP         RCC_CDCCIP1R_SAI1SEL_2

#endif /* RCC_D2CCIP1R_SAI1SEL */

#if defined(SAI3)

#define RCC_SAI23CLKSOURCE_PLL         (0x00000000U)

#define RCC_SAI23CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI23SEL_0

#define RCC_SAI23CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI23SEL_1

#define RCC_SAI23CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)

#define RCC_SAI23CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI23SEL_2

#define RCC_SAI2CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL

#define RCC_SAI2CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2

#define RCC_SAI2CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3

#define RCC_SAI2CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN

#define RCC_SAI2CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP


#define RCC_SAI3CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL

#define RCC_SAI3CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2

#define RCC_SAI3CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3

#define RCC_SAI3CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN

#define RCC_SAI3CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP

#endif /* SAI3 */


#if defined(RCC_CDCCIP1R_SAI2ASEL)

#define RCC_SAI2ACLKSOURCE_PLL         (0x00000000U)

#define RCC_SAI2ACLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2ASEL_0

#define RCC_SAI2ACLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2ASEL_1

#define RCC_SAI2ACLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)

#define RCC_SAI2ACLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2ASEL_2

#define RCC_SAI2ACLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)

#endif /* RCC_CDCCIP1R_SAI2ASEL */


#if defined(RCC_CDCCIP1R_SAI2BSEL)

#define RCC_SAI2BCLKSOURCE_PLL         (0x00000000U)

#define RCC_SAI2BCLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2BSEL_0

#define RCC_SAI2BCLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2BSEL_1

#define RCC_SAI2BCLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)

#define RCC_SAI2BCLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2BSEL_2

#define RCC_SAI2BCLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)

#endif /* RCC_CDCCIP1R_SAI2BSEL */


#if defined(RCC_D2CCIP1R_SPI123SEL)

#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)

#define RCC_SPI123CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL_0

#define RCC_SPI123CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1

#define RCC_SPI123CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)

#define RCC_SPI123CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2

#else

#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)

#define RCC_SPI123CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI123SEL_0

#define RCC_SPI123CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI123SEL_1

#define RCC_SPI123CLKSOURCE_PIN         (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)

#define RCC_SPI123CLKSOURCE_CLKP         RCC_CDCCIP1R_SPI123SEL_2

#endif /* RCC_D2CCIP1R_SPI123SEL */

#define RCC_SPI1CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL

#define RCC_SPI1CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2

#define RCC_SPI1CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3

#define RCC_SPI1CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN

#define RCC_SPI1CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP


#define RCC_SPI2CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL

#define RCC_SPI2CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2

#define RCC_SPI2CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3

#define RCC_SPI2CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN

#define RCC_SPI2CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP


#define RCC_SPI3CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL

#define RCC_SPI3CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2

#define RCC_SPI3CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3

#define RCC_SPI3CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN

#define RCC_SPI3CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP


#if defined(RCC_D2CCIP1R_SPI45SEL)

#define RCC_SPI45CLKSOURCE_D2PCLK1     (0x00000000U)

#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_D2PCLK1

#define RCC_SPI45CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0

#define RCC_SPI45CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1

#define RCC_SPI45CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)

#define RCC_SPI45CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2

#define RCC_SPI45CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)

#else

#define RCC_SPI45CLKSOURCE_CDPCLK1     (0x00000000U)

/* aliases */

#define RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_CDPCLK1  /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */

#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_CDPCLK1

#define RCC_SPI45CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI45SEL_0

#define RCC_SPI45CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI45SEL_1

#define RCC_SPI45CLKSOURCE_HSI         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)

#define RCC_SPI45CLKSOURCE_CSI          RCC_CDCCIP1R_SPI45SEL_2

#define RCC_SPI45CLKSOURCE_HSE         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)

#endif /* RCC_D2CCIP1R_SPI45SEL */

#define RCC_SPI4CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1

#define RCC_SPI4CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2

#define RCC_SPI4CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3

#define RCC_SPI4CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI

#define RCC_SPI4CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI

#define RCC_SPI4CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE


#define RCC_SPI5CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1

#define RCC_SPI5CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2

#define RCC_SPI5CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3

#define RCC_SPI5CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI

#define RCC_SPI5CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI

#define RCC_SPI5CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE


#if defined(RCC_D3CCIPR_SPI6SEL)

#define RCC_SPI6CLKSOURCE_D3PCLK1     (0x00000000U)

#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_D3PCLK1

#define RCC_SPI6CLKSOURCE_PLL2         RCC_D3CCIPR_SPI6SEL_0

#define RCC_SPI6CLKSOURCE_PLL3         RCC_D3CCIPR_SPI6SEL_1

#define RCC_SPI6CLKSOURCE_HSI         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)

#define RCC_SPI6CLKSOURCE_CSI          RCC_D3CCIPR_SPI6SEL_2

#define RCC_SPI6CLKSOURCE_HSE         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)

#else

#define RCC_SPI6CLKSOURCE_SRDPCLK4    (0x00000000U)

/* alias */

#define RCC_SPI6CLKSOURCE_D3PCLK1      RCC_SPI6CLKSOURCE_SRDPCLK4  /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */

#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_SRDPCLK4

#define RCC_SPI6CLKSOURCE_PLL2         RCC_SRDCCIPR_SPI6SEL_0

#define RCC_SPI6CLKSOURCE_PLL3         RCC_SRDCCIPR_SPI6SEL_1

#define RCC_SPI6CLKSOURCE_HSI         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)

#define RCC_SPI6CLKSOURCE_CSI          RCC_SRDCCIPR_SPI6SEL_2

#define RCC_SPI6CLKSOURCE_HSE         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)

#define RCC_SPI6CLKSOURCE_PIN         (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

#endif /* RCC_D3CCIPR_SPI6SEL */


#if defined(SAI4_Block_A)

#define RCC_SAI4ACLKSOURCE_PLL         (0x00000000U)

#define RCC_SAI4ACLKSOURCE_PLL2         RCC_D3CCIPR_SAI4ASEL_0

#define RCC_SAI4ACLKSOURCE_PLL3         RCC_D3CCIPR_SAI4ASEL_1

#define RCC_SAI4ACLKSOURCE_PIN         (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)

#define RCC_SAI4ACLKSOURCE_CLKP         RCC_D3CCIPR_SAI4ASEL_2

#if defined(RCC_VER_3_0)

#define RCC_SAI4ACLKSOURCE_SPDIF       (RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)

#endif /*RCC_VER_3_0*/


#endif /* SAI4_Block_A */


#if defined(SAI4_Block_B)

#define RCC_SAI4BCLKSOURCE_PLL         (0x00000000U)

#define RCC_SAI4BCLKSOURCE_PLL2         RCC_D3CCIPR_SAI4BSEL_0

#define RCC_SAI4BCLKSOURCE_PLL3         RCC_D3CCIPR_SAI4BSEL_1

#define RCC_SAI4BCLKSOURCE_PIN         (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)

#define RCC_SAI4BCLKSOURCE_CLKP         RCC_D3CCIPR_SAI4BSEL_2

#if defined(RCC_VER_3_0)

#define RCC_SAI4BCLKSOURCE_SPDIF       (RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)

#endif /* RCC_VER_3_0 */


#endif /* SAI4_Block_B */


#if defined(RCC_D2CCIP2R_LPTIM1SEL)

#define RCC_LPTIM1CLKSOURCE_D2PCLK1        (0x00000000U)

/* alias */

#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_D2PCLK1

#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_D2CCIP2R_LPTIM1SEL_0

#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_D2CCIP2R_LPTIM1SEL_1

#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)

#define RCC_LPTIM1CLKSOURCE_LSI           RCC_D2CCIP2R_LPTIM1SEL_2

#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)

#else

#define RCC_LPTIM1CLKSOURCE_CDPCLK1        (0x00000000U)

/* alias */

#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_CDPCLK1

#define RCC_LPTIM1CLKSOURCE_D2PCLK1       RCC_LPTIM1CLKSOURCE_CDPCLK1

#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_CDCCIP2R_LPTIM1SEL_0

#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_CDCCIP2R_LPTIM1SEL_1

#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)

#define RCC_LPTIM1CLKSOURCE_LSI           RCC_CDCCIP2R_LPTIM1SEL_2

#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)

#endif /* RCC_D2CCIP2R_LPTIM1SEL */


#if defined(RCC_D3CCIPR_LPTIM2SEL)

#define RCC_LPTIM2CLKSOURCE_D3PCLK1       (0x00000000U)

/* alias */

#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_D3PCLK1

#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM2SEL_0

#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM2SEL_1

#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)

#define RCC_LPTIM2CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM2SEL_2

#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)

#else

#define RCC_LPTIM2CLKSOURCE_SRDPCLK4       (0x00000000U)

/*alias*/

#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_SRDPCLK4

#define RCC_LPTIM2CLKSOURCE_D3PCLK1       RCC_LPTIM2CLKSOURCE_SRDPCLK4

#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM2SEL_0

#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM2SEL_1

#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)

#define RCC_LPTIM2CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM2SEL_2

#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)

#endif /* RCC_D3CCIPR_LPTIM2SEL */

#if defined(RCC_D3CCIPR_LPTIM345SEL)

#define RCC_LPTIM345CLKSOURCE_D3PCLK1        (0x00000000U)

/* alias*/

#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_D3PCLK1

#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0

#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1

#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)

#define RCC_LPTIM345CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM345SEL_2

#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

#else

#define RCC_LPTIM345CLKSOURCE_SRDPCLK4      (0x00000000U)

/* alias */

#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_SRDPCLK4

#define RCC_LPTIM345CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_SRDPCLK4

#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM3SEL_0

#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM3SEL_1

#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)

#define RCC_LPTIM345CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM3SEL_2

#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)

#endif /* RCC_D3CCIPR_LPTIM345SEL */

#define RCC_LPTIM3CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1

#define RCC_LPTIM3CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2

#define RCC_LPTIM3CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3

#define RCC_LPTIM3CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE

#define RCC_LPTIM3CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI

#define RCC_LPTIM3CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP


#if defined(LPTIM4)

#define RCC_LPTIM4CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1

#define RCC_LPTIM4CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2

#define RCC_LPTIM4CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3

#define RCC_LPTIM4CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE

#define RCC_LPTIM4CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI

#define RCC_LPTIM4CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP

#endif /* LPTIM4 */


#if defined(LPTIM5)

#define RCC_LPTIM5CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1

#define RCC_LPTIM5CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2

#define RCC_LPTIM5CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3

#define RCC_LPTIM5CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE

#define RCC_LPTIM5CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI

#define RCC_LPTIM5CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP


#endif /* LPTIM5 */


#if defined(QUADSPI)

#define RCC_QSPICLKSOURCE_D1HCLK       (0x00000000U)

#define RCC_QSPICLKSOURCE_PLL          RCC_D1CCIPR_QSPISEL_0

#define RCC_QSPICLKSOURCE_PLL2         RCC_D1CCIPR_QSPISEL_1

#define RCC_QSPICLKSOURCE_CLKP         RCC_D1CCIPR_QSPISEL


#endif /* QUADSPI */


#if defined(OCTOSPI1) || defined(OCTOSPI2)

#if defined(RCC_CDCCIPR_OCTOSPISEL)

#define RCC_OSPICLKSOURCE_CDHCLK       (0x00000000U)

/*aliases*/

#define RCC_OSPICLKSOURCE_D1HCLK       RCC_OSPICLKSOURCE_CDHCLK

#define RCC_OSPICLKSOURCE_HCLK         RCC_OSPICLKSOURCE_CDHCLK

#define RCC_OSPICLKSOURCE_PLL          RCC_CDCCIPR_OCTOSPISEL_0

#define RCC_OSPICLKSOURCE_PLL2         RCC_CDCCIPR_OCTOSPISEL_1

#define RCC_OSPICLKSOURCE_CLKP         RCC_CDCCIPR_OCTOSPISEL

#else

#define RCC_OSPICLKSOURCE_D1HCLK       (0x00000000U)

#define RCC_OSPICLKSOURCE_HCLK         RCC_OSPICLKSOURCE_D1HCLK

#define RCC_OSPICLKSOURCE_PLL          RCC_D1CCIPR_OCTOSPISEL_0

#define RCC_OSPICLKSOURCE_PLL2         RCC_D1CCIPR_OCTOSPISEL_1

#define RCC_OSPICLKSOURCE_CLKP         RCC_D1CCIPR_OCTOSPISEL

#endif /* RCC_CDCCIPR_OCTOSPISEL */


#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */


#if defined(DSI)

#define RCC_DSICLKSOURCE_PHY       (0x00000000U)

#define RCC_DSICLKSOURCE_PLL2       RCC_D1CCIPR_DSISEL


#endif /* DSI */


#if defined(RCC_D1CCIPR_FMCSEL)

#define RCC_FMCCLKSOURCE_D1HCLK       (0x00000000U)

#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_D1HCLK

#define RCC_FMCCLKSOURCE_PLL          RCC_D1CCIPR_FMCSEL_0

#define RCC_FMCCLKSOURCE_PLL2         RCC_D1CCIPR_FMCSEL_1

#define RCC_FMCCLKSOURCE_CLKP         RCC_D1CCIPR_FMCSEL

#else

#define RCC_FMCCLKSOURCE_CDHCLK       (0x00000000U)

#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_CDHCLK

/*alias*/

#define RCC_FMCCLKSOURCE_D1HCLK       RCC_FMCCLKSOURCE_CDHCLK

#define RCC_FMCCLKSOURCE_PLL          RCC_CDCCIPR_FMCSEL_0

#define RCC_FMCCLKSOURCE_PLL2         RCC_CDCCIPR_FMCSEL_1

#define RCC_FMCCLKSOURCE_CLKP         RCC_CDCCIPR_FMCSEL

#endif /* RCC_D1CCIPR_FMCSEL */

#if defined(FDCAN1) || defined(FDCAN2)

#if defined(RCC_D2CCIP1R_FDCANSEL)

#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)

#define RCC_FDCANCLKSOURCE_PLL          RCC_D2CCIP1R_FDCANSEL_0

#define RCC_FDCANCLKSOURCE_PLL2         RCC_D2CCIP1R_FDCANSEL_1

#else

#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)

#define RCC_FDCANCLKSOURCE_PLL          RCC_CDCCIP1R_FDCANSEL_0

#define RCC_FDCANCLKSOURCE_PLL2         RCC_CDCCIP1R_FDCANSEL_1

#endif /* D3_SRAM_BASE */

#endif /*FDCAN1 || FDCAN2*/


#if defined(RCC_D1CCIPR_SDMMCSEL)

#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)

#define RCC_SDMMCCLKSOURCE_PLL2           RCC_D1CCIPR_SDMMCSEL

#else

#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)

#define RCC_SDMMCCLKSOURCE_PLL2           RCC_CDCCIPR_SDMMCSEL

#endif /* RCC_D1CCIPR_SDMMCSEL */

#if defined(RCC_D3CCIPR_ADCSEL_0)

#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)

#define RCC_ADCCLKSOURCE_PLL3       RCC_D3CCIPR_ADCSEL_0

#define RCC_ADCCLKSOURCE_CLKP       RCC_D3CCIPR_ADCSEL_1

#else

#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)

#define RCC_ADCCLKSOURCE_PLL3       RCC_SRDCCIPR_ADCSEL_0

#define RCC_ADCCLKSOURCE_CLKP       RCC_SRDCCIPR_ADCSEL_1

#endif /* RCC_D3CCIPR_ADCSEL_0  */

#if defined(RCC_D2CCIP1R_SWPSEL)

#define RCC_SWPMI1CLKSOURCE_D2PCLK1       (0x00000000U)

#define RCC_SWPMI1CLKSOURCE_HSI            RCC_D2CCIP1R_SWPSEL

#else

#define RCC_SWPMI1CLKSOURCE_CDPCLK1       (0x00000000U)

/* alias */

#define RCC_SWPMI1CLKSOURCE_D2PCLK1        RCC_SWPMI1CLKSOURCE_CDPCLK1

#define RCC_SWPMI1CLKSOURCE_HSI            RCC_CDCCIP1R_SWPSEL

#endif /* RCC_D2CCIP1R_SWPSEL */

#if defined(RCC_D2CCIP1R_DFSDM1SEL)

#define RCC_DFSDM1CLKSOURCE_D2PCLK1        (0x00000000U)

#define RCC_DFSDM1CLKSOURCE_SYS            RCC_D2CCIP1R_DFSDM1SEL

#else

#define RCC_DFSDM1CLKSOURCE_CDPCLK1        (0x00000000U)

/* alias */

#define RCC_DFSDM1CLKSOURCE_D2PCLK1        RCC_DFSDM1CLKSOURCE_CDPCLK1

#define RCC_DFSDM1CLKSOURCE_SYS            RCC_CDCCIP1R_DFSDM1SEL

#endif /* RCC_D2CCIP1R_DFSDM1SEL */

#if defined(DFSDM2_BASE)

#define RCC_DFSDM2CLKSOURCE_SRDPCLK4       (0x00000000U)

/* alias */

#define RCC_DFSDM2CLKSOURCE_SRDPCLK1       RCC_DFSDM2CLKSOURCE_SRDPCLK4

#define RCC_DFSDM2CLKSOURCE_SYS            RCC_SRDCCIPR_DFSDM2SEL

#endif /* DFSDM2 */


#if defined(RCC_D2CCIP1R_SPDIFSEL_0)

#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)

#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_D2CCIP1R_SPDIFSEL_0

#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_D2CCIP1R_SPDIFSEL_1

#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_D2CCIP1R_SPDIFSEL

#else

#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)

#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_CDCCIP1R_SPDIFSEL_0

#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_CDCCIP1R_SPDIFSEL_1

#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_CDCCIP1R_SPDIFSEL

#endif /* RCC_D2CCIP1R_SPDIFSEL_0 */

#if defined(RCC_D2CCIP2R_CECSEL_0)

#define RCC_CECCLKSOURCE_LSE        (0x00000000U)

#define RCC_CECCLKSOURCE_LSI         RCC_D2CCIP2R_CECSEL_0

#define RCC_CECCLKSOURCE_CSI         RCC_D2CCIP2R_CECSEL_1

#else

#define RCC_CECCLKSOURCE_LSE        (0x00000000U)

#define RCC_CECCLKSOURCE_LSI         RCC_CDCCIP2R_CECSEL_0

#define RCC_CECCLKSOURCE_CSI         RCC_CDCCIP2R_CECSEL_1

#endif /* RCC_D2CCIP2R_CECSEL_0 */

#if defined(RCC_D1CCIPR_CKPERSEL_0)

#define RCC_CLKPSOURCE_HSI        (0x00000000U)

#define RCC_CLKPSOURCE_CSI         RCC_D1CCIPR_CKPERSEL_0

#define RCC_CLKPSOURCE_HSE         RCC_D1CCIPR_CKPERSEL_1

#else

#define RCC_CLKPSOURCE_HSI        (0x00000000U)

#define RCC_CLKPSOURCE_CSI         RCC_CDCCIPR_CKPERSEL_0

#define RCC_CLKPSOURCE_HSE         RCC_CDCCIPR_CKPERSEL_1

#endif /* RCC_D1CCIPR_CKPERSEL_0 */

#define RCC_TIMPRES_DESACTIVATED        (0x00000000U)

#define RCC_TIMPRES_ACTIVATED            RCC_CFGR_TIMPRE


#if defined(DUAL_CORE)


#define RCC_BOOT_C1        RCC_GCR_BOOT_C1

#define RCC_BOOT_C2        RCC_GCR_BOOT_C2


#endif /*DUAL_CORE*/


#if defined(DUAL_CORE)

#define RCC_WWDG1        RCC_GCR_WW1RSC

#define RCC_WWDG2        RCC_GCR_WW2RSC


#else


#define RCC_WWDG1        RCC_GCR_WW1RSC


#endif /*DUAL_CORE*/


#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM18

#define RCC_CRS_NONE                   (0x00000000U)

#define RCC_CRS_TIMEOUT                (0x00000001U)

#define RCC_CRS_SYNCOK                 (0x00000002U)

#define RCC_CRS_SYNCWARN               (0x00000004U)

#define RCC_CRS_SYNCERR                (0x00000008U)

#define RCC_CRS_SYNCMISS               (0x00000010U)

#define RCC_CRS_TRIMOVF                (0x00000020U)

#define RCC_CRS_SYNC_SOURCE_PIN       (0x00000000U)

#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0

#define RCC_CRS_SYNC_SOURCE_USB1       CRS_CFGR_SYNCSRC_1

#define RCC_CRS_SYNC_SOURCE_USB2      (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)

#define RCC_CRS_SYNC_DIV1        (0x00000000U)

#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0

#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1

#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)

#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2

#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0)

#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1)

#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV

#define RCC_CRS_SYNC_POLARITY_RISING   (0x00000000U)

#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL

#define RCC_CRS_RELOADVALUE_DEFAULT    (0x0000BB7FU)

#define RCC_CRS_ERRORLIMIT_DEFAULT     (0x00000022U)

#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U)

#define RCC_CRS_FREQERRORDIR_UP        (0x00000000U)

#define RCC_CRS_FREQERRORDIR_DOWN      (CRS_ISR_FEDIR)

#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE

#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE

#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE

#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE

#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE

#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE

#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE

#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF

#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF

#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF

#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF

#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR

#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS

#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF

/* Exported macro ------------------------------------------------------------*/

#define __HAL_RCC_PLL2_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL2ON)

#define __HAL_RCC_PLL2_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)


#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))


#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))


#define __HAL_RCC_PLL2FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)


#define __HAL_RCC_PLL2FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)


#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \

                  do{ \

                       MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \

                       WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \

                       ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \

                    } while(0)


#define  __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \

                 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))


#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \

                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))


#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \

                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))


#define __HAL_RCC_PLL3_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL3ON)

#define __HAL_RCC_PLL3_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)


#define __HAL_RCC_PLL3FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)


#define __HAL_RCC_PLL3FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)


#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))


#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))


#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \

                  do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \

                         WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \

                                   ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \

                       } while(0)


 #define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)


#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \

                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))


#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \

                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))


#if defined(RCC_D2CCIP1R_SAI1SEL)

#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\

                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))

#else


#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\

                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))


#endif /* RCC_D2CCIP1R_SAI1SEL */


#if defined(RCC_D2CCIP1R_SAI1SEL)

#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))

#else

#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))

#endif /* RCC_D2CCIP1R_SAI1SEL */


#if defined(RCC_D2CCIP1R_SPDIFSEL)

#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\

                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))

#else


#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\

                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))


#endif /* RCC_D2CCIP1R_SPDIFSEL */


#if defined(RCC_D2CCIP1R_SPDIFSEL)

#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))

#else

#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))

#endif /* RCC_D2CCIP1R_SPDIFSEL */


#if defined(SAI3)

#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\

                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))


#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))


#define __HAL_RCC_SAI2_CONFIG  __HAL_RCC_SAI23_CONFIG


#define __HAL_RCC_GET_SAI2_SOURCE  __HAL_RCC_GET_SAI23_SOURCE


#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG


#define __HAL_RCC_GET_SAI3_SOURCE  __HAL_RCC_GET_SAI23_SOURCE

#endif /* SAI3 */


#if defined(RCC_CDCCIP1R_SAI2ASEL)

#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\

                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))


#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))

#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */


#if defined(RCC_CDCCIP1R_SAI2BSEL)

#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\

                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))


#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))

#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */


#if defined(SAI4_Block_A)

#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\

                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))


#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))

#endif /* SAI4_Block_A */


#if defined(SAI4_Block_B)

#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\

                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))


#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))

#endif /* SAI4_Block_B */


#if defined(RCC_D2CCIP2R_I2C123SEL)

#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \

                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__))

#elif defined(RCC_CDCCIP2R_I2C123SEL)

#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \

                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__))

#else /* RCC_D2CCIP2R_I2C1235SEL */


#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \

                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__))


/* alias */

#define __HAL_RCC_I2C123_CONFIG  __HAL_RCC_I2C1235_CONFIG

#endif /* RCC_D2CCIP2R_I2C123SEL */


#if defined(RCC_D2CCIP2R_I2C123SEL)

#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))

#elif defined(RCC_CDCCIP2R_I2C123SEL)

#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))

#else /* RCC_D2CCIP2R_I2C1235SEL */

#define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL)))

/* alias */

#define __HAL_RCC_GET_I2C123_SOURCE  __HAL_RCC_GET_I2C1235_SOURCE

#endif /* RCC_D2CCIP2R_I2C123SEL */


#if defined(I2C5)

#define __HAL_RCC_I2C1_CONFIG  __HAL_RCC_I2C1235_CONFIG

#else

#define __HAL_RCC_I2C1_CONFIG  __HAL_RCC_I2C123_CONFIG

#endif /*I2C5*/


#if defined(I2C5)

#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE

#else

#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE

#endif /*I2C5*/


#if defined(I2C5)

#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG

#else

#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG

#endif /*I2C5*/


#if defined(I2C5)

#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE

#else

#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE

#endif /*I2C5*/


#if defined(I2C5)

#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG

#else

#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG

#endif /*I2C5*/


#if defined(I2C5)

#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE

#else

#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE

#endif /*I2C5*/


#if defined(RCC_D3CCIPR_I2C4SEL)

#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \

                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))

#else


#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \

                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))


#endif /* RCC_D3CCIPR_I2C4SEL */


#if defined(RCC_D3CCIPR_I2C4SEL)

#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))

#else

#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL)))

#endif /* RCC_D3CCIPR_I2C4SEL */


#if defined(I2C5)

#define __HAL_RCC_I2C5_CONFIG  __HAL_RCC_I2C1235_CONFIG

#endif /* I2C5 */


#if defined(I2C5)

#define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE

#endif /* I2C5 */


#if defined(RCC_D2CCIP2R_USART16SEL)

#define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \

                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__))

#elif defined(RCC_CDCCIP2R_USART16910SEL)

#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \

                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))

/* alias */

#define __HAL_RCC_USART16_CONFIG  __HAL_RCC_USART16910_CONFIG

#else  /* RCC_D2CCIP2R_USART16910SEL */


#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \

                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))


/* alias */

#define __HAL_RCC_USART16_CONFIG  __HAL_RCC_USART16910_CONFIG

#endif /* RCC_D2CCIP2R_USART16SEL */


#if defined(RCC_D2CCIP2R_USART16SEL)

#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))

#elif defined(RCC_CDCCIP2R_USART16910SEL)

#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))

/* alias*/

#define  __HAL_RCC_GET_USART16_SOURCE  __HAL_RCC_GET_USART16910_SOURCE

#else  /* RCC_D2CCIP2R_USART16910SEL */

#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL)))

/* alias */

#define __HAL_RCC_GET_USART16_SOURCE  __HAL_RCC_GET_USART16910_SOURCE

#endif /* RCC_D2CCIP2R_USART16SEL */


#if defined(RCC_D2CCIP2R_USART28SEL)

#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \

                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))

#else


#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \

                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))


#endif /* RCC_D2CCIP2R_USART28SEL */


#if defined(RCC_D2CCIP2R_USART28SEL)

#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))

#else

#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))

#endif /* RCC_D2CCIP2R_USART28SEL */


#define __HAL_RCC_USART1_CONFIG  __HAL_RCC_USART16_CONFIG


#define __HAL_RCC_GET_USART1_SOURCE  __HAL_RCC_GET_USART16_SOURCE


#define __HAL_RCC_USART2_CONFIG  __HAL_RCC_USART234578_CONFIG


#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE


#define __HAL_RCC_USART3_CONFIG  __HAL_RCC_USART234578_CONFIG


#define __HAL_RCC_GET_USART3_SOURCE  __HAL_RCC_GET_USART234578_SOURCE


#define __HAL_RCC_UART4_CONFIG  __HAL_RCC_USART234578_CONFIG


#define __HAL_RCC_GET_UART4_SOURCE  __HAL_RCC_GET_USART234578_SOURCE


#define __HAL_RCC_UART5_CONFIG  __HAL_RCC_USART234578_CONFIG


#define __HAL_RCC_GET_UART5_SOURCE  __HAL_RCC_GET_USART234578_SOURCE


#define __HAL_RCC_USART6_CONFIG  __HAL_RCC_USART16_CONFIG


#define __HAL_RCC_GET_USART6_SOURCE  __HAL_RCC_GET_USART16_SOURCE


#define __HAL_RCC_UART7_CONFIG  __HAL_RCC_USART234578_CONFIG


#define __HAL_RCC_GET_UART7_SOURCE  __HAL_RCC_GET_USART234578_SOURCE


#define __HAL_RCC_UART8_CONFIG  __HAL_RCC_USART234578_CONFIG


#define __HAL_RCC_GET_UART8_SOURCE  __HAL_RCC_GET_USART234578_SOURCE


#if defined(UART9)

#define __HAL_RCC_UART9_CONFIG  __HAL_RCC_USART16_CONFIG


#define __HAL_RCC_GET_UART9_SOURCE  __HAL_RCC_GET_USART16_SOURCE

#endif /* UART9 */


#if defined(USART10)

#define __HAL_RCC_USART10_CONFIG  __HAL_RCC_USART16_CONFIG


#define __HAL_RCC_GET_USART10_SOURCE  __HAL_RCC_GET_USART16_SOURCE

#endif /* USART10 */


#if defined (RCC_D3CCIPR_LPUART1SEL)

#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \

                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))

#else


#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \

                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))


#endif /* RCC_D3CCIPR_LPUART1SEL */


#if defined (RCC_D3CCIPR_LPUART1SEL)

#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))

#else

#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))

#endif /* RCC_D3CCIPR_LPUART1SEL */


#if defined(RCC_D2CCIP2R_LPTIM1SEL)

#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \

                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))

#else


#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \

                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))


#endif /* RCC_D2CCIP2R_LPTIM1SEL */


#if defined(RCC_D2CCIP2R_LPTIM1SEL)

#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))

#else

#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))

#endif /* RCC_D2CCIP2R_LPTIM1SEL */


#if defined(RCC_D3CCIPR_LPTIM2SEL)

#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \

                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))

#else


#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \

                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))


#endif /* RCC_D3CCIPR_LPTIM2SEL */


#if defined(RCC_D3CCIPR_LPTIM2SEL)

#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))

#else

#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))

#endif /* RCC_D3CCIPR_LPTIM2SEL */


#if defined(RCC_D3CCIPR_LPTIM345SEL)

#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \

                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))

#else


#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \

                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__))


#endif /* RCC_D3CCIPR_LPTIM345SEL */


#if defined(RCC_D3CCIPR_LPTIM345SEL)

#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))

#else

#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))

#endif /* RCC_D3CCIPR_LPTIM345SEL */


#define __HAL_RCC_LPTIM3_CONFIG  __HAL_RCC_LPTIM345_CONFIG


#define __HAL_RCC_GET_LPTIM3_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE


#if defined(LPTIM4)

#define __HAL_RCC_LPTIM4_CONFIG  __HAL_RCC_LPTIM345_CONFIG


#define __HAL_RCC_GET_LPTIM4_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE

#endif /* LPTIM4 */


#if defined(LPTIM5)

#define __HAL_RCC_LPTIM5_CONFIG  __HAL_RCC_LPTIM345_CONFIG


#define __HAL_RCC_GET_LPTIM5_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE

#endif /* LPTIM5 */


#if defined(QUADSPI)

#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \

                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))


#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))

#endif /* QUADSPI */


#if defined(OCTOSPI1) || defined(OCTOSPI2)

#if defined(RCC_CDCCIPR_OCTOSPISEL)

#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \

                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))

#else

#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \

                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))

#endif /* RCC_CDCCIPR_OCTOSPISEL */


#if defined(RCC_CDCCIPR_OCTOSPISEL)

#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))

#else

#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)))

#endif /* RCC_CDCCIPR_OCTOSPISEL */

#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */


#if defined(DSI)

#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \

                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))


#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))

#endif /*DSI*/


#if defined(RCC_D1CCIPR_FMCSEL)

#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \

                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))

#else


#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \

                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))


#endif /* RCC_D1CCIPR_FMCSEL */


#if defined(RCC_D1CCIPR_FMCSEL)

#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))

#else

#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))

#endif /* RCC_D1CCIPR_FMCSEL */


#if defined(RCC_D2CCIP2R_USBSEL)

#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \

                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))

#else


#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \

                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))


#endif /* RCC_D2CCIP2R_USBSEL */


#if defined(RCC_D2CCIP2R_USBSEL)

#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))

#else

#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))

#endif /* RCC_D2CCIP2R_USBSEL */


#if defined(RCC_D3CCIPR_ADCSEL)

#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \

                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))

#else


#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \

                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))


#endif /* RCC_D3CCIPR_ADCSEL */


#if defined(RCC_D3CCIPR_ADCSEL)

#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))

#else

#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))

#endif /* RCC_D3CCIPR_ADCSEL */


#if defined(RCC_D2CCIP1R_SWPSEL)

#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \

                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))

#else


#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \

                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))


#endif /* RCC_D2CCIP1R_SWPSEL */


#if defined(RCC_D2CCIP1R_SWPSEL)

#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))

#else

#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))

#endif /* RCC_D2CCIP1R_SWPSEL */


#if defined(RCC_D2CCIP1R_DFSDM1SEL)

#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \

                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))

#else


#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \

                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))


#endif /* RCC_D2CCIP1R_DFSDM1SEL */


#if defined (RCC_D2CCIP1R_DFSDM1SEL)

#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))

#else

#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))

#endif /* RCC_D2CCIP1R_DFSDM1SEL */


#if defined(DFSDM2_BASE)

#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \

                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))


#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))

#endif /* DFSDM2 */


#if defined(RCC_D2CCIP2R_CECSEL)

#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \

                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))

#else


#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \

                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))


#endif /* RCC_D2CCIP2R_CECSEL */


#if defined(RCC_D2CCIP2R_CECSEL)

#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))

#else

#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))

#endif /* RCC_D2CCIP2R_CECSEL */


#if defined(RCC_D1CCIPR_CKPERSEL)

#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \

                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))

#else


#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \

                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))


#endif /* RCC_D1CCIPR_CKPERSEL */


#if defined(RCC_D1CCIPR_CKPERSEL)

#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))

#else

#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))

#endif /* RCC_D1CCIPR_CKPERSEL */


#if defined(FDCAN1) || defined(FDCAN2)

#if defined(RCC_D2CCIP1R_FDCANSEL)

#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \

                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))

#else

#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \

                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))

#endif /* RCC_D2CCIP1R_FDCANSEL */


#if defined(RCC_D2CCIP1R_FDCANSEL)

#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))

#else

#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))

#endif /* RCC_D2CCIP1R_FDCANSEL */


#endif /*FDCAN1 || FDCAN2*/


#if defined(RCC_D2CCIP1R_SPI123SEL)

#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\

                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))

#else


#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\

                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))


#endif /* RCC_D2CCIP1R_SPI123SEL */


#if defined(RCC_D2CCIP1R_SPI123SEL)

#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))

#else

#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))

#endif /* RCC_D2CCIP1R_SPI123SEL */


#define __HAL_RCC_SPI1_CONFIG  __HAL_RCC_SPI123_CONFIG


#define __HAL_RCC_GET_SPI1_SOURCE  __HAL_RCC_GET_SPI123_SOURCE


#define __HAL_RCC_SPI2_CONFIG  __HAL_RCC_SPI123_CONFIG


#define __HAL_RCC_GET_SPI2_SOURCE  __HAL_RCC_GET_SPI123_SOURCE


#define __HAL_RCC_SPI3_CONFIG  __HAL_RCC_SPI123_CONFIG


#define __HAL_RCC_GET_SPI3_SOURCE  __HAL_RCC_GET_SPI123_SOURCE


#if defined(RCC_D2CCIP1R_SPI45SEL)

#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\

                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))

#else


#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\

                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))


#endif /* RCC_D2CCIP1R_SPI45SEL */


#if defined(RCC_D2CCIP1R_SPI45SEL)

#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))

#else

#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))

#endif /* RCC_D2CCIP1R_SPI45SEL */


#define __HAL_RCC_SPI4_CONFIG  __HAL_RCC_SPI45_CONFIG


#define __HAL_RCC_GET_SPI4_SOURCE  __HAL_RCC_GET_SPI45_SOURCE


#define __HAL_RCC_SPI5_CONFIG  __HAL_RCC_SPI45_CONFIG


#define __HAL_RCC_GET_SPI5_SOURCE  __HAL_RCC_GET_SPI45_SOURCE


#if defined(RCC_D3CCIPR_SPI6SEL)

#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\

                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))

#else


#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\

                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))


#endif /* RCC_D3CCIPR_SPI6SEL */


#if defined(RCC_D3CCIPR_SPI6SEL)

#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))

#else

#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))

#endif /* RCC_D3CCIPR_SPI6SEL */


#if defined(RCC_D1CCIPR_SDMMCSEL)

#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \

                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))

#else


#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \

                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))


#endif /* RCC_D1CCIPR_SDMMCSEL */


#if defined(RCC_D1CCIPR_SDMMCSEL)

#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))

#else

#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))

#endif /* RCC_D1CCIPR_SDMMCSEL */


#if defined(RCC_D2CCIP2R_RNGSEL)

#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \

                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))

#else


#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \

                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))


#endif /* RCC_D2CCIP2R_RNGSEL */


#if defined(RCC_D2CCIP2R_RNGSEL)

#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))

#else

#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))

#endif /* RCC_D2CCIP2R_RNGSEL */


#if defined(HRTIM1)

#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \

                  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))


#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))

#endif /* HRTIM1 */


#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\

                                                 RCC->CFGR |= (__PRESC__);       \

                                                }while(0)


#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)


#if defined(DUAL_CORE)

#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT()       SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT()      CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT()    SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT()   CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)

#endif /* DUAL_CORE */


#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \

  do {                                                      \

    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \

    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \

  } while(0)


#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \

  do {                                                       \

    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \

    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \

  } while(0)


#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)


#if defined(DUAL_CORE)

#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)

#endif /* DUAL_CORE */

#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)


#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))


#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))


#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)


/* CRS IT Error Mask */

#define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))


#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \

                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \

                                                 { \

                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \

                                                 } \

                                                 else \

                                                 { \

                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \

                                                 } \

                                               } while(0)


#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))


/* CRS Flag Error Mask */

#define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))


#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \

                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \

                                                 { \

                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \

                                                 } \

                                                 else \

                                                 { \

                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \

                                                 } \

                                               } while(0)


#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)


#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)


#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)


#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)


#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)


/* Exported functions --------------------------------------------------------*/

HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);

void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);

uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);

uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);

uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);

uint32_t HAL_RCCEx_GetD1SysClockFreq(void);

void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);

void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);

void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);

void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);

void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);

void HAL_RCCEx_EnableLSECSS(void);

void HAL_RCCEx_DisableLSECSS(void);

void HAL_RCCEx_EnableLSECSS_IT(void);

void HAL_RCCEx_LSECSS_IRQHandler(void);

void HAL_RCCEx_LSECSS_Callback(void);

#if defined(DUAL_CORE)

void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);

#endif /*DUAL_CORE*/

#if defined(RCC_GCR_WW1RSC)

void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);

#endif /*RCC_GCR_WW1RSC*/

void     HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);

void     HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);

void     HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);

uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);

void     HAL_RCCEx_CRS_IRQHandler(void);

void     HAL_RCCEx_CRS_SyncOkCallback(void);

void     HAL_RCCEx_CRS_SyncWarnCallback(void);

void     HAL_RCCEx_CRS_ExpectedSyncCallback(void);

void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);


 /* Private macros ------------------------------------------------------------*/

#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \

                                         ((VALUE) == RCC_PLL2_DIVQ)  || \

                                         ((VALUE) == RCC_PLL2_DIVR))


#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \

                                          ((VALUE) == RCC_PLL3_DIVQ) || \

                                          ((VALUE) == RCC_PLL3_DIVR))


#if defined(RCC_D2CCIP2R_USART16SEL)

#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))

#else

#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \

                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))

/* alias*/

#define IS_RCC_USART16910CLKSOURCE    IS_RCC_USART16CLKSOURCE

#endif /* RCC_D2CCIP2R_USART16SEL */


#if defined(RCC_D2CCIP2R_USART28SEL)

#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))

#else

#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \

                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))

#endif /* RCC_D2CCIP2R_USART28SEL */


#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \

                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \

                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \

                                        ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \

                                        ((SOURCE) == RCC_USART1CLKSOURCE_HSI))


#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \

                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \

                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \

                                        ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \

                                        ((SOURCE) == RCC_USART2CLKSOURCE_HSI))


#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \

                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \

                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \

                                        ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \

                                        ((SOURCE) == RCC_USART3CLKSOURCE_HSI))


#define IS_RCC_UART4CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \

                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)    || \

                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)    || \

                                        ((SOURCE) == RCC_UART4CLKSOURCE_CSI)     || \

                                        ((SOURCE) == RCC_UART4CLKSOURCE_LSE)     || \

                                        ((SOURCE) == RCC_UART4CLKSOURCE_HSI))


#define IS_RCC_UART5CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \

                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)    || \

                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)    || \

                                        ((SOURCE) == RCC_UART5CLKSOURCE_CSI)     || \

                                        ((SOURCE) == RCC_UART5CLKSOURCE_LSE)     || \

                                        ((SOURCE) == RCC_UART5CLKSOURCE_HSI))


#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \

                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \

                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \

                                        ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \

                                        ((SOURCE) == RCC_USART6CLKSOURCE_HSI))


#define IS_RCC_UART7CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \

                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)    || \

                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)    || \

                                        ((SOURCE) == RCC_UART7CLKSOURCE_CSI)     || \

                                        ((SOURCE) == RCC_UART7CLKSOURCE_LSE)     || \

                                        ((SOURCE) == RCC_UART7CLKSOURCE_HSI))


#define IS_RCC_UART8CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \

                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)    || \

                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)    || \

                                        ((SOURCE) == RCC_UART8CLKSOURCE_CSI)     || \

                                        ((SOURCE) == RCC_UART8CLKSOURCE_LSE)     || \

                                        ((SOURCE) == RCC_UART8CLKSOURCE_HSI))


#if defined(UART9)

#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \

                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL2)  || \

                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL3)  || \

                                        ((SOURCE) == RCC_UART9CLKSOURCE_CSI)   || \

                                        ((SOURCE) == RCC_UART9CLKSOURCE_LSE)   || \

                                        ((SOURCE) == RCC_UART9CLKSOURCE_HSI))

#endif


#if defined(USART10)

#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \

                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL2)    || \

                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL3)    || \

                                        ((SOURCE) == RCC_USART10CLKSOURCE_CSI)     || \

                                        ((SOURCE) == RCC_USART10CLKSOURCE_LSE)     || \

                                        ((SOURCE) == RCC_USART10CLKSOURCE_HSI))

#endif


#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \

                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)    || \

                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)    || \

                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)     || \

                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)     || \

                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))


#if defined(I2C5)

#define IS_RCC_I2C1235CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3)   || \

                                          ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI)     || \

                                          ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \

                                          ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI))


#define IS_RCC_I2C123CLKSOURCE    IS_RCC_I2C1235CLKSOURCE  /* For  API Backward compatibility */

#else

#define IS_RCC_I2C123CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3)   || \

                                          ((SOURCE) == RCC_I2C123CLKSOURCE_HSI)    || \

                                          ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \

                                          ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))

#endif /*I2C5*/


#define IS_RCC_I2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \

                                        ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \

                                        ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))


#define IS_RCC_I2C2CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \

                                        ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \

                                        ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))


#define IS_RCC_I2C3CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \

                                        ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \

                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))


#define IS_RCC_I2C4CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \

                                        ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \

                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))


#if defined(I2C5)

#define IS_RCC_I2C5CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_I2C5CLKSOURCE_HSI)    || \

                                        ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \

                                        ((SOURCE) == RCC_I2C5CLKSOURCE_CSI))

#endif /*I2C5*/


#define IS_RCC_RNGCLKSOURCE(SOURCE)    (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \

                                        ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \

                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \

                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSI))


#if defined(HRTIM1)

#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \

                                        ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))

#endif


#define IS_RCC_USBCLKSOURCE(SOURCE)    (((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \

                                        ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \

                                        ((SOURCE) == RCC_USBCLKSOURCE_HSI48))


#define IS_RCC_SAI1CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))


#if defined(SAI3)

#define IS_RCC_SAI23CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))


#define IS_RCC_SAI2CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))


#define IS_RCC_SAI3CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))

#endif


#if defined(RCC_CDCCIP1R_SAI2ASEL)

#define IS_RCC_SAI2ACLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \

                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))

#endif


#if defined(RCC_CDCCIP1R_SAI2BSEL)

#define IS_RCC_SAI2BCLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \

                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))

#endif


#define IS_RCC_SPI123CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))


#define IS_RCC_SPI1CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))


#define IS_RCC_SPI2CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))


#define IS_RCC_SPI3CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))


#define IS_RCC_SPI45CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1)  || \

                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2)     || \

                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3)     || \

                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI)      || \

                ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI)      || \

                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))


#define IS_RCC_SPI4CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \

                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \

                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \

                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \

                ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \

                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))


#define IS_RCC_SPI5CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \

                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \

                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \

                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \

                ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \

                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))


#if defined(RCC_D3CCIPR_SPI6SEL)

#define IS_RCC_SPI6CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))

#else

#define IS_RCC_SPI6CLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)     || \

                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))

#endif /* RCC_D3CCIPR_SPI6SEL */


#if defined(SAI4)

#define IS_RCC_SAI4ACLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))


#define IS_RCC_SAI4BCLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \

                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \

                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \

                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))

#endif /*SAI4*/


#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))

#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))

#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))


#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))

#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))

#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))


#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0)  || \

                                    ((VALUE) == RCC_PLL2VCIRANGE_1)   || \

                                    ((VALUE) == RCC_PLL2VCIRANGE_2)   || \

                                    ((VALUE) == RCC_PLL2VCIRANGE_3))


#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0)  || \

                                    ((VALUE) == RCC_PLL3VCIRANGE_1)   || \

                                    ((VALUE) == RCC_PLL3VCIRANGE_2)   || \

                                    ((VALUE) == RCC_PLL3VCIRANGE_3))


#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE)  || \

                                    ((VALUE) == RCC_PLL2VCOMEDIUM))


#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE)  || \

                                    ((VALUE) == RCC_PLL3VCOMEDIUM))


#define IS_RCC_LPTIM1CLK(SOURCE)       (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \

                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \

                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \

                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \

                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))


#define IS_RCC_LPTIM2CLK(SOURCE)       (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \

                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \

                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \

                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \

                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))


#define IS_RCC_LPTIM345CLK(SOURCE)     (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \

                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2)   || \

                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE)    || \

                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI)    || \

                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))


#define IS_RCC_LPTIM3CLK(SOURCE)       (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)  || \

                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)     || \

                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)     || \

                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)      || \

                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)      || \

                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))


#if defined(LPTIM4)

#define IS_RCC_LPTIM4CLK(SOURCE)       (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \

                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2)   || \

                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE)    || \

                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI)    || \

                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))

#endif /* LPTIM4*/


#if defined(LPTIM5)

#define IS_RCC_LPTIM5CLK(SOURCE)       (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \

                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2)   || \

                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3)   || \

                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE)    || \

                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI)    || \

                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))

#endif /*LPTIM5*/


#if defined(QUADSPI)

#define IS_RCC_QSPICLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK)  || \

                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)     || \

                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2)    || \

                ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))

#endif /*QUADSPI*/


#if defined(OCTOSPI1) || defined(OCTOSPI1)

#define IS_RCC_OSPICLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK)  || \

                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)     || \

                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)    || \

                ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))

#endif /*OCTOSPI1 || OCTOSPI1*/


#if defined(DSI)

#define IS_RCC_DSICLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_DSICLKSOURCE_PHY)  || \

                ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))

#endif /*DSI*/


#define IS_RCC_FMCCLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \

                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \

                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \

                ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))


#if defined(FDCAN1) || defined(FDCAN2)

#define IS_RCC_FDCANCLK(__SOURCE__)   \

               (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \

                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))

#endif /*FDCAN1 || FDCAN2*/


#define IS_RCC_SDMMC(__SOURCE__)   \

                (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \

                ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))


#define IS_RCC_ADCCLKSOURCE(SOURCE)    (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \

                                        ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \

                                        ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))


#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \

                                        ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))


#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \

                                         ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))


#if defined(DFSDM2_BASE)

#define IS_RCC_DFSDM2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \

                                        ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))

#endif /*DFSDM2*/


#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \

                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \

                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \

                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))


#define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \

                                      ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \

                                      ((SOURCE) == RCC_CECCLKSOURCE_CSI))


#define IS_RCC_CLKPSOURCE(SOURCE)   (((SOURCE) == RCC_CLKPSOURCE_HSI)  || \

                                      ((SOURCE) == RCC_CLKPSOURCE_CSI) || \

                                      ((SOURCE) == RCC_CLKPSOURCE_HSE))

#define IS_RCC_TIMPRES(VALUE)  \

               (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \

                ((VALUE) == RCC_TIMPRES_ACTIVATED))


#if defined(DUAL_CORE)

#define IS_RCC_BOOT_CORE(CORE)   (((CORE) == RCC_BOOT_C1)  || \

                                  ((CORE) == RCC_BOOT_C2))

#endif /*DUAL_CORE*/


#if defined(DUAL_CORE)

#define IS_RCC_SCOPE_WWDG(WWDG)   (((WWDG) == RCC_WWDG1)  || \

                                  ((WWDG) == RCC_WWDG2))

#else

#define IS_RCC_SCOPE_WWDG(WWDG)   ((WWDG) == RCC_WWDG1)


#endif /*DUAL_CORE*/


#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \

                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \

                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \

                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))


#define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \

                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \

                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \

                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))


#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \

                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))


#define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))


#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))


#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))


#define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \

                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))

#ifdef __cplusplus

}

#endif


#endif /* STM32H7xx_HAL_RCC_EX_H */


/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f1xx_hal_def.h:40

stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.

PLL1_ClocksTypeDef
RCC PLL1 Clocks structure definition.
Definition stm32h7xx_hal_rcc_ex.h:112

PLL2_ClocksTypeDef
RCC PLL2 Clocks structure definition.
Definition stm32h7xx_hal_rcc_ex.h:122

PLL3_ClocksTypeDef
RCC PLL3 Clocks structure definition.
Definition stm32h7xx_hal_rcc_ex.h:132

RCC_CRSInitTypeDef
RCC_CRS Init structure definition.
Definition stm32h7xx_hal_rcc_ex.h:296

RCC_CRSInitTypeDef::Polarity
uint32_t Polarity
Definition stm32h7xx_hal_rcc_ex.h:303

RCC_CRSInitTypeDef::HSI48CalibrationValue
uint32_t HSI48CalibrationValue
Definition stm32h7xx_hal_rcc_ex.h:313

RCC_CRSInitTypeDef::Prescaler
uint32_t Prescaler
Definition stm32h7xx_hal_rcc_ex.h:297

RCC_CRSInitTypeDef::ReloadValue
uint32_t ReloadValue
Definition stm32h7xx_hal_rcc_ex.h:306

RCC_CRSInitTypeDef::Source
uint32_t Source
Definition stm32h7xx_hal_rcc_ex.h:300

RCC_CRSInitTypeDef::ErrorLimitValue
uint32_t ErrorLimitValue
Definition stm32h7xx_hal_rcc_ex.h:310

RCC_CRSSynchroInfoTypeDef
RCC_CRS Synchronization structure definition.
Definition stm32h7xx_hal_rcc_ex.h:322

RCC_CRSSynchroInfoTypeDef::HSI48CalibrationValue
uint32_t HSI48CalibrationValue
Definition stm32h7xx_hal_rcc_ex.h:326

RCC_CRSSynchroInfoTypeDef::ReloadValue
uint32_t ReloadValue
Definition stm32h7xx_hal_rcc_ex.h:323

RCC_CRSSynchroInfoTypeDef::FreqErrorDirection
uint32_t FreqErrorDirection
Definition stm32h7xx_hal_rcc_ex.h:333

RCC_CRSSynchroInfoTypeDef::FreqErrorCapture
uint32_t FreqErrorCapture
Definition stm32h7xx_hal_rcc_ex.h:329

RCC_PLL2InitTypeDef
PLL2 Clock structure definition.
Definition stm32h7xx_hal_rcc_ex.h:48

RCC_PLL2InitTypeDef::PLL2R
uint32_t PLL2R
Definition stm32h7xx_hal_rcc_ex.h:65

RCC_PLL2InitTypeDef::PLL2M
uint32_t PLL2M
Definition stm32h7xx_hal_rcc_ex.h:50

RCC_PLL2InitTypeDef::PLL2RGE
uint32_t PLL2RGE
Definition stm32h7xx_hal_rcc_ex.h:67

RCC_PLL2InitTypeDef::PLL2N
uint32_t PLL2N
Definition stm32h7xx_hal_rcc_ex.h:53

RCC_PLL2InitTypeDef::PLL2FRACN
uint32_t PLL2FRACN
Definition stm32h7xx_hal_rcc_ex.h:72

RCC_PLL2InitTypeDef::PLL2VCOSEL
uint32_t PLL2VCOSEL
Definition stm32h7xx_hal_rcc_ex.h:69

RCC_PLL2InitTypeDef::PLL2P
uint32_t PLL2P
Definition stm32h7xx_hal_rcc_ex.h:58

RCC_PLL2InitTypeDef::PLL2Q
uint32_t PLL2Q
Definition stm32h7xx_hal_rcc_ex.h:62

RCC_PLL3InitTypeDef
PLL3 Clock structure definition.
Definition stm32h7xx_hal_rcc_ex.h:80

RCC_PLL3InitTypeDef::PLL3Q
uint32_t PLL3Q
Definition stm32h7xx_hal_rcc_ex.h:94

RCC_PLL3InitTypeDef::PLL3FRACN
uint32_t PLL3FRACN
Definition stm32h7xx_hal_rcc_ex.h:104

RCC_PLL3InitTypeDef::PLL3N
uint32_t PLL3N
Definition stm32h7xx_hal_rcc_ex.h:85

RCC_PLL3InitTypeDef::PLL3VCOSEL
uint32_t PLL3VCOSEL
Definition stm32h7xx_hal_rcc_ex.h:101

RCC_PLL3InitTypeDef::PLL3P
uint32_t PLL3P
Definition stm32h7xx_hal_rcc_ex.h:90

RCC_PLL3InitTypeDef::PLL3R
uint32_t PLL3R
Definition stm32h7xx_hal_rcc_ex.h:97

RCC_PLL3InitTypeDef::PLL3RGE
uint32_t PLL3RGE
Definition stm32h7xx_hal_rcc_ex.h:99

RCC_PLL3InitTypeDef::PLL3M
uint32_t PLL3M
Definition stm32h7xx_hal_rcc_ex.h:82

RCC_PeriphCLKInitTypeDef
RCC extended clocks structure definition.
Definition stm32f1xx_hal_rcc_ex.h:284

RCC_PeriphCLKInitTypeDef::Spi123ClockSelection
uint32_t Spi123ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:196

RCC_PeriphCLKInitTypeDef::Spi6ClockSelection
uint32_t Spi6ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:269

RCC_PeriphCLKInitTypeDef::I2c123ClockSelection
uint32_t I2c123ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:234

RCC_PeriphCLKInitTypeDef::Usart16ClockSelection
uint32_t Usart16ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:224

RCC_PeriphCLKInitTypeDef::CkperClockSelection
uint32_t CkperClockSelection
Definition stm32h7xx_hal_rcc_ex.h:175

RCC_PeriphCLKInitTypeDef::Swpmi1ClockSelection
uint32_t Swpmi1ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:218

RCC_PeriphCLKInitTypeDef::Lptim2ClockSelection
uint32_t Lptim2ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:253

RCC_PeriphCLKInitTypeDef::SpdifrxClockSelection
uint32_t SpdifrxClockSelection
Definition stm32h7xx_hal_rcc_ex.h:202

RCC_PeriphCLKInitTypeDef::SdmmcClockSelection
uint32_t SdmmcClockSelection
Definition stm32h7xx_hal_rcc_ex.h:172

RCC_PeriphCLKInitTypeDef::PLL2
RCC_PLL2InitTypeDef PLL2
Definition stm32h7xx_hal_rcc_ex.h:147

RCC_PeriphCLKInitTypeDef::Dfsdm1ClockSelection
uint32_t Dfsdm1ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:205

RCC_PeriphCLKInitTypeDef::PLL3
RCC_PLL3InitTypeDef PLL3
Definition stm32h7xx_hal_rcc_ex.h:150

RCC_PeriphCLKInitTypeDef::Lptim345ClockSelection
uint32_t Lptim345ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:256

RCC_PeriphCLKInitTypeDef::Usart234578ClockSelection
uint32_t Usart234578ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:221

RCC_PeriphCLKInitTypeDef::FmcClockSelection
uint32_t FmcClockSelection
Definition stm32h7xx_hal_rcc_ex.h:153

RCC_PeriphCLKInitTypeDef::UsbClockSelection
uint32_t UsbClockSelection
Definition stm32h7xx_hal_rcc_ex.h:238

RCC_PeriphCLKInitTypeDef::Lpuart1ClockSelection
uint32_t Lpuart1ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:247

RCC_PeriphCLKInitTypeDef::Spi45ClockSelection
uint32_t Spi45ClockSelection
Definition stm32h7xx_hal_rcc_ex.h:199

RCC_PeriphCLKInitTypeDef::RngClockSelection
uint32_t RngClockSelection
Definition stm32h7xx_hal_rcc_ex.h:227