hw_eth.h

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#ifndef _HW_ETH_H_
#define _HW_ETH_H_
 
#ifdef __cplusplus
extern "C"{
#endif
 
#include "mcu.h"
#include "net.h"
 
static inline void hw_eth_init(void);
 
void mk6xEthInitGpio(NetInterface *interface) {
    hw_eth_init();
}
 
static inline void hw_eth_init(void) {
    //Note: Added for MikroE implementation.
 
    //Enable PORTA and PORTB peripheral clocks and PORTE for ENET_1588_CLKIN
    SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTE_MASK;
 
    //Configure RMII0_RXER (PTA5)
    PORTA->PCR[5] = PORT_PCR_MUX(4) | PORT_PCR_PE_MASK;
    //Configure RMII0_RXD1 (PTA12)
    PORTA->PCR[12] = PORT_PCR_MUX(4);
    //Configure RMII0_RXD0 (PTA13)
    PORTA->PCR[13] = PORT_PCR_MUX(4);
    //Configure RMII0_CRS_DV (PTA14)
    PORTA->PCR[14] = PORT_PCR_MUX(4);
    //Configure RMII0_TXEN (PTA15)
    PORTA->PCR[15] = PORT_PCR_MUX(4);
    //Configure RMII0_TXD0 (PTA16)
    PORTA->PCR[16] = PORT_PCR_MUX(4);
    //Configure RMII0_TXD1 (PTA17)
    PORTA->PCR[17] = PORT_PCR_MUX(4);
 
    //Configure RMII0_MDIO (PTB0)
    PORTB->PCR[0] = PORT_PCR_MUX(4) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
    //Configure RMII0_MDC (PTB1)
    PORTB->PCR[1] = PORT_PCR_MUX(4);
    
    //Configure ENET_1588_CLKIN (PTE26)
    PORTE->PCR[26] = PORT_PCR_MUX(2);
 
    //Select RMII clock source (ENET_1588_CLKIN) and IEEE 1588 timestamp clock source (ENET_1588_CLKIN)
    SIM->SOPT2 |= SIM_SOPT2_RMIISRC_MASK | SIM_SOPT2_TIMESRC_MASK;
}
 
 // ethernet
 // middleware
 
#ifdef __cplusplus
}
#endif
 
#endif // _HW_ETH_H_
// ------------------------------------------------------------------------- END