PORT Register Masks

Macros
#define	PORTA_BASE   (0x40049000u)
#define	PORTA   ((PORT_Type *)PORTA_BASE)
#define	PORTB_BASE   (0x4004A000u)
#define	PORTB   ((PORT_Type *)PORTB_BASE)
#define	PORTC_BASE   (0x4004B000u)
#define	PORTC   ((PORT_Type *)PORTC_BASE)
#define	PORTD_BASE   (0x4004C000u)
#define	PORTD   ((PORT_Type *)PORTD_BASE)
#define	PORTE_BASE   (0x4004D000u)
#define	PORTE   ((PORT_Type *)PORTE_BASE)
#define	PORT_BASE_ADDRS   { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
#define	PORT_BASE_PTRS   { PORTA, PORTB, PORTC, PORTD, PORTE }
#define	PORT_IRQS   { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
#define	PORT_PCR_COUNT   (32U)
#define	PORT_PCR_COUNT   (32U)
#define	PORT_PCR_COUNT   (32U)
#define	PORT_PCR_COUNT   (32U)

PCR - Pin Control Register n
#define	PORT_PCR_PS_MASK   (0x1U)
#define	PORT_PCR_PS_SHIFT   (0U)
#define	PORT_PCR_PS(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
#define	PORT_PCR_PE_MASK   (0x2U)
#define	PORT_PCR_PE_SHIFT   (1U)
#define	PORT_PCR_PE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
#define	PORT_PCR_SRE_MASK   (0x4U)
#define	PORT_PCR_SRE_SHIFT   (2U)
#define	PORT_PCR_SRE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
#define	PORT_PCR_PFE_MASK   (0x10U)
#define	PORT_PCR_PFE_SHIFT   (4U)
#define	PORT_PCR_PFE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
#define	PORT_PCR_ODE_MASK   (0x20U)
#define	PORT_PCR_ODE_SHIFT   (5U)
#define	PORT_PCR_ODE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
#define	PORT_PCR_DSE_MASK   (0x40U)
#define	PORT_PCR_DSE_SHIFT   (6U)
#define	PORT_PCR_DSE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
#define	PORT_PCR_MUX_MASK   (0x700U)
#define	PORT_PCR_MUX_SHIFT   (8U)
#define	PORT_PCR_MUX(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
#define	PORT_PCR_LK_MASK   (0x8000U)
#define	PORT_PCR_LK_SHIFT   (15U)
#define	PORT_PCR_LK(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
#define	PORT_PCR_IRQC_MASK   (0xF0000U)
#define	PORT_PCR_IRQC_SHIFT   (16U)
#define	PORT_PCR_IRQC(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
#define	PORT_PCR_ISF_MASK   (0x1000000U)
#define	PORT_PCR_ISF_SHIFT   (24U)
#define	PORT_PCR_ISF(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
#define	PORT_PCR_PS_MASK   0x1u
#define	PORT_PCR_PS_SHIFT   0
#define	PORT_PCR_PE_MASK   0x2u
#define	PORT_PCR_PE_SHIFT   1
#define	PORT_PCR_SRE_MASK   0x4u
#define	PORT_PCR_SRE_SHIFT   2
#define	PORT_PCR_PFE_MASK   0x10u
#define	PORT_PCR_PFE_SHIFT   4
#define	PORT_PCR_ODE_MASK   0x20u
#define	PORT_PCR_ODE_SHIFT   5
#define	PORT_PCR_DSE_MASK   0x40u
#define	PORT_PCR_DSE_SHIFT   6
#define	PORT_PCR_MUX_MASK   0x700u
#define	PORT_PCR_MUX_SHIFT   8
#define	PORT_PCR_MUX(x)   (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
#define	PORT_PCR_LK_MASK   0x8000u
#define	PORT_PCR_LK_SHIFT   15
#define	PORT_PCR_IRQC_MASK   0xF0000u
#define	PORT_PCR_IRQC_SHIFT   16
#define	PORT_PCR_IRQC(x)   (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
#define	PORT_PCR_ISF_MASK   0x1000000u
#define	PORT_PCR_ISF_SHIFT   24
#define	PORT_PCR_PS_MASK   (0x1U)
#define	PORT_PCR_PS_SHIFT   (0U)
#define	PORT_PCR_PS(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
#define	PORT_PCR_PE_MASK   (0x2U)
#define	PORT_PCR_PE_SHIFT   (1U)
#define	PORT_PCR_PE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
#define	PORT_PCR_SRE_MASK   (0x4U)
#define	PORT_PCR_SRE_SHIFT   (2U)
#define	PORT_PCR_SRE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
#define	PORT_PCR_PFE_MASK   (0x10U)
#define	PORT_PCR_PFE_SHIFT   (4U)
#define	PORT_PCR_PFE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
#define	PORT_PCR_ODE_MASK   (0x20U)
#define	PORT_PCR_ODE_SHIFT   (5U)
#define	PORT_PCR_ODE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
#define	PORT_PCR_DSE_MASK   (0x40U)
#define	PORT_PCR_DSE_SHIFT   (6U)
#define	PORT_PCR_DSE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
#define	PORT_PCR_MUX_MASK   (0x700U)
#define	PORT_PCR_MUX_SHIFT   (8U)
#define	PORT_PCR_MUX(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
#define	PORT_PCR_LK_MASK   (0x8000U)
#define	PORT_PCR_LK_SHIFT   (15U)
#define	PORT_PCR_LK(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
#define	PORT_PCR_IRQC_MASK   (0xF0000U)
#define	PORT_PCR_IRQC_SHIFT   (16U)
#define	PORT_PCR_IRQC(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
#define	PORT_PCR_ISF_MASK   (0x1000000U)
#define	PORT_PCR_ISF_SHIFT   (24U)
#define	PORT_PCR_ISF(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
#define	PORT_PCR_PS_MASK   (0x1U)
#define	PORT_PCR_PS_SHIFT   (0U)
#define	PORT_PCR_PS(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
#define	PORT_PCR_PE_MASK   (0x2U)
#define	PORT_PCR_PE_SHIFT   (1U)
#define	PORT_PCR_PE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
#define	PORT_PCR_SRE_MASK   (0x4U)
#define	PORT_PCR_SRE_SHIFT   (2U)
#define	PORT_PCR_SRE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
#define	PORT_PCR_PFE_MASK   (0x10U)
#define	PORT_PCR_PFE_SHIFT   (4U)
#define	PORT_PCR_PFE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
#define	PORT_PCR_ODE_MASK   (0x20U)
#define	PORT_PCR_ODE_SHIFT   (5U)
#define	PORT_PCR_ODE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
#define	PORT_PCR_DSE_MASK   (0x40U)
#define	PORT_PCR_DSE_SHIFT   (6U)
#define	PORT_PCR_DSE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
#define	PORT_PCR_MUX_MASK   (0x700U)
#define	PORT_PCR_MUX_SHIFT   (8U)
#define	PORT_PCR_MUX(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
#define	PORT_PCR_LK_MASK   (0x8000U)
#define	PORT_PCR_LK_SHIFT   (15U)
#define	PORT_PCR_LK(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
#define	PORT_PCR_IRQC_MASK   (0xF0000U)
#define	PORT_PCR_IRQC_SHIFT   (16U)
#define	PORT_PCR_IRQC(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
#define	PORT_PCR_ISF_MASK   (0x1000000U)
#define	PORT_PCR_ISF_SHIFT   (24U)
#define	PORT_PCR_ISF(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
#define	PORT_PCR_PS_MASK   (0x1U)
#define	PORT_PCR_PS_SHIFT   (0U)
#define	PORT_PCR_PS(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
#define	PORT_PCR_PE_MASK   (0x2U)
#define	PORT_PCR_PE_SHIFT   (1U)
#define	PORT_PCR_PE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
#define	PORT_PCR_SRE_MASK   (0x4U)
#define	PORT_PCR_SRE_SHIFT   (2U)
#define	PORT_PCR_SRE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
#define	PORT_PCR_PFE_MASK   (0x10U)
#define	PORT_PCR_PFE_SHIFT   (4U)
#define	PORT_PCR_PFE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
#define	PORT_PCR_ODE_MASK   (0x20U)
#define	PORT_PCR_ODE_SHIFT   (5U)
#define	PORT_PCR_ODE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
#define	PORT_PCR_DSE_MASK   (0x40U)
#define	PORT_PCR_DSE_SHIFT   (6U)
#define	PORT_PCR_DSE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
#define	PORT_PCR_MUX_MASK   (0x700U)
#define	PORT_PCR_MUX_SHIFT   (8U)
#define	PORT_PCR_MUX(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
#define	PORT_PCR_LK_MASK   (0x8000U)
#define	PORT_PCR_LK_SHIFT   (15U)
#define	PORT_PCR_LK(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
#define	PORT_PCR_IRQC_MASK   (0xF0000U)
#define	PORT_PCR_IRQC_SHIFT   (16U)
#define	PORT_PCR_IRQC(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
#define	PORT_PCR_ISF_MASK   (0x1000000U)
#define	PORT_PCR_ISF_SHIFT   (24U)
#define	PORT_PCR_ISF(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
#define	PORT_PCR_PS_MASK   (0x1U)
#define	PORT_PCR_PS_SHIFT   (0U)
#define	PORT_PCR_PS(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
#define	PORT_PCR_PE_MASK   (0x2U)
#define	PORT_PCR_PE_SHIFT   (1U)
#define	PORT_PCR_PE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
#define	PORT_PCR_SRE_MASK   (0x4U)
#define	PORT_PCR_SRE_SHIFT   (2U)
#define	PORT_PCR_SRE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
#define	PORT_PCR_PFE_MASK   (0x10U)
#define	PORT_PCR_PFE_SHIFT   (4U)
#define	PORT_PCR_PFE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
#define	PORT_PCR_ODE_MASK   (0x20U)
#define	PORT_PCR_ODE_SHIFT   (5U)
#define	PORT_PCR_ODE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
#define	PORT_PCR_DSE_MASK   (0x40U)
#define	PORT_PCR_DSE_SHIFT   (6U)
#define	PORT_PCR_DSE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
#define	PORT_PCR_MUX_MASK   (0xF00U)
#define	PORT_PCR_MUX_SHIFT   (8U)
#define	PORT_PCR_MUX(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
#define	PORT_PCR_LK_MASK   (0x8000U)
#define	PORT_PCR_LK_SHIFT   (15U)
#define	PORT_PCR_LK(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
#define	PORT_PCR_IRQC_MASK   (0xF0000U)
#define	PORT_PCR_IRQC_SHIFT   (16U)
#define	PORT_PCR_IRQC(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
#define	PORT_PCR_ISF_MASK   (0x1000000U)
#define	PORT_PCR_ISF_SHIFT   (24U)
#define	PORT_PCR_ISF(x)   (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)

PCR - Pin Control Register n
#define	PORT_PCR_COUNT   (32U)

GPCLR - Global Pin Control Low Register
#define	PORT_GPCLR_GPWD_MASK   (0xFFFFU)
#define	PORT_GPCLR_GPWD_SHIFT   (0U)
#define	PORT_GPCLR_GPWD(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
#define	PORT_GPCLR_GPWE_MASK   (0xFFFF0000U)
#define	PORT_GPCLR_GPWE_SHIFT   (16U)
#define	PORT_GPCLR_GPWE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
#define	PORT_GPCLR_GPWD_MASK   0xFFFFu
#define	PORT_GPCLR_GPWD_SHIFT   0
#define	PORT_GPCLR_GPWD(x)   (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
#define	PORT_GPCLR_GPWE_MASK   0xFFFF0000u
#define	PORT_GPCLR_GPWE_SHIFT   16
#define	PORT_GPCLR_GPWE(x)   (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
#define	PORT_GPCLR_GPWD_MASK   (0xFFFFU)
#define	PORT_GPCLR_GPWD_SHIFT   (0U)
#define	PORT_GPCLR_GPWD(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
#define	PORT_GPCLR_GPWE_MASK   (0xFFFF0000U)
#define	PORT_GPCLR_GPWE_SHIFT   (16U)
#define	PORT_GPCLR_GPWE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
#define	PORT_GPCLR_GPWD_MASK   (0xFFFFU)
#define	PORT_GPCLR_GPWD_SHIFT   (0U)
#define	PORT_GPCLR_GPWD(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
#define	PORT_GPCLR_GPWE_MASK   (0xFFFF0000U)
#define	PORT_GPCLR_GPWE_SHIFT   (16U)
#define	PORT_GPCLR_GPWE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
#define	PORT_GPCLR_GPWD_MASK   (0xFFFFU)
#define	PORT_GPCLR_GPWD_SHIFT   (0U)
#define	PORT_GPCLR_GPWD(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
#define	PORT_GPCLR_GPWE_MASK   (0xFFFF0000U)
#define	PORT_GPCLR_GPWE_SHIFT   (16U)
#define	PORT_GPCLR_GPWE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
#define	PORT_GPCLR_GPWD_MASK   (0xFFFFU)
#define	PORT_GPCLR_GPWD_SHIFT   (0U)
#define	PORT_GPCLR_GPWD(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
#define	PORT_GPCLR_GPWE_MASK   (0xFFFF0000U)
#define	PORT_GPCLR_GPWE_SHIFT   (16U)
#define	PORT_GPCLR_GPWE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)

GPCHR - Global Pin Control High Register
#define	PORT_GPCHR_GPWD_MASK   (0xFFFFU)
#define	PORT_GPCHR_GPWD_SHIFT   (0U)
#define	PORT_GPCHR_GPWD(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
#define	PORT_GPCHR_GPWE_MASK   (0xFFFF0000U)
#define	PORT_GPCHR_GPWE_SHIFT   (16U)
#define	PORT_GPCHR_GPWE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
#define	PORT_GPCHR_GPWD_MASK   0xFFFFu
#define	PORT_GPCHR_GPWD_SHIFT   0
#define	PORT_GPCHR_GPWD(x)   (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
#define	PORT_GPCHR_GPWE_MASK   0xFFFF0000u
#define	PORT_GPCHR_GPWE_SHIFT   16
#define	PORT_GPCHR_GPWE(x)   (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
#define	PORT_GPCHR_GPWD_MASK   (0xFFFFU)
#define	PORT_GPCHR_GPWD_SHIFT   (0U)
#define	PORT_GPCHR_GPWD(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
#define	PORT_GPCHR_GPWE_MASK   (0xFFFF0000U)
#define	PORT_GPCHR_GPWE_SHIFT   (16U)
#define	PORT_GPCHR_GPWE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
#define	PORT_GPCHR_GPWD_MASK   (0xFFFFU)
#define	PORT_GPCHR_GPWD_SHIFT   (0U)
#define	PORT_GPCHR_GPWD(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
#define	PORT_GPCHR_GPWE_MASK   (0xFFFF0000U)
#define	PORT_GPCHR_GPWE_SHIFT   (16U)
#define	PORT_GPCHR_GPWE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
#define	PORT_GPCHR_GPWD_MASK   (0xFFFFU)
#define	PORT_GPCHR_GPWD_SHIFT   (0U)
#define	PORT_GPCHR_GPWD(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
#define	PORT_GPCHR_GPWE_MASK   (0xFFFF0000U)
#define	PORT_GPCHR_GPWE_SHIFT   (16U)
#define	PORT_GPCHR_GPWE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
#define	PORT_GPCHR_GPWD_MASK   (0xFFFFU)
#define	PORT_GPCHR_GPWD_SHIFT   (0U)
#define	PORT_GPCHR_GPWD(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
#define	PORT_GPCHR_GPWE_MASK   (0xFFFF0000U)
#define	PORT_GPCHR_GPWE_SHIFT   (16U)
#define	PORT_GPCHR_GPWE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)

ISFR - Interrupt Status Flag Register
#define	PORT_ISFR_ISF_MASK   (0xFFFFFFFFU)
#define	PORT_ISFR_ISF_SHIFT   (0U)
#define	PORT_ISFR_ISF(x)   (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
#define	PORT_ISFR_ISF_MASK   0xFFFFFFFFu
#define	PORT_ISFR_ISF_SHIFT   0
#define	PORT_ISFR_ISF(x)   (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
#define	PORT_ISFR_ISF_MASK   (0xFFFFFFFFU)
#define	PORT_ISFR_ISF_SHIFT   (0U)
#define	PORT_ISFR_ISF(x)   (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
#define	PORT_ISFR_ISF_MASK   (0xFFFFFFFFU)
#define	PORT_ISFR_ISF_SHIFT   (0U)
#define	PORT_ISFR_ISF(x)   (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
#define	PORT_ISFR_ISF_MASK   (0xFFFFFFFFU)
#define	PORT_ISFR_ISF_SHIFT   (0U)
#define	PORT_ISFR_ISF(x)   (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
#define	PORT_ISFR_ISF_MASK   (0xFFFFFFFFU)
#define	PORT_ISFR_ISF_SHIFT   (0U)
#define	PORT_ISFR_ISF(x)   (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)

DFER - Digital Filter Enable Register
#define	PORT_DFER_DFE_MASK   (0xFFFFFFFFU)
#define	PORT_DFER_DFE_SHIFT   (0U)
#define	PORT_DFER_DFE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
#define	PORT_DFER_DFE_MASK   0xFFFFFFFFu
#define	PORT_DFER_DFE_SHIFT   0
#define	PORT_DFER_DFE(x)   (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
#define	PORT_DFER_DFE_MASK   (0xFFFFFFFFU)
#define	PORT_DFER_DFE_SHIFT   (0U)
#define	PORT_DFER_DFE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
#define	PORT_DFER_DFE_MASK   (0xFFFFFFFFU)
#define	PORT_DFER_DFE_SHIFT   (0U)
#define	PORT_DFER_DFE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
#define	PORT_DFER_DFE_MASK   (0xFFFFFFFFU)
#define	PORT_DFER_DFE_SHIFT   (0U)
#define	PORT_DFER_DFE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
#define	PORT_DFER_DFE_MASK   (0xFFFFFFFFU)
#define	PORT_DFER_DFE_SHIFT   (0U)
#define	PORT_DFER_DFE(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)

DFCR - Digital Filter Clock Register
#define	PORT_DFCR_CS_MASK   (0x1U)
#define	PORT_DFCR_CS_SHIFT   (0U)
#define	PORT_DFCR_CS(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
#define	PORT_DFCR_CS_MASK   0x1u
#define	PORT_DFCR_CS_SHIFT   0
#define	PORT_DFCR_CS_MASK   (0x1U)
#define	PORT_DFCR_CS_SHIFT   (0U)
#define	PORT_DFCR_CS(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
#define	PORT_DFCR_CS_MASK   (0x1U)
#define	PORT_DFCR_CS_SHIFT   (0U)
#define	PORT_DFCR_CS(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
#define	PORT_DFCR_CS_MASK   (0x1U)
#define	PORT_DFCR_CS_SHIFT   (0U)
#define	PORT_DFCR_CS(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
#define	PORT_DFCR_CS_MASK   (0x1U)
#define	PORT_DFCR_CS_SHIFT   (0U)
#define	PORT_DFCR_CS(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)

DFWR - Digital Filter Width Register
#define	PORT_DFWR_FILT_MASK   (0x1FU)
#define	PORT_DFWR_FILT_SHIFT   (0U)
#define	PORT_DFWR_FILT(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
#define	PORT_DFWR_FILT_MASK   0x1Fu
#define	PORT_DFWR_FILT_SHIFT   0
#define	PORT_DFWR_FILT(x)   (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
#define	PORT_DFWR_FILT_MASK   (0x1FU)
#define	PORT_DFWR_FILT_SHIFT   (0U)
#define	PORT_DFWR_FILT(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
#define	PORT_DFWR_FILT_MASK   (0x1FU)
#define	PORT_DFWR_FILT_SHIFT   (0U)
#define	PORT_DFWR_FILT(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
#define	PORT_DFWR_FILT_MASK   (0x1FU)
#define	PORT_DFWR_FILT_SHIFT   (0U)
#define	PORT_DFWR_FILT(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
#define	PORT_DFWR_FILT_MASK   (0x1FU)
#define	PORT_DFWR_FILT_SHIFT   (0U)
#define	PORT_DFWR_FILT(x)   (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)

Macro Definition Documentation

PORT_BASE_ADDRS

#define PORT_BASE_ADDRS   { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }

Array initializer of PORT peripheral base addresses

PORT_BASE_PTRS

#define PORT_BASE_PTRS   { PORTA, PORTB, PORTC, PORTD, PORTE }

Array initializer of PORT peripheral base pointers

PORT_DFCR_CS [1/5]

#define PORT_DFCR_CS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)

CS - Clock Source 0b0..Digital filters are clocked by the bus clock. 0b1..Digital filters are clocked by the 1 kHz LPO clock.

CS - Clock Source 0b0..Digital filters are clocked by the bus clock. 0b1..Digital filters are clocked by the LPO clock.

PORT_DFCR_CS [2/5]

#define PORT_DFCR_CS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)

CS - Clock Source 0b0..Digital filters are clocked by the bus clock. 0b1..Digital filters are clocked by the 1 kHz LPO clock.

CS - Clock Source 0b0..Digital filters are clocked by the bus clock. 0b1..Digital filters are clocked by the LPO clock.

PORT_DFCR_CS [3/5]

#define PORT_DFCR_CS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)

CS - Clock Source 0b0..Digital filters are clocked by the bus clock. 0b1..Digital filters are clocked by the LPO clock.

PORT_DFCR_CS [4/5]

#define PORT_DFCR_CS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)

CS - Clock Source 0b0..Digital filters are clocked by the bus clock. 0b1..Digital filters are clocked by the LPO clock.

PORT_DFCR_CS [5/5]

#define PORT_DFCR_CS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)

CS - Clock Source 0b0..Digital filters are clocked by the bus clock. 0b1..Digital filters are clocked by the LPO clock.

PORT_DFER_DFE [1/6]

#define PORT_DFER_DFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)

DFE - Digital Filter Enable 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_DFER_DFE [2/6]

#define PORT_DFER_DFE

(

x

)

(((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)

DFE - Digital Filter Enable 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_DFER_DFE [3/6]

#define PORT_DFER_DFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)

DFE - Digital Filter Enable 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_DFER_DFE [4/6]

#define PORT_DFER_DFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)

DFE - Digital Filter Enable 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_DFER_DFE [5/6]

#define PORT_DFER_DFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)

DFE - Digital Filter Enable 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_DFER_DFE [6/6]

#define PORT_DFER_DFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)

DFE - Digital Filter Enable 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_GPCHR_GPWE [1/6]

#define PORT_GPCHR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCHR_GPWE [2/6]

#define PORT_GPCHR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCHR_GPWE [3/6]

#define PORT_GPCHR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCHR_GPWE [4/6]

#define PORT_GPCHR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCHR_GPWE [5/6]

#define PORT_GPCHR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCHR_GPWE [6/6]

#define PORT_GPCHR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCLR_GPWE [1/6]

#define PORT_GPCLR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCLR_GPWE [2/6]

#define PORT_GPCLR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCLR_GPWE [3/6]

#define PORT_GPCLR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCLR_GPWE [4/6]

#define PORT_GPCLR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCLR_GPWE [5/6]

#define PORT_GPCLR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_GPCLR_GPWE [6/6]

#define PORT_GPCLR_GPWE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)

GPWE - Global Pin Write Enable 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.

PORT_IRQS

#define PORT_IRQS   { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }

Interrupt vectors for the PORT peripheral type

PORT_ISFR_ISF [1/6]

#define PORT_ISFR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)

ISF - Interrupt Status Flag 0b00000000000000000000000000000000..Configured interrupt is not detected. 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_ISFR_ISF [2/6]

#define PORT_ISFR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)

ISF - Interrupt Status Flag 0b00000000000000000000000000000000..Configured interrupt is not detected. 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_ISFR_ISF [3/6]

#define PORT_ISFR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)

ISF - Interrupt Status Flag 0b00000000000000000000000000000000..Configured interrupt is not detected. 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_ISFR_ISF [4/6]

#define PORT_ISFR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)

ISF - Interrupt Status Flag 0b00000000000000000000000000000000..Configured interrupt is not detected. 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_ISFR_ISF [5/6]

#define PORT_ISFR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)

ISF - Interrupt Status Flag 0b00000000000000000000000000000000..Configured interrupt is not detected. 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_ISFR_ISF [6/6]

#define PORT_ISFR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)

ISF - Interrupt Status Flag 0b00000000000000000000000000000000..Configured interrupt is not detected. 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_PCR_DSE [1/5]

#define PORT_PCR_DSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)

DSE - Drive Strength Enable 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

PORT_PCR_DSE [2/5]

#define PORT_PCR_DSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)

DSE - Drive Strength Enable 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

PORT_PCR_DSE [3/5]

#define PORT_PCR_DSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)

DSE - Drive Strength Enable 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

PORT_PCR_DSE [4/5]

#define PORT_PCR_DSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)

DSE - Drive Strength Enable 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

PORT_PCR_DSE [5/5]

#define PORT_PCR_DSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)

DSE - Drive Strength Enable 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.

PORT_PCR_IRQC [1/6]

#define PORT_PCR_IRQC

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)

IRQC - Interrupt Configuration 0b0000..Interrupt/DMA request disabled. 0b0001..DMA request on rising edge. 0b0010..DMA request on falling edge. 0b0011..DMA request on either edge. 0b1000..Interrupt when logic 0. 0b1001..Interrupt on rising-edge. 0b1010..Interrupt on falling-edge. 0b1011..Interrupt on either edge. 0b1100..Interrupt when logic 1.

IRQC - Interrupt Configuration 0b0000..Interrupt Status Flag (ISF) is disabled. 0b0001..ISF flag and DMA request on rising edge. 0b0010..ISF flag and DMA request on falling edge. 0b0011..ISF flag and DMA request on either edge. 0b0100..Reserved. 0b0101..Reserved. 0b0110..Reserved. 0b0111..Reserved. 0b1000..ISF flag and Interrupt when logic 0. 0b1001..ISF flag and Interrupt on rising-edge. 0b1010..ISF flag and Interrupt on falling-edge. 0b1011..ISF flag and Interrupt on either edge. 0b1100..ISF flag and Interrupt when logic 1. 0b1101..Reserved. 0b1110..Reserved. 0b1111..Reserved.

PORT_PCR_IRQC [2/6]

#define PORT_PCR_IRQC

(

x

)

(((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)

IRQC - Interrupt Configuration 0b0000..Interrupt/DMA request disabled. 0b0001..DMA request on rising edge. 0b0010..DMA request on falling edge. 0b0011..DMA request on either edge. 0b1000..Interrupt when logic 0. 0b1001..Interrupt on rising-edge. 0b1010..Interrupt on falling-edge. 0b1011..Interrupt on either edge. 0b1100..Interrupt when logic 1.

IRQC - Interrupt Configuration 0b0000..Interrupt Status Flag (ISF) is disabled. 0b0001..ISF flag and DMA request on rising edge. 0b0010..ISF flag and DMA request on falling edge. 0b0011..ISF flag and DMA request on either edge. 0b0100..Reserved. 0b0101..Reserved. 0b0110..Reserved. 0b0111..Reserved. 0b1000..ISF flag and Interrupt when logic 0. 0b1001..ISF flag and Interrupt on rising-edge. 0b1010..ISF flag and Interrupt on falling-edge. 0b1011..ISF flag and Interrupt on either edge. 0b1100..ISF flag and Interrupt when logic 1. 0b1101..Reserved. 0b1110..Reserved. 0b1111..Reserved.

PORT_PCR_IRQC [3/6]

#define PORT_PCR_IRQC

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)

IRQC - Interrupt Configuration 0b0000..Interrupt/DMA request disabled. 0b0001..DMA request on rising edge. 0b0010..DMA request on falling edge. 0b0011..DMA request on either edge. 0b1000..Interrupt when logic 0. 0b1001..Interrupt on rising-edge. 0b1010..Interrupt on falling-edge. 0b1011..Interrupt on either edge. 0b1100..Interrupt when logic 1.

IRQC - Interrupt Configuration 0b0000..Interrupt Status Flag (ISF) is disabled. 0b0001..ISF flag and DMA request on rising edge. 0b0010..ISF flag and DMA request on falling edge. 0b0011..ISF flag and DMA request on either edge. 0b0100..Reserved. 0b0101..Reserved. 0b0110..Reserved. 0b0111..Reserved. 0b1000..ISF flag and Interrupt when logic 0. 0b1001..ISF flag and Interrupt on rising-edge. 0b1010..ISF flag and Interrupt on falling-edge. 0b1011..ISF flag and Interrupt on either edge. 0b1100..ISF flag and Interrupt when logic 1. 0b1101..Reserved. 0b1110..Reserved. 0b1111..Reserved.

PORT_PCR_IRQC [4/6]

#define PORT_PCR_IRQC

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)

IRQC - Interrupt Configuration 0b0000..Interrupt Status Flag (ISF) is disabled. 0b0001..ISF flag and DMA request on rising edge. 0b0010..ISF flag and DMA request on falling edge. 0b0011..ISF flag and DMA request on either edge. 0b0100..Reserved. 0b0101..Reserved. 0b0110..Reserved. 0b0111..Reserved. 0b1000..ISF flag and Interrupt when logic 0. 0b1001..ISF flag and Interrupt on rising-edge. 0b1010..ISF flag and Interrupt on falling-edge. 0b1011..ISF flag and Interrupt on either edge. 0b1100..ISF flag and Interrupt when logic 1. 0b1101..Reserved. 0b1110..Reserved. 0b1111..Reserved.

PORT_PCR_IRQC [5/6]

#define PORT_PCR_IRQC

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)

IRQC - Interrupt Configuration 0b0000..Interrupt Status Flag (ISF) is disabled. 0b0001..ISF flag and DMA request on rising edge. 0b0010..ISF flag and DMA request on falling edge. 0b0011..ISF flag and DMA request on either edge. 0b0100..Reserved. 0b0101..Reserved. 0b0110..Reserved. 0b0111..Reserved. 0b1000..ISF flag and Interrupt when logic 0. 0b1001..ISF flag and Interrupt on rising-edge. 0b1010..ISF flag and Interrupt on falling-edge. 0b1011..ISF flag and Interrupt on either edge. 0b1100..ISF flag and Interrupt when logic 1. 0b1101..Reserved. 0b1110..Reserved. 0b1111..Reserved.

PORT_PCR_IRQC [6/6]

#define PORT_PCR_IRQC

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)

IRQC - Interrupt Configuration 0b0000..Interrupt Status Flag (ISF) is disabled. 0b0001..ISF flag and DMA request on rising edge. 0b0010..ISF flag and DMA request on falling edge. 0b0011..ISF flag and DMA request on either edge. 0b0100..Reserved. 0b0101..Reserved. 0b0110..Reserved. 0b0111..Reserved. 0b1000..ISF flag and Interrupt when logic 0. 0b1001..ISF flag and Interrupt on rising-edge. 0b1010..ISF flag and Interrupt on falling-edge. 0b1011..ISF flag and Interrupt on either edge. 0b1100..ISF flag and Interrupt when logic 1. 0b1101..Reserved. 0b1110..Reserved. 0b1111..Reserved.

PORT_PCR_ISF [1/5]

#define PORT_PCR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)

ISF - Interrupt Status Flag 0b0..Configured interrupt is not detected. 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_PCR_ISF [2/5]

#define PORT_PCR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)

ISF - Interrupt Status Flag 0b0..Configured interrupt is not detected. 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_PCR_ISF [3/5]

#define PORT_PCR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)

ISF - Interrupt Status Flag 0b0..Configured interrupt is not detected. 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_PCR_ISF [4/5]

#define PORT_PCR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)

ISF - Interrupt Status Flag 0b0..Configured interrupt is not detected. 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_PCR_ISF [5/5]

#define PORT_PCR_ISF

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)

ISF - Interrupt Status Flag 0b0..Configured interrupt is not detected. 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

PORT_PCR_LK [1/5]

#define PORT_PCR_LK

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)

LK - Lock Register 0b0..Pin Control Register fields [15:0] are not locked. 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

PORT_PCR_LK [2/5]

#define PORT_PCR_LK

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)

LK - Lock Register 0b0..Pin Control Register fields [15:0] are not locked. 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

PORT_PCR_LK [3/5]

#define PORT_PCR_LK

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)

LK - Lock Register 0b0..Pin Control Register fields [15:0] are not locked. 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

PORT_PCR_LK [4/5]

#define PORT_PCR_LK

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)

LK - Lock Register 0b0..Pin Control Register fields [15:0] are not locked. 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

PORT_PCR_LK [5/5]

#define PORT_PCR_LK

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)

LK - Lock Register 0b0..Pin Control Register fields [15:0] are not locked. 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.

PORT_PCR_MUX [1/6]

#define PORT_PCR_MUX

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)

MUX - Pin Mux Control 0b000..Pin disabled (analog). 0b001..Alternative 1 (GPIO). 0b010..Alternative 2 (chip-specific). 0b011..Alternative 3 (chip-specific). 0b100..Alternative 4 (chip-specific). 0b101..Alternative 5 (chip-specific). 0b110..Alternative 6 (chip-specific). 0b111..Alternative 7 (chip-specific).

MUX - Pin Mux Control 0b0000..Pin disabled. 0b0001..Alternative 1 (GPIO). 0b0010..Alternative 2 (chip-specific). 0b0011..Alternative 3 (chip-specific). 0b0100..Alternative 4 (chip-specific). 0b0101..Alternative 5 (chip-specific). 0b0110..Alternative 6 (chip-specific). 0b0111..Alternative 7 (chip-specific). 0b1000..Alternative 8 (chip-specific). 0b1001..Alternative 9 (chip-specific). 0b1010..Alternative 10 (chip-specific). 0b1011..Alternative 11 (chip-specific). 0b1100..Alternative 12 (chip-specific). 0b1101..Alternative 13 (chip-specific). 0b1110..Alternative 14 (chip-specific). 0b1111..Alternative 15 (chip-specific).

PORT_PCR_MUX [2/6]

#define PORT_PCR_MUX

(

x

)

(((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)

MUX - Pin Mux Control 0b000..Pin disabled (analog). 0b001..Alternative 1 (GPIO). 0b010..Alternative 2 (chip-specific). 0b011..Alternative 3 (chip-specific). 0b100..Alternative 4 (chip-specific). 0b101..Alternative 5 (chip-specific). 0b110..Alternative 6 (chip-specific). 0b111..Alternative 7 (chip-specific).

MUX - Pin Mux Control 0b0000..Pin disabled. 0b0001..Alternative 1 (GPIO). 0b0010..Alternative 2 (chip-specific). 0b0011..Alternative 3 (chip-specific). 0b0100..Alternative 4 (chip-specific). 0b0101..Alternative 5 (chip-specific). 0b0110..Alternative 6 (chip-specific). 0b0111..Alternative 7 (chip-specific). 0b1000..Alternative 8 (chip-specific). 0b1001..Alternative 9 (chip-specific). 0b1010..Alternative 10 (chip-specific). 0b1011..Alternative 11 (chip-specific). 0b1100..Alternative 12 (chip-specific). 0b1101..Alternative 13 (chip-specific). 0b1110..Alternative 14 (chip-specific). 0b1111..Alternative 15 (chip-specific).

PORT_PCR_MUX [3/6]

#define PORT_PCR_MUX

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)

MUX - Pin Mux Control 0b000..Pin disabled (analog). 0b001..Alternative 1 (GPIO). 0b010..Alternative 2 (chip-specific). 0b011..Alternative 3 (chip-specific). 0b100..Alternative 4 (chip-specific). 0b101..Alternative 5 (chip-specific). 0b110..Alternative 6 (chip-specific). 0b111..Alternative 7 (chip-specific).

MUX - Pin Mux Control 0b0000..Pin disabled. 0b0001..Alternative 1 (GPIO). 0b0010..Alternative 2 (chip-specific). 0b0011..Alternative 3 (chip-specific). 0b0100..Alternative 4 (chip-specific). 0b0101..Alternative 5 (chip-specific). 0b0110..Alternative 6 (chip-specific). 0b0111..Alternative 7 (chip-specific). 0b1000..Alternative 8 (chip-specific). 0b1001..Alternative 9 (chip-specific). 0b1010..Alternative 10 (chip-specific). 0b1011..Alternative 11 (chip-specific). 0b1100..Alternative 12 (chip-specific). 0b1101..Alternative 13 (chip-specific). 0b1110..Alternative 14 (chip-specific). 0b1111..Alternative 15 (chip-specific).

PORT_PCR_MUX [4/6]

#define PORT_PCR_MUX

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)

MUX - Pin Mux Control 0b000..Pin disabled (analog). 0b001..Alternative 1 (GPIO). 0b010..Alternative 2 (chip-specific). 0b011..Alternative 3 (chip-specific). 0b100..Alternative 4 (chip-specific). 0b101..Alternative 5 (chip-specific). 0b110..Alternative 6 (chip-specific). 0b111..Alternative 7 (chip-specific).

MUX - Pin Mux Control 0b0000..Pin disabled. 0b0001..Alternative 1 (GPIO). 0b0010..Alternative 2 (chip-specific). 0b0011..Alternative 3 (chip-specific). 0b0100..Alternative 4 (chip-specific). 0b0101..Alternative 5 (chip-specific). 0b0110..Alternative 6 (chip-specific). 0b0111..Alternative 7 (chip-specific). 0b1000..Alternative 8 (chip-specific). 0b1001..Alternative 9 (chip-specific). 0b1010..Alternative 10 (chip-specific). 0b1011..Alternative 11 (chip-specific). 0b1100..Alternative 12 (chip-specific). 0b1101..Alternative 13 (chip-specific). 0b1110..Alternative 14 (chip-specific). 0b1111..Alternative 15 (chip-specific).

PORT_PCR_MUX [5/6]

#define PORT_PCR_MUX

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)

MUX - Pin Mux Control 0b000..Pin disabled (analog). 0b001..Alternative 1 (GPIO). 0b010..Alternative 2 (chip-specific). 0b011..Alternative 3 (chip-specific). 0b100..Alternative 4 (chip-specific). 0b101..Alternative 5 (chip-specific). 0b110..Alternative 6 (chip-specific). 0b111..Alternative 7 (chip-specific).

MUX - Pin Mux Control 0b0000..Pin disabled. 0b0001..Alternative 1 (GPIO). 0b0010..Alternative 2 (chip-specific). 0b0011..Alternative 3 (chip-specific). 0b0100..Alternative 4 (chip-specific). 0b0101..Alternative 5 (chip-specific). 0b0110..Alternative 6 (chip-specific). 0b0111..Alternative 7 (chip-specific). 0b1000..Alternative 8 (chip-specific). 0b1001..Alternative 9 (chip-specific). 0b1010..Alternative 10 (chip-specific). 0b1011..Alternative 11 (chip-specific). 0b1100..Alternative 12 (chip-specific). 0b1101..Alternative 13 (chip-specific). 0b1110..Alternative 14 (chip-specific). 0b1111..Alternative 15 (chip-specific).

PORT_PCR_MUX [6/6]

#define PORT_PCR_MUX

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)

MUX - Pin Mux Control 0b0000..Pin disabled. 0b0001..Alternative 1 (GPIO). 0b0010..Alternative 2 (chip-specific). 0b0011..Alternative 3 (chip-specific). 0b0100..Alternative 4 (chip-specific). 0b0101..Alternative 5 (chip-specific). 0b0110..Alternative 6 (chip-specific). 0b0111..Alternative 7 (chip-specific). 0b1000..Alternative 8 (chip-specific). 0b1001..Alternative 9 (chip-specific). 0b1010..Alternative 10 (chip-specific). 0b1011..Alternative 11 (chip-specific). 0b1100..Alternative 12 (chip-specific). 0b1101..Alternative 13 (chip-specific). 0b1110..Alternative 14 (chip-specific). 0b1111..Alternative 15 (chip-specific).

PORT_PCR_ODE [1/5]

#define PORT_PCR_ODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)

ODE - Open Drain Enable 0b0..Open drain output is disabled on the corresponding pin. 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

PORT_PCR_ODE [2/5]

#define PORT_PCR_ODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)

ODE - Open Drain Enable 0b0..Open drain output is disabled on the corresponding pin. 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

PORT_PCR_ODE [3/5]

#define PORT_PCR_ODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)

ODE - Open Drain Enable 0b0..Open drain output is disabled on the corresponding pin. 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

PORT_PCR_ODE [4/5]

#define PORT_PCR_ODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)

ODE - Open Drain Enable 0b0..Open drain output is disabled on the corresponding pin. 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

PORT_PCR_ODE [5/5]

#define PORT_PCR_ODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)

ODE - Open Drain Enable 0b0..Open drain output is disabled on the corresponding pin. 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.

PORT_PCR_PE [1/5]

#define PORT_PCR_PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)

PE - Pull Enable 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_PCR_PE [2/5]

#define PORT_PCR_PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)

PE - Pull Enable 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_PCR_PE [3/5]

#define PORT_PCR_PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)

PE - Pull Enable 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_PCR_PE [4/5]

#define PORT_PCR_PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)

PE - Pull Enable 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_PCR_PE [5/5]

#define PORT_PCR_PE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)

PE - Pull Enable 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.

PORT_PCR_PFE [1/5]

#define PORT_PCR_PFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)

PFE - Passive Filter Enable 0b0..Passive input filter is disabled on the corresponding pin. 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

PORT_PCR_PFE [2/5]

#define PORT_PCR_PFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)

PFE - Passive Filter Enable 0b0..Passive input filter is disabled on the corresponding pin. 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

PORT_PCR_PFE [3/5]

#define PORT_PCR_PFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)

PFE - Passive Filter Enable 0b0..Passive input filter is disabled on the corresponding pin. 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

PORT_PCR_PFE [4/5]

#define PORT_PCR_PFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)

PFE - Passive Filter Enable 0b0..Passive input filter is disabled on the corresponding pin. 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

PORT_PCR_PFE [5/5]

#define PORT_PCR_PFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)

PFE - Passive Filter Enable 0b0..Passive input filter is disabled on the corresponding pin. 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.

PORT_PCR_PS [1/5]

#define PORT_PCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)

PS - Pull Select 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

PORT_PCR_PS [2/5]

#define PORT_PCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)

PS - Pull Select 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

PORT_PCR_PS [3/5]

#define PORT_PCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)

PS - Pull Select 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

PORT_PCR_PS [4/5]

#define PORT_PCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)

PS - Pull Select 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

PORT_PCR_PS [5/5]

#define PORT_PCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)

PS - Pull Select 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.

PORT_PCR_SRE [1/5]

#define PORT_PCR_SRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)

SRE - Slew Rate Enable 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

PORT_PCR_SRE [2/5]

#define PORT_PCR_SRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)

SRE - Slew Rate Enable 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

PORT_PCR_SRE [3/5]

#define PORT_PCR_SRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)

SRE - Slew Rate Enable 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

PORT_PCR_SRE [4/5]

#define PORT_PCR_SRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)

SRE - Slew Rate Enable 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

PORT_PCR_SRE [5/5]

#define PORT_PCR_SRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)

SRE - Slew Rate Enable 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.

PORTA

#define PORTA   ((PORT_Type *)PORTA_BASE)

Peripheral PORTA base pointer

PORTA_BASE

#define PORTA_BASE   (0x40049000u)

Peripheral PORTA base address

PORTB

#define PORTB   ((PORT_Type *)PORTB_BASE)

Peripheral PORTB base pointer

PORTB_BASE

#define PORTB_BASE   (0x4004A000u)

Peripheral PORTB base address

PORTC

#define PORTC   ((PORT_Type *)PORTC_BASE)

Peripheral PORTC base pointer

PORTC_BASE

#define PORTC_BASE   (0x4004B000u)

Peripheral PORTC base address

PORTD

#define PORTD   ((PORT_Type *)PORTD_BASE)

Peripheral PORTD base pointer

PORTD_BASE

#define PORTD_BASE   (0x4004C000u)

Peripheral PORTD base address

PORTE

#define PORTE   ((PORT_Type *)PORTE_BASE)

Peripheral PORTE base pointer

PORTE_BASE

#define PORTE_BASE   (0x4004D000u)

Peripheral PORTE base address