mikroSDK Reference Manual
Macros
SIM Register Masks
Mapping Information » Device Peripheral Access Layer » ADC Peripheral Access Layer » AIPS Peripheral Access Layer » AXBS Peripheral Access Layer » CAN Peripheral Access Layer » CAU Peripheral Access Layer » CMP Peripheral Access Layer » CMT Peripheral Access Layer » CRC Peripheral Access Layer » DAC Peripheral Access Layer » DMA Peripheral Access Layer » DMAMUX Peripheral Access Layer » ENET Peripheral Access Layer » EWM Peripheral Access Layer » FB Peripheral Access Layer » FMC Peripheral Access Layer » FTFL Peripheral Access Layer » FTM Peripheral Access Layer » GPIO Peripheral Access Layer » I2C Peripheral Access Layer » I2S Peripheral Access Layer » LLWU Peripheral Access Layer » LPTMR Peripheral Access Layer » MCG Peripheral Access Layer » MCM Peripheral Access Layer » NV Peripheral Access Layer » OSC Peripheral Access Layer » PDB Peripheral Access Layer » PIT Peripheral Access Layer » PMC Peripheral Access Layer » PORT Peripheral Access Layer » RCM Peripheral Access Layer » RFSYS Peripheral Access Layer » RFVBAT Peripheral Access Layer » RNG Peripheral Access Layer » RTC Peripheral Access Layer » SDHC Peripheral Access Layer » SIM Peripheral Access Layer

Macros

#define SIM_BASE   (0x40047000u)
 
#define SIM   ((SIM_Type *)SIM_BASE)
 
#define SIM_BASE_ADDRS   { SIM_BASE }
 
#define SIM_BASE_PTRS   { SIM }
 
#define SIM_SOPT1_MS_MASK   0x800000u
 
#define SIM_SOPT1_MS_SHIFT   23
 
#define SIM_SOPT1_USBSTBY_MASK   0x40000000u
 
#define SIM_SOPT1_USBSTBY_SHIFT   30
 
#define SIM_SOPT2_MCGCLKSEL_MASK   0x1u
 
#define SIM_SOPT2_MCGCLKSEL_SHIFT   0
 
#define SIM_SOPT2_CMTUARTPAD_MASK   0x800u
 
#define SIM_SOPT2_CMTUARTPAD_SHIFT   11
 
#define SIM_SOPT2_I2SSRC_MASK   0x3000000u
 
#define SIM_SOPT2_I2SSRC_SHIFT   24
 
#define SIM_SOPT2_I2SSRC(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_I2SSRC_SHIFT))&SIM_SOPT2_I2SSRC_MASK)
 
#define SIM_SOPT5_UARTTXSRC_MASK   0x30u
 
#define SIM_SOPT5_UARTTXSRC_SHIFT   4
 
#define SIM_SOPT5_UARTTXSRC(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UARTTXSRC_SHIFT))&SIM_SOPT5_UARTTXSRC_MASK)
 
#define SIM_SOPT6_RSTFLTSEL_MASK   0x1F000000u
 
#define SIM_SOPT6_RSTFLTSEL_SHIFT   24
 
#define SIM_SOPT6_RSTFLTSEL(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT6_RSTFLTSEL_SHIFT))&SIM_SOPT6_RSTFLTSEL_MASK)
 
#define SIM_SOPT6_RSTFLTEN_MASK   0xE0000000u
 
#define SIM_SOPT6_RSTFLTEN_SHIFT   29
 
#define SIM_SOPT6_RSTFLTEN(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT6_RSTFLTEN_SHIFT))&SIM_SOPT6_RSTFLTEN_MASK)
 
#define SIM_SCGC3_RNGB_MASK   0x1u
 
#define SIM_SCGC3_RNGB_SHIFT   0
 
#define SIM_SCGC4_LLWU_MASK   0x10000000u
 
#define SIM_SCGC4_LLWU_SHIFT   28
 
#define SIM_SCGC5_LPTIMER_MASK   0x1u
 
#define SIM_SCGC5_LPTIMER_SHIFT   0
 
#define SIM_SCGC5_REGFILE_MASK   0x2u
 
#define SIM_SCGC5_REGFILE_SHIFT   1
 
#define SIM_SCGC6_FTFL_MASK   0x1u
 
#define SIM_SCGC6_FTFL_SHIFT   0
 
#define SIM_SCGC6_DSPI0_MASK   0x1000u
 
#define SIM_SCGC6_DSPI0_SHIFT   12
 
#define SIM_CLKDIV2_I2SFRAC_MASK   0xFF00u
 
#define SIM_CLKDIV2_I2SFRAC_SHIFT   8
 
#define SIM_CLKDIV2_I2SFRAC(x)   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_I2SFRAC_SHIFT))&SIM_CLKDIV2_I2SFRAC_MASK)
 
#define SIM_CLKDIV2_I2SDIV_MASK   0xFFF00000u
 
#define SIM_CLKDIV2_I2SDIV_SHIFT   20
 
#define SIM_CLKDIV2_I2SDIV(x)   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_I2SDIV_SHIFT))&SIM_CLKDIV2_I2SDIV_MASK)
 
#define SIM_FCFG1_FSIZE_MASK   0xFF000000u
 
#define SIM_FCFG1_FSIZE_SHIFT   24
 
#define SIM_FCFG1_FSIZE(x)   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FSIZE_SHIFT))&SIM_FCFG1_FSIZE_MASK)
 

SOPT1 - System Options Register 1

#define SIM_SOPT1_RAMSIZE_MASK   (0xF000U)
 
#define SIM_SOPT1_RAMSIZE_SHIFT   (12U)
 
#define SIM_SOPT1_RAMSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
 
#define SIM_SOPT1_OSC32KSEL_MASK   (0xC0000U)
 
#define SIM_SOPT1_OSC32KSEL_SHIFT   (18U)
 
#define SIM_SOPT1_OSC32KSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
 
#define SIM_SOPT1_RAMSIZE_MASK   0xF000u
 
#define SIM_SOPT1_RAMSIZE_SHIFT   12
 
#define SIM_SOPT1_RAMSIZE(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
 
#define SIM_SOPT1_OSC32KSEL_MASK   0x80000u
 
#define SIM_SOPT1_OSC32KSEL_SHIFT   19
 
#define SIM_SOPT1_RAMSIZE_MASK   (0xF000U)
 
#define SIM_SOPT1_RAMSIZE_SHIFT   (12U)
 
#define SIM_SOPT1_RAMSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
 
#define SIM_SOPT1_OSC32KSEL_MASK   (0xC0000U)
 
#define SIM_SOPT1_OSC32KSEL_SHIFT   (18U)
 
#define SIM_SOPT1_OSC32KSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
 
#define SIM_SOPT1_RAMSIZE_MASK   (0xF000U)
 
#define SIM_SOPT1_RAMSIZE_SHIFT   (12U)
 
#define SIM_SOPT1_RAMSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
 
#define SIM_SOPT1_OSC32KSEL_MASK   (0xC0000U)
 
#define SIM_SOPT1_OSC32KSEL_SHIFT   (18U)
 
#define SIM_SOPT1_OSC32KSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
 
#define SIM_SOPT1_RAMSIZE_MASK   (0xF000U)
 
#define SIM_SOPT1_RAMSIZE_SHIFT   (12U)
 
#define SIM_SOPT1_RAMSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
 
#define SIM_SOPT1_OSC32KSEL_MASK   (0xC0000U)
 
#define SIM_SOPT1_OSC32KSEL_SHIFT   (18U)
 
#define SIM_SOPT1_OSC32KSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
 
#define SIM_SOPT1_RAMSIZE_MASK   (0xF000U)
 
#define SIM_SOPT1_RAMSIZE_SHIFT   (12U)
 
#define SIM_SOPT1_RAMSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
 
#define SIM_SOPT1_OSC32KSEL_MASK   (0xC0000U)
 
#define SIM_SOPT1_OSC32KSEL_SHIFT   (18U)
 
#define SIM_SOPT1_OSC32KSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
 

SOPT1 - System Options Register 1

#define SIM_SOPT1_USBVSTBY_MASK   (0x20000000U)
 
#define SIM_SOPT1_USBVSTBY_SHIFT   (29U)
 
#define SIM_SOPT1_USBVSTBY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
 
#define SIM_SOPT1_USBSSTBY_MASK   (0x40000000U)
 
#define SIM_SOPT1_USBSSTBY_SHIFT   (30U)
 
#define SIM_SOPT1_USBSSTBY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
 
#define SIM_SOPT1_USBREGEN_MASK   (0x80000000U)
 
#define SIM_SOPT1_USBREGEN_SHIFT   (31U)
 
#define SIM_SOPT1_USBREGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
 
#define SIM_SOPT1_USBREGEN_MASK   0x80000000u
 
#define SIM_SOPT1_USBREGEN_SHIFT   31
 
#define SIM_SOPT1_USBVSTBY_MASK   (0x20000000U)
 
#define SIM_SOPT1_USBVSTBY_SHIFT   (29U)
 
#define SIM_SOPT1_USBVSTBY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
 
#define SIM_SOPT1_USBSSTBY_MASK   (0x40000000U)
 
#define SIM_SOPT1_USBSSTBY_SHIFT   (30U)
 
#define SIM_SOPT1_USBSSTBY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
 
#define SIM_SOPT1_USBREGEN_MASK   (0x80000000U)
 
#define SIM_SOPT1_USBREGEN_SHIFT   (31U)
 
#define SIM_SOPT1_USBREGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
 
#define SIM_SOPT1_USBVSTBY_MASK   (0x20000000U)
 
#define SIM_SOPT1_USBVSTBY_SHIFT   (29U)
 
#define SIM_SOPT1_USBVSTBY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
 
#define SIM_SOPT1_USBSSTBY_MASK   (0x40000000U)
 
#define SIM_SOPT1_USBSSTBY_SHIFT   (30U)
 
#define SIM_SOPT1_USBSSTBY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
 
#define SIM_SOPT1_USBREGEN_MASK   (0x80000000U)
 
#define SIM_SOPT1_USBREGEN_SHIFT   (31U)
 
#define SIM_SOPT1_USBREGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
 
#define SIM_SOPT1_USBVSTBY_MASK   (0x20000000U)
 
#define SIM_SOPT1_USBVSTBY_SHIFT   (29U)
 
#define SIM_SOPT1_USBVSTBY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
 
#define SIM_SOPT1_USBSSTBY_MASK   (0x40000000U)
 
#define SIM_SOPT1_USBSSTBY_SHIFT   (30U)
 
#define SIM_SOPT1_USBSSTBY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
 
#define SIM_SOPT1_USBREGEN_MASK   (0x80000000U)
 
#define SIM_SOPT1_USBREGEN_SHIFT   (31U)
 
#define SIM_SOPT1_USBREGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
 

SOPT1CFG - SOPT1 Configuration Register

#define SIM_SOPT1CFG_URWE_MASK   (0x1000000U)
 
#define SIM_SOPT1CFG_URWE_SHIFT   (24U)
 
#define SIM_SOPT1CFG_URWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
 
#define SIM_SOPT1CFG_UVSWE_MASK   (0x2000000U)
 
#define SIM_SOPT1CFG_UVSWE_SHIFT   (25U)
 
#define SIM_SOPT1CFG_UVSWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
 
#define SIM_SOPT1CFG_USSWE_MASK   (0x4000000U)
 
#define SIM_SOPT1CFG_USSWE_SHIFT   (26U)
 
#define SIM_SOPT1CFG_USSWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
 
#define SIM_SOPT1CFG_URWE_MASK   (0x1000000U)
 
#define SIM_SOPT1CFG_URWE_SHIFT   (24U)
 
#define SIM_SOPT1CFG_URWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
 
#define SIM_SOPT1CFG_UVSWE_MASK   (0x2000000U)
 
#define SIM_SOPT1CFG_UVSWE_SHIFT   (25U)
 
#define SIM_SOPT1CFG_UVSWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
 
#define SIM_SOPT1CFG_USSWE_MASK   (0x4000000U)
 
#define SIM_SOPT1CFG_USSWE_SHIFT   (26U)
 
#define SIM_SOPT1CFG_USSWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
 
#define SIM_SOPT1CFG_URWE_MASK   (0x1000000U)
 
#define SIM_SOPT1CFG_URWE_SHIFT   (24U)
 
#define SIM_SOPT1CFG_URWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
 
#define SIM_SOPT1CFG_UVSWE_MASK   (0x2000000U)
 
#define SIM_SOPT1CFG_UVSWE_SHIFT   (25U)
 
#define SIM_SOPT1CFG_UVSWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
 
#define SIM_SOPT1CFG_USSWE_MASK   (0x4000000U)
 
#define SIM_SOPT1CFG_USSWE_SHIFT   (26U)
 
#define SIM_SOPT1CFG_USSWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
 
#define SIM_SOPT1CFG_URWE_MASK   (0x1000000U)
 
#define SIM_SOPT1CFG_URWE_SHIFT   (24U)
 
#define SIM_SOPT1CFG_URWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
 
#define SIM_SOPT1CFG_UVSWE_MASK   (0x2000000U)
 
#define SIM_SOPT1CFG_UVSWE_SHIFT   (25U)
 
#define SIM_SOPT1CFG_UVSWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
 
#define SIM_SOPT1CFG_USSWE_MASK   (0x4000000U)
 
#define SIM_SOPT1CFG_USSWE_SHIFT   (26U)
 
#define SIM_SOPT1CFG_USSWE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
 

SOPT2 - System Options Register 2

#define SIM_SOPT2_RTCCLKOUTSEL_MASK   (0x10U)
 
#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT   (4U)
 
#define SIM_SOPT2_RTCCLKOUTSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
 
#define SIM_SOPT2_USBSRC_MASK   (0x40000U)
 
#define SIM_SOPT2_USBSRC_SHIFT   (18U)
 
#define SIM_SOPT2_USBSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
 
#define SIM_SOPT2_SDHCSRC_MASK   (0x30000000U)
 
#define SIM_SOPT2_SDHCSRC_SHIFT   (28U)
 
#define SIM_SOPT2_SDHCSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
 
#define SIM_SOPT2_USBSRC_MASK   0x40000u
 
#define SIM_SOPT2_USBSRC_SHIFT   18
 
#define SIM_SOPT2_SDHCSRC_MASK   0x30000000u
 
#define SIM_SOPT2_SDHCSRC_SHIFT   28
 
#define SIM_SOPT2_SDHCSRC(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
 
#define SIM_SOPT2_RTCCLKOUTSEL_MASK   (0x10U)
 
#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT   (4U)
 
#define SIM_SOPT2_RTCCLKOUTSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
 
#define SIM_SOPT2_USBSRC_MASK   (0x40000U)
 
#define SIM_SOPT2_USBSRC_SHIFT   (18U)
 
#define SIM_SOPT2_USBSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
 
#define SIM_SOPT2_SDHCSRC_MASK   (0x30000000U)
 
#define SIM_SOPT2_SDHCSRC_SHIFT   (28U)
 
#define SIM_SOPT2_SDHCSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
 
#define SIM_SOPT2_USBSLSRC_MASK   (0x1U)
 
#define SIM_SOPT2_USBSLSRC_SHIFT   (0U)
 
#define SIM_SOPT2_USBSLSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
 
#define SIM_SOPT2_USBREGEN_MASK   (0x2U)
 
#define SIM_SOPT2_USBREGEN_SHIFT   (1U)
 
#define SIM_SOPT2_USBREGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
 
#define SIM_SOPT2_RTCCLKOUTSEL_MASK   (0x10U)
 
#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT   (4U)
 
#define SIM_SOPT2_RTCCLKOUTSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
 
#define SIM_SOPT2_USBSRC_MASK   (0x40000U)
 
#define SIM_SOPT2_USBSRC_SHIFT   (18U)
 
#define SIM_SOPT2_USBSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
 
#define SIM_SOPT2_TPMSRC_MASK   (0x3000000U)
 
#define SIM_SOPT2_TPMSRC_SHIFT   (24U)
 
#define SIM_SOPT2_TPMSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
 
#define SIM_SOPT2_LPUARTSRC_MASK   (0xC000000U)
 
#define SIM_SOPT2_LPUARTSRC_SHIFT   (26U)
 
#define SIM_SOPT2_LPUARTSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
 
#define SIM_SOPT2_SDHCSRC_MASK   (0x30000000U)
 
#define SIM_SOPT2_SDHCSRC_SHIFT   (28U)
 
#define SIM_SOPT2_SDHCSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
 
#define SIM_SOPT2_USBSLSRC_MASK   (0x1U)
 
#define SIM_SOPT2_USBSLSRC_SHIFT   (0U)
 
#define SIM_SOPT2_USBSLSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
 
#define SIM_SOPT2_USBREGEN_MASK   (0x2U)
 
#define SIM_SOPT2_USBREGEN_SHIFT   (1U)
 
#define SIM_SOPT2_USBREGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
 
#define SIM_SOPT2_RTCCLKOUTSEL_MASK   (0x10U)
 
#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT   (4U)
 
#define SIM_SOPT2_RTCCLKOUTSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
 
#define SIM_SOPT2_USBSRC_MASK   (0x40000U)
 
#define SIM_SOPT2_USBSRC_SHIFT   (18U)
 
#define SIM_SOPT2_USBSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
 
#define SIM_SOPT2_TPMSRC_MASK   (0x3000000U)
 
#define SIM_SOPT2_TPMSRC_SHIFT   (24U)
 
#define SIM_SOPT2_TPMSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
 
#define SIM_SOPT2_LPUARTSRC_MASK   (0xC000000U)
 
#define SIM_SOPT2_LPUARTSRC_SHIFT   (26U)
 
#define SIM_SOPT2_LPUARTSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
 
#define SIM_SOPT2_SDHCSRC_MASK   (0x30000000U)
 
#define SIM_SOPT2_SDHCSRC_SHIFT   (28U)
 
#define SIM_SOPT2_SDHCSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
 

SOPT2 - System Options Register 2

#define SIM_SOPT2_CLKOUTSEL_MASK   (0xE0U)
 
#define SIM_SOPT2_CLKOUTSEL_SHIFT   (5U)
 
#define SIM_SOPT2_CLKOUTSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
 
#define SIM_SOPT2_FBSL_MASK   (0x300U)
 
#define SIM_SOPT2_FBSL_SHIFT   (8U)
 
#define SIM_SOPT2_FBSL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
 
#define SIM_SOPT2_TRACECLKSEL_MASK   (0x1000U)
 
#define SIM_SOPT2_TRACECLKSEL_SHIFT   (12U)
 
#define SIM_SOPT2_TRACECLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
 
#define SIM_SOPT2_PLLFLLSEL_MASK   (0x10000U)
 
#define SIM_SOPT2_PLLFLLSEL_SHIFT   (16U)
 
#define SIM_SOPT2_PLLFLLSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
 
#define SIM_SOPT2_RMIISRC_MASK   (0x80000U)
 
#define SIM_SOPT2_RMIISRC_SHIFT   (19U)
 
#define SIM_SOPT2_RMIISRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
 
#define SIM_SOPT2_TIMESRC_MASK   (0x300000U)
 
#define SIM_SOPT2_TIMESRC_SHIFT   (20U)
 
#define SIM_SOPT2_TIMESRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
 
#define SIM_SOPT2_FBSL_MASK   0x300u
 
#define SIM_SOPT2_FBSL_SHIFT   8
 
#define SIM_SOPT2_FBSL(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
 
#define SIM_SOPT2_TRACECLKSEL_MASK   0x1000u
 
#define SIM_SOPT2_TRACECLKSEL_SHIFT   12
 
#define SIM_SOPT2_PLLFLLSEL_MASK   0x10000u
 
#define SIM_SOPT2_PLLFLLSEL_SHIFT   16
 
#define SIM_SOPT2_TIMESRC_MASK   0x300000u
 
#define SIM_SOPT2_TIMESRC_SHIFT   20
 
#define SIM_SOPT2_TIMESRC(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
 
#define SIM_SOPT2_CLKOUTSEL_MASK   (0xE0U)
 
#define SIM_SOPT2_CLKOUTSEL_SHIFT   (5U)
 
#define SIM_SOPT2_CLKOUTSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
 
#define SIM_SOPT2_FBSL_MASK   (0x300U)
 
#define SIM_SOPT2_FBSL_SHIFT   (8U)
 
#define SIM_SOPT2_FBSL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
 
#define SIM_SOPT2_TRACECLKSEL_MASK   (0x1000U)
 
#define SIM_SOPT2_TRACECLKSEL_SHIFT   (12U)
 
#define SIM_SOPT2_TRACECLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
 
#define SIM_SOPT2_PLLFLLSEL_MASK   (0x30000U)
 
#define SIM_SOPT2_PLLFLLSEL_SHIFT   (16U)
 
#define SIM_SOPT2_PLLFLLSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
 
#define SIM_SOPT2_RMIISRC_MASK   (0x80000U)
 
#define SIM_SOPT2_RMIISRC_SHIFT   (19U)
 
#define SIM_SOPT2_RMIISRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
 
#define SIM_SOPT2_TIMESRC_MASK   (0x300000U)
 
#define SIM_SOPT2_TIMESRC_SHIFT   (20U)
 
#define SIM_SOPT2_TIMESRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
 
#define SIM_SOPT2_CLKOUTSEL_MASK   (0xE0U)
 
#define SIM_SOPT2_CLKOUTSEL_SHIFT   (5U)
 
#define SIM_SOPT2_CLKOUTSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
 
#define SIM_SOPT2_FBSL_MASK   (0x300U)
 
#define SIM_SOPT2_FBSL_SHIFT   (8U)
 
#define SIM_SOPT2_FBSL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
 
#define SIM_SOPT2_TRACECLKSEL_MASK   (0x1000U)
 
#define SIM_SOPT2_TRACECLKSEL_SHIFT   (12U)
 
#define SIM_SOPT2_TRACECLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
 
#define SIM_SOPT2_PLLFLLSEL_MASK   (0x30000U)
 
#define SIM_SOPT2_PLLFLLSEL_SHIFT   (16U)
 
#define SIM_SOPT2_PLLFLLSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
 
#define SIM_SOPT2_RMIISRC_MASK   (0x80000U)
 
#define SIM_SOPT2_RMIISRC_SHIFT   (19U)
 
#define SIM_SOPT2_RMIISRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
 
#define SIM_SOPT2_TIMESRC_MASK   (0x300000U)
 
#define SIM_SOPT2_TIMESRC_SHIFT   (20U)
 
#define SIM_SOPT2_TIMESRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
 
#define SIM_SOPT2_CLKOUTSEL_MASK   (0xE0U)
 
#define SIM_SOPT2_CLKOUTSEL_SHIFT   (5U)
 
#define SIM_SOPT2_CLKOUTSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
 
#define SIM_SOPT2_FBSL_MASK   (0x300U)
 
#define SIM_SOPT2_FBSL_SHIFT   (8U)
 
#define SIM_SOPT2_FBSL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
 
#define SIM_SOPT2_TRACECLKSEL_MASK   (0x1000U)
 
#define SIM_SOPT2_TRACECLKSEL_SHIFT   (12U)
 
#define SIM_SOPT2_TRACECLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
 
#define SIM_SOPT2_PLLFLLSEL_MASK   (0x30000U)
 
#define SIM_SOPT2_PLLFLLSEL_SHIFT   (16U)
 
#define SIM_SOPT2_PLLFLLSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
 
#define SIM_SOPT2_RMIISRC_MASK   (0x80000U)
 
#define SIM_SOPT2_RMIISRC_SHIFT   (19U)
 
#define SIM_SOPT2_RMIISRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
 
#define SIM_SOPT2_TIMESRC_MASK   (0x300000U)
 
#define SIM_SOPT2_TIMESRC_SHIFT   (20U)
 
#define SIM_SOPT2_TIMESRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
 
#define SIM_SOPT2_CLKOUTSEL_MASK   (0xE0U)
 
#define SIM_SOPT2_CLKOUTSEL_SHIFT   (5U)
 
#define SIM_SOPT2_CLKOUTSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
 
#define SIM_SOPT2_FBSL_MASK   (0x300U)
 
#define SIM_SOPT2_FBSL_SHIFT   (8U)
 
#define SIM_SOPT2_FBSL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
 
#define SIM_SOPT2_TRACECLKSEL_MASK   (0x1000U)
 
#define SIM_SOPT2_TRACECLKSEL_SHIFT   (12U)
 
#define SIM_SOPT2_TRACECLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
 
#define SIM_SOPT2_PLLFLLSEL_MASK   (0x30000U)
 
#define SIM_SOPT2_PLLFLLSEL_SHIFT   (16U)
 
#define SIM_SOPT2_PLLFLLSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
 
#define SIM_SOPT2_RMIISRC_MASK   (0x80000U)
 
#define SIM_SOPT2_RMIISRC_SHIFT   (19U)
 
#define SIM_SOPT2_RMIISRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
 
#define SIM_SOPT2_TIMESRC_MASK   (0x300000U)
 
#define SIM_SOPT2_TIMESRC_SHIFT   (20U)
 
#define SIM_SOPT2_TIMESRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
 

SOPT2 - System Options Register 2

#define SIM_SOPT2_PTD7PAD_MASK   (0x800U)
 
#define SIM_SOPT2_PTD7PAD_SHIFT   (11U)
 
#define SIM_SOPT2_PTD7PAD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
 
#define SIM_SOPT2_PTD7PAD_MASK   (0x800U)
 
#define SIM_SOPT2_PTD7PAD_SHIFT   (11U)
 
#define SIM_SOPT2_PTD7PAD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
 

SOPT4 - System Options Register 4

#define SIM_SOPT4_FTM0FLT0_MASK   (0x1U)
 
#define SIM_SOPT4_FTM0FLT0_SHIFT   (0U)
 
#define SIM_SOPT4_FTM0FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
 
#define SIM_SOPT4_FTM0FLT1_MASK   (0x2U)
 
#define SIM_SOPT4_FTM0FLT1_SHIFT   (1U)
 
#define SIM_SOPT4_FTM0FLT1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
 
#define SIM_SOPT4_FTM0FLT2_MASK   (0x4U)
 
#define SIM_SOPT4_FTM0FLT2_SHIFT   (2U)
 
#define SIM_SOPT4_FTM0FLT2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
 
#define SIM_SOPT4_FTM1FLT0_MASK   (0x10U)
 
#define SIM_SOPT4_FTM1FLT0_SHIFT   (4U)
 
#define SIM_SOPT4_FTM1FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
 
#define SIM_SOPT4_FTM2FLT0_MASK   (0x100U)
 
#define SIM_SOPT4_FTM2FLT0_SHIFT   (8U)
 
#define SIM_SOPT4_FTM2FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
 
#define SIM_SOPT4_FTM0TRG0SRC_MASK   (0x10000000U)
 
#define SIM_SOPT4_FTM0TRG0SRC_SHIFT   (28U)
 
#define SIM_SOPT4_FTM0TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM0TRG1SRC_MASK   (0x20000000U)
 
#define SIM_SOPT4_FTM0TRG1SRC_SHIFT   (29U)
 
#define SIM_SOPT4_FTM0TRG1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
 
#define SIM_SOPT4_FTM0FLT0_MASK   0x1u
 
#define SIM_SOPT4_FTM0FLT0_SHIFT   0
 
#define SIM_SOPT4_FTM0FLT1_MASK   0x2u
 
#define SIM_SOPT4_FTM0FLT1_SHIFT   1
 
#define SIM_SOPT4_FTM0FLT2_MASK   0x4u
 
#define SIM_SOPT4_FTM0FLT2_SHIFT   2
 
#define SIM_SOPT4_FTM1FLT0_MASK   0x10u
 
#define SIM_SOPT4_FTM1FLT0_SHIFT   4
 
#define SIM_SOPT4_FTM2FLT0_MASK   0x100u
 
#define SIM_SOPT4_FTM2FLT0_SHIFT   8
 
#define SIM_SOPT4_FTM0FLT0_MASK   (0x1U)
 
#define SIM_SOPT4_FTM0FLT0_SHIFT   (0U)
 
#define SIM_SOPT4_FTM0FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
 
#define SIM_SOPT4_FTM0FLT1_MASK   (0x2U)
 
#define SIM_SOPT4_FTM0FLT1_SHIFT   (1U)
 
#define SIM_SOPT4_FTM0FLT1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
 
#define SIM_SOPT4_FTM0FLT2_MASK   (0x4U)
 
#define SIM_SOPT4_FTM0FLT2_SHIFT   (2U)
 
#define SIM_SOPT4_FTM0FLT2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
 
#define SIM_SOPT4_FTM1FLT0_MASK   (0x10U)
 
#define SIM_SOPT4_FTM1FLT0_SHIFT   (4U)
 
#define SIM_SOPT4_FTM1FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
 
#define SIM_SOPT4_FTM2FLT0_MASK   (0x100U)
 
#define SIM_SOPT4_FTM2FLT0_SHIFT   (8U)
 
#define SIM_SOPT4_FTM2FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
 
#define SIM_SOPT4_FTM3FLT0_MASK   (0x1000U)
 
#define SIM_SOPT4_FTM3FLT0_SHIFT   (12U)
 
#define SIM_SOPT4_FTM3FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
 
#define SIM_SOPT4_FTM0TRG0SRC_MASK   (0x10000000U)
 
#define SIM_SOPT4_FTM0TRG0SRC_SHIFT   (28U)
 
#define SIM_SOPT4_FTM0TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM0TRG1SRC_MASK   (0x20000000U)
 
#define SIM_SOPT4_FTM0TRG1SRC_SHIFT   (29U)
 
#define SIM_SOPT4_FTM0TRG1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
 
#define SIM_SOPT4_FTM3TRG0SRC_MASK   (0x40000000U)
 
#define SIM_SOPT4_FTM3TRG0SRC_SHIFT   (30U)
 
#define SIM_SOPT4_FTM3TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM3TRG1SRC_MASK   (0x80000000U)
 
#define SIM_SOPT4_FTM3TRG1SRC_SHIFT   (31U)
 
#define SIM_SOPT4_FTM3TRG1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
 
#define SIM_SOPT4_FTM0FLT0_MASK   (0x1U)
 
#define SIM_SOPT4_FTM0FLT0_SHIFT   (0U)
 
#define SIM_SOPT4_FTM0FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
 
#define SIM_SOPT4_FTM0FLT1_MASK   (0x2U)
 
#define SIM_SOPT4_FTM0FLT1_SHIFT   (1U)
 
#define SIM_SOPT4_FTM0FLT1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
 
#define SIM_SOPT4_FTM0FLT2_MASK   (0x4U)
 
#define SIM_SOPT4_FTM0FLT2_SHIFT   (2U)
 
#define SIM_SOPT4_FTM0FLT2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
 
#define SIM_SOPT4_FTM0FLT3_MASK   (0x8U)
 
#define SIM_SOPT4_FTM0FLT3_SHIFT   (3U)
 
#define SIM_SOPT4_FTM0FLT3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
 
#define SIM_SOPT4_FTM1FLT0_MASK   (0x10U)
 
#define SIM_SOPT4_FTM1FLT0_SHIFT   (4U)
 
#define SIM_SOPT4_FTM1FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
 
#define SIM_SOPT4_FTM2FLT0_MASK   (0x100U)
 
#define SIM_SOPT4_FTM2FLT0_SHIFT   (8U)
 
#define SIM_SOPT4_FTM2FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
 
#define SIM_SOPT4_FTM3FLT0_MASK   (0x1000U)
 
#define SIM_SOPT4_FTM3FLT0_SHIFT   (12U)
 
#define SIM_SOPT4_FTM3FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
 
#define SIM_SOPT4_FTM0TRG0SRC_MASK   (0x10000000U)
 
#define SIM_SOPT4_FTM0TRG0SRC_SHIFT   (28U)
 
#define SIM_SOPT4_FTM0TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM0TRG1SRC_MASK   (0x20000000U)
 
#define SIM_SOPT4_FTM0TRG1SRC_SHIFT   (29U)
 
#define SIM_SOPT4_FTM0TRG1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
 
#define SIM_SOPT4_FTM3TRG0SRC_MASK   (0x40000000U)
 
#define SIM_SOPT4_FTM3TRG0SRC_SHIFT   (30U)
 
#define SIM_SOPT4_FTM3TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM3TRG1SRC_MASK   (0x80000000U)
 
#define SIM_SOPT4_FTM3TRG1SRC_SHIFT   (31U)
 
#define SIM_SOPT4_FTM3TRG1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
 
#define SIM_SOPT4_FTM0FLT0_MASK   (0x1U)
 
#define SIM_SOPT4_FTM0FLT0_SHIFT   (0U)
 
#define SIM_SOPT4_FTM0FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
 
#define SIM_SOPT4_FTM0FLT1_MASK   (0x2U)
 
#define SIM_SOPT4_FTM0FLT1_SHIFT   (1U)
 
#define SIM_SOPT4_FTM0FLT1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
 
#define SIM_SOPT4_FTM0FLT2_MASK   (0x4U)
 
#define SIM_SOPT4_FTM0FLT2_SHIFT   (2U)
 
#define SIM_SOPT4_FTM0FLT2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
 
#define SIM_SOPT4_FTM0FLT3_MASK   (0x8U)
 
#define SIM_SOPT4_FTM0FLT3_SHIFT   (3U)
 
#define SIM_SOPT4_FTM0FLT3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
 
#define SIM_SOPT4_FTM1FLT0_MASK   (0x10U)
 
#define SIM_SOPT4_FTM1FLT0_SHIFT   (4U)
 
#define SIM_SOPT4_FTM1FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
 
#define SIM_SOPT4_FTM2FLT0_MASK   (0x100U)
 
#define SIM_SOPT4_FTM2FLT0_SHIFT   (8U)
 
#define SIM_SOPT4_FTM2FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
 
#define SIM_SOPT4_FTM3FLT0_MASK   (0x1000U)
 
#define SIM_SOPT4_FTM3FLT0_SHIFT   (12U)
 
#define SIM_SOPT4_FTM3FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
 
#define SIM_SOPT4_FTM0TRG0SRC_MASK   (0x10000000U)
 
#define SIM_SOPT4_FTM0TRG0SRC_SHIFT   (28U)
 
#define SIM_SOPT4_FTM0TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM0TRG1SRC_MASK   (0x20000000U)
 
#define SIM_SOPT4_FTM0TRG1SRC_SHIFT   (29U)
 
#define SIM_SOPT4_FTM0TRG1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
 
#define SIM_SOPT4_FTM3TRG0SRC_MASK   (0x40000000U)
 
#define SIM_SOPT4_FTM3TRG0SRC_SHIFT   (30U)
 
#define SIM_SOPT4_FTM3TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM3TRG1SRC_MASK   (0x80000000U)
 
#define SIM_SOPT4_FTM3TRG1SRC_SHIFT   (31U)
 
#define SIM_SOPT4_FTM3TRG1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
 
#define SIM_SOPT4_FTM0FLT0_MASK   (0x1U)
 
#define SIM_SOPT4_FTM0FLT0_SHIFT   (0U)
 
#define SIM_SOPT4_FTM0FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
 
#define SIM_SOPT4_FTM0FLT1_MASK   (0x2U)
 
#define SIM_SOPT4_FTM0FLT1_SHIFT   (1U)
 
#define SIM_SOPT4_FTM0FLT1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
 
#define SIM_SOPT4_FTM0FLT2_MASK   (0x4U)
 
#define SIM_SOPT4_FTM0FLT2_SHIFT   (2U)
 
#define SIM_SOPT4_FTM0FLT2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
 
#define SIM_SOPT4_FTM0FLT3_MASK   (0x8U)
 
#define SIM_SOPT4_FTM0FLT3_SHIFT   (3U)
 
#define SIM_SOPT4_FTM0FLT3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
 
#define SIM_SOPT4_FTM1FLT0_MASK   (0x10U)
 
#define SIM_SOPT4_FTM1FLT0_SHIFT   (4U)
 
#define SIM_SOPT4_FTM1FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
 
#define SIM_SOPT4_FTM2FLT0_MASK   (0x100U)
 
#define SIM_SOPT4_FTM2FLT0_SHIFT   (8U)
 
#define SIM_SOPT4_FTM2FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
 
#define SIM_SOPT4_FTM3FLT0_MASK   (0x1000U)
 
#define SIM_SOPT4_FTM3FLT0_SHIFT   (12U)
 
#define SIM_SOPT4_FTM3FLT0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
 
#define SIM_SOPT4_FTM0TRG0SRC_MASK   (0x10000U)
 
#define SIM_SOPT4_FTM0TRG0SRC_SHIFT   (16U)
 
#define SIM_SOPT4_FTM0TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM0TRG1SRC_MASK   (0x20000U)
 
#define SIM_SOPT4_FTM0TRG1SRC_SHIFT   (17U)
 
#define SIM_SOPT4_FTM0TRG1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
 
#define SIM_SOPT4_FTM0TRG2SRC_MASK   (0x40000U)
 
#define SIM_SOPT4_FTM0TRG2SRC_SHIFT   (18U)
 
#define SIM_SOPT4_FTM0TRG2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG2SRC_SHIFT)) & SIM_SOPT4_FTM0TRG2SRC_MASK)
 
#define SIM_SOPT4_FTM1TRG0SRC_MASK   (0x100000U)
 
#define SIM_SOPT4_FTM1TRG0SRC_SHIFT   (20U)
 
#define SIM_SOPT4_FTM1TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1TRG0SRC_SHIFT)) & SIM_SOPT4_FTM1TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM1TRG2SRC_MASK   (0x400000U)
 
#define SIM_SOPT4_FTM1TRG2SRC_SHIFT   (22U)
 
#define SIM_SOPT4_FTM1TRG2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1TRG2SRC_SHIFT)) & SIM_SOPT4_FTM1TRG2SRC_MASK)
 
#define SIM_SOPT4_FTM2TRG0SRC_MASK   (0x1000000U)
 
#define SIM_SOPT4_FTM2TRG0SRC_SHIFT   (24U)
 
#define SIM_SOPT4_FTM2TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2TRG0SRC_SHIFT)) & SIM_SOPT4_FTM2TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM2TRG2SRC_MASK   (0x4000000U)
 
#define SIM_SOPT4_FTM2TRG2SRC_SHIFT   (26U)
 
#define SIM_SOPT4_FTM2TRG2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2TRG2SRC_SHIFT)) & SIM_SOPT4_FTM2TRG2SRC_MASK)
 
#define SIM_SOPT4_FTM3TRG0SRC_MASK   (0x10000000U)
 
#define SIM_SOPT4_FTM3TRG0SRC_SHIFT   (28U)
 
#define SIM_SOPT4_FTM3TRG0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
 
#define SIM_SOPT4_FTM3TRG1SRC_MASK   (0x20000000U)
 
#define SIM_SOPT4_FTM3TRG1SRC_SHIFT   (29U)
 
#define SIM_SOPT4_FTM3TRG1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
 
#define SIM_SOPT4_FTM3TRG2SRC_MASK   (0x40000000U)
 
#define SIM_SOPT4_FTM3TRG2SRC_SHIFT   (30U)
 
#define SIM_SOPT4_FTM3TRG2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG2SRC_SHIFT)) & SIM_SOPT4_FTM3TRG2SRC_MASK)
 

SOPT4 - System Options Register 4

#define SIM_SOPT4_FTM1CH0SRC_MASK   (0xC0000U)
 
#define SIM_SOPT4_FTM1CH0SRC_SHIFT   (18U)
 
#define SIM_SOPT4_FTM1CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
 
#define SIM_SOPT4_FTM2CH0SRC_MASK   (0x300000U)
 
#define SIM_SOPT4_FTM2CH0SRC_SHIFT   (20U)
 
#define SIM_SOPT4_FTM2CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
 
#define SIM_SOPT4_FTM0CLKSEL_MASK   (0x1000000U)
 
#define SIM_SOPT4_FTM0CLKSEL_SHIFT   (24U)
 
#define SIM_SOPT4_FTM0CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
 
#define SIM_SOPT4_FTM1CLKSEL_MASK   (0x2000000U)
 
#define SIM_SOPT4_FTM1CLKSEL_SHIFT   (25U)
 
#define SIM_SOPT4_FTM1CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
 
#define SIM_SOPT4_FTM2CLKSEL_MASK   (0x4000000U)
 
#define SIM_SOPT4_FTM2CLKSEL_SHIFT   (26U)
 
#define SIM_SOPT4_FTM2CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
 
#define SIM_SOPT4_FTM1CH0SRC_MASK   0xC0000u
 
#define SIM_SOPT4_FTM1CH0SRC_SHIFT   18
 
#define SIM_SOPT4_FTM1CH0SRC(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
 
#define SIM_SOPT4_FTM2CH0SRC_MASK   0x300000u
 
#define SIM_SOPT4_FTM2CH0SRC_SHIFT   20
 
#define SIM_SOPT4_FTM2CH0SRC(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
 
#define SIM_SOPT4_FTM0CLKSEL_MASK   0x1000000u
 
#define SIM_SOPT4_FTM0CLKSEL_SHIFT   24
 
#define SIM_SOPT4_FTM1CLKSEL_MASK   0x2000000u
 
#define SIM_SOPT4_FTM1CLKSEL_SHIFT   25
 
#define SIM_SOPT4_FTM2CLKSEL_MASK   0x4000000u
 
#define SIM_SOPT4_FTM2CLKSEL_SHIFT   26
 
#define SIM_SOPT4_FTM1CH0SRC_MASK   (0xC0000U)
 
#define SIM_SOPT4_FTM1CH0SRC_SHIFT   (18U)
 
#define SIM_SOPT4_FTM1CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
 
#define SIM_SOPT4_FTM2CH0SRC_MASK   (0x300000U)
 
#define SIM_SOPT4_FTM2CH0SRC_SHIFT   (20U)
 
#define SIM_SOPT4_FTM2CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
 
#define SIM_SOPT4_FTM0CLKSEL_MASK   (0x1000000U)
 
#define SIM_SOPT4_FTM0CLKSEL_SHIFT   (24U)
 
#define SIM_SOPT4_FTM0CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
 
#define SIM_SOPT4_FTM1CLKSEL_MASK   (0x2000000U)
 
#define SIM_SOPT4_FTM1CLKSEL_SHIFT   (25U)
 
#define SIM_SOPT4_FTM1CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
 
#define SIM_SOPT4_FTM2CLKSEL_MASK   (0x4000000U)
 
#define SIM_SOPT4_FTM2CLKSEL_SHIFT   (26U)
 
#define SIM_SOPT4_FTM2CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
 
#define SIM_SOPT4_FTM3CLKSEL_MASK   (0x8000000U)
 
#define SIM_SOPT4_FTM3CLKSEL_SHIFT   (27U)
 
#define SIM_SOPT4_FTM3CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
 
#define SIM_SOPT4_FTM1CH0SRC_MASK   (0xC0000U)
 
#define SIM_SOPT4_FTM1CH0SRC_SHIFT   (18U)
 
#define SIM_SOPT4_FTM1CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
 
#define SIM_SOPT4_FTM2CH0SRC_MASK   (0x300000U)
 
#define SIM_SOPT4_FTM2CH0SRC_SHIFT   (20U)
 
#define SIM_SOPT4_FTM2CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
 
#define SIM_SOPT4_FTM2CH1SRC_MASK   (0x400000U)
 
#define SIM_SOPT4_FTM2CH1SRC_SHIFT   (22U)
 
#define SIM_SOPT4_FTM2CH1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
 
#define SIM_SOPT4_FTM0CLKSEL_MASK   (0x1000000U)
 
#define SIM_SOPT4_FTM0CLKSEL_SHIFT   (24U)
 
#define SIM_SOPT4_FTM0CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
 
#define SIM_SOPT4_FTM1CLKSEL_MASK   (0x2000000U)
 
#define SIM_SOPT4_FTM1CLKSEL_SHIFT   (25U)
 
#define SIM_SOPT4_FTM1CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
 
#define SIM_SOPT4_FTM2CLKSEL_MASK   (0x4000000U)
 
#define SIM_SOPT4_FTM2CLKSEL_SHIFT   (26U)
 
#define SIM_SOPT4_FTM2CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
 
#define SIM_SOPT4_FTM3CLKSEL_MASK   (0x8000000U)
 
#define SIM_SOPT4_FTM3CLKSEL_SHIFT   (27U)
 
#define SIM_SOPT4_FTM3CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
 
#define SIM_SOPT4_FTM1CH0SRC_MASK   (0xC0000U)
 
#define SIM_SOPT4_FTM1CH0SRC_SHIFT   (18U)
 
#define SIM_SOPT4_FTM1CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
 
#define SIM_SOPT4_FTM2CH0SRC_MASK   (0x300000U)
 
#define SIM_SOPT4_FTM2CH0SRC_SHIFT   (20U)
 
#define SIM_SOPT4_FTM2CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
 
#define SIM_SOPT4_FTM2CH1SRC_MASK   (0x400000U)
 
#define SIM_SOPT4_FTM2CH1SRC_SHIFT   (22U)
 
#define SIM_SOPT4_FTM2CH1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
 
#define SIM_SOPT4_FTM0CLKSEL_MASK   (0x1000000U)
 
#define SIM_SOPT4_FTM0CLKSEL_SHIFT   (24U)
 
#define SIM_SOPT4_FTM0CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
 
#define SIM_SOPT4_FTM1CLKSEL_MASK   (0x2000000U)
 
#define SIM_SOPT4_FTM1CLKSEL_SHIFT   (25U)
 
#define SIM_SOPT4_FTM1CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
 
#define SIM_SOPT4_FTM2CLKSEL_MASK   (0x4000000U)
 
#define SIM_SOPT4_FTM2CLKSEL_SHIFT   (26U)
 
#define SIM_SOPT4_FTM2CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
 
#define SIM_SOPT4_FTM3CLKSEL_MASK   (0x8000000U)
 
#define SIM_SOPT4_FTM3CLKSEL_SHIFT   (27U)
 
#define SIM_SOPT4_FTM3CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
 

SOPT5 - System Options Register 5

#define SIM_SOPT5_UART0TXSRC_MASK   (0x3U)
 
#define SIM_SOPT5_UART0TXSRC_SHIFT   (0U)
 
#define SIM_SOPT5_UART0TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
 
#define SIM_SOPT5_UART0RXSRC_MASK   (0xCU)
 
#define SIM_SOPT5_UART0RXSRC_SHIFT   (2U)
 
#define SIM_SOPT5_UART0RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
 
#define SIM_SOPT5_UART1TXSRC_MASK   (0x30U)
 
#define SIM_SOPT5_UART1TXSRC_SHIFT   (4U)
 
#define SIM_SOPT5_UART1TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
 
#define SIM_SOPT5_UART1RXSRC_MASK   (0xC0U)
 
#define SIM_SOPT5_UART1RXSRC_SHIFT   (6U)
 
#define SIM_SOPT5_UART1RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
 
#define SIM_SOPT5_UART0TXSRC_MASK   0x3u
 
#define SIM_SOPT5_UART0TXSRC_SHIFT   0
 
#define SIM_SOPT5_UART0TXSRC(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
 
#define SIM_SOPT5_UART0RXSRC_MASK   0xCu
 
#define SIM_SOPT5_UART0RXSRC_SHIFT   2
 
#define SIM_SOPT5_UART0RXSRC(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
 
#define SIM_SOPT5_UART1RXSRC_MASK   0xC0u
 
#define SIM_SOPT5_UART1RXSRC_SHIFT   6
 
#define SIM_SOPT5_UART1RXSRC(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
 
#define SIM_SOPT5_UART0TXSRC_MASK   (0x3U)
 
#define SIM_SOPT5_UART0TXSRC_SHIFT   (0U)
 
#define SIM_SOPT5_UART0TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
 
#define SIM_SOPT5_UART0RXSRC_MASK   (0xCU)
 
#define SIM_SOPT5_UART0RXSRC_SHIFT   (2U)
 
#define SIM_SOPT5_UART0RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
 
#define SIM_SOPT5_UART1TXSRC_MASK   (0x30U)
 
#define SIM_SOPT5_UART1TXSRC_SHIFT   (4U)
 
#define SIM_SOPT5_UART1TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
 
#define SIM_SOPT5_UART1RXSRC_MASK   (0xC0U)
 
#define SIM_SOPT5_UART1RXSRC_SHIFT   (6U)
 
#define SIM_SOPT5_UART1RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
 
#define SIM_SOPT5_UART0TXSRC_MASK   (0x3U)
 
#define SIM_SOPT5_UART0TXSRC_SHIFT   (0U)
 
#define SIM_SOPT5_UART0TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
 
#define SIM_SOPT5_UART0RXSRC_MASK   (0xCU)
 
#define SIM_SOPT5_UART0RXSRC_SHIFT   (2U)
 
#define SIM_SOPT5_UART0RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
 
#define SIM_SOPT5_UART1TXSRC_MASK   (0x30U)
 
#define SIM_SOPT5_UART1TXSRC_SHIFT   (4U)
 
#define SIM_SOPT5_UART1TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
 
#define SIM_SOPT5_UART1RXSRC_MASK   (0xC0U)
 
#define SIM_SOPT5_UART1RXSRC_SHIFT   (6U)
 
#define SIM_SOPT5_UART1RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
 
#define SIM_SOPT5_UART0TXSRC_MASK   (0x3U)
 
#define SIM_SOPT5_UART0TXSRC_SHIFT   (0U)
 
#define SIM_SOPT5_UART0TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
 
#define SIM_SOPT5_UART0RXSRC_MASK   (0xCU)
 
#define SIM_SOPT5_UART0RXSRC_SHIFT   (2U)
 
#define SIM_SOPT5_UART0RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
 
#define SIM_SOPT5_UART1TXSRC_MASK   (0x30U)
 
#define SIM_SOPT5_UART1TXSRC_SHIFT   (4U)
 
#define SIM_SOPT5_UART1TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
 
#define SIM_SOPT5_UART1RXSRC_MASK   (0xC0U)
 
#define SIM_SOPT5_UART1RXSRC_SHIFT   (6U)
 
#define SIM_SOPT5_UART1RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
 
#define SIM_SOPT5_UART0TXSRC_MASK   (0x3U)
 
#define SIM_SOPT5_UART0TXSRC_SHIFT   (0U)
 
#define SIM_SOPT5_UART0TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
 
#define SIM_SOPT5_UART0RXSRC_MASK   (0xCU)
 
#define SIM_SOPT5_UART0RXSRC_SHIFT   (2U)
 
#define SIM_SOPT5_UART0RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
 
#define SIM_SOPT5_UART1TXSRC_MASK   (0x30U)
 
#define SIM_SOPT5_UART1TXSRC_SHIFT   (4U)
 
#define SIM_SOPT5_UART1TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
 
#define SIM_SOPT5_UART1RXSRC_MASK   (0xC0U)
 
#define SIM_SOPT5_UART1RXSRC_SHIFT   (6U)
 
#define SIM_SOPT5_UART1RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
 

SOPT7 - System Options Register 7

#define SIM_SOPT7_ADC0TRGSEL_MASK   (0xFU)
 
#define SIM_SOPT7_ADC0TRGSEL_SHIFT   (0U)
 
#define SIM_SOPT7_ADC0TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
 
#define SIM_SOPT7_ADC0PRETRGSEL_MASK   (0x10U)
 
#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT   (4U)
 
#define SIM_SOPT7_ADC0PRETRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
 
#define SIM_SOPT7_ADC0ALTTRGEN_MASK   (0x80U)
 
#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT   (7U)
 
#define SIM_SOPT7_ADC0ALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
 
#define SIM_SOPT7_ADC1TRGSEL_MASK   (0xF00U)
 
#define SIM_SOPT7_ADC1TRGSEL_SHIFT   (8U)
 
#define SIM_SOPT7_ADC1TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
 
#define SIM_SOPT7_ADC1PRETRGSEL_MASK   (0x1000U)
 
#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT   (12U)
 
#define SIM_SOPT7_ADC1PRETRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
 
#define SIM_SOPT7_ADC1ALTTRGEN_MASK   (0x8000U)
 
#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT   (15U)
 
#define SIM_SOPT7_ADC1ALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
 
#define SIM_SOPT7_ADC0TRGSEL_MASK   0xFu
 
#define SIM_SOPT7_ADC0TRGSEL_SHIFT   0
 
#define SIM_SOPT7_ADC0TRGSEL(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
 
#define SIM_SOPT7_ADC0PRETRGSEL_MASK   0x10u
 
#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT   4
 
#define SIM_SOPT7_ADC0ALTTRGEN_MASK   0x80u
 
#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT   7
 
#define SIM_SOPT7_ADC1TRGSEL_MASK   0xF00u
 
#define SIM_SOPT7_ADC1TRGSEL_SHIFT   8
 
#define SIM_SOPT7_ADC1TRGSEL(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
 
#define SIM_SOPT7_ADC1PRETRGSEL_MASK   0x1000u
 
#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT   12
 
#define SIM_SOPT7_ADC1ALTTRGEN_MASK   0x8000u
 
#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT   15
 
#define SIM_SOPT7_ADC0TRGSEL_MASK   (0xFU)
 
#define SIM_SOPT7_ADC0TRGSEL_SHIFT   (0U)
 
#define SIM_SOPT7_ADC0TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
 
#define SIM_SOPT7_ADC0PRETRGSEL_MASK   (0x10U)
 
#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT   (4U)
 
#define SIM_SOPT7_ADC0PRETRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
 
#define SIM_SOPT7_ADC0ALTTRGEN_MASK   (0x80U)
 
#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT   (7U)
 
#define SIM_SOPT7_ADC0ALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
 
#define SIM_SOPT7_ADC1TRGSEL_MASK   (0xF00U)
 
#define SIM_SOPT7_ADC1TRGSEL_SHIFT   (8U)
 
#define SIM_SOPT7_ADC1TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
 
#define SIM_SOPT7_ADC1PRETRGSEL_MASK   (0x1000U)
 
#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT   (12U)
 
#define SIM_SOPT7_ADC1PRETRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
 
#define SIM_SOPT7_ADC1ALTTRGEN_MASK   (0x8000U)
 
#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT   (15U)
 
#define SIM_SOPT7_ADC1ALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
 
#define SIM_SOPT7_ADC0TRGSEL_MASK   (0xFU)
 
#define SIM_SOPT7_ADC0TRGSEL_SHIFT   (0U)
 
#define SIM_SOPT7_ADC0TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
 
#define SIM_SOPT7_ADC0PRETRGSEL_MASK   (0x10U)
 
#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT   (4U)
 
#define SIM_SOPT7_ADC0PRETRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
 
#define SIM_SOPT7_ADC0ALTTRGEN_MASK   (0x80U)
 
#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT   (7U)
 
#define SIM_SOPT7_ADC0ALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
 
#define SIM_SOPT7_ADC1TRGSEL_MASK   (0xF00U)
 
#define SIM_SOPT7_ADC1TRGSEL_SHIFT   (8U)
 
#define SIM_SOPT7_ADC1TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
 
#define SIM_SOPT7_ADC1PRETRGSEL_MASK   (0x1000U)
 
#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT   (12U)
 
#define SIM_SOPT7_ADC1PRETRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
 
#define SIM_SOPT7_ADC1ALTTRGEN_MASK   (0x8000U)
 
#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT   (15U)
 
#define SIM_SOPT7_ADC1ALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
 
#define SIM_SOPT7_ADC0TRGSEL_MASK   (0xFU)
 
#define SIM_SOPT7_ADC0TRGSEL_SHIFT   (0U)
 
#define SIM_SOPT7_ADC0TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
 
#define SIM_SOPT7_ADC0PRETRGSEL_MASK   (0x10U)
 
#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT   (4U)
 
#define SIM_SOPT7_ADC0PRETRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
 
#define SIM_SOPT7_ADC0ALTTRGEN_MASK   (0x80U)
 
#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT   (7U)
 
#define SIM_SOPT7_ADC0ALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
 
#define SIM_SOPT7_ADC1TRGSEL_MASK   (0xF00U)
 
#define SIM_SOPT7_ADC1TRGSEL_SHIFT   (8U)
 
#define SIM_SOPT7_ADC1TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
 
#define SIM_SOPT7_ADC1PRETRGSEL_MASK   (0x1000U)
 
#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT   (12U)
 
#define SIM_SOPT7_ADC1PRETRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
 
#define SIM_SOPT7_ADC1ALTTRGEN_MASK   (0x8000U)
 
#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT   (15U)
 
#define SIM_SOPT7_ADC1ALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
 

SDID - System Device Identification Register

#define SIM_SDID_PINID_MASK   (0xFU)
 
#define SIM_SDID_PINID_SHIFT   (0U)
 
#define SIM_SDID_PINID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
 
#define SIM_SDID_REVID_MASK   (0xF000U)
 
#define SIM_SDID_REVID_SHIFT   (12U)
 
#define SIM_SDID_REVID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
 
#define SIM_SDID_PINID_MASK   0xFu
 
#define SIM_SDID_PINID_SHIFT   0
 
#define SIM_SDID_PINID(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
 
#define SIM_SDID_REVID_MASK   0xF000u
 
#define SIM_SDID_REVID_SHIFT   12
 
#define SIM_SDID_REVID(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
 
#define SIM_SDID_PINID_MASK   (0xFU)
 
#define SIM_SDID_PINID_SHIFT   (0U)
 
#define SIM_SDID_PINID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
 
#define SIM_SDID_DIEID_MASK   (0xF80U)
 
#define SIM_SDID_DIEID_SHIFT   (7U)
 
#define SIM_SDID_DIEID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
 
#define SIM_SDID_REVID_MASK   (0xF000U)
 
#define SIM_SDID_REVID_SHIFT   (12U)
 
#define SIM_SDID_REVID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
 
#define SIM_SDID_SERIESID_MASK   (0xF00000U)
 
#define SIM_SDID_SERIESID_SHIFT   (20U)
 
#define SIM_SDID_SERIESID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
 
#define SIM_SDID_SUBFAMID_MASK   (0xF000000U)
 
#define SIM_SDID_SUBFAMID_SHIFT   (24U)
 
#define SIM_SDID_SUBFAMID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
 
#define SIM_SDID_FAMILYID_MASK   (0xF0000000U)
 
#define SIM_SDID_FAMILYID_SHIFT   (28U)
 
#define SIM_SDID_FAMILYID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
 
#define SIM_SDID_PINID_MASK   (0xFU)
 
#define SIM_SDID_PINID_SHIFT   (0U)
 
#define SIM_SDID_PINID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
 
#define SIM_SDID_DIEID_MASK   (0xF80U)
 
#define SIM_SDID_DIEID_SHIFT   (7U)
 
#define SIM_SDID_DIEID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
 
#define SIM_SDID_REVID_MASK   (0xF000U)
 
#define SIM_SDID_REVID_SHIFT   (12U)
 
#define SIM_SDID_REVID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
 
#define SIM_SDID_SERIESID_MASK   (0xF00000U)
 
#define SIM_SDID_SERIESID_SHIFT   (20U)
 
#define SIM_SDID_SERIESID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
 
#define SIM_SDID_SUBFAMID_MASK   (0xF000000U)
 
#define SIM_SDID_SUBFAMID_SHIFT   (24U)
 
#define SIM_SDID_SUBFAMID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
 
#define SIM_SDID_FAMILYID_MASK   (0xF0000000U)
 
#define SIM_SDID_FAMILYID_SHIFT   (28U)
 
#define SIM_SDID_FAMILYID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
 
#define SIM_SDID_PINID_MASK   (0xFU)
 
#define SIM_SDID_PINID_SHIFT   (0U)
 
#define SIM_SDID_PINID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
 
#define SIM_SDID_DIEID_MASK   (0xF80U)
 
#define SIM_SDID_DIEID_SHIFT   (7U)
 
#define SIM_SDID_DIEID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
 
#define SIM_SDID_REVID_MASK   (0xF000U)
 
#define SIM_SDID_REVID_SHIFT   (12U)
 
#define SIM_SDID_REVID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
 
#define SIM_SDID_SERIESID_MASK   (0xF00000U)
 
#define SIM_SDID_SERIESID_SHIFT   (20U)
 
#define SIM_SDID_SERIESID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
 
#define SIM_SDID_SUBFAMID_MASK   (0xF000000U)
 
#define SIM_SDID_SUBFAMID_SHIFT   (24U)
 
#define SIM_SDID_SUBFAMID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
 
#define SIM_SDID_FAMILYID_MASK   (0xF0000000U)
 
#define SIM_SDID_FAMILYID_SHIFT   (28U)
 
#define SIM_SDID_FAMILYID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
 
#define SIM_SDID_PINID_MASK   (0xFU)
 
#define SIM_SDID_PINID_SHIFT   (0U)
 
#define SIM_SDID_PINID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
 
#define SIM_SDID_DIEID_MASK   (0xF80U)
 
#define SIM_SDID_DIEID_SHIFT   (7U)
 
#define SIM_SDID_DIEID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
 
#define SIM_SDID_REVID_MASK   (0xF000U)
 
#define SIM_SDID_REVID_SHIFT   (12U)
 
#define SIM_SDID_REVID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
 
#define SIM_SDID_SERIESID_MASK   (0xF00000U)
 
#define SIM_SDID_SERIESID_SHIFT   (20U)
 
#define SIM_SDID_SERIESID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
 
#define SIM_SDID_SUBFAMID_MASK   (0xF000000U)
 
#define SIM_SDID_SUBFAMID_SHIFT   (24U)
 
#define SIM_SDID_SUBFAMID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
 
#define SIM_SDID_FAMILYID_MASK   (0xF0000000U)
 
#define SIM_SDID_FAMILYID_SHIFT   (28U)
 
#define SIM_SDID_FAMILYID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
 

SDID - System Device Identification Register

#define SIM_SDID_FAMID_MASK   (0x70U)
 
#define SIM_SDID_FAMID_SHIFT   (4U)
 
#define SIM_SDID_FAMID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
 
#define SIM_SDID_FAMID_MASK   0x70u
 
#define SIM_SDID_FAMID_SHIFT   4
 
#define SIM_SDID_FAMID(x)   (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
 
#define SIM_SDID_FAMID_MASK   (0x70U)
 
#define SIM_SDID_FAMID_SHIFT   (4U)
 
#define SIM_SDID_FAMID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
 
#define SIM_SDID_FAMID_MASK   (0x70U)
 
#define SIM_SDID_FAMID_SHIFT   (4U)
 
#define SIM_SDID_FAMID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
 
#define SIM_SDID_FAMID_MASK   (0x70U)
 
#define SIM_SDID_FAMID_SHIFT   (4U)
 
#define SIM_SDID_FAMID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
 

SCGC1 - System Clock Gating Control Register 1

#define SIM_SCGC1_UART4_MASK   (0x400U)
 
#define SIM_SCGC1_UART4_SHIFT   (10U)
 
#define SIM_SCGC1_UART4(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
 
#define SIM_SCGC1_UART5_MASK   (0x800U)
 
#define SIM_SCGC1_UART5_SHIFT   (11U)
 
#define SIM_SCGC1_UART5(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
 
#define SIM_SCGC1_UART4_MASK   0x400u
 
#define SIM_SCGC1_UART4_SHIFT   10
 
#define SIM_SCGC1_UART5_MASK   0x800u
 
#define SIM_SCGC1_UART5_SHIFT   11
 
#define SIM_SCGC1_UART4_MASK   (0x400U)
 
#define SIM_SCGC1_UART4_SHIFT   (10U)
 
#define SIM_SCGC1_UART4(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
 
#define SIM_SCGC1_UART5_MASK   (0x800U)
 
#define SIM_SCGC1_UART5_SHIFT   (11U)
 
#define SIM_SCGC1_UART5(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
 
#define SIM_SCGC1_UART4_MASK   (0x400U)
 
#define SIM_SCGC1_UART4_SHIFT   (10U)
 
#define SIM_SCGC1_UART4(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
 
#define SIM_SCGC1_UART4_MASK   (0x400U)
 
#define SIM_SCGC1_UART4_SHIFT   (10U)
 
#define SIM_SCGC1_UART4(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
 
#define SIM_SCGC1_UART4_MASK   (0x400U)
 
#define SIM_SCGC1_UART4_SHIFT   (10U)
 
#define SIM_SCGC1_UART4(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
 
#define SIM_SCGC1_UART5_MASK   (0x800U)
 
#define SIM_SCGC1_UART5_SHIFT   (11U)
 
#define SIM_SCGC1_UART5(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
 
#define SIM_SCGC1_PWM1_SM0_MASK   (0x1000000U)
 
#define SIM_SCGC1_PWM1_SM0_SHIFT   (24U)
 
#define SIM_SCGC1_PWM1_SM0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM0_SHIFT)) & SIM_SCGC1_PWM1_SM0_MASK)
 
#define SIM_SCGC1_PWM1_SM1_MASK   (0x2000000U)
 
#define SIM_SCGC1_PWM1_SM1_SHIFT   (25U)
 
#define SIM_SCGC1_PWM1_SM1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM1_SHIFT)) & SIM_SCGC1_PWM1_SM1_MASK)
 
#define SIM_SCGC1_PWM1_SM2_MASK   (0x4000000U)
 
#define SIM_SCGC1_PWM1_SM2_SHIFT   (26U)
 
#define SIM_SCGC1_PWM1_SM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM2_SHIFT)) & SIM_SCGC1_PWM1_SM2_MASK)
 
#define SIM_SCGC1_PWM1_SM3_MASK   (0x8000000U)
 
#define SIM_SCGC1_PWM1_SM3_SHIFT   (27U)
 
#define SIM_SCGC1_PWM1_SM3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM3_SHIFT)) & SIM_SCGC1_PWM1_SM3_MASK)
 

SCGC2 - System Clock Gating Control Register 2

#define SIM_SCGC2_ENET_MASK   (0x1U)
 
#define SIM_SCGC2_ENET_SHIFT   (0U)
 
#define SIM_SCGC2_ENET(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
 
#define SIM_SCGC2_ENET_MASK   0x1u
 
#define SIM_SCGC2_ENET_SHIFT   0
 
#define SIM_SCGC2_ENET_MASK   (0x1U)
 
#define SIM_SCGC2_ENET_SHIFT   (0U)
 
#define SIM_SCGC2_ENET(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
 
#define SIM_SCGC2_ENET_MASK   (0x1U)
 
#define SIM_SCGC2_ENET_SHIFT   (0U)
 
#define SIM_SCGC2_ENET(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
 
#define SIM_SCGC2_ENET_MASK   (0x1U)
 
#define SIM_SCGC2_ENET_SHIFT   (0U)
 
#define SIM_SCGC2_ENET(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
 
#define SIM_SCGC2_ENET_MASK   (0x1U)
 
#define SIM_SCGC2_ENET_SHIFT   (0U)
 
#define SIM_SCGC2_ENET(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
 
#define SIM_SCGC2_HSADC1_MASK   (0x10000000U)
 
#define SIM_SCGC2_HSADC1_SHIFT   (28U)
 
#define SIM_SCGC2_HSADC1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_HSADC1_SHIFT)) & SIM_SCGC2_HSADC1_MASK)
 

SCGC2 - System Clock Gating Control Register 2

#define SIM_SCGC2_DAC0_MASK   (0x1000U)
 
#define SIM_SCGC2_DAC0_SHIFT   (12U)
 
#define SIM_SCGC2_DAC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
 
#define SIM_SCGC2_DAC1_MASK   (0x2000U)
 
#define SIM_SCGC2_DAC1_SHIFT   (13U)
 
#define SIM_SCGC2_DAC1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
 
#define SIM_SCGC2_DAC0_MASK   0x1000u
 
#define SIM_SCGC2_DAC0_SHIFT   12
 
#define SIM_SCGC2_DAC1_MASK   0x2000u
 
#define SIM_SCGC2_DAC1_SHIFT   13
 
#define SIM_SCGC2_DAC0_MASK   (0x1000U)
 
#define SIM_SCGC2_DAC0_SHIFT   (12U)
 
#define SIM_SCGC2_DAC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
 
#define SIM_SCGC2_DAC1_MASK   (0x2000U)
 
#define SIM_SCGC2_DAC1_SHIFT   (13U)
 
#define SIM_SCGC2_DAC1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
 
#define SIM_SCGC2_LPUART0_MASK   (0x10U)
 
#define SIM_SCGC2_LPUART0_SHIFT   (4U)
 
#define SIM_SCGC2_LPUART0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
 
#define SIM_SCGC2_TPM1_MASK   (0x200U)
 
#define SIM_SCGC2_TPM1_SHIFT   (9U)
 
#define SIM_SCGC2_TPM1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
 
#define SIM_SCGC2_TPM2_MASK   (0x400U)
 
#define SIM_SCGC2_TPM2_SHIFT   (10U)
 
#define SIM_SCGC2_TPM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
 
#define SIM_SCGC2_DAC0_MASK   (0x1000U)
 
#define SIM_SCGC2_DAC0_SHIFT   (12U)
 
#define SIM_SCGC2_DAC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
 
#define SIM_SCGC2_DAC1_MASK   (0x2000U)
 
#define SIM_SCGC2_DAC1_SHIFT   (13U)
 
#define SIM_SCGC2_DAC1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
 
#define SIM_SCGC2_LPUART0_MASK   (0x10U)
 
#define SIM_SCGC2_LPUART0_SHIFT   (4U)
 
#define SIM_SCGC2_LPUART0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
 
#define SIM_SCGC2_TPM1_MASK   (0x200U)
 
#define SIM_SCGC2_TPM1_SHIFT   (9U)
 
#define SIM_SCGC2_TPM1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
 
#define SIM_SCGC2_TPM2_MASK   (0x400U)
 
#define SIM_SCGC2_TPM2_SHIFT   (10U)
 
#define SIM_SCGC2_TPM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
 
#define SIM_SCGC2_DAC0_MASK   (0x1000U)
 
#define SIM_SCGC2_DAC0_SHIFT   (12U)
 
#define SIM_SCGC2_DAC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
 
#define SIM_SCGC2_DAC1_MASK   (0x2000U)
 
#define SIM_SCGC2_DAC1_SHIFT   (13U)
 
#define SIM_SCGC2_DAC1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
 

SCGC3 - System Clock Gating Control Register 3

#define SIM_SCGC3_RNGA_MASK   (0x1U)
 
#define SIM_SCGC3_RNGA_SHIFT   (0U)
 
#define SIM_SCGC3_RNGA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
 
#define SIM_SCGC3_FLEXCAN1_MASK   (0x10U)
 
#define SIM_SCGC3_FLEXCAN1_SHIFT   (4U)
 
#define SIM_SCGC3_FLEXCAN1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
 
#define SIM_SCGC3_SDHC_MASK   (0x20000U)
 
#define SIM_SCGC3_SDHC_SHIFT   (17U)
 
#define SIM_SCGC3_SDHC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
 
#define SIM_SCGC3_FTM2_MASK   (0x1000000U)
 
#define SIM_SCGC3_FTM2_SHIFT   (24U)
 
#define SIM_SCGC3_FTM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
 
#define SIM_SCGC3_ADC1_MASK   (0x8000000U)
 
#define SIM_SCGC3_ADC1_SHIFT   (27U)
 
#define SIM_SCGC3_ADC1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
 
#define SIM_SCGC3_FLEXCAN1_MASK   0x10u
 
#define SIM_SCGC3_FLEXCAN1_SHIFT   4
 
#define SIM_SCGC3_SDHC_MASK   0x20000u
 
#define SIM_SCGC3_SDHC_SHIFT   17
 
#define SIM_SCGC3_FTM2_MASK   0x1000000u
 
#define SIM_SCGC3_FTM2_SHIFT   24
 
#define SIM_SCGC3_ADC1_MASK   0x8000000u
 
#define SIM_SCGC3_ADC1_SHIFT   27
 
#define SIM_SCGC3_RNGA_MASK   (0x1U)
 
#define SIM_SCGC3_RNGA_SHIFT   (0U)
 
#define SIM_SCGC3_RNGA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
 
#define SIM_SCGC3_SDHC_MASK   (0x20000U)
 
#define SIM_SCGC3_SDHC_SHIFT   (17U)
 
#define SIM_SCGC3_SDHC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
 
#define SIM_SCGC3_FTM2_MASK   (0x1000000U)
 
#define SIM_SCGC3_FTM2_SHIFT   (24U)
 
#define SIM_SCGC3_FTM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
 
#define SIM_SCGC3_FTM3_MASK   (0x2000000U)
 
#define SIM_SCGC3_FTM3_SHIFT   (25U)
 
#define SIM_SCGC3_FTM3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
 
#define SIM_SCGC3_ADC1_MASK   (0x8000000U)
 
#define SIM_SCGC3_ADC1_SHIFT   (27U)
 
#define SIM_SCGC3_ADC1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
 
#define SIM_SCGC3_RNGA_MASK   (0x1U)
 
#define SIM_SCGC3_RNGA_SHIFT   (0U)
 
#define SIM_SCGC3_RNGA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
 
#define SIM_SCGC3_USBHS_MASK   (0x2U)
 
#define SIM_SCGC3_USBHS_SHIFT   (1U)
 
#define SIM_SCGC3_USBHS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
 
#define SIM_SCGC3_USBHSPHY_MASK   (0x4U)
 
#define SIM_SCGC3_USBHSPHY_SHIFT   (2U)
 
#define SIM_SCGC3_USBHSPHY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
 
#define SIM_SCGC3_USBHSDCD_MASK   (0x8U)
 
#define SIM_SCGC3_USBHSDCD_SHIFT   (3U)
 
#define SIM_SCGC3_USBHSDCD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
 
#define SIM_SCGC3_FLEXCAN1_MASK   (0x10U)
 
#define SIM_SCGC3_FLEXCAN1_SHIFT   (4U)
 
#define SIM_SCGC3_FLEXCAN1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
 
#define SIM_SCGC3_SDHC_MASK   (0x20000U)
 
#define SIM_SCGC3_SDHC_SHIFT   (17U)
 
#define SIM_SCGC3_SDHC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
 
#define SIM_SCGC3_FTM2_MASK   (0x1000000U)
 
#define SIM_SCGC3_FTM2_SHIFT   (24U)
 
#define SIM_SCGC3_FTM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
 
#define SIM_SCGC3_FTM3_MASK   (0x2000000U)
 
#define SIM_SCGC3_FTM3_SHIFT   (25U)
 
#define SIM_SCGC3_FTM3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
 
#define SIM_SCGC3_ADC1_MASK   (0x8000000U)
 
#define SIM_SCGC3_ADC1_SHIFT   (27U)
 
#define SIM_SCGC3_ADC1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
 
#define SIM_SCGC3_RNGA_MASK   (0x1U)
 
#define SIM_SCGC3_RNGA_SHIFT   (0U)
 
#define SIM_SCGC3_RNGA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
 
#define SIM_SCGC3_USBHS_MASK   (0x2U)
 
#define SIM_SCGC3_USBHS_SHIFT   (1U)
 
#define SIM_SCGC3_USBHS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
 
#define SIM_SCGC3_USBHSPHY_MASK   (0x4U)
 
#define SIM_SCGC3_USBHSPHY_SHIFT   (2U)
 
#define SIM_SCGC3_USBHSPHY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
 
#define SIM_SCGC3_USBHSDCD_MASK   (0x8U)
 
#define SIM_SCGC3_USBHSDCD_SHIFT   (3U)
 
#define SIM_SCGC3_USBHSDCD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
 
#define SIM_SCGC3_FLEXCAN1_MASK   (0x10U)
 
#define SIM_SCGC3_FLEXCAN1_SHIFT   (4U)
 
#define SIM_SCGC3_FLEXCAN1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
 
#define SIM_SCGC3_SDHC_MASK   (0x20000U)
 
#define SIM_SCGC3_SDHC_SHIFT   (17U)
 
#define SIM_SCGC3_SDHC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
 
#define SIM_SCGC3_FTM2_MASK   (0x1000000U)
 
#define SIM_SCGC3_FTM2_SHIFT   (24U)
 
#define SIM_SCGC3_FTM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
 
#define SIM_SCGC3_FTM3_MASK   (0x2000000U)
 
#define SIM_SCGC3_FTM3_SHIFT   (25U)
 
#define SIM_SCGC3_FTM3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
 
#define SIM_SCGC3_ADC1_MASK   (0x8000000U)
 
#define SIM_SCGC3_ADC1_SHIFT   (27U)
 
#define SIM_SCGC3_ADC1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
 

SCGC3 - System Clock Gating Control Register 3

#define SIM_SCGC3_SPI2_MASK   (0x1000U)
 
#define SIM_SCGC3_SPI2_SHIFT   (12U)
 
#define SIM_SCGC3_SPI2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
 
#define SIM_SCGC3_SPI2_MASK   0x1000u
 
#define SIM_SCGC3_SPI2_SHIFT   12
 
#define SIM_SCGC3_SPI2_MASK   (0x1000U)
 
#define SIM_SCGC3_SPI2_SHIFT   (12U)
 
#define SIM_SCGC3_SPI2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
 
#define SIM_SCGC3_SPI2_MASK   (0x1000U)
 
#define SIM_SCGC3_SPI2_SHIFT   (12U)
 
#define SIM_SCGC3_SPI2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
 
#define SIM_SCGC3_SPI2_MASK   (0x1000U)
 
#define SIM_SCGC3_SPI2_SHIFT   (12U)
 
#define SIM_SCGC3_SPI2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
 
#define SIM_SCGC3_TRNG_MASK   (0x1U)
 
#define SIM_SCGC3_TRNG_SHIFT   (0U)
 
#define SIM_SCGC3_TRNG(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_TRNG_SHIFT)) & SIM_SCGC3_TRNG_MASK)
 
#define SIM_SCGC3_FLEXCAN2_MASK   (0x10U)
 
#define SIM_SCGC3_FLEXCAN2_SHIFT   (4U)
 
#define SIM_SCGC3_FLEXCAN2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN2_SHIFT)) & SIM_SCGC3_FLEXCAN2_MASK)
 
#define SIM_SCGC3_SPI2_MASK   (0x1000U)
 
#define SIM_SCGC3_SPI2_SHIFT   (12U)
 
#define SIM_SCGC3_SPI2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
 

SCGC4 - System Clock Gating Control Register 4

#define SIM_SCGC4_EWM_MASK   (0x2U)
 
#define SIM_SCGC4_EWM_SHIFT   (1U)
 
#define SIM_SCGC4_EWM(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
 
#define SIM_SCGC4_I2C0_MASK   (0x40U)
 
#define SIM_SCGC4_I2C0_SHIFT   (6U)
 
#define SIM_SCGC4_I2C0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
 
#define SIM_SCGC4_I2C1_MASK   (0x80U)
 
#define SIM_SCGC4_I2C1_SHIFT   (7U)
 
#define SIM_SCGC4_I2C1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
 
#define SIM_SCGC4_UART0_MASK   (0x400U)
 
#define SIM_SCGC4_UART0_SHIFT   (10U)
 
#define SIM_SCGC4_UART0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
 
#define SIM_SCGC4_UART1_MASK   (0x800U)
 
#define SIM_SCGC4_UART1_SHIFT   (11U)
 
#define SIM_SCGC4_UART1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
 
#define SIM_SCGC4_UART2_MASK   (0x1000U)
 
#define SIM_SCGC4_UART2_SHIFT   (12U)
 
#define SIM_SCGC4_UART2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
 
#define SIM_SCGC4_UART3_MASK   (0x2000U)
 
#define SIM_SCGC4_UART3_SHIFT   (13U)
 
#define SIM_SCGC4_UART3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
 
#define SIM_SCGC4_CMP_MASK   (0x80000U)
 
#define SIM_SCGC4_CMP_SHIFT   (19U)
 
#define SIM_SCGC4_CMP(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
 
#define SIM_SCGC4_EWM_MASK   0x2u
 
#define SIM_SCGC4_EWM_SHIFT   1
 
#define SIM_SCGC4_I2C0_MASK   0x40u
 
#define SIM_SCGC4_I2C0_SHIFT   6
 
#define SIM_SCGC4_I2C1_MASK   0x80u
 
#define SIM_SCGC4_I2C1_SHIFT   7
 
#define SIM_SCGC4_UART0_MASK   0x400u
 
#define SIM_SCGC4_UART0_SHIFT   10
 
#define SIM_SCGC4_UART1_MASK   0x800u
 
#define SIM_SCGC4_UART1_SHIFT   11
 
#define SIM_SCGC4_UART2_MASK   0x1000u
 
#define SIM_SCGC4_UART2_SHIFT   12
 
#define SIM_SCGC4_UART3_MASK   0x2000u
 
#define SIM_SCGC4_UART3_SHIFT   13
 
#define SIM_SCGC4_CMP_MASK   0x80000u
 
#define SIM_SCGC4_CMP_SHIFT   19
 
#define SIM_SCGC4_EWM_MASK   (0x2U)
 
#define SIM_SCGC4_EWM_SHIFT   (1U)
 
#define SIM_SCGC4_EWM(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
 
#define SIM_SCGC4_I2C0_MASK   (0x40U)
 
#define SIM_SCGC4_I2C0_SHIFT   (6U)
 
#define SIM_SCGC4_I2C0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
 
#define SIM_SCGC4_I2C1_MASK   (0x80U)
 
#define SIM_SCGC4_I2C1_SHIFT   (7U)
 
#define SIM_SCGC4_I2C1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
 
#define SIM_SCGC4_UART0_MASK   (0x400U)
 
#define SIM_SCGC4_UART0_SHIFT   (10U)
 
#define SIM_SCGC4_UART0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
 
#define SIM_SCGC4_UART1_MASK   (0x800U)
 
#define SIM_SCGC4_UART1_SHIFT   (11U)
 
#define SIM_SCGC4_UART1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
 
#define SIM_SCGC4_UART2_MASK   (0x1000U)
 
#define SIM_SCGC4_UART2_SHIFT   (12U)
 
#define SIM_SCGC4_UART2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
 
#define SIM_SCGC4_UART3_MASK   (0x2000U)
 
#define SIM_SCGC4_UART3_SHIFT   (13U)
 
#define SIM_SCGC4_UART3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
 
#define SIM_SCGC4_CMP_MASK   (0x80000U)
 
#define SIM_SCGC4_CMP_SHIFT   (19U)
 
#define SIM_SCGC4_CMP(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
 
#define SIM_SCGC4_EWM_MASK   (0x2U)
 
#define SIM_SCGC4_EWM_SHIFT   (1U)
 
#define SIM_SCGC4_EWM(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
 
#define SIM_SCGC4_I2C0_MASK   (0x40U)
 
#define SIM_SCGC4_I2C0_SHIFT   (6U)
 
#define SIM_SCGC4_I2C0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
 
#define SIM_SCGC4_I2C1_MASK   (0x80U)
 
#define SIM_SCGC4_I2C1_SHIFT   (7U)
 
#define SIM_SCGC4_I2C1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
 
#define SIM_SCGC4_UART0_MASK   (0x400U)
 
#define SIM_SCGC4_UART0_SHIFT   (10U)
 
#define SIM_SCGC4_UART0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
 
#define SIM_SCGC4_UART1_MASK   (0x800U)
 
#define SIM_SCGC4_UART1_SHIFT   (11U)
 
#define SIM_SCGC4_UART1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
 
#define SIM_SCGC4_UART2_MASK   (0x1000U)
 
#define SIM_SCGC4_UART2_SHIFT   (12U)
 
#define SIM_SCGC4_UART2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
 
#define SIM_SCGC4_UART3_MASK   (0x2000U)
 
#define SIM_SCGC4_UART3_SHIFT   (13U)
 
#define SIM_SCGC4_UART3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
 
#define SIM_SCGC4_CMP_MASK   (0x80000U)
 
#define SIM_SCGC4_CMP_SHIFT   (19U)
 
#define SIM_SCGC4_CMP(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
 
#define SIM_SCGC4_EWM_MASK   (0x2U)
 
#define SIM_SCGC4_EWM_SHIFT   (1U)
 
#define SIM_SCGC4_EWM(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
 
#define SIM_SCGC4_I2C0_MASK   (0x40U)
 
#define SIM_SCGC4_I2C0_SHIFT   (6U)
 
#define SIM_SCGC4_I2C0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
 
#define SIM_SCGC4_I2C1_MASK   (0x80U)
 
#define SIM_SCGC4_I2C1_SHIFT   (7U)
 
#define SIM_SCGC4_I2C1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
 
#define SIM_SCGC4_UART0_MASK   (0x400U)
 
#define SIM_SCGC4_UART0_SHIFT   (10U)
 
#define SIM_SCGC4_UART0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
 
#define SIM_SCGC4_UART1_MASK   (0x800U)
 
#define SIM_SCGC4_UART1_SHIFT   (11U)
 
#define SIM_SCGC4_UART1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
 
#define SIM_SCGC4_UART2_MASK   (0x1000U)
 
#define SIM_SCGC4_UART2_SHIFT   (12U)
 
#define SIM_SCGC4_UART2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
 
#define SIM_SCGC4_UART3_MASK   (0x2000U)
 
#define SIM_SCGC4_UART3_SHIFT   (13U)
 
#define SIM_SCGC4_UART3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
 
#define SIM_SCGC4_CMP_MASK   (0x80000U)
 
#define SIM_SCGC4_CMP_SHIFT   (19U)
 
#define SIM_SCGC4_CMP(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
 
#define SIM_SCGC4_EWM_MASK   (0x2U)
 
#define SIM_SCGC4_EWM_SHIFT   (1U)
 
#define SIM_SCGC4_EWM(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
 
#define SIM_SCGC4_I2C0_MASK   (0x40U)
 
#define SIM_SCGC4_I2C0_SHIFT   (6U)
 
#define SIM_SCGC4_I2C0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
 
#define SIM_SCGC4_I2C1_MASK   (0x80U)
 
#define SIM_SCGC4_I2C1_SHIFT   (7U)
 
#define SIM_SCGC4_I2C1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
 
#define SIM_SCGC4_UART0_MASK   (0x400U)
 
#define SIM_SCGC4_UART0_SHIFT   (10U)
 
#define SIM_SCGC4_UART0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
 
#define SIM_SCGC4_UART1_MASK   (0x800U)
 
#define SIM_SCGC4_UART1_SHIFT   (11U)
 
#define SIM_SCGC4_UART1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
 
#define SIM_SCGC4_UART2_MASK   (0x1000U)
 
#define SIM_SCGC4_UART2_SHIFT   (12U)
 
#define SIM_SCGC4_UART2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
 
#define SIM_SCGC4_UART3_MASK   (0x2000U)
 
#define SIM_SCGC4_UART3_SHIFT   (13U)
 
#define SIM_SCGC4_UART3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
 
#define SIM_SCGC4_CMP_MASK   (0x80000U)
 
#define SIM_SCGC4_CMP_SHIFT   (19U)
 
#define SIM_SCGC4_CMP(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
 
#define SIM_SCGC4_PWM0_SM0_MASK   (0x1000000U)
 
#define SIM_SCGC4_PWM0_SM0_SHIFT   (24U)
 
#define SIM_SCGC4_PWM0_SM0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM0_SHIFT)) & SIM_SCGC4_PWM0_SM0_MASK)
 
#define SIM_SCGC4_PWM0_SM1_MASK   (0x2000000U)
 
#define SIM_SCGC4_PWM0_SM1_SHIFT   (25U)
 
#define SIM_SCGC4_PWM0_SM1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM1_SHIFT)) & SIM_SCGC4_PWM0_SM1_MASK)
 
#define SIM_SCGC4_PWM0_SM2_MASK   (0x4000000U)
 
#define SIM_SCGC4_PWM0_SM2_SHIFT   (26U)
 
#define SIM_SCGC4_PWM0_SM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM2_SHIFT)) & SIM_SCGC4_PWM0_SM2_MASK)
 
#define SIM_SCGC4_PWM0_SM3_MASK   (0x8000000U)
 
#define SIM_SCGC4_PWM0_SM3_SHIFT   (27U)
 
#define SIM_SCGC4_PWM0_SM3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM3_SHIFT)) & SIM_SCGC4_PWM0_SM3_MASK)
 

SCGC4 - System Clock Gating Control Register 4

#define SIM_SCGC4_CMT_MASK   (0x4U)
 
#define SIM_SCGC4_CMT_SHIFT   (2U)
 
#define SIM_SCGC4_CMT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
 
#define SIM_SCGC4_USBOTG_MASK   (0x40000U)
 
#define SIM_SCGC4_USBOTG_SHIFT   (18U)
 
#define SIM_SCGC4_USBOTG(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
 
#define SIM_SCGC4_VREF_MASK   (0x100000U)
 
#define SIM_SCGC4_VREF_SHIFT   (20U)
 
#define SIM_SCGC4_VREF(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
 
#define SIM_SCGC4_CMT_MASK   0x4u
 
#define SIM_SCGC4_CMT_SHIFT   2
 
#define SIM_SCGC4_USBOTG_MASK   0x40000u
 
#define SIM_SCGC4_USBOTG_SHIFT   18
 
#define SIM_SCGC4_VREF_MASK   0x100000u
 
#define SIM_SCGC4_VREF_SHIFT   20
 
#define SIM_SCGC4_CMT_MASK   (0x4U)
 
#define SIM_SCGC4_CMT_SHIFT   (2U)
 
#define SIM_SCGC4_CMT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
 
#define SIM_SCGC4_USBOTG_MASK   (0x40000U)
 
#define SIM_SCGC4_USBOTG_SHIFT   (18U)
 
#define SIM_SCGC4_USBOTG(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
 
#define SIM_SCGC4_VREF_MASK   (0x100000U)
 
#define SIM_SCGC4_VREF_SHIFT   (20U)
 
#define SIM_SCGC4_VREF(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
 
#define SIM_SCGC4_CMT_MASK   (0x4U)
 
#define SIM_SCGC4_CMT_SHIFT   (2U)
 
#define SIM_SCGC4_CMT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
 
#define SIM_SCGC4_USBOTG_MASK   (0x40000U)
 
#define SIM_SCGC4_USBOTG_SHIFT   (18U)
 
#define SIM_SCGC4_USBOTG(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
 
#define SIM_SCGC4_VREF_MASK   (0x100000U)
 
#define SIM_SCGC4_VREF_SHIFT   (20U)
 
#define SIM_SCGC4_VREF(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
 
#define SIM_SCGC4_CMT_MASK   (0x4U)
 
#define SIM_SCGC4_CMT_SHIFT   (2U)
 
#define SIM_SCGC4_CMT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
 
#define SIM_SCGC4_USBOTG_MASK   (0x40000U)
 
#define SIM_SCGC4_USBOTG_SHIFT   (18U)
 
#define SIM_SCGC4_USBOTG(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
 
#define SIM_SCGC4_VREF_MASK   (0x100000U)
 
#define SIM_SCGC4_VREF_SHIFT   (20U)
 
#define SIM_SCGC4_VREF(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
 

SCGC4 - System Clock Gating Control Register 4

#define SIM_SCGC4_LLWU_MASK   (0x10000000U)
 
#define SIM_SCGC4_LLWU_SHIFT   (28U)
 
#define SIM_SCGC4_LLWU(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_LLWU_SHIFT)) & SIM_SCGC4_LLWU_MASK)
 

SCGC5 - System Clock Gating Control Register 5

#define SIM_SCGC5_LPTIMER_MASK   (0x1U)
 
#define SIM_SCGC5_LPTIMER_SHIFT   (0U)
 
#define SIM_SCGC5_LPTIMER(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTIMER_SHIFT)) & SIM_SCGC5_LPTIMER_MASK)
 

SCGC5 - System Clock Gating Control Register 5

#define SIM_SCGC5_TSI_MASK   (0x20U)
 
#define SIM_SCGC5_TSI_SHIFT   (5U)
 
#define SIM_SCGC5_TSI(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
 
#define SIM_SCGC5_TSI_MASK   0x20u
 
#define SIM_SCGC5_TSI_SHIFT   5
 
#define SIM_SCGC5_TSI_MASK   (0x20U)
 
#define SIM_SCGC5_TSI_SHIFT   (5U)
 
#define SIM_SCGC5_TSI(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
 
#define SIM_SCGC5_TSI_MASK   (0x20U)
 
#define SIM_SCGC5_TSI_SHIFT   (5U)
 
#define SIM_SCGC5_TSI(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
 

SCGC5 - System Clock Gating Control Register 5

#define SIM_SCGC5_PORTA_MASK   (0x200U)
 
#define SIM_SCGC5_PORTA_SHIFT   (9U)
 
#define SIM_SCGC5_PORTA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
 
#define SIM_SCGC5_PORTB_MASK   (0x400U)
 
#define SIM_SCGC5_PORTB_SHIFT   (10U)
 
#define SIM_SCGC5_PORTB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
 
#define SIM_SCGC5_PORTC_MASK   (0x800U)
 
#define SIM_SCGC5_PORTC_SHIFT   (11U)
 
#define SIM_SCGC5_PORTC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
 
#define SIM_SCGC5_PORTD_MASK   (0x1000U)
 
#define SIM_SCGC5_PORTD_SHIFT   (12U)
 
#define SIM_SCGC5_PORTD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
 
#define SIM_SCGC5_PORTE_MASK   (0x2000U)
 
#define SIM_SCGC5_PORTE_SHIFT   (13U)
 
#define SIM_SCGC5_PORTE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
 
#define SIM_SCGC5_PORTA_MASK   0x200u
 
#define SIM_SCGC5_PORTA_SHIFT   9
 
#define SIM_SCGC5_PORTB_MASK   0x400u
 
#define SIM_SCGC5_PORTB_SHIFT   10
 
#define SIM_SCGC5_PORTC_MASK   0x800u
 
#define SIM_SCGC5_PORTC_SHIFT   11
 
#define SIM_SCGC5_PORTD_MASK   0x1000u
 
#define SIM_SCGC5_PORTD_SHIFT   12
 
#define SIM_SCGC5_PORTE_MASK   0x2000u
 
#define SIM_SCGC5_PORTE_SHIFT   13
 
#define SIM_SCGC5_LPTMR_MASK   (0x1U)
 
#define SIM_SCGC5_LPTMR_SHIFT   (0U)
 
#define SIM_SCGC5_LPTMR(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
 
#define SIM_SCGC5_PORTA_MASK   (0x200U)
 
#define SIM_SCGC5_PORTA_SHIFT   (9U)
 
#define SIM_SCGC5_PORTA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
 
#define SIM_SCGC5_PORTB_MASK   (0x400U)
 
#define SIM_SCGC5_PORTB_SHIFT   (10U)
 
#define SIM_SCGC5_PORTB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
 
#define SIM_SCGC5_PORTC_MASK   (0x800U)
 
#define SIM_SCGC5_PORTC_SHIFT   (11U)
 
#define SIM_SCGC5_PORTC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
 
#define SIM_SCGC5_PORTD_MASK   (0x1000U)
 
#define SIM_SCGC5_PORTD_SHIFT   (12U)
 
#define SIM_SCGC5_PORTD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
 
#define SIM_SCGC5_PORTE_MASK   (0x2000U)
 
#define SIM_SCGC5_PORTE_SHIFT   (13U)
 
#define SIM_SCGC5_PORTE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
 
#define SIM_SCGC5_LPTMR_MASK   (0x1U)
 
#define SIM_SCGC5_LPTMR_SHIFT   (0U)
 
#define SIM_SCGC5_LPTMR(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
 
#define SIM_SCGC5_PORTA_MASK   (0x200U)
 
#define SIM_SCGC5_PORTA_SHIFT   (9U)
 
#define SIM_SCGC5_PORTA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
 
#define SIM_SCGC5_PORTB_MASK   (0x400U)
 
#define SIM_SCGC5_PORTB_SHIFT   (10U)
 
#define SIM_SCGC5_PORTB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
 
#define SIM_SCGC5_PORTC_MASK   (0x800U)
 
#define SIM_SCGC5_PORTC_SHIFT   (11U)
 
#define SIM_SCGC5_PORTC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
 
#define SIM_SCGC5_PORTD_MASK   (0x1000U)
 
#define SIM_SCGC5_PORTD_SHIFT   (12U)
 
#define SIM_SCGC5_PORTD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
 
#define SIM_SCGC5_PORTE_MASK   (0x2000U)
 
#define SIM_SCGC5_PORTE_SHIFT   (13U)
 
#define SIM_SCGC5_PORTE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
 
#define SIM_SCGC5_LPTMR_MASK   (0x1U)
 
#define SIM_SCGC5_LPTMR_SHIFT   (0U)
 
#define SIM_SCGC5_LPTMR(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
 
#define SIM_SCGC5_PORTA_MASK   (0x200U)
 
#define SIM_SCGC5_PORTA_SHIFT   (9U)
 
#define SIM_SCGC5_PORTA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
 
#define SIM_SCGC5_PORTB_MASK   (0x400U)
 
#define SIM_SCGC5_PORTB_SHIFT   (10U)
 
#define SIM_SCGC5_PORTB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
 
#define SIM_SCGC5_PORTC_MASK   (0x800U)
 
#define SIM_SCGC5_PORTC_SHIFT   (11U)
 
#define SIM_SCGC5_PORTC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
 
#define SIM_SCGC5_PORTD_MASK   (0x1000U)
 
#define SIM_SCGC5_PORTD_SHIFT   (12U)
 
#define SIM_SCGC5_PORTD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
 
#define SIM_SCGC5_PORTE_MASK   (0x2000U)
 
#define SIM_SCGC5_PORTE_SHIFT   (13U)
 
#define SIM_SCGC5_PORTE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
 
#define SIM_SCGC5_LPTMR_MASK   (0x1U)
 
#define SIM_SCGC5_LPTMR_SHIFT   (0U)
 
#define SIM_SCGC5_LPTMR(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
 
#define SIM_SCGC5_PORTA_MASK   (0x200U)
 
#define SIM_SCGC5_PORTA_SHIFT   (9U)
 
#define SIM_SCGC5_PORTA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
 
#define SIM_SCGC5_PORTB_MASK   (0x400U)
 
#define SIM_SCGC5_PORTB_SHIFT   (10U)
 
#define SIM_SCGC5_PORTB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
 
#define SIM_SCGC5_PORTC_MASK   (0x800U)
 
#define SIM_SCGC5_PORTC_SHIFT   (11U)
 
#define SIM_SCGC5_PORTC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
 
#define SIM_SCGC5_PORTD_MASK   (0x1000U)
 
#define SIM_SCGC5_PORTD_SHIFT   (12U)
 
#define SIM_SCGC5_PORTD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
 
#define SIM_SCGC5_PORTE_MASK   (0x2000U)
 
#define SIM_SCGC5_PORTE_SHIFT   (13U)
 
#define SIM_SCGC5_PORTE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
 
#define SIM_SCGC5_ENC_MASK   (0x200000U)
 
#define SIM_SCGC5_ENC_SHIFT   (21U)
 
#define SIM_SCGC5_ENC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_ENC_SHIFT)) & SIM_SCGC5_ENC_MASK)
 
#define SIM_SCGC5_XBARA_MASK   (0x2000000U)
 
#define SIM_SCGC5_XBARA_SHIFT   (25U)
 
#define SIM_SCGC5_XBARA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_XBARA_SHIFT)) & SIM_SCGC5_XBARA_MASK)
 
#define SIM_SCGC5_XBARB_MASK   (0x4000000U)
 
#define SIM_SCGC5_XBARB_SHIFT   (26U)
 
#define SIM_SCGC5_XBARB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_XBARB_SHIFT)) & SIM_SCGC5_XBARB_MASK)
 
#define SIM_SCGC5_AOI_MASK   (0x8000000U)
 
#define SIM_SCGC5_AOI_SHIFT   (27U)
 
#define SIM_SCGC5_AOI(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_AOI_SHIFT)) & SIM_SCGC5_AOI_MASK)
 
#define SIM_SCGC5_HSADC0_MASK   (0x10000000U)
 
#define SIM_SCGC5_HSADC0_SHIFT   (28U)
 
#define SIM_SCGC5_HSADC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_HSADC0_SHIFT)) & SIM_SCGC5_HSADC0_MASK)
 

SCGC6 - System Clock Gating Control Register 6

#define SIM_SCGC6_FTFL_MASK   (0x1U)
 
#define SIM_SCGC6_FTFL_SHIFT   (0U)
 
#define SIM_SCGC6_FTFL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTFL_SHIFT)) & SIM_SCGC6_FTFL_MASK)
 

SCGC6 - System Clock Gating Control Register 6

#define SIM_SCGC6_DMAMUX_MASK   (0x2U)
 
#define SIM_SCGC6_DMAMUX_SHIFT   (1U)
 
#define SIM_SCGC6_DMAMUX(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
 
#define SIM_SCGC6_FLEXCAN0_MASK   (0x10U)
 
#define SIM_SCGC6_FLEXCAN0_SHIFT   (4U)
 
#define SIM_SCGC6_FLEXCAN0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
 
#define SIM_SCGC6_SPI0_MASK   (0x1000U)
 
#define SIM_SCGC6_SPI0_SHIFT   (12U)
 
#define SIM_SCGC6_SPI0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
 
#define SIM_SCGC6_SPI1_MASK   (0x2000U)
 
#define SIM_SCGC6_SPI1_SHIFT   (13U)
 
#define SIM_SCGC6_SPI1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
 
#define SIM_SCGC6_CRC_MASK   (0x40000U)
 
#define SIM_SCGC6_CRC_SHIFT   (18U)
 
#define SIM_SCGC6_CRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
 
#define SIM_SCGC6_PIT_MASK   (0x800000U)
 
#define SIM_SCGC6_PIT_SHIFT   (23U)
 
#define SIM_SCGC6_PIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
 
#define SIM_SCGC6_FTM0_MASK   (0x1000000U)
 
#define SIM_SCGC6_FTM0_SHIFT   (24U)
 
#define SIM_SCGC6_FTM0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
 
#define SIM_SCGC6_FTM1_MASK   (0x2000000U)
 
#define SIM_SCGC6_FTM1_SHIFT   (25U)
 
#define SIM_SCGC6_FTM1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
 
#define SIM_SCGC6_ADC0_MASK   (0x8000000U)
 
#define SIM_SCGC6_ADC0_SHIFT   (27U)
 
#define SIM_SCGC6_ADC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
 
#define SIM_SCGC6_DMAMUX_MASK   0x2u
 
#define SIM_SCGC6_DMAMUX_SHIFT   1
 
#define SIM_SCGC6_FLEXCAN0_MASK   0x10u
 
#define SIM_SCGC6_FLEXCAN0_SHIFT   4
 
#define SIM_SCGC6_SPI1_MASK   0x2000u
 
#define SIM_SCGC6_SPI1_SHIFT   13
 
#define SIM_SCGC6_CRC_MASK   0x40000u
 
#define SIM_SCGC6_CRC_SHIFT   18
 
#define SIM_SCGC6_PIT_MASK   0x800000u
 
#define SIM_SCGC6_PIT_SHIFT   23
 
#define SIM_SCGC6_FTM0_MASK   0x1000000u
 
#define SIM_SCGC6_FTM0_SHIFT   24
 
#define SIM_SCGC6_FTM1_MASK   0x2000000u
 
#define SIM_SCGC6_FTM1_SHIFT   25
 
#define SIM_SCGC6_ADC0_MASK   0x8000000u
 
#define SIM_SCGC6_ADC0_SHIFT   27
 
#define SIM_SCGC6_FTF_MASK   (0x1U)
 
#define SIM_SCGC6_FTF_SHIFT   (0U)
 
#define SIM_SCGC6_FTF(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
 
#define SIM_SCGC6_DMAMUX_MASK   (0x2U)
 
#define SIM_SCGC6_DMAMUX_SHIFT   (1U)
 
#define SIM_SCGC6_DMAMUX(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
 
#define SIM_SCGC6_FLEXCAN0_MASK   (0x10U)
 
#define SIM_SCGC6_FLEXCAN0_SHIFT   (4U)
 
#define SIM_SCGC6_FLEXCAN0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
 
#define SIM_SCGC6_SPI0_MASK   (0x1000U)
 
#define SIM_SCGC6_SPI0_SHIFT   (12U)
 
#define SIM_SCGC6_SPI0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
 
#define SIM_SCGC6_SPI1_MASK   (0x2000U)
 
#define SIM_SCGC6_SPI1_SHIFT   (13U)
 
#define SIM_SCGC6_SPI1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
 
#define SIM_SCGC6_CRC_MASK   (0x40000U)
 
#define SIM_SCGC6_CRC_SHIFT   (18U)
 
#define SIM_SCGC6_CRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
 
#define SIM_SCGC6_PIT_MASK   (0x800000U)
 
#define SIM_SCGC6_PIT_SHIFT   (23U)
 
#define SIM_SCGC6_PIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
 
#define SIM_SCGC6_FTM0_MASK   (0x1000000U)
 
#define SIM_SCGC6_FTM0_SHIFT   (24U)
 
#define SIM_SCGC6_FTM0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
 
#define SIM_SCGC6_FTM1_MASK   (0x2000000U)
 
#define SIM_SCGC6_FTM1_SHIFT   (25U)
 
#define SIM_SCGC6_FTM1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
 
#define SIM_SCGC6_FTM2_MASK   (0x4000000U)
 
#define SIM_SCGC6_FTM2_SHIFT   (26U)
 
#define SIM_SCGC6_FTM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
 
#define SIM_SCGC6_ADC0_MASK   (0x8000000U)
 
#define SIM_SCGC6_ADC0_SHIFT   (27U)
 
#define SIM_SCGC6_ADC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
 
#define SIM_SCGC6_DAC0_MASK   (0x80000000U)
 
#define SIM_SCGC6_DAC0_SHIFT   (31U)
 
#define SIM_SCGC6_DAC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
 
#define SIM_SCGC6_FTF_MASK   (0x1U)
 
#define SIM_SCGC6_FTF_SHIFT   (0U)
 
#define SIM_SCGC6_FTF(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
 
#define SIM_SCGC6_DMAMUX_MASK   (0x2U)
 
#define SIM_SCGC6_DMAMUX_SHIFT   (1U)
 
#define SIM_SCGC6_DMAMUX(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
 
#define SIM_SCGC6_FLEXCAN0_MASK   (0x10U)
 
#define SIM_SCGC6_FLEXCAN0_SHIFT   (4U)
 
#define SIM_SCGC6_FLEXCAN0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
 
#define SIM_SCGC6_SPI0_MASK   (0x1000U)
 
#define SIM_SCGC6_SPI0_SHIFT   (12U)
 
#define SIM_SCGC6_SPI0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
 
#define SIM_SCGC6_SPI1_MASK   (0x2000U)
 
#define SIM_SCGC6_SPI1_SHIFT   (13U)
 
#define SIM_SCGC6_SPI1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
 
#define SIM_SCGC6_CRC_MASK   (0x40000U)
 
#define SIM_SCGC6_CRC_SHIFT   (18U)
 
#define SIM_SCGC6_CRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
 
#define SIM_SCGC6_PIT_MASK   (0x800000U)
 
#define SIM_SCGC6_PIT_SHIFT   (23U)
 
#define SIM_SCGC6_PIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
 
#define SIM_SCGC6_FTM0_MASK   (0x1000000U)
 
#define SIM_SCGC6_FTM0_SHIFT   (24U)
 
#define SIM_SCGC6_FTM0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
 
#define SIM_SCGC6_FTM1_MASK   (0x2000000U)
 
#define SIM_SCGC6_FTM1_SHIFT   (25U)
 
#define SIM_SCGC6_FTM1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
 
#define SIM_SCGC6_FTM2_MASK   (0x4000000U)
 
#define SIM_SCGC6_FTM2_SHIFT   (26U)
 
#define SIM_SCGC6_FTM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
 
#define SIM_SCGC6_ADC0_MASK   (0x8000000U)
 
#define SIM_SCGC6_ADC0_SHIFT   (27U)
 
#define SIM_SCGC6_ADC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
 
#define SIM_SCGC6_DAC0_MASK   (0x80000000U)
 
#define SIM_SCGC6_DAC0_SHIFT   (31U)
 
#define SIM_SCGC6_DAC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
 
#define SIM_SCGC6_FTF_MASK   (0x1U)
 
#define SIM_SCGC6_FTF_SHIFT   (0U)
 
#define SIM_SCGC6_FTF(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
 
#define SIM_SCGC6_DMAMUX_MASK   (0x2U)
 
#define SIM_SCGC6_DMAMUX_SHIFT   (1U)
 
#define SIM_SCGC6_DMAMUX(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
 
#define SIM_SCGC6_FLEXCAN0_MASK   (0x10U)
 
#define SIM_SCGC6_FLEXCAN0_SHIFT   (4U)
 
#define SIM_SCGC6_FLEXCAN0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
 
#define SIM_SCGC6_SPI0_MASK   (0x1000U)
 
#define SIM_SCGC6_SPI0_SHIFT   (12U)
 
#define SIM_SCGC6_SPI0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
 
#define SIM_SCGC6_SPI1_MASK   (0x2000U)
 
#define SIM_SCGC6_SPI1_SHIFT   (13U)
 
#define SIM_SCGC6_SPI1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
 
#define SIM_SCGC6_CRC_MASK   (0x40000U)
 
#define SIM_SCGC6_CRC_SHIFT   (18U)
 
#define SIM_SCGC6_CRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
 
#define SIM_SCGC6_PIT_MASK   (0x800000U)
 
#define SIM_SCGC6_PIT_SHIFT   (23U)
 
#define SIM_SCGC6_PIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
 
#define SIM_SCGC6_FTM0_MASK   (0x1000000U)
 
#define SIM_SCGC6_FTM0_SHIFT   (24U)
 
#define SIM_SCGC6_FTM0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
 
#define SIM_SCGC6_FTM1_MASK   (0x2000000U)
 
#define SIM_SCGC6_FTM1_SHIFT   (25U)
 
#define SIM_SCGC6_FTM1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
 
#define SIM_SCGC6_FTM2_MASK   (0x4000000U)
 
#define SIM_SCGC6_FTM2_SHIFT   (26U)
 
#define SIM_SCGC6_FTM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
 
#define SIM_SCGC6_ADC0_MASK   (0x8000000U)
 
#define SIM_SCGC6_ADC0_SHIFT   (27U)
 
#define SIM_SCGC6_ADC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
 
#define SIM_SCGC6_DAC0_MASK   (0x80000000U)
 
#define SIM_SCGC6_DAC0_SHIFT   (31U)
 
#define SIM_SCGC6_DAC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
 
#define SIM_SCGC6_FTF_MASK   (0x1U)
 
#define SIM_SCGC6_FTF_SHIFT   (0U)
 
#define SIM_SCGC6_FTF(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
 
#define SIM_SCGC6_DMAMUX_MASK   (0x2U)
 
#define SIM_SCGC6_DMAMUX_SHIFT   (1U)
 
#define SIM_SCGC6_DMAMUX(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
 
#define SIM_SCGC6_FLEXCAN0_MASK   (0x10U)
 
#define SIM_SCGC6_FLEXCAN0_SHIFT   (4U)
 
#define SIM_SCGC6_FLEXCAN0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
 
#define SIM_SCGC6_FLEXCAN1_MASK   (0x20U)
 
#define SIM_SCGC6_FLEXCAN1_SHIFT   (5U)
 
#define SIM_SCGC6_FLEXCAN1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN1_SHIFT)) & SIM_SCGC6_FLEXCAN1_MASK)
 
#define SIM_SCGC6_FTM3_MASK   (0x40U)
 
#define SIM_SCGC6_FTM3_SHIFT   (6U)
 
#define SIM_SCGC6_FTM3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM3_SHIFT)) & SIM_SCGC6_FTM3_MASK)
 
#define SIM_SCGC6_SPI0_MASK   (0x1000U)
 
#define SIM_SCGC6_SPI0_SHIFT   (12U)
 
#define SIM_SCGC6_SPI0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
 
#define SIM_SCGC6_SPI1_MASK   (0x2000U)
 
#define SIM_SCGC6_SPI1_SHIFT   (13U)
 
#define SIM_SCGC6_SPI1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
 
#define SIM_SCGC6_PDB1_MASK   (0x20000U)
 
#define SIM_SCGC6_PDB1_SHIFT   (17U)
 
#define SIM_SCGC6_PDB1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB1_SHIFT)) & SIM_SCGC6_PDB1_MASK)
 
#define SIM_SCGC6_CRC_MASK   (0x40000U)
 
#define SIM_SCGC6_CRC_SHIFT   (18U)
 
#define SIM_SCGC6_CRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
 
#define SIM_SCGC6_PDB0_MASK   (0x400000U)
 
#define SIM_SCGC6_PDB0_SHIFT   (22U)
 
#define SIM_SCGC6_PDB0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB0_SHIFT)) & SIM_SCGC6_PDB0_MASK)
 
#define SIM_SCGC6_PIT_MASK   (0x800000U)
 
#define SIM_SCGC6_PIT_SHIFT   (23U)
 
#define SIM_SCGC6_PIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
 
#define SIM_SCGC6_FTM0_MASK   (0x1000000U)
 
#define SIM_SCGC6_FTM0_SHIFT   (24U)
 
#define SIM_SCGC6_FTM0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
 
#define SIM_SCGC6_FTM1_MASK   (0x2000000U)
 
#define SIM_SCGC6_FTM1_SHIFT   (25U)
 
#define SIM_SCGC6_FTM1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
 
#define SIM_SCGC6_FTM2_MASK   (0x4000000U)
 
#define SIM_SCGC6_FTM2_SHIFT   (26U)
 
#define SIM_SCGC6_FTM2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
 
#define SIM_SCGC6_ADC0_MASK   (0x8000000U)
 
#define SIM_SCGC6_ADC0_SHIFT   (27U)
 
#define SIM_SCGC6_ADC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
 
#define SIM_SCGC6_DAC0_MASK   (0x80000000U)
 
#define SIM_SCGC6_DAC0_SHIFT   (31U)
 
#define SIM_SCGC6_DAC0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
 

SCGC6 - System Clock Gating Control Register 6

#define SIM_SCGC6_I2S_MASK   (0x8000U)
 
#define SIM_SCGC6_I2S_SHIFT   (15U)
 
#define SIM_SCGC6_I2S(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
 
#define SIM_SCGC6_USBDCD_MASK   (0x200000U)
 
#define SIM_SCGC6_USBDCD_SHIFT   (21U)
 
#define SIM_SCGC6_USBDCD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
 
#define SIM_SCGC6_PDB_MASK   (0x400000U)
 
#define SIM_SCGC6_PDB_SHIFT   (22U)
 
#define SIM_SCGC6_PDB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
 
#define SIM_SCGC6_RTC_MASK   (0x20000000U)
 
#define SIM_SCGC6_RTC_SHIFT   (29U)
 
#define SIM_SCGC6_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
 
#define SIM_SCGC6_I2S_MASK   0x8000u
 
#define SIM_SCGC6_I2S_SHIFT   15
 
#define SIM_SCGC6_USBDCD_MASK   0x200000u
 
#define SIM_SCGC6_USBDCD_SHIFT   21
 
#define SIM_SCGC6_PDB_MASK   0x400000u
 
#define SIM_SCGC6_PDB_SHIFT   22
 
#define SIM_SCGC6_RTC_MASK   0x20000000u
 
#define SIM_SCGC6_RTC_SHIFT   29
 
#define SIM_SCGC6_RNGA_MASK   (0x200U)
 
#define SIM_SCGC6_RNGA_SHIFT   (9U)
 
#define SIM_SCGC6_RNGA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
 
#define SIM_SCGC6_I2S_MASK   (0x8000U)
 
#define SIM_SCGC6_I2S_SHIFT   (15U)
 
#define SIM_SCGC6_I2S(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
 
#define SIM_SCGC6_USBDCD_MASK   (0x200000U)
 
#define SIM_SCGC6_USBDCD_SHIFT   (21U)
 
#define SIM_SCGC6_USBDCD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
 
#define SIM_SCGC6_PDB_MASK   (0x400000U)
 
#define SIM_SCGC6_PDB_SHIFT   (22U)
 
#define SIM_SCGC6_PDB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
 
#define SIM_SCGC6_RTC_MASK   (0x20000000U)
 
#define SIM_SCGC6_RTC_SHIFT   (29U)
 
#define SIM_SCGC6_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
 
#define SIM_SCGC6_RNGA_MASK   (0x200U)
 
#define SIM_SCGC6_RNGA_SHIFT   (9U)
 
#define SIM_SCGC6_RNGA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
 
#define SIM_SCGC6_I2S_MASK   (0x8000U)
 
#define SIM_SCGC6_I2S_SHIFT   (15U)
 
#define SIM_SCGC6_I2S(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
 
#define SIM_SCGC6_USBDCD_MASK   (0x200000U)
 
#define SIM_SCGC6_USBDCD_SHIFT   (21U)
 
#define SIM_SCGC6_USBDCD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
 
#define SIM_SCGC6_PDB_MASK   (0x400000U)
 
#define SIM_SCGC6_PDB_SHIFT   (22U)
 
#define SIM_SCGC6_PDB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
 
#define SIM_SCGC6_RTC_MASK   (0x20000000U)
 
#define SIM_SCGC6_RTC_SHIFT   (29U)
 
#define SIM_SCGC6_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
 
#define SIM_SCGC6_RNGA_MASK   (0x200U)
 
#define SIM_SCGC6_RNGA_SHIFT   (9U)
 
#define SIM_SCGC6_RNGA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
 
#define SIM_SCGC6_I2S_MASK   (0x8000U)
 
#define SIM_SCGC6_I2S_SHIFT   (15U)
 
#define SIM_SCGC6_I2S(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
 
#define SIM_SCGC6_USBDCD_MASK   (0x200000U)
 
#define SIM_SCGC6_USBDCD_SHIFT   (21U)
 
#define SIM_SCGC6_USBDCD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
 
#define SIM_SCGC6_PDB_MASK   (0x400000U)
 
#define SIM_SCGC6_PDB_SHIFT   (22U)
 
#define SIM_SCGC6_PDB(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
 
#define SIM_SCGC6_RTC_MASK   (0x20000000U)
 
#define SIM_SCGC6_RTC_SHIFT   (29U)
 
#define SIM_SCGC6_RTC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
 

SCGC7 - System Clock Gating Control Register 7

#define SIM_SCGC7_FLEXBUS_MASK   (0x1U)
 
#define SIM_SCGC7_FLEXBUS_SHIFT   (0U)
 
#define SIM_SCGC7_FLEXBUS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
 
#define SIM_SCGC7_DMA_MASK   (0x2U)
 
#define SIM_SCGC7_DMA_SHIFT   (1U)
 
#define SIM_SCGC7_DMA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
 
#define SIM_SCGC7_FLEXBUS_MASK   0x1u
 
#define SIM_SCGC7_FLEXBUS_SHIFT   0
 
#define SIM_SCGC7_DMA_MASK   0x2u
 
#define SIM_SCGC7_DMA_SHIFT   1
 
#define SIM_SCGC7_FLEXBUS_MASK   (0x1U)
 
#define SIM_SCGC7_FLEXBUS_SHIFT   (0U)
 
#define SIM_SCGC7_FLEXBUS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
 
#define SIM_SCGC7_DMA_MASK   (0x2U)
 
#define SIM_SCGC7_DMA_SHIFT   (1U)
 
#define SIM_SCGC7_DMA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
 
#define SIM_SCGC7_FLEXBUS_MASK   (0x1U)
 
#define SIM_SCGC7_FLEXBUS_SHIFT   (0U)
 
#define SIM_SCGC7_FLEXBUS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
 
#define SIM_SCGC7_DMA_MASK   (0x2U)
 
#define SIM_SCGC7_DMA_SHIFT   (1U)
 
#define SIM_SCGC7_DMA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
 
#define SIM_SCGC7_FLEXBUS_MASK   (0x1U)
 
#define SIM_SCGC7_FLEXBUS_SHIFT   (0U)
 
#define SIM_SCGC7_FLEXBUS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
 
#define SIM_SCGC7_DMA_MASK   (0x2U)
 
#define SIM_SCGC7_DMA_SHIFT   (1U)
 
#define SIM_SCGC7_DMA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
 
#define SIM_SCGC7_FLEXBUS_MASK   (0x1U)
 
#define SIM_SCGC7_FLEXBUS_SHIFT   (0U)
 
#define SIM_SCGC7_FLEXBUS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
 
#define SIM_SCGC7_SMPU_MASK   (0x4U)
 
#define SIM_SCGC7_SMPU_SHIFT   (2U)
 
#define SIM_SCGC7_SMPU(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SMPU_SHIFT)) & SIM_SCGC7_SMPU_MASK)
 
#define SIM_SCGC7_DMA_MASK   (0x100U)
 
#define SIM_SCGC7_DMA_SHIFT   (8U)
 
#define SIM_SCGC7_DMA(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
 

SCGC7 - System Clock Gating Control Register 7

#define SIM_SCGC7_MPU_MASK   (0x4U)
 
#define SIM_SCGC7_MPU_SHIFT   (2U)
 
#define SIM_SCGC7_MPU(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
 
#define SIM_SCGC7_MPU_MASK   0x4u
 
#define SIM_SCGC7_MPU_SHIFT   2
 
#define SIM_SCGC7_MPU_MASK   (0x4U)
 
#define SIM_SCGC7_MPU_SHIFT   (2U)
 
#define SIM_SCGC7_MPU(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
 
#define SIM_SCGC7_MPU_MASK   (0x4U)
 
#define SIM_SCGC7_MPU_SHIFT   (2U)
 
#define SIM_SCGC7_MPU(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
 
#define SIM_SCGC7_SDRAMC_MASK   (0x8U)
 
#define SIM_SCGC7_SDRAMC_SHIFT   (3U)
 
#define SIM_SCGC7_SDRAMC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
 
#define SIM_SCGC7_MPU_MASK   (0x4U)
 
#define SIM_SCGC7_MPU_SHIFT   (2U)
 
#define SIM_SCGC7_MPU(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
 
#define SIM_SCGC7_SDRAMC_MASK   (0x8U)
 
#define SIM_SCGC7_SDRAMC_SHIFT   (3U)
 
#define SIM_SCGC7_SDRAMC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
 

CLKDIV1 - System Clock Divider Register 1

#define SIM_CLKDIV1_OUTDIV4_MASK   (0xF0000U)
 
#define SIM_CLKDIV1_OUTDIV4_SHIFT   (16U)
 
#define SIM_CLKDIV1_OUTDIV4(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
 
#define SIM_CLKDIV1_OUTDIV3_MASK   (0xF00000U)
 
#define SIM_CLKDIV1_OUTDIV3_SHIFT   (20U)
 
#define SIM_CLKDIV1_OUTDIV3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
 
#define SIM_CLKDIV1_OUTDIV2_MASK   (0xF000000U)
 
#define SIM_CLKDIV1_OUTDIV2_SHIFT   (24U)
 
#define SIM_CLKDIV1_OUTDIV2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
 
#define SIM_CLKDIV1_OUTDIV1_MASK   (0xF0000000U)
 
#define SIM_CLKDIV1_OUTDIV1_SHIFT   (28U)
 
#define SIM_CLKDIV1_OUTDIV1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
 
#define SIM_CLKDIV1_OUTDIV4_MASK   0xF0000u
 
#define SIM_CLKDIV1_OUTDIV4_SHIFT   16
 
#define SIM_CLKDIV1_OUTDIV4(x)   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
 
#define SIM_CLKDIV1_OUTDIV3_MASK   0xF00000u
 
#define SIM_CLKDIV1_OUTDIV3_SHIFT   20
 
#define SIM_CLKDIV1_OUTDIV3(x)   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
 
#define SIM_CLKDIV1_OUTDIV2_MASK   0xF000000u
 
#define SIM_CLKDIV1_OUTDIV2_SHIFT   24
 
#define SIM_CLKDIV1_OUTDIV2(x)   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
 
#define SIM_CLKDIV1_OUTDIV1_MASK   0xF0000000u
 
#define SIM_CLKDIV1_OUTDIV1_SHIFT   28
 
#define SIM_CLKDIV1_OUTDIV1(x)   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
 
#define SIM_CLKDIV1_OUTDIV4_MASK   (0xF0000U)
 
#define SIM_CLKDIV1_OUTDIV4_SHIFT   (16U)
 
#define SIM_CLKDIV1_OUTDIV4(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
 
#define SIM_CLKDIV1_OUTDIV3_MASK   (0xF00000U)
 
#define SIM_CLKDIV1_OUTDIV3_SHIFT   (20U)
 
#define SIM_CLKDIV1_OUTDIV3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
 
#define SIM_CLKDIV1_OUTDIV2_MASK   (0xF000000U)
 
#define SIM_CLKDIV1_OUTDIV2_SHIFT   (24U)
 
#define SIM_CLKDIV1_OUTDIV2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
 
#define SIM_CLKDIV1_OUTDIV1_MASK   (0xF0000000U)
 
#define SIM_CLKDIV1_OUTDIV1_SHIFT   (28U)
 
#define SIM_CLKDIV1_OUTDIV1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
 
#define SIM_CLKDIV1_OUTDIV4_MASK   (0xF0000U)
 
#define SIM_CLKDIV1_OUTDIV4_SHIFT   (16U)
 
#define SIM_CLKDIV1_OUTDIV4(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
 
#define SIM_CLKDIV1_OUTDIV3_MASK   (0xF00000U)
 
#define SIM_CLKDIV1_OUTDIV3_SHIFT   (20U)
 
#define SIM_CLKDIV1_OUTDIV3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
 
#define SIM_CLKDIV1_OUTDIV2_MASK   (0xF000000U)
 
#define SIM_CLKDIV1_OUTDIV2_SHIFT   (24U)
 
#define SIM_CLKDIV1_OUTDIV2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
 
#define SIM_CLKDIV1_OUTDIV1_MASK   (0xF0000000U)
 
#define SIM_CLKDIV1_OUTDIV1_SHIFT   (28U)
 
#define SIM_CLKDIV1_OUTDIV1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
 
#define SIM_CLKDIV1_OUTDIV4_MASK   (0xF0000U)
 
#define SIM_CLKDIV1_OUTDIV4_SHIFT   (16U)
 
#define SIM_CLKDIV1_OUTDIV4(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
 
#define SIM_CLKDIV1_OUTDIV3_MASK   (0xF00000U)
 
#define SIM_CLKDIV1_OUTDIV3_SHIFT   (20U)
 
#define SIM_CLKDIV1_OUTDIV3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
 
#define SIM_CLKDIV1_OUTDIV2_MASK   (0xF000000U)
 
#define SIM_CLKDIV1_OUTDIV2_SHIFT   (24U)
 
#define SIM_CLKDIV1_OUTDIV2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
 
#define SIM_CLKDIV1_OUTDIV1_MASK   (0xF0000000U)
 
#define SIM_CLKDIV1_OUTDIV1_SHIFT   (28U)
 
#define SIM_CLKDIV1_OUTDIV1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
 
#define SIM_CLKDIV1_OUTDIV4_MASK   (0xF0000U)
 
#define SIM_CLKDIV1_OUTDIV4_SHIFT   (16U)
 
#define SIM_CLKDIV1_OUTDIV4(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
 
#define SIM_CLKDIV1_OUTDIV3_MASK   (0xF00000U)
 
#define SIM_CLKDIV1_OUTDIV3_SHIFT   (20U)
 
#define SIM_CLKDIV1_OUTDIV3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
 
#define SIM_CLKDIV1_OUTDIV2_MASK   (0xF000000U)
 
#define SIM_CLKDIV1_OUTDIV2_SHIFT   (24U)
 
#define SIM_CLKDIV1_OUTDIV2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
 
#define SIM_CLKDIV1_OUTDIV1_MASK   (0xF0000000U)
 
#define SIM_CLKDIV1_OUTDIV1_SHIFT   (28U)
 
#define SIM_CLKDIV1_OUTDIV1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
 

CLKDIV2 - System Clock Divider Register 2

#define SIM_CLKDIV2_USBFRAC_MASK   (0x1U)
 
#define SIM_CLKDIV2_USBFRAC_SHIFT   (0U)
 
#define SIM_CLKDIV2_USBFRAC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
 
#define SIM_CLKDIV2_USBDIV_MASK   (0xEU)
 
#define SIM_CLKDIV2_USBDIV_SHIFT   (1U)
 
#define SIM_CLKDIV2_USBDIV(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
 
#define SIM_CLKDIV2_USBFRAC_MASK   0x1u
 
#define SIM_CLKDIV2_USBFRAC_SHIFT   0
 
#define SIM_CLKDIV2_USBDIV_MASK   0xEu
 
#define SIM_CLKDIV2_USBDIV_SHIFT   1
 
#define SIM_CLKDIV2_USBDIV(x)   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
 
#define SIM_CLKDIV2_USBFRAC_MASK   (0x1U)
 
#define SIM_CLKDIV2_USBFRAC_SHIFT   (0U)
 
#define SIM_CLKDIV2_USBFRAC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
 
#define SIM_CLKDIV2_USBDIV_MASK   (0xEU)
 
#define SIM_CLKDIV2_USBDIV_SHIFT   (1U)
 
#define SIM_CLKDIV2_USBDIV(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
 
#define SIM_CLKDIV2_USBFRAC_MASK   (0x1U)
 
#define SIM_CLKDIV2_USBFRAC_SHIFT   (0U)
 
#define SIM_CLKDIV2_USBFRAC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
 
#define SIM_CLKDIV2_USBDIV_MASK   (0xEU)
 
#define SIM_CLKDIV2_USBDIV_SHIFT   (1U)
 
#define SIM_CLKDIV2_USBDIV(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
 
#define SIM_CLKDIV2_USBFRAC_MASK   (0x1U)
 
#define SIM_CLKDIV2_USBFRAC_SHIFT   (0U)
 
#define SIM_CLKDIV2_USBFRAC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
 
#define SIM_CLKDIV2_USBDIV_MASK   (0xEU)
 
#define SIM_CLKDIV2_USBDIV_SHIFT   (1U)
 
#define SIM_CLKDIV2_USBDIV(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
 

FCFG1 - Flash Configuration Register 1

#define SIM_FCFG1_FLASHDIS_MASK   (0x1U)
 
#define SIM_FCFG1_FLASHDIS_SHIFT   (0U)
 
#define SIM_FCFG1_FLASHDIS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
 
#define SIM_FCFG1_FLASHDOZE_MASK   (0x2U)
 
#define SIM_FCFG1_FLASHDOZE_SHIFT   (1U)
 
#define SIM_FCFG1_FLASHDOZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
 
#define SIM_FCFG1_PFSIZE_MASK   (0xF000000U)
 
#define SIM_FCFG1_PFSIZE_SHIFT   (24U)
 
#define SIM_FCFG1_PFSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
 
#define SIM_FCFG1_FLASHDIS_MASK   (0x1U)
 
#define SIM_FCFG1_FLASHDIS_SHIFT   (0U)
 
#define SIM_FCFG1_FLASHDIS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
 
#define SIM_FCFG1_FLASHDOZE_MASK   (0x2U)
 
#define SIM_FCFG1_FLASHDOZE_SHIFT   (1U)
 
#define SIM_FCFG1_FLASHDOZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
 
#define SIM_FCFG1_PFSIZE_MASK   (0xF000000U)
 
#define SIM_FCFG1_PFSIZE_SHIFT   (24U)
 
#define SIM_FCFG1_PFSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
 
#define SIM_FCFG1_FLASHDIS_MASK   (0x1U)
 
#define SIM_FCFG1_FLASHDIS_SHIFT   (0U)
 
#define SIM_FCFG1_FLASHDIS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
 
#define SIM_FCFG1_FLASHDOZE_MASK   (0x2U)
 
#define SIM_FCFG1_FLASHDOZE_SHIFT   (1U)
 
#define SIM_FCFG1_FLASHDOZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
 
#define SIM_FCFG1_PFSIZE_MASK   (0xF000000U)
 
#define SIM_FCFG1_PFSIZE_SHIFT   (24U)
 
#define SIM_FCFG1_PFSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
 
#define SIM_FCFG1_FLASHDIS_MASK   (0x1U)
 
#define SIM_FCFG1_FLASHDIS_SHIFT   (0U)
 
#define SIM_FCFG1_FLASHDIS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
 
#define SIM_FCFG1_FLASHDOZE_MASK   (0x2U)
 
#define SIM_FCFG1_FLASHDOZE_SHIFT   (1U)
 
#define SIM_FCFG1_FLASHDOZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
 
#define SIM_FCFG1_PFSIZE_MASK   (0xF000000U)
 
#define SIM_FCFG1_PFSIZE_SHIFT   (24U)
 
#define SIM_FCFG1_PFSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
 
#define SIM_FCFG1_FLASHDIS_MASK   (0x1U)
 
#define SIM_FCFG1_FLASHDIS_SHIFT   (0U)
 
#define SIM_FCFG1_FLASHDIS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
 
#define SIM_FCFG1_FLASHDOZE_MASK   (0x2U)
 
#define SIM_FCFG1_FLASHDOZE_SHIFT   (1U)
 
#define SIM_FCFG1_FLASHDOZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
 
#define SIM_FCFG1_PFSIZE_MASK   (0xF000000U)
 
#define SIM_FCFG1_PFSIZE_SHIFT   (24U)
 
#define SIM_FCFG1_PFSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
 

FCFG1 - Flash Configuration Register 1

#define SIM_FCFG1_DEPART_MASK   (0xF00U)
 
#define SIM_FCFG1_DEPART_SHIFT   (8U)
 
#define SIM_FCFG1_DEPART(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
 
#define SIM_FCFG1_EESIZE_MASK   (0xF0000U)
 
#define SIM_FCFG1_EESIZE_SHIFT   (16U)
 
#define SIM_FCFG1_EESIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
 
#define SIM_FCFG1_NVMSIZE_MASK   (0xF0000000U)
 
#define SIM_FCFG1_NVMSIZE_SHIFT   (28U)
 
#define SIM_FCFG1_NVMSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
 
#define SIM_FCFG1_DEPART_MASK   0xF00u
 
#define SIM_FCFG1_DEPART_SHIFT   8
 
#define SIM_FCFG1_DEPART(x)   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
 
#define SIM_FCFG1_EESIZE_MASK   0xF0000u
 
#define SIM_FCFG1_EESIZE_SHIFT   16
 
#define SIM_FCFG1_EESIZE(x)   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
 
#define SIM_FCFG1_DEPART_MASK   (0xF00U)
 
#define SIM_FCFG1_DEPART_SHIFT   (8U)
 
#define SIM_FCFG1_DEPART(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
 
#define SIM_FCFG1_EESIZE_MASK   (0xF0000U)
 
#define SIM_FCFG1_EESIZE_SHIFT   (16U)
 
#define SIM_FCFG1_EESIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
 
#define SIM_FCFG1_NVMSIZE_MASK   (0xF0000000U)
 
#define SIM_FCFG1_NVMSIZE_SHIFT   (28U)
 
#define SIM_FCFG1_NVMSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
 
#define SIM_FCFG1_DEPART_MASK   (0xF00U)
 
#define SIM_FCFG1_DEPART_SHIFT   (8U)
 
#define SIM_FCFG1_DEPART(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
 
#define SIM_FCFG1_EESIZE_MASK   (0xF0000U)
 
#define SIM_FCFG1_EESIZE_SHIFT   (16U)
 
#define SIM_FCFG1_EESIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
 
#define SIM_FCFG1_NVMSIZE_MASK   (0xF0000000U)
 
#define SIM_FCFG1_NVMSIZE_SHIFT   (28U)
 
#define SIM_FCFG1_NVMSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
 
#define SIM_FCFG1_DEPART_MASK   (0xF00U)
 
#define SIM_FCFG1_DEPART_SHIFT   (8U)
 
#define SIM_FCFG1_DEPART(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
 
#define SIM_FCFG1_EESIZE_MASK   (0xF0000U)
 
#define SIM_FCFG1_EESIZE_SHIFT   (16U)
 
#define SIM_FCFG1_EESIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
 
#define SIM_FCFG1_NVMSIZE_MASK   (0xF0000000U)
 
#define SIM_FCFG1_NVMSIZE_SHIFT   (28U)
 
#define SIM_FCFG1_NVMSIZE(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
 

FCFG2 - Flash Configuration Register 2

#define SIM_FCFG2_MAXADDR1_MASK   (0x7F0000U)
 
#define SIM_FCFG2_MAXADDR1_SHIFT   (16U)
 
#define SIM_FCFG2_MAXADDR1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
 
#define SIM_FCFG2_PFLSH_MASK   (0x800000U)
 
#define SIM_FCFG2_PFLSH_SHIFT   (23U)
 
#define SIM_FCFG2_PFLSH(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
 
#define SIM_FCFG2_SWAPPFLSH_MASK   (0x80000000U)
 
#define SIM_FCFG2_SWAPPFLSH_SHIFT   (31U)
 
#define SIM_FCFG2_SWAPPFLSH(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
 
#define SIM_FCFG2_MAXADDR1_MASK   0x3F0000u
 
#define SIM_FCFG2_MAXADDR1_SHIFT   16
 
#define SIM_FCFG2_MAXADDR1(x)   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
 
#define SIM_FCFG2_PFLSH_MASK   0x800000u
 
#define SIM_FCFG2_PFLSH_SHIFT   23
 
#define SIM_FCFG2_SWAPPFLSH_MASK   0x80000000u
 
#define SIM_FCFG2_SWAPPFLSH_SHIFT   31
 
#define SIM_FCFG2_MAXADDR1_MASK   (0x7F0000U)
 
#define SIM_FCFG2_MAXADDR1_SHIFT   (16U)
 
#define SIM_FCFG2_MAXADDR1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
 
#define SIM_FCFG2_PFLSH_MASK   (0x800000U)
 
#define SIM_FCFG2_PFLSH_SHIFT   (23U)
 
#define SIM_FCFG2_PFLSH(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
 
#define SIM_FCFG2_MAXADDR1_MASK   (0x7F0000U)
 
#define SIM_FCFG2_MAXADDR1_SHIFT   (16U)
 
#define SIM_FCFG2_MAXADDR1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
 
#define SIM_FCFG2_PFLSH_MASK   (0x800000U)
 
#define SIM_FCFG2_PFLSH_SHIFT   (23U)
 
#define SIM_FCFG2_PFLSH(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
 
#define SIM_FCFG2_SWAPPFLSH_MASK   (0x80000000U)
 
#define SIM_FCFG2_SWAPPFLSH_SHIFT   (31U)
 
#define SIM_FCFG2_SWAPPFLSH(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
 
#define SIM_FCFG2_MAXADDR1_MASK   (0x7F0000U)
 
#define SIM_FCFG2_MAXADDR1_SHIFT   (16U)
 
#define SIM_FCFG2_MAXADDR1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
 
#define SIM_FCFG2_PFLSH_MASK   (0x800000U)
 
#define SIM_FCFG2_PFLSH_SHIFT   (23U)
 
#define SIM_FCFG2_PFLSH(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
 
#define SIM_FCFG2_SWAPPFLSH_MASK   (0x80000000U)
 
#define SIM_FCFG2_SWAPPFLSH_SHIFT   (31U)
 
#define SIM_FCFG2_SWAPPFLSH(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
 

FCFG2 - Flash Configuration Register 2

#define SIM_FCFG2_MAXADDR0_MASK   (0x7F000000U)
 
#define SIM_FCFG2_MAXADDR0_SHIFT   (24U)
 
#define SIM_FCFG2_MAXADDR0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
 
#define SIM_FCFG2_MAXADDR0_MASK   0x3F000000u
 
#define SIM_FCFG2_MAXADDR0_SHIFT   24
 
#define SIM_FCFG2_MAXADDR0(x)   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
 
#define SIM_FCFG2_MAXADDR0_MASK   (0x7F000000U)
 
#define SIM_FCFG2_MAXADDR0_SHIFT   (24U)
 
#define SIM_FCFG2_MAXADDR0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
 
#define SIM_FCFG2_MAXADDR0_MASK   (0x7F000000U)
 
#define SIM_FCFG2_MAXADDR0_SHIFT   (24U)
 
#define SIM_FCFG2_MAXADDR0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
 
#define SIM_FCFG2_MAXADDR0_MASK   (0x7F000000U)
 
#define SIM_FCFG2_MAXADDR0_SHIFT   (24U)
 
#define SIM_FCFG2_MAXADDR0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
 
#define SIM_FCFG2_MAXADDR0_MASK   (0x7F000000U)
 
#define SIM_FCFG2_MAXADDR0_SHIFT   (24U)
 
#define SIM_FCFG2_MAXADDR0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
 

UIDH - Unique Identification Register High

#define SIM_UIDH_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDH_UID_SHIFT   (0U)
 
#define SIM_UIDH_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
 
#define SIM_UIDH_UID_MASK   0xFFFFFFFFu
 
#define SIM_UIDH_UID_SHIFT   0
 
#define SIM_UIDH_UID(x)   (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
 
#define SIM_UIDH_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDH_UID_SHIFT   (0U)
 
#define SIM_UIDH_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
 
#define SIM_UIDH_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDH_UID_SHIFT   (0U)
 
#define SIM_UIDH_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
 
#define SIM_UIDH_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDH_UID_SHIFT   (0U)
 
#define SIM_UIDH_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
 
#define SIM_UIDH_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDH_UID_SHIFT   (0U)
 
#define SIM_UIDH_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
 

UIDMH - Unique Identification Register Mid-High

#define SIM_UIDMH_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDMH_UID_SHIFT   (0U)
 
#define SIM_UIDMH_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
 
#define SIM_UIDMH_UID_MASK   0xFFFFFFFFu
 
#define SIM_UIDMH_UID_SHIFT   0
 
#define SIM_UIDMH_UID(x)   (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
 
#define SIM_UIDMH_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDMH_UID_SHIFT   (0U)
 
#define SIM_UIDMH_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
 
#define SIM_UIDMH_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDMH_UID_SHIFT   (0U)
 
#define SIM_UIDMH_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
 
#define SIM_UIDMH_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDMH_UID_SHIFT   (0U)
 
#define SIM_UIDMH_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
 
#define SIM_UIDMH_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDMH_UID_SHIFT   (0U)
 
#define SIM_UIDMH_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
 

UIDML - Unique Identification Register Mid Low

#define SIM_UIDML_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDML_UID_SHIFT   (0U)
 
#define SIM_UIDML_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
 
#define SIM_UIDML_UID_MASK   0xFFFFFFFFu
 
#define SIM_UIDML_UID_SHIFT   0
 
#define SIM_UIDML_UID(x)   (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
 
#define SIM_UIDML_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDML_UID_SHIFT   (0U)
 
#define SIM_UIDML_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
 
#define SIM_UIDML_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDML_UID_SHIFT   (0U)
 
#define SIM_UIDML_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
 
#define SIM_UIDML_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDML_UID_SHIFT   (0U)
 
#define SIM_UIDML_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
 
#define SIM_UIDML_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDML_UID_SHIFT   (0U)
 
#define SIM_UIDML_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
 

UIDL - Unique Identification Register Low

#define SIM_UIDL_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDL_UID_SHIFT   (0U)
 
#define SIM_UIDL_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
 
#define SIM_UIDL_UID_MASK   0xFFFFFFFFu
 
#define SIM_UIDL_UID_SHIFT   0
 
#define SIM_UIDL_UID(x)   (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
 
#define SIM_UIDL_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDL_UID_SHIFT   (0U)
 
#define SIM_UIDL_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
 
#define SIM_UIDL_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDL_UID_SHIFT   (0U)
 
#define SIM_UIDL_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
 
#define SIM_UIDL_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDL_UID_SHIFT   (0U)
 
#define SIM_UIDL_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
 
#define SIM_UIDL_UID_MASK   (0xFFFFFFFFU)
 
#define SIM_UIDL_UID_SHIFT   (0U)
 
#define SIM_UIDL_UID(x)   (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
 

SCGC1 - System Clock Gating Control Register 1

#define SIM_SCGC1_I2C2_MASK   (0x40U)
 
#define SIM_SCGC1_I2C2_SHIFT   (6U)
 
#define SIM_SCGC1_I2C2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
 
#define SIM_SCGC1_I2C2_MASK   (0x40U)
 
#define SIM_SCGC1_I2C2_SHIFT   (6U)
 
#define SIM_SCGC1_I2C2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
 
#define SIM_SCGC1_I2C3_MASK   (0x80U)
 
#define SIM_SCGC1_I2C3_SHIFT   (7U)
 
#define SIM_SCGC1_I2C3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
 
#define SIM_SCGC1_I2C2_MASK   (0x40U)
 
#define SIM_SCGC1_I2C2_SHIFT   (6U)
 
#define SIM_SCGC1_I2C2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
 
#define SIM_SCGC1_I2C3_MASK   (0x80U)
 
#define SIM_SCGC1_I2C3_SHIFT   (7U)
 
#define SIM_SCGC1_I2C3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
 

USBPHYCTL - USB PHY Control Register

#define SIM_USBPHYCTL_USBVREGSEL_MASK   (0x100U)
 
#define SIM_USBPHYCTL_USBVREGSEL_SHIFT   (8U)
 
#define SIM_USBPHYCTL_USBVREGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)
 
#define SIM_USBPHYCTL_USBVREGPD_MASK   (0x200U)
 
#define SIM_USBPHYCTL_USBVREGPD_SHIFT   (9U)
 
#define SIM_USBPHYCTL_USBVREGPD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)
 
#define SIM_USBPHYCTL_USB3VOUTTRG_MASK   (0x700000U)
 
#define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT   (20U)
 
#define SIM_USBPHYCTL_USB3VOUTTRG(x)   (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
 
#define SIM_USBPHYCTL_USBDISILIM_MASK   (0x800000U)
 
#define SIM_USBPHYCTL_USBDISILIM_SHIFT   (23U)
 
#define SIM_USBPHYCTL_USBDISILIM(x)   (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
 
#define SIM_USBPHYCTL_USBVREGSEL_MASK   (0x100U)
 
#define SIM_USBPHYCTL_USBVREGSEL_SHIFT   (8U)
 
#define SIM_USBPHYCTL_USBVREGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)
 
#define SIM_USBPHYCTL_USBVREGPD_MASK   (0x200U)
 
#define SIM_USBPHYCTL_USBVREGPD_SHIFT   (9U)
 
#define SIM_USBPHYCTL_USBVREGPD(x)   (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)
 
#define SIM_USBPHYCTL_USB3VOUTTRG_MASK   (0x700000U)
 
#define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT   (20U)
 
#define SIM_USBPHYCTL_USB3VOUTTRG(x)   (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
 
#define SIM_USBPHYCTL_USBDISILIM_MASK   (0x800000U)
 
#define SIM_USBPHYCTL_USBDISILIM_SHIFT   (23U)
 
#define SIM_USBPHYCTL_USBDISILIM(x)   (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
 

SOPT5 - System Options Register 5

#define SIM_SOPT5_LPUART0TXSRC_MASK   (0x30000U)
 
#define SIM_SOPT5_LPUART0TXSRC_SHIFT   (16U)
 
#define SIM_SOPT5_LPUART0TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
 
#define SIM_SOPT5_LPUART0RXSRC_MASK   (0xC0000U)
 
#define SIM_SOPT5_LPUART0RXSRC_SHIFT   (18U)
 
#define SIM_SOPT5_LPUART0RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
 
#define SIM_SOPT5_LPUART0TXSRC_MASK   (0x30000U)
 
#define SIM_SOPT5_LPUART0TXSRC_SHIFT   (16U)
 
#define SIM_SOPT5_LPUART0TXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
 
#define SIM_SOPT5_LPUART0RXSRC_MASK   (0xC0000U)
 
#define SIM_SOPT5_LPUART0RXSRC_SHIFT   (18U)
 
#define SIM_SOPT5_LPUART0RXSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
 

SOPT8 - System Options Register 8

#define SIM_SOPT8_FTM0SYNCBIT_MASK   (0x1U)
 
#define SIM_SOPT8_FTM0SYNCBIT_SHIFT   (0U)
 
#define SIM_SOPT8_FTM0SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM1SYNCBIT_MASK   (0x2U)
 
#define SIM_SOPT8_FTM1SYNCBIT_SHIFT   (1U)
 
#define SIM_SOPT8_FTM1SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM2SYNCBIT_MASK   (0x4U)
 
#define SIM_SOPT8_FTM2SYNCBIT_SHIFT   (2U)
 
#define SIM_SOPT8_FTM2SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM3SYNCBIT_MASK   (0x8U)
 
#define SIM_SOPT8_FTM3SYNCBIT_SHIFT   (3U)
 
#define SIM_SOPT8_FTM3SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM0OCH0SRC_MASK   (0x10000U)
 
#define SIM_SOPT8_FTM0OCH0SRC_SHIFT   (16U)
 
#define SIM_SOPT8_FTM0OCH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH1SRC_MASK   (0x20000U)
 
#define SIM_SOPT8_FTM0OCH1SRC_SHIFT   (17U)
 
#define SIM_SOPT8_FTM0OCH1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH2SRC_MASK   (0x40000U)
 
#define SIM_SOPT8_FTM0OCH2SRC_SHIFT   (18U)
 
#define SIM_SOPT8_FTM0OCH2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH3SRC_MASK   (0x80000U)
 
#define SIM_SOPT8_FTM0OCH3SRC_SHIFT   (19U)
 
#define SIM_SOPT8_FTM0OCH3SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH4SRC_MASK   (0x100000U)
 
#define SIM_SOPT8_FTM0OCH4SRC_SHIFT   (20U)
 
#define SIM_SOPT8_FTM0OCH4SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH5SRC_MASK   (0x200000U)
 
#define SIM_SOPT8_FTM0OCH5SRC_SHIFT   (21U)
 
#define SIM_SOPT8_FTM0OCH5SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH6SRC_MASK   (0x400000U)
 
#define SIM_SOPT8_FTM0OCH6SRC_SHIFT   (22U)
 
#define SIM_SOPT8_FTM0OCH6SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH7SRC_MASK   (0x800000U)
 
#define SIM_SOPT8_FTM0OCH7SRC_SHIFT   (23U)
 
#define SIM_SOPT8_FTM0OCH7SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH0SRC_MASK   (0x1000000U)
 
#define SIM_SOPT8_FTM3OCH0SRC_SHIFT   (24U)
 
#define SIM_SOPT8_FTM3OCH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH1SRC_MASK   (0x2000000U)
 
#define SIM_SOPT8_FTM3OCH1SRC_SHIFT   (25U)
 
#define SIM_SOPT8_FTM3OCH1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH2SRC_MASK   (0x4000000U)
 
#define SIM_SOPT8_FTM3OCH2SRC_SHIFT   (26U)
 
#define SIM_SOPT8_FTM3OCH2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH3SRC_MASK   (0x8000000U)
 
#define SIM_SOPT8_FTM3OCH3SRC_SHIFT   (27U)
 
#define SIM_SOPT8_FTM3OCH3SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH4SRC_MASK   (0x10000000U)
 
#define SIM_SOPT8_FTM3OCH4SRC_SHIFT   (28U)
 
#define SIM_SOPT8_FTM3OCH4SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH5SRC_MASK   (0x20000000U)
 
#define SIM_SOPT8_FTM3OCH5SRC_SHIFT   (29U)
 
#define SIM_SOPT8_FTM3OCH5SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH6SRC_MASK   (0x40000000U)
 
#define SIM_SOPT8_FTM3OCH6SRC_SHIFT   (30U)
 
#define SIM_SOPT8_FTM3OCH6SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH7SRC_MASK   (0x80000000U)
 
#define SIM_SOPT8_FTM3OCH7SRC_SHIFT   (31U)
 
#define SIM_SOPT8_FTM3OCH7SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
 
#define SIM_SOPT8_FTM0SYNCBIT_MASK   (0x1U)
 
#define SIM_SOPT8_FTM0SYNCBIT_SHIFT   (0U)
 
#define SIM_SOPT8_FTM0SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM1SYNCBIT_MASK   (0x2U)
 
#define SIM_SOPT8_FTM1SYNCBIT_SHIFT   (1U)
 
#define SIM_SOPT8_FTM1SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM2SYNCBIT_MASK   (0x4U)
 
#define SIM_SOPT8_FTM2SYNCBIT_SHIFT   (2U)
 
#define SIM_SOPT8_FTM2SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM3SYNCBIT_MASK   (0x8U)
 
#define SIM_SOPT8_FTM3SYNCBIT_SHIFT   (3U)
 
#define SIM_SOPT8_FTM3SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM0OCH0SRC_MASK   (0x10000U)
 
#define SIM_SOPT8_FTM0OCH0SRC_SHIFT   (16U)
 
#define SIM_SOPT8_FTM0OCH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH1SRC_MASK   (0x20000U)
 
#define SIM_SOPT8_FTM0OCH1SRC_SHIFT   (17U)
 
#define SIM_SOPT8_FTM0OCH1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH2SRC_MASK   (0x40000U)
 
#define SIM_SOPT8_FTM0OCH2SRC_SHIFT   (18U)
 
#define SIM_SOPT8_FTM0OCH2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH3SRC_MASK   (0x80000U)
 
#define SIM_SOPT8_FTM0OCH3SRC_SHIFT   (19U)
 
#define SIM_SOPT8_FTM0OCH3SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH4SRC_MASK   (0x100000U)
 
#define SIM_SOPT8_FTM0OCH4SRC_SHIFT   (20U)
 
#define SIM_SOPT8_FTM0OCH4SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH5SRC_MASK   (0x200000U)
 
#define SIM_SOPT8_FTM0OCH5SRC_SHIFT   (21U)
 
#define SIM_SOPT8_FTM0OCH5SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH6SRC_MASK   (0x400000U)
 
#define SIM_SOPT8_FTM0OCH6SRC_SHIFT   (22U)
 
#define SIM_SOPT8_FTM0OCH6SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH7SRC_MASK   (0x800000U)
 
#define SIM_SOPT8_FTM0OCH7SRC_SHIFT   (23U)
 
#define SIM_SOPT8_FTM0OCH7SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH0SRC_MASK   (0x1000000U)
 
#define SIM_SOPT8_FTM3OCH0SRC_SHIFT   (24U)
 
#define SIM_SOPT8_FTM3OCH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH1SRC_MASK   (0x2000000U)
 
#define SIM_SOPT8_FTM3OCH1SRC_SHIFT   (25U)
 
#define SIM_SOPT8_FTM3OCH1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH2SRC_MASK   (0x4000000U)
 
#define SIM_SOPT8_FTM3OCH2SRC_SHIFT   (26U)
 
#define SIM_SOPT8_FTM3OCH2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH3SRC_MASK   (0x8000000U)
 
#define SIM_SOPT8_FTM3OCH3SRC_SHIFT   (27U)
 
#define SIM_SOPT8_FTM3OCH3SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH4SRC_MASK   (0x10000000U)
 
#define SIM_SOPT8_FTM3OCH4SRC_SHIFT   (28U)
 
#define SIM_SOPT8_FTM3OCH4SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH5SRC_MASK   (0x20000000U)
 
#define SIM_SOPT8_FTM3OCH5SRC_SHIFT   (29U)
 
#define SIM_SOPT8_FTM3OCH5SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH6SRC_MASK   (0x40000000U)
 
#define SIM_SOPT8_FTM3OCH6SRC_SHIFT   (30U)
 
#define SIM_SOPT8_FTM3OCH6SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH7SRC_MASK   (0x80000000U)
 
#define SIM_SOPT8_FTM3OCH7SRC_SHIFT   (31U)
 
#define SIM_SOPT8_FTM3OCH7SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
 
#define SIM_SOPT8_FTM0SYNCBIT_MASK   (0x1U)
 
#define SIM_SOPT8_FTM0SYNCBIT_SHIFT   (0U)
 
#define SIM_SOPT8_FTM0SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM1SYNCBIT_MASK   (0x2U)
 
#define SIM_SOPT8_FTM1SYNCBIT_SHIFT   (1U)
 
#define SIM_SOPT8_FTM1SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM2SYNCBIT_MASK   (0x4U)
 
#define SIM_SOPT8_FTM2SYNCBIT_SHIFT   (2U)
 
#define SIM_SOPT8_FTM2SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM3SYNCBIT_MASK   (0x8U)
 
#define SIM_SOPT8_FTM3SYNCBIT_SHIFT   (3U)
 
#define SIM_SOPT8_FTM3SYNCBIT(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
 
#define SIM_SOPT8_FTM0CFSEL_MASK   (0x100U)
 
#define SIM_SOPT8_FTM0CFSEL_SHIFT   (8U)
 
#define SIM_SOPT8_FTM0CFSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0CFSEL_SHIFT)) & SIM_SOPT8_FTM0CFSEL_MASK)
 
#define SIM_SOPT8_FTM3CFSEL_MASK   (0x200U)
 
#define SIM_SOPT8_FTM3CFSEL_SHIFT   (9U)
 
#define SIM_SOPT8_FTM3CFSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3CFSEL_SHIFT)) & SIM_SOPT8_FTM3CFSEL_MASK)
 
#define SIM_SOPT8_FTM0OCH0SRC_MASK   (0x10000U)
 
#define SIM_SOPT8_FTM0OCH0SRC_SHIFT   (16U)
 
#define SIM_SOPT8_FTM0OCH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH1SRC_MASK   (0x20000U)
 
#define SIM_SOPT8_FTM0OCH1SRC_SHIFT   (17U)
 
#define SIM_SOPT8_FTM0OCH1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH2SRC_MASK   (0x40000U)
 
#define SIM_SOPT8_FTM0OCH2SRC_SHIFT   (18U)
 
#define SIM_SOPT8_FTM0OCH2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH3SRC_MASK   (0x80000U)
 
#define SIM_SOPT8_FTM0OCH3SRC_SHIFT   (19U)
 
#define SIM_SOPT8_FTM0OCH3SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH4SRC_MASK   (0x100000U)
 
#define SIM_SOPT8_FTM0OCH4SRC_SHIFT   (20U)
 
#define SIM_SOPT8_FTM0OCH4SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH5SRC_MASK   (0x200000U)
 
#define SIM_SOPT8_FTM0OCH5SRC_SHIFT   (21U)
 
#define SIM_SOPT8_FTM0OCH5SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH6SRC_MASK   (0x400000U)
 
#define SIM_SOPT8_FTM0OCH6SRC_SHIFT   (22U)
 
#define SIM_SOPT8_FTM0OCH6SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
 
#define SIM_SOPT8_FTM0OCH7SRC_MASK   (0x800000U)
 
#define SIM_SOPT8_FTM0OCH7SRC_SHIFT   (23U)
 
#define SIM_SOPT8_FTM0OCH7SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH0SRC_MASK   (0x1000000U)
 
#define SIM_SOPT8_FTM3OCH0SRC_SHIFT   (24U)
 
#define SIM_SOPT8_FTM3OCH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH1SRC_MASK   (0x2000000U)
 
#define SIM_SOPT8_FTM3OCH1SRC_SHIFT   (25U)
 
#define SIM_SOPT8_FTM3OCH1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH2SRC_MASK   (0x4000000U)
 
#define SIM_SOPT8_FTM3OCH2SRC_SHIFT   (26U)
 
#define SIM_SOPT8_FTM3OCH2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH3SRC_MASK   (0x8000000U)
 
#define SIM_SOPT8_FTM3OCH3SRC_SHIFT   (27U)
 
#define SIM_SOPT8_FTM3OCH3SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH4SRC_MASK   (0x10000000U)
 
#define SIM_SOPT8_FTM3OCH4SRC_SHIFT   (28U)
 
#define SIM_SOPT8_FTM3OCH4SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH5SRC_MASK   (0x20000000U)
 
#define SIM_SOPT8_FTM3OCH5SRC_SHIFT   (29U)
 
#define SIM_SOPT8_FTM3OCH5SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH6SRC_MASK   (0x40000000U)
 
#define SIM_SOPT8_FTM3OCH6SRC_SHIFT   (30U)
 
#define SIM_SOPT8_FTM3OCH6SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
 
#define SIM_SOPT8_FTM3OCH7SRC_MASK   (0x80000000U)
 
#define SIM_SOPT8_FTM3OCH7SRC_SHIFT   (31U)
 
#define SIM_SOPT8_FTM3OCH7SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
 

SOPT9 - System Options Register 9

#define SIM_SOPT9_TPM1CH0SRC_MASK   (0xC0000U)
 
#define SIM_SOPT9_TPM1CH0SRC_SHIFT   (18U)
 
#define SIM_SOPT9_TPM1CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
 
#define SIM_SOPT9_TPM2CH0SRC_MASK   (0x300000U)
 
#define SIM_SOPT9_TPM2CH0SRC_SHIFT   (20U)
 
#define SIM_SOPT9_TPM2CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
 
#define SIM_SOPT9_TPM1CLKSEL_MASK   (0x2000000U)
 
#define SIM_SOPT9_TPM1CLKSEL_SHIFT   (25U)
 
#define SIM_SOPT9_TPM1CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
 
#define SIM_SOPT9_TPM2CLKSEL_MASK   (0x4000000U)
 
#define SIM_SOPT9_TPM2CLKSEL_SHIFT   (26U)
 
#define SIM_SOPT9_TPM2CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
 
#define SIM_SOPT9_TPM1CH0SRC_MASK   (0xC0000U)
 
#define SIM_SOPT9_TPM1CH0SRC_SHIFT   (18U)
 
#define SIM_SOPT9_TPM1CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
 
#define SIM_SOPT9_TPM2CH0SRC_MASK   (0x300000U)
 
#define SIM_SOPT9_TPM2CH0SRC_SHIFT   (20U)
 
#define SIM_SOPT9_TPM2CH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
 
#define SIM_SOPT9_TPM1CLKSEL_MASK   (0x2000000U)
 
#define SIM_SOPT9_TPM1CLKSEL_SHIFT   (25U)
 
#define SIM_SOPT9_TPM1CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
 
#define SIM_SOPT9_TPM2CLKSEL_MASK   (0x4000000U)
 
#define SIM_SOPT9_TPM2CLKSEL_SHIFT   (26U)
 
#define SIM_SOPT9_TPM2CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
 

CLKDIV3 - System Clock Divider Register 3

#define SIM_CLKDIV3_PLLFLLFRAC_MASK   (0x1U)
 
#define SIM_CLKDIV3_PLLFLLFRAC_SHIFT   (0U)
 
#define SIM_CLKDIV3_PLLFLLFRAC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
 
#define SIM_CLKDIV3_PLLFLLDIV_MASK   (0xEU)
 
#define SIM_CLKDIV3_PLLFLLDIV_SHIFT   (1U)
 
#define SIM_CLKDIV3_PLLFLLDIV(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
 
#define SIM_CLKDIV3_PLLFLLFRAC_MASK   (0x1U)
 
#define SIM_CLKDIV3_PLLFLLFRAC_SHIFT   (0U)
 
#define SIM_CLKDIV3_PLLFLLFRAC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
 
#define SIM_CLKDIV3_PLLFLLDIV_MASK   (0xEU)
 
#define SIM_CLKDIV3_PLLFLLDIV_SHIFT   (1U)
 
#define SIM_CLKDIV3_PLLFLLDIV(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
 

CLKDIV4 - System Clock Divider Register 4

#define SIM_CLKDIV4_TRACEFRAC_MASK   (0x1U)
 
#define SIM_CLKDIV4_TRACEFRAC_SHIFT   (0U)
 
#define SIM_CLKDIV4_TRACEFRAC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
 
#define SIM_CLKDIV4_TRACEDIV_MASK   (0xEU)
 
#define SIM_CLKDIV4_TRACEDIV_SHIFT   (1U)
 
#define SIM_CLKDIV4_TRACEDIV(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
 
#define SIM_CLKDIV4_TRACEFRAC_MASK   (0x1U)
 
#define SIM_CLKDIV4_TRACEFRAC_SHIFT   (0U)
 
#define SIM_CLKDIV4_TRACEFRAC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
 
#define SIM_CLKDIV4_TRACEDIV_MASK   (0xEU)
 
#define SIM_CLKDIV4_TRACEDIV_SHIFT   (1U)
 
#define SIM_CLKDIV4_TRACEDIV(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
 
#define SIM_CLKDIV4_TRACEFRAC_MASK   (0x1U)
 
#define SIM_CLKDIV4_TRACEFRAC_SHIFT   (0U)
 
#define SIM_CLKDIV4_TRACEFRAC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
 
#define SIM_CLKDIV4_TRACEDIV_MASK   (0xEU)
 
#define SIM_CLKDIV4_TRACEDIV_SHIFT   (1U)
 
#define SIM_CLKDIV4_TRACEDIV(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
 
#define SIM_CLKDIV4_TRACEDIVEN_MASK   (0x10000000U)
 
#define SIM_CLKDIV4_TRACEDIVEN_SHIFT   (28U)
 
#define SIM_CLKDIV4_TRACEDIVEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIVEN_SHIFT)) & SIM_CLKDIV4_TRACEDIVEN_MASK)
 

SOPT7 - System Options Register 7

#define SIM_SOPT7_HSADC0ATRGSEL_MASK   (0xFU)
 
#define SIM_SOPT7_HSADC0ATRGSEL_SHIFT   (0U)
 
#define SIM_SOPT7_HSADC0ATRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0ATRGSEL_SHIFT)) & SIM_SOPT7_HSADC0ATRGSEL_MASK)
 
#define SIM_SOPT7_HSADC0AALTTRGEN_MASK   (0xC0U)
 
#define SIM_SOPT7_HSADC0AALTTRGEN_SHIFT   (6U)
 
#define SIM_SOPT7_HSADC0AALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0AALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC0AALTTRGEN_MASK)
 
#define SIM_SOPT7_HSADC0BTRGSEL_MASK   (0xF00U)
 
#define SIM_SOPT7_HSADC0BTRGSEL_SHIFT   (8U)
 
#define SIM_SOPT7_HSADC0BTRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0BTRGSEL_SHIFT)) & SIM_SOPT7_HSADC0BTRGSEL_MASK)
 
#define SIM_SOPT7_HSADC0BALTTRGEN_MASK   (0xC000U)
 
#define SIM_SOPT7_HSADC0BALTTRGEN_SHIFT   (14U)
 
#define SIM_SOPT7_HSADC0BALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0BALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC0BALTTRGEN_MASK)
 
#define SIM_SOPT7_HSADC1ATRGSEL_MASK   (0xF0000U)
 
#define SIM_SOPT7_HSADC1ATRGSEL_SHIFT   (16U)
 
#define SIM_SOPT7_HSADC1ATRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1ATRGSEL_SHIFT)) & SIM_SOPT7_HSADC1ATRGSEL_MASK)
 
#define SIM_SOPT7_HSADC1AALTTRGEN_MASK   (0xC00000U)
 
#define SIM_SOPT7_HSADC1AALTTRGEN_SHIFT   (22U)
 
#define SIM_SOPT7_HSADC1AALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1AALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC1AALTTRGEN_MASK)
 
#define SIM_SOPT7_HSADC1BTRGSEL_MASK   (0xF000000U)
 
#define SIM_SOPT7_HSADC1BTRGSEL_SHIFT   (24U)
 
#define SIM_SOPT7_HSADC1BTRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1BTRGSEL_SHIFT)) & SIM_SOPT7_HSADC1BTRGSEL_MASK)
 
#define SIM_SOPT7_HSADC1BALTTRGEN_MASK   (0xC0000000U)
 
#define SIM_SOPT7_HSADC1BALTTRGEN_SHIFT   (30U)
 
#define SIM_SOPT7_HSADC1BALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1BALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC1BALTTRGEN_MASK)
 

SOPT9 - System Options Register 9

#define SIM_SOPT9_FTM1ICH0SRC_MASK   (0x30U)
 
#define SIM_SOPT9_FTM1ICH0SRC_SHIFT   (4U)
 
#define SIM_SOPT9_FTM1ICH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM1ICH0SRC_SHIFT)) & SIM_SOPT9_FTM1ICH0SRC_MASK)
 
#define SIM_SOPT9_FTM1ICH1SRC_MASK   (0x40U)
 
#define SIM_SOPT9_FTM1ICH1SRC_SHIFT   (6U)
 
#define SIM_SOPT9_FTM1ICH1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM1ICH1SRC_SHIFT)) & SIM_SOPT9_FTM1ICH1SRC_MASK)
 
#define SIM_SOPT9_FTM2ICH0SRC_MASK   (0x300U)
 
#define SIM_SOPT9_FTM2ICH0SRC_SHIFT   (8U)
 
#define SIM_SOPT9_FTM2ICH0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM2ICH0SRC_SHIFT)) & SIM_SOPT9_FTM2ICH0SRC_MASK)
 
#define SIM_SOPT9_FTM2ICH1SRC_MASK   (0x400U)
 
#define SIM_SOPT9_FTM2ICH1SRC_SHIFT   (10U)
 
#define SIM_SOPT9_FTM2ICH1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM2ICH1SRC_SHIFT)) & SIM_SOPT9_FTM2ICH1SRC_MASK)
 
#define SIM_SOPT9_FTM0CLKSEL_MASK   (0x3000000U)
 
#define SIM_SOPT9_FTM0CLKSEL_SHIFT   (24U)
 
#define SIM_SOPT9_FTM0CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM0CLKSEL_SHIFT)) & SIM_SOPT9_FTM0CLKSEL_MASK)
 
#define SIM_SOPT9_FTM1CLKSEL_MASK   (0xC000000U)
 
#define SIM_SOPT9_FTM1CLKSEL_SHIFT   (26U)
 
#define SIM_SOPT9_FTM1CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM1CLKSEL_SHIFT)) & SIM_SOPT9_FTM1CLKSEL_MASK)
 
#define SIM_SOPT9_FTM2CLKSEL_MASK   (0x30000000U)
 
#define SIM_SOPT9_FTM2CLKSEL_SHIFT   (28U)
 
#define SIM_SOPT9_FTM2CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM2CLKSEL_SHIFT)) & SIM_SOPT9_FTM2CLKSEL_MASK)
 
#define SIM_SOPT9_FTM3CLKSEL_MASK   (0xC0000000U)
 
#define SIM_SOPT9_FTM3CLKSEL_SHIFT   (30U)
 
#define SIM_SOPT9_FTM3CLKSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM3CLKSEL_SHIFT)) & SIM_SOPT9_FTM3CLKSEL_MASK)
 

MISCTRL0 - Miscellaneous Control Register 0

#define SIM_MISCTRL0_CMPWIN0SRC_MASK   (0x300U)
 
#define SIM_MISCTRL0_CMPWIN0SRC_SHIFT   (8U)
 
#define SIM_MISCTRL0_CMPWIN0SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN0SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN0SRC_MASK)
 
#define SIM_MISCTRL0_CMPWIN1SRC_MASK   (0xC00U)
 
#define SIM_MISCTRL0_CMPWIN1SRC_SHIFT   (10U)
 
#define SIM_MISCTRL0_CMPWIN1SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN1SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN1SRC_MASK)
 
#define SIM_MISCTRL0_CMPWIN2SRC_MASK   (0x3000U)
 
#define SIM_MISCTRL0_CMPWIN2SRC_SHIFT   (12U)
 
#define SIM_MISCTRL0_CMPWIN2SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN2SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN2SRC_MASK)
 
#define SIM_MISCTRL0_CMPWIN3SRC_MASK   (0xC000U)
 
#define SIM_MISCTRL0_CMPWIN3SRC_SHIFT   (14U)
 
#define SIM_MISCTRL0_CMPWIN3SRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN3SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN3SRC_MASK)
 
#define SIM_MISCTRL0_EWMINSRC_MASK   (0x10000U)
 
#define SIM_MISCTRL0_EWMINSRC_SHIFT   (16U)
 
#define SIM_MISCTRL0_EWMINSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_EWMINSRC_SHIFT)) & SIM_MISCTRL0_EWMINSRC_MASK)
 
#define SIM_MISCTRL0_DACTRIGSRC_MASK   (0xC0000U)
 
#define SIM_MISCTRL0_DACTRIGSRC_SHIFT   (18U)
 
#define SIM_MISCTRL0_DACTRIGSRC(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_DACTRIGSRC_SHIFT)) & SIM_MISCTRL0_DACTRIGSRC_MASK)
 

MISCTRL1 - Miscellaneous Control Register 1

#define SIM_MISCTRL1_SYNCXBARAPITTRIG0_MASK   (0x100U)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG0_SHIFT   (8U)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG0_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG0_MASK)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG1_MASK   (0x200U)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG1_SHIFT   (9U)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG1_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG1_MASK)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG2_MASK   (0x400U)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG2_SHIFT   (10U)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG2(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG2_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG2_MASK)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG3_MASK   (0x800U)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG3_SHIFT   (11U)
 
#define SIM_MISCTRL1_SYNCXBARAPITTRIG3(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG3_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG3_MASK)
 
#define SIM_MISCTRL1_SYNCXBARBPITTRIG0_MASK   (0x1000U)
 
#define SIM_MISCTRL1_SYNCXBARBPITTRIG0_SHIFT   (12U)
 
#define SIM_MISCTRL1_SYNCXBARBPITTRIG0(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARBPITTRIG0_SHIFT)) & SIM_MISCTRL1_SYNCXBARBPITTRIG0_MASK)
 
#define SIM_MISCTRL1_SYNCXBARBPITTRIG1_MASK   (0x2000U)
 
#define SIM_MISCTRL1_SYNCXBARBPITTRIG1_SHIFT   (13U)
 
#define SIM_MISCTRL1_SYNCXBARBPITTRIG1(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARBPITTRIG1_SHIFT)) & SIM_MISCTRL1_SYNCXBARBPITTRIG1_MASK)
 
#define SIM_MISCTRL1_SYNCDACHWTRIG_MASK   (0x10000U)
 
#define SIM_MISCTRL1_SYNCDACHWTRIG_SHIFT   (16U)
 
#define SIM_MISCTRL1_SYNCDACHWTRIG(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCDACHWTRIG_SHIFT)) & SIM_MISCTRL1_SYNCDACHWTRIG_MASK)
 
#define SIM_MISCTRL1_SYNCEWMIN_MASK   (0x20000U)
 
#define SIM_MISCTRL1_SYNCEWMIN_SHIFT   (17U)
 
#define SIM_MISCTRL1_SYNCEWMIN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCEWMIN_SHIFT)) & SIM_MISCTRL1_SYNCEWMIN_MASK)
 
#define SIM_MISCTRL1_SYNCCMP0SAMPLEWIN_MASK   (0x100000U)
 
#define SIM_MISCTRL1_SYNCCMP0SAMPLEWIN_SHIFT   (20U)
 
#define SIM_MISCTRL1_SYNCCMP0SAMPLEWIN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP0SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP0SAMPLEWIN_MASK)
 
#define SIM_MISCTRL1_SYNCCMP1SAMPLEWIN_MASK   (0x200000U)
 
#define SIM_MISCTRL1_SYNCCMP1SAMPLEWIN_SHIFT   (21U)
 
#define SIM_MISCTRL1_SYNCCMP1SAMPLEWIN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP1SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP1SAMPLEWIN_MASK)
 
#define SIM_MISCTRL1_SYNCCMP2SAMPLEWIN_MASK   (0x400000U)
 
#define SIM_MISCTRL1_SYNCCMP2SAMPLEWIN_SHIFT   (22U)
 
#define SIM_MISCTRL1_SYNCCMP2SAMPLEWIN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP2SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP2SAMPLEWIN_MASK)
 
#define SIM_MISCTRL1_SYNCCMP3SAMPLEWIN_MASK   (0x800000U)
 
#define SIM_MISCTRL1_SYNCCMP3SAMPLEWIN_SHIFT   (23U)
 
#define SIM_MISCTRL1_SYNCCMP3SAMPLEWIN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP3SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP3SAMPLEWIN_MASK)
 

WDOGC - WDOG Control Register

#define SIM_WDOGC_WDOGCLKS_MASK   (0x2U)
 
#define SIM_WDOGC_WDOGCLKS_SHIFT   (1U)
 
#define SIM_WDOGC_WDOGCLKS(x)   (((uint32_t)(((uint32_t)(x)) << SIM_WDOGC_WDOGCLKS_SHIFT)) & SIM_WDOGC_WDOGCLKS_MASK)
 

PWRC - Power Control Register

#define SIM_PWRC_SRPDN_MASK   (0x3U)
 
#define SIM_PWRC_SRPDN_SHIFT   (0U)
 
#define SIM_PWRC_SRPDN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPDN_SHIFT)) & SIM_PWRC_SRPDN_MASK)
 
#define SIM_PWRC_SR27STDBY_MASK   (0xCU)
 
#define SIM_PWRC_SR27STDBY_SHIFT   (2U)
 
#define SIM_PWRC_SR27STDBY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SR27STDBY_SHIFT)) & SIM_PWRC_SR27STDBY_MASK)
 
#define SIM_PWRC_SR12STDBY_MASK   (0xC0U)
 
#define SIM_PWRC_SR12STDBY_SHIFT   (6U)
 
#define SIM_PWRC_SR12STDBY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SR12STDBY_SHIFT)) & SIM_PWRC_SR12STDBY_MASK)
 
#define SIM_PWRC_SRPWRDETEN_MASK   (0x100U)
 
#define SIM_PWRC_SRPWRDETEN_SHIFT   (8U)
 
#define SIM_PWRC_SRPWRDETEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPWRDETEN_SHIFT)) & SIM_PWRC_SRPWRDETEN_MASK)
 
#define SIM_PWRC_SRPWRRDY_MASK   (0x200U)
 
#define SIM_PWRC_SRPWRRDY_SHIFT   (9U)
 
#define SIM_PWRC_SRPWRRDY(x)   (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPWRRDY_SHIFT)) & SIM_PWRC_SRPWRRDY_MASK)
 
#define SIM_PWRC_SRPWROK_MASK   (0x10000U)
 
#define SIM_PWRC_SRPWROK_SHIFT   (16U)
 
#define SIM_PWRC_SRPWROK(x)   (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPWROK_SHIFT)) & SIM_PWRC_SRPWROK_MASK)
 

ADCOPT - ADC Additional Option Register

#define SIM_ADCOPT_ADC0TRGSEL_MASK   (0xF0000U)
 
#define SIM_ADCOPT_ADC0TRGSEL_SHIFT   (16U)
 
#define SIM_ADCOPT_ADC0TRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0TRGSEL_SHIFT)) & SIM_ADCOPT_ADC0TRGSEL_MASK)
 
#define SIM_ADCOPT_ADC0PRETRGSEL_MASK   (0x100000U)
 
#define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT   (20U)
 
#define SIM_ADCOPT_ADC0PRETRGSEL(x)   (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT)) & SIM_ADCOPT_ADC0PRETRGSEL_MASK)
 
#define SIM_ADCOPT_ADC0ALTTRGEN_MASK   (0xC00000U)
 
#define SIM_ADCOPT_ADC0ALTTRGEN_SHIFT   (22U)
 
#define SIM_ADCOPT_ADC0ALTTRGEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0ALTTRGEN_SHIFT)) & SIM_ADCOPT_ADC0ALTTRGEN_MASK)
 
#define SIM_ADCOPT_HSADCIRCLK_MASK   (0x2000000U)
 
#define SIM_ADCOPT_HSADCIRCLK_SHIFT   (25U)
 
#define SIM_ADCOPT_HSADCIRCLK(x)   (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_HSADCIRCLK_SHIFT)) & SIM_ADCOPT_HSADCIRCLK_MASK)
 
#define SIM_ADCOPT_HSADCSTOPEN_MASK   (0x4000000U)
 
#define SIM_ADCOPT_HSADCSTOPEN_SHIFT   (26U)
 
#define SIM_ADCOPT_HSADCSTOPEN(x)   (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_HSADCSTOPEN_SHIFT)) & SIM_ADCOPT_HSADCSTOPEN_MASK)
 

Macro Definition Documentation

◆ SIM

#define SIM   ((SIM_Type *)SIM_BASE)

Peripheral SIM base pointer

◆ SIM_ADCOPT_ADC0ALTTRGEN

#define SIM_ADCOPT_ADC0ALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0ALTTRGEN_SHIFT)) & SIM_ADCOPT_ADC0ALTTRGEN_MASK)

ADC0ALTTRGEN - ADC0 alternate trigger enable 0b00..XBARA output 39. 0b01..PDB0 channel1 trigger selected for ADC0 0b10..PDB1 channel0 trigger selected for ADC0 0b11..Alternate trigger selected for ADC0 as defined by ADC0TRGSEL.

◆ SIM_ADCOPT_ADC0PRETRGSEL

#define SIM_ADCOPT_ADC0PRETRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT)) & SIM_ADCOPT_ADC0PRETRGSEL_MASK)

ADC0PRETRGSEL - ADC0 pretrigger select 0b0..Pre-trigger A 0b1..Pre-trigger B

◆ SIM_ADCOPT_ADC0TRGSEL

#define SIM_ADCOPT_ADC0TRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_ADC0TRGSEL_SHIFT)) & SIM_ADCOPT_ADC0TRGSEL_MASK)

ADC0TRGSEL - ADC0 trigger select 0b0000..PDB0 external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..XBARA output 38 0b1101..Reserved 0b1110..Low-power timer (LPTMR) trigger 0b1111..Reserved

◆ SIM_ADCOPT_HSADCIRCLK

#define SIM_ADCOPT_HSADCIRCLK ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_HSADCIRCLK_SHIFT)) & SIM_ADCOPT_HSADCIRCLK_MASK)

HSADCIRCLK - HSADC Clock Status 0b0..HSADC clock is Core/System clock. 0b1..HSADC clock is MCGIRCLK.

◆ SIM_ADCOPT_HSADCSTOPEN

#define SIM_ADCOPT_HSADCSTOPEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_ADCOPT_HSADCSTOPEN_SHIFT)) & SIM_ADCOPT_HSADCSTOPEN_MASK)

HSADCSTOPEN - Enable HSADCs in STOP mode 0b0..HSADCs stopsin system STOP modes 0b1..HSADCs can be enabled in system STOP modes

◆ SIM_BASE

#define SIM_BASE   (0x40047000u)

Peripheral SIM base address

◆ SIM_BASE_ADDRS

#define SIM_BASE_ADDRS   { SIM_BASE }

Array initializer of SIM peripheral base addresses

◆ SIM_BASE_PTRS

#define SIM_BASE_PTRS   { SIM }

Array initializer of SIM peripheral base pointers

◆ SIM_CLKDIV1_OUTDIV1 [1/6]

#define SIM_CLKDIV1_OUTDIV1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)

OUTDIV1 - Clock 1 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV1 [2/6]

#define SIM_CLKDIV1_OUTDIV1 ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)

OUTDIV1 - Clock 1 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV1 [3/6]

#define SIM_CLKDIV1_OUTDIV1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)

OUTDIV1 - Clock 1 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV1 [4/6]

#define SIM_CLKDIV1_OUTDIV1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)

OUTDIV1 - Clock 1 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV1 [5/6]

#define SIM_CLKDIV1_OUTDIV1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)

OUTDIV1 - Clock 1 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV1 [6/6]

#define SIM_CLKDIV1_OUTDIV1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)

OUTDIV1 - Clock 1 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV2 [1/6]

#define SIM_CLKDIV1_OUTDIV2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)

OUTDIV2 - Clock 2 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV2 [2/6]

#define SIM_CLKDIV1_OUTDIV2 ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)

OUTDIV2 - Clock 2 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV2 [3/6]

#define SIM_CLKDIV1_OUTDIV2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)

OUTDIV2 - Clock 2 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV2 [4/6]

#define SIM_CLKDIV1_OUTDIV2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)

OUTDIV2 - Clock 2 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV2 [5/6]

#define SIM_CLKDIV1_OUTDIV2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)

OUTDIV2 - Clock 2 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV2 [6/6]

#define SIM_CLKDIV1_OUTDIV2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)

OUTDIV2 - Clock 2 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV3 [1/6]

#define SIM_CLKDIV1_OUTDIV3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)

OUTDIV3 - Clock 3 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV3 [2/6]

#define SIM_CLKDIV1_OUTDIV3 ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)

OUTDIV3 - Clock 3 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV3 [3/6]

#define SIM_CLKDIV1_OUTDIV3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)

OUTDIV3 - Clock 3 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV3 [4/6]

#define SIM_CLKDIV1_OUTDIV3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)

OUTDIV3 - Clock 3 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV3 [5/6]

#define SIM_CLKDIV1_OUTDIV3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)

OUTDIV3 - Clock 3 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV3 [6/6]

#define SIM_CLKDIV1_OUTDIV3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)

OUTDIV3 - Clock 3 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV4 [1/6]

#define SIM_CLKDIV1_OUTDIV4 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)

OUTDIV4 - Clock 4 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV4 [2/6]

#define SIM_CLKDIV1_OUTDIV4 ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)

OUTDIV4 - Clock 4 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV4 [3/6]

#define SIM_CLKDIV1_OUTDIV4 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)

OUTDIV4 - Clock 4 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV4 [4/6]

#define SIM_CLKDIV1_OUTDIV4 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)

OUTDIV4 - Clock 4 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV4 [5/6]

#define SIM_CLKDIV1_OUTDIV4 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)

OUTDIV4 - Clock 4 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV1_OUTDIV4 [6/6]

#define SIM_CLKDIV1_OUTDIV4 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)

OUTDIV4 - Clock 4 output divider value 0b0000..Divide-by-1. 0b0001..Divide-by-2. 0b0010..Divide-by-3. 0b0011..Divide-by-4. 0b0100..Divide-by-5. 0b0101..Divide-by-6. 0b0110..Divide-by-7. 0b0111..Divide-by-8. 0b1000..Divide-by-9. 0b1001..Divide-by-10. 0b1010..Divide-by-11. 0b1011..Divide-by-12. 0b1100..Divide-by-13. 0b1101..Divide-by-14. 0b1110..Divide-by-15. 0b1111..Divide-by-16.

◆ SIM_CLKDIV4_TRACEDIVEN

#define SIM_CLKDIV4_TRACEDIVEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIVEN_SHIFT)) & SIM_CLKDIV4_TRACEDIVEN_MASK)

TRACEDIVEN - Debug Trace Divider Control 0b0..Debug trace divider disabled 0b1..Debug trace divider enabled

◆ SIM_FCFG1_EESIZE [1/5]

#define SIM_FCFG1_EESIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)

EESIZE - EEPROM size 0b0000..16 KB 0b0001..8 KB 0b0010..4 KB 0b0011..2 KB 0b0100..1 KB 0b0101..512 Bytes 0b0110..256 Bytes 0b0111..128 Bytes 0b1000..64 Bytes 0b1001..32 Bytes 0b1111..0 Bytes

◆ SIM_FCFG1_EESIZE [2/5]

#define SIM_FCFG1_EESIZE ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)

EESIZE - EEPROM size 0b0000..16 KB 0b0001..8 KB 0b0010..4 KB 0b0011..2 KB 0b0100..1 KB 0b0101..512 Bytes 0b0110..256 Bytes 0b0111..128 Bytes 0b1000..64 Bytes 0b1001..32 Bytes 0b1111..0 Bytes

◆ SIM_FCFG1_EESIZE [3/5]

#define SIM_FCFG1_EESIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)

EESIZE - EEPROM size 0b0000..16 KB 0b0001..8 KB 0b0010..4 KB 0b0011..2 KB 0b0100..1 KB 0b0101..512 Bytes 0b0110..256 Bytes 0b0111..128 Bytes 0b1000..64 Bytes 0b1001..32 Bytes 0b1111..0 Bytes

◆ SIM_FCFG1_EESIZE [4/5]

#define SIM_FCFG1_EESIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)

EESIZE - EEPROM size 0b0000..16 KB 0b0001..8 KB 0b0010..4 KB 0b0011..2 KB 0b0100..1 KB 0b0101..512 Bytes 0b0110..256 Bytes 0b0111..128 Bytes 0b1000..64 Bytes 0b1001..32 Bytes 0b1111..0 Bytes

◆ SIM_FCFG1_EESIZE [5/5]

#define SIM_FCFG1_EESIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)

EESIZE - EEPROM size 0b0000..16 KB 0b0001..8 KB 0b0010..4 KB 0b0011..2 KB 0b0100..1 KB 0b0101..512 Bytes 0b0110..256 Bytes 0b0111..128 Bytes 0b1000..64 Bytes 0b1001..32 Bytes 0b1111..0 Bytes

◆ SIM_FCFG1_FLASHDIS [1/5]

#define SIM_FCFG1_FLASHDIS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)

FLASHDIS - Flash Disable 0b0..Flash is enabled 0b1..Flash is disabled

◆ SIM_FCFG1_FLASHDIS [2/5]

#define SIM_FCFG1_FLASHDIS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)

FLASHDIS - Flash Disable 0b0..Flash is enabled 0b1..Flash is disabled

◆ SIM_FCFG1_FLASHDIS [3/5]

#define SIM_FCFG1_FLASHDIS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)

FLASHDIS - Flash Disable 0b0..Flash is enabled 0b1..Flash is disabled

◆ SIM_FCFG1_FLASHDIS [4/5]

#define SIM_FCFG1_FLASHDIS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)

FLASHDIS - Flash Disable 0b0..Flash is enabled 0b1..Flash is disabled

◆ SIM_FCFG1_FLASHDIS [5/5]

#define SIM_FCFG1_FLASHDIS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)

FLASHDIS - Flash Disable 0b0..Flash is enabled 0b1..Flash is disabled

◆ SIM_FCFG1_FLASHDOZE [1/5]

#define SIM_FCFG1_FLASHDOZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)

FLASHDOZE - Flash Doze 0b0..Flash remains enabled during Wait mode 0b1..Flash is disabled for the duration of Wait mode

◆ SIM_FCFG1_FLASHDOZE [2/5]

#define SIM_FCFG1_FLASHDOZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)

FLASHDOZE - Flash Doze 0b0..Flash remains enabled during Wait mode 0b1..Flash is disabled for the duration of Wait mode

◆ SIM_FCFG1_FLASHDOZE [3/5]

#define SIM_FCFG1_FLASHDOZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)

FLASHDOZE - Flash Doze 0b0..Flash remains enabled during Wait mode 0b1..Flash is disabled for the duration of Wait mode

◆ SIM_FCFG1_FLASHDOZE [4/5]

#define SIM_FCFG1_FLASHDOZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)

FLASHDOZE - Flash Doze 0b0..Flash remains enabled during Wait mode 0b1..Flash is disabled for the duration of Wait mode

◆ SIM_FCFG1_FLASHDOZE [5/5]

#define SIM_FCFG1_FLASHDOZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)

FLASHDOZE - Flash Doze 0b0..Flash remains enabled during Wait mode 0b1..Flash is disabled for the duration of Wait mode

◆ SIM_FCFG1_NVMSIZE [1/4]

#define SIM_FCFG1_NVMSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)

NVMSIZE - FlexNVM size 0b0000..0 KB of FlexNVM 0b0011..32 KB of FlexNVM 0b0101..64 KB of FlexNVM 0b0111..128 KB of FlexNVM 0b1001..256 KB of FlexNVM 0b1011..512 KB of FlexNVM 0b1111..512 KB of FlexNVM

NVMSIZE - FlexNVM size 0b0000..0 KB of FlexNVM 0b0011..32 KB of FlexNVM 0b0101..64 KB of FlexNVM 0b0111..128 KB of FlexNVM 0b1001..256 KB of FlexNVM 0b1011..512 KB of FlexNVM 0b1111..256 KB of FlexNVM

◆ SIM_FCFG1_NVMSIZE [2/4]

#define SIM_FCFG1_NVMSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)

NVMSIZE - FlexNVM size 0b0000..0 KB of FlexNVM 0b0011..32 KB of FlexNVM 0b0101..64 KB of FlexNVM 0b0111..128 KB of FlexNVM 0b1001..256 KB of FlexNVM 0b1011..512 KB of FlexNVM 0b1111..512 KB of FlexNVM

NVMSIZE - FlexNVM size 0b0000..0 KB of FlexNVM 0b0011..32 KB of FlexNVM 0b0101..64 KB of FlexNVM 0b0111..128 KB of FlexNVM 0b1001..256 KB of FlexNVM 0b1011..512 KB of FlexNVM 0b1111..256 KB of FlexNVM

◆ SIM_FCFG1_NVMSIZE [3/4]

#define SIM_FCFG1_NVMSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)

NVMSIZE - FlexNVM size 0b0000..0 KB of FlexNVM 0b0011..32 KB of FlexNVM 0b0101..64 KB of FlexNVM 0b0111..128 KB of FlexNVM 0b1001..256 KB of FlexNVM 0b1011..512 KB of FlexNVM 0b1111..256 KB of FlexNVM

◆ SIM_FCFG1_NVMSIZE [4/4]

#define SIM_FCFG1_NVMSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)

NVMSIZE - FlexNVM size 0b0000..0 KB of FlexNVM 0b0011..32 KB of FlexNVM 0b0101..64 KB of FlexNVM 0b0111..128 KB of FlexNVM 0b1001..256 KB of FlexNVM 0b1011..512 KB of FlexNVM 0b1111..256 KB of FlexNVM

◆ SIM_FCFG1_PFSIZE [1/5]

#define SIM_FCFG1_PFSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)

PFSIZE - Program flash size 0b0011..32 KB of program flash memory 0b0101..64 KB of program flash memory 0b0111..128 KB of program flash memory 0b1001..256 KB of program flash memory 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory 0b1111..1024 KB of program flash memory

PFSIZE - Program flash size 0b0011..32 KB of program flash memory 0b0101..64 KB of program flash memory 0b0111..128 KB of program flash memory 0b1001..256 KB of program flash memory 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory 0b1111..2048 KB of program flash memory

PFSIZE - Program flash size 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory

◆ SIM_FCFG1_PFSIZE [2/5]

#define SIM_FCFG1_PFSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)

PFSIZE - Program flash size 0b0011..32 KB of program flash memory 0b0101..64 KB of program flash memory 0b0111..128 KB of program flash memory 0b1001..256 KB of program flash memory 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory 0b1111..1024 KB of program flash memory

PFSIZE - Program flash size 0b0011..32 KB of program flash memory 0b0101..64 KB of program flash memory 0b0111..128 KB of program flash memory 0b1001..256 KB of program flash memory 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory 0b1111..2048 KB of program flash memory

PFSIZE - Program flash size 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory

◆ SIM_FCFG1_PFSIZE [3/5]

#define SIM_FCFG1_PFSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)

PFSIZE - Program flash size 0b0011..32 KB of program flash memory 0b0101..64 KB of program flash memory 0b0111..128 KB of program flash memory 0b1001..256 KB of program flash memory 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory 0b1111..2048 KB of program flash memory

PFSIZE - Program flash size 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory

◆ SIM_FCFG1_PFSIZE [4/5]

#define SIM_FCFG1_PFSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)

PFSIZE - Program flash size 0b0011..32 KB of program flash memory 0b0101..64 KB of program flash memory 0b0111..128 KB of program flash memory 0b1001..256 KB of program flash memory 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory 0b1111..2048 KB of program flash memory

PFSIZE - Program flash size 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory

◆ SIM_FCFG1_PFSIZE [5/5]

#define SIM_FCFG1_PFSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)

PFSIZE - Program flash size 0b1011..512 KB of program flash memory 0b1101..1024 KB of program flash memory

◆ SIM_FCFG2_PFLSH [1/4]

#define SIM_FCFG2_PFLSH ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)

PFLSH - Program flash only 0b0..Device supports FlexNVM 0b1..Program Flash only, device does not support FlexNVM

◆ SIM_FCFG2_PFLSH [2/4]

#define SIM_FCFG2_PFLSH ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)

PFLSH - Program flash only 0b0..Device supports FlexNVM 0b1..Program Flash only, device does not support FlexNVM

◆ SIM_FCFG2_PFLSH [3/4]

#define SIM_FCFG2_PFLSH ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)

PFLSH - Program flash only 0b0..Device supports FlexNVM 0b1..Program Flash only, device does not support FlexNVM

◆ SIM_FCFG2_PFLSH [4/4]

#define SIM_FCFG2_PFLSH ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)

PFLSH - Program flash only 0b0..Device supports FlexNVM 0b1..Program Flash only, device does not support FlexNVM

◆ SIM_FCFG2_SWAPPFLSH [1/3]

#define SIM_FCFG2_SWAPPFLSH ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)

SWAPPFLSH - Swap program flash 0b0..Swap is not active. 0b1..Swap is active.

◆ SIM_FCFG2_SWAPPFLSH [2/3]

#define SIM_FCFG2_SWAPPFLSH ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)

SWAPPFLSH - Swap program flash 0b0..Swap is not active. 0b1..Swap is active.

◆ SIM_FCFG2_SWAPPFLSH [3/3]

#define SIM_FCFG2_SWAPPFLSH ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)

SWAPPFLSH - Swap program flash 0b0..Swap is not active. 0b1..Swap is active.

◆ SIM_MISCTRL0_CMPWIN0SRC

#define SIM_MISCTRL0_CMPWIN0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN0SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN0SRC_MASK)

CMPWIN0SRC - CMP Sample/Window Input 0 Source 0b00..XBARA output 16. 0b01..CMP0 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 0. 0b10..PDB0 pluse-out channel 0. 0b11..PDB1 pluse-out channel 0.

◆ SIM_MISCTRL0_CMPWIN1SRC

#define SIM_MISCTRL0_CMPWIN1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN1SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN1SRC_MASK)

CMPWIN1SRC - CMP Sample/Window Input 1 Source 0b00..XBARA output 17. 0b01..CMP1 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 1. 0b10..PDB0 pluse-out channel 1. 0b11..PDB1 pluse-out channel 1.

◆ SIM_MISCTRL0_CMPWIN2SRC

#define SIM_MISCTRL0_CMPWIN2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN2SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN2SRC_MASK)

CMPWIN2SRC - CMP Sample/Window Input 2 Source 0b00..XBARA output 18. 0b01..CMP2 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 2. 0b10..PDB0 pluse-out channel 2. 0b11..PDB1 pluse-out channel 2.

◆ SIM_MISCTRL0_CMPWIN3SRC

#define SIM_MISCTRL0_CMPWIN3SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_CMPWIN3SRC_SHIFT)) & SIM_MISCTRL0_CMPWIN3SRC_MASK)

CMPWIN3SRC - CMP Sample/Window Input 3 Source 0b00..XBARA output 19. 0b01..CMP3 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 3. 0b10..PDB0 pluse-out channel 3. 0b11..PDB1 pluse-out channel 3.

◆ SIM_MISCTRL0_DACTRIGSRC

#define SIM_MISCTRL0_DACTRIGSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_DACTRIGSRC_SHIFT)) & SIM_MISCTRL0_DACTRIGSRC_MASK)

DACTRIGSRC - DAC0 Hardware Trigger Input Source 0b00..XBARA output 15. 0b01..DAC0 can be triggered by both PDB0 interval trigger 0 and PDB1 interval trigger 0. 0b10..PDB0 interval trigger 0 0b11..PDB1 interval trigger 0

◆ SIM_MISCTRL0_EWMINSRC

#define SIM_MISCTRL0_EWMINSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL0_EWMINSRC_SHIFT)) & SIM_MISCTRL0_EWMINSRC_MASK)

EWMINSRC - EWM_IN Source 0b0..XBARA output 58. 0b1..EWM_IN pin

◆ SIM_MISCTRL1_SYNCCMP0SAMPLEWIN

#define SIM_MISCTRL1_SYNCCMP0SAMPLEWIN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP0SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP0SAMPLEWIN_MASK)

SYNCCMP0SAMPLEWIN - Synchronize XBARA's output for CMP0's Sample/Window Input with flash/slow clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCCMP1SAMPLEWIN

#define SIM_MISCTRL1_SYNCCMP1SAMPLEWIN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP1SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP1SAMPLEWIN_MASK)

SYNCCMP1SAMPLEWIN - Synchronize XBARA's output for CMP1's Sample/Window Input with flash/slow clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCCMP2SAMPLEWIN

#define SIM_MISCTRL1_SYNCCMP2SAMPLEWIN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP2SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP2SAMPLEWIN_MASK)

SYNCCMP2SAMPLEWIN - Synchronize XBARA's output for CMP2's Sample/Window Input with flash/slow clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCCMP3SAMPLEWIN

#define SIM_MISCTRL1_SYNCCMP3SAMPLEWIN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCCMP3SAMPLEWIN_SHIFT)) & SIM_MISCTRL1_SYNCCMP3SAMPLEWIN_MASK)

SYNCCMP3SAMPLEWIN - Synchronize XBARA's output for CMP3's Sample/Window Input with flash/slow clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCDACHWTRIG

#define SIM_MISCTRL1_SYNCDACHWTRIG ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCDACHWTRIG_SHIFT)) & SIM_MISCTRL1_SYNCDACHWTRIG_MASK)

SYNCDACHWTRIG - Synchronize XBARA's output for DAC Hardware Trigger with flash/slow clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCEWMIN

#define SIM_MISCTRL1_SYNCEWMIN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCEWMIN_SHIFT)) & SIM_MISCTRL1_SYNCEWMIN_MASK)

SYNCEWMIN - Synchronize XBARA's output for EWM's ewm_in with flash/slow clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCXBARAPITTRIG0

#define SIM_MISCTRL1_SYNCXBARAPITTRIG0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG0_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG0_MASK)

SYNCXBARAPITTRIG0 - Synchronize XBARA's Input PIT Trigger 0 with fast clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCXBARAPITTRIG1

#define SIM_MISCTRL1_SYNCXBARAPITTRIG1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG1_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG1_MASK)

SYNCXBARAPITTRIG1 - Synchronize XBARA's Input PIT Trigger 1 with fast clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCXBARAPITTRIG2

#define SIM_MISCTRL1_SYNCXBARAPITTRIG2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG2_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG2_MASK)

SYNCXBARAPITTRIG2 - Synchronize XBARA's Input PIT Trigger 2 with fast clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCXBARAPITTRIG3

#define SIM_MISCTRL1_SYNCXBARAPITTRIG3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARAPITTRIG3_SHIFT)) & SIM_MISCTRL1_SYNCXBARAPITTRIG3_MASK)

SYNCXBARAPITTRIG3 - Synchronize XBARA's Input PIT Trigger 3 with fast clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCXBARBPITTRIG0

#define SIM_MISCTRL1_SYNCXBARBPITTRIG0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARBPITTRIG0_SHIFT)) & SIM_MISCTRL1_SYNCXBARBPITTRIG0_MASK)

SYNCXBARBPITTRIG0 - Synchronize XBARB's Input PIT Trigger 0 with fast clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_MISCTRL1_SYNCXBARBPITTRIG1

#define SIM_MISCTRL1_SYNCXBARBPITTRIG1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_MISCTRL1_SYNCXBARBPITTRIG1_SHIFT)) & SIM_MISCTRL1_SYNCXBARBPITTRIG1_MASK)

SYNCXBARBPITTRIG1 - Synchronize XBARB's Input PIT Trigger 1 with fast clock 0b0..Disable, bypass synchronizer. 0b1..Enable.

◆ SIM_PWRC_SR12STDBY

#define SIM_PWRC_SR12STDBY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SR12STDBY_SHIFT)) & SIM_PWRC_SR12STDBY_MASK)

SR12STDBY - Nanoedge Regulator 1.2 V Supply Standby Control 0b00..Nanoedge regulator 1.2 V supply placed in normal mode 0b01..Nanoedge regulator 1.2 V supply placed in standby mode. 0b10..Nanoedge regulator 1.2 V supply placed in normal mode and SR12STDBY is write protected until chip reset. 0b11..Nanoedge regulator 1.2 V supply placed in standby mode and SR12STDBY is write protected until chip reset.

◆ SIM_PWRC_SR27STDBY

#define SIM_PWRC_SR27STDBY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SR27STDBY_SHIFT)) & SIM_PWRC_SR27STDBY_MASK)

SR27STDBY - Nanoedge Regulator 2.7 V Supply Standby Control 0b00..Nanoedge regulator 2.7 V placed in normal mode. 0b01..Nanoedge regulator 2.7 V placed in standby mode. 0b10..Nanoedge regulator 2.7 V supply placed in normal mode and SR27STDBY is write protected until chip reset. 0b11..Nanoedge regulator 2.7 V supply placed in standby mode and SR27STDBY is write protected until chip reset.

◆ SIM_PWRC_SRPDN

#define SIM_PWRC_SRPDN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPDN_SHIFT)) & SIM_PWRC_SRPDN_MASK)

SRPDN - Nanoedge Regulator 2.7V and 1.2V Supply Powerdown Control 0b00..Nanoedge regulator placed in normal mode. 0b01..Nanoedge regulator placed in powerdown mode. 0b10..Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset. 0b11..Nanoedge regulator placed in powerdown mode and SRPDN is write protected until chip reset.

◆ SIM_PWRC_SRPWRDETEN

#define SIM_PWRC_SRPWRDETEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPWRDETEN_SHIFT)) & SIM_PWRC_SRPWRDETEN_MASK)

SRPWRDETEN - Nanoedge PMC POWER Dectect Enable 0b0..Disable 0b1..Enable

◆ SIM_PWRC_SRPWROK

#define SIM_PWRC_SRPWROK ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPWROK_SHIFT)) & SIM_PWRC_SRPWROK_MASK)

SRPWROK - Nanoedge PMC Status 0b0..Power supply for nanoedge isn't ready. 0b1..Power supply for nanoedge is OK.

◆ SIM_PWRC_SRPWRRDY

#define SIM_PWRC_SRPWRRDY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_PWRC_SRPWRRDY_SHIFT)) & SIM_PWRC_SRPWRRDY_MASK)

SRPWRRDY - Nanoedge PMC POWER Ready 0b0..Not ready 0b1..Assert PMC power output ready

◆ SIM_SCGC1_I2C2 [1/3]

#define SIM_SCGC1_I2C2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)

I2C2 - I2C2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_I2C2 [2/3]

#define SIM_SCGC1_I2C2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)

I2C2 - I2C2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_I2C2 [3/3]

#define SIM_SCGC1_I2C2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)

I2C2 - I2C2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_I2C3 [1/2]

#define SIM_SCGC1_I2C3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)

I2C3 - I2C3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_I2C3 [2/2]

#define SIM_SCGC1_I2C3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)

I2C3 - I2C3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_PWM1_SM0

#define SIM_SCGC1_PWM1_SM0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM0_SHIFT)) & SIM_SCGC1_PWM1_SM0_MASK)

PWM1_SM0 - PWM1 submodule 0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_PWM1_SM1

#define SIM_SCGC1_PWM1_SM1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM1_SHIFT)) & SIM_SCGC1_PWM1_SM1_MASK)

PWM1_SM1 - PWM1 submodule 1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_PWM1_SM2

#define SIM_SCGC1_PWM1_SM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM2_SHIFT)) & SIM_SCGC1_PWM1_SM2_MASK)

PWM1_SM2 - PWM1 submodule 2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_PWM1_SM3

#define SIM_SCGC1_PWM1_SM3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_PWM1_SM3_SHIFT)) & SIM_SCGC1_PWM1_SM3_MASK)

PWM1_SM3 - PWM1 submodule 3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_UART4 [1/5]

#define SIM_SCGC1_UART4 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)

UART4 - UART4 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_UART4 [2/5]

#define SIM_SCGC1_UART4 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)

UART4 - UART4 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_UART4 [3/5]

#define SIM_SCGC1_UART4 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)

UART4 - UART4 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_UART4 [4/5]

#define SIM_SCGC1_UART4 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)

UART4 - UART4 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_UART4 [5/5]

#define SIM_SCGC1_UART4 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)

UART4 - UART4 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_UART5 [1/3]

#define SIM_SCGC1_UART5 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)

UART5 - UART5 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_UART5 [2/3]

#define SIM_SCGC1_UART5 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)

UART5 - UART5 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC1_UART5 [3/3]

#define SIM_SCGC1_UART5 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)

UART5 - UART5 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_DAC0 [1/4]

#define SIM_SCGC2_DAC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)

DAC0 - DAC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_DAC0 [2/4]

#define SIM_SCGC2_DAC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)

DAC0 - DAC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_DAC0 [3/4]

#define SIM_SCGC2_DAC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)

DAC0 - DAC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_DAC0 [4/4]

#define SIM_SCGC2_DAC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)

DAC0 - DAC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_DAC1 [1/4]

#define SIM_SCGC2_DAC1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)

DAC1 - DAC1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_DAC1 [2/4]

#define SIM_SCGC2_DAC1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)

DAC1 - DAC1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_DAC1 [3/4]

#define SIM_SCGC2_DAC1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)

DAC1 - DAC1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_DAC1 [4/4]

#define SIM_SCGC2_DAC1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)

DAC1 - DAC1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_ENET [1/5]

#define SIM_SCGC2_ENET ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)

ENET - ENET Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_ENET [2/5]

#define SIM_SCGC2_ENET ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)

ENET - ENET Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_ENET [3/5]

#define SIM_SCGC2_ENET ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)

ENET - ENET Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_ENET [4/5]

#define SIM_SCGC2_ENET ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)

ENET - ENET Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_ENET [5/5]

#define SIM_SCGC2_ENET ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)

ENET - ENET Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_HSADC1

#define SIM_SCGC2_HSADC1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_HSADC1_SHIFT)) & SIM_SCGC2_HSADC1_MASK)

HSADC1 - HSADC1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_LPUART0 [1/2]

#define SIM_SCGC2_LPUART0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)

LPUART0 - LPUART0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_LPUART0 [2/2]

#define SIM_SCGC2_LPUART0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)

LPUART0 - LPUART0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_TPM1 [1/2]

#define SIM_SCGC2_TPM1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)

TPM1 - TPM1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_TPM1 [2/2]

#define SIM_SCGC2_TPM1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)

TPM1 - TPM1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_TPM2 [1/2]

#define SIM_SCGC2_TPM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)

TPM2 - TPM2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC2_TPM2 [2/2]

#define SIM_SCGC2_TPM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)

TPM2 - TPM2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_ADC1 [1/4]

#define SIM_SCGC3_ADC1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)

ADC1 - ADC1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_ADC1 [2/4]

#define SIM_SCGC3_ADC1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)

ADC1 - ADC1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_ADC1 [3/4]

#define SIM_SCGC3_ADC1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)

ADC1 - ADC1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_ADC1 [4/4]

#define SIM_SCGC3_ADC1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)

ADC1 - ADC1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FLEXCAN1 [1/3]

#define SIM_SCGC3_FLEXCAN1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)

FLEXCAN1 - FlexCAN1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FLEXCAN1 [2/3]

#define SIM_SCGC3_FLEXCAN1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)

FLEXCAN1 - FlexCAN1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FLEXCAN1 [3/3]

#define SIM_SCGC3_FLEXCAN1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)

FLEXCAN1 - FlexCAN1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FLEXCAN2

#define SIM_SCGC3_FLEXCAN2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN2_SHIFT)) & SIM_SCGC3_FLEXCAN2_MASK)

FLEXCAN2 - FlexCAN2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FTM2 [1/4]

#define SIM_SCGC3_FTM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)

FTM2 - FTM2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FTM2 [2/4]

#define SIM_SCGC3_FTM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)

FTM2 - FTM2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FTM2 [3/4]

#define SIM_SCGC3_FTM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)

FTM2 - FTM2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FTM2 [4/4]

#define SIM_SCGC3_FTM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)

FTM2 - FTM2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FTM3 [1/3]

#define SIM_SCGC3_FTM3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)

FTM3 - FTM3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FTM3 [2/3]

#define SIM_SCGC3_FTM3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)

FTM3 - FTM3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_FTM3 [3/3]

#define SIM_SCGC3_FTM3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)

FTM3 - FTM3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_RNGA [1/4]

#define SIM_SCGC3_RNGA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)

RNGA - RNGA Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_RNGA [2/4]

#define SIM_SCGC3_RNGA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)

RNGA - RNGA Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_RNGA [3/4]

#define SIM_SCGC3_RNGA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)

RNGA - RNGA Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_RNGA [4/4]

#define SIM_SCGC3_RNGA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)

RNGA - RNGA Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_SDHC [1/4]

#define SIM_SCGC3_SDHC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)

SDHC - SDHC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_SDHC [2/4]

#define SIM_SCGC3_SDHC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)

SDHC - SDHC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_SDHC [3/4]

#define SIM_SCGC3_SDHC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)

SDHC - SDHC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_SDHC [4/4]

#define SIM_SCGC3_SDHC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)

SDHC - SDHC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_SPI2 [1/5]

#define SIM_SCGC3_SPI2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)

SPI2 - SPI2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_SPI2 [2/5]

#define SIM_SCGC3_SPI2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)

SPI2 - SPI2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_SPI2 [3/5]

#define SIM_SCGC3_SPI2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)

SPI2 - SPI2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_SPI2 [4/5]

#define SIM_SCGC3_SPI2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)

SPI2 - SPI2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_SPI2 [5/5]

#define SIM_SCGC3_SPI2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)

SPI2 - SPI2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_TRNG

#define SIM_SCGC3_TRNG ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_TRNG_SHIFT)) & SIM_SCGC3_TRNG_MASK)

TRNG - TRNG Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_USBHS [1/2]

#define SIM_SCGC3_USBHS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)

USBHS - USBHS Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_USBHS [2/2]

#define SIM_SCGC3_USBHS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)

USBHS - USBHS Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_USBHSDCD [1/2]

#define SIM_SCGC3_USBHSDCD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)

USBHSDCD - USBHS DCD Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_USBHSDCD [2/2]

#define SIM_SCGC3_USBHSDCD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)

USBHSDCD - USBHS DCD Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_USBHSPHY [1/2]

#define SIM_SCGC3_USBHSPHY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)

USBHSPHY - USBHS PHY Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC3_USBHSPHY [2/2]

#define SIM_SCGC3_USBHSPHY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)

USBHSPHY - USBHS PHY Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_CMP [1/5]

#define SIM_SCGC4_CMP ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)

CMP - Comparator Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

CMP - Comparators Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_CMP [2/5]

#define SIM_SCGC4_CMP ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)

CMP - Comparator Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

CMP - Comparators Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_CMP [3/5]

#define SIM_SCGC4_CMP ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)

CMP - Comparator Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

CMP - Comparators Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_CMP [4/5]

#define SIM_SCGC4_CMP ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)

CMP - Comparator Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

CMP - Comparators Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_CMP [5/5]

#define SIM_SCGC4_CMP ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)

CMP - Comparators Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_CMT [1/4]

#define SIM_SCGC4_CMT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)

CMT - CMT Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_CMT [2/4]

#define SIM_SCGC4_CMT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)

CMT - CMT Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_CMT [3/4]

#define SIM_SCGC4_CMT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)

CMT - CMT Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_CMT [4/4]

#define SIM_SCGC4_CMT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)

CMT - CMT Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_EWM [1/5]

#define SIM_SCGC4_EWM ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)

EWM - EWM Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_EWM [2/5]

#define SIM_SCGC4_EWM ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)

EWM - EWM Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_EWM [3/5]

#define SIM_SCGC4_EWM ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)

EWM - EWM Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_EWM [4/5]

#define SIM_SCGC4_EWM ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)

EWM - EWM Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_EWM [5/5]

#define SIM_SCGC4_EWM ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)

EWM - EWM Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_I2C0 [1/5]

#define SIM_SCGC4_I2C0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)

I2C0 - I2C0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_I2C0 [2/5]

#define SIM_SCGC4_I2C0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)

I2C0 - I2C0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_I2C0 [3/5]

#define SIM_SCGC4_I2C0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)

I2C0 - I2C0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_I2C0 [4/5]

#define SIM_SCGC4_I2C0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)

I2C0 - I2C0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_I2C0 [5/5]

#define SIM_SCGC4_I2C0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)

I2C0 - I2C0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_I2C1 [1/4]

#define SIM_SCGC4_I2C1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)

I2C1 - I2C1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_I2C1 [2/4]

#define SIM_SCGC4_I2C1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)

I2C1 - I2C1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_I2C1 [3/4]

#define SIM_SCGC4_I2C1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)

I2C1 - I2C1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_I2C1 [4/4]

#define SIM_SCGC4_I2C1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)

I2C1 - I2C1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_PWM0_SM0

#define SIM_SCGC4_PWM0_SM0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM0_SHIFT)) & SIM_SCGC4_PWM0_SM0_MASK)

PWM0_SM0 - PWM0 submodule 0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_PWM0_SM1

#define SIM_SCGC4_PWM0_SM1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM1_SHIFT)) & SIM_SCGC4_PWM0_SM1_MASK)

PWM0_SM1 - PWM0 submodule 1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_PWM0_SM2

#define SIM_SCGC4_PWM0_SM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM2_SHIFT)) & SIM_SCGC4_PWM0_SM2_MASK)

PWM0_SM2 - PWM0 submodule 2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_PWM0_SM3

#define SIM_SCGC4_PWM0_SM3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_PWM0_SM3_SHIFT)) & SIM_SCGC4_PWM0_SM3_MASK)

PWM0_SM3 - PWM0 submodule 3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART0 [1/5]

#define SIM_SCGC4_UART0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)

UART0 - UART0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART0 [2/5]

#define SIM_SCGC4_UART0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)

UART0 - UART0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART0 [3/5]

#define SIM_SCGC4_UART0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)

UART0 - UART0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART0 [4/5]

#define SIM_SCGC4_UART0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)

UART0 - UART0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART0 [5/5]

#define SIM_SCGC4_UART0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)

UART0 - UART0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART1 [1/5]

#define SIM_SCGC4_UART1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)

UART1 - UART1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART1 [2/5]

#define SIM_SCGC4_UART1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)

UART1 - UART1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART1 [3/5]

#define SIM_SCGC4_UART1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)

UART1 - UART1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART1 [4/5]

#define SIM_SCGC4_UART1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)

UART1 - UART1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART1 [5/5]

#define SIM_SCGC4_UART1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)

UART1 - UART1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART2 [1/5]

#define SIM_SCGC4_UART2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)

UART2 - UART2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART2 [2/5]

#define SIM_SCGC4_UART2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)

UART2 - UART2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART2 [3/5]

#define SIM_SCGC4_UART2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)

UART2 - UART2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART2 [4/5]

#define SIM_SCGC4_UART2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)

UART2 - UART2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART2 [5/5]

#define SIM_SCGC4_UART2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)

UART2 - UART2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART3 [1/5]

#define SIM_SCGC4_UART3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)

UART3 - UART3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART3 [2/5]

#define SIM_SCGC4_UART3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)

UART3 - UART3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART3 [3/5]

#define SIM_SCGC4_UART3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)

UART3 - UART3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART3 [4/5]

#define SIM_SCGC4_UART3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)

UART3 - UART3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_UART3 [5/5]

#define SIM_SCGC4_UART3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)

UART3 - UART3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_USBOTG [1/4]

#define SIM_SCGC4_USBOTG ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)

USBOTG - USB Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_USBOTG [2/4]

#define SIM_SCGC4_USBOTG ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)

USBOTG - USB Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_USBOTG [3/4]

#define SIM_SCGC4_USBOTG ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)

USBOTG - USB Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_USBOTG [4/4]

#define SIM_SCGC4_USBOTG ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)

USBOTG - USB Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_VREF [1/4]

#define SIM_SCGC4_VREF ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)

VREF - VREF Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_VREF [2/4]

#define SIM_SCGC4_VREF ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)

VREF - VREF Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_VREF [3/4]

#define SIM_SCGC4_VREF ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)

VREF - VREF Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC4_VREF [4/4]

#define SIM_SCGC4_VREF ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)

VREF - VREF Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_AOI

#define SIM_SCGC5_AOI ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_AOI_SHIFT)) & SIM_SCGC5_AOI_MASK)

AOI - AOI Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_ENC

#define SIM_SCGC5_ENC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_ENC_SHIFT)) & SIM_SCGC5_ENC_MASK)

ENC 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_HSADC0

#define SIM_SCGC5_HSADC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_HSADC0_SHIFT)) & SIM_SCGC5_HSADC0_MASK)

HSADC0 - HSADC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_LPTMR [1/4]

#define SIM_SCGC5_LPTMR ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)

LPTMR - Low Power Timer Access Control 0b0..Access disabled 0b1..Access enabled

◆ SIM_SCGC5_LPTMR [2/4]

#define SIM_SCGC5_LPTMR ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)

LPTMR - Low Power Timer Access Control 0b0..Access disabled 0b1..Access enabled

◆ SIM_SCGC5_LPTMR [3/4]

#define SIM_SCGC5_LPTMR ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)

LPTMR - Low Power Timer Access Control 0b0..Access disabled 0b1..Access enabled

◆ SIM_SCGC5_LPTMR [4/4]

#define SIM_SCGC5_LPTMR ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)

LPTMR - Low Power Timer Access Control 0b0..Access disabled 0b1..Access enabled

◆ SIM_SCGC5_PORTA [1/5]

#define SIM_SCGC5_PORTA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)

PORTA - Port A Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTA [2/5]

#define SIM_SCGC5_PORTA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)

PORTA - Port A Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTA [3/5]

#define SIM_SCGC5_PORTA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)

PORTA - Port A Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTA [4/5]

#define SIM_SCGC5_PORTA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)

PORTA - Port A Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTA [5/5]

#define SIM_SCGC5_PORTA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)

PORTA - Port A Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTB [1/5]

#define SIM_SCGC5_PORTB ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)

PORTB - Port B Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTB [2/5]

#define SIM_SCGC5_PORTB ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)

PORTB - Port B Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTB [3/5]

#define SIM_SCGC5_PORTB ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)

PORTB - Port B Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTB [4/5]

#define SIM_SCGC5_PORTB ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)

PORTB - Port B Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTB [5/5]

#define SIM_SCGC5_PORTB ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)

PORTB - Port B Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTC [1/5]

#define SIM_SCGC5_PORTC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)

PORTC - Port C Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTC [2/5]

#define SIM_SCGC5_PORTC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)

PORTC - Port C Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTC [3/5]

#define SIM_SCGC5_PORTC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)

PORTC - Port C Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTC [4/5]

#define SIM_SCGC5_PORTC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)

PORTC - Port C Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTC [5/5]

#define SIM_SCGC5_PORTC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)

PORTC - Port C Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTD [1/5]

#define SIM_SCGC5_PORTD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)

PORTD - Port D Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTD [2/5]

#define SIM_SCGC5_PORTD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)

PORTD - Port D Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTD [3/5]

#define SIM_SCGC5_PORTD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)

PORTD - Port D Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTD [4/5]

#define SIM_SCGC5_PORTD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)

PORTD - Port D Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTD [5/5]

#define SIM_SCGC5_PORTD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)

PORTD - Port D Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTE [1/5]

#define SIM_SCGC5_PORTE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)

PORTE - Port E Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTE [2/5]

#define SIM_SCGC5_PORTE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)

PORTE - Port E Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTE [3/5]

#define SIM_SCGC5_PORTE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)

PORTE - Port E Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTE [4/5]

#define SIM_SCGC5_PORTE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)

PORTE - Port E Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_PORTE [5/5]

#define SIM_SCGC5_PORTE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)

PORTE - Port E Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_TSI [1/3]

#define SIM_SCGC5_TSI ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)

TSI - TSI Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_TSI [2/3]

#define SIM_SCGC5_TSI ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)

TSI - TSI Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_TSI [3/3]

#define SIM_SCGC5_TSI ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)

TSI - TSI Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_XBARA

#define SIM_SCGC5_XBARA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_XBARA_SHIFT)) & SIM_SCGC5_XBARA_MASK)

XBARA - XBARA Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC5_XBARB

#define SIM_SCGC5_XBARB ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_XBARB_SHIFT)) & SIM_SCGC5_XBARB_MASK)

XBARB - XBARB Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_ADC0 [1/5]

#define SIM_SCGC6_ADC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)

ADC0 - ADC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_ADC0 [2/5]

#define SIM_SCGC6_ADC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)

ADC0 - ADC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_ADC0 [3/5]

#define SIM_SCGC6_ADC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)

ADC0 - ADC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_ADC0 [4/5]

#define SIM_SCGC6_ADC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)

ADC0 - ADC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_ADC0 [5/5]

#define SIM_SCGC6_ADC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)

ADC0 - ADC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_CRC [1/5]

#define SIM_SCGC6_CRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)

CRC - CRC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_CRC [2/5]

#define SIM_SCGC6_CRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)

CRC - CRC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_CRC [3/5]

#define SIM_SCGC6_CRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)

CRC - CRC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_CRC [4/5]

#define SIM_SCGC6_CRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)

CRC - CRC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_CRC [5/5]

#define SIM_SCGC6_CRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)

CRC - CRC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_DAC0 [1/4]

#define SIM_SCGC6_DAC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)

DAC0 - DAC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_DAC0 [2/4]

#define SIM_SCGC6_DAC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)

DAC0 - DAC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_DAC0 [3/4]

#define SIM_SCGC6_DAC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)

DAC0 - DAC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_DAC0 [4/4]

#define SIM_SCGC6_DAC0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)

DAC0 - DAC0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_DMAMUX [1/5]

#define SIM_SCGC6_DMAMUX ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)

DMAMUX - DMA Mux Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_DMAMUX [2/5]

#define SIM_SCGC6_DMAMUX ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)

DMAMUX - DMA Mux Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_DMAMUX [3/5]

#define SIM_SCGC6_DMAMUX ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)

DMAMUX - DMA Mux Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_DMAMUX [4/5]

#define SIM_SCGC6_DMAMUX ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)

DMAMUX - DMA Mux Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_DMAMUX [5/5]

#define SIM_SCGC6_DMAMUX ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)

DMAMUX - DMA Mux Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FLEXCAN0 [1/5]

#define SIM_SCGC6_FLEXCAN0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)

FLEXCAN0 - FlexCAN0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FLEXCAN0 [2/5]

#define SIM_SCGC6_FLEXCAN0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)

FLEXCAN0 - FlexCAN0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FLEXCAN0 [3/5]

#define SIM_SCGC6_FLEXCAN0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)

FLEXCAN0 - FlexCAN0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FLEXCAN0 [4/5]

#define SIM_SCGC6_FLEXCAN0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)

FLEXCAN0 - FlexCAN0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FLEXCAN0 [5/5]

#define SIM_SCGC6_FLEXCAN0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)

FLEXCAN0 - FlexCAN0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FLEXCAN1

#define SIM_SCGC6_FLEXCAN1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN1_SHIFT)) & SIM_SCGC6_FLEXCAN1_MASK)

FLEXCAN1 - FlexCAN1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTF [1/4]

#define SIM_SCGC6_FTF ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)

FTF - Flash Memory Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTF [2/4]

#define SIM_SCGC6_FTF ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)

FTF - Flash Memory Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTF [3/4]

#define SIM_SCGC6_FTF ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)

FTF - Flash Memory Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTF [4/4]

#define SIM_SCGC6_FTF ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)

FTF - Flash Memory Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM0 [1/5]

#define SIM_SCGC6_FTM0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)

FTM0 - FTM0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM0 [2/5]

#define SIM_SCGC6_FTM0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)

FTM0 - FTM0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM0 [3/5]

#define SIM_SCGC6_FTM0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)

FTM0 - FTM0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM0 [4/5]

#define SIM_SCGC6_FTM0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)

FTM0 - FTM0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM0 [5/5]

#define SIM_SCGC6_FTM0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)

FTM0 - FTM0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM1 [1/5]

#define SIM_SCGC6_FTM1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)

FTM1 - FTM1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM1 [2/5]

#define SIM_SCGC6_FTM1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)

FTM1 - FTM1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM1 [3/5]

#define SIM_SCGC6_FTM1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)

FTM1 - FTM1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM1 [4/5]

#define SIM_SCGC6_FTM1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)

FTM1 - FTM1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM1 [5/5]

#define SIM_SCGC6_FTM1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)

FTM1 - FTM1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM2 [1/4]

#define SIM_SCGC6_FTM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)

FTM2 - FTM2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM2 [2/4]

#define SIM_SCGC6_FTM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)

FTM2 - FTM2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM2 [3/4]

#define SIM_SCGC6_FTM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)

FTM2 - FTM2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM2 [4/4]

#define SIM_SCGC6_FTM2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)

FTM2 - FTM2 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_FTM3

#define SIM_SCGC6_FTM3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM3_SHIFT)) & SIM_SCGC6_FTM3_MASK)

FTM3 - FTM3 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_I2S [1/4]

#define SIM_SCGC6_I2S ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)

I2S - I2S Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_I2S [2/4]

#define SIM_SCGC6_I2S ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)

I2S - I2S Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_I2S [3/4]

#define SIM_SCGC6_I2S ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)

I2S - I2S Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_I2S [4/4]

#define SIM_SCGC6_I2S ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)

I2S - I2S Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PDB [1/4]

#define SIM_SCGC6_PDB ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)

PDB - PDB Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PDB [2/4]

#define SIM_SCGC6_PDB ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)

PDB - PDB Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PDB [3/4]

#define SIM_SCGC6_PDB ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)

PDB - PDB Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PDB [4/4]

#define SIM_SCGC6_PDB ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)

PDB - PDB Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PDB0

#define SIM_SCGC6_PDB0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB0_SHIFT)) & SIM_SCGC6_PDB0_MASK)

PDB0 - PDB0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PDB1

#define SIM_SCGC6_PDB1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB1_SHIFT)) & SIM_SCGC6_PDB1_MASK)

PDB1 - PDB1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PIT [1/5]

#define SIM_SCGC6_PIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)

PIT - PIT Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PIT [2/5]

#define SIM_SCGC6_PIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)

PIT - PIT Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PIT [3/5]

#define SIM_SCGC6_PIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)

PIT - PIT Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PIT [4/5]

#define SIM_SCGC6_PIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)

PIT - PIT Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_PIT [5/5]

#define SIM_SCGC6_PIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)

PIT - PIT Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_RTC [1/4]

#define SIM_SCGC6_RTC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)

RTC - RTC Access Control 0b0..Access and interrupts disabled 0b1..Access and interrupts enabled

◆ SIM_SCGC6_RTC [2/4]

#define SIM_SCGC6_RTC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)

RTC - RTC Access Control 0b0..Access and interrupts disabled 0b1..Access and interrupts enabled

◆ SIM_SCGC6_RTC [3/4]

#define SIM_SCGC6_RTC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)

RTC - RTC Access Control 0b0..Access and interrupts disabled 0b1..Access and interrupts enabled

◆ SIM_SCGC6_RTC [4/4]

#define SIM_SCGC6_RTC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)

RTC - RTC Access Control 0b0..Access and interrupts disabled 0b1..Access and interrupts enabled

◆ SIM_SCGC6_SPI0 [1/5]

#define SIM_SCGC6_SPI0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)

SPI0 - SPI0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_SPI0 [2/5]

#define SIM_SCGC6_SPI0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)

SPI0 - SPI0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_SPI0 [3/5]

#define SIM_SCGC6_SPI0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)

SPI0 - SPI0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_SPI0 [4/5]

#define SIM_SCGC6_SPI0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)

SPI0 - SPI0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_SPI0 [5/5]

#define SIM_SCGC6_SPI0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)

SPI0 - SPI0 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_SPI1 [1/5]

#define SIM_SCGC6_SPI1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)

SPI1 - SPI1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_SPI1 [2/5]

#define SIM_SCGC6_SPI1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)

SPI1 - SPI1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_SPI1 [3/5]

#define SIM_SCGC6_SPI1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)

SPI1 - SPI1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_SPI1 [4/5]

#define SIM_SCGC6_SPI1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)

SPI1 - SPI1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_SPI1 [5/5]

#define SIM_SCGC6_SPI1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)

SPI1 - SPI1 Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_USBDCD [1/4]

#define SIM_SCGC6_USBDCD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)

USBDCD - USB DCD Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_USBDCD [2/4]

#define SIM_SCGC6_USBDCD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)

USBDCD - USB DCD Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_USBDCD [3/4]

#define SIM_SCGC6_USBDCD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)

USBDCD - USB DCD Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC6_USBDCD [4/4]

#define SIM_SCGC6_USBDCD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)

USBDCD - USB DCD Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_DMA [1/5]

#define SIM_SCGC7_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)

DMA - DMA Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_DMA [2/5]

#define SIM_SCGC7_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)

DMA - DMA Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_DMA [3/5]

#define SIM_SCGC7_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)

DMA - DMA Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_DMA [4/5]

#define SIM_SCGC7_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)

DMA - DMA Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_DMA [5/5]

#define SIM_SCGC7_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)

DMA - DMA Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_FLEXBUS [1/5]

#define SIM_SCGC7_FLEXBUS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)

FLEXBUS - FlexBus Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_FLEXBUS [2/5]

#define SIM_SCGC7_FLEXBUS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)

FLEXBUS - FlexBus Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_FLEXBUS [3/5]

#define SIM_SCGC7_FLEXBUS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)

FLEXBUS - FlexBus Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_FLEXBUS [4/5]

#define SIM_SCGC7_FLEXBUS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)

FLEXBUS - FlexBus Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_FLEXBUS [5/5]

#define SIM_SCGC7_FLEXBUS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)

FLEXBUS - FlexBus Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_MPU [1/4]

#define SIM_SCGC7_MPU ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)

MPU - MPU Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_MPU [2/4]

#define SIM_SCGC7_MPU ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)

MPU - MPU Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_MPU [3/4]

#define SIM_SCGC7_MPU ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)

MPU - MPU Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_MPU [4/4]

#define SIM_SCGC7_MPU ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)

MPU - MPU Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_SDRAMC [1/2]

#define SIM_SCGC7_SDRAMC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)

SDRAMC - SDRAMC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_SDRAMC [2/2]

#define SIM_SCGC7_SDRAMC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)

SDRAMC - SDRAMC Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SCGC7_SMPU

#define SIM_SCGC7_SMPU ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SMPU_SHIFT)) & SIM_SCGC7_SMPU_MASK)

SMPU - SMPU Clock Gate Control 0b0..Clock disabled 0b1..Clock enabled

◆ SIM_SDID_DIEID [1/4]

#define SIM_SDID_DIEID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)

DIEID - Device die number 0b00011..KV5x

◆ SIM_SDID_DIEID [2/4]

#define SIM_SDID_DIEID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)

DIEID - Device die number 0b00011..KV5x

◆ SIM_SDID_DIEID [3/4]

#define SIM_SDID_DIEID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)

DIEID - Device die number 0b00011..KV5x

◆ SIM_SDID_DIEID [4/4]

#define SIM_SDID_DIEID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)

DIEID - Device die number 0b00011..KV5x

◆ SIM_SDID_FAMID [1/5]

#define SIM_SDID_FAMID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)

FAMID - Kinetis family identification 0b000..K1x Family (without tamper) 0b001..K2x Family (without tamper) 0b010..K3x Family or K1x/K6x Family (with tamper) 0b011..K4x Family or K2x Family (with tamper) 0b100..K6x Family (without tamper) 0b101..K7x Family 0b110..Reserved 0b111..Reserved

◆ SIM_SDID_FAMID [2/5]

#define SIM_SDID_FAMID ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)

FAMID - Kinetis family identification 0b000..K1x Family (without tamper) 0b001..K2x Family (without tamper) 0b010..K3x Family or K1x/K6x Family (with tamper) 0b011..K4x Family or K2x Family (with tamper) 0b100..K6x Family (without tamper) 0b101..K7x Family 0b110..Reserved 0b111..Reserved

◆ SIM_SDID_FAMID [3/5]

#define SIM_SDID_FAMID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)

FAMID - Kinetis family identification 0b000..K1x Family (without tamper) 0b001..K2x Family (without tamper) 0b010..K3x Family or K1x/K6x Family (with tamper) 0b011..K4x Family or K2x Family (with tamper) 0b100..K6x Family (without tamper) 0b101..K7x Family 0b110..Reserved 0b111..Reserved

◆ SIM_SDID_FAMID [4/5]

#define SIM_SDID_FAMID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)

FAMID - Kinetis family identification 0b000..K1x Family (without tamper) 0b001..K2x Family (without tamper) 0b010..K3x Family or K1x/K6x Family (with tamper) 0b011..K4x Family or K2x Family (with tamper) 0b100..K6x Family (without tamper) 0b101..K7x Family 0b110..Reserved 0b111..Reserved

◆ SIM_SDID_FAMID [5/5]

#define SIM_SDID_FAMID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)

FAMID - Kinetis family identification 0b000..K1x Family (without tamper) 0b001..K2x Family (without tamper) 0b010..K3x Family or K1x/K6x Family (with tamper) 0b011..K4x Family or K2x Family (with tamper) 0b100..K6x Family (without tamper) 0b101..K7x Family 0b110..Reserved 0b111..Reserved

◆ SIM_SDID_FAMILYID [1/4]

#define SIM_SDID_FAMILYID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)

FAMILYID - Kinetis Family ID 0b0001..K1x Family 0b0010..K2x Family 0b0011..K3x Family 0b0100..K4x Family 0b0110..K6x Family 0b0111..K7x Family

FAMILYID - Kinetis Family ID 0b0000..K0x Family 0b0001..K1x Family 0b0010..K2x Family 0b0011..K3x Family 0b0100..K4x Family 0b0110..K6x Family 0b0111..K7x Family 0b1000..K8x Family

FAMILYID - Kinetis Family ID 0b0101..This is the KV5x series

◆ SIM_SDID_FAMILYID [2/4]

#define SIM_SDID_FAMILYID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)

FAMILYID - Kinetis Family ID 0b0000..K0x Family 0b0001..K1x Family 0b0010..K2x Family 0b0011..K3x Family 0b0100..K4x Family 0b0110..K6x Family 0b0111..K7x Family 0b1000..K8x Family

FAMILYID - Kinetis Family ID 0b0101..This is the KV5x series

◆ SIM_SDID_FAMILYID [3/4]

#define SIM_SDID_FAMILYID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)

FAMILYID - Kinetis Family ID 0b0000..K0x Family 0b0001..K1x Family 0b0010..K2x Family 0b0011..K3x Family 0b0100..K4x Family 0b0110..K6x Family 0b0111..K7x Family 0b1000..K8x Family

FAMILYID - Kinetis Family ID 0b0101..This is the KV5x series

◆ SIM_SDID_FAMILYID [4/4]

#define SIM_SDID_FAMILYID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)

FAMILYID - Kinetis Family ID 0b0101..This is the KV5x series

◆ SIM_SDID_PINID [1/6]

#define SIM_SDID_PINID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)

PINID - Pincount identification 0b0000..Reserved 0b0001..Reserved 0b0010..32-pin 0b0011..Reserved 0b0100..48-pin 0b0101..64-pin 0b0110..80-pin 0b0111..81-pin or 121-pin 0b1000..100-pin 0b1001..121-pin 0b1010..144-pin 0b1011..Custom pinout (WLCSP) 0b1100..169-pin 0b1101..Reserved 0b1110..256-pin 0b1111..Reserved

PINID - Pincount identification 0b1000..100-pin 0b1001..Reserved 0b1010..144-pin

◆ SIM_SDID_PINID [2/6]

#define SIM_SDID_PINID ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)

PINID - Pincount identification 0b0000..Reserved 0b0001..Reserved 0b0010..32-pin 0b0011..Reserved 0b0100..48-pin 0b0101..64-pin 0b0110..80-pin 0b0111..81-pin or 121-pin 0b1000..100-pin 0b1001..121-pin 0b1010..144-pin 0b1011..Custom pinout (WLCSP) 0b1100..169-pin 0b1101..Reserved 0b1110..256-pin 0b1111..Reserved

PINID - Pincount identification 0b1000..100-pin 0b1001..Reserved 0b1010..144-pin

◆ SIM_SDID_PINID [3/6]

#define SIM_SDID_PINID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)

PINID - Pincount identification 0b0000..Reserved 0b0001..Reserved 0b0010..32-pin 0b0011..Reserved 0b0100..48-pin 0b0101..64-pin 0b0110..80-pin 0b0111..81-pin or 121-pin 0b1000..100-pin 0b1001..121-pin 0b1010..144-pin 0b1011..Custom pinout (WLCSP) 0b1100..169-pin 0b1101..Reserved 0b1110..256-pin 0b1111..Reserved

PINID - Pincount identification 0b1000..100-pin 0b1001..Reserved 0b1010..144-pin

◆ SIM_SDID_PINID [4/6]

#define SIM_SDID_PINID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)

PINID - Pincount identification 0b0000..Reserved 0b0001..Reserved 0b0010..32-pin 0b0011..Reserved 0b0100..48-pin 0b0101..64-pin 0b0110..80-pin 0b0111..81-pin or 121-pin 0b1000..100-pin 0b1001..121-pin 0b1010..144-pin 0b1011..Custom pinout (WLCSP) 0b1100..169-pin 0b1101..Reserved 0b1110..256-pin 0b1111..Reserved

PINID - Pincount identification 0b1000..100-pin 0b1001..Reserved 0b1010..144-pin

◆ SIM_SDID_PINID [5/6]

#define SIM_SDID_PINID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)

PINID - Pincount identification 0b0000..Reserved 0b0001..Reserved 0b0010..32-pin 0b0011..Reserved 0b0100..48-pin 0b0101..64-pin 0b0110..80-pin 0b0111..81-pin or 121-pin 0b1000..100-pin 0b1001..121-pin 0b1010..144-pin 0b1011..Custom pinout (WLCSP) 0b1100..169-pin 0b1101..Reserved 0b1110..256-pin 0b1111..Reserved

PINID - Pincount identification 0b1000..100-pin 0b1001..Reserved 0b1010..144-pin

◆ SIM_SDID_PINID [6/6]

#define SIM_SDID_PINID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)

PINID - Pincount identification 0b1000..100-pin 0b1001..Reserved 0b1010..144-pin

◆ SIM_SDID_SERIESID [1/4]

#define SIM_SDID_SERIESID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)

SERIESID - Kinetis Series ID 0b0000..Kinetis K series 0b0001..Kinetis L series 0b0101..Kinetis W series 0b0110..Kinetis V series

SERIESID - Kinetis Series ID 0b0110..Kinetis V series

◆ SIM_SDID_SERIESID [2/4]

#define SIM_SDID_SERIESID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)

SERIESID - Kinetis Series ID 0b0000..Kinetis K series 0b0001..Kinetis L series 0b0101..Kinetis W series 0b0110..Kinetis V series

SERIESID - Kinetis Series ID 0b0110..Kinetis V series

◆ SIM_SDID_SERIESID [3/4]

#define SIM_SDID_SERIESID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)

SERIESID - Kinetis Series ID 0b0000..Kinetis K series 0b0001..Kinetis L series 0b0101..Kinetis W series 0b0110..Kinetis V series

SERIESID - Kinetis Series ID 0b0110..Kinetis V series

◆ SIM_SDID_SERIESID [4/4]

#define SIM_SDID_SERIESID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)

SERIESID - Kinetis Series ID 0b0110..Kinetis V series

◆ SIM_SDID_SUBFAMID [1/4]

#define SIM_SDID_SUBFAMID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)

SUBFAMID - Kinetis Sub-Family ID 0b0000..Kx0 Subfamily 0b0001..Kx1 Subfamily (tamper detect) 0b0010..Kx2 Subfamily 0b0011..Kx3 Subfamily (tamper detect) 0b0100..Kx4 Subfamily 0b0101..Kx5 Subfamily (tamper detect) 0b0110..Kx6 Subfamily

SUBFAMID - Kinetis Sub-Family ID 0b0110..KVx6 Subfamily (eFlexPWM with FlexTimer and HSADC) 0b0111..Reserved 0b1000..KVx8 Subfamily (eFlexPWM with FlexTimer, HSADC, and Ethernet)

◆ SIM_SDID_SUBFAMID [2/4]

#define SIM_SDID_SUBFAMID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)

SUBFAMID - Kinetis Sub-Family ID 0b0000..Kx0 Subfamily 0b0001..Kx1 Subfamily (tamper detect) 0b0010..Kx2 Subfamily 0b0011..Kx3 Subfamily (tamper detect) 0b0100..Kx4 Subfamily 0b0101..Kx5 Subfamily (tamper detect) 0b0110..Kx6 Subfamily

SUBFAMID - Kinetis Sub-Family ID 0b0110..KVx6 Subfamily (eFlexPWM with FlexTimer and HSADC) 0b0111..Reserved 0b1000..KVx8 Subfamily (eFlexPWM with FlexTimer, HSADC, and Ethernet)

◆ SIM_SDID_SUBFAMID [3/4]

#define SIM_SDID_SUBFAMID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)

SUBFAMID - Kinetis Sub-Family ID 0b0000..Kx0 Subfamily 0b0001..Kx1 Subfamily (tamper detect) 0b0010..Kx2 Subfamily 0b0011..Kx3 Subfamily (tamper detect) 0b0100..Kx4 Subfamily 0b0101..Kx5 Subfamily (tamper detect) 0b0110..Kx6 Subfamily

SUBFAMID - Kinetis Sub-Family ID 0b0110..KVx6 Subfamily (eFlexPWM with FlexTimer and HSADC) 0b0111..Reserved 0b1000..KVx8 Subfamily (eFlexPWM with FlexTimer, HSADC, and Ethernet)

◆ SIM_SDID_SUBFAMID [4/4]

#define SIM_SDID_SUBFAMID ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)

SUBFAMID - Kinetis Sub-Family ID 0b0110..KVx6 Subfamily (eFlexPWM with FlexTimer and HSADC) 0b0111..Reserved 0b1000..KVx8 Subfamily (eFlexPWM with FlexTimer, HSADC, and Ethernet)

◆ SIM_SOPT1_OSC32KSEL [1/5]

#define SIM_SOPT1_OSC32KSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)

OSC32KSEL - 32K oscillator clock select 0b00..System oscillator (OSC32KCLK) 0b01..Reserved 0b10..RTC 32.768kHz oscillator 0b11..LPO 1 kHz

OSC32KSEL - 32K oscillator clock select 0b00..System oscillator (OSC32KCLK) 0b01..Reserved 0b10..Reserved 0b11..LPO 1 kHz

◆ SIM_SOPT1_OSC32KSEL [2/5]

#define SIM_SOPT1_OSC32KSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)

OSC32KSEL - 32K oscillator clock select 0b00..System oscillator (OSC32KCLK) 0b01..Reserved 0b10..RTC 32.768kHz oscillator 0b11..LPO 1 kHz

OSC32KSEL - 32K oscillator clock select 0b00..System oscillator (OSC32KCLK) 0b01..Reserved 0b10..Reserved 0b11..LPO 1 kHz

◆ SIM_SOPT1_OSC32KSEL [3/5]

#define SIM_SOPT1_OSC32KSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)

OSC32KSEL - 32K oscillator clock select 0b00..System oscillator (OSC32KCLK) 0b01..Reserved 0b10..RTC 32.768kHz oscillator 0b11..LPO 1 kHz

OSC32KSEL - 32K oscillator clock select 0b00..System oscillator (OSC32KCLK) 0b01..Reserved 0b10..Reserved 0b11..LPO 1 kHz

◆ SIM_SOPT1_OSC32KSEL [4/5]

#define SIM_SOPT1_OSC32KSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)

OSC32KSEL - 32K oscillator clock select 0b00..System oscillator (OSC32KCLK) 0b01..Reserved 0b10..RTC 32.768kHz oscillator 0b11..LPO 1 kHz

OSC32KSEL - 32K oscillator clock select 0b00..System oscillator (OSC32KCLK) 0b01..Reserved 0b10..Reserved 0b11..LPO 1 kHz

◆ SIM_SOPT1_OSC32KSEL [5/5]

#define SIM_SOPT1_OSC32KSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)

OSC32KSEL - 32K oscillator clock select 0b00..System oscillator (OSC32KCLK) 0b01..Reserved 0b10..Reserved 0b11..LPO 1 kHz

◆ SIM_SOPT1_RAMSIZE [1/6]

#define SIM_SOPT1_RAMSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)

RAMSIZE - RAM size 0b0001..8 KB 0b0011..16 KB 0b0100..24 KB 0b0101..32 KB 0b0110..48 KB 0b0111..64 KB 0b1000..96 KB 0b1001..128 KB 0b1011..256 KB

RAMSIZE - RAM size 0b0001..Reserved 0b0011..Reserved 0b0100..Reserved 0b0101..Reserved 0b0110..Reserved 0b0111..Reserved 0b1000..Reserved 0b1001..128 KB 0b1011..256 KB

◆ SIM_SOPT1_RAMSIZE [2/6]

#define SIM_SOPT1_RAMSIZE ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)

RAMSIZE - RAM size 0b0001..8 KB 0b0011..16 KB 0b0100..24 KB 0b0101..32 KB 0b0110..48 KB 0b0111..64 KB 0b1000..96 KB 0b1001..128 KB 0b1011..256 KB

RAMSIZE - RAM size 0b0001..Reserved 0b0011..Reserved 0b0100..Reserved 0b0101..Reserved 0b0110..Reserved 0b0111..Reserved 0b1000..Reserved 0b1001..128 KB 0b1011..256 KB

◆ SIM_SOPT1_RAMSIZE [3/6]

#define SIM_SOPT1_RAMSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)

RAMSIZE - RAM size 0b0001..8 KB 0b0011..16 KB 0b0100..24 KB 0b0101..32 KB 0b0110..48 KB 0b0111..64 KB 0b1000..96 KB 0b1001..128 KB 0b1011..256 KB

RAMSIZE - RAM size 0b0001..Reserved 0b0011..Reserved 0b0100..Reserved 0b0101..Reserved 0b0110..Reserved 0b0111..Reserved 0b1000..Reserved 0b1001..128 KB 0b1011..256 KB

◆ SIM_SOPT1_RAMSIZE [4/6]

#define SIM_SOPT1_RAMSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)

RAMSIZE - RAM size 0b0001..8 KB 0b0011..16 KB 0b0100..24 KB 0b0101..32 KB 0b0110..48 KB 0b0111..64 KB 0b1000..96 KB 0b1001..128 KB 0b1011..256 KB

RAMSIZE - RAM size 0b0001..Reserved 0b0011..Reserved 0b0100..Reserved 0b0101..Reserved 0b0110..Reserved 0b0111..Reserved 0b1000..Reserved 0b1001..128 KB 0b1011..256 KB

◆ SIM_SOPT1_RAMSIZE [5/6]

#define SIM_SOPT1_RAMSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)

RAMSIZE - RAM size 0b0001..8 KB 0b0011..16 KB 0b0100..24 KB 0b0101..32 KB 0b0110..48 KB 0b0111..64 KB 0b1000..96 KB 0b1001..128 KB 0b1011..256 KB

RAMSIZE - RAM size 0b0001..Reserved 0b0011..Reserved 0b0100..Reserved 0b0101..Reserved 0b0110..Reserved 0b0111..Reserved 0b1000..Reserved 0b1001..128 KB 0b1011..256 KB

◆ SIM_SOPT1_RAMSIZE [6/6]

#define SIM_SOPT1_RAMSIZE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)

RAMSIZE - RAM size 0b0001..Reserved 0b0011..Reserved 0b0100..Reserved 0b0101..Reserved 0b0110..Reserved 0b0111..Reserved 0b1000..Reserved 0b1001..128 KB 0b1011..256 KB

◆ SIM_SOPT1_USBREGEN [1/4]

#define SIM_SOPT1_USBREGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)

USBREGEN - USB voltage regulator enable 0b0..USB voltage regulator is disabled. 0b1..USB voltage regulator is enabled.

◆ SIM_SOPT1_USBREGEN [2/4]

#define SIM_SOPT1_USBREGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)

USBREGEN - USB voltage regulator enable 0b0..USB voltage regulator is disabled. 0b1..USB voltage regulator is enabled.

◆ SIM_SOPT1_USBREGEN [3/4]

#define SIM_SOPT1_USBREGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)

USBREGEN - USB voltage regulator enable 0b0..USB voltage regulator is disabled. 0b1..USB voltage regulator is enabled.

◆ SIM_SOPT1_USBREGEN [4/4]

#define SIM_SOPT1_USBREGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)

USBREGEN - USB voltage regulator enable 0b0..USB voltage regulator is disabled. 0b1..USB voltage regulator is enabled.

◆ SIM_SOPT1_USBSSTBY [1/4]

#define SIM_SOPT1_USBSSTBY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)

USBSSTBY - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. 0b0..USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. 0b1..USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.

◆ SIM_SOPT1_USBSSTBY [2/4]

#define SIM_SOPT1_USBSSTBY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)

USBSSTBY - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. 0b0..USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. 0b1..USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.

◆ SIM_SOPT1_USBSSTBY [3/4]

#define SIM_SOPT1_USBSSTBY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)

USBSSTBY - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. 0b0..USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. 0b1..USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.

◆ SIM_SOPT1_USBSSTBY [4/4]

#define SIM_SOPT1_USBSSTBY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)

USBSSTBY - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. 0b0..USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. 0b1..USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.

◆ SIM_SOPT1_USBVSTBY [1/4]

#define SIM_SOPT1_USBVSTBY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)

USBVSTBY - USB voltage regulator in standby mode during VLPR and VLPW modes 0b0..USB voltage regulator not in standby during VLPR and VLPW modes. 0b1..USB voltage regulator in standby during VLPR and VLPW modes.

◆ SIM_SOPT1_USBVSTBY [2/4]

#define SIM_SOPT1_USBVSTBY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)

USBVSTBY - USB voltage regulator in standby mode during VLPR and VLPW modes 0b0..USB voltage regulator not in standby during VLPR and VLPW modes. 0b1..USB voltage regulator in standby during VLPR and VLPW modes.

◆ SIM_SOPT1_USBVSTBY [3/4]

#define SIM_SOPT1_USBVSTBY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)

USBVSTBY - USB voltage regulator in standby mode during VLPR and VLPW modes 0b0..USB voltage regulator not in standby during VLPR and VLPW modes. 0b1..USB voltage regulator in standby during VLPR and VLPW modes.

◆ SIM_SOPT1_USBVSTBY [4/4]

#define SIM_SOPT1_USBVSTBY ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)

USBVSTBY - USB voltage regulator in standby mode during VLPR and VLPW modes 0b0..USB voltage regulator not in standby during VLPR and VLPW modes. 0b1..USB voltage regulator in standby during VLPR and VLPW modes.

◆ SIM_SOPT1CFG_URWE [1/4]

#define SIM_SOPT1CFG_URWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)

URWE - USB voltage regulator enable write enable 0b0..SOPT1 USBREGEN cannot be written. 0b1..SOPT1 USBREGEN can be written.

◆ SIM_SOPT1CFG_URWE [2/4]

#define SIM_SOPT1CFG_URWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)

URWE - USB voltage regulator enable write enable 0b0..SOPT1 USBREGEN cannot be written. 0b1..SOPT1 USBREGEN can be written.

◆ SIM_SOPT1CFG_URWE [3/4]

#define SIM_SOPT1CFG_URWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)

URWE - USB voltage regulator enable write enable 0b0..SOPT1 USBREGEN cannot be written. 0b1..SOPT1 USBREGEN can be written.

◆ SIM_SOPT1CFG_URWE [4/4]

#define SIM_SOPT1CFG_URWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)

URWE - USB voltage regulator enable write enable 0b0..SOPT1 USBREGEN cannot be written. 0b1..SOPT1 USBREGEN can be written.

◆ SIM_SOPT1CFG_USSWE [1/4]

#define SIM_SOPT1CFG_USSWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)

USSWE - USB voltage regulator stop standby write enable 0b0..SOPT1 USBSSTBY cannot be written. 0b1..SOPT1 USBSSTBY can be written.

◆ SIM_SOPT1CFG_USSWE [2/4]

#define SIM_SOPT1CFG_USSWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)

USSWE - USB voltage regulator stop standby write enable 0b0..SOPT1 USBSSTBY cannot be written. 0b1..SOPT1 USBSSTBY can be written.

◆ SIM_SOPT1CFG_USSWE [3/4]

#define SIM_SOPT1CFG_USSWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)

USSWE - USB voltage regulator stop standby write enable 0b0..SOPT1 USBSSTBY cannot be written. 0b1..SOPT1 USBSSTBY can be written.

◆ SIM_SOPT1CFG_USSWE [4/4]

#define SIM_SOPT1CFG_USSWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)

USSWE - USB voltage regulator stop standby write enable 0b0..SOPT1 USBSSTBY cannot be written. 0b1..SOPT1 USBSSTBY can be written.

◆ SIM_SOPT1CFG_UVSWE [1/4]

#define SIM_SOPT1CFG_UVSWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)

UVSWE - USB voltage regulator VLP standby write enable 0b0..SOPT1 USBVSTBY cannot be written. 0b1..SOPT1 USBVSTBY can be written.

◆ SIM_SOPT1CFG_UVSWE [2/4]

#define SIM_SOPT1CFG_UVSWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)

UVSWE - USB voltage regulator VLP standby write enable 0b0..SOPT1 USBVSTBY cannot be written. 0b1..SOPT1 USBVSTBY can be written.

◆ SIM_SOPT1CFG_UVSWE [3/4]

#define SIM_SOPT1CFG_UVSWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)

UVSWE - USB voltage regulator VLP standby write enable 0b0..SOPT1 USBVSTBY cannot be written. 0b1..SOPT1 USBVSTBY can be written.

◆ SIM_SOPT1CFG_UVSWE [4/4]

#define SIM_SOPT1CFG_UVSWE ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)

UVSWE - USB voltage regulator VLP standby write enable 0b0..SOPT1 USBVSTBY cannot be written. 0b1..SOPT1 USBVSTBY can be written.

◆ SIM_SOPT2_CLKOUTSEL [1/5]

#define SIM_SOPT2_CLKOUTSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)

CLKOUTSEL - CLKOUT select 0b000..FlexBus CLKOUT 0b001..Reserved 0b010..Flash clock 0b011..LPO clock (1 kHz) 0b100..MCGIRCLK 0b101..RTC 32.768kHz clock 0b110..OSCERCLK0 0b111..IRC 48 MHz clock

CLKOUTSEL - CLKOUT select 0b000..FlexBus CLKOUT 0b001..Reserved 0b010..Flash clock 0b011..LPO clock (1 kHz) 0b100..MCGIRCLK 0b101..OSCERCLK_UNDIV 0b110..OSCERCLK 0b111..Reserved

◆ SIM_SOPT2_CLKOUTSEL [2/5]

#define SIM_SOPT2_CLKOUTSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)

CLKOUTSEL - CLKOUT select 0b000..FlexBus CLKOUT 0b001..Reserved 0b010..Flash clock 0b011..LPO clock (1 kHz) 0b100..MCGIRCLK 0b101..RTC 32.768kHz clock 0b110..OSCERCLK0 0b111..IRC 48 MHz clock

CLKOUTSEL - CLKOUT select 0b000..FlexBus CLKOUT 0b001..Reserved 0b010..Flash clock 0b011..LPO clock (1 kHz) 0b100..MCGIRCLK 0b101..OSCERCLK_UNDIV 0b110..OSCERCLK 0b111..Reserved

◆ SIM_SOPT2_CLKOUTSEL [3/5]

#define SIM_SOPT2_CLKOUTSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)

CLKOUTSEL - CLKOUT select 0b000..FlexBus CLKOUT 0b001..Reserved 0b010..Flash clock 0b011..LPO clock (1 kHz) 0b100..MCGIRCLK 0b101..RTC 32.768kHz clock 0b110..OSCERCLK0 0b111..IRC 48 MHz clock

CLKOUTSEL - CLKOUT select 0b000..FlexBus CLKOUT 0b001..Reserved 0b010..Flash clock 0b011..LPO clock (1 kHz) 0b100..MCGIRCLK 0b101..OSCERCLK_UNDIV 0b110..OSCERCLK 0b111..Reserved

◆ SIM_SOPT2_CLKOUTSEL [4/5]

#define SIM_SOPT2_CLKOUTSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)

CLKOUTSEL - CLKOUT select 0b000..FlexBus CLKOUT 0b001..Reserved 0b010..Flash clock 0b011..LPO clock (1 kHz) 0b100..MCGIRCLK 0b101..RTC 32.768kHz clock 0b110..OSCERCLK0 0b111..IRC 48 MHz clock

CLKOUTSEL - CLKOUT select 0b000..FlexBus CLKOUT 0b001..Reserved 0b010..Flash clock 0b011..LPO clock (1 kHz) 0b100..MCGIRCLK 0b101..OSCERCLK_UNDIV 0b110..OSCERCLK 0b111..Reserved

◆ SIM_SOPT2_CLKOUTSEL [5/5]

#define SIM_SOPT2_CLKOUTSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)

CLKOUTSEL - CLKOUT select 0b000..FlexBus CLKOUT 0b001..Reserved 0b010..Flash clock 0b011..LPO clock (1 kHz) 0b100..MCGIRCLK 0b101..OSCERCLK_UNDIV 0b110..OSCERCLK 0b111..Reserved

◆ SIM_SOPT2_FBSL [1/6]

#define SIM_SOPT2_FBSL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

◆ SIM_SOPT2_FBSL [2/6]

#define SIM_SOPT2_FBSL ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

◆ SIM_SOPT2_FBSL [3/6]

#define SIM_SOPT2_FBSL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

◆ SIM_SOPT2_FBSL [4/6]

#define SIM_SOPT2_FBSL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

◆ SIM_SOPT2_FBSL [5/6]

#define SIM_SOPT2_FBSL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

◆ SIM_SOPT2_FBSL [6/6]

#define SIM_SOPT2_FBSL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)

FBSL - FlexBus security level 0b00..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b01..All off-chip accesses (instruction and data) via the FlexBus are disallowed. 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed. 0b11..Off-chip instruction accesses and data accesses are allowed.

◆ SIM_SOPT2_LPUARTSRC [1/2]

#define SIM_SOPT2_LPUARTSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)

LPUARTSRC - LPUART clock source select 0b00..Clock disabled 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. 0b10..OSCERCLK clock 0b11..MCGIRCLK clock

◆ SIM_SOPT2_LPUARTSRC [2/2]

#define SIM_SOPT2_LPUARTSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)

LPUARTSRC - LPUART clock source select 0b00..Clock disabled 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. 0b10..OSCERCLK clock 0b11..MCGIRCLK clock

◆ SIM_SOPT2_PLLFLLSEL [1/5]

#define SIM_SOPT2_PLLFLLSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..Reserved 0b11..IRC48 MHz clock

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..USB1 PFD clock 0b11..IRC48 MHz clock

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..Reserved 0b11..Reserved

◆ SIM_SOPT2_PLLFLLSEL [2/5]

#define SIM_SOPT2_PLLFLLSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..Reserved 0b11..IRC48 MHz clock

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..USB1 PFD clock 0b11..IRC48 MHz clock

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..Reserved 0b11..Reserved

◆ SIM_SOPT2_PLLFLLSEL [3/5]

#define SIM_SOPT2_PLLFLLSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..USB1 PFD clock 0b11..IRC48 MHz clock

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..Reserved 0b11..Reserved

◆ SIM_SOPT2_PLLFLLSEL [4/5]

#define SIM_SOPT2_PLLFLLSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..USB1 PFD clock 0b11..IRC48 MHz clock

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..Reserved 0b11..Reserved

◆ SIM_SOPT2_PLLFLLSEL [5/5]

#define SIM_SOPT2_PLLFLLSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)

PLLFLLSEL - PLL/FLL clock select 0b00..MCGFLLCLK clock 0b01..MCGPLLCLK clock 0b10..Reserved 0b11..Reserved

◆ SIM_SOPT2_PTD7PAD [1/2]

#define SIM_SOPT2_PTD7PAD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)

PTD7PAD - PTD7 pad drive strength 0b0..Single-pad drive strength for PTD7. 0b1..Double pad drive strength for PTD7.

◆ SIM_SOPT2_PTD7PAD [2/2]

#define SIM_SOPT2_PTD7PAD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)

PTD7PAD - PTD7 pad drive strength 0b0..Single-pad drive strength for PTD7. 0b1..Double pad drive strength for PTD7.

◆ SIM_SOPT2_RMIISRC [1/5]

#define SIM_SOPT2_RMIISRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)

RMIISRC - RMII clock source select 0b0..EXTAL clock 0b1..External bypass clock (ENET_1588_CLKIN).

◆ SIM_SOPT2_RMIISRC [2/5]

#define SIM_SOPT2_RMIISRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)

RMIISRC - RMII clock source select 0b0..EXTAL clock 0b1..External bypass clock (ENET_1588_CLKIN).

◆ SIM_SOPT2_RMIISRC [3/5]

#define SIM_SOPT2_RMIISRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)

RMIISRC - RMII clock source select 0b0..EXTAL clock 0b1..External bypass clock (ENET_1588_CLKIN).

◆ SIM_SOPT2_RMIISRC [4/5]

#define SIM_SOPT2_RMIISRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)

RMIISRC - RMII clock source select 0b0..EXTAL clock 0b1..External bypass clock (ENET_1588_CLKIN).

◆ SIM_SOPT2_RMIISRC [5/5]

#define SIM_SOPT2_RMIISRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)

RMIISRC - RMII clock source select 0b0..EXTAL clock 0b1..External bypass clock (ENET_1588_CLKIN).

◆ SIM_SOPT2_RTCCLKOUTSEL [1/4]

#define SIM_SOPT2_RTCCLKOUTSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)

RTCCLKOUTSEL - RTC clock out select 0b0..RTC 1 Hz clock is output on the RTC_CLKOUT pin. 0b1..RTC 32.768kHz clock is output on the RTC_CLKOUT pin.

◆ SIM_SOPT2_RTCCLKOUTSEL [2/4]

#define SIM_SOPT2_RTCCLKOUTSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)

RTCCLKOUTSEL - RTC clock out select 0b0..RTC 1 Hz clock is output on the RTC_CLKOUT pin. 0b1..RTC 32.768kHz clock is output on the RTC_CLKOUT pin.

◆ SIM_SOPT2_RTCCLKOUTSEL [3/4]

#define SIM_SOPT2_RTCCLKOUTSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)

RTCCLKOUTSEL - RTC clock out select 0b0..RTC 1 Hz clock is output on the RTC_CLKOUT pin. 0b1..RTC 32.768kHz clock is output on the RTC_CLKOUT pin.

◆ SIM_SOPT2_RTCCLKOUTSEL [4/4]

#define SIM_SOPT2_RTCCLKOUTSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)

RTCCLKOUTSEL - RTC clock out select 0b0..RTC 1 Hz clock is output on the RTC_CLKOUT pin. 0b1..RTC 32.768kHz clock is output on the RTC_CLKOUT pin.

◆ SIM_SOPT2_SDHCSRC [1/5]

#define SIM_SOPT2_SDHCSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)

SDHCSRC - SDHC clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (SDHC0_CLKIN)

SDHCSRC - SDHC clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (SDHC0_CLKIN)

◆ SIM_SOPT2_SDHCSRC [2/5]

#define SIM_SOPT2_SDHCSRC ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)

SDHCSRC - SDHC clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (SDHC0_CLKIN)

SDHCSRC - SDHC clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (SDHC0_CLKIN)

◆ SIM_SOPT2_SDHCSRC [3/5]

#define SIM_SOPT2_SDHCSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)

SDHCSRC - SDHC clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (SDHC0_CLKIN)

SDHCSRC - SDHC clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (SDHC0_CLKIN)

◆ SIM_SOPT2_SDHCSRC [4/5]

#define SIM_SOPT2_SDHCSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)

SDHCSRC - SDHC clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (SDHC0_CLKIN)

◆ SIM_SOPT2_SDHCSRC [5/5]

#define SIM_SOPT2_SDHCSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)

SDHCSRC - SDHC clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (SDHC0_CLKIN)

◆ SIM_SOPT2_TIMESRC [1/6]

#define SIM_SOPT2_TIMESRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN).

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN).

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock 0b01..MCGFLLCLK , or MCGPLLCLK as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN)

◆ SIM_SOPT2_TIMESRC [2/6]

#define SIM_SOPT2_TIMESRC ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN).

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN).

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock 0b01..MCGFLLCLK , or MCGPLLCLK as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN)

◆ SIM_SOPT2_TIMESRC [3/6]

#define SIM_SOPT2_TIMESRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN).

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN).

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock 0b01..MCGFLLCLK , or MCGPLLCLK as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN)

◆ SIM_SOPT2_TIMESRC [4/6]

#define SIM_SOPT2_TIMESRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN).

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock 0b01..MCGFLLCLK , or MCGPLLCLK as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN)

◆ SIM_SOPT2_TIMESRC [5/6]

#define SIM_SOPT2_TIMESRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock. 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN).

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock 0b01..MCGFLLCLK , or MCGPLLCLK as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN)

◆ SIM_SOPT2_TIMESRC [6/6]

#define SIM_SOPT2_TIMESRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)

TIMESRC - IEEE 1588 timestamp clock source select 0b00..Core/system clock 0b01..MCGFLLCLK , or MCGPLLCLK as selected by SOPT2[PLLFLLSEL]. 0b10..OSCERCLK clock 0b11..External bypass clock (ENET_1588_CLKIN)

◆ SIM_SOPT2_TPMSRC [1/2]

#define SIM_SOPT2_TPMSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)

TPMSRC - TPM clock source select 0b00..Clock disabled 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. 0b10..OSCERCLK clock 0b11..MCGIRCLK clock

◆ SIM_SOPT2_TPMSRC [2/2]

#define SIM_SOPT2_TPMSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)

TPMSRC - TPM clock source select 0b00..Clock disabled 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV]. 0b10..OSCERCLK clock 0b11..MCGIRCLK clock

◆ SIM_SOPT2_TRACECLKSEL [1/5]

#define SIM_SOPT2_TRACECLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)

TRACECLKSEL - Debug trace clock select 0b0..MCGOUTCLK 0b1..Core/system clock

TRACECLKSEL - Debug trace clock select 0b0..MCGOUTCLK, divided by the TRACECLK fractional divider as configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV] 0b1..Core/system clock

◆ SIM_SOPT2_TRACECLKSEL [2/5]

#define SIM_SOPT2_TRACECLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)

TRACECLKSEL - Debug trace clock select 0b0..MCGOUTCLK 0b1..Core/system clock

TRACECLKSEL - Debug trace clock select 0b0..MCGOUTCLK, divided by the TRACECLK fractional divider as configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV] 0b1..Core/system clock

◆ SIM_SOPT2_TRACECLKSEL [3/5]

#define SIM_SOPT2_TRACECLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)

TRACECLKSEL - Debug trace clock select 0b0..MCGOUTCLK, divided by the TRACECLK fractional divider as configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV] 0b1..Core/system clock

TRACECLKSEL - Debug trace clock select 0b0..MCGOUTCLK 0b1..Core/system clock

◆ SIM_SOPT2_TRACECLKSEL [4/5]

#define SIM_SOPT2_TRACECLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)

TRACECLKSEL - Debug trace clock select 0b0..MCGOUTCLK, divided by the TRACECLK fractional divider as configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV] 0b1..Core/system clock

TRACECLKSEL - Debug trace clock select 0b0..MCGOUTCLK 0b1..Core/system clock

◆ SIM_SOPT2_TRACECLKSEL [5/5]

#define SIM_SOPT2_TRACECLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)

TRACECLKSEL - Debug trace clock select 0b0..MCGOUTCLK 0b1..Core/system clock

◆ SIM_SOPT2_USBREGEN [1/2]

#define SIM_SOPT2_USBREGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)

USBREGEN - USB PHY PLL Regulator Enable 0b0..USB PHY PLL Regulator disabled. 0b1..USB PHY PLL Regulator enabled.

◆ SIM_SOPT2_USBREGEN [2/2]

#define SIM_SOPT2_USBREGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)

USBREGEN - USB PHY PLL Regulator Enable 0b0..USB PHY PLL Regulator disabled. 0b1..USB PHY PLL Regulator enabled.

◆ SIM_SOPT2_USBSLSRC [1/2]

#define SIM_SOPT2_USBSLSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)

USBSLSRC - USB Slow Clock Source 0b0..MCGIRCLK 0b1..RTC 32.768kHz clock

◆ SIM_SOPT2_USBSLSRC [2/2]

#define SIM_SOPT2_USBSLSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)

USBSLSRC - USB Slow Clock Source 0b0..MCGIRCLK 0b1..RTC 32.768kHz clock

◆ SIM_SOPT2_USBSRC [1/4]

#define SIM_SOPT2_USBSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)

USBSRC - USB clock source select 0b0..External bypass clock (USB_CLKIN). 0b1..MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].

USBSRC - USB clock source select 0b0..External bypass clock (USB_CLKIN). 0b1..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].

◆ SIM_SOPT2_USBSRC [2/4]

#define SIM_SOPT2_USBSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)

USBSRC - USB clock source select 0b0..External bypass clock (USB_CLKIN). 0b1..MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].

USBSRC - USB clock source select 0b0..External bypass clock (USB_CLKIN). 0b1..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].

◆ SIM_SOPT2_USBSRC [3/4]

#define SIM_SOPT2_USBSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)

USBSRC - USB clock source select 0b0..External bypass clock (USB_CLKIN). 0b1..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].

◆ SIM_SOPT2_USBSRC [4/4]

#define SIM_SOPT2_USBSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)

USBSRC - USB clock source select 0b0..External bypass clock (USB_CLKIN). 0b1..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].

◆ SIM_SOPT4_FTM0CLKSEL [1/4]

#define SIM_SOPT4_FTM0CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)

FTM0CLKSEL - FlexTimer 0 External Clock Pin Select 0b0..FTM_CLK0 pin 0b1..FTM_CLK1 pin

◆ SIM_SOPT4_FTM0CLKSEL [2/4]

#define SIM_SOPT4_FTM0CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)

FTM0CLKSEL - FlexTimer 0 External Clock Pin Select 0b0..FTM_CLK0 pin 0b1..FTM_CLK1 pin

◆ SIM_SOPT4_FTM0CLKSEL [3/4]

#define SIM_SOPT4_FTM0CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)

FTM0CLKSEL - FlexTimer 0 External Clock Pin Select 0b0..FTM_CLK0 pin 0b1..FTM_CLK1 pin

◆ SIM_SOPT4_FTM0CLKSEL [4/4]

#define SIM_SOPT4_FTM0CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)

FTM0CLKSEL - FlexTimer 0 External Clock Pin Select 0b0..FTM_CLK0 pin 0b1..FTM_CLK1 pin

◆ SIM_SOPT4_FTM0FLT0 [1/5]

#define SIM_SOPT4_FTM0FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)

FTM0FLT0 - FTM0 Fault 0 Select 0b0..FTM0_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM0FLT0 [2/5]

#define SIM_SOPT4_FTM0FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)

FTM0FLT0 - FTM0 Fault 0 Select 0b0..FTM0_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM0FLT0 [3/5]

#define SIM_SOPT4_FTM0FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)

FTM0FLT0 - FTM0 Fault 0 Select 0b0..FTM0_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM0FLT0 [4/5]

#define SIM_SOPT4_FTM0FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)

FTM0FLT0 - FTM0 Fault 0 Select 0b0..FTM0_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM0FLT0 [5/5]

#define SIM_SOPT4_FTM0FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)

FTM0FLT0 - FTM0 Fault 0 Select 0b0..FTM0_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM0FLT1 [1/5]

#define SIM_SOPT4_FTM0FLT1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)

FTM0FLT1 - FTM0 Fault 1 Select 0b0..FTM0_FLT1 pin 0b1..CMP1 out

◆ SIM_SOPT4_FTM0FLT1 [2/5]

#define SIM_SOPT4_FTM0FLT1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)

FTM0FLT1 - FTM0 Fault 1 Select 0b0..FTM0_FLT1 pin 0b1..CMP1 out

◆ SIM_SOPT4_FTM0FLT1 [3/5]

#define SIM_SOPT4_FTM0FLT1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)

FTM0FLT1 - FTM0 Fault 1 Select 0b0..FTM0_FLT1 pin 0b1..CMP1 out

◆ SIM_SOPT4_FTM0FLT1 [4/5]

#define SIM_SOPT4_FTM0FLT1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)

FTM0FLT1 - FTM0 Fault 1 Select 0b0..FTM0_FLT1 pin 0b1..CMP1 out

◆ SIM_SOPT4_FTM0FLT1 [5/5]

#define SIM_SOPT4_FTM0FLT1 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)

FTM0FLT1 - FTM0 Fault 1 Select 0b0..FTM0_FLT1 pin 0b1..CMP1 out

◆ SIM_SOPT4_FTM0FLT2 [1/5]

#define SIM_SOPT4_FTM0FLT2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)

FTM0FLT2 - FTM0 Fault 2 Select 0b0..FTM0_FLT2 pin 0b1..CMP2 out

◆ SIM_SOPT4_FTM0FLT2 [2/5]

#define SIM_SOPT4_FTM0FLT2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)

FTM0FLT2 - FTM0 Fault 2 Select 0b0..FTM0_FLT2 pin 0b1..CMP2 out

◆ SIM_SOPT4_FTM0FLT2 [3/5]

#define SIM_SOPT4_FTM0FLT2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)

FTM0FLT2 - FTM0 Fault 2 Select 0b0..FTM0_FLT2 pin 0b1..CMP2 out

◆ SIM_SOPT4_FTM0FLT2 [4/5]

#define SIM_SOPT4_FTM0FLT2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)

FTM0FLT2 - FTM0 Fault 2 Select 0b0..FTM0_FLT2 pin 0b1..CMP2 out

◆ SIM_SOPT4_FTM0FLT2 [5/5]

#define SIM_SOPT4_FTM0FLT2 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)

FTM0FLT2 - FTM0 Fault 2 Select 0b0..FTM0_FLT2 pin 0b1..CMP2 out

◆ SIM_SOPT4_FTM0FLT3 [1/3]

#define SIM_SOPT4_FTM0FLT3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)

FTM0FLT3 - FTM0 Fault 3 Select 0b0..FTM0_FLT3 pin 0b1..CMP3 out

FTM0FLT3 0b0..FTM0_FLT3 pin 0b1..XBARA output 49

◆ SIM_SOPT4_FTM0FLT3 [2/3]

#define SIM_SOPT4_FTM0FLT3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)

FTM0FLT3 - FTM0 Fault 3 Select 0b0..FTM0_FLT3 pin 0b1..CMP3 out

FTM0FLT3 0b0..FTM0_FLT3 pin 0b1..XBARA output 49

◆ SIM_SOPT4_FTM0FLT3 [3/3]

#define SIM_SOPT4_FTM0FLT3 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)

FTM0FLT3 0b0..FTM0_FLT3 pin 0b1..XBARA output 49

◆ SIM_SOPT4_FTM0TRG0SRC [1/5]

#define SIM_SOPT4_FTM0TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)

FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select 0b0..HSCMP0 output drives FTM0 hardware trigger 0 0b1..FTM1 channel match drives FTM0 hardware trigger 0

FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM0 hardware trigger 0 0b1..FTM1 channel match drives FTM0 hardware trigger 0

◆ SIM_SOPT4_FTM0TRG0SRC [2/5]

#define SIM_SOPT4_FTM0TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)

FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select 0b0..HSCMP0 output drives FTM0 hardware trigger 0 0b1..FTM1 channel match drives FTM0 hardware trigger 0

FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM0 hardware trigger 0 0b1..FTM1 channel match drives FTM0 hardware trigger 0

◆ SIM_SOPT4_FTM0TRG0SRC [3/5]

#define SIM_SOPT4_FTM0TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)

FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select 0b0..HSCMP0 output drives FTM0 hardware trigger 0 0b1..FTM1 channel match drives FTM0 hardware trigger 0

FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM0 hardware trigger 0 0b1..FTM1 channel match drives FTM0 hardware trigger 0

◆ SIM_SOPT4_FTM0TRG0SRC [4/5]

#define SIM_SOPT4_FTM0TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)

FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select 0b0..HSCMP0 output drives FTM0 hardware trigger 0 0b1..FTM1 channel match drives FTM0 hardware trigger 0

FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM0 hardware trigger 0 0b1..FTM1 channel match drives FTM0 hardware trigger 0

◆ SIM_SOPT4_FTM0TRG0SRC [5/5]

#define SIM_SOPT4_FTM0TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)

FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM0 hardware trigger 0 0b1..FTM1 channel match drives FTM0 hardware trigger 0

◆ SIM_SOPT4_FTM0TRG1SRC [1/5]

#define SIM_SOPT4_FTM0TRG1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)

FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select 0b0..PDB output trigger 1 drives FTM0 hardware trigger 1 0b1..FTM2 channel match drives FTM0 hardware trigger 1

FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select 0b0..PDB0 channel 1 output trigger drives FTM0 hardware trigger 1 0b1..FTM1 channel match drives FTM0 hardware trigger 1

◆ SIM_SOPT4_FTM0TRG1SRC [2/5]

#define SIM_SOPT4_FTM0TRG1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)

FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select 0b0..PDB output trigger 1 drives FTM0 hardware trigger 1 0b1..FTM2 channel match drives FTM0 hardware trigger 1

FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select 0b0..PDB0 channel 1 output trigger drives FTM0 hardware trigger 1 0b1..FTM1 channel match drives FTM0 hardware trigger 1

◆ SIM_SOPT4_FTM0TRG1SRC [3/5]

#define SIM_SOPT4_FTM0TRG1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)

FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select 0b0..PDB output trigger 1 drives FTM0 hardware trigger 1 0b1..FTM2 channel match drives FTM0 hardware trigger 1

FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select 0b0..PDB0 channel 1 output trigger drives FTM0 hardware trigger 1 0b1..FTM1 channel match drives FTM0 hardware trigger 1

◆ SIM_SOPT4_FTM0TRG1SRC [4/5]

#define SIM_SOPT4_FTM0TRG1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)

FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select 0b0..PDB output trigger 1 drives FTM0 hardware trigger 1 0b1..FTM2 channel match drives FTM0 hardware trigger 1

FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select 0b0..PDB0 channel 1 output trigger drives FTM0 hardware trigger 1 0b1..FTM1 channel match drives FTM0 hardware trigger 1

◆ SIM_SOPT4_FTM0TRG1SRC [5/5]

#define SIM_SOPT4_FTM0TRG1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)

FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select 0b0..PDB0 channel 1 output trigger drives FTM0 hardware trigger 1 0b1..FTM1 channel match drives FTM0 hardware trigger 1

◆ SIM_SOPT4_FTM0TRG2SRC

#define SIM_SOPT4_FTM0TRG2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG2SRC_SHIFT)) & SIM_SOPT4_FTM0TRG2SRC_MASK)

FTM0TRG2SRC - FlexTimer 0 Hardware Trigger 2 Source Select 0b0..FTM0_FLT0 pin drives FTM0 hardware trigger 2 0b1..XBARA output 34 drives FTM0 hardware trigger 2

◆ SIM_SOPT4_FTM1CH0SRC [1/5]

#define SIM_SOPT4_FTM1CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)

FTM1CH0SRC - FTM1 channel 0 input capture source select 0b00..FTM1_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..USB start of frame pulse

◆ SIM_SOPT4_FTM1CH0SRC [2/5]

#define SIM_SOPT4_FTM1CH0SRC ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)

FTM1CH0SRC - FTM1 channel 0 input capture source select 0b00..FTM1_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..USB start of frame pulse

◆ SIM_SOPT4_FTM1CH0SRC [3/5]

#define SIM_SOPT4_FTM1CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)

FTM1CH0SRC - FTM1 channel 0 input capture source select 0b00..FTM1_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..USB start of frame pulse

◆ SIM_SOPT4_FTM1CH0SRC [4/5]

#define SIM_SOPT4_FTM1CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)

FTM1CH0SRC - FTM1 channel 0 input capture source select 0b00..FTM1_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..USB start of frame pulse

◆ SIM_SOPT4_FTM1CH0SRC [5/5]

#define SIM_SOPT4_FTM1CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)

FTM1CH0SRC - FTM1 channel 0 input capture source select 0b00..FTM1_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..USB start of frame pulse

◆ SIM_SOPT4_FTM1CLKSEL [1/4]

#define SIM_SOPT4_FTM1CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)

FTM1CLKSEL - FTM1 External Clock Pin Select 0b0..FTM_CLK0 pin 0b1..FTM_CLK1 pin

◆ SIM_SOPT4_FTM1CLKSEL [2/4]

#define SIM_SOPT4_FTM1CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)

FTM1CLKSEL - FTM1 External Clock Pin Select 0b0..FTM_CLK0 pin 0b1..FTM_CLK1 pin

◆ SIM_SOPT4_FTM1CLKSEL [3/4]

#define SIM_SOPT4_FTM1CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)

FTM1CLKSEL - FTM1 External Clock Pin Select 0b0..FTM_CLK0 pin 0b1..FTM_CLK1 pin

◆ SIM_SOPT4_FTM1CLKSEL [4/4]

#define SIM_SOPT4_FTM1CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)

FTM1CLKSEL - FTM1 External Clock Pin Select 0b0..FTM_CLK0 pin 0b1..FTM_CLK1 pin

◆ SIM_SOPT4_FTM1FLT0 [1/5]

#define SIM_SOPT4_FTM1FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)

FTM1FLT0 - FTM1 Fault 0 Select 0b0..FTM1_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM1FLT0 [2/5]

#define SIM_SOPT4_FTM1FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)

FTM1FLT0 - FTM1 Fault 0 Select 0b0..FTM1_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM1FLT0 [3/5]

#define SIM_SOPT4_FTM1FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)

FTM1FLT0 - FTM1 Fault 0 Select 0b0..FTM1_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM1FLT0 [4/5]

#define SIM_SOPT4_FTM1FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)

FTM1FLT0 - FTM1 Fault 0 Select 0b0..FTM1_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM1FLT0 [5/5]

#define SIM_SOPT4_FTM1FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)

FTM1FLT0 - FTM1 Fault 0 Select 0b0..FTM1_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM1TRG0SRC

#define SIM_SOPT4_FTM1TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1TRG0SRC_SHIFT)) & SIM_SOPT4_FTM1TRG0SRC_MASK)

FTM1TRG0SRC - FlexTimer 1 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM1 hardware trigger 0 0b1..FTM0 channel match drives FTM1 hardware trigger 0

◆ SIM_SOPT4_FTM1TRG2SRC

#define SIM_SOPT4_FTM1TRG2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1TRG2SRC_SHIFT)) & SIM_SOPT4_FTM1TRG2SRC_MASK)

FTM1TRG2SRC - FlexTimer 1 Hardware Trigger 2 Source Select 0b0..FTM1_FLT0 pin drives FTM1 hardware trigger 2 0b1..XBARA output 35 drives FTM1 hardware trigger 2

◆ SIM_SOPT4_FTM2CH0SRC [1/5]

#define SIM_SOPT4_FTM2CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)

FTM2CH0SRC - FTM2 channel 0 input capture source select 0b00..FTM2_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT4_FTM2CH0SRC [2/5]

#define SIM_SOPT4_FTM2CH0SRC ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)

FTM2CH0SRC - FTM2 channel 0 input capture source select 0b00..FTM2_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT4_FTM2CH0SRC [3/5]

#define SIM_SOPT4_FTM2CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)

FTM2CH0SRC - FTM2 channel 0 input capture source select 0b00..FTM2_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT4_FTM2CH0SRC [4/5]

#define SIM_SOPT4_FTM2CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)

FTM2CH0SRC - FTM2 channel 0 input capture source select 0b00..FTM2_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT4_FTM2CH0SRC [5/5]

#define SIM_SOPT4_FTM2CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)

FTM2CH0SRC - FTM2 channel 0 input capture source select 0b00..FTM2_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT4_FTM2CH1SRC [1/2]

#define SIM_SOPT4_FTM2CH1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)

FTM2CH1SRC - FTM2 channel 1 input capture source select 0b0..FTM2_CH1 signal 0b1..Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.

◆ SIM_SOPT4_FTM2CH1SRC [2/2]

#define SIM_SOPT4_FTM2CH1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)

FTM2CH1SRC - FTM2 channel 1 input capture source select 0b0..FTM2_CH1 signal 0b1..Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.

◆ SIM_SOPT4_FTM2CLKSEL [1/4]

#define SIM_SOPT4_FTM2CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)

FTM2CLKSEL - FlexTimer 2 External Clock Pin Select 0b0..FTM2 external clock driven by FTM_CLK0 pin. 0b1..FTM2 external clock driven by FTM_CLK1 pin.

◆ SIM_SOPT4_FTM2CLKSEL [2/4]

#define SIM_SOPT4_FTM2CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)

FTM2CLKSEL - FlexTimer 2 External Clock Pin Select 0b0..FTM2 external clock driven by FTM_CLK0 pin. 0b1..FTM2 external clock driven by FTM_CLK1 pin.

◆ SIM_SOPT4_FTM2CLKSEL [3/4]

#define SIM_SOPT4_FTM2CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)

FTM2CLKSEL - FlexTimer 2 External Clock Pin Select 0b0..FTM2 external clock driven by FTM_CLK0 pin. 0b1..FTM2 external clock driven by FTM_CLK1 pin.

◆ SIM_SOPT4_FTM2CLKSEL [4/4]

#define SIM_SOPT4_FTM2CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)

FTM2CLKSEL - FlexTimer 2 External Clock Pin Select 0b0..FTM2 external clock driven by FTM_CLK0 pin. 0b1..FTM2 external clock driven by FTM_CLK1 pin.

◆ SIM_SOPT4_FTM2FLT0 [1/5]

#define SIM_SOPT4_FTM2FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)

FTM2FLT0 - FTM2 Fault 0 Select 0b0..FTM2_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM2FLT0 [2/5]

#define SIM_SOPT4_FTM2FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)

FTM2FLT0 - FTM2 Fault 0 Select 0b0..FTM2_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM2FLT0 [3/5]

#define SIM_SOPT4_FTM2FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)

FTM2FLT0 - FTM2 Fault 0 Select 0b0..FTM2_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM2FLT0 [4/5]

#define SIM_SOPT4_FTM2FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)

FTM2FLT0 - FTM2 Fault 0 Select 0b0..FTM2_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM2FLT0 [5/5]

#define SIM_SOPT4_FTM2FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)

FTM2FLT0 - FTM2 Fault 0 Select 0b0..FTM2_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM2TRG0SRC

#define SIM_SOPT4_FTM2TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2TRG0SRC_SHIFT)) & SIM_SOPT4_FTM2TRG0SRC_MASK)

FTM2TRG0SRC - FlexTimer 2 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM2 hardware trigger 0 0b1..FTM0 channel match drives FTM2 hardware trigger 0

◆ SIM_SOPT4_FTM2TRG2SRC

#define SIM_SOPT4_FTM2TRG2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2TRG2SRC_SHIFT)) & SIM_SOPT4_FTM2TRG2SRC_MASK)

FTM2TRG2SRC - FlexTimer 2 Hardware Trigger 2 Source Select 0b0..FTM2_FLT0 pin drives FTM2 hardware trigger 2 0b1..XBARA output 36 drives FTM2 hardware trigger 2

◆ SIM_SOPT4_FTM3CLKSEL [1/3]

#define SIM_SOPT4_FTM3CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)

FTM3CLKSEL - FlexTimer 3 External Clock Pin Select 0b0..FTM3 external clock driven by FTM_CLK0 pin. 0b1..FTM3 external clock driven by FTM_CLK1 pin.

◆ SIM_SOPT4_FTM3CLKSEL [2/3]

#define SIM_SOPT4_FTM3CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)

FTM3CLKSEL - FlexTimer 3 External Clock Pin Select 0b0..FTM3 external clock driven by FTM_CLK0 pin. 0b1..FTM3 external clock driven by FTM_CLK1 pin.

◆ SIM_SOPT4_FTM3CLKSEL [3/3]

#define SIM_SOPT4_FTM3CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)

FTM3CLKSEL - FlexTimer 3 External Clock Pin Select 0b0..FTM3 external clock driven by FTM_CLK0 pin. 0b1..FTM3 external clock driven by FTM_CLK1 pin.

◆ SIM_SOPT4_FTM3FLT0 [1/4]

#define SIM_SOPT4_FTM3FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)

FTM3FLT0 - FTM3 Fault 0 Select 0b0..FTM3_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM3FLT0 [2/4]

#define SIM_SOPT4_FTM3FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)

FTM3FLT0 - FTM3 Fault 0 Select 0b0..FTM3_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM3FLT0 [3/4]

#define SIM_SOPT4_FTM3FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)

FTM3FLT0 - FTM3 Fault 0 Select 0b0..FTM3_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM3FLT0 [4/4]

#define SIM_SOPT4_FTM3FLT0 ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)

FTM3FLT0 - FTM3 Fault 0 Select 0b0..FTM3_FLT0 pin 0b1..CMP0 out

◆ SIM_SOPT4_FTM3TRG0SRC [1/4]

#define SIM_SOPT4_FTM3TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)

FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select 0b0..Reserved 0b1..FTM1 channel match drives FTM3 hardware trigger 0

FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM3 hardware trigger 0 0b1..FTM1 channel match drives FTM3 hardware trigger 0

◆ SIM_SOPT4_FTM3TRG0SRC [2/4]

#define SIM_SOPT4_FTM3TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)

FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select 0b0..Reserved 0b1..FTM1 channel match drives FTM3 hardware trigger 0

FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM3 hardware trigger 0 0b1..FTM1 channel match drives FTM3 hardware trigger 0

◆ SIM_SOPT4_FTM3TRG0SRC [3/4]

#define SIM_SOPT4_FTM3TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)

FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select 0b0..Reserved 0b1..FTM1 channel match drives FTM3 hardware trigger 0

FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM3 hardware trigger 0 0b1..FTM1 channel match drives FTM3 hardware trigger 0

◆ SIM_SOPT4_FTM3TRG0SRC [4/4]

#define SIM_SOPT4_FTM3TRG0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)

FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select 0b0..CMP0 output drives FTM3 hardware trigger 0 0b1..FTM1 channel match drives FTM3 hardware trigger 0

◆ SIM_SOPT4_FTM3TRG1SRC [1/4]

#define SIM_SOPT4_FTM3TRG1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)

FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select 0b0..Reserved 0b1..FTM2 channel match drives FTM3 hardware trigger 1

FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select 0b0..PDB1 channel 1 output trigger drives FTM3 hardware trigger 1 0b1..FTM1 channel match drives FTM3 hardware trigger 1

◆ SIM_SOPT4_FTM3TRG1SRC [2/4]

#define SIM_SOPT4_FTM3TRG1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)

FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select 0b0..Reserved 0b1..FTM2 channel match drives FTM3 hardware trigger 1

FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select 0b0..PDB1 channel 1 output trigger drives FTM3 hardware trigger 1 0b1..FTM1 channel match drives FTM3 hardware trigger 1

◆ SIM_SOPT4_FTM3TRG1SRC [3/4]

#define SIM_SOPT4_FTM3TRG1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)

FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select 0b0..Reserved 0b1..FTM2 channel match drives FTM3 hardware trigger 1

FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select 0b0..PDB1 channel 1 output trigger drives FTM3 hardware trigger 1 0b1..FTM1 channel match drives FTM3 hardware trigger 1

◆ SIM_SOPT4_FTM3TRG1SRC [4/4]

#define SIM_SOPT4_FTM3TRG1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)

FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select 0b0..PDB1 channel 1 output trigger drives FTM3 hardware trigger 1 0b1..FTM1 channel match drives FTM3 hardware trigger 1

◆ SIM_SOPT4_FTM3TRG2SRC

#define SIM_SOPT4_FTM3TRG2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG2SRC_SHIFT)) & SIM_SOPT4_FTM3TRG2SRC_MASK)

FTM3TRG2SRC - FlexTimer 3 Hardware Trigger 2 Source Select 0b0..FTM3_FLT0 pin drives FTM3 hardware trigger 2 0b1..XBARA output 37 drives FTM3 hardware trigger 2

◆ SIM_SOPT5_LPUART0RXSRC [1/2]

#define SIM_SOPT5_LPUART0RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)

LPUART0RXSRC - LPUART0 receive data source select 0b00..LPUART0_RX pin 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT5_LPUART0RXSRC [2/2]

#define SIM_SOPT5_LPUART0RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)

LPUART0RXSRC - LPUART0 receive data source select 0b00..LPUART0_RX pin 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT5_LPUART0TXSRC [1/2]

#define SIM_SOPT5_LPUART0TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)

LPUART0TXSRC - LPUART0 transmit data source select 0b00..LPUART0_TX pin 0b01..LPUART0_TX pin modulated with TPM1 channel 0 output 0b10..LPUART0_TX pin modulated with TPM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_LPUART0TXSRC [2/2]

#define SIM_SOPT5_LPUART0TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)

LPUART0TXSRC - LPUART0 transmit data source select 0b00..LPUART0_TX pin 0b01..LPUART0_TX pin modulated with TPM1 channel 0 output 0b10..LPUART0_TX pin modulated with TPM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART0RXSRC [1/6]

#define SIM_SOPT5_UART0RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)

UART0RXSRC - UART 0 receive data source select 0b00..UART0_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART0RXSRC [2/6]

#define SIM_SOPT5_UART0RXSRC ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)

UART0RXSRC - UART 0 receive data source select 0b00..UART0_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART0RXSRC [3/6]

#define SIM_SOPT5_UART0RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)

UART0RXSRC - UART 0 receive data source select 0b00..UART0_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART0RXSRC [4/6]

#define SIM_SOPT5_UART0RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)

UART0RXSRC - UART 0 receive data source select 0b00..UART0_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART0RXSRC [5/6]

#define SIM_SOPT5_UART0RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)

UART0RXSRC - UART 0 receive data source select 0b00..UART0_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART0RXSRC [6/6]

#define SIM_SOPT5_UART0RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)

UART0RXSRC - UART 0 receive data source select 0b00..UART0_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART0TXSRC [1/6]

#define SIM_SOPT5_UART0TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)

UART0TXSRC - UART 0 transmit data source select 0b00..UART0_TX pin 0b01..UART0_TX pin modulated with FTM1 channel 0 output 0b10..UART0_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART0TXSRC [2/6]

#define SIM_SOPT5_UART0TXSRC ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)

UART0TXSRC - UART 0 transmit data source select 0b00..UART0_TX pin 0b01..UART0_TX pin modulated with FTM1 channel 0 output 0b10..UART0_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART0TXSRC [3/6]

#define SIM_SOPT5_UART0TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)

UART0TXSRC - UART 0 transmit data source select 0b00..UART0_TX pin 0b01..UART0_TX pin modulated with FTM1 channel 0 output 0b10..UART0_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART0TXSRC [4/6]

#define SIM_SOPT5_UART0TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)

UART0TXSRC - UART 0 transmit data source select 0b00..UART0_TX pin 0b01..UART0_TX pin modulated with FTM1 channel 0 output 0b10..UART0_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART0TXSRC [5/6]

#define SIM_SOPT5_UART0TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)

UART0TXSRC - UART 0 transmit data source select 0b00..UART0_TX pin 0b01..UART0_TX pin modulated with FTM1 channel 0 output 0b10..UART0_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART0TXSRC [6/6]

#define SIM_SOPT5_UART0TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)

UART0TXSRC - UART 0 transmit data source select 0b00..UART0_TX pin 0b01..UART0_TX pin modulated with FTM1 channel 0 output 0b10..UART0_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART1RXSRC [1/6]

#define SIM_SOPT5_UART1RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)

UART1RXSRC - UART 1 receive data source select 0b00..UART1_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART1RXSRC [2/6]

#define SIM_SOPT5_UART1RXSRC ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)

UART1RXSRC - UART 1 receive data source select 0b00..UART1_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART1RXSRC [3/6]

#define SIM_SOPT5_UART1RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)

UART1RXSRC - UART 1 receive data source select 0b00..UART1_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART1RXSRC [4/6]

#define SIM_SOPT5_UART1RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)

UART1RXSRC - UART 1 receive data source select 0b00..UART1_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART1RXSRC [5/6]

#define SIM_SOPT5_UART1RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)

UART1RXSRC - UART 1 receive data source select 0b00..UART1_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART1RXSRC [6/6]

#define SIM_SOPT5_UART1RXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)

UART1RXSRC - UART 1 receive data source select 0b00..UART1_RX pin 0b01..CMP0 0b10..CMP1 0b11..Reserved

◆ SIM_SOPT5_UART1TXSRC [1/5]

#define SIM_SOPT5_UART1TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)

UART1TXSRC - UART 1 transmit data source select 0b00..UART1_TX pin 0b01..UART1_TX pin modulated with FTM1 channel 0 output 0b10..UART1_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART1TXSRC [2/5]

#define SIM_SOPT5_UART1TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)

UART1TXSRC - UART 1 transmit data source select 0b00..UART1_TX pin 0b01..UART1_TX pin modulated with FTM1 channel 0 output 0b10..UART1_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART1TXSRC [3/5]

#define SIM_SOPT5_UART1TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)

UART1TXSRC - UART 1 transmit data source select 0b00..UART1_TX pin 0b01..UART1_TX pin modulated with FTM1 channel 0 output 0b10..UART1_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART1TXSRC [4/5]

#define SIM_SOPT5_UART1TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)

UART1TXSRC - UART 1 transmit data source select 0b00..UART1_TX pin 0b01..UART1_TX pin modulated with FTM1 channel 0 output 0b10..UART1_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT5_UART1TXSRC [5/5]

#define SIM_SOPT5_UART1TXSRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)

UART1TXSRC - UART 1 transmit data source select 0b00..UART1_TX pin 0b01..UART1_TX pin modulated with FTM1 channel 0 output 0b10..UART1_TX pin modulated with FTM2 channel 0 output 0b11..Reserved

◆ SIM_SOPT7_ADC0ALTTRGEN [1/4]

#define SIM_SOPT7_ADC0ALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)

ADC0ALTTRGEN - ADC0 alternate trigger enable 0b0..PDB trigger selected for ADC0. 0b1..Alternate trigger selected for ADC0.

◆ SIM_SOPT7_ADC0ALTTRGEN [2/4]

#define SIM_SOPT7_ADC0ALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)

ADC0ALTTRGEN - ADC0 alternate trigger enable 0b0..PDB trigger selected for ADC0. 0b1..Alternate trigger selected for ADC0.

◆ SIM_SOPT7_ADC0ALTTRGEN [3/4]

#define SIM_SOPT7_ADC0ALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)

ADC0ALTTRGEN - ADC0 alternate trigger enable 0b0..PDB trigger selected for ADC0. 0b1..Alternate trigger selected for ADC0.

◆ SIM_SOPT7_ADC0ALTTRGEN [4/4]

#define SIM_SOPT7_ADC0ALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)

ADC0ALTTRGEN - ADC0 alternate trigger enable 0b0..PDB trigger selected for ADC0. 0b1..Alternate trigger selected for ADC0.

◆ SIM_SOPT7_ADC0PRETRGSEL [1/4]

#define SIM_SOPT7_ADC0PRETRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)

ADC0PRETRGSEL - ADC0 pretrigger select 0b0..Pre-trigger A 0b1..Pre-trigger B

◆ SIM_SOPT7_ADC0PRETRGSEL [2/4]

#define SIM_SOPT7_ADC0PRETRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)

ADC0PRETRGSEL - ADC0 pretrigger select 0b0..Pre-trigger A 0b1..Pre-trigger B

◆ SIM_SOPT7_ADC0PRETRGSEL [3/4]

#define SIM_SOPT7_ADC0PRETRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)

ADC0PRETRGSEL - ADC0 pretrigger select 0b0..Pre-trigger A 0b1..Pre-trigger B

◆ SIM_SOPT7_ADC0PRETRGSEL [4/4]

#define SIM_SOPT7_ADC0PRETRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)

ADC0PRETRGSEL - ADC0 pretrigger select 0b0..Pre-trigger A 0b1..Pre-trigger B

◆ SIM_SOPT7_ADC0TRGSEL [1/5]

#define SIM_SOPT7_ADC0TRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)

ADC0TRGSEL - ADC0 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..Reserved

ADC0TRGSEL - ADC0 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger)

◆ SIM_SOPT7_ADC0TRGSEL [2/5]

#define SIM_SOPT7_ADC0TRGSEL ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)

ADC0TRGSEL - ADC0 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..Reserved

ADC0TRGSEL - ADC0 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger)

◆ SIM_SOPT7_ADC0TRGSEL [3/5]

#define SIM_SOPT7_ADC0TRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)

ADC0TRGSEL - ADC0 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..Reserved

ADC0TRGSEL - ADC0 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger)

◆ SIM_SOPT7_ADC0TRGSEL [4/5]

#define SIM_SOPT7_ADC0TRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)

ADC0TRGSEL - ADC0 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger)

◆ SIM_SOPT7_ADC0TRGSEL [5/5]

#define SIM_SOPT7_ADC0TRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)

ADC0TRGSEL - ADC0 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger)

◆ SIM_SOPT7_ADC1ALTTRGEN [1/4]

#define SIM_SOPT7_ADC1ALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)

ADC1ALTTRGEN - ADC1 alternate trigger enable 0b0..PDB trigger selected for ADC1 0b1..Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.

◆ SIM_SOPT7_ADC1ALTTRGEN [2/4]

#define SIM_SOPT7_ADC1ALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)

ADC1ALTTRGEN - ADC1 alternate trigger enable 0b0..PDB trigger selected for ADC1 0b1..Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.

◆ SIM_SOPT7_ADC1ALTTRGEN [3/4]

#define SIM_SOPT7_ADC1ALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)

ADC1ALTTRGEN - ADC1 alternate trigger enable 0b0..PDB trigger selected for ADC1 0b1..Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.

◆ SIM_SOPT7_ADC1ALTTRGEN [4/4]

#define SIM_SOPT7_ADC1ALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)

ADC1ALTTRGEN - ADC1 alternate trigger enable 0b0..PDB trigger selected for ADC1 0b1..Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.

◆ SIM_SOPT7_ADC1PRETRGSEL [1/4]

#define SIM_SOPT7_ADC1PRETRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)

ADC1PRETRGSEL - ADC1 pre-trigger select 0b0..Pre-trigger A selected for ADC1. 0b1..Pre-trigger B selected for ADC1.

◆ SIM_SOPT7_ADC1PRETRGSEL [2/4]

#define SIM_SOPT7_ADC1PRETRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)

ADC1PRETRGSEL - ADC1 pre-trigger select 0b0..Pre-trigger A selected for ADC1. 0b1..Pre-trigger B selected for ADC1.

◆ SIM_SOPT7_ADC1PRETRGSEL [3/4]

#define SIM_SOPT7_ADC1PRETRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)

ADC1PRETRGSEL - ADC1 pre-trigger select 0b0..Pre-trigger A selected for ADC1. 0b1..Pre-trigger B selected for ADC1.

◆ SIM_SOPT7_ADC1PRETRGSEL [4/4]

#define SIM_SOPT7_ADC1PRETRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)

ADC1PRETRGSEL - ADC1 pre-trigger select 0b0..Pre-trigger A selected for ADC1. 0b1..Pre-trigger B selected for ADC1.

◆ SIM_SOPT7_ADC1TRGSEL [1/5]

#define SIM_SOPT7_ADC1TRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)

ADC1TRGSEL - ADC1 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..Reserved

ADC1TRGSEL - ADC1 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..TPM2 channel 0 (A pretrigger) and channel 1 (B pretrigger)

◆ SIM_SOPT7_ADC1TRGSEL [2/5]

#define SIM_SOPT7_ADC1TRGSEL ( x)    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)

ADC1TRGSEL - ADC1 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..Reserved

ADC1TRGSEL - ADC1 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..TPM2 channel 0 (A pretrigger) and channel 1 (B pretrigger)

◆ SIM_SOPT7_ADC1TRGSEL [3/5]

#define SIM_SOPT7_ADC1TRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)

ADC1TRGSEL - ADC1 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..Reserved

ADC1TRGSEL - ADC1 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..TPM2 channel 0 (A pretrigger) and channel 1 (B pretrigger)

◆ SIM_SOPT7_ADC1TRGSEL [4/5]

#define SIM_SOPT7_ADC1TRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)

ADC1TRGSEL - ADC1 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..TPM2 channel 0 (A pretrigger) and channel 1 (B pretrigger)

◆ SIM_SOPT7_ADC1TRGSEL [5/5]

#define SIM_SOPT7_ADC1TRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)

ADC1TRGSEL - ADC1 trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..RTC alarm 0b1101..RTC seconds 0b1110..Low-power timer (LPTMR) trigger 0b1111..TPM2 channel 0 (A pretrigger) and channel 1 (B pretrigger)

◆ SIM_SOPT7_HSADC0AALTTRGEN

#define SIM_SOPT7_HSADC0AALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0AALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC0AALTTRGEN_MASK)

HSADC0AALTTRGEN - HSADC0A alternate trigger enable 0b00..XBARA output 12. 0b01..PDB0 channel0 trigger selected for HSADC0A.

◆ SIM_SOPT7_HSADC0ATRGSEL

#define SIM_SOPT7_HSADC0ATRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0ATRGSEL_SHIFT)) & SIM_SOPT7_HSADC0ATRGSEL_MASK)

HSADC0ATRGSEL - HSADC0A trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..XBARA output 38 0b1101..Reserved 0b1110..Low-power timer trigger 0b1111..Reserved

◆ SIM_SOPT7_HSADC0BALTTRGEN

#define SIM_SOPT7_HSADC0BALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0BALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC0BALTTRGEN_MASK)

HSADC0BALTTRGEN - HSADC0B alternate trigger enable 0b00..XBARA output 13. 0b01..PDB1 channel0 trigger selected for HSADC0B

◆ SIM_SOPT7_HSADC0BTRGSEL

#define SIM_SOPT7_HSADC0BTRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC0BTRGSEL_SHIFT)) & SIM_SOPT7_HSADC0BTRGSEL_MASK)

HSADC0BTRGSEL - HSADC0B trigger select 0b0000..Reserved 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..XBARA output 41 0b1101..Reserved 0b1110..Low-power timer trigger 0b1111..Reserved

◆ SIM_SOPT7_HSADC1AALTTRGEN

#define SIM_SOPT7_HSADC1AALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1AALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC1AALTTRGEN_MASK)

HSADC1AALTTRGEN - HSADC1A alternate trigger enable 0b00..XBARA output 42. 0b01..PDB1 channel 1 trigger selected for HSADC1A.

◆ SIM_SOPT7_HSADC1ATRGSEL

#define SIM_SOPT7_HSADC1ATRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1ATRGSEL_SHIFT)) & SIM_SOPT7_HSADC1ATRGSEL_MASK)

HSADC1ATRGSEL - HSADC1A trigger select 0b0000..Reserved 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..XBARA output 41 0b1101..Reserved 0b1110..Low-power timer trigger 0b1111..Reserved

◆ SIM_SOPT7_HSADC1BALTTRGEN

#define SIM_SOPT7_HSADC1BALTTRGEN ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1BALTTRGEN_SHIFT)) & SIM_SOPT7_HSADC1BALTTRGEN_MASK)

HSADC1BALTTRGEN - HSADC1B alternate trigger enable 0b00..XBARA output 43. 0b01..PDB0 channel 1 trigger selected for HSADC1B

◆ SIM_SOPT7_HSADC1BTRGSEL

#define SIM_SOPT7_HSADC1BTRGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_HSADC1BTRGSEL_SHIFT)) & SIM_SOPT7_HSADC1BTRGSEL_MASK)

HSADC1BTRGSEL - HSADC1B trigger select 0b0000..PDB external trigger pin input (PDB0_EXTRG) 0b0001..High speed comparator 0 output 0b0010..High speed comparator 1 output 0b0011..High speed comparator 2 output 0b0100..PIT trigger 0 0b0101..PIT trigger 1 0b0110..PIT trigger 2 0b0111..PIT trigger 3 0b1000..FTM0 trigger 0b1001..FTM1 trigger 0b1010..FTM2 trigger 0b1011..FTM3 trigger 0b1100..XBARA output 38 0b1101..Reserved 0b1110..Low-power timer trigger 0b1111..Reserved

◆ SIM_SOPT8_FTM0CFSEL

#define SIM_SOPT8_FTM0CFSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0CFSEL_SHIFT)) & SIM_SOPT8_FTM0CFSEL_MASK)

FTM0CFSEL - Carrier frequency selection for FTM0 output channel 0b0..FTM1 channel 1 output provides the carrier signal for FTM0 Timer Modulation mode. 0b1..LPTMR0 prescaler output provides the carrier signal for FTM0 Timer Modulation mode.

◆ SIM_SOPT8_FTM0OCH0SRC [1/3]

#define SIM_SOPT8_FTM0OCH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)

FTM0OCH0SRC - FTM0 channel 0 output source 0b0..FTM0_CH0 pin is output of FTM0 channel 0 output 0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output

FTM0OCH0SRC - FTM0 channel 0 output source 0b0..FTM0_CH0 pin is output of FTM0 channel 0 output 0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH0SRC [2/3]

#define SIM_SOPT8_FTM0OCH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)

FTM0OCH0SRC - FTM0 channel 0 output source 0b0..FTM0_CH0 pin is output of FTM0 channel 0 output 0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output

FTM0OCH0SRC - FTM0 channel 0 output source 0b0..FTM0_CH0 pin is output of FTM0 channel 0 output 0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH0SRC [3/3]

#define SIM_SOPT8_FTM0OCH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)

FTM0OCH0SRC - FTM0 channel 0 output source 0b0..FTM0_CH0 pin is output of FTM0 channel 0 output 0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH1SRC [1/3]

#define SIM_SOPT8_FTM0OCH1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)

FTM0OCH1SRC - FTM0 channel 1 output source 0b0..FTM0_CH1 pin is output of FTM0 channel 1 output 0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output

FTM0OCH1SRC - FTM0 channel 1 output source 0b0..FTM0_CH1 pin is output of FTM0 channel 1 output 0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH1SRC [2/3]

#define SIM_SOPT8_FTM0OCH1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)

FTM0OCH1SRC - FTM0 channel 1 output source 0b0..FTM0_CH1 pin is output of FTM0 channel 1 output 0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output

FTM0OCH1SRC - FTM0 channel 1 output source 0b0..FTM0_CH1 pin is output of FTM0 channel 1 output 0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH1SRC [3/3]

#define SIM_SOPT8_FTM0OCH1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)

FTM0OCH1SRC - FTM0 channel 1 output source 0b0..FTM0_CH1 pin is output of FTM0 channel 1 output 0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH2SRC [1/3]

#define SIM_SOPT8_FTM0OCH2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)

FTM0OCH2SRC - FTM0 channel 2 output source 0b0..FTM0_CH2 pin is output of FTM0 channel 2 output 0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output

FTM0OCH2SRC - FTM0 channel 2 output source 0b0..FTM0_CH2 pin is output of FTM0 channel 2 output 0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH2SRC [2/3]

#define SIM_SOPT8_FTM0OCH2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)

FTM0OCH2SRC - FTM0 channel 2 output source 0b0..FTM0_CH2 pin is output of FTM0 channel 2 output 0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output

FTM0OCH2SRC - FTM0 channel 2 output source 0b0..FTM0_CH2 pin is output of FTM0 channel 2 output 0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH2SRC [3/3]

#define SIM_SOPT8_FTM0OCH2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)

FTM0OCH2SRC - FTM0 channel 2 output source 0b0..FTM0_CH2 pin is output of FTM0 channel 2 output 0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH3SRC [1/3]

#define SIM_SOPT8_FTM0OCH3SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)

FTM0OCH3SRC - FTM0 channel 3 output source 0b0..FTM0_CH3 pin is output of FTM0 channel 3 output 0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output

FTM0OCH3SRC - FTM0 channel 3 output source 0b0..FTM0_CH3 pin is output of FTM0 channel 3 output 0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH3SRC [2/3]

#define SIM_SOPT8_FTM0OCH3SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)

FTM0OCH3SRC - FTM0 channel 3 output source 0b0..FTM0_CH3 pin is output of FTM0 channel 3 output 0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output

FTM0OCH3SRC - FTM0 channel 3 output source 0b0..FTM0_CH3 pin is output of FTM0 channel 3 output 0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH3SRC [3/3]

#define SIM_SOPT8_FTM0OCH3SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)

FTM0OCH3SRC - FTM0 channel 3 output source 0b0..FTM0_CH3 pin is output of FTM0 channel 3 output 0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH4SRC [1/3]

#define SIM_SOPT8_FTM0OCH4SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)

FTM0OCH4SRC - FTM0 channel 4 output source 0b0..FTM0_CH4 pin is output of FTM0 channel 4 output 0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output

FTM0OCH4SRC - FTM0 channel 4 output source 0b0..FTM0_CH4 pin is output of FTM0 channel 4 output 0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH4SRC [2/3]

#define SIM_SOPT8_FTM0OCH4SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)

FTM0OCH4SRC - FTM0 channel 4 output source 0b0..FTM0_CH4 pin is output of FTM0 channel 4 output 0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output

FTM0OCH4SRC - FTM0 channel 4 output source 0b0..FTM0_CH4 pin is output of FTM0 channel 4 output 0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH4SRC [3/3]

#define SIM_SOPT8_FTM0OCH4SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)

FTM0OCH4SRC - FTM0 channel 4 output source 0b0..FTM0_CH4 pin is output of FTM0 channel 4 output 0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH5SRC [1/3]

#define SIM_SOPT8_FTM0OCH5SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)

FTM0OCH5SRC - FTM0 channel 5 output source 0b0..FTM0_CH5 pin is output of FTM0 channel 5 output 0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output

FTM0OCH5SRC - FTM0 channel 5 output source 0b0..FTM0_CH5 pin is output of FTM0 channel 5 output 0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH5SRC [2/3]

#define SIM_SOPT8_FTM0OCH5SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)

FTM0OCH5SRC - FTM0 channel 5 output source 0b0..FTM0_CH5 pin is output of FTM0 channel 5 output 0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output

FTM0OCH5SRC - FTM0 channel 5 output source 0b0..FTM0_CH5 pin is output of FTM0 channel 5 output 0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH5SRC [3/3]

#define SIM_SOPT8_FTM0OCH5SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)

FTM0OCH5SRC - FTM0 channel 5 output source 0b0..FTM0_CH5 pin is output of FTM0 channel 5 output 0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH6SRC [1/3]

#define SIM_SOPT8_FTM0OCH6SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)

FTM0OCH6SRC - FTM0 channel 6 output source 0b0..FTM0_CH6 pin is output of FTM0 channel 6 output 0b1..FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output

FTM0OCH6SRC - FTM0 channel 6 output source 0b0..FTM0_CH6 pin is output of FTM0 channel 6 output 0b1..FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH6SRC [2/3]

#define SIM_SOPT8_FTM0OCH6SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)

FTM0OCH6SRC - FTM0 channel 6 output source 0b0..FTM0_CH6 pin is output of FTM0 channel 6 output 0b1..FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output

FTM0OCH6SRC - FTM0 channel 6 output source 0b0..FTM0_CH6 pin is output of FTM0 channel 6 output 0b1..FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH6SRC [3/3]

#define SIM_SOPT8_FTM0OCH6SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)

FTM0OCH6SRC - FTM0 channel 6 output source 0b0..FTM0_CH6 pin is output of FTM0 channel 6 output 0b1..FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH7SRC [1/3]

#define SIM_SOPT8_FTM0OCH7SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)

FTM0OCH7SRC - FTM0 channel 7 output source 0b0..FTM0_CH7 pin is output of FTM0 channel 7 output 0b1..FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output

FTM0OCH7SRC - FTM0 channel 7 output source 0b0..FTM0_CH7 pin is output of FTM0 channel 7 output 0b1..FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH7SRC [2/3]

#define SIM_SOPT8_FTM0OCH7SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)

FTM0OCH7SRC - FTM0 channel 7 output source 0b0..FTM0_CH7 pin is output of FTM0 channel 7 output 0b1..FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output

FTM0OCH7SRC - FTM0 channel 7 output source 0b0..FTM0_CH7 pin is output of FTM0 channel 7 output 0b1..FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0OCH7SRC [3/3]

#define SIM_SOPT8_FTM0OCH7SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)

FTM0OCH7SRC - FTM0 channel 7 output source 0b0..FTM0_CH7 pin is output of FTM0 channel 7 output 0b1..FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by carrier frequency clock, as per FTM0CFSEL

◆ SIM_SOPT8_FTM0SYNCBIT [1/3]

#define SIM_SOPT8_FTM0SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)

FTM0SYNCBIT - FTM0 Hardware Trigger 0 Software Synchronization 0b0..No effect 0b1..Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM0SYNCBIT [2/3]

#define SIM_SOPT8_FTM0SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)

FTM0SYNCBIT - FTM0 Hardware Trigger 0 Software Synchronization 0b0..No effect 0b1..Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM0SYNCBIT [3/3]

#define SIM_SOPT8_FTM0SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)

FTM0SYNCBIT - FTM0 Hardware Trigger 0 Software Synchronization 0b0..No effect 0b1..Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM1SYNCBIT [1/3]

#define SIM_SOPT8_FTM1SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)

FTM1SYNCBIT - FTM1 Hardware Trigger 0 Software Synchronization 0b0..No effect. 0b1..Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM1SYNCBIT [2/3]

#define SIM_SOPT8_FTM1SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)

FTM1SYNCBIT - FTM1 Hardware Trigger 0 Software Synchronization 0b0..No effect. 0b1..Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM1SYNCBIT [3/3]

#define SIM_SOPT8_FTM1SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)

FTM1SYNCBIT - FTM1 Hardware Trigger 0 Software Synchronization 0b0..No effect. 0b1..Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM2SYNCBIT [1/3]

#define SIM_SOPT8_FTM2SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)

FTM2SYNCBIT - FTM2 Hardware Trigger 0 Software Synchronization 0b0..No effect. 0b1..Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM2SYNCBIT [2/3]

#define SIM_SOPT8_FTM2SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)

FTM2SYNCBIT - FTM2 Hardware Trigger 0 Software Synchronization 0b0..No effect. 0b1..Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM2SYNCBIT [3/3]

#define SIM_SOPT8_FTM2SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)

FTM2SYNCBIT - FTM2 Hardware Trigger 0 Software Synchronization 0b0..No effect. 0b1..Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM3CFSEL

#define SIM_SOPT8_FTM3CFSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3CFSEL_SHIFT)) & SIM_SOPT8_FTM3CFSEL_MASK)

FTM3CFSEL - Carrier frequency selection for FTM3 output channel 0b0..FTM1 channel 1 output provides the carrier signal for FTM3 Timer Modulation mode. 0b1..LPTMR0 prescaler output provides the carrier signal for FTM3 Timer Modulation mode.

◆ SIM_SOPT8_FTM3OCH0SRC [1/3]

#define SIM_SOPT8_FTM3OCH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)

FTM3OCH0SRC - FTM3 channel 0 output source 0b0..FTM3_CH0 pin is output of FTM3 channel 0 output 0b1..FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 channel 1 output.

FTM3OCH0SRC - FTM3 channel 0 output source 0b0..FTM3_CH0 pin is output of FTM3 channel 0 output 0b1..FTM3_CH0 pin is output of FTM3 channel 0 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH0SRC [2/3]

#define SIM_SOPT8_FTM3OCH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)

FTM3OCH0SRC - FTM3 channel 0 output source 0b0..FTM3_CH0 pin is output of FTM3 channel 0 output 0b1..FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 channel 1 output.

FTM3OCH0SRC - FTM3 channel 0 output source 0b0..FTM3_CH0 pin is output of FTM3 channel 0 output 0b1..FTM3_CH0 pin is output of FTM3 channel 0 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH0SRC [3/3]

#define SIM_SOPT8_FTM3OCH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)

FTM3OCH0SRC - FTM3 channel 0 output source 0b0..FTM3_CH0 pin is output of FTM3 channel 0 output 0b1..FTM3_CH0 pin is output of FTM3 channel 0 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH1SRC [1/3]

#define SIM_SOPT8_FTM3OCH1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)

FTM3OCH1SRC - FTM3 channel 1 output source 0b0..FTM3_CH1 pin is output of FTM3 channel 1 output 0b1..FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 channel 1 output.

FTM3OCH1SRC - FTM3 channel 1 output source 0b0..FTM3_CH1 pin is output of FTM3 channel 1 output 0b1..FTM3_CH1 pin is output of FTM3 channel 1 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH1SRC [2/3]

#define SIM_SOPT8_FTM3OCH1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)

FTM3OCH1SRC - FTM3 channel 1 output source 0b0..FTM3_CH1 pin is output of FTM3 channel 1 output 0b1..FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 channel 1 output.

FTM3OCH1SRC - FTM3 channel 1 output source 0b0..FTM3_CH1 pin is output of FTM3 channel 1 output 0b1..FTM3_CH1 pin is output of FTM3 channel 1 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH1SRC [3/3]

#define SIM_SOPT8_FTM3OCH1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)

FTM3OCH1SRC - FTM3 channel 1 output source 0b0..FTM3_CH1 pin is output of FTM3 channel 1 output 0b1..FTM3_CH1 pin is output of FTM3 channel 1 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH2SRC [1/3]

#define SIM_SOPT8_FTM3OCH2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)

FTM3OCH2SRC - FTM3 channel 2 output source 0b0..FTM3_CH2 pin is output of FTM3 channel 2 output 0b1..FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output.

FTM3OCH2SRC - FTM3 channel 2 output source 0b0..FTM3_CH2 pin is output of FTM3 channel 2 output 0b1..FTM3_CH2 pin is output of FTM3 channel 2 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH2SRC [2/3]

#define SIM_SOPT8_FTM3OCH2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)

FTM3OCH2SRC - FTM3 channel 2 output source 0b0..FTM3_CH2 pin is output of FTM3 channel 2 output 0b1..FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output.

FTM3OCH2SRC - FTM3 channel 2 output source 0b0..FTM3_CH2 pin is output of FTM3 channel 2 output 0b1..FTM3_CH2 pin is output of FTM3 channel 2 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH2SRC [3/3]

#define SIM_SOPT8_FTM3OCH2SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)

FTM3OCH2SRC - FTM3 channel 2 output source 0b0..FTM3_CH2 pin is output of FTM3 channel 2 output 0b1..FTM3_CH2 pin is output of FTM3 channel 2 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH3SRC [1/3]

#define SIM_SOPT8_FTM3OCH3SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)

FTM3OCH3SRC - FTM3 channel 3 output source 0b0..FTM3_CH3 pin is output of FTM3 channel 3 output 0b1..FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 channel 1 output.

FTM3OCH3SRC - FTM3 channel 3 output source 0b0..FTM3_CH3 pin is output of FTM3 channel 3 output 0b1..FTM3_CH3 pin is output of FTM3 channel 3 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH3SRC [2/3]

#define SIM_SOPT8_FTM3OCH3SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)

FTM3OCH3SRC - FTM3 channel 3 output source 0b0..FTM3_CH3 pin is output of FTM3 channel 3 output 0b1..FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 channel 1 output.

FTM3OCH3SRC - FTM3 channel 3 output source 0b0..FTM3_CH3 pin is output of FTM3 channel 3 output 0b1..FTM3_CH3 pin is output of FTM3 channel 3 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH3SRC [3/3]

#define SIM_SOPT8_FTM3OCH3SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)

FTM3OCH3SRC - FTM3 channel 3 output source 0b0..FTM3_CH3 pin is output of FTM3 channel 3 output 0b1..FTM3_CH3 pin is output of FTM3 channel 3 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH4SRC [1/3]

#define SIM_SOPT8_FTM3OCH4SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)

FTM3OCH4SRC - FTM3 channel 4 output source 0b0..FTM3_CH4 pin is output of FTM3 channel 4 output 0b1..FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 channel 1 output.

FTM3OCH4SRC - FTM3 channel 4 output source 0b0..FTM3_CH4 pin is output of FTM3 channel 4 output 0b1..FTM3_CH4 pin is output of FTM3 channel 4 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH4SRC [2/3]

#define SIM_SOPT8_FTM3OCH4SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)

FTM3OCH4SRC - FTM3 channel 4 output source 0b0..FTM3_CH4 pin is output of FTM3 channel 4 output 0b1..FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 channel 1 output.

FTM3OCH4SRC - FTM3 channel 4 output source 0b0..FTM3_CH4 pin is output of FTM3 channel 4 output 0b1..FTM3_CH4 pin is output of FTM3 channel 4 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH4SRC [3/3]

#define SIM_SOPT8_FTM3OCH4SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)

FTM3OCH4SRC - FTM3 channel 4 output source 0b0..FTM3_CH4 pin is output of FTM3 channel 4 output 0b1..FTM3_CH4 pin is output of FTM3 channel 4 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH5SRC [1/3]

#define SIM_SOPT8_FTM3OCH5SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)

FTM3OCH5SRC - FTM3 channel 5 output source 0b0..FTM3_CH5 pin is output of FTM3 channel 5 output 0b1..FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 channel 1 output.

FTM3OCH5SRC - FTM3 channel 5 output source 0b0..FTM3_CH5 pin is output of FTM3 channel 5 output 0b1..FTM3_CH5 pin is output of FTM3 channel 5 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH5SRC [2/3]

#define SIM_SOPT8_FTM3OCH5SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)

FTM3OCH5SRC - FTM3 channel 5 output source 0b0..FTM3_CH5 pin is output of FTM3 channel 5 output 0b1..FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 channel 1 output.

FTM3OCH5SRC - FTM3 channel 5 output source 0b0..FTM3_CH5 pin is output of FTM3 channel 5 output 0b1..FTM3_CH5 pin is output of FTM3 channel 5 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH5SRC [3/3]

#define SIM_SOPT8_FTM3OCH5SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)

FTM3OCH5SRC - FTM3 channel 5 output source 0b0..FTM3_CH5 pin is output of FTM3 channel 5 output 0b1..FTM3_CH5 pin is output of FTM3 channel 5 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH6SRC [1/3]

#define SIM_SOPT8_FTM3OCH6SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)

FTM3OCH6SRC - FTM3 channel 6 output source 0b0..FTM3_CH6 pin is output of FTM3 channel 6 output 0b1..FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output.

FTM3OCH6SRC - FTM3 channel 6 output source 0b0..FTM3_CH6 pin is output of FTM3 channel 6 output 0b1..FTM3_CH6 pin is output of FTM3 channel 6 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH6SRC [2/3]

#define SIM_SOPT8_FTM3OCH6SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)

FTM3OCH6SRC - FTM3 channel 6 output source 0b0..FTM3_CH6 pin is output of FTM3 channel 6 output 0b1..FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output.

FTM3OCH6SRC - FTM3 channel 6 output source 0b0..FTM3_CH6 pin is output of FTM3 channel 6 output 0b1..FTM3_CH6 pin is output of FTM3 channel 6 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH6SRC [3/3]

#define SIM_SOPT8_FTM3OCH6SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)

FTM3OCH6SRC - FTM3 channel 6 output source 0b0..FTM3_CH6 pin is output of FTM3 channel 6 output 0b1..FTM3_CH6 pin is output of FTM3 channel 6 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH7SRC [1/3]

#define SIM_SOPT8_FTM3OCH7SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)

FTM3OCH7SRC - FTM3 channel 7 output source 0b0..FTM3_CH7 pin is output of FTM3 channel 7 output 0b1..FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 channel 1 output.

FTM3OCH7SRC - FTM3 channel 7 output source 0b0..FTM3_CH7 pin is output of FTM3 channel 7 output 0b1..FTM3_CH7 pin is output of FTM3 channel 7 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH7SRC [2/3]

#define SIM_SOPT8_FTM3OCH7SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)

FTM3OCH7SRC - FTM3 channel 7 output source 0b0..FTM3_CH7 pin is output of FTM3 channel 7 output 0b1..FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 channel 1 output.

FTM3OCH7SRC - FTM3 channel 7 output source 0b0..FTM3_CH7 pin is output of FTM3 channel 7 output 0b1..FTM3_CH7 pin is output of FTM3 channel 7 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3OCH7SRC [3/3]

#define SIM_SOPT8_FTM3OCH7SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)

FTM3OCH7SRC - FTM3 channel 7 output source 0b0..FTM3_CH7 pin is output of FTM3 channel 7 output 0b1..FTM3_CH7 pin is output of FTM3 channel 7 output modulated by carrier frequency clock, as per FTM3CFSEL.

◆ SIM_SOPT8_FTM3SYNCBIT [1/3]

#define SIM_SOPT8_FTM3SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)

FTM3SYNCBIT - FTM3 Hardware Trigger 0 Software Synchronization 0b0..No effect. 0b1..Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM3SYNCBIT [2/3]

#define SIM_SOPT8_FTM3SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)

FTM3SYNCBIT - FTM3 Hardware Trigger 0 Software Synchronization 0b0..No effect. 0b1..Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT8_FTM3SYNCBIT [3/3]

#define SIM_SOPT8_FTM3SYNCBIT ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)

FTM3SYNCBIT - FTM3 Hardware Trigger 0 Software Synchronization 0b0..No effect. 0b1..Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert.

◆ SIM_SOPT9_FTM0CLKSEL

#define SIM_SOPT9_FTM0CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM0CLKSEL_SHIFT)) & SIM_SOPT9_FTM0CLKSEL_MASK)

FTM0CLKSEL - FlexTimer 0 External Clock Pin Select 0b00..FTM0 external clock driven by FTM_CLK0 pin 0b01..FTM0 external clock driven by FTM_CLK1 pin 0b10..FTM0 external clock driven by FTM_CLK2 pin 0b11..Reserved

◆ SIM_SOPT9_FTM1CLKSEL

#define SIM_SOPT9_FTM1CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM1CLKSEL_SHIFT)) & SIM_SOPT9_FTM1CLKSEL_MASK)

FTM1CLKSEL - FlexTimer 1 External Clock Pin Select 0b00..FTM1 external clock driven by FTM_CLK0 pin 0b01..FTM1 external clock driven by FTM_CLK1 pin 0b10..FTM1 external clock driven by FTM_CLK2 pin 0b11..Reserved

◆ SIM_SOPT9_FTM1ICH0SRC

#define SIM_SOPT9_FTM1ICH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM1ICH0SRC_SHIFT)) & SIM_SOPT9_FTM1ICH0SRC_MASK)

FTM1ICH0SRC - FTM1 channel 0 input capture source select 0b00..FTM1_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT9_FTM1ICH1SRC

#define SIM_SOPT9_FTM1ICH1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM1ICH1SRC_SHIFT)) & SIM_SOPT9_FTM1ICH1SRC_MASK)

FTM1ICH1SRC - FTM1 channel 0 input capture source select 0b0..FTM1_CH1 signal 0b1..Exclusive OR of FTM1_CH1, FTM1_CH0, and XBARA output 42 (XBARA output 42 can also trigger HSADC1A sync0)

◆ SIM_SOPT9_FTM2CLKSEL

#define SIM_SOPT9_FTM2CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM2CLKSEL_SHIFT)) & SIM_SOPT9_FTM2CLKSEL_MASK)

FTM2CLKSEL - FlexTimer 2 External Clock Pin Select 0b00..FTM2 external clock driven by FTM_CLK0 pin 0b01..FTM2 external clock driven by FTM_CLK1 pin 0b10..FTM2 external clock driven by FTM_CLK2 pin 0b11..Reserved

◆ SIM_SOPT9_FTM2ICH0SRC

#define SIM_SOPT9_FTM2ICH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM2ICH0SRC_SHIFT)) & SIM_SOPT9_FTM2ICH0SRC_MASK)

FTM2ICH0SRC - FTM2 channel 0 input capture source select 0b00..FTM2_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT9_FTM2ICH1SRC

#define SIM_SOPT9_FTM2ICH1SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM2ICH1SRC_SHIFT)) & SIM_SOPT9_FTM2ICH1SRC_MASK)

FTM2ICH1SRC - FTM2 channel 1 input capture source select 0b0..FTM2_CH1 signal 0b1..Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1

◆ SIM_SOPT9_FTM3CLKSEL

#define SIM_SOPT9_FTM3CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_FTM3CLKSEL_SHIFT)) & SIM_SOPT9_FTM3CLKSEL_MASK)

FTM3CLKSEL - FlexTimer 3 External Clock Pin Select 0b00..FTM3 external clock driven by FTM_CLK0 pin 0b01..FTM3 external clock driven by FTM_CLK1 pin 0b10..FTM3 external clock driven by FTM_CLK2 pin 0b11..Reserved

◆ SIM_SOPT9_TPM1CH0SRC [1/2]

#define SIM_SOPT9_TPM1CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)

TPM1CH0SRC - TPM1 channel 0 input capture source select 0b00..TPM1_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT9_TPM1CH0SRC [2/2]

#define SIM_SOPT9_TPM1CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)

TPM1CH0SRC - TPM1 channel 0 input capture source select 0b00..TPM1_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT9_TPM1CLKSEL [1/2]

#define SIM_SOPT9_TPM1CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)

TPM1CLKSEL - TPM1 External Clock Pin Select 0b0..TPM_CLKIN0 pin 0b1..TPM_CLKIN1 pin

◆ SIM_SOPT9_TPM1CLKSEL [2/2]

#define SIM_SOPT9_TPM1CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)

TPM1CLKSEL - TPM1 External Clock Pin Select 0b0..TPM_CLKIN0 pin 0b1..TPM_CLKIN1 pin

◆ SIM_SOPT9_TPM2CH0SRC [1/2]

#define SIM_SOPT9_TPM2CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)

TPM2CH0SRC - TPM2 channel 0 input capture source select 0b00..TPM2_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT9_TPM2CH0SRC [2/2]

#define SIM_SOPT9_TPM2CH0SRC ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)

TPM2CH0SRC - TPM2 channel 0 input capture source select 0b00..TPM2_CH0 signal 0b01..CMP0 output 0b10..CMP1 output 0b11..Reserved

◆ SIM_SOPT9_TPM2CLKSEL [1/2]

#define SIM_SOPT9_TPM2CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)

TPM2CLKSEL - TPM2 External Clock Pin Select 0b0..TPM_CLKIN0 pin 0b1..TPM_CLKIN1 pin

◆ SIM_SOPT9_TPM2CLKSEL [2/2]

#define SIM_SOPT9_TPM2CLKSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)

TPM2CLKSEL - TPM2 External Clock Pin Select 0b0..TPM_CLKIN0 pin 0b1..TPM_CLKIN1 pin

◆ SIM_USBPHYCTL_USB3VOUTTRG [1/2]

#define SIM_USBPHYCTL_USB3VOUTTRG ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)

USB3VOUTTRG - USB 3.3V Output Target 0b000..2.733V 0b001..3.020V 0b010..3.074V 0b011..3.130V 0b100..3.188V 0b101..3.248V 0b110..3.310V (default) 0b111..3.662V (For Freescale use only, not for customer use)

◆ SIM_USBPHYCTL_USB3VOUTTRG [2/2]

#define SIM_USBPHYCTL_USB3VOUTTRG ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)

USB3VOUTTRG - USB 3.3V Output Target 0b000..2.733V 0b001..3.020V 0b010..3.074V 0b011..3.130V 0b100..3.188V 0b101..3.248V 0b110..3.310V (default) 0b111..3.662V (For Freescale use only, not for customer use)

◆ SIM_USBPHYCTL_USBDISILIM [1/2]

#define SIM_USBPHYCTL_USBDISILIM ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)

USBDISILIM - USB Disable Inrush Current Limit 0b0..The current limiter for the USB Voltage Regulator is enabled 0b1..The current limiter for the USB Voltage Regulator is disabled

◆ SIM_USBPHYCTL_USBDISILIM [2/2]

#define SIM_USBPHYCTL_USBDISILIM ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)

USBDISILIM - USB Disable Inrush Current Limit 0b0..The current limiter for the USB Voltage Regulator is enabled 0b1..The current limiter for the USB Voltage Regulator is disabled

◆ SIM_USBPHYCTL_USBVREGPD [1/2]

#define SIM_USBPHYCTL_USBVREGPD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)

USBVREGPD 0b0..Regulator output pulldown resistor is not enabled 0b1..Regulator output pulldown resistor is enabled

◆ SIM_USBPHYCTL_USBVREGPD [2/2]

#define SIM_USBPHYCTL_USBVREGPD ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)

USBVREGPD 0b0..Regulator output pulldown resistor is not enabled 0b1..Regulator output pulldown resistor is enabled

◆ SIM_USBPHYCTL_USBVREGSEL [1/2]

#define SIM_USBPHYCTL_USBVREGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)

USBVREGSEL 0b0..VREG_IN0 will be selected if both regulator inputs are powered 0b1..VREG_IN1 will be selected if both regulator inputs are powered

◆ SIM_USBPHYCTL_USBVREGSEL [2/2]

#define SIM_USBPHYCTL_USBVREGSEL ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)

USBVREGSEL 0b0..VREG_IN0 will be selected if both regulator inputs are powered 0b1..VREG_IN1 will be selected if both regulator inputs are powered

◆ SIM_WDOGC_WDOGCLKS

#define SIM_WDOGC_WDOGCLKS ( x)    (((uint32_t)(((uint32_t)(x)) << SIM_WDOGC_WDOGCLKS_SHIFT)) & SIM_WDOGC_WDOGCLKS_MASK)

WDOGCLKS - WDOG Clock Select 0b0..1 kHz LPO clock is source to WDOG 0b1..MCGIRCLK is source to WDOG