Topics
	CAN Register Masks

	CAU Peripheral Access Layer

Data Structures
struct	CAN_Type

Macros
#define	CAN0_BASE (0x40024000u)

#define	CAN0 ((CAN_Type *)CAN0_BASE)

#define	CAN1_BASE (0x400A4000u)

#define	CAN1 ((CAN_Type *)CAN1_BASE)

#define	CAN0_BASE (0x40024000u)

#define	CAN0 ((CAN_Type *)CAN0_BASE)

#define	CAN_BASE_ADDRS { CAN0_BASE }

#define	CAN_BASE_PTRS { CAN0 }

#define	CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }

#define	CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }

#define	CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }

#define	CAN_Error_IRQS { CAN0_Error_IRQn }

#define	CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }

#define	CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }

#define	CAN0_BASE (0x40024000u)

#define	CAN0 ((CAN_Type *)CAN0_BASE)

#define	CAN1_BASE (0x400A4000u)

#define	CAN1 ((CAN_Type *)CAN1_BASE)

#define	CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }

#define	CAN_BASE_PTRS { CAN0, CAN1 }

#define	CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }

#define	CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }

#define	CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }

#define	CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }

#define	CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }

#define	CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }

#define	CAN0_BASE (0x40024000u)

#define	CAN0 ((CAN_Type *)CAN0_BASE)

#define	CAN1_BASE (0x400A4000u)

#define	CAN1 ((CAN_Type *)CAN1_BASE)

#define	CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }

#define	CAN_BASE_PTRS { CAN0, CAN1 }

#define	CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }

#define	CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }

#define	CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }

#define	CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }

#define	CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }

#define	CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }

#define	CAN0_BASE (0x40024000u)

#define	CAN0 ((CAN_Type *)CAN0_BASE)

#define	CAN1_BASE (0x40025000u)

#define	CAN1 ((CAN_Type *)CAN1_BASE)

#define	CAN2_BASE (0x400A4000u)

#define	CAN2 ((CAN_Type *)CAN2_BASE)

#define	CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE, CAN2_BASE }

#define	CAN_BASE_PTRS { CAN0, CAN1, CAN2 }

#define	CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn, CAN2_Rx_Warning_IRQn }

#define	CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn, CAN2_Tx_Warning_IRQn }

#define	CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn, CAN2_Wake_Up_IRQn }

#define	CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn, CAN2_Error_IRQn }

#define	CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn, CAN2_Bus_Off_IRQn }

#define	CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn, CAN2_ORed_Message_buffer_IRQn }

#define	CAN_IMASK1_BUFLM_MASK CAN_IMASK1_BUF31TO0M_MASK

#define	CAN_IMASK1_BUFLM_SHIFT CAN_IMASK1_BUF31TO0M_SHIFT

#define	CAN_IMASK1_BUFLM_WIDTH CAN_IMASK1_BUF31TO0M_WIDTH

#define	CAN_IMASK1_BUFLM(x) CAN_IMASK1_BUF31TO0M(x)

Macro Definition Documentation

◆ CAN0 [1/5]

#define CAN0 ((CAN_Type *)CAN0_BASE)

Peripheral CAN0 base pointer

◆ CAN0 [2/5]

#define CAN0 ((CAN_Type *)CAN0_BASE)

Peripheral CAN0 base pointer

◆ CAN0 [3/5]

#define CAN0 ((CAN_Type *)CAN0_BASE)

Peripheral CAN0 base pointer

◆ CAN0 [4/5]

#define CAN0 ((CAN_Type *)CAN0_BASE)

Peripheral CAN0 base pointer