mikroSDK Reference Manual
Macros
CAN Register Masks
Mapping Information » Device Peripheral Access Layer » ADC Peripheral Access Layer » AIPS Peripheral Access Layer » AXBS Peripheral Access Layer » CAN Peripheral Access Layer

Macros

#define CAN0_BASE   (0x40024000u)
 
#define CAN0   ((CAN_Type *)CAN0_BASE)
 
#define CAN1_BASE   (0x400A4000u)
 
#define CAN1   ((CAN_Type *)CAN1_BASE)
 
#define CAN_BASE_ADDRS   { CAN0_BASE, CAN1_BASE }
 
#define CAN_BASE_PTRS   { CAN0, CAN1 }
 
#define CAN_Rx_Warning_IRQS   { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }
 
#define CAN_Tx_Warning_IRQS   { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }
 
#define CAN_Wake_Up_IRQS   { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }
 
#define CAN_Error_IRQS   { CAN0_Error_IRQn, CAN1_Error_IRQn }
 
#define CAN_Bus_Off_IRQS   { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
 
#define CAN_ORed_Message_buffer_IRQS   { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
 
#define CAN_IMASK2_BUFHM_MASK   0xFFFFFFFFu
 
#define CAN_IMASK2_BUFHM_SHIFT   0
 
#define CAN_IMASK2_BUFHM(x)   (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUFHM_SHIFT))&CAN_IMASK2_BUFHM_MASK)
 
#define CAN_IFLAG2_BUFHI_MASK   0xFFFFFFFFu
 
#define CAN_IFLAG2_BUFHI_SHIFT   0
 
#define CAN_IFLAG2_BUFHI(x)   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUFHI_SHIFT))&CAN_IFLAG2_BUFHI_MASK)
 
#define CAN_IFLAG1_BUF4TO0I_MASK   0x1Fu
 
#define CAN_IFLAG1_BUF4TO0I_SHIFT   0
 
#define CAN_IFLAG1_BUF4TO0I(x)   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)
 
#define CAN_CS_COUNT   (16U)
 
#define CAN_ID_COUNT   (16U)
 
#define CAN_WORD0_COUNT   (16U)
 
#define CAN_WORD1_COUNT   (16U)
 
#define CAN_RXIMR_COUNT   (16U)
 
#define CAN_CS_COUNT   (16U)
 
#define CAN_ID_COUNT   (16U)
 
#define CAN_WORD0_COUNT   (16U)
 
#define CAN_WORD1_COUNT   (16U)
 
#define CAN_RXIMR_COUNT   (16U)
 
#define CAN_CS_COUNT   (16U)
 
#define CAN_ID_COUNT   (16U)
 
#define CAN_WORD0_COUNT   (16U)
 
#define CAN_WORD1_COUNT   (16U)
 
#define CAN_RXIMR_COUNT   (16U)
 
#define CAN_CS_COUNT   (16U)
 
#define CAN_ID_COUNT   (16U)
 
#define CAN_WORD0_COUNT   (16U)
 
#define CAN_WORD1_COUNT   (16U)
 
#define CAN_RXIMR_COUNT   (16U)
 

MCR - Module Configuration Register

#define CAN_MCR_MAXMB_MASK   (0x7FU)
 
#define CAN_MCR_MAXMB_SHIFT   (0U)
 
#define CAN_MCR_MAXMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
 
#define CAN_MCR_IDAM_MASK   (0x300U)
 
#define CAN_MCR_IDAM_SHIFT   (8U)
 
#define CAN_MCR_IDAM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
 
#define CAN_MCR_AEN_MASK   (0x1000U)
 
#define CAN_MCR_AEN_SHIFT   (12U)
 
#define CAN_MCR_AEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
 
#define CAN_MCR_LPRIOEN_MASK   (0x2000U)
 
#define CAN_MCR_LPRIOEN_SHIFT   (13U)
 
#define CAN_MCR_LPRIOEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
 
#define CAN_MCR_IRMQ_MASK   (0x10000U)
 
#define CAN_MCR_IRMQ_SHIFT   (16U)
 
#define CAN_MCR_IRMQ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
 
#define CAN_MCR_SRXDIS_MASK   (0x20000U)
 
#define CAN_MCR_SRXDIS_SHIFT   (17U)
 
#define CAN_MCR_SRXDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
 
#define CAN_MCR_WAKSRC_MASK   (0x80000U)
 
#define CAN_MCR_WAKSRC_SHIFT   (19U)
 
#define CAN_MCR_WAKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
 
#define CAN_MCR_LPMACK_MASK   (0x100000U)
 
#define CAN_MCR_LPMACK_SHIFT   (20U)
 
#define CAN_MCR_LPMACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
 
#define CAN_MCR_WRNEN_MASK   (0x200000U)
 
#define CAN_MCR_WRNEN_SHIFT   (21U)
 
#define CAN_MCR_WRNEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
 
#define CAN_MCR_SLFWAK_MASK   (0x400000U)
 
#define CAN_MCR_SLFWAK_SHIFT   (22U)
 
#define CAN_MCR_SLFWAK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
 
#define CAN_MCR_SUPV_MASK   (0x800000U)
 
#define CAN_MCR_SUPV_SHIFT   (23U)
 
#define CAN_MCR_SUPV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
 
#define CAN_MCR_FRZACK_MASK   (0x1000000U)
 
#define CAN_MCR_FRZACK_SHIFT   (24U)
 
#define CAN_MCR_FRZACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
 
#define CAN_MCR_SOFTRST_MASK   (0x2000000U)
 
#define CAN_MCR_SOFTRST_SHIFT   (25U)
 
#define CAN_MCR_SOFTRST(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
 
#define CAN_MCR_WAKMSK_MASK   (0x4000000U)
 
#define CAN_MCR_WAKMSK_SHIFT   (26U)
 
#define CAN_MCR_WAKMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
 
#define CAN_MCR_NOTRDY_MASK   (0x8000000U)
 
#define CAN_MCR_NOTRDY_SHIFT   (27U)
 
#define CAN_MCR_NOTRDY(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
 
#define CAN_MCR_HALT_MASK   (0x10000000U)
 
#define CAN_MCR_HALT_SHIFT   (28U)
 
#define CAN_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
 
#define CAN_MCR_RFEN_MASK   (0x20000000U)
 
#define CAN_MCR_RFEN_SHIFT   (29U)
 
#define CAN_MCR_RFEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
 
#define CAN_MCR_FRZ_MASK   (0x40000000U)
 
#define CAN_MCR_FRZ_SHIFT   (30U)
 
#define CAN_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
 
#define CAN_MCR_MDIS_MASK   (0x80000000U)
 
#define CAN_MCR_MDIS_SHIFT   (31U)
 
#define CAN_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
 
#define CAN_MCR_MAXMB_MASK   0x7Fu
 
#define CAN_MCR_MAXMB_SHIFT   0
 
#define CAN_MCR_MAXMB(x)   (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
 
#define CAN_MCR_IDAM_MASK   0x300u
 
#define CAN_MCR_IDAM_SHIFT   8
 
#define CAN_MCR_IDAM(x)   (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
 
#define CAN_MCR_AEN_MASK   0x1000u
 
#define CAN_MCR_AEN_SHIFT   12
 
#define CAN_MCR_LPRIOEN_MASK   0x2000u
 
#define CAN_MCR_LPRIOEN_SHIFT   13
 
#define CAN_MCR_IRMQ_MASK   0x10000u
 
#define CAN_MCR_IRMQ_SHIFT   16
 
#define CAN_MCR_SRXDIS_MASK   0x20000u
 
#define CAN_MCR_SRXDIS_SHIFT   17
 
#define CAN_MCR_DOZE_MASK   0x40000u
 
#define CAN_MCR_DOZE_SHIFT   18
 
#define CAN_MCR_LPMACK_MASK   0x100000u
 
#define CAN_MCR_LPMACK_SHIFT   20
 
#define CAN_MCR_WRNEN_MASK   0x200000u
 
#define CAN_MCR_WRNEN_SHIFT   21
 
#define CAN_MCR_SLFWAK_MASK   0x400000u
 
#define CAN_MCR_SLFWAK_SHIFT   22
 
#define CAN_MCR_SUPV_MASK   0x800000u
 
#define CAN_MCR_SUPV_SHIFT   23
 
#define CAN_MCR_FRZACK_MASK   0x1000000u
 
#define CAN_MCR_FRZACK_SHIFT   24
 
#define CAN_MCR_SOFTRST_MASK   0x2000000u
 
#define CAN_MCR_SOFTRST_SHIFT   25
 
#define CAN_MCR_WAKMSK_MASK   0x4000000u
 
#define CAN_MCR_WAKMSK_SHIFT   26
 
#define CAN_MCR_NOTRDY_MASK   0x8000000u
 
#define CAN_MCR_NOTRDY_SHIFT   27
 
#define CAN_MCR_HALT_MASK   0x10000000u
 
#define CAN_MCR_HALT_SHIFT   28
 
#define CAN_MCR_RFEN_MASK   0x20000000u
 
#define CAN_MCR_RFEN_SHIFT   29
 
#define CAN_MCR_FRZ_MASK   0x40000000u
 
#define CAN_MCR_FRZ_SHIFT   30
 
#define CAN_MCR_MDIS_MASK   0x80000000u
 
#define CAN_MCR_MDIS_SHIFT   31
 
#define CAN_MCR_MAXMB_MASK   (0x7FU)
 
#define CAN_MCR_MAXMB_SHIFT   (0U)
 
#define CAN_MCR_MAXMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
 
#define CAN_MCR_IDAM_MASK   (0x300U)
 
#define CAN_MCR_IDAM_SHIFT   (8U)
 
#define CAN_MCR_IDAM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
 
#define CAN_MCR_AEN_MASK   (0x1000U)
 
#define CAN_MCR_AEN_SHIFT   (12U)
 
#define CAN_MCR_AEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
 
#define CAN_MCR_LPRIOEN_MASK   (0x2000U)
 
#define CAN_MCR_LPRIOEN_SHIFT   (13U)
 
#define CAN_MCR_LPRIOEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
 
#define CAN_MCR_IRMQ_MASK   (0x10000U)
 
#define CAN_MCR_IRMQ_SHIFT   (16U)
 
#define CAN_MCR_IRMQ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
 
#define CAN_MCR_SRXDIS_MASK   (0x20000U)
 
#define CAN_MCR_SRXDIS_SHIFT   (17U)
 
#define CAN_MCR_SRXDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
 
#define CAN_MCR_WAKSRC_MASK   (0x80000U)
 
#define CAN_MCR_WAKSRC_SHIFT   (19U)
 
#define CAN_MCR_WAKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
 
#define CAN_MCR_LPMACK_MASK   (0x100000U)
 
#define CAN_MCR_LPMACK_SHIFT   (20U)
 
#define CAN_MCR_LPMACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
 
#define CAN_MCR_WRNEN_MASK   (0x200000U)
 
#define CAN_MCR_WRNEN_SHIFT   (21U)
 
#define CAN_MCR_WRNEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
 
#define CAN_MCR_SLFWAK_MASK   (0x400000U)
 
#define CAN_MCR_SLFWAK_SHIFT   (22U)
 
#define CAN_MCR_SLFWAK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
 
#define CAN_MCR_SUPV_MASK   (0x800000U)
 
#define CAN_MCR_SUPV_SHIFT   (23U)
 
#define CAN_MCR_SUPV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
 
#define CAN_MCR_FRZACK_MASK   (0x1000000U)
 
#define CAN_MCR_FRZACK_SHIFT   (24U)
 
#define CAN_MCR_FRZACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
 
#define CAN_MCR_SOFTRST_MASK   (0x2000000U)
 
#define CAN_MCR_SOFTRST_SHIFT   (25U)
 
#define CAN_MCR_SOFTRST(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
 
#define CAN_MCR_WAKMSK_MASK   (0x4000000U)
 
#define CAN_MCR_WAKMSK_SHIFT   (26U)
 
#define CAN_MCR_WAKMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
 
#define CAN_MCR_NOTRDY_MASK   (0x8000000U)
 
#define CAN_MCR_NOTRDY_SHIFT   (27U)
 
#define CAN_MCR_NOTRDY(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
 
#define CAN_MCR_HALT_MASK   (0x10000000U)
 
#define CAN_MCR_HALT_SHIFT   (28U)
 
#define CAN_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
 
#define CAN_MCR_RFEN_MASK   (0x20000000U)
 
#define CAN_MCR_RFEN_SHIFT   (29U)
 
#define CAN_MCR_RFEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
 
#define CAN_MCR_FRZ_MASK   (0x40000000U)
 
#define CAN_MCR_FRZ_SHIFT   (30U)
 
#define CAN_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
 
#define CAN_MCR_MDIS_MASK   (0x80000000U)
 
#define CAN_MCR_MDIS_SHIFT   (31U)
 
#define CAN_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
 
#define CAN_MCR_MAXMB_MASK   (0x7FU)
 
#define CAN_MCR_MAXMB_SHIFT   (0U)
 
#define CAN_MCR_MAXMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
 
#define CAN_MCR_IDAM_MASK   (0x300U)
 
#define CAN_MCR_IDAM_SHIFT   (8U)
 
#define CAN_MCR_IDAM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
 
#define CAN_MCR_AEN_MASK   (0x1000U)
 
#define CAN_MCR_AEN_SHIFT   (12U)
 
#define CAN_MCR_AEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
 
#define CAN_MCR_LPRIOEN_MASK   (0x2000U)
 
#define CAN_MCR_LPRIOEN_SHIFT   (13U)
 
#define CAN_MCR_LPRIOEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
 
#define CAN_MCR_IRMQ_MASK   (0x10000U)
 
#define CAN_MCR_IRMQ_SHIFT   (16U)
 
#define CAN_MCR_IRMQ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
 
#define CAN_MCR_SRXDIS_MASK   (0x20000U)
 
#define CAN_MCR_SRXDIS_SHIFT   (17U)
 
#define CAN_MCR_SRXDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
 
#define CAN_MCR_WAKSRC_MASK   (0x80000U)
 
#define CAN_MCR_WAKSRC_SHIFT   (19U)
 
#define CAN_MCR_WAKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
 
#define CAN_MCR_LPMACK_MASK   (0x100000U)
 
#define CAN_MCR_LPMACK_SHIFT   (20U)
 
#define CAN_MCR_LPMACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
 
#define CAN_MCR_WRNEN_MASK   (0x200000U)
 
#define CAN_MCR_WRNEN_SHIFT   (21U)
 
#define CAN_MCR_WRNEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
 
#define CAN_MCR_SLFWAK_MASK   (0x400000U)
 
#define CAN_MCR_SLFWAK_SHIFT   (22U)
 
#define CAN_MCR_SLFWAK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
 
#define CAN_MCR_SUPV_MASK   (0x800000U)
 
#define CAN_MCR_SUPV_SHIFT   (23U)
 
#define CAN_MCR_SUPV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
 
#define CAN_MCR_FRZACK_MASK   (0x1000000U)
 
#define CAN_MCR_FRZACK_SHIFT   (24U)
 
#define CAN_MCR_FRZACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
 
#define CAN_MCR_SOFTRST_MASK   (0x2000000U)
 
#define CAN_MCR_SOFTRST_SHIFT   (25U)
 
#define CAN_MCR_SOFTRST(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
 
#define CAN_MCR_WAKMSK_MASK   (0x4000000U)
 
#define CAN_MCR_WAKMSK_SHIFT   (26U)
 
#define CAN_MCR_WAKMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
 
#define CAN_MCR_NOTRDY_MASK   (0x8000000U)
 
#define CAN_MCR_NOTRDY_SHIFT   (27U)
 
#define CAN_MCR_NOTRDY(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
 
#define CAN_MCR_HALT_MASK   (0x10000000U)
 
#define CAN_MCR_HALT_SHIFT   (28U)
 
#define CAN_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
 
#define CAN_MCR_RFEN_MASK   (0x20000000U)
 
#define CAN_MCR_RFEN_SHIFT   (29U)
 
#define CAN_MCR_RFEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
 
#define CAN_MCR_FRZ_MASK   (0x40000000U)
 
#define CAN_MCR_FRZ_SHIFT   (30U)
 
#define CAN_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
 
#define CAN_MCR_MDIS_MASK   (0x80000000U)
 
#define CAN_MCR_MDIS_SHIFT   (31U)
 
#define CAN_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
 
#define CAN_MCR_MAXMB_MASK   (0x7FU)
 
#define CAN_MCR_MAXMB_SHIFT   (0U)
 
#define CAN_MCR_MAXMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
 
#define CAN_MCR_IDAM_MASK   (0x300U)
 
#define CAN_MCR_IDAM_SHIFT   (8U)
 
#define CAN_MCR_IDAM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
 
#define CAN_MCR_AEN_MASK   (0x1000U)
 
#define CAN_MCR_AEN_SHIFT   (12U)
 
#define CAN_MCR_AEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
 
#define CAN_MCR_LPRIOEN_MASK   (0x2000U)
 
#define CAN_MCR_LPRIOEN_SHIFT   (13U)
 
#define CAN_MCR_LPRIOEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
 
#define CAN_MCR_IRMQ_MASK   (0x10000U)
 
#define CAN_MCR_IRMQ_SHIFT   (16U)
 
#define CAN_MCR_IRMQ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
 
#define CAN_MCR_SRXDIS_MASK   (0x20000U)
 
#define CAN_MCR_SRXDIS_SHIFT   (17U)
 
#define CAN_MCR_SRXDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
 
#define CAN_MCR_WAKSRC_MASK   (0x80000U)
 
#define CAN_MCR_WAKSRC_SHIFT   (19U)
 
#define CAN_MCR_WAKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
 
#define CAN_MCR_LPMACK_MASK   (0x100000U)
 
#define CAN_MCR_LPMACK_SHIFT   (20U)
 
#define CAN_MCR_LPMACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
 
#define CAN_MCR_WRNEN_MASK   (0x200000U)
 
#define CAN_MCR_WRNEN_SHIFT   (21U)
 
#define CAN_MCR_WRNEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
 
#define CAN_MCR_SLFWAK_MASK   (0x400000U)
 
#define CAN_MCR_SLFWAK_SHIFT   (22U)
 
#define CAN_MCR_SLFWAK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
 
#define CAN_MCR_SUPV_MASK   (0x800000U)
 
#define CAN_MCR_SUPV_SHIFT   (23U)
 
#define CAN_MCR_SUPV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
 
#define CAN_MCR_FRZACK_MASK   (0x1000000U)
 
#define CAN_MCR_FRZACK_SHIFT   (24U)
 
#define CAN_MCR_FRZACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
 
#define CAN_MCR_SOFTRST_MASK   (0x2000000U)
 
#define CAN_MCR_SOFTRST_SHIFT   (25U)
 
#define CAN_MCR_SOFTRST(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
 
#define CAN_MCR_WAKMSK_MASK   (0x4000000U)
 
#define CAN_MCR_WAKMSK_SHIFT   (26U)
 
#define CAN_MCR_WAKMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
 
#define CAN_MCR_NOTRDY_MASK   (0x8000000U)
 
#define CAN_MCR_NOTRDY_SHIFT   (27U)
 
#define CAN_MCR_NOTRDY(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
 
#define CAN_MCR_HALT_MASK   (0x10000000U)
 
#define CAN_MCR_HALT_SHIFT   (28U)
 
#define CAN_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
 
#define CAN_MCR_RFEN_MASK   (0x20000000U)
 
#define CAN_MCR_RFEN_SHIFT   (29U)
 
#define CAN_MCR_RFEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
 
#define CAN_MCR_FRZ_MASK   (0x40000000U)
 
#define CAN_MCR_FRZ_SHIFT   (30U)
 
#define CAN_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
 
#define CAN_MCR_MDIS_MASK   (0x80000000U)
 
#define CAN_MCR_MDIS_SHIFT   (31U)
 
#define CAN_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
 
#define CAN_MCR_MAXMB_MASK   (0x7FU)
 
#define CAN_MCR_MAXMB_SHIFT   (0U)
 
#define CAN_MCR_MAXMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
 
#define CAN_MCR_IDAM_MASK   (0x300U)
 
#define CAN_MCR_IDAM_SHIFT   (8U)
 
#define CAN_MCR_IDAM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
 
#define CAN_MCR_AEN_MASK   (0x1000U)
 
#define CAN_MCR_AEN_SHIFT   (12U)
 
#define CAN_MCR_AEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
 
#define CAN_MCR_LPRIOEN_MASK   (0x2000U)
 
#define CAN_MCR_LPRIOEN_SHIFT   (13U)
 
#define CAN_MCR_LPRIOEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
 
#define CAN_MCR_DMA_MASK   (0x8000U)
 
#define CAN_MCR_DMA_SHIFT   (15U)
 
#define CAN_MCR_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
 
#define CAN_MCR_IRMQ_MASK   (0x10000U)
 
#define CAN_MCR_IRMQ_SHIFT   (16U)
 
#define CAN_MCR_IRMQ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
 
#define CAN_MCR_SRXDIS_MASK   (0x20000U)
 
#define CAN_MCR_SRXDIS_SHIFT   (17U)
 
#define CAN_MCR_SRXDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
 
#define CAN_MCR_DOZE_MASK   (0x40000U)
 
#define CAN_MCR_DOZE_SHIFT   (18U)
 
#define CAN_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
 
#define CAN_MCR_WAKSRC_MASK   (0x80000U)
 
#define CAN_MCR_WAKSRC_SHIFT   (19U)
 
#define CAN_MCR_WAKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
 
#define CAN_MCR_LPMACK_MASK   (0x100000U)
 
#define CAN_MCR_LPMACK_SHIFT   (20U)
 
#define CAN_MCR_LPMACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
 
#define CAN_MCR_WRNEN_MASK   (0x200000U)
 
#define CAN_MCR_WRNEN_SHIFT   (21U)
 
#define CAN_MCR_WRNEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
 
#define CAN_MCR_SLFWAK_MASK   (0x400000U)
 
#define CAN_MCR_SLFWAK_SHIFT   (22U)
 
#define CAN_MCR_SLFWAK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
 
#define CAN_MCR_SUPV_MASK   (0x800000U)
 
#define CAN_MCR_SUPV_SHIFT   (23U)
 
#define CAN_MCR_SUPV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
 
#define CAN_MCR_FRZACK_MASK   (0x1000000U)
 
#define CAN_MCR_FRZACK_SHIFT   (24U)
 
#define CAN_MCR_FRZACK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
 
#define CAN_MCR_SOFTRST_MASK   (0x2000000U)
 
#define CAN_MCR_SOFTRST_SHIFT   (25U)
 
#define CAN_MCR_SOFTRST(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
 
#define CAN_MCR_WAKMSK_MASK   (0x4000000U)
 
#define CAN_MCR_WAKMSK_SHIFT   (26U)
 
#define CAN_MCR_WAKMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
 
#define CAN_MCR_NOTRDY_MASK   (0x8000000U)
 
#define CAN_MCR_NOTRDY_SHIFT   (27U)
 
#define CAN_MCR_NOTRDY(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
 
#define CAN_MCR_HALT_MASK   (0x10000000U)
 
#define CAN_MCR_HALT_SHIFT   (28U)
 
#define CAN_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
 
#define CAN_MCR_RFEN_MASK   (0x20000000U)
 
#define CAN_MCR_RFEN_SHIFT   (29U)
 
#define CAN_MCR_RFEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
 
#define CAN_MCR_FRZ_MASK   (0x40000000U)
 
#define CAN_MCR_FRZ_SHIFT   (30U)
 
#define CAN_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
 
#define CAN_MCR_MDIS_MASK   (0x80000000U)
 
#define CAN_MCR_MDIS_SHIFT   (31U)
 
#define CAN_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
 
#define SPI_MCR_HALT_MASK   (0x1U)
 
#define SPI_MCR_HALT_SHIFT   (0U)
 
#define SPI_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
 
#define SPI_MCR_SMPL_PT_MASK   (0x300U)
 
#define SPI_MCR_SMPL_PT_SHIFT   (8U)
 
#define SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
 
#define SPI_MCR_CLR_RXF_MASK   (0x400U)
 
#define SPI_MCR_CLR_RXF_SHIFT   (10U)
 
#define SPI_MCR_CLR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
 
#define SPI_MCR_CLR_TXF_MASK   (0x800U)
 
#define SPI_MCR_CLR_TXF_SHIFT   (11U)
 
#define SPI_MCR_CLR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
 
#define SPI_MCR_DIS_RXF_MASK   (0x1000U)
 
#define SPI_MCR_DIS_RXF_SHIFT   (12U)
 
#define SPI_MCR_DIS_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
 
#define SPI_MCR_DIS_TXF_MASK   (0x2000U)
 
#define SPI_MCR_DIS_TXF_SHIFT   (13U)
 
#define SPI_MCR_DIS_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
 
#define SPI_MCR_MDIS_MASK   (0x4000U)
 
#define SPI_MCR_MDIS_SHIFT   (14U)
 
#define SPI_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
 
#define SPI_MCR_DOZE_MASK   (0x8000U)
 
#define SPI_MCR_DOZE_SHIFT   (15U)
 
#define SPI_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
 
#define SPI_MCR_PCSIS_MASK   (0x3F0000U)
 
#define SPI_MCR_PCSIS_SHIFT   (16U)
 
#define SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
 
#define SPI_MCR_ROOE_MASK   (0x1000000U)
 
#define SPI_MCR_ROOE_SHIFT   (24U)
 
#define SPI_MCR_ROOE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
 
#define SPI_MCR_PCSSE_MASK   (0x2000000U)
 
#define SPI_MCR_PCSSE_SHIFT   (25U)
 
#define SPI_MCR_PCSSE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
 
#define SPI_MCR_MTFE_MASK   (0x4000000U)
 
#define SPI_MCR_MTFE_SHIFT   (26U)
 
#define SPI_MCR_MTFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
 
#define SPI_MCR_FRZ_MASK   (0x8000000U)
 
#define SPI_MCR_FRZ_SHIFT   (27U)
 
#define SPI_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
 
#define SPI_MCR_DCONF_MASK   (0x30000000U)
 
#define SPI_MCR_DCONF_SHIFT   (28U)
 
#define SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
 
#define SPI_MCR_CONT_SCKE_MASK   (0x40000000U)
 
#define SPI_MCR_CONT_SCKE_SHIFT   (30U)
 
#define SPI_MCR_CONT_SCKE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
 
#define SPI_MCR_MSTR_MASK   (0x80000000U)
 
#define SPI_MCR_MSTR_SHIFT   (31U)
 
#define SPI_MCR_MSTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
 
#define SPI_MCR_HALT_MASK   0x1u
 
#define SPI_MCR_HALT_SHIFT   0
 
#define SPI_MCR_SMPL_PT_MASK   0x300u
 
#define SPI_MCR_SMPL_PT_SHIFT   8
 
#define SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
 
#define SPI_MCR_CLR_RXF_MASK   0x400u
 
#define SPI_MCR_CLR_RXF_SHIFT   10
 
#define SPI_MCR_CLR_TXF_MASK   0x800u
 
#define SPI_MCR_CLR_TXF_SHIFT   11
 
#define SPI_MCR_DIS_RXF_MASK   0x1000u
 
#define SPI_MCR_DIS_RXF_SHIFT   12
 
#define SPI_MCR_DIS_TXF_MASK   0x2000u
 
#define SPI_MCR_DIS_TXF_SHIFT   13
 
#define SPI_MCR_MDIS_MASK   0x4000u
 
#define SPI_MCR_MDIS_SHIFT   14
 
#define SPI_MCR_DOZE_MASK   0x8000u
 
#define SPI_MCR_DOZE_SHIFT   15
 
#define SPI_MCR_PCSIS_MASK   0x3F0000u
 
#define SPI_MCR_PCSIS_SHIFT   16
 
#define SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
 
#define SPI_MCR_ROOE_MASK   0x1000000u
 
#define SPI_MCR_ROOE_SHIFT   24
 
#define SPI_MCR_PCSSE_MASK   0x2000000u
 
#define SPI_MCR_PCSSE_SHIFT   25
 
#define SPI_MCR_MTFE_MASK   0x4000000u
 
#define SPI_MCR_MTFE_SHIFT   26
 
#define SPI_MCR_FRZ_MASK   0x8000000u
 
#define SPI_MCR_FRZ_SHIFT   27
 
#define SPI_MCR_DCONF_MASK   0x30000000u
 
#define SPI_MCR_DCONF_SHIFT   28
 
#define SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
 
#define SPI_MCR_CONT_SCKE_MASK   0x40000000u
 
#define SPI_MCR_CONT_SCKE_SHIFT   30
 
#define SPI_MCR_MSTR_MASK   0x80000000u
 
#define SPI_MCR_MSTR_SHIFT   31
 
#define SPI_MCR_HALT_MASK   (0x1U)
 
#define SPI_MCR_HALT_SHIFT   (0U)
 
#define SPI_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
 
#define SPI_MCR_SMPL_PT_MASK   (0x300U)
 
#define SPI_MCR_SMPL_PT_SHIFT   (8U)
 
#define SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
 
#define SPI_MCR_CLR_RXF_MASK   (0x400U)
 
#define SPI_MCR_CLR_RXF_SHIFT   (10U)
 
#define SPI_MCR_CLR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
 
#define SPI_MCR_CLR_TXF_MASK   (0x800U)
 
#define SPI_MCR_CLR_TXF_SHIFT   (11U)
 
#define SPI_MCR_CLR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
 
#define SPI_MCR_DIS_RXF_MASK   (0x1000U)
 
#define SPI_MCR_DIS_RXF_SHIFT   (12U)
 
#define SPI_MCR_DIS_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
 
#define SPI_MCR_DIS_TXF_MASK   (0x2000U)
 
#define SPI_MCR_DIS_TXF_SHIFT   (13U)
 
#define SPI_MCR_DIS_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
 
#define SPI_MCR_MDIS_MASK   (0x4000U)
 
#define SPI_MCR_MDIS_SHIFT   (14U)
 
#define SPI_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
 
#define SPI_MCR_DOZE_MASK   (0x8000U)
 
#define SPI_MCR_DOZE_SHIFT   (15U)
 
#define SPI_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
 
#define SPI_MCR_PCSIS_MASK   (0x3F0000U)
 
#define SPI_MCR_PCSIS_SHIFT   (16U)
 
#define SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
 
#define SPI_MCR_ROOE_MASK   (0x1000000U)
 
#define SPI_MCR_ROOE_SHIFT   (24U)
 
#define SPI_MCR_ROOE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
 
#define SPI_MCR_PCSSE_MASK   (0x2000000U)
 
#define SPI_MCR_PCSSE_SHIFT   (25U)
 
#define SPI_MCR_PCSSE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
 
#define SPI_MCR_MTFE_MASK   (0x4000000U)
 
#define SPI_MCR_MTFE_SHIFT   (26U)
 
#define SPI_MCR_MTFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
 
#define SPI_MCR_FRZ_MASK   (0x8000000U)
 
#define SPI_MCR_FRZ_SHIFT   (27U)
 
#define SPI_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
 
#define SPI_MCR_DCONF_MASK   (0x30000000U)
 
#define SPI_MCR_DCONF_SHIFT   (28U)
 
#define SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
 
#define SPI_MCR_CONT_SCKE_MASK   (0x40000000U)
 
#define SPI_MCR_CONT_SCKE_SHIFT   (30U)
 
#define SPI_MCR_CONT_SCKE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
 
#define SPI_MCR_MSTR_MASK   (0x80000000U)
 
#define SPI_MCR_MSTR_SHIFT   (31U)
 
#define SPI_MCR_MSTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
 
#define SPI_MCR_HALT_MASK   (0x1U)
 
#define SPI_MCR_HALT_SHIFT   (0U)
 
#define SPI_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
 
#define SPI_MCR_SMPL_PT_MASK   (0x300U)
 
#define SPI_MCR_SMPL_PT_SHIFT   (8U)
 
#define SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
 
#define SPI_MCR_CLR_RXF_MASK   (0x400U)
 
#define SPI_MCR_CLR_RXF_SHIFT   (10U)
 
#define SPI_MCR_CLR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
 
#define SPI_MCR_CLR_TXF_MASK   (0x800U)
 
#define SPI_MCR_CLR_TXF_SHIFT   (11U)
 
#define SPI_MCR_CLR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
 
#define SPI_MCR_DIS_RXF_MASK   (0x1000U)
 
#define SPI_MCR_DIS_RXF_SHIFT   (12U)
 
#define SPI_MCR_DIS_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
 
#define SPI_MCR_DIS_TXF_MASK   (0x2000U)
 
#define SPI_MCR_DIS_TXF_SHIFT   (13U)
 
#define SPI_MCR_DIS_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
 
#define SPI_MCR_MDIS_MASK   (0x4000U)
 
#define SPI_MCR_MDIS_SHIFT   (14U)
 
#define SPI_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
 
#define SPI_MCR_DOZE_MASK   (0x8000U)
 
#define SPI_MCR_DOZE_SHIFT   (15U)
 
#define SPI_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
 
#define SPI_MCR_PCSIS_MASK   (0x3F0000U)
 
#define SPI_MCR_PCSIS_SHIFT   (16U)
 
#define SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
 
#define SPI_MCR_ROOE_MASK   (0x1000000U)
 
#define SPI_MCR_ROOE_SHIFT   (24U)
 
#define SPI_MCR_ROOE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
 
#define SPI_MCR_PCSSE_MASK   (0x2000000U)
 
#define SPI_MCR_PCSSE_SHIFT   (25U)
 
#define SPI_MCR_PCSSE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
 
#define SPI_MCR_MTFE_MASK   (0x4000000U)
 
#define SPI_MCR_MTFE_SHIFT   (26U)
 
#define SPI_MCR_MTFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
 
#define SPI_MCR_FRZ_MASK   (0x8000000U)
 
#define SPI_MCR_FRZ_SHIFT   (27U)
 
#define SPI_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
 
#define SPI_MCR_DCONF_MASK   (0x30000000U)
 
#define SPI_MCR_DCONF_SHIFT   (28U)
 
#define SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
 
#define SPI_MCR_CONT_SCKE_MASK   (0x40000000U)
 
#define SPI_MCR_CONT_SCKE_SHIFT   (30U)
 
#define SPI_MCR_CONT_SCKE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
 
#define SPI_MCR_MSTR_MASK   (0x80000000U)
 
#define SPI_MCR_MSTR_SHIFT   (31U)
 
#define SPI_MCR_MSTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
 
#define SPI_MCR_HALT_MASK   (0x1U)
 
#define SPI_MCR_HALT_SHIFT   (0U)
 
#define SPI_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
 
#define SPI_MCR_SMPL_PT_MASK   (0x300U)
 
#define SPI_MCR_SMPL_PT_SHIFT   (8U)
 
#define SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
 
#define SPI_MCR_CLR_RXF_MASK   (0x400U)
 
#define SPI_MCR_CLR_RXF_SHIFT   (10U)
 
#define SPI_MCR_CLR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
 
#define SPI_MCR_CLR_TXF_MASK   (0x800U)
 
#define SPI_MCR_CLR_TXF_SHIFT   (11U)
 
#define SPI_MCR_CLR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
 
#define SPI_MCR_DIS_RXF_MASK   (0x1000U)
 
#define SPI_MCR_DIS_RXF_SHIFT   (12U)
 
#define SPI_MCR_DIS_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
 
#define SPI_MCR_DIS_TXF_MASK   (0x2000U)
 
#define SPI_MCR_DIS_TXF_SHIFT   (13U)
 
#define SPI_MCR_DIS_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
 
#define SPI_MCR_MDIS_MASK   (0x4000U)
 
#define SPI_MCR_MDIS_SHIFT   (14U)
 
#define SPI_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
 
#define SPI_MCR_DOZE_MASK   (0x8000U)
 
#define SPI_MCR_DOZE_SHIFT   (15U)
 
#define SPI_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
 
#define SPI_MCR_PCSIS_MASK   (0x3F0000U)
 
#define SPI_MCR_PCSIS_SHIFT   (16U)
 
#define SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
 
#define SPI_MCR_ROOE_MASK   (0x1000000U)
 
#define SPI_MCR_ROOE_SHIFT   (24U)
 
#define SPI_MCR_ROOE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
 
#define SPI_MCR_PCSSE_MASK   (0x2000000U)
 
#define SPI_MCR_PCSSE_SHIFT   (25U)
 
#define SPI_MCR_PCSSE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
 
#define SPI_MCR_MTFE_MASK   (0x4000000U)
 
#define SPI_MCR_MTFE_SHIFT   (26U)
 
#define SPI_MCR_MTFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
 
#define SPI_MCR_FRZ_MASK   (0x8000000U)
 
#define SPI_MCR_FRZ_SHIFT   (27U)
 
#define SPI_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
 
#define SPI_MCR_DCONF_MASK   (0x30000000U)
 
#define SPI_MCR_DCONF_SHIFT   (28U)
 
#define SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
 
#define SPI_MCR_CONT_SCKE_MASK   (0x40000000U)
 
#define SPI_MCR_CONT_SCKE_SHIFT   (30U)
 
#define SPI_MCR_CONT_SCKE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
 
#define SPI_MCR_MSTR_MASK   (0x80000000U)
 
#define SPI_MCR_MSTR_SHIFT   (31U)
 
#define SPI_MCR_MSTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
 
#define SPI_MCR_HALT_MASK   (0x1U)
 
#define SPI_MCR_HALT_SHIFT   (0U)
 
#define SPI_MCR_HALT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
 
#define SPI_MCR_SMPL_PT_MASK   (0x300U)
 
#define SPI_MCR_SMPL_PT_SHIFT   (8U)
 
#define SPI_MCR_SMPL_PT(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
 
#define SPI_MCR_CLR_RXF_MASK   (0x400U)
 
#define SPI_MCR_CLR_RXF_SHIFT   (10U)
 
#define SPI_MCR_CLR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
 
#define SPI_MCR_CLR_TXF_MASK   (0x800U)
 
#define SPI_MCR_CLR_TXF_SHIFT   (11U)
 
#define SPI_MCR_CLR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
 
#define SPI_MCR_DIS_RXF_MASK   (0x1000U)
 
#define SPI_MCR_DIS_RXF_SHIFT   (12U)
 
#define SPI_MCR_DIS_RXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
 
#define SPI_MCR_DIS_TXF_MASK   (0x2000U)
 
#define SPI_MCR_DIS_TXF_SHIFT   (13U)
 
#define SPI_MCR_DIS_TXF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
 
#define SPI_MCR_MDIS_MASK   (0x4000U)
 
#define SPI_MCR_MDIS_SHIFT   (14U)
 
#define SPI_MCR_MDIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
 
#define SPI_MCR_DOZE_MASK   (0x8000U)
 
#define SPI_MCR_DOZE_SHIFT   (15U)
 
#define SPI_MCR_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
 
#define SPI_MCR_PCSIS_MASK   (0x3F0000U)
 
#define SPI_MCR_PCSIS_SHIFT   (16U)
 
#define SPI_MCR_PCSIS(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
 
#define SPI_MCR_ROOE_MASK   (0x1000000U)
 
#define SPI_MCR_ROOE_SHIFT   (24U)
 
#define SPI_MCR_ROOE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
 
#define SPI_MCR_PCSSE_MASK   (0x2000000U)
 
#define SPI_MCR_PCSSE_SHIFT   (25U)
 
#define SPI_MCR_PCSSE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
 
#define SPI_MCR_MTFE_MASK   (0x4000000U)
 
#define SPI_MCR_MTFE_SHIFT   (26U)
 
#define SPI_MCR_MTFE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
 
#define SPI_MCR_FRZ_MASK   (0x8000000U)
 
#define SPI_MCR_FRZ_SHIFT   (27U)
 
#define SPI_MCR_FRZ(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
 
#define SPI_MCR_DCONF_MASK   (0x30000000U)
 
#define SPI_MCR_DCONF_SHIFT   (28U)
 
#define SPI_MCR_DCONF(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
 
#define SPI_MCR_CONT_SCKE_MASK   (0x40000000U)
 
#define SPI_MCR_CONT_SCKE_SHIFT   (30U)
 
#define SPI_MCR_CONT_SCKE(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
 
#define SPI_MCR_MSTR_MASK   (0x80000000U)
 
#define SPI_MCR_MSTR_SHIFT   (31U)
 
#define SPI_MCR_MSTR(x)   (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
 

CTRL1 - Control 1 register

#define CAN_CTRL1_PROPSEG_MASK   (0x7U)
 
#define CAN_CTRL1_PROPSEG_SHIFT   (0U)
 
#define CAN_CTRL1_PROPSEG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
 
#define CAN_CTRL1_LOM_MASK   (0x8U)
 
#define CAN_CTRL1_LOM_SHIFT   (3U)
 
#define CAN_CTRL1_LOM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
 
#define CAN_CTRL1_LBUF_MASK   (0x10U)
 
#define CAN_CTRL1_LBUF_SHIFT   (4U)
 
#define CAN_CTRL1_LBUF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
 
#define CAN_CTRL1_TSYN_MASK   (0x20U)
 
#define CAN_CTRL1_TSYN_SHIFT   (5U)
 
#define CAN_CTRL1_TSYN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
 
#define CAN_CTRL1_BOFFREC_MASK   (0x40U)
 
#define CAN_CTRL1_BOFFREC_SHIFT   (6U)
 
#define CAN_CTRL1_BOFFREC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
 
#define CAN_CTRL1_SMP_MASK   (0x80U)
 
#define CAN_CTRL1_SMP_SHIFT   (7U)
 
#define CAN_CTRL1_SMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
 
#define CAN_CTRL1_RWRNMSK_MASK   (0x400U)
 
#define CAN_CTRL1_RWRNMSK_SHIFT   (10U)
 
#define CAN_CTRL1_RWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
 
#define CAN_CTRL1_TWRNMSK_MASK   (0x800U)
 
#define CAN_CTRL1_TWRNMSK_SHIFT   (11U)
 
#define CAN_CTRL1_TWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
 
#define CAN_CTRL1_LPB_MASK   (0x1000U)
 
#define CAN_CTRL1_LPB_SHIFT   (12U)
 
#define CAN_CTRL1_LPB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
 
#define CAN_CTRL1_CLKSRC_MASK   (0x2000U)
 
#define CAN_CTRL1_CLKSRC_SHIFT   (13U)
 
#define CAN_CTRL1_CLKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
 
#define CAN_CTRL1_ERRMSK_MASK   (0x4000U)
 
#define CAN_CTRL1_ERRMSK_SHIFT   (14U)
 
#define CAN_CTRL1_ERRMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
 
#define CAN_CTRL1_BOFFMSK_MASK   (0x8000U)
 
#define CAN_CTRL1_BOFFMSK_SHIFT   (15U)
 
#define CAN_CTRL1_BOFFMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
 
#define CAN_CTRL1_PSEG2_MASK   (0x70000U)
 
#define CAN_CTRL1_PSEG2_SHIFT   (16U)
 
#define CAN_CTRL1_PSEG2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
 
#define CAN_CTRL1_PSEG1_MASK   (0x380000U)
 
#define CAN_CTRL1_PSEG1_SHIFT   (19U)
 
#define CAN_CTRL1_PSEG1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
 
#define CAN_CTRL1_RJW_MASK   (0xC00000U)
 
#define CAN_CTRL1_RJW_SHIFT   (22U)
 
#define CAN_CTRL1_RJW(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
 
#define CAN_CTRL1_PRESDIV_MASK   (0xFF000000U)
 
#define CAN_CTRL1_PRESDIV_SHIFT   (24U)
 
#define CAN_CTRL1_PRESDIV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
 
#define CAN_CTRL1_PROPSEG_MASK   0x7u
 
#define CAN_CTRL1_PROPSEG_SHIFT   0
 
#define CAN_CTRL1_PROPSEG(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
 
#define CAN_CTRL1_LOM_MASK   0x8u
 
#define CAN_CTRL1_LOM_SHIFT   3
 
#define CAN_CTRL1_LBUF_MASK   0x10u
 
#define CAN_CTRL1_LBUF_SHIFT   4
 
#define CAN_CTRL1_TSYN_MASK   0x20u
 
#define CAN_CTRL1_TSYN_SHIFT   5
 
#define CAN_CTRL1_BOFFREC_MASK   0x40u
 
#define CAN_CTRL1_BOFFREC_SHIFT   6
 
#define CAN_CTRL1_SMP_MASK   0x80u
 
#define CAN_CTRL1_SMP_SHIFT   7
 
#define CAN_CTRL1_RWRNMSK_MASK   0x400u
 
#define CAN_CTRL1_RWRNMSK_SHIFT   10
 
#define CAN_CTRL1_TWRNMSK_MASK   0x800u
 
#define CAN_CTRL1_TWRNMSK_SHIFT   11
 
#define CAN_CTRL1_LPB_MASK   0x1000u
 
#define CAN_CTRL1_LPB_SHIFT   12
 
#define CAN_CTRL1_CLKSRC_MASK   0x2000u
 
#define CAN_CTRL1_CLKSRC_SHIFT   13
 
#define CAN_CTRL1_ERRMSK_MASK   0x4000u
 
#define CAN_CTRL1_ERRMSK_SHIFT   14
 
#define CAN_CTRL1_BOFFMSK_MASK   0x8000u
 
#define CAN_CTRL1_BOFFMSK_SHIFT   15
 
#define CAN_CTRL1_PSEG2_MASK   0x70000u
 
#define CAN_CTRL1_PSEG2_SHIFT   16
 
#define CAN_CTRL1_PSEG2(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
 
#define CAN_CTRL1_PSEG1_MASK   0x380000u
 
#define CAN_CTRL1_PSEG1_SHIFT   19
 
#define CAN_CTRL1_PSEG1(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
 
#define CAN_CTRL1_RJW_MASK   0xC00000u
 
#define CAN_CTRL1_RJW_SHIFT   22
 
#define CAN_CTRL1_RJW(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
 
#define CAN_CTRL1_PRESDIV_MASK   0xFF000000u
 
#define CAN_CTRL1_PRESDIV_SHIFT   24
 
#define CAN_CTRL1_PRESDIV(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
 
#define CAN_CTRL1_PROPSEG_MASK   (0x7U)
 
#define CAN_CTRL1_PROPSEG_SHIFT   (0U)
 
#define CAN_CTRL1_PROPSEG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
 
#define CAN_CTRL1_LOM_MASK   (0x8U)
 
#define CAN_CTRL1_LOM_SHIFT   (3U)
 
#define CAN_CTRL1_LOM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
 
#define CAN_CTRL1_LBUF_MASK   (0x10U)
 
#define CAN_CTRL1_LBUF_SHIFT   (4U)
 
#define CAN_CTRL1_LBUF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
 
#define CAN_CTRL1_TSYN_MASK   (0x20U)
 
#define CAN_CTRL1_TSYN_SHIFT   (5U)
 
#define CAN_CTRL1_TSYN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
 
#define CAN_CTRL1_BOFFREC_MASK   (0x40U)
 
#define CAN_CTRL1_BOFFREC_SHIFT   (6U)
 
#define CAN_CTRL1_BOFFREC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
 
#define CAN_CTRL1_SMP_MASK   (0x80U)
 
#define CAN_CTRL1_SMP_SHIFT   (7U)
 
#define CAN_CTRL1_SMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
 
#define CAN_CTRL1_RWRNMSK_MASK   (0x400U)
 
#define CAN_CTRL1_RWRNMSK_SHIFT   (10U)
 
#define CAN_CTRL1_RWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
 
#define CAN_CTRL1_TWRNMSK_MASK   (0x800U)
 
#define CAN_CTRL1_TWRNMSK_SHIFT   (11U)
 
#define CAN_CTRL1_TWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
 
#define CAN_CTRL1_LPB_MASK   (0x1000U)
 
#define CAN_CTRL1_LPB_SHIFT   (12U)
 
#define CAN_CTRL1_LPB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
 
#define CAN_CTRL1_CLKSRC_MASK   (0x2000U)
 
#define CAN_CTRL1_CLKSRC_SHIFT   (13U)
 
#define CAN_CTRL1_CLKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
 
#define CAN_CTRL1_ERRMSK_MASK   (0x4000U)
 
#define CAN_CTRL1_ERRMSK_SHIFT   (14U)
 
#define CAN_CTRL1_ERRMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
 
#define CAN_CTRL1_BOFFMSK_MASK   (0x8000U)
 
#define CAN_CTRL1_BOFFMSK_SHIFT   (15U)
 
#define CAN_CTRL1_BOFFMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
 
#define CAN_CTRL1_PSEG2_MASK   (0x70000U)
 
#define CAN_CTRL1_PSEG2_SHIFT   (16U)
 
#define CAN_CTRL1_PSEG2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
 
#define CAN_CTRL1_PSEG1_MASK   (0x380000U)
 
#define CAN_CTRL1_PSEG1_SHIFT   (19U)
 
#define CAN_CTRL1_PSEG1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
 
#define CAN_CTRL1_RJW_MASK   (0xC00000U)
 
#define CAN_CTRL1_RJW_SHIFT   (22U)
 
#define CAN_CTRL1_RJW(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
 
#define CAN_CTRL1_PRESDIV_MASK   (0xFF000000U)
 
#define CAN_CTRL1_PRESDIV_SHIFT   (24U)
 
#define CAN_CTRL1_PRESDIV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
 
#define CAN_CTRL1_PROPSEG_MASK   (0x7U)
 
#define CAN_CTRL1_PROPSEG_SHIFT   (0U)
 
#define CAN_CTRL1_PROPSEG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
 
#define CAN_CTRL1_LOM_MASK   (0x8U)
 
#define CAN_CTRL1_LOM_SHIFT   (3U)
 
#define CAN_CTRL1_LOM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
 
#define CAN_CTRL1_LBUF_MASK   (0x10U)
 
#define CAN_CTRL1_LBUF_SHIFT   (4U)
 
#define CAN_CTRL1_LBUF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
 
#define CAN_CTRL1_TSYN_MASK   (0x20U)
 
#define CAN_CTRL1_TSYN_SHIFT   (5U)
 
#define CAN_CTRL1_TSYN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
 
#define CAN_CTRL1_BOFFREC_MASK   (0x40U)
 
#define CAN_CTRL1_BOFFREC_SHIFT   (6U)
 
#define CAN_CTRL1_BOFFREC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
 
#define CAN_CTRL1_SMP_MASK   (0x80U)
 
#define CAN_CTRL1_SMP_SHIFT   (7U)
 
#define CAN_CTRL1_SMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
 
#define CAN_CTRL1_RWRNMSK_MASK   (0x400U)
 
#define CAN_CTRL1_RWRNMSK_SHIFT   (10U)
 
#define CAN_CTRL1_RWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
 
#define CAN_CTRL1_TWRNMSK_MASK   (0x800U)
 
#define CAN_CTRL1_TWRNMSK_SHIFT   (11U)
 
#define CAN_CTRL1_TWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
 
#define CAN_CTRL1_LPB_MASK   (0x1000U)
 
#define CAN_CTRL1_LPB_SHIFT   (12U)
 
#define CAN_CTRL1_LPB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
 
#define CAN_CTRL1_CLKSRC_MASK   (0x2000U)
 
#define CAN_CTRL1_CLKSRC_SHIFT   (13U)
 
#define CAN_CTRL1_CLKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
 
#define CAN_CTRL1_ERRMSK_MASK   (0x4000U)
 
#define CAN_CTRL1_ERRMSK_SHIFT   (14U)
 
#define CAN_CTRL1_ERRMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
 
#define CAN_CTRL1_BOFFMSK_MASK   (0x8000U)
 
#define CAN_CTRL1_BOFFMSK_SHIFT   (15U)
 
#define CAN_CTRL1_BOFFMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
 
#define CAN_CTRL1_PSEG2_MASK   (0x70000U)
 
#define CAN_CTRL1_PSEG2_SHIFT   (16U)
 
#define CAN_CTRL1_PSEG2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
 
#define CAN_CTRL1_PSEG1_MASK   (0x380000U)
 
#define CAN_CTRL1_PSEG1_SHIFT   (19U)
 
#define CAN_CTRL1_PSEG1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
 
#define CAN_CTRL1_RJW_MASK   (0xC00000U)
 
#define CAN_CTRL1_RJW_SHIFT   (22U)
 
#define CAN_CTRL1_RJW(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
 
#define CAN_CTRL1_PRESDIV_MASK   (0xFF000000U)
 
#define CAN_CTRL1_PRESDIV_SHIFT   (24U)
 
#define CAN_CTRL1_PRESDIV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
 
#define CAN_CTRL1_PROPSEG_MASK   (0x7U)
 
#define CAN_CTRL1_PROPSEG_SHIFT   (0U)
 
#define CAN_CTRL1_PROPSEG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
 
#define CAN_CTRL1_LOM_MASK   (0x8U)
 
#define CAN_CTRL1_LOM_SHIFT   (3U)
 
#define CAN_CTRL1_LOM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
 
#define CAN_CTRL1_LBUF_MASK   (0x10U)
 
#define CAN_CTRL1_LBUF_SHIFT   (4U)
 
#define CAN_CTRL1_LBUF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
 
#define CAN_CTRL1_TSYN_MASK   (0x20U)
 
#define CAN_CTRL1_TSYN_SHIFT   (5U)
 
#define CAN_CTRL1_TSYN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
 
#define CAN_CTRL1_BOFFREC_MASK   (0x40U)
 
#define CAN_CTRL1_BOFFREC_SHIFT   (6U)
 
#define CAN_CTRL1_BOFFREC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
 
#define CAN_CTRL1_SMP_MASK   (0x80U)
 
#define CAN_CTRL1_SMP_SHIFT   (7U)
 
#define CAN_CTRL1_SMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
 
#define CAN_CTRL1_RWRNMSK_MASK   (0x400U)
 
#define CAN_CTRL1_RWRNMSK_SHIFT   (10U)
 
#define CAN_CTRL1_RWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
 
#define CAN_CTRL1_TWRNMSK_MASK   (0x800U)
 
#define CAN_CTRL1_TWRNMSK_SHIFT   (11U)
 
#define CAN_CTRL1_TWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
 
#define CAN_CTRL1_LPB_MASK   (0x1000U)
 
#define CAN_CTRL1_LPB_SHIFT   (12U)
 
#define CAN_CTRL1_LPB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
 
#define CAN_CTRL1_CLKSRC_MASK   (0x2000U)
 
#define CAN_CTRL1_CLKSRC_SHIFT   (13U)
 
#define CAN_CTRL1_CLKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
 
#define CAN_CTRL1_ERRMSK_MASK   (0x4000U)
 
#define CAN_CTRL1_ERRMSK_SHIFT   (14U)
 
#define CAN_CTRL1_ERRMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
 
#define CAN_CTRL1_BOFFMSK_MASK   (0x8000U)
 
#define CAN_CTRL1_BOFFMSK_SHIFT   (15U)
 
#define CAN_CTRL1_BOFFMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
 
#define CAN_CTRL1_PSEG2_MASK   (0x70000U)
 
#define CAN_CTRL1_PSEG2_SHIFT   (16U)
 
#define CAN_CTRL1_PSEG2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
 
#define CAN_CTRL1_PSEG1_MASK   (0x380000U)
 
#define CAN_CTRL1_PSEG1_SHIFT   (19U)
 
#define CAN_CTRL1_PSEG1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
 
#define CAN_CTRL1_RJW_MASK   (0xC00000U)
 
#define CAN_CTRL1_RJW_SHIFT   (22U)
 
#define CAN_CTRL1_RJW(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
 
#define CAN_CTRL1_PRESDIV_MASK   (0xFF000000U)
 
#define CAN_CTRL1_PRESDIV_SHIFT   (24U)
 
#define CAN_CTRL1_PRESDIV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
 
#define CAN_CTRL1_PROPSEG_MASK   (0x7U)
 
#define CAN_CTRL1_PROPSEG_SHIFT   (0U)
 
#define CAN_CTRL1_PROPSEG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
 
#define CAN_CTRL1_LOM_MASK   (0x8U)
 
#define CAN_CTRL1_LOM_SHIFT   (3U)
 
#define CAN_CTRL1_LOM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
 
#define CAN_CTRL1_LBUF_MASK   (0x10U)
 
#define CAN_CTRL1_LBUF_SHIFT   (4U)
 
#define CAN_CTRL1_LBUF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
 
#define CAN_CTRL1_TSYN_MASK   (0x20U)
 
#define CAN_CTRL1_TSYN_SHIFT   (5U)
 
#define CAN_CTRL1_TSYN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
 
#define CAN_CTRL1_BOFFREC_MASK   (0x40U)
 
#define CAN_CTRL1_BOFFREC_SHIFT   (6U)
 
#define CAN_CTRL1_BOFFREC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
 
#define CAN_CTRL1_SMP_MASK   (0x80U)
 
#define CAN_CTRL1_SMP_SHIFT   (7U)
 
#define CAN_CTRL1_SMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
 
#define CAN_CTRL1_RWRNMSK_MASK   (0x400U)
 
#define CAN_CTRL1_RWRNMSK_SHIFT   (10U)
 
#define CAN_CTRL1_RWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
 
#define CAN_CTRL1_TWRNMSK_MASK   (0x800U)
 
#define CAN_CTRL1_TWRNMSK_SHIFT   (11U)
 
#define CAN_CTRL1_TWRNMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
 
#define CAN_CTRL1_LPB_MASK   (0x1000U)
 
#define CAN_CTRL1_LPB_SHIFT   (12U)
 
#define CAN_CTRL1_LPB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
 
#define CAN_CTRL1_CLKSRC_MASK   (0x2000U)
 
#define CAN_CTRL1_CLKSRC_SHIFT   (13U)
 
#define CAN_CTRL1_CLKSRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
 
#define CAN_CTRL1_ERRMSK_MASK   (0x4000U)
 
#define CAN_CTRL1_ERRMSK_SHIFT   (14U)
 
#define CAN_CTRL1_ERRMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
 
#define CAN_CTRL1_BOFFMSK_MASK   (0x8000U)
 
#define CAN_CTRL1_BOFFMSK_SHIFT   (15U)
 
#define CAN_CTRL1_BOFFMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
 
#define CAN_CTRL1_PSEG2_MASK   (0x70000U)
 
#define CAN_CTRL1_PSEG2_SHIFT   (16U)
 
#define CAN_CTRL1_PSEG2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
 
#define CAN_CTRL1_PSEG1_MASK   (0x380000U)
 
#define CAN_CTRL1_PSEG1_SHIFT   (19U)
 
#define CAN_CTRL1_PSEG1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
 
#define CAN_CTRL1_RJW_MASK   (0xC00000U)
 
#define CAN_CTRL1_RJW_SHIFT   (22U)
 
#define CAN_CTRL1_RJW(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
 
#define CAN_CTRL1_PRESDIV_MASK   (0xFF000000U)
 
#define CAN_CTRL1_PRESDIV_SHIFT   (24U)
 
#define CAN_CTRL1_PRESDIV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
 

TIMER - Free Running Timer

#define CAN_TIMER_TIMER_MASK   (0xFFFFU)
 
#define CAN_TIMER_TIMER_SHIFT   (0U)
 
#define CAN_TIMER_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
 
#define CAN_TIMER_TIMER_MASK   0xFFFFu
 
#define CAN_TIMER_TIMER_SHIFT   0
 
#define CAN_TIMER_TIMER(x)   (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
 
#define CAN_TIMER_TIMER_MASK   (0xFFFFU)
 
#define CAN_TIMER_TIMER_SHIFT   (0U)
 
#define CAN_TIMER_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
 
#define CAN_TIMER_TIMER_MASK   (0xFFFFU)
 
#define CAN_TIMER_TIMER_SHIFT   (0U)
 
#define CAN_TIMER_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
 
#define CAN_TIMER_TIMER_MASK   (0xFFFFU)
 
#define CAN_TIMER_TIMER_SHIFT   (0U)
 
#define CAN_TIMER_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
 
#define CAN_TIMER_TIMER_MASK   (0xFFFFU)
 
#define CAN_TIMER_TIMER_SHIFT   (0U)
 
#define CAN_TIMER_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
 

RXMGMASK - Rx Mailboxes Global Mask Register

#define CAN_RXMGMASK_MG_MASK   (0xFFFFFFFFU)
 
#define CAN_RXMGMASK_MG_SHIFT   (0U)
 
#define CAN_RXMGMASK_MG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
 
#define CAN_RXMGMASK_MG_MASK   0xFFFFFFFFu
 
#define CAN_RXMGMASK_MG_SHIFT   0
 
#define CAN_RXMGMASK_MG(x)   (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
 
#define CAN_RXMGMASK_MG_MASK   (0xFFFFFFFFU)
 
#define CAN_RXMGMASK_MG_SHIFT   (0U)
 
#define CAN_RXMGMASK_MG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
 
#define CAN_RXMGMASK_MG_MASK   (0xFFFFFFFFU)
 
#define CAN_RXMGMASK_MG_SHIFT   (0U)
 
#define CAN_RXMGMASK_MG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
 
#define CAN_RXMGMASK_MG_MASK   (0xFFFFFFFFU)
 
#define CAN_RXMGMASK_MG_SHIFT   (0U)
 
#define CAN_RXMGMASK_MG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
 
#define CAN_RXMGMASK_MG_MASK   (0xFFFFFFFFU)
 
#define CAN_RXMGMASK_MG_SHIFT   (0U)
 
#define CAN_RXMGMASK_MG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
 

RX14MASK - Rx 14 Mask register

#define CAN_RX14MASK_RX14M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX14MASK_RX14M_SHIFT   (0U)
 
#define CAN_RX14MASK_RX14M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
 
#define CAN_RX14MASK_RX14M_MASK   0xFFFFFFFFu
 
#define CAN_RX14MASK_RX14M_SHIFT   0
 
#define CAN_RX14MASK_RX14M(x)   (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
 
#define CAN_RX14MASK_RX14M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX14MASK_RX14M_SHIFT   (0U)
 
#define CAN_RX14MASK_RX14M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
 
#define CAN_RX14MASK_RX14M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX14MASK_RX14M_SHIFT   (0U)
 
#define CAN_RX14MASK_RX14M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
 
#define CAN_RX14MASK_RX14M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX14MASK_RX14M_SHIFT   (0U)
 
#define CAN_RX14MASK_RX14M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
 
#define CAN_RX14MASK_RX14M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX14MASK_RX14M_SHIFT   (0U)
 
#define CAN_RX14MASK_RX14M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
 

RX15MASK - Rx 15 Mask register

#define CAN_RX15MASK_RX15M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX15MASK_RX15M_SHIFT   (0U)
 
#define CAN_RX15MASK_RX15M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
 
#define CAN_RX15MASK_RX15M_MASK   0xFFFFFFFFu
 
#define CAN_RX15MASK_RX15M_SHIFT   0
 
#define CAN_RX15MASK_RX15M(x)   (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
 
#define CAN_RX15MASK_RX15M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX15MASK_RX15M_SHIFT   (0U)
 
#define CAN_RX15MASK_RX15M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
 
#define CAN_RX15MASK_RX15M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX15MASK_RX15M_SHIFT   (0U)
 
#define CAN_RX15MASK_RX15M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
 
#define CAN_RX15MASK_RX15M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX15MASK_RX15M_SHIFT   (0U)
 
#define CAN_RX15MASK_RX15M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
 
#define CAN_RX15MASK_RX15M_MASK   (0xFFFFFFFFU)
 
#define CAN_RX15MASK_RX15M_SHIFT   (0U)
 
#define CAN_RX15MASK_RX15M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
 

ECR - Error Counter

#define CAN_ECR_TXERRCNT_MASK   (0xFFU)
 
#define CAN_ECR_TXERRCNT_SHIFT   (0U)
 
#define CAN_ECR_TXERRCNT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
 
#define CAN_ECR_RXERRCNT_MASK   (0xFF00U)
 
#define CAN_ECR_RXERRCNT_SHIFT   (8U)
 
#define CAN_ECR_RXERRCNT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
 
#define CAN_ECR_TXERRCNT_MASK   0xFFu
 
#define CAN_ECR_TXERRCNT_SHIFT   0
 
#define CAN_ECR_TXERRCNT(x)   (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
 
#define CAN_ECR_RXERRCNT_MASK   0xFF00u
 
#define CAN_ECR_RXERRCNT_SHIFT   8
 
#define CAN_ECR_RXERRCNT(x)   (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
 
#define CAN_ECR_TXERRCNT_MASK   (0xFFU)
 
#define CAN_ECR_TXERRCNT_SHIFT   (0U)
 
#define CAN_ECR_TXERRCNT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
 
#define CAN_ECR_RXERRCNT_MASK   (0xFF00U)
 
#define CAN_ECR_RXERRCNT_SHIFT   (8U)
 
#define CAN_ECR_RXERRCNT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
 
#define CAN_ECR_TXERRCNT_MASK   (0xFFU)
 
#define CAN_ECR_TXERRCNT_SHIFT   (0U)
 
#define CAN_ECR_TXERRCNT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
 
#define CAN_ECR_RXERRCNT_MASK   (0xFF00U)
 
#define CAN_ECR_RXERRCNT_SHIFT   (8U)
 
#define CAN_ECR_RXERRCNT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
 
#define CAN_ECR_TXERRCNT_MASK   (0xFFU)
 
#define CAN_ECR_TXERRCNT_SHIFT   (0U)
 
#define CAN_ECR_TXERRCNT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
 
#define CAN_ECR_RXERRCNT_MASK   (0xFF00U)
 
#define CAN_ECR_RXERRCNT_SHIFT   (8U)
 
#define CAN_ECR_RXERRCNT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
 
#define CAN_ECR_TXERRCNT_MASK   (0xFFU)
 
#define CAN_ECR_TXERRCNT_SHIFT   (0U)
 
#define CAN_ECR_TXERRCNT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
 
#define CAN_ECR_RXERRCNT_MASK   (0xFF00U)
 
#define CAN_ECR_RXERRCNT_SHIFT   (8U)
 
#define CAN_ECR_RXERRCNT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
 

ESR1 - Error and Status 1 register

#define CAN_ESR1_WAKINT_MASK   (0x1U)
 
#define CAN_ESR1_WAKINT_SHIFT   (0U)
 
#define CAN_ESR1_WAKINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
 
#define CAN_ESR1_ERRINT_MASK   (0x2U)
 
#define CAN_ESR1_ERRINT_SHIFT   (1U)
 
#define CAN_ESR1_ERRINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
 
#define CAN_ESR1_BOFFINT_MASK   (0x4U)
 
#define CAN_ESR1_BOFFINT_SHIFT   (2U)
 
#define CAN_ESR1_BOFFINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
 
#define CAN_ESR1_RX_MASK   (0x8U)
 
#define CAN_ESR1_RX_SHIFT   (3U)
 
#define CAN_ESR1_RX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
 
#define CAN_ESR1_FLTCONF_MASK   (0x30U)
 
#define CAN_ESR1_FLTCONF_SHIFT   (4U)
 
#define CAN_ESR1_FLTCONF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
 
#define CAN_ESR1_TX_MASK   (0x40U)
 
#define CAN_ESR1_TX_SHIFT   (6U)
 
#define CAN_ESR1_TX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
 
#define CAN_ESR1_IDLE_MASK   (0x80U)
 
#define CAN_ESR1_IDLE_SHIFT   (7U)
 
#define CAN_ESR1_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
 
#define CAN_ESR1_RXWRN_MASK   (0x100U)
 
#define CAN_ESR1_RXWRN_SHIFT   (8U)
 
#define CAN_ESR1_RXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
 
#define CAN_ESR1_TXWRN_MASK   (0x200U)
 
#define CAN_ESR1_TXWRN_SHIFT   (9U)
 
#define CAN_ESR1_TXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
 
#define CAN_ESR1_STFERR_MASK   (0x400U)
 
#define CAN_ESR1_STFERR_SHIFT   (10U)
 
#define CAN_ESR1_STFERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
 
#define CAN_ESR1_FRMERR_MASK   (0x800U)
 
#define CAN_ESR1_FRMERR_SHIFT   (11U)
 
#define CAN_ESR1_FRMERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
 
#define CAN_ESR1_CRCERR_MASK   (0x1000U)
 
#define CAN_ESR1_CRCERR_SHIFT   (12U)
 
#define CAN_ESR1_CRCERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
 
#define CAN_ESR1_ACKERR_MASK   (0x2000U)
 
#define CAN_ESR1_ACKERR_SHIFT   (13U)
 
#define CAN_ESR1_ACKERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
 
#define CAN_ESR1_BIT0ERR_MASK   (0x4000U)
 
#define CAN_ESR1_BIT0ERR_SHIFT   (14U)
 
#define CAN_ESR1_BIT0ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
 
#define CAN_ESR1_BIT1ERR_MASK   (0x8000U)
 
#define CAN_ESR1_BIT1ERR_SHIFT   (15U)
 
#define CAN_ESR1_BIT1ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
 
#define CAN_ESR1_RWRNINT_MASK   (0x10000U)
 
#define CAN_ESR1_RWRNINT_SHIFT   (16U)
 
#define CAN_ESR1_RWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
 
#define CAN_ESR1_TWRNINT_MASK   (0x20000U)
 
#define CAN_ESR1_TWRNINT_SHIFT   (17U)
 
#define CAN_ESR1_TWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
 
#define CAN_ESR1_SYNCH_MASK   (0x40000U)
 
#define CAN_ESR1_SYNCH_SHIFT   (18U)
 
#define CAN_ESR1_SYNCH(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
 
#define CAN_ESR1_WAKINT_MASK   0x1u
 
#define CAN_ESR1_WAKINT_SHIFT   0
 
#define CAN_ESR1_ERRINT_MASK   0x2u
 
#define CAN_ESR1_ERRINT_SHIFT   1
 
#define CAN_ESR1_BOFFINT_MASK   0x4u
 
#define CAN_ESR1_BOFFINT_SHIFT   2
 
#define CAN_ESR1_RX_MASK   0x8u
 
#define CAN_ESR1_RX_SHIFT   3
 
#define CAN_ESR1_FLTCONF_MASK   0x30u
 
#define CAN_ESR1_FLTCONF_SHIFT   4
 
#define CAN_ESR1_FLTCONF(x)   (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
 
#define CAN_ESR1_TX_MASK   0x40u
 
#define CAN_ESR1_TX_SHIFT   6
 
#define CAN_ESR1_IDLE_MASK   0x80u
 
#define CAN_ESR1_IDLE_SHIFT   7
 
#define CAN_ESR1_RXWRN_MASK   0x100u
 
#define CAN_ESR1_RXWRN_SHIFT   8
 
#define CAN_ESR1_TXWRN_MASK   0x200u
 
#define CAN_ESR1_TXWRN_SHIFT   9
 
#define CAN_ESR1_STFERR_MASK   0x400u
 
#define CAN_ESR1_STFERR_SHIFT   10
 
#define CAN_ESR1_FRMERR_MASK   0x800u
 
#define CAN_ESR1_FRMERR_SHIFT   11
 
#define CAN_ESR1_CRCERR_MASK   0x1000u
 
#define CAN_ESR1_CRCERR_SHIFT   12
 
#define CAN_ESR1_ACKERR_MASK   0x2000u
 
#define CAN_ESR1_ACKERR_SHIFT   13
 
#define CAN_ESR1_BIT0ERR_MASK   0x4000u
 
#define CAN_ESR1_BIT0ERR_SHIFT   14
 
#define CAN_ESR1_BIT1ERR_MASK   0x8000u
 
#define CAN_ESR1_BIT1ERR_SHIFT   15
 
#define CAN_ESR1_RWRNINT_MASK   0x10000u
 
#define CAN_ESR1_RWRNINT_SHIFT   16
 
#define CAN_ESR1_TWRNINT_MASK   0x20000u
 
#define CAN_ESR1_TWRNINT_SHIFT   17
 
#define CAN_ESR1_SYNCH_MASK   0x40000u
 
#define CAN_ESR1_SYNCH_SHIFT   18
 
#define CAN_ESR1_WAKINT_MASK   (0x1U)
 
#define CAN_ESR1_WAKINT_SHIFT   (0U)
 
#define CAN_ESR1_WAKINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
 
#define CAN_ESR1_ERRINT_MASK   (0x2U)
 
#define CAN_ESR1_ERRINT_SHIFT   (1U)
 
#define CAN_ESR1_ERRINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
 
#define CAN_ESR1_BOFFINT_MASK   (0x4U)
 
#define CAN_ESR1_BOFFINT_SHIFT   (2U)
 
#define CAN_ESR1_BOFFINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
 
#define CAN_ESR1_RX_MASK   (0x8U)
 
#define CAN_ESR1_RX_SHIFT   (3U)
 
#define CAN_ESR1_RX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
 
#define CAN_ESR1_FLTCONF_MASK   (0x30U)
 
#define CAN_ESR1_FLTCONF_SHIFT   (4U)
 
#define CAN_ESR1_FLTCONF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
 
#define CAN_ESR1_TX_MASK   (0x40U)
 
#define CAN_ESR1_TX_SHIFT   (6U)
 
#define CAN_ESR1_TX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
 
#define CAN_ESR1_IDLE_MASK   (0x80U)
 
#define CAN_ESR1_IDLE_SHIFT   (7U)
 
#define CAN_ESR1_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
 
#define CAN_ESR1_RXWRN_MASK   (0x100U)
 
#define CAN_ESR1_RXWRN_SHIFT   (8U)
 
#define CAN_ESR1_RXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
 
#define CAN_ESR1_TXWRN_MASK   (0x200U)
 
#define CAN_ESR1_TXWRN_SHIFT   (9U)
 
#define CAN_ESR1_TXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
 
#define CAN_ESR1_STFERR_MASK   (0x400U)
 
#define CAN_ESR1_STFERR_SHIFT   (10U)
 
#define CAN_ESR1_STFERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
 
#define CAN_ESR1_FRMERR_MASK   (0x800U)
 
#define CAN_ESR1_FRMERR_SHIFT   (11U)
 
#define CAN_ESR1_FRMERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
 
#define CAN_ESR1_CRCERR_MASK   (0x1000U)
 
#define CAN_ESR1_CRCERR_SHIFT   (12U)
 
#define CAN_ESR1_CRCERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
 
#define CAN_ESR1_ACKERR_MASK   (0x2000U)
 
#define CAN_ESR1_ACKERR_SHIFT   (13U)
 
#define CAN_ESR1_ACKERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
 
#define CAN_ESR1_BIT0ERR_MASK   (0x4000U)
 
#define CAN_ESR1_BIT0ERR_SHIFT   (14U)
 
#define CAN_ESR1_BIT0ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
 
#define CAN_ESR1_BIT1ERR_MASK   (0x8000U)
 
#define CAN_ESR1_BIT1ERR_SHIFT   (15U)
 
#define CAN_ESR1_BIT1ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
 
#define CAN_ESR1_RWRNINT_MASK   (0x10000U)
 
#define CAN_ESR1_RWRNINT_SHIFT   (16U)
 
#define CAN_ESR1_RWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
 
#define CAN_ESR1_TWRNINT_MASK   (0x20000U)
 
#define CAN_ESR1_TWRNINT_SHIFT   (17U)
 
#define CAN_ESR1_TWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
 
#define CAN_ESR1_SYNCH_MASK   (0x40000U)
 
#define CAN_ESR1_SYNCH_SHIFT   (18U)
 
#define CAN_ESR1_SYNCH(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
 
#define CAN_ESR1_WAKINT_MASK   (0x1U)
 
#define CAN_ESR1_WAKINT_SHIFT   (0U)
 
#define CAN_ESR1_WAKINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
 
#define CAN_ESR1_ERRINT_MASK   (0x2U)
 
#define CAN_ESR1_ERRINT_SHIFT   (1U)
 
#define CAN_ESR1_ERRINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
 
#define CAN_ESR1_BOFFINT_MASK   (0x4U)
 
#define CAN_ESR1_BOFFINT_SHIFT   (2U)
 
#define CAN_ESR1_BOFFINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
 
#define CAN_ESR1_RX_MASK   (0x8U)
 
#define CAN_ESR1_RX_SHIFT   (3U)
 
#define CAN_ESR1_RX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
 
#define CAN_ESR1_FLTCONF_MASK   (0x30U)
 
#define CAN_ESR1_FLTCONF_SHIFT   (4U)
 
#define CAN_ESR1_FLTCONF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
 
#define CAN_ESR1_TX_MASK   (0x40U)
 
#define CAN_ESR1_TX_SHIFT   (6U)
 
#define CAN_ESR1_TX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
 
#define CAN_ESR1_IDLE_MASK   (0x80U)
 
#define CAN_ESR1_IDLE_SHIFT   (7U)
 
#define CAN_ESR1_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
 
#define CAN_ESR1_RXWRN_MASK   (0x100U)
 
#define CAN_ESR1_RXWRN_SHIFT   (8U)
 
#define CAN_ESR1_RXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
 
#define CAN_ESR1_TXWRN_MASK   (0x200U)
 
#define CAN_ESR1_TXWRN_SHIFT   (9U)
 
#define CAN_ESR1_TXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
 
#define CAN_ESR1_STFERR_MASK   (0x400U)
 
#define CAN_ESR1_STFERR_SHIFT   (10U)
 
#define CAN_ESR1_STFERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
 
#define CAN_ESR1_FRMERR_MASK   (0x800U)
 
#define CAN_ESR1_FRMERR_SHIFT   (11U)
 
#define CAN_ESR1_FRMERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
 
#define CAN_ESR1_CRCERR_MASK   (0x1000U)
 
#define CAN_ESR1_CRCERR_SHIFT   (12U)
 
#define CAN_ESR1_CRCERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
 
#define CAN_ESR1_ACKERR_MASK   (0x2000U)
 
#define CAN_ESR1_ACKERR_SHIFT   (13U)
 
#define CAN_ESR1_ACKERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
 
#define CAN_ESR1_BIT0ERR_MASK   (0x4000U)
 
#define CAN_ESR1_BIT0ERR_SHIFT   (14U)
 
#define CAN_ESR1_BIT0ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
 
#define CAN_ESR1_BIT1ERR_MASK   (0x8000U)
 
#define CAN_ESR1_BIT1ERR_SHIFT   (15U)
 
#define CAN_ESR1_BIT1ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
 
#define CAN_ESR1_RWRNINT_MASK   (0x10000U)
 
#define CAN_ESR1_RWRNINT_SHIFT   (16U)
 
#define CAN_ESR1_RWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
 
#define CAN_ESR1_TWRNINT_MASK   (0x20000U)
 
#define CAN_ESR1_TWRNINT_SHIFT   (17U)
 
#define CAN_ESR1_TWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
 
#define CAN_ESR1_SYNCH_MASK   (0x40000U)
 
#define CAN_ESR1_SYNCH_SHIFT   (18U)
 
#define CAN_ESR1_SYNCH(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
 
#define CAN_ESR1_WAKINT_MASK   (0x1U)
 
#define CAN_ESR1_WAKINT_SHIFT   (0U)
 
#define CAN_ESR1_WAKINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
 
#define CAN_ESR1_ERRINT_MASK   (0x2U)
 
#define CAN_ESR1_ERRINT_SHIFT   (1U)
 
#define CAN_ESR1_ERRINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
 
#define CAN_ESR1_BOFFINT_MASK   (0x4U)
 
#define CAN_ESR1_BOFFINT_SHIFT   (2U)
 
#define CAN_ESR1_BOFFINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
 
#define CAN_ESR1_RX_MASK   (0x8U)
 
#define CAN_ESR1_RX_SHIFT   (3U)
 
#define CAN_ESR1_RX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
 
#define CAN_ESR1_FLTCONF_MASK   (0x30U)
 
#define CAN_ESR1_FLTCONF_SHIFT   (4U)
 
#define CAN_ESR1_FLTCONF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
 
#define CAN_ESR1_TX_MASK   (0x40U)
 
#define CAN_ESR1_TX_SHIFT   (6U)
 
#define CAN_ESR1_TX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
 
#define CAN_ESR1_IDLE_MASK   (0x80U)
 
#define CAN_ESR1_IDLE_SHIFT   (7U)
 
#define CAN_ESR1_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
 
#define CAN_ESR1_RXWRN_MASK   (0x100U)
 
#define CAN_ESR1_RXWRN_SHIFT   (8U)
 
#define CAN_ESR1_RXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
 
#define CAN_ESR1_TXWRN_MASK   (0x200U)
 
#define CAN_ESR1_TXWRN_SHIFT   (9U)
 
#define CAN_ESR1_TXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
 
#define CAN_ESR1_STFERR_MASK   (0x400U)
 
#define CAN_ESR1_STFERR_SHIFT   (10U)
 
#define CAN_ESR1_STFERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
 
#define CAN_ESR1_FRMERR_MASK   (0x800U)
 
#define CAN_ESR1_FRMERR_SHIFT   (11U)
 
#define CAN_ESR1_FRMERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
 
#define CAN_ESR1_CRCERR_MASK   (0x1000U)
 
#define CAN_ESR1_CRCERR_SHIFT   (12U)
 
#define CAN_ESR1_CRCERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
 
#define CAN_ESR1_ACKERR_MASK   (0x2000U)
 
#define CAN_ESR1_ACKERR_SHIFT   (13U)
 
#define CAN_ESR1_ACKERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
 
#define CAN_ESR1_BIT0ERR_MASK   (0x4000U)
 
#define CAN_ESR1_BIT0ERR_SHIFT   (14U)
 
#define CAN_ESR1_BIT0ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
 
#define CAN_ESR1_BIT1ERR_MASK   (0x8000U)
 
#define CAN_ESR1_BIT1ERR_SHIFT   (15U)
 
#define CAN_ESR1_BIT1ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
 
#define CAN_ESR1_RWRNINT_MASK   (0x10000U)
 
#define CAN_ESR1_RWRNINT_SHIFT   (16U)
 
#define CAN_ESR1_RWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
 
#define CAN_ESR1_TWRNINT_MASK   (0x20000U)
 
#define CAN_ESR1_TWRNINT_SHIFT   (17U)
 
#define CAN_ESR1_TWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
 
#define CAN_ESR1_SYNCH_MASK   (0x40000U)
 
#define CAN_ESR1_SYNCH_SHIFT   (18U)
 
#define CAN_ESR1_SYNCH(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
 
#define CAN_ESR1_WAKINT_MASK   (0x1U)
 
#define CAN_ESR1_WAKINT_SHIFT   (0U)
 
#define CAN_ESR1_WAKINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
 
#define CAN_ESR1_ERRINT_MASK   (0x2U)
 
#define CAN_ESR1_ERRINT_SHIFT   (1U)
 
#define CAN_ESR1_ERRINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
 
#define CAN_ESR1_BOFFINT_MASK   (0x4U)
 
#define CAN_ESR1_BOFFINT_SHIFT   (2U)
 
#define CAN_ESR1_BOFFINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
 
#define CAN_ESR1_RX_MASK   (0x8U)
 
#define CAN_ESR1_RX_SHIFT   (3U)
 
#define CAN_ESR1_RX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
 
#define CAN_ESR1_FLTCONF_MASK   (0x30U)
 
#define CAN_ESR1_FLTCONF_SHIFT   (4U)
 
#define CAN_ESR1_FLTCONF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
 
#define CAN_ESR1_TX_MASK   (0x40U)
 
#define CAN_ESR1_TX_SHIFT   (6U)
 
#define CAN_ESR1_TX(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
 
#define CAN_ESR1_IDLE_MASK   (0x80U)
 
#define CAN_ESR1_IDLE_SHIFT   (7U)
 
#define CAN_ESR1_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
 
#define CAN_ESR1_RXWRN_MASK   (0x100U)
 
#define CAN_ESR1_RXWRN_SHIFT   (8U)
 
#define CAN_ESR1_RXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
 
#define CAN_ESR1_TXWRN_MASK   (0x200U)
 
#define CAN_ESR1_TXWRN_SHIFT   (9U)
 
#define CAN_ESR1_TXWRN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
 
#define CAN_ESR1_STFERR_MASK   (0x400U)
 
#define CAN_ESR1_STFERR_SHIFT   (10U)
 
#define CAN_ESR1_STFERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
 
#define CAN_ESR1_FRMERR_MASK   (0x800U)
 
#define CAN_ESR1_FRMERR_SHIFT   (11U)
 
#define CAN_ESR1_FRMERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
 
#define CAN_ESR1_CRCERR_MASK   (0x1000U)
 
#define CAN_ESR1_CRCERR_SHIFT   (12U)
 
#define CAN_ESR1_CRCERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
 
#define CAN_ESR1_ACKERR_MASK   (0x2000U)
 
#define CAN_ESR1_ACKERR_SHIFT   (13U)
 
#define CAN_ESR1_ACKERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
 
#define CAN_ESR1_BIT0ERR_MASK   (0x4000U)
 
#define CAN_ESR1_BIT0ERR_SHIFT   (14U)
 
#define CAN_ESR1_BIT0ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
 
#define CAN_ESR1_BIT1ERR_MASK   (0x8000U)
 
#define CAN_ESR1_BIT1ERR_SHIFT   (15U)
 
#define CAN_ESR1_BIT1ERR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
 
#define CAN_ESR1_RWRNINT_MASK   (0x10000U)
 
#define CAN_ESR1_RWRNINT_SHIFT   (16U)
 
#define CAN_ESR1_RWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
 
#define CAN_ESR1_TWRNINT_MASK   (0x20000U)
 
#define CAN_ESR1_TWRNINT_SHIFT   (17U)
 
#define CAN_ESR1_TWRNINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
 
#define CAN_ESR1_SYNCH_MASK   (0x40000U)
 
#define CAN_ESR1_SYNCH_SHIFT   (18U)
 
#define CAN_ESR1_SYNCH(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
 
#define CAN_ESR1_BOFFDONEINT_MASK   (0x80000U)
 
#define CAN_ESR1_BOFFDONEINT_SHIFT   (19U)
 
#define CAN_ESR1_BOFFDONEINT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
 
#define CAN_ESR1_ERROVR_MASK   (0x200000U)
 
#define CAN_ESR1_ERROVR_SHIFT   (21U)
 
#define CAN_ESR1_ERROVR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
 

IMASK1 - Interrupt Masks 1 register

#define CAN_IMASK1_BUFLM_MASK   (0xFFFFFFFFU)
 
#define CAN_IMASK1_BUFLM_SHIFT   (0U)
 
#define CAN_IMASK1_BUFLM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
 
#define CAN_IMASK1_BUFLM_MASK   0xFFFFFFFFu
 
#define CAN_IMASK1_BUFLM_SHIFT   0
 
#define CAN_IMASK1_BUFLM(x)   (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
 
#define CAN_IMASK1_BUFLM_MASK   (0xFFFFFFFFU)
 
#define CAN_IMASK1_BUFLM_SHIFT   (0U)
 
#define CAN_IMASK1_BUFLM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
 
#define CAN_IMASK1_BUFLM_MASK   (0xFFFFFFFFU)
 
#define CAN_IMASK1_BUFLM_SHIFT   (0U)
 
#define CAN_IMASK1_BUFLM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
 
#define CAN_IMASK1_BUFLM_MASK   (0xFFFFFFFFU)
 
#define CAN_IMASK1_BUFLM_SHIFT   (0U)
 
#define CAN_IMASK1_BUFLM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
 

IFLAG1 - Interrupt Flags 1 register

#define CAN_IFLAG1_BUF4TO0I_MASK   (0x1FU)
 
#define CAN_IFLAG1_BUF4TO0I_SHIFT   (0U)
 
#define CAN_IFLAG1_BUF4TO0I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
 

IFLAG1 - Interrupt Flags 1 register

#define CAN_IFLAG1_BUF5I_MASK   (0x20U)
 
#define CAN_IFLAG1_BUF5I_SHIFT   (5U)
 
#define CAN_IFLAG1_BUF5I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
 
#define CAN_IFLAG1_BUF6I_MASK   (0x40U)
 
#define CAN_IFLAG1_BUF6I_SHIFT   (6U)
 
#define CAN_IFLAG1_BUF6I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
 
#define CAN_IFLAG1_BUF7I_MASK   (0x80U)
 
#define CAN_IFLAG1_BUF7I_SHIFT   (7U)
 
#define CAN_IFLAG1_BUF7I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
 
#define CAN_IFLAG1_BUF31TO8I_MASK   (0xFFFFFF00U)
 
#define CAN_IFLAG1_BUF31TO8I_SHIFT   (8U)
 
#define CAN_IFLAG1_BUF31TO8I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
 
#define CAN_IFLAG1_BUF5I_MASK   0x20u
 
#define CAN_IFLAG1_BUF5I_SHIFT   5
 
#define CAN_IFLAG1_BUF6I_MASK   0x40u
 
#define CAN_IFLAG1_BUF6I_SHIFT   6
 
#define CAN_IFLAG1_BUF7I_MASK   0x80u
 
#define CAN_IFLAG1_BUF7I_SHIFT   7
 
#define CAN_IFLAG1_BUF31TO8I_MASK   0xFFFFFF00u
 
#define CAN_IFLAG1_BUF31TO8I_SHIFT   8
 
#define CAN_IFLAG1_BUF31TO8I(x)   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
 
#define CAN_IFLAG1_BUF0I_MASK   (0x1U)
 
#define CAN_IFLAG1_BUF0I_SHIFT   (0U)
 
#define CAN_IFLAG1_BUF0I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
 
#define CAN_IFLAG1_BUF4TO1I_MASK   (0x1EU)
 
#define CAN_IFLAG1_BUF4TO1I_SHIFT   (1U)
 
#define CAN_IFLAG1_BUF4TO1I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
 
#define CAN_IFLAG1_BUF5I_MASK   (0x20U)
 
#define CAN_IFLAG1_BUF5I_SHIFT   (5U)
 
#define CAN_IFLAG1_BUF5I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
 
#define CAN_IFLAG1_BUF6I_MASK   (0x40U)
 
#define CAN_IFLAG1_BUF6I_SHIFT   (6U)
 
#define CAN_IFLAG1_BUF6I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
 
#define CAN_IFLAG1_BUF7I_MASK   (0x80U)
 
#define CAN_IFLAG1_BUF7I_SHIFT   (7U)
 
#define CAN_IFLAG1_BUF7I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
 
#define CAN_IFLAG1_BUF31TO8I_MASK   (0xFFFFFF00U)
 
#define CAN_IFLAG1_BUF31TO8I_SHIFT   (8U)
 
#define CAN_IFLAG1_BUF31TO8I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
 
#define CAN_IFLAG1_BUF0I_MASK   (0x1U)
 
#define CAN_IFLAG1_BUF0I_SHIFT   (0U)
 
#define CAN_IFLAG1_BUF0I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
 
#define CAN_IFLAG1_BUF4TO1I_MASK   (0x1EU)
 
#define CAN_IFLAG1_BUF4TO1I_SHIFT   (1U)
 
#define CAN_IFLAG1_BUF4TO1I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
 
#define CAN_IFLAG1_BUF5I_MASK   (0x20U)
 
#define CAN_IFLAG1_BUF5I_SHIFT   (5U)
 
#define CAN_IFLAG1_BUF5I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
 
#define CAN_IFLAG1_BUF6I_MASK   (0x40U)
 
#define CAN_IFLAG1_BUF6I_SHIFT   (6U)
 
#define CAN_IFLAG1_BUF6I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
 
#define CAN_IFLAG1_BUF7I_MASK   (0x80U)
 
#define CAN_IFLAG1_BUF7I_SHIFT   (7U)
 
#define CAN_IFLAG1_BUF7I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
 
#define CAN_IFLAG1_BUF31TO8I_MASK   (0xFFFFFF00U)
 
#define CAN_IFLAG1_BUF31TO8I_SHIFT   (8U)
 
#define CAN_IFLAG1_BUF31TO8I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
 
#define CAN_IFLAG1_BUF0I_MASK   (0x1U)
 
#define CAN_IFLAG1_BUF0I_SHIFT   (0U)
 
#define CAN_IFLAG1_BUF0I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
 
#define CAN_IFLAG1_BUF4TO1I_MASK   (0x1EU)
 
#define CAN_IFLAG1_BUF4TO1I_SHIFT   (1U)
 
#define CAN_IFLAG1_BUF4TO1I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
 
#define CAN_IFLAG1_BUF5I_MASK   (0x20U)
 
#define CAN_IFLAG1_BUF5I_SHIFT   (5U)
 
#define CAN_IFLAG1_BUF5I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
 
#define CAN_IFLAG1_BUF6I_MASK   (0x40U)
 
#define CAN_IFLAG1_BUF6I_SHIFT   (6U)
 
#define CAN_IFLAG1_BUF6I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
 
#define CAN_IFLAG1_BUF7I_MASK   (0x80U)
 
#define CAN_IFLAG1_BUF7I_SHIFT   (7U)
 
#define CAN_IFLAG1_BUF7I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
 
#define CAN_IFLAG1_BUF31TO8I_MASK   (0xFFFFFF00U)
 
#define CAN_IFLAG1_BUF31TO8I_SHIFT   (8U)
 
#define CAN_IFLAG1_BUF31TO8I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
 
#define CAN_IFLAG1_BUF0I_MASK   (0x1U)
 
#define CAN_IFLAG1_BUF0I_SHIFT   (0U)
 
#define CAN_IFLAG1_BUF0I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
 
#define CAN_IFLAG1_BUF4TO1I_MASK   (0x1EU)
 
#define CAN_IFLAG1_BUF4TO1I_SHIFT   (1U)
 
#define CAN_IFLAG1_BUF4TO1I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
 
#define CAN_IFLAG1_BUF5I_MASK   (0x20U)
 
#define CAN_IFLAG1_BUF5I_SHIFT   (5U)
 
#define CAN_IFLAG1_BUF5I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
 
#define CAN_IFLAG1_BUF6I_MASK   (0x40U)
 
#define CAN_IFLAG1_BUF6I_SHIFT   (6U)
 
#define CAN_IFLAG1_BUF6I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
 
#define CAN_IFLAG1_BUF7I_MASK   (0x80U)
 
#define CAN_IFLAG1_BUF7I_SHIFT   (7U)
 
#define CAN_IFLAG1_BUF7I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
 
#define CAN_IFLAG1_BUF31TO8I_MASK   (0xFFFFFF00U)
 
#define CAN_IFLAG1_BUF31TO8I_SHIFT   (8U)
 
#define CAN_IFLAG1_BUF31TO8I(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
 

CTRL2 - Control 2 register

#define CAN_CTRL2_EACEN_MASK   (0x10000U)
 
#define CAN_CTRL2_EACEN_SHIFT   (16U)
 
#define CAN_CTRL2_EACEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
 
#define CAN_CTRL2_RRS_MASK   (0x20000U)
 
#define CAN_CTRL2_RRS_SHIFT   (17U)
 
#define CAN_CTRL2_RRS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
 
#define CAN_CTRL2_MRP_MASK   (0x40000U)
 
#define CAN_CTRL2_MRP_SHIFT   (18U)
 
#define CAN_CTRL2_MRP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
 
#define CAN_CTRL2_TASD_MASK   (0xF80000U)
 
#define CAN_CTRL2_TASD_SHIFT   (19U)
 
#define CAN_CTRL2_TASD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
 
#define CAN_CTRL2_RFFN_MASK   (0xF000000U)
 
#define CAN_CTRL2_RFFN_SHIFT   (24U)
 
#define CAN_CTRL2_RFFN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
 
#define CAN_CTRL2_EACEN_MASK   0x10000u
 
#define CAN_CTRL2_EACEN_SHIFT   16
 
#define CAN_CTRL2_RRS_MASK   0x20000u
 
#define CAN_CTRL2_RRS_SHIFT   17
 
#define CAN_CTRL2_MRP_MASK   0x40000u
 
#define CAN_CTRL2_MRP_SHIFT   18
 
#define CAN_CTRL2_TASD_MASK   0xF80000u
 
#define CAN_CTRL2_TASD_SHIFT   19
 
#define CAN_CTRL2_TASD(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
 
#define CAN_CTRL2_RFFN_MASK   0xF000000u
 
#define CAN_CTRL2_RFFN_SHIFT   24
 
#define CAN_CTRL2_RFFN(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
 
#define CAN_CTRL2_EACEN_MASK   (0x10000U)
 
#define CAN_CTRL2_EACEN_SHIFT   (16U)
 
#define CAN_CTRL2_EACEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
 
#define CAN_CTRL2_RRS_MASK   (0x20000U)
 
#define CAN_CTRL2_RRS_SHIFT   (17U)
 
#define CAN_CTRL2_RRS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
 
#define CAN_CTRL2_MRP_MASK   (0x40000U)
 
#define CAN_CTRL2_MRP_SHIFT   (18U)
 
#define CAN_CTRL2_MRP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
 
#define CAN_CTRL2_TASD_MASK   (0xF80000U)
 
#define CAN_CTRL2_TASD_SHIFT   (19U)
 
#define CAN_CTRL2_TASD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
 
#define CAN_CTRL2_RFFN_MASK   (0xF000000U)
 
#define CAN_CTRL2_RFFN_SHIFT   (24U)
 
#define CAN_CTRL2_RFFN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
 
#define CAN_CTRL2_EACEN_MASK   (0x10000U)
 
#define CAN_CTRL2_EACEN_SHIFT   (16U)
 
#define CAN_CTRL2_EACEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
 
#define CAN_CTRL2_RRS_MASK   (0x20000U)
 
#define CAN_CTRL2_RRS_SHIFT   (17U)
 
#define CAN_CTRL2_RRS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
 
#define CAN_CTRL2_MRP_MASK   (0x40000U)
 
#define CAN_CTRL2_MRP_SHIFT   (18U)
 
#define CAN_CTRL2_MRP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
 
#define CAN_CTRL2_TASD_MASK   (0xF80000U)
 
#define CAN_CTRL2_TASD_SHIFT   (19U)
 
#define CAN_CTRL2_TASD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
 
#define CAN_CTRL2_RFFN_MASK   (0xF000000U)
 
#define CAN_CTRL2_RFFN_SHIFT   (24U)
 
#define CAN_CTRL2_RFFN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
 
#define CAN_CTRL2_EACEN_MASK   (0x10000U)
 
#define CAN_CTRL2_EACEN_SHIFT   (16U)
 
#define CAN_CTRL2_EACEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
 
#define CAN_CTRL2_RRS_MASK   (0x20000U)
 
#define CAN_CTRL2_RRS_SHIFT   (17U)
 
#define CAN_CTRL2_RRS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
 
#define CAN_CTRL2_MRP_MASK   (0x40000U)
 
#define CAN_CTRL2_MRP_SHIFT   (18U)
 
#define CAN_CTRL2_MRP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
 
#define CAN_CTRL2_TASD_MASK   (0xF80000U)
 
#define CAN_CTRL2_TASD_SHIFT   (19U)
 
#define CAN_CTRL2_TASD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
 
#define CAN_CTRL2_RFFN_MASK   (0xF000000U)
 
#define CAN_CTRL2_RFFN_SHIFT   (24U)
 
#define CAN_CTRL2_RFFN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
 
#define CAN_CTRL2_EACEN_MASK   (0x10000U)
 
#define CAN_CTRL2_EACEN_SHIFT   (16U)
 
#define CAN_CTRL2_EACEN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
 
#define CAN_CTRL2_RRS_MASK   (0x20000U)
 
#define CAN_CTRL2_RRS_SHIFT   (17U)
 
#define CAN_CTRL2_RRS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
 
#define CAN_CTRL2_MRP_MASK   (0x40000U)
 
#define CAN_CTRL2_MRP_SHIFT   (18U)
 
#define CAN_CTRL2_MRP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
 
#define CAN_CTRL2_TASD_MASK   (0xF80000U)
 
#define CAN_CTRL2_TASD_SHIFT   (19U)
 
#define CAN_CTRL2_TASD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
 
#define CAN_CTRL2_RFFN_MASK   (0xF000000U)
 
#define CAN_CTRL2_RFFN_SHIFT   (24U)
 
#define CAN_CTRL2_RFFN(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
 
#define CAN_CTRL2_BOFFDONEMSK_MASK   (0x40000000U)
 
#define CAN_CTRL2_BOFFDONEMSK_SHIFT   (30U)
 
#define CAN_CTRL2_BOFFDONEMSK(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
 
#define ENC_CTRL2_UPDHLD_MASK   (0x1U)
 
#define ENC_CTRL2_UPDHLD_SHIFT   (0U)
 
#define ENC_CTRL2_UPDHLD(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
 
#define ENC_CTRL2_UPDPOS_MASK   (0x2U)
 
#define ENC_CTRL2_UPDPOS_SHIFT   (1U)
 
#define ENC_CTRL2_UPDPOS(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
 
#define ENC_CTRL2_MOD_MASK   (0x4U)
 
#define ENC_CTRL2_MOD_SHIFT   (2U)
 
#define ENC_CTRL2_MOD(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
 
#define ENC_CTRL2_DIR_MASK   (0x8U)
 
#define ENC_CTRL2_DIR_SHIFT   (3U)
 
#define ENC_CTRL2_DIR(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
 
#define ENC_CTRL2_RUIE_MASK   (0x10U)
 
#define ENC_CTRL2_RUIE_SHIFT   (4U)
 
#define ENC_CTRL2_RUIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
 
#define ENC_CTRL2_RUIRQ_MASK   (0x20U)
 
#define ENC_CTRL2_RUIRQ_SHIFT   (5U)
 
#define ENC_CTRL2_RUIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
 
#define ENC_CTRL2_ROIE_MASK   (0x40U)
 
#define ENC_CTRL2_ROIE_SHIFT   (6U)
 
#define ENC_CTRL2_ROIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
 
#define ENC_CTRL2_ROIRQ_MASK   (0x80U)
 
#define ENC_CTRL2_ROIRQ_SHIFT   (7U)
 
#define ENC_CTRL2_ROIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
 
#define ENC_CTRL2_REVMOD_MASK   (0x100U)
 
#define ENC_CTRL2_REVMOD_SHIFT   (8U)
 
#define ENC_CTRL2_REVMOD(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
 
#define ENC_CTRL2_OUTCTL_MASK   (0x200U)
 
#define ENC_CTRL2_OUTCTL_SHIFT   (9U)
 
#define ENC_CTRL2_OUTCTL(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
 
#define ENC_CTRL2_SABIE_MASK   (0x400U)
 
#define ENC_CTRL2_SABIE_SHIFT   (10U)
 
#define ENC_CTRL2_SABIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
 
#define ENC_CTRL2_SABIRQ_MASK   (0x800U)
 
#define ENC_CTRL2_SABIRQ_SHIFT   (11U)
 
#define ENC_CTRL2_SABIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
 
#define PWM_CTRL2_CLK_SEL_MASK   (0x3U)
 
#define PWM_CTRL2_CLK_SEL_SHIFT   (0U)
 
#define PWM_CTRL2_CLK_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
 
#define PWM_CTRL2_RELOAD_SEL_MASK   (0x4U)
 
#define PWM_CTRL2_RELOAD_SEL_SHIFT   (2U)
 
#define PWM_CTRL2_RELOAD_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
 
#define PWM_CTRL2_FORCE_SEL_MASK   (0x38U)
 
#define PWM_CTRL2_FORCE_SEL_SHIFT   (3U)
 
#define PWM_CTRL2_FORCE_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
 
#define PWM_CTRL2_FORCE_MASK   (0x40U)
 
#define PWM_CTRL2_FORCE_SHIFT   (6U)
 
#define PWM_CTRL2_FORCE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
 
#define PWM_CTRL2_FRCEN_MASK   (0x80U)
 
#define PWM_CTRL2_FRCEN_SHIFT   (7U)
 
#define PWM_CTRL2_FRCEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
 
#define PWM_CTRL2_INIT_SEL_MASK   (0x300U)
 
#define PWM_CTRL2_INIT_SEL_SHIFT   (8U)
 
#define PWM_CTRL2_INIT_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
 
#define PWM_CTRL2_PWMX_INIT_MASK   (0x400U)
 
#define PWM_CTRL2_PWMX_INIT_SHIFT   (10U)
 
#define PWM_CTRL2_PWMX_INIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
 
#define PWM_CTRL2_PWM45_INIT_MASK   (0x800U)
 
#define PWM_CTRL2_PWM45_INIT_SHIFT   (11U)
 
#define PWM_CTRL2_PWM45_INIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
 
#define PWM_CTRL2_PWM23_INIT_MASK   (0x1000U)
 
#define PWM_CTRL2_PWM23_INIT_SHIFT   (12U)
 
#define PWM_CTRL2_PWM23_INIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
 
#define PWM_CTRL2_INDEP_MASK   (0x2000U)
 
#define PWM_CTRL2_INDEP_SHIFT   (13U)
 
#define PWM_CTRL2_INDEP(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
 
#define PWM_CTRL2_WAITEN_MASK   (0x4000U)
 
#define PWM_CTRL2_WAITEN_SHIFT   (14U)
 
#define PWM_CTRL2_WAITEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
 
#define PWM_CTRL2_DBGEN_MASK   (0x8000U)
 
#define PWM_CTRL2_DBGEN_SHIFT   (15U)
 
#define PWM_CTRL2_DBGEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
 

CTRL2 - Control 2 register

#define CAN_CTRL2_WRMFRZ_MASK   (0x10000000U)
 
#define CAN_CTRL2_WRMFRZ_SHIFT   (28U)
 
#define CAN_CTRL2_WRMFRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
 
#define CAN_CTRL2_WRMFRZ_MASK   0x10000000u
 
#define CAN_CTRL2_WRMFRZ_SHIFT   28
 
#define CAN_CTRL2_WRMFRZ_MASK   (0x10000000U)
 
#define CAN_CTRL2_WRMFRZ_SHIFT   (28U)
 
#define CAN_CTRL2_WRMFRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
 
#define CAN_CTRL2_WRMFRZ_MASK   (0x10000000U)
 
#define CAN_CTRL2_WRMFRZ_SHIFT   (28U)
 
#define CAN_CTRL2_WRMFRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
 
#define CAN_CTRL2_WRMFRZ_MASK   (0x10000000U)
 
#define CAN_CTRL2_WRMFRZ_SHIFT   (28U)
 
#define CAN_CTRL2_WRMFRZ(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
 

ESR2 - Error and Status 2 register

#define CAN_ESR2_IMB_MASK   (0x2000U)
 
#define CAN_ESR2_IMB_SHIFT   (13U)
 
#define CAN_ESR2_IMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
 
#define CAN_ESR2_VPS_MASK   (0x4000U)
 
#define CAN_ESR2_VPS_SHIFT   (14U)
 
#define CAN_ESR2_VPS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
 
#define CAN_ESR2_LPTM_MASK   (0x7F0000U)
 
#define CAN_ESR2_LPTM_SHIFT   (16U)
 
#define CAN_ESR2_LPTM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
 
#define CAN_ESR2_IMB_MASK   0x2000u
 
#define CAN_ESR2_IMB_SHIFT   13
 
#define CAN_ESR2_VPS_MASK   0x4000u
 
#define CAN_ESR2_VPS_SHIFT   14
 
#define CAN_ESR2_LPTM_MASK   0x7F0000u
 
#define CAN_ESR2_LPTM_SHIFT   16
 
#define CAN_ESR2_LPTM(x)   (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
 
#define CAN_ESR2_IMB_MASK   (0x2000U)
 
#define CAN_ESR2_IMB_SHIFT   (13U)
 
#define CAN_ESR2_IMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
 
#define CAN_ESR2_VPS_MASK   (0x4000U)
 
#define CAN_ESR2_VPS_SHIFT   (14U)
 
#define CAN_ESR2_VPS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
 
#define CAN_ESR2_LPTM_MASK   (0x7F0000U)
 
#define CAN_ESR2_LPTM_SHIFT   (16U)
 
#define CAN_ESR2_LPTM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
 
#define CAN_ESR2_IMB_MASK   (0x2000U)
 
#define CAN_ESR2_IMB_SHIFT   (13U)
 
#define CAN_ESR2_IMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
 
#define CAN_ESR2_VPS_MASK   (0x4000U)
 
#define CAN_ESR2_VPS_SHIFT   (14U)
 
#define CAN_ESR2_VPS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
 
#define CAN_ESR2_LPTM_MASK   (0x7F0000U)
 
#define CAN_ESR2_LPTM_SHIFT   (16U)
 
#define CAN_ESR2_LPTM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
 
#define CAN_ESR2_IMB_MASK   (0x2000U)
 
#define CAN_ESR2_IMB_SHIFT   (13U)
 
#define CAN_ESR2_IMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
 
#define CAN_ESR2_VPS_MASK   (0x4000U)
 
#define CAN_ESR2_VPS_SHIFT   (14U)
 
#define CAN_ESR2_VPS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
 
#define CAN_ESR2_LPTM_MASK   (0x7F0000U)
 
#define CAN_ESR2_LPTM_SHIFT   (16U)
 
#define CAN_ESR2_LPTM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
 
#define CAN_ESR2_IMB_MASK   (0x2000U)
 
#define CAN_ESR2_IMB_SHIFT   (13U)
 
#define CAN_ESR2_IMB(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
 
#define CAN_ESR2_VPS_MASK   (0x4000U)
 
#define CAN_ESR2_VPS_SHIFT   (14U)
 
#define CAN_ESR2_VPS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
 
#define CAN_ESR2_LPTM_MASK   (0x7F0000U)
 
#define CAN_ESR2_LPTM_SHIFT   (16U)
 
#define CAN_ESR2_LPTM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
 

CRCR - CRC Register

#define CAN_CRCR_TXCRC_MASK   (0x7FFFU)
 
#define CAN_CRCR_TXCRC_SHIFT   (0U)
 
#define CAN_CRCR_TXCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
 
#define CAN_CRCR_MBCRC_MASK   (0x7F0000U)
 
#define CAN_CRCR_MBCRC_SHIFT   (16U)
 
#define CAN_CRCR_MBCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
 
#define CAN_CRCR_TXCRC_MASK   0x7FFFu
 
#define CAN_CRCR_TXCRC_SHIFT   0
 
#define CAN_CRCR_TXCRC(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
 
#define CAN_CRCR_MBCRC_MASK   0x7F0000u
 
#define CAN_CRCR_MBCRC_SHIFT   16
 
#define CAN_CRCR_MBCRC(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
 
#define CAN_CRCR_TXCRC_MASK   (0x7FFFU)
 
#define CAN_CRCR_TXCRC_SHIFT   (0U)
 
#define CAN_CRCR_TXCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
 
#define CAN_CRCR_MBCRC_MASK   (0x7F0000U)
 
#define CAN_CRCR_MBCRC_SHIFT   (16U)
 
#define CAN_CRCR_MBCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
 
#define CAN_CRCR_TXCRC_MASK   (0x7FFFU)
 
#define CAN_CRCR_TXCRC_SHIFT   (0U)
 
#define CAN_CRCR_TXCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
 
#define CAN_CRCR_MBCRC_MASK   (0x7F0000U)
 
#define CAN_CRCR_MBCRC_SHIFT   (16U)
 
#define CAN_CRCR_MBCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
 
#define CAN_CRCR_TXCRC_MASK   (0x7FFFU)
 
#define CAN_CRCR_TXCRC_SHIFT   (0U)
 
#define CAN_CRCR_TXCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
 
#define CAN_CRCR_MBCRC_MASK   (0x7F0000U)
 
#define CAN_CRCR_MBCRC_SHIFT   (16U)
 
#define CAN_CRCR_MBCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
 
#define CAN_CRCR_TXCRC_MASK   (0x7FFFU)
 
#define CAN_CRCR_TXCRC_SHIFT   (0U)
 
#define CAN_CRCR_TXCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
 
#define CAN_CRCR_MBCRC_MASK   (0x7F0000U)
 
#define CAN_CRCR_MBCRC_SHIFT   (16U)
 
#define CAN_CRCR_MBCRC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
 

RXFGMASK - Rx FIFO Global Mask register

#define CAN_RXFGMASK_FGM_MASK   (0xFFFFFFFFU)
 
#define CAN_RXFGMASK_FGM_SHIFT   (0U)
 
#define CAN_RXFGMASK_FGM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
 
#define CAN_RXFGMASK_FGM_MASK   0xFFFFFFFFu
 
#define CAN_RXFGMASK_FGM_SHIFT   0
 
#define CAN_RXFGMASK_FGM(x)   (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
 
#define CAN_RXFGMASK_FGM_MASK   (0xFFFFFFFFU)
 
#define CAN_RXFGMASK_FGM_SHIFT   (0U)
 
#define CAN_RXFGMASK_FGM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
 
#define CAN_RXFGMASK_FGM_MASK   (0xFFFFFFFFU)
 
#define CAN_RXFGMASK_FGM_SHIFT   (0U)
 
#define CAN_RXFGMASK_FGM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
 
#define CAN_RXFGMASK_FGM_MASK   (0xFFFFFFFFU)
 
#define CAN_RXFGMASK_FGM_SHIFT   (0U)
 
#define CAN_RXFGMASK_FGM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
 
#define CAN_RXFGMASK_FGM_MASK   (0xFFFFFFFFU)
 
#define CAN_RXFGMASK_FGM_SHIFT   (0U)
 
#define CAN_RXFGMASK_FGM(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
 

RXFIR - Rx FIFO Information Register

#define CAN_RXFIR_IDHIT_MASK   (0x1FFU)
 
#define CAN_RXFIR_IDHIT_SHIFT   (0U)
 
#define CAN_RXFIR_IDHIT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
 
#define CAN_RXFIR_IDHIT_MASK   0x1FFu
 
#define CAN_RXFIR_IDHIT_SHIFT   0
 
#define CAN_RXFIR_IDHIT(x)   (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
 
#define CAN_RXFIR_IDHIT_MASK   (0x1FFU)
 
#define CAN_RXFIR_IDHIT_SHIFT   (0U)
 
#define CAN_RXFIR_IDHIT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
 
#define CAN_RXFIR_IDHIT_MASK   (0x1FFU)
 
#define CAN_RXFIR_IDHIT_SHIFT   (0U)
 
#define CAN_RXFIR_IDHIT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
 
#define CAN_RXFIR_IDHIT_MASK   (0x1FFU)
 
#define CAN_RXFIR_IDHIT_SHIFT   (0U)
 
#define CAN_RXFIR_IDHIT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
 
#define CAN_RXFIR_IDHIT_MASK   (0x1FFU)
 
#define CAN_RXFIR_IDHIT_SHIFT   (0U)
 
#define CAN_RXFIR_IDHIT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
 

CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register

#define CAN_CS_TIME_STAMP_MASK   (0xFFFFU)
 
#define CAN_CS_TIME_STAMP_SHIFT   (0U)
 
#define CAN_CS_TIME_STAMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
 
#define CAN_CS_DLC_MASK   (0xF0000U)
 
#define CAN_CS_DLC_SHIFT   (16U)
 
#define CAN_CS_DLC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
 
#define CAN_CS_RTR_MASK   (0x100000U)
 
#define CAN_CS_RTR_SHIFT   (20U)
 
#define CAN_CS_RTR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
 
#define CAN_CS_IDE_MASK   (0x200000U)
 
#define CAN_CS_IDE_SHIFT   (21U)
 
#define CAN_CS_IDE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
 
#define CAN_CS_SRR_MASK   (0x400000U)
 
#define CAN_CS_SRR_SHIFT   (22U)
 
#define CAN_CS_SRR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
 
#define CAN_CS_CODE_MASK   (0xF000000U)
 
#define CAN_CS_CODE_SHIFT   (24U)
 
#define CAN_CS_CODE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
 
#define CAN_CS_TIME_STAMP_MASK   0xFFFFu
 
#define CAN_CS_TIME_STAMP_SHIFT   0
 
#define CAN_CS_TIME_STAMP(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
 
#define CAN_CS_DLC_MASK   0xF0000u
 
#define CAN_CS_DLC_SHIFT   16
 
#define CAN_CS_DLC(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
 
#define CAN_CS_RTR_MASK   0x100000u
 
#define CAN_CS_RTR_SHIFT   20
 
#define CAN_CS_IDE_MASK   0x200000u
 
#define CAN_CS_IDE_SHIFT   21
 
#define CAN_CS_SRR_MASK   0x400000u
 
#define CAN_CS_SRR_SHIFT   22
 
#define CAN_CS_CODE_MASK   0xF000000u
 
#define CAN_CS_CODE_SHIFT   24
 
#define CAN_CS_CODE(x)   (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
 
#define CAN_CS_TIME_STAMP_MASK   (0xFFFFU)
 
#define CAN_CS_TIME_STAMP_SHIFT   (0U)
 
#define CAN_CS_TIME_STAMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
 
#define CAN_CS_DLC_MASK   (0xF0000U)
 
#define CAN_CS_DLC_SHIFT   (16U)
 
#define CAN_CS_DLC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
 
#define CAN_CS_RTR_MASK   (0x100000U)
 
#define CAN_CS_RTR_SHIFT   (20U)
 
#define CAN_CS_RTR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
 
#define CAN_CS_IDE_MASK   (0x200000U)
 
#define CAN_CS_IDE_SHIFT   (21U)
 
#define CAN_CS_IDE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
 
#define CAN_CS_SRR_MASK   (0x400000U)
 
#define CAN_CS_SRR_SHIFT   (22U)
 
#define CAN_CS_SRR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
 
#define CAN_CS_CODE_MASK   (0xF000000U)
 
#define CAN_CS_CODE_SHIFT   (24U)
 
#define CAN_CS_CODE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
 
#define CAN_CS_TIME_STAMP_MASK   (0xFFFFU)
 
#define CAN_CS_TIME_STAMP_SHIFT   (0U)
 
#define CAN_CS_TIME_STAMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
 
#define CAN_CS_DLC_MASK   (0xF0000U)
 
#define CAN_CS_DLC_SHIFT   (16U)
 
#define CAN_CS_DLC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
 
#define CAN_CS_RTR_MASK   (0x100000U)
 
#define CAN_CS_RTR_SHIFT   (20U)
 
#define CAN_CS_RTR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
 
#define CAN_CS_IDE_MASK   (0x200000U)
 
#define CAN_CS_IDE_SHIFT   (21U)
 
#define CAN_CS_IDE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
 
#define CAN_CS_SRR_MASK   (0x400000U)
 
#define CAN_CS_SRR_SHIFT   (22U)
 
#define CAN_CS_SRR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
 
#define CAN_CS_CODE_MASK   (0xF000000U)
 
#define CAN_CS_CODE_SHIFT   (24U)
 
#define CAN_CS_CODE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
 
#define CAN_CS_TIME_STAMP_MASK   (0xFFFFU)
 
#define CAN_CS_TIME_STAMP_SHIFT   (0U)
 
#define CAN_CS_TIME_STAMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
 
#define CAN_CS_DLC_MASK   (0xF0000U)
 
#define CAN_CS_DLC_SHIFT   (16U)
 
#define CAN_CS_DLC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
 
#define CAN_CS_RTR_MASK   (0x100000U)
 
#define CAN_CS_RTR_SHIFT   (20U)
 
#define CAN_CS_RTR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
 
#define CAN_CS_IDE_MASK   (0x200000U)
 
#define CAN_CS_IDE_SHIFT   (21U)
 
#define CAN_CS_IDE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
 
#define CAN_CS_SRR_MASK   (0x400000U)
 
#define CAN_CS_SRR_SHIFT   (22U)
 
#define CAN_CS_SRR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
 
#define CAN_CS_CODE_MASK   (0xF000000U)
 
#define CAN_CS_CODE_SHIFT   (24U)
 
#define CAN_CS_CODE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
 
#define CAN_CS_TIME_STAMP_MASK   (0xFFFFU)
 
#define CAN_CS_TIME_STAMP_SHIFT   (0U)
 
#define CAN_CS_TIME_STAMP(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
 
#define CAN_CS_DLC_MASK   (0xF0000U)
 
#define CAN_CS_DLC_SHIFT   (16U)
 
#define CAN_CS_DLC(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
 
#define CAN_CS_RTR_MASK   (0x100000U)
 
#define CAN_CS_RTR_SHIFT   (20U)
 
#define CAN_CS_RTR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
 
#define CAN_CS_IDE_MASK   (0x200000U)
 
#define CAN_CS_IDE_SHIFT   (21U)
 
#define CAN_CS_IDE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
 
#define CAN_CS_SRR_MASK   (0x400000U)
 
#define CAN_CS_SRR_SHIFT   (22U)
 
#define CAN_CS_SRR(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
 
#define CAN_CS_CODE_MASK   (0xF000000U)
 
#define CAN_CS_CODE_SHIFT   (24U)
 
#define CAN_CS_CODE(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
 
#define CAN_CS_ESI_MASK   (0x20000000U)
 
#define CAN_CS_ESI_SHIFT   (29U)
 
#define CAN_CS_ESI(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
 
#define CAN_CS_BRS_MASK   (0x40000000U)
 
#define CAN_CS_BRS_SHIFT   (30U)
 
#define CAN_CS_BRS(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
 
#define CAN_CS_EDL_MASK   (0x80000000U)
 
#define CAN_CS_EDL_SHIFT   (31U)
 
#define CAN_CS_EDL(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
 

CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register

#define CAN_CS_COUNT   (16U)
 

ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register

#define CAN_ID_EXT_MASK   (0x3FFFFU)
 
#define CAN_ID_EXT_SHIFT   (0U)
 
#define CAN_ID_EXT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
 
#define CAN_ID_STD_MASK   (0x1FFC0000U)
 
#define CAN_ID_STD_SHIFT   (18U)
 
#define CAN_ID_STD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
 
#define CAN_ID_PRIO_MASK   (0xE0000000U)
 
#define CAN_ID_PRIO_SHIFT   (29U)
 
#define CAN_ID_PRIO(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
 
#define CAN_ID_EXT_MASK   0x3FFFFu
 
#define CAN_ID_EXT_SHIFT   0
 
#define CAN_ID_EXT(x)   (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
 
#define CAN_ID_STD_MASK   0x1FFC0000u
 
#define CAN_ID_STD_SHIFT   18
 
#define CAN_ID_STD(x)   (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
 
#define CAN_ID_PRIO_MASK   0xE0000000u
 
#define CAN_ID_PRIO_SHIFT   29
 
#define CAN_ID_PRIO(x)   (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
 
#define CAN_ID_EXT_MASK   (0x3FFFFU)
 
#define CAN_ID_EXT_SHIFT   (0U)
 
#define CAN_ID_EXT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
 
#define CAN_ID_STD_MASK   (0x1FFC0000U)
 
#define CAN_ID_STD_SHIFT   (18U)
 
#define CAN_ID_STD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
 
#define CAN_ID_PRIO_MASK   (0xE0000000U)
 
#define CAN_ID_PRIO_SHIFT   (29U)
 
#define CAN_ID_PRIO(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
 
#define CAN_ID_EXT_MASK   (0x3FFFFU)
 
#define CAN_ID_EXT_SHIFT   (0U)
 
#define CAN_ID_EXT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
 
#define CAN_ID_STD_MASK   (0x1FFC0000U)
 
#define CAN_ID_STD_SHIFT   (18U)
 
#define CAN_ID_STD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
 
#define CAN_ID_PRIO_MASK   (0xE0000000U)
 
#define CAN_ID_PRIO_SHIFT   (29U)
 
#define CAN_ID_PRIO(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
 
#define CAN_ID_EXT_MASK   (0x3FFFFU)
 
#define CAN_ID_EXT_SHIFT   (0U)
 
#define CAN_ID_EXT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
 
#define CAN_ID_STD_MASK   (0x1FFC0000U)
 
#define CAN_ID_STD_SHIFT   (18U)
 
#define CAN_ID_STD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
 
#define CAN_ID_PRIO_MASK   (0xE0000000U)
 
#define CAN_ID_PRIO_SHIFT   (29U)
 
#define CAN_ID_PRIO(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
 
#define CAN_ID_EXT_MASK   (0x3FFFFU)
 
#define CAN_ID_EXT_SHIFT   (0U)
 
#define CAN_ID_EXT(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
 
#define CAN_ID_STD_MASK   (0x1FFC0000U)
 
#define CAN_ID_STD_SHIFT   (18U)
 
#define CAN_ID_STD(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
 
#define CAN_ID_PRIO_MASK   (0xE0000000U)
 
#define CAN_ID_PRIO_SHIFT   (29U)
 
#define CAN_ID_PRIO(x)   (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
 

ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register

#define CAN_ID_COUNT   (16U)
 

WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register

#define CAN_WORD0_DATA_BYTE_3_MASK   (0xFFU)
 
#define CAN_WORD0_DATA_BYTE_3_SHIFT   (0U)
 
#define CAN_WORD0_DATA_BYTE_3(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
 
#define CAN_WORD0_DATA_BYTE_2_MASK   (0xFF00U)
 
#define CAN_WORD0_DATA_BYTE_2_SHIFT   (8U)
 
#define CAN_WORD0_DATA_BYTE_2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
 
#define CAN_WORD0_DATA_BYTE_1_MASK   (0xFF0000U)
 
#define CAN_WORD0_DATA_BYTE_1_SHIFT   (16U)
 
#define CAN_WORD0_DATA_BYTE_1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
 
#define CAN_WORD0_DATA_BYTE_0_MASK   (0xFF000000U)
 
#define CAN_WORD0_DATA_BYTE_0_SHIFT   (24U)
 
#define CAN_WORD0_DATA_BYTE_0(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
 
#define CAN_WORD0_DATA_BYTE_3_MASK   0xFFu
 
#define CAN_WORD0_DATA_BYTE_3_SHIFT   0
 
#define CAN_WORD0_DATA_BYTE_3(x)   (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
 
#define CAN_WORD0_DATA_BYTE_2_MASK   0xFF00u
 
#define CAN_WORD0_DATA_BYTE_2_SHIFT   8
 
#define CAN_WORD0_DATA_BYTE_2(x)   (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
 
#define CAN_WORD0_DATA_BYTE_1_MASK   0xFF0000u
 
#define CAN_WORD0_DATA_BYTE_1_SHIFT   16
 
#define CAN_WORD0_DATA_BYTE_1(x)   (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
 
#define CAN_WORD0_DATA_BYTE_0_MASK   0xFF000000u
 
#define CAN_WORD0_DATA_BYTE_0_SHIFT   24
 
#define CAN_WORD0_DATA_BYTE_0(x)   (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
 
#define CAN_WORD0_DATA_BYTE_3_MASK   (0xFFU)
 
#define CAN_WORD0_DATA_BYTE_3_SHIFT   (0U)
 
#define CAN_WORD0_DATA_BYTE_3(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
 
#define CAN_WORD0_DATA_BYTE_2_MASK   (0xFF00U)
 
#define CAN_WORD0_DATA_BYTE_2_SHIFT   (8U)
 
#define CAN_WORD0_DATA_BYTE_2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
 
#define CAN_WORD0_DATA_BYTE_1_MASK   (0xFF0000U)
 
#define CAN_WORD0_DATA_BYTE_1_SHIFT   (16U)
 
#define CAN_WORD0_DATA_BYTE_1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
 
#define CAN_WORD0_DATA_BYTE_0_MASK   (0xFF000000U)
 
#define CAN_WORD0_DATA_BYTE_0_SHIFT   (24U)
 
#define CAN_WORD0_DATA_BYTE_0(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
 
#define CAN_WORD0_DATA_BYTE_3_MASK   (0xFFU)
 
#define CAN_WORD0_DATA_BYTE_3_SHIFT   (0U)
 
#define CAN_WORD0_DATA_BYTE_3(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
 
#define CAN_WORD0_DATA_BYTE_2_MASK   (0xFF00U)
 
#define CAN_WORD0_DATA_BYTE_2_SHIFT   (8U)
 
#define CAN_WORD0_DATA_BYTE_2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
 
#define CAN_WORD0_DATA_BYTE_1_MASK   (0xFF0000U)
 
#define CAN_WORD0_DATA_BYTE_1_SHIFT   (16U)
 
#define CAN_WORD0_DATA_BYTE_1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
 
#define CAN_WORD0_DATA_BYTE_0_MASK   (0xFF000000U)
 
#define CAN_WORD0_DATA_BYTE_0_SHIFT   (24U)
 
#define CAN_WORD0_DATA_BYTE_0(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
 
#define CAN_WORD0_DATA_BYTE_3_MASK   (0xFFU)
 
#define CAN_WORD0_DATA_BYTE_3_SHIFT   (0U)
 
#define CAN_WORD0_DATA_BYTE_3(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
 
#define CAN_WORD0_DATA_BYTE_2_MASK   (0xFF00U)
 
#define CAN_WORD0_DATA_BYTE_2_SHIFT   (8U)
 
#define CAN_WORD0_DATA_BYTE_2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
 
#define CAN_WORD0_DATA_BYTE_1_MASK   (0xFF0000U)
 
#define CAN_WORD0_DATA_BYTE_1_SHIFT   (16U)
 
#define CAN_WORD0_DATA_BYTE_1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
 
#define CAN_WORD0_DATA_BYTE_0_MASK   (0xFF000000U)
 
#define CAN_WORD0_DATA_BYTE_0_SHIFT   (24U)
 
#define CAN_WORD0_DATA_BYTE_0(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
 
#define CAN_WORD0_DATA_BYTE_3_MASK   (0xFFU)
 
#define CAN_WORD0_DATA_BYTE_3_SHIFT   (0U)
 
#define CAN_WORD0_DATA_BYTE_3(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
 
#define CAN_WORD0_DATA_BYTE_2_MASK   (0xFF00U)
 
#define CAN_WORD0_DATA_BYTE_2_SHIFT   (8U)
 
#define CAN_WORD0_DATA_BYTE_2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
 
#define CAN_WORD0_DATA_BYTE_1_MASK   (0xFF0000U)
 
#define CAN_WORD0_DATA_BYTE_1_SHIFT   (16U)
 
#define CAN_WORD0_DATA_BYTE_1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
 
#define CAN_WORD0_DATA_BYTE_0_MASK   (0xFF000000U)
 
#define CAN_WORD0_DATA_BYTE_0_SHIFT   (24U)
 
#define CAN_WORD0_DATA_BYTE_0(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
 

WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register

#define CAN_WORD0_COUNT   (16U)
 

WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register

#define CAN_WORD1_DATA_BYTE_7_MASK   (0xFFU)
 
#define CAN_WORD1_DATA_BYTE_7_SHIFT   (0U)
 
#define CAN_WORD1_DATA_BYTE_7(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
 
#define CAN_WORD1_DATA_BYTE_6_MASK   (0xFF00U)
 
#define CAN_WORD1_DATA_BYTE_6_SHIFT   (8U)
 
#define CAN_WORD1_DATA_BYTE_6(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
 
#define CAN_WORD1_DATA_BYTE_5_MASK   (0xFF0000U)
 
#define CAN_WORD1_DATA_BYTE_5_SHIFT   (16U)
 
#define CAN_WORD1_DATA_BYTE_5(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
 
#define CAN_WORD1_DATA_BYTE_4_MASK   (0xFF000000U)
 
#define CAN_WORD1_DATA_BYTE_4_SHIFT   (24U)
 
#define CAN_WORD1_DATA_BYTE_4(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
 
#define CAN_WORD1_DATA_BYTE_7_MASK   0xFFu
 
#define CAN_WORD1_DATA_BYTE_7_SHIFT   0
 
#define CAN_WORD1_DATA_BYTE_7(x)   (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
 
#define CAN_WORD1_DATA_BYTE_6_MASK   0xFF00u
 
#define CAN_WORD1_DATA_BYTE_6_SHIFT   8
 
#define CAN_WORD1_DATA_BYTE_6(x)   (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
 
#define CAN_WORD1_DATA_BYTE_5_MASK   0xFF0000u
 
#define CAN_WORD1_DATA_BYTE_5_SHIFT   16
 
#define CAN_WORD1_DATA_BYTE_5(x)   (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
 
#define CAN_WORD1_DATA_BYTE_4_MASK   0xFF000000u
 
#define CAN_WORD1_DATA_BYTE_4_SHIFT   24
 
#define CAN_WORD1_DATA_BYTE_4(x)   (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
 
#define CAN_WORD1_DATA_BYTE_7_MASK   (0xFFU)
 
#define CAN_WORD1_DATA_BYTE_7_SHIFT   (0U)
 
#define CAN_WORD1_DATA_BYTE_7(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
 
#define CAN_WORD1_DATA_BYTE_6_MASK   (0xFF00U)
 
#define CAN_WORD1_DATA_BYTE_6_SHIFT   (8U)
 
#define CAN_WORD1_DATA_BYTE_6(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
 
#define CAN_WORD1_DATA_BYTE_5_MASK   (0xFF0000U)
 
#define CAN_WORD1_DATA_BYTE_5_SHIFT   (16U)
 
#define CAN_WORD1_DATA_BYTE_5(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
 
#define CAN_WORD1_DATA_BYTE_4_MASK   (0xFF000000U)
 
#define CAN_WORD1_DATA_BYTE_4_SHIFT   (24U)
 
#define CAN_WORD1_DATA_BYTE_4(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
 
#define CAN_WORD1_DATA_BYTE_7_MASK   (0xFFU)
 
#define CAN_WORD1_DATA_BYTE_7_SHIFT   (0U)
 
#define CAN_WORD1_DATA_BYTE_7(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
 
#define CAN_WORD1_DATA_BYTE_6_MASK   (0xFF00U)
 
#define CAN_WORD1_DATA_BYTE_6_SHIFT   (8U)
 
#define CAN_WORD1_DATA_BYTE_6(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
 
#define CAN_WORD1_DATA_BYTE_5_MASK   (0xFF0000U)
 
#define CAN_WORD1_DATA_BYTE_5_SHIFT   (16U)
 
#define CAN_WORD1_DATA_BYTE_5(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
 
#define CAN_WORD1_DATA_BYTE_4_MASK   (0xFF000000U)
 
#define CAN_WORD1_DATA_BYTE_4_SHIFT   (24U)
 
#define CAN_WORD1_DATA_BYTE_4(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
 
#define CAN_WORD1_DATA_BYTE_7_MASK   (0xFFU)
 
#define CAN_WORD1_DATA_BYTE_7_SHIFT   (0U)
 
#define CAN_WORD1_DATA_BYTE_7(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
 
#define CAN_WORD1_DATA_BYTE_6_MASK   (0xFF00U)
 
#define CAN_WORD1_DATA_BYTE_6_SHIFT   (8U)
 
#define CAN_WORD1_DATA_BYTE_6(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
 
#define CAN_WORD1_DATA_BYTE_5_MASK   (0xFF0000U)
 
#define CAN_WORD1_DATA_BYTE_5_SHIFT   (16U)
 
#define CAN_WORD1_DATA_BYTE_5(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
 
#define CAN_WORD1_DATA_BYTE_4_MASK   (0xFF000000U)
 
#define CAN_WORD1_DATA_BYTE_4_SHIFT   (24U)
 
#define CAN_WORD1_DATA_BYTE_4(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
 
#define CAN_WORD1_DATA_BYTE_7_MASK   (0xFFU)
 
#define CAN_WORD1_DATA_BYTE_7_SHIFT   (0U)
 
#define CAN_WORD1_DATA_BYTE_7(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
 
#define CAN_WORD1_DATA_BYTE_6_MASK   (0xFF00U)
 
#define CAN_WORD1_DATA_BYTE_6_SHIFT   (8U)
 
#define CAN_WORD1_DATA_BYTE_6(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
 
#define CAN_WORD1_DATA_BYTE_5_MASK   (0xFF0000U)
 
#define CAN_WORD1_DATA_BYTE_5_SHIFT   (16U)
 
#define CAN_WORD1_DATA_BYTE_5(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
 
#define CAN_WORD1_DATA_BYTE_4_MASK   (0xFF000000U)
 
#define CAN_WORD1_DATA_BYTE_4_SHIFT   (24U)
 
#define CAN_WORD1_DATA_BYTE_4(x)   (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
 

WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register

#define CAN_WORD1_COUNT   (16U)
 

RXIMR - Rx Individual Mask Registers

#define CAN_RXIMR_MI_MASK   (0xFFFFFFFFU)
 
#define CAN_RXIMR_MI_SHIFT   (0U)
 
#define CAN_RXIMR_MI(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
 
#define CAN_RXIMR_MI_MASK   0xFFFFFFFFu
 
#define CAN_RXIMR_MI_SHIFT   0
 
#define CAN_RXIMR_MI(x)   (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
 
#define CAN_RXIMR_MI_MASK   (0xFFFFFFFFU)
 
#define CAN_RXIMR_MI_SHIFT   (0U)
 
#define CAN_RXIMR_MI(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
 
#define CAN_RXIMR_MI_MASK   (0xFFFFFFFFU)
 
#define CAN_RXIMR_MI_SHIFT   (0U)
 
#define CAN_RXIMR_MI(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
 
#define CAN_RXIMR_MI_MASK   (0xFFFFFFFFU)
 
#define CAN_RXIMR_MI_SHIFT   (0U)
 
#define CAN_RXIMR_MI(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
 
#define CAN_RXIMR_MI_MASK   (0xFFFFFFFFU)
 
#define CAN_RXIMR_MI_SHIFT   (0U)
 
#define CAN_RXIMR_MI(x)   (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
 

RXIMR - Rx Individual Mask Registers

#define CAN_RXIMR_COUNT   (16U)
 

IMASK1 - Interrupt Masks 1 register

#define CAN_IMASK1_BUF31TO0M_MASK   (0xFFFFFFFFU)
 
#define CAN_IMASK1_BUF31TO0M_SHIFT   (0U)
 
#define CAN_IMASK1_BUF31TO0M(x)   (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
 

CBT - CAN Bit Timing Register

#define CAN_CBT_EPSEG2_MASK   (0x1FU)
 
#define CAN_CBT_EPSEG2_SHIFT   (0U)
 
#define CAN_CBT_EPSEG2(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
 
#define CAN_CBT_EPSEG1_MASK   (0x3E0U)
 
#define CAN_CBT_EPSEG1_SHIFT   (5U)
 
#define CAN_CBT_EPSEG1(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
 
#define CAN_CBT_EPROPSEG_MASK   (0xFC00U)
 
#define CAN_CBT_EPROPSEG_SHIFT   (10U)
 
#define CAN_CBT_EPROPSEG(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
 
#define CAN_CBT_ERJW_MASK   (0xF0000U)
 
#define CAN_CBT_ERJW_SHIFT   (16U)
 
#define CAN_CBT_ERJW(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
 
#define CAN_CBT_EPRESDIV_MASK   (0x7FE00000U)
 
#define CAN_CBT_EPRESDIV_SHIFT   (21U)
 
#define CAN_CBT_EPRESDIV(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
 
#define CAN_CBT_BTF_MASK   (0x80000000U)
 
#define CAN_CBT_BTF_SHIFT   (31U)
 
#define CAN_CBT_BTF(x)   (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
 

Macro Definition Documentation

◆ CAN0

#define CAN0   ((CAN_Type *)CAN0_BASE)

Peripheral CAN0 base pointer

◆ CAN0_BASE

#define CAN0_BASE   (0x40024000u)

Peripheral CAN0 base address

◆ CAN1

#define CAN1   ((CAN_Type *)CAN1_BASE)

Peripheral CAN1 base pointer

◆ CAN1_BASE

#define CAN1_BASE   (0x400A4000u)

Peripheral CAN1 base address

◆ CAN_BASE_ADDRS

#define CAN_BASE_ADDRS   { CAN0_BASE, CAN1_BASE }

Array initializer of CAN peripheral base addresses

◆ CAN_BASE_PTRS

#define CAN_BASE_PTRS   { CAN0, CAN1 }

Array initializer of CAN peripheral base pointers

◆ CAN_CBT_BTF

#define CAN_CBT_BTF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)

BTF - Bit Timing Format Enable 0b0..Extended bit time definitions disabled. 0b1..Extended bit time definitions enabled.

◆ CAN_CTRL1_BOFFMSK [1/5]

#define CAN_CTRL1_BOFFMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

BOFFMSK - Bus Off Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

BOFFMSK - Bus Off Interrupt Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

◆ CAN_CTRL1_BOFFMSK [2/5]

#define CAN_CTRL1_BOFFMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

BOFFMSK - Bus Off Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

BOFFMSK - Bus Off Interrupt Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

◆ CAN_CTRL1_BOFFMSK [3/5]

#define CAN_CTRL1_BOFFMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

BOFFMSK - Bus Off Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

BOFFMSK - Bus Off Interrupt Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

◆ CAN_CTRL1_BOFFMSK [4/5]

#define CAN_CTRL1_BOFFMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

BOFFMSK - Bus Off Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

BOFFMSK - Bus Off Interrupt Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

◆ CAN_CTRL1_BOFFMSK [5/5]

#define CAN_CTRL1_BOFFMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)

BOFFMSK - Bus Off Interrupt Mask 0b0..Bus Off interrupt disabled. 0b1..Bus Off interrupt enabled.

◆ CAN_CTRL1_BOFFREC [1/5]

#define CAN_CTRL1_BOFFREC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B. 0b1..Automatic recovering from Bus Off state disabled.

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled. 0b1..Automatic recovering from Bus Off state disabled.

◆ CAN_CTRL1_BOFFREC [2/5]

#define CAN_CTRL1_BOFFREC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B. 0b1..Automatic recovering from Bus Off state disabled.

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled. 0b1..Automatic recovering from Bus Off state disabled.

◆ CAN_CTRL1_BOFFREC [3/5]

#define CAN_CTRL1_BOFFREC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B. 0b1..Automatic recovering from Bus Off state disabled.

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled. 0b1..Automatic recovering from Bus Off state disabled.

◆ CAN_CTRL1_BOFFREC [4/5]

#define CAN_CTRL1_BOFFREC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B. 0b1..Automatic recovering from Bus Off state disabled.

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled. 0b1..Automatic recovering from Bus Off state disabled.

◆ CAN_CTRL1_BOFFREC [5/5]

#define CAN_CTRL1_BOFFREC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)

BOFFREC - Bus Off Recovery 0b0..Automatic recovering from Bus Off state enabled. 0b1..Automatic recovering from Bus Off state disabled.

◆ CAN_CTRL1_CLKSRC [1/5]

#define CAN_CTRL1_CLKSRC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)

CLKSRC - CAN Engine Clock Source 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 0b1..The CAN engine clock source is the peripheral clock.

◆ CAN_CTRL1_CLKSRC [2/5]

#define CAN_CTRL1_CLKSRC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)

CLKSRC - CAN Engine Clock Source 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 0b1..The CAN engine clock source is the peripheral clock.

◆ CAN_CTRL1_CLKSRC [3/5]

#define CAN_CTRL1_CLKSRC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)

CLKSRC - CAN Engine Clock Source 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 0b1..The CAN engine clock source is the peripheral clock.

◆ CAN_CTRL1_CLKSRC [4/5]

#define CAN_CTRL1_CLKSRC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)

CLKSRC - CAN Engine Clock Source 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 0b1..The CAN engine clock source is the peripheral clock.

◆ CAN_CTRL1_CLKSRC [5/5]

#define CAN_CTRL1_CLKSRC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)

CLKSRC - CAN Engine Clock Source 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. 0b1..The CAN engine clock source is the peripheral clock.

◆ CAN_CTRL1_ERRMSK [1/5]

#define CAN_CTRL1_ERRMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

ERRMSK - Error Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

ERRMSK - Error Interrupt Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

◆ CAN_CTRL1_ERRMSK [2/5]

#define CAN_CTRL1_ERRMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

ERRMSK - Error Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

ERRMSK - Error Interrupt Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

◆ CAN_CTRL1_ERRMSK [3/5]

#define CAN_CTRL1_ERRMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

ERRMSK - Error Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

ERRMSK - Error Interrupt Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

◆ CAN_CTRL1_ERRMSK [4/5]

#define CAN_CTRL1_ERRMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

ERRMSK - Error Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

ERRMSK - Error Interrupt Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

◆ CAN_CTRL1_ERRMSK [5/5]

#define CAN_CTRL1_ERRMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)

ERRMSK - Error Interrupt Mask 0b0..Error interrupt disabled. 0b1..Error interrupt enabled.

◆ CAN_CTRL1_LBUF [1/5]

#define CAN_CTRL1_LBUF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

LBUF - Lowest Buffer Transmitted First 0b0..Buffer with highest priority is transmitted first. 0b1..Lowest number buffer is transmitted first.

◆ CAN_CTRL1_LBUF [2/5]

#define CAN_CTRL1_LBUF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

LBUF - Lowest Buffer Transmitted First 0b0..Buffer with highest priority is transmitted first. 0b1..Lowest number buffer is transmitted first.

◆ CAN_CTRL1_LBUF [3/5]

#define CAN_CTRL1_LBUF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

LBUF - Lowest Buffer Transmitted First 0b0..Buffer with highest priority is transmitted first. 0b1..Lowest number buffer is transmitted first.

◆ CAN_CTRL1_LBUF [4/5]

#define CAN_CTRL1_LBUF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

LBUF - Lowest Buffer Transmitted First 0b0..Buffer with highest priority is transmitted first. 0b1..Lowest number buffer is transmitted first.

◆ CAN_CTRL1_LBUF [5/5]

#define CAN_CTRL1_LBUF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)

LBUF - Lowest Buffer Transmitted First 0b0..Buffer with highest priority is transmitted first. 0b1..Lowest number buffer is transmitted first.

◆ CAN_CTRL1_LOM [1/5]

#define CAN_CTRL1_LOM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

LOM - Listen-Only Mode 0b0..Listen-Only mode is deactivated. 0b1..FlexCAN module operates in Listen-Only mode.

◆ CAN_CTRL1_LOM [2/5]

#define CAN_CTRL1_LOM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

LOM - Listen-Only Mode 0b0..Listen-Only mode is deactivated. 0b1..FlexCAN module operates in Listen-Only mode.

◆ CAN_CTRL1_LOM [3/5]

#define CAN_CTRL1_LOM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

LOM - Listen-Only Mode 0b0..Listen-Only mode is deactivated. 0b1..FlexCAN module operates in Listen-Only mode.

◆ CAN_CTRL1_LOM [4/5]

#define CAN_CTRL1_LOM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

LOM - Listen-Only Mode 0b0..Listen-Only mode is deactivated. 0b1..FlexCAN module operates in Listen-Only mode.

◆ CAN_CTRL1_LOM [5/5]

#define CAN_CTRL1_LOM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)

LOM - Listen-Only Mode 0b0..Listen-Only mode is deactivated. 0b1..FlexCAN module operates in Listen-Only mode.

◆ CAN_CTRL1_LPB [1/5]

#define CAN_CTRL1_LPB ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

LPB - Loop Back Mode 0b0..Loop Back disabled. 0b1..Loop Back enabled.

◆ CAN_CTRL1_LPB [2/5]

#define CAN_CTRL1_LPB ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

LPB - Loop Back Mode 0b0..Loop Back disabled. 0b1..Loop Back enabled.

◆ CAN_CTRL1_LPB [3/5]

#define CAN_CTRL1_LPB ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

LPB - Loop Back Mode 0b0..Loop Back disabled. 0b1..Loop Back enabled.

◆ CAN_CTRL1_LPB [4/5]

#define CAN_CTRL1_LPB ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

LPB - Loop Back Mode 0b0..Loop Back disabled. 0b1..Loop Back enabled.

◆ CAN_CTRL1_LPB [5/5]

#define CAN_CTRL1_LPB ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)

LPB - Loop Back Mode 0b0..Loop Back disabled. 0b1..Loop Back enabled.

◆ CAN_CTRL1_RWRNMSK [1/5]

#define CAN_CTRL1_RWRNMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

RWRNMSK - Rx Warning Interrupt Mask 0b0..Rx Warning Interrupt disabled. 0b1..Rx Warning Interrupt enabled.

◆ CAN_CTRL1_RWRNMSK [2/5]

#define CAN_CTRL1_RWRNMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

RWRNMSK - Rx Warning Interrupt Mask 0b0..Rx Warning Interrupt disabled. 0b1..Rx Warning Interrupt enabled.

◆ CAN_CTRL1_RWRNMSK [3/5]

#define CAN_CTRL1_RWRNMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

RWRNMSK - Rx Warning Interrupt Mask 0b0..Rx Warning Interrupt disabled. 0b1..Rx Warning Interrupt enabled.

◆ CAN_CTRL1_RWRNMSK [4/5]

#define CAN_CTRL1_RWRNMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

RWRNMSK - Rx Warning Interrupt Mask 0b0..Rx Warning Interrupt disabled. 0b1..Rx Warning Interrupt enabled.

◆ CAN_CTRL1_RWRNMSK [5/5]

#define CAN_CTRL1_RWRNMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)

RWRNMSK - Rx Warning Interrupt Mask 0b0..Rx Warning Interrupt disabled. 0b1..Rx Warning Interrupt enabled.

◆ CAN_CTRL1_SMP [1/5]

#define CAN_CTRL1_SMP ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

SMP - CAN Bit Sampling 0b0..Just one sample is used to determine the bit value. 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.

◆ CAN_CTRL1_SMP [2/5]

#define CAN_CTRL1_SMP ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

SMP - CAN Bit Sampling 0b0..Just one sample is used to determine the bit value. 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.

◆ CAN_CTRL1_SMP [3/5]

#define CAN_CTRL1_SMP ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

SMP - CAN Bit Sampling 0b0..Just one sample is used to determine the bit value. 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.

◆ CAN_CTRL1_SMP [4/5]

#define CAN_CTRL1_SMP ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

SMP - CAN Bit Sampling 0b0..Just one sample is used to determine the bit value. 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.

◆ CAN_CTRL1_SMP [5/5]

#define CAN_CTRL1_SMP ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)

SMP - CAN Bit Sampling 0b0..Just one sample is used to determine the bit value. 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.

◆ CAN_CTRL1_TSYN [1/5]

#define CAN_CTRL1_TSYN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

TSYN - Timer Sync 0b0..Timer Sync feature disabled 0b1..Timer Sync feature enabled

◆ CAN_CTRL1_TSYN [2/5]

#define CAN_CTRL1_TSYN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

TSYN - Timer Sync 0b0..Timer Sync feature disabled 0b1..Timer Sync feature enabled

◆ CAN_CTRL1_TSYN [3/5]

#define CAN_CTRL1_TSYN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

TSYN - Timer Sync 0b0..Timer Sync feature disabled 0b1..Timer Sync feature enabled

◆ CAN_CTRL1_TSYN [4/5]

#define CAN_CTRL1_TSYN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

TSYN - Timer Sync 0b0..Timer Sync feature disabled 0b1..Timer Sync feature enabled

◆ CAN_CTRL1_TSYN [5/5]

#define CAN_CTRL1_TSYN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)

TSYN - Timer Sync 0b0..Timer Sync feature disabled 0b1..Timer Sync feature enabled

◆ CAN_CTRL1_TWRNMSK [1/5]

#define CAN_CTRL1_TWRNMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

TWRNMSK - Tx Warning Interrupt Mask 0b0..Tx Warning Interrupt disabled. 0b1..Tx Warning Interrupt enabled.

◆ CAN_CTRL1_TWRNMSK [2/5]

#define CAN_CTRL1_TWRNMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

TWRNMSK - Tx Warning Interrupt Mask 0b0..Tx Warning Interrupt disabled. 0b1..Tx Warning Interrupt enabled.

◆ CAN_CTRL1_TWRNMSK [3/5]

#define CAN_CTRL1_TWRNMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

TWRNMSK - Tx Warning Interrupt Mask 0b0..Tx Warning Interrupt disabled. 0b1..Tx Warning Interrupt enabled.

◆ CAN_CTRL1_TWRNMSK [4/5]

#define CAN_CTRL1_TWRNMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

TWRNMSK - Tx Warning Interrupt Mask 0b0..Tx Warning Interrupt disabled. 0b1..Tx Warning Interrupt enabled.

◆ CAN_CTRL1_TWRNMSK [5/5]

#define CAN_CTRL1_TWRNMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)

TWRNMSK - Tx Warning Interrupt Mask 0b0..Tx Warning Interrupt disabled. 0b1..Tx Warning Interrupt enabled.

◆ CAN_CTRL2_BOFFDONEMSK

#define CAN_CTRL2_BOFFDONEMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)

BOFFDONEMSK - Bus Off Done Interrupt Mask 0b0..Bus Off Done interrupt disabled. 0b1..Bus Off Done interrupt enabled.

◆ CAN_CTRL2_EACEN [1/5]

#define CAN_CTRL2_EACEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.

◆ CAN_CTRL2_EACEN [2/5]

#define CAN_CTRL2_EACEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.

◆ CAN_CTRL2_EACEN [3/5]

#define CAN_CTRL2_EACEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.

◆ CAN_CTRL2_EACEN [4/5]

#define CAN_CTRL2_EACEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.

◆ CAN_CTRL2_EACEN [5/5]

#define CAN_CTRL2_EACEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)

EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.

◆ CAN_CTRL2_MRP [1/5]

#define CAN_CTRL2_MRP ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

MRP - Mailboxes Reception Priority 0b0..Matching starts from Rx FIFO and continues on Mailboxes. 0b1..Matching starts from Mailboxes and continues on Rx FIFO.

◆ CAN_CTRL2_MRP [2/5]

#define CAN_CTRL2_MRP ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

MRP - Mailboxes Reception Priority 0b0..Matching starts from Rx FIFO and continues on Mailboxes. 0b1..Matching starts from Mailboxes and continues on Rx FIFO.

◆ CAN_CTRL2_MRP [3/5]

#define CAN_CTRL2_MRP ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

MRP - Mailboxes Reception Priority 0b0..Matching starts from Rx FIFO and continues on Mailboxes. 0b1..Matching starts from Mailboxes and continues on Rx FIFO.

◆ CAN_CTRL2_MRP [4/5]

#define CAN_CTRL2_MRP ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

MRP - Mailboxes Reception Priority 0b0..Matching starts from Rx FIFO and continues on Mailboxes. 0b1..Matching starts from Mailboxes and continues on Rx FIFO.

◆ CAN_CTRL2_MRP [5/5]

#define CAN_CTRL2_MRP ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)

MRP - Mailboxes Reception Priority 0b0..Matching starts from Rx FIFO and continues on Mailboxes. 0b1..Matching starts from Mailboxes and continues on Rx FIFO.

◆ CAN_CTRL2_RRS [1/5]

#define CAN_CTRL2_RRS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

RRS - Remote Request Storing 0b0..Remote Response Frame is generated. 0b1..Remote Request Frame is stored.

◆ CAN_CTRL2_RRS [2/5]

#define CAN_CTRL2_RRS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

RRS - Remote Request Storing 0b0..Remote Response Frame is generated. 0b1..Remote Request Frame is stored.

◆ CAN_CTRL2_RRS [3/5]

#define CAN_CTRL2_RRS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

RRS - Remote Request Storing 0b0..Remote Response Frame is generated. 0b1..Remote Request Frame is stored.

◆ CAN_CTRL2_RRS [4/5]

#define CAN_CTRL2_RRS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

RRS - Remote Request Storing 0b0..Remote Response Frame is generated. 0b1..Remote Request Frame is stored.

◆ CAN_CTRL2_RRS [5/5]

#define CAN_CTRL2_RRS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)

RRS - Remote Request Storing 0b0..Remote Response Frame is generated. 0b1..Remote Request Frame is stored.

◆ CAN_CTRL2_WRMFRZ [1/4]

#define CAN_CTRL2_WRMFRZ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

WRMFRZ - Write-Access To Memory In Freeze Mode 0b0..Maintain the write access restrictions. 0b1..Enable unrestricted write access to FlexCAN memory.

◆ CAN_CTRL2_WRMFRZ [2/4]

#define CAN_CTRL2_WRMFRZ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

WRMFRZ - Write-Access To Memory In Freeze Mode 0b0..Maintain the write access restrictions. 0b1..Enable unrestricted write access to FlexCAN memory.

◆ CAN_CTRL2_WRMFRZ [3/4]

#define CAN_CTRL2_WRMFRZ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

WRMFRZ - Write-Access To Memory In Freeze Mode 0b0..Maintain the write access restrictions. 0b1..Enable unrestricted write access to FlexCAN memory.

◆ CAN_CTRL2_WRMFRZ [4/4]

#define CAN_CTRL2_WRMFRZ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)

WRMFRZ - Write-Access To Memory In Freeze Mode 0b0..Maintain the write access restrictions. 0b1..Enable unrestricted write access to FlexCAN memory.

◆ CAN_ESR1_ACKERR [1/5]

#define CAN_ESR1_ACKERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

ACKERR - Acknowledge Error 0b0..No such occurrence. 0b1..An ACK error occurred since last read of this register.

◆ CAN_ESR1_ACKERR [2/5]

#define CAN_ESR1_ACKERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

ACKERR - Acknowledge Error 0b0..No such occurrence. 0b1..An ACK error occurred since last read of this register.

◆ CAN_ESR1_ACKERR [3/5]

#define CAN_ESR1_ACKERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

ACKERR - Acknowledge Error 0b0..No such occurrence. 0b1..An ACK error occurred since last read of this register.

◆ CAN_ESR1_ACKERR [4/5]

#define CAN_ESR1_ACKERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

ACKERR - Acknowledge Error 0b0..No such occurrence. 0b1..An ACK error occurred since last read of this register.

◆ CAN_ESR1_ACKERR [5/5]

#define CAN_ESR1_ACKERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)

ACKERR - Acknowledge Error 0b0..No such occurrence. 0b1..An ACK error occurred since last read of this register.

◆ CAN_ESR1_BIT0ERR [1/5]

#define CAN_ESR1_BIT0ERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

BIT0ERR - Bit0 Error 0b0..No such occurrence. 0b1..At least one bit sent as dominant is received as recessive.

◆ CAN_ESR1_BIT0ERR [2/5]

#define CAN_ESR1_BIT0ERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

BIT0ERR - Bit0 Error 0b0..No such occurrence. 0b1..At least one bit sent as dominant is received as recessive.

◆ CAN_ESR1_BIT0ERR [3/5]

#define CAN_ESR1_BIT0ERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

BIT0ERR - Bit0 Error 0b0..No such occurrence. 0b1..At least one bit sent as dominant is received as recessive.

◆ CAN_ESR1_BIT0ERR [4/5]

#define CAN_ESR1_BIT0ERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

BIT0ERR - Bit0 Error 0b0..No such occurrence. 0b1..At least one bit sent as dominant is received as recessive.

◆ CAN_ESR1_BIT0ERR [5/5]

#define CAN_ESR1_BIT0ERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)

BIT0ERR - Bit0 Error 0b0..No such occurrence. 0b1..At least one bit sent as dominant is received as recessive.

◆ CAN_ESR1_BIT1ERR [1/5]

#define CAN_ESR1_BIT1ERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

BIT1ERR - Bit1 Error 0b0..No such occurrence. 0b1..At least one bit sent as recessive is received as dominant.

◆ CAN_ESR1_BIT1ERR [2/5]

#define CAN_ESR1_BIT1ERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

BIT1ERR - Bit1 Error 0b0..No such occurrence. 0b1..At least one bit sent as recessive is received as dominant.

◆ CAN_ESR1_BIT1ERR [3/5]

#define CAN_ESR1_BIT1ERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

BIT1ERR - Bit1 Error 0b0..No such occurrence. 0b1..At least one bit sent as recessive is received as dominant.

◆ CAN_ESR1_BIT1ERR [4/5]

#define CAN_ESR1_BIT1ERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

BIT1ERR - Bit1 Error 0b0..No such occurrence. 0b1..At least one bit sent as recessive is received as dominant.

◆ CAN_ESR1_BIT1ERR [5/5]

#define CAN_ESR1_BIT1ERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)

BIT1ERR - Bit1 Error 0b0..No such occurrence. 0b1..At least one bit sent as recessive is received as dominant.

◆ CAN_ESR1_BOFFDONEINT

#define CAN_ESR1_BOFFDONEINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)

BOFFDONEINT - Bus Off Done Interrupt 0b0..No such occurrence. 0b1..FlexCAN module has completed Bus Off process.

◆ CAN_ESR1_BOFFINT [1/5]

#define CAN_ESR1_BOFFINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

BOFFINT - Bus Off Interrupt 0b0..No such occurrence. 0b1..FlexCAN module entered Bus Off state.

◆ CAN_ESR1_BOFFINT [2/5]

#define CAN_ESR1_BOFFINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

BOFFINT - Bus Off Interrupt 0b0..No such occurrence. 0b1..FlexCAN module entered Bus Off state.

◆ CAN_ESR1_BOFFINT [3/5]

#define CAN_ESR1_BOFFINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

BOFFINT - Bus Off Interrupt 0b0..No such occurrence. 0b1..FlexCAN module entered Bus Off state.

◆ CAN_ESR1_BOFFINT [4/5]

#define CAN_ESR1_BOFFINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

BOFFINT - Bus Off Interrupt 0b0..No such occurrence. 0b1..FlexCAN module entered Bus Off state.

◆ CAN_ESR1_BOFFINT [5/5]

#define CAN_ESR1_BOFFINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)

BOFFINT - Bus Off Interrupt 0b0..No such occurrence. 0b1..FlexCAN module entered Bus Off state.

◆ CAN_ESR1_CRCERR [1/5]

#define CAN_ESR1_CRCERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

CRCERR - Cyclic Redundancy Check Error 0b0..No such occurrence. 0b1..A CRC error occurred since last read of this register.

◆ CAN_ESR1_CRCERR [2/5]

#define CAN_ESR1_CRCERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

CRCERR - Cyclic Redundancy Check Error 0b0..No such occurrence. 0b1..A CRC error occurred since last read of this register.

◆ CAN_ESR1_CRCERR [3/5]

#define CAN_ESR1_CRCERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

CRCERR - Cyclic Redundancy Check Error 0b0..No such occurrence. 0b1..A CRC error occurred since last read of this register.

◆ CAN_ESR1_CRCERR [4/5]

#define CAN_ESR1_CRCERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

CRCERR - Cyclic Redundancy Check Error 0b0..No such occurrence. 0b1..A CRC error occurred since last read of this register.

◆ CAN_ESR1_CRCERR [5/5]

#define CAN_ESR1_CRCERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)

CRCERR - Cyclic Redundancy Check Error 0b0..No such occurrence. 0b1..A CRC error occurred since last read of this register.

◆ CAN_ESR1_ERRINT [1/5]

#define CAN_ESR1_ERRINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

ERRINT - Error Interrupt 0b0..No such occurrence. 0b1..Indicates setting of any Error Bit in the Error and Status Register.

◆ CAN_ESR1_ERRINT [2/5]

#define CAN_ESR1_ERRINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

ERRINT - Error Interrupt 0b0..No such occurrence. 0b1..Indicates setting of any Error Bit in the Error and Status Register.

◆ CAN_ESR1_ERRINT [3/5]

#define CAN_ESR1_ERRINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

ERRINT - Error Interrupt 0b0..No such occurrence. 0b1..Indicates setting of any Error Bit in the Error and Status Register.

◆ CAN_ESR1_ERRINT [4/5]

#define CAN_ESR1_ERRINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

ERRINT - Error Interrupt 0b0..No such occurrence. 0b1..Indicates setting of any Error Bit in the Error and Status Register.

◆ CAN_ESR1_ERRINT [5/5]

#define CAN_ESR1_ERRINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)

ERRINT - Error Interrupt 0b0..No such occurrence. 0b1..Indicates setting of any Error Bit in the Error and Status Register.

◆ CAN_ESR1_ERROVR

#define CAN_ESR1_ERROVR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)

ERROVR - Error Overrun bit 0b0..Overrun has not occurred. 0b1..Overrun has occured.

◆ CAN_ESR1_FLTCONF [1/6]

#define CAN_ESR1_FLTCONF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

FLTCONF - Fault Confinement State 0b00..Error Active 0b01..Error Passive 0b1x..Bus Off

◆ CAN_ESR1_FLTCONF [2/6]

#define CAN_ESR1_FLTCONF ( x)    (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)

FLTCONF - Fault Confinement State 0b00..Error Active 0b01..Error Passive 0b1x..Bus Off

◆ CAN_ESR1_FLTCONF [3/6]

#define CAN_ESR1_FLTCONF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

FLTCONF - Fault Confinement State 0b00..Error Active 0b01..Error Passive 0b1x..Bus Off

◆ CAN_ESR1_FLTCONF [4/6]

#define CAN_ESR1_FLTCONF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

FLTCONF - Fault Confinement State 0b00..Error Active 0b01..Error Passive 0b1x..Bus Off

◆ CAN_ESR1_FLTCONF [5/6]

#define CAN_ESR1_FLTCONF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

FLTCONF - Fault Confinement State 0b00..Error Active 0b01..Error Passive 0b1x..Bus Off

◆ CAN_ESR1_FLTCONF [6/6]

#define CAN_ESR1_FLTCONF ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)

FLTCONF - Fault Confinement State 0b00..Error Active 0b01..Error Passive 0b1x..Bus Off

◆ CAN_ESR1_FRMERR [1/5]

#define CAN_ESR1_FRMERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

FRMERR - Form Error 0b0..No such occurrence. 0b1..A Form Error occurred since last read of this register.

◆ CAN_ESR1_FRMERR [2/5]

#define CAN_ESR1_FRMERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

FRMERR - Form Error 0b0..No such occurrence. 0b1..A Form Error occurred since last read of this register.

◆ CAN_ESR1_FRMERR [3/5]

#define CAN_ESR1_FRMERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

FRMERR - Form Error 0b0..No such occurrence. 0b1..A Form Error occurred since last read of this register.

◆ CAN_ESR1_FRMERR [4/5]

#define CAN_ESR1_FRMERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

FRMERR - Form Error 0b0..No such occurrence. 0b1..A Form Error occurred since last read of this register.

◆ CAN_ESR1_FRMERR [5/5]

#define CAN_ESR1_FRMERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)

FRMERR - Form Error 0b0..No such occurrence. 0b1..A Form Error occurred since last read of this register.

◆ CAN_ESR1_IDLE [1/5]

#define CAN_ESR1_IDLE ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

IDLE 0b0..No such occurrence. 0b1..CAN bus is now IDLE.

◆ CAN_ESR1_IDLE [2/5]

#define CAN_ESR1_IDLE ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

IDLE 0b0..No such occurrence. 0b1..CAN bus is now IDLE.

◆ CAN_ESR1_IDLE [3/5]

#define CAN_ESR1_IDLE ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

IDLE 0b0..No such occurrence. 0b1..CAN bus is now IDLE.

◆ CAN_ESR1_IDLE [4/5]

#define CAN_ESR1_IDLE ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

IDLE 0b0..No such occurrence. 0b1..CAN bus is now IDLE.

◆ CAN_ESR1_IDLE [5/5]

#define CAN_ESR1_IDLE ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)

IDLE 0b0..No such occurrence. 0b1..CAN bus is now IDLE.

◆ CAN_ESR1_RWRNINT [1/5]

#define CAN_ESR1_RWRNINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

RWRNINT - Rx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_RWRNINT [2/5]

#define CAN_ESR1_RWRNINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

RWRNINT - Rx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_RWRNINT [3/5]

#define CAN_ESR1_RWRNINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

RWRNINT - Rx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_RWRNINT [4/5]

#define CAN_ESR1_RWRNINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

RWRNINT - Rx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_RWRNINT [5/5]

#define CAN_ESR1_RWRNINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)

RWRNINT - Rx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_RX [1/5]

#define CAN_ESR1_RX ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

RX - FlexCAN In Reception 0b0..FlexCAN is not receiving a message. 0b1..FlexCAN is receiving a message.

◆ CAN_ESR1_RX [2/5]

#define CAN_ESR1_RX ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

RX - FlexCAN In Reception 0b0..FlexCAN is not receiving a message. 0b1..FlexCAN is receiving a message.

◆ CAN_ESR1_RX [3/5]

#define CAN_ESR1_RX ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

RX - FlexCAN In Reception 0b0..FlexCAN is not receiving a message. 0b1..FlexCAN is receiving a message.

◆ CAN_ESR1_RX [4/5]

#define CAN_ESR1_RX ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

RX - FlexCAN In Reception 0b0..FlexCAN is not receiving a message. 0b1..FlexCAN is receiving a message.

◆ CAN_ESR1_RX [5/5]

#define CAN_ESR1_RX ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)

RX - FlexCAN In Reception 0b0..FlexCAN is not receiving a message. 0b1..FlexCAN is receiving a message.

◆ CAN_ESR1_RXWRN [1/5]

#define CAN_ESR1_RXWRN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

RXWRN - Rx Error Warning 0b0..No such occurrence. 0b1..RXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_RXWRN [2/5]

#define CAN_ESR1_RXWRN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

RXWRN - Rx Error Warning 0b0..No such occurrence. 0b1..RXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_RXWRN [3/5]

#define CAN_ESR1_RXWRN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

RXWRN - Rx Error Warning 0b0..No such occurrence. 0b1..RXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_RXWRN [4/5]

#define CAN_ESR1_RXWRN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

RXWRN - Rx Error Warning 0b0..No such occurrence. 0b1..RXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_RXWRN [5/5]

#define CAN_ESR1_RXWRN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)

RXWRN - Rx Error Warning 0b0..No such occurrence. 0b1..RXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_STFERR [1/5]

#define CAN_ESR1_STFERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

STFERR - Stuffing Error 0b0..No such occurrence. 0b1..A Stuffing Error occurred since last read of this register.

◆ CAN_ESR1_STFERR [2/5]

#define CAN_ESR1_STFERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

STFERR - Stuffing Error 0b0..No such occurrence. 0b1..A Stuffing Error occurred since last read of this register.

◆ CAN_ESR1_STFERR [3/5]

#define CAN_ESR1_STFERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

STFERR - Stuffing Error 0b0..No such occurrence. 0b1..A Stuffing Error occurred since last read of this register.

◆ CAN_ESR1_STFERR [4/5]

#define CAN_ESR1_STFERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

STFERR - Stuffing Error 0b0..No such occurrence. 0b1..A Stuffing Error occurred since last read of this register.

◆ CAN_ESR1_STFERR [5/5]

#define CAN_ESR1_STFERR ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)

STFERR - Stuffing Error 0b0..No such occurrence. 0b1..A Stuffing Error occurred since last read of this register.

◆ CAN_ESR1_SYNCH [1/5]

#define CAN_ESR1_SYNCH ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

SYNCH - CAN Synchronization Status 0b0..FlexCAN is not synchronized to the CAN bus. 0b1..FlexCAN is synchronized to the CAN bus.

◆ CAN_ESR1_SYNCH [2/5]

#define CAN_ESR1_SYNCH ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

SYNCH - CAN Synchronization Status 0b0..FlexCAN is not synchronized to the CAN bus. 0b1..FlexCAN is synchronized to the CAN bus.

◆ CAN_ESR1_SYNCH [3/5]

#define CAN_ESR1_SYNCH ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

SYNCH - CAN Synchronization Status 0b0..FlexCAN is not synchronized to the CAN bus. 0b1..FlexCAN is synchronized to the CAN bus.

◆ CAN_ESR1_SYNCH [4/5]

#define CAN_ESR1_SYNCH ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

SYNCH - CAN Synchronization Status 0b0..FlexCAN is not synchronized to the CAN bus. 0b1..FlexCAN is synchronized to the CAN bus.

◆ CAN_ESR1_SYNCH [5/5]

#define CAN_ESR1_SYNCH ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)

SYNCH - CAN Synchronization Status 0b0..FlexCAN is not synchronized to the CAN bus. 0b1..FlexCAN is synchronized to the CAN bus.

◆ CAN_ESR1_TWRNINT [1/5]

#define CAN_ESR1_TWRNINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

TWRNINT - Tx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_TWRNINT [2/5]

#define CAN_ESR1_TWRNINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

TWRNINT - Tx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_TWRNINT [3/5]

#define CAN_ESR1_TWRNINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

TWRNINT - Tx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_TWRNINT [4/5]

#define CAN_ESR1_TWRNINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

TWRNINT - Tx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_TWRNINT [5/5]

#define CAN_ESR1_TWRNINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)

TWRNINT - Tx Warning Interrupt Flag 0b0..No such occurrence. 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.

◆ CAN_ESR1_TX [1/5]

#define CAN_ESR1_TX ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

TX - FlexCAN In Transmission 0b0..FlexCAN is not transmitting a message. 0b1..FlexCAN is transmitting a message.

◆ CAN_ESR1_TX [2/5]

#define CAN_ESR1_TX ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

TX - FlexCAN In Transmission 0b0..FlexCAN is not transmitting a message. 0b1..FlexCAN is transmitting a message.

◆ CAN_ESR1_TX [3/5]

#define CAN_ESR1_TX ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

TX - FlexCAN In Transmission 0b0..FlexCAN is not transmitting a message. 0b1..FlexCAN is transmitting a message.

◆ CAN_ESR1_TX [4/5]

#define CAN_ESR1_TX ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

TX - FlexCAN In Transmission 0b0..FlexCAN is not transmitting a message. 0b1..FlexCAN is transmitting a message.

◆ CAN_ESR1_TX [5/5]

#define CAN_ESR1_TX ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)

TX - FlexCAN In Transmission 0b0..FlexCAN is not transmitting a message. 0b1..FlexCAN is transmitting a message.

◆ CAN_ESR1_TXWRN [1/5]

#define CAN_ESR1_TXWRN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

TXWRN - TX Error Warning 0b0..No such occurrence. 0b1..TXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_TXWRN [2/5]

#define CAN_ESR1_TXWRN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

TXWRN - TX Error Warning 0b0..No such occurrence. 0b1..TXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_TXWRN [3/5]

#define CAN_ESR1_TXWRN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

TXWRN - TX Error Warning 0b0..No such occurrence. 0b1..TXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_TXWRN [4/5]

#define CAN_ESR1_TXWRN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

TXWRN - TX Error Warning 0b0..No such occurrence. 0b1..TXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_TXWRN [5/5]

#define CAN_ESR1_TXWRN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)

TXWRN - TX Error Warning 0b0..No such occurrence. 0b1..TXERRCNT is greater than or equal to 96.

◆ CAN_ESR1_WAKINT [1/5]

#define CAN_ESR1_WAKINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

WAKINT - Wake-Up Interrupt 0b0..No such occurrence. 0b1..Indicates a recessive to dominant transition was received on the CAN bus.

◆ CAN_ESR1_WAKINT [2/5]

#define CAN_ESR1_WAKINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

WAKINT - Wake-Up Interrupt 0b0..No such occurrence. 0b1..Indicates a recessive to dominant transition was received on the CAN bus.

◆ CAN_ESR1_WAKINT [3/5]

#define CAN_ESR1_WAKINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

WAKINT - Wake-Up Interrupt 0b0..No such occurrence. 0b1..Indicates a recessive to dominant transition was received on the CAN bus.

◆ CAN_ESR1_WAKINT [4/5]

#define CAN_ESR1_WAKINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

WAKINT - Wake-Up Interrupt 0b0..No such occurrence. 0b1..Indicates a recessive to dominant transition was received on the CAN bus.

◆ CAN_ESR1_WAKINT [5/5]

#define CAN_ESR1_WAKINT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)

WAKINT - Wake-Up Interrupt 0b0..No such occurrence. 0b1..Indicates a recessive to dominant transition was received on the CAN bus.

◆ CAN_ESR2_IMB [1/5]

#define CAN_ESR2_IMB ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

IMB - Inactive Mailbox 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.

◆ CAN_ESR2_IMB [2/5]

#define CAN_ESR2_IMB ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

IMB - Inactive Mailbox 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.

◆ CAN_ESR2_IMB [3/5]

#define CAN_ESR2_IMB ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

IMB - Inactive Mailbox 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.

◆ CAN_ESR2_IMB [4/5]

#define CAN_ESR2_IMB ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

IMB - Inactive Mailbox 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.

◆ CAN_ESR2_IMB [5/5]

#define CAN_ESR2_IMB ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)

IMB - Inactive Mailbox 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.

◆ CAN_ESR2_VPS [1/5]

#define CAN_ESR2_VPS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

VPS - Valid Priority Status 0b0..Contents of IMB and LPTM are invalid. 0b1..Contents of IMB and LPTM are valid.

◆ CAN_ESR2_VPS [2/5]

#define CAN_ESR2_VPS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

VPS - Valid Priority Status 0b0..Contents of IMB and LPTM are invalid. 0b1..Contents of IMB and LPTM are valid.

◆ CAN_ESR2_VPS [3/5]

#define CAN_ESR2_VPS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

VPS - Valid Priority Status 0b0..Contents of IMB and LPTM are invalid. 0b1..Contents of IMB and LPTM are valid.

◆ CAN_ESR2_VPS [4/5]

#define CAN_ESR2_VPS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

VPS - Valid Priority Status 0b0..Contents of IMB and LPTM are invalid. 0b1..Contents of IMB and LPTM are valid.

◆ CAN_ESR2_VPS [5/5]

#define CAN_ESR2_VPS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)

VPS - Valid Priority Status 0b0..Contents of IMB and LPTM are invalid. 0b1..Contents of IMB and LPTM are valid.

◆ CAN_IFLAG1_BUF0I [1/4]

#define CAN_IFLAG1_BUF0I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)

BUF0I - Buffer MB0 Interrupt Or "reserved" 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

◆ CAN_IFLAG1_BUF0I [2/4]

#define CAN_IFLAG1_BUF0I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)

BUF0I - Buffer MB0 Interrupt Or "reserved" 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

◆ CAN_IFLAG1_BUF0I [3/4]

#define CAN_IFLAG1_BUF0I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)

BUF0I - Buffer MB0 Interrupt Or "reserved" 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

◆ CAN_IFLAG1_BUF0I [4/4]

#define CAN_IFLAG1_BUF0I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)

BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

◆ CAN_IFLAG1_BUF31TO8I [1/6]

#define CAN_IFLAG1_BUF31TO8I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

BUF31TO8I - Buffer MBi Interrupt 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception. 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception.

◆ CAN_IFLAG1_BUF31TO8I [2/6]

#define CAN_IFLAG1_BUF31TO8I ( x)    (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)

BUF31TO8I - Buffer MBi Interrupt 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception. 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception.

◆ CAN_IFLAG1_BUF31TO8I [3/6]

#define CAN_IFLAG1_BUF31TO8I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

BUF31TO8I - Buffer MBi Interrupt 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception. 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception.

◆ CAN_IFLAG1_BUF31TO8I [4/6]

#define CAN_IFLAG1_BUF31TO8I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

BUF31TO8I - Buffer MBi Interrupt 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception. 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception.

◆ CAN_IFLAG1_BUF31TO8I [5/6]

#define CAN_IFLAG1_BUF31TO8I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

BUF31TO8I - Buffer MBi Interrupt 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception. 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception.

◆ CAN_IFLAG1_BUF31TO8I [6/6]

#define CAN_IFLAG1_BUF31TO8I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)

BUF31TO8I - Buffer MBi Interrupt 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception. 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception.

◆ CAN_IFLAG1_BUF4TO1I [1/4]

#define CAN_IFLAG1_BUF4TO1I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)

BUF4TO1I - Buffer MB i Interrupt Or "reserved" 0b0000..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b0001..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

◆ CAN_IFLAG1_BUF4TO1I [2/4]

#define CAN_IFLAG1_BUF4TO1I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)

BUF4TO1I - Buffer MB i Interrupt Or "reserved" 0b0000..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b0001..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

◆ CAN_IFLAG1_BUF4TO1I [3/4]

#define CAN_IFLAG1_BUF4TO1I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)

BUF4TO1I - Buffer MB i Interrupt Or "reserved" 0b0000..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b0001..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

◆ CAN_IFLAG1_BUF4TO1I [4/4]

#define CAN_IFLAG1_BUF4TO1I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)

BUF4TO1I - Buffer MB i Interrupt Or "reserved" 0b0000..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0. 0b0001..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.

◆ CAN_IFLAG1_BUF5I [1/5]

#define CAN_IFLAG1_BUF5I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1

BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.

◆ CAN_IFLAG1_BUF5I [2/5]

#define CAN_IFLAG1_BUF5I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1

BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.

◆ CAN_IFLAG1_BUF5I [3/5]

#define CAN_IFLAG1_BUF5I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1

BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.

◆ CAN_IFLAG1_BUF5I [4/5]

#define CAN_IFLAG1_BUF5I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1

BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.

◆ CAN_IFLAG1_BUF5I [5/5]

#define CAN_IFLAG1_BUF5I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)

BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO" 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.

◆ CAN_IFLAG1_BUF6I [1/5]

#define CAN_IFLAG1_BUF6I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning" 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF6I [2/5]

#define CAN_IFLAG1_BUF6I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning" 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF6I [3/5]

#define CAN_IFLAG1_BUF6I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning" 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF6I [4/5]

#define CAN_IFLAG1_BUF6I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning" 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF6I [5/5]

#define CAN_IFLAG1_BUF6I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)

BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning" 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF7I [1/5]

#define CAN_IFLAG1_BUF7I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow" 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF7I [2/5]

#define CAN_IFLAG1_BUF7I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow" 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF7I [3/5]

#define CAN_IFLAG1_BUF7I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow" 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF7I [4/5]

#define CAN_IFLAG1_BUF7I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow" 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1

◆ CAN_IFLAG1_BUF7I [5/5]

#define CAN_IFLAG1_BUF7I ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)

BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow" 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1

◆ CAN_IMASK1_BUF31TO0M

#define CAN_IMASK1_BUF31TO0M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)

BUF31TO0M - Buffer MB i Mask 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled. 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled.

◆ CAN_IMASK1_BUFLM [1/5]

#define CAN_IMASK1_BUFLM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)

BUFLM - Buffer MB i Mask 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled. 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled.

◆ CAN_IMASK1_BUFLM [2/5]

#define CAN_IMASK1_BUFLM ( x)    (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)

BUFLM - Buffer MB i Mask 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled. 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled.

◆ CAN_IMASK1_BUFLM [3/5]

#define CAN_IMASK1_BUFLM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)

BUFLM - Buffer MB i Mask 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled. 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled.

◆ CAN_IMASK1_BUFLM [4/5]

#define CAN_IMASK1_BUFLM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)

BUFLM - Buffer MB i Mask 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled. 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled.

◆ CAN_IMASK1_BUFLM [5/5]

#define CAN_IMASK1_BUFLM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)

BUFLM - Buffer MB i Mask 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled. 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled.

◆ CAN_MCR_AEN [1/5]

#define CAN_MCR_AEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

AEN - Abort Enable 0b0..Abort disabled. 0b1..Abort enabled.

◆ CAN_MCR_AEN [2/5]

#define CAN_MCR_AEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

AEN - Abort Enable 0b0..Abort disabled. 0b1..Abort enabled.

◆ CAN_MCR_AEN [3/5]

#define CAN_MCR_AEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

AEN - Abort Enable 0b0..Abort disabled. 0b1..Abort enabled.

◆ CAN_MCR_AEN [4/5]

#define CAN_MCR_AEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

AEN - Abort Enable 0b0..Abort disabled. 0b1..Abort enabled.

◆ CAN_MCR_AEN [5/5]

#define CAN_MCR_AEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)

AEN - Abort Enable 0b0..Abort disabled. 0b1..Abort enabled.

◆ CAN_MCR_DMA

#define CAN_MCR_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)

DMA - DMA Enable 0b0..DMA feature for RX FIFO disabled. 0b1..DMA feature for RX FIFO enabled.

◆ CAN_MCR_DOZE

#define CAN_MCR_DOZE ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)

DOZE - Doze Mode Enable 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested. 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.

◆ CAN_MCR_FRZ [1/5]

#define CAN_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

FRZ - Freeze Enable 0b0..Not enabled to enter Freeze mode. 0b1..Enabled to enter Freeze mode.

◆ CAN_MCR_FRZ [2/5]

#define CAN_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

FRZ - Freeze Enable 0b0..Not enabled to enter Freeze mode. 0b1..Enabled to enter Freeze mode.

◆ CAN_MCR_FRZ [3/5]

#define CAN_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

FRZ - Freeze Enable 0b0..Not enabled to enter Freeze mode. 0b1..Enabled to enter Freeze mode.

◆ CAN_MCR_FRZ [4/5]

#define CAN_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

FRZ - Freeze Enable 0b0..Not enabled to enter Freeze mode. 0b1..Enabled to enter Freeze mode.

◆ CAN_MCR_FRZ [5/5]

#define CAN_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)

FRZ - Freeze Enable 0b0..Not enabled to enter Freeze mode. 0b1..Enabled to enter Freeze mode.

◆ CAN_MCR_FRZACK [1/5]

#define CAN_MCR_FRZACK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

FRZACK - Freeze Mode Acknowledge 0b0..FlexCAN not in Freeze mode, prescaler running. 0b1..FlexCAN in Freeze mode, prescaler stopped.

◆ CAN_MCR_FRZACK [2/5]

#define CAN_MCR_FRZACK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

FRZACK - Freeze Mode Acknowledge 0b0..FlexCAN not in Freeze mode, prescaler running. 0b1..FlexCAN in Freeze mode, prescaler stopped.

◆ CAN_MCR_FRZACK [3/5]

#define CAN_MCR_FRZACK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

FRZACK - Freeze Mode Acknowledge 0b0..FlexCAN not in Freeze mode, prescaler running. 0b1..FlexCAN in Freeze mode, prescaler stopped.

◆ CAN_MCR_FRZACK [4/5]

#define CAN_MCR_FRZACK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

FRZACK - Freeze Mode Acknowledge 0b0..FlexCAN not in Freeze mode, prescaler running. 0b1..FlexCAN in Freeze mode, prescaler stopped.

◆ CAN_MCR_FRZACK [5/5]

#define CAN_MCR_FRZACK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)

FRZACK - Freeze Mode Acknowledge 0b0..FlexCAN not in Freeze mode, prescaler running. 0b1..FlexCAN in Freeze mode, prescaler stopped.

◆ CAN_MCR_HALT [1/5]

#define CAN_MCR_HALT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

HALT - Halt FlexCAN 0b0..No Freeze mode request. 0b1..Enters Freeze mode if the FRZ bit is asserted.

◆ CAN_MCR_HALT [2/5]

#define CAN_MCR_HALT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

HALT - Halt FlexCAN 0b0..No Freeze mode request. 0b1..Enters Freeze mode if the FRZ bit is asserted.

◆ CAN_MCR_HALT [3/5]

#define CAN_MCR_HALT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

HALT - Halt FlexCAN 0b0..No Freeze mode request. 0b1..Enters Freeze mode if the FRZ bit is asserted.

◆ CAN_MCR_HALT [4/5]

#define CAN_MCR_HALT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

HALT - Halt FlexCAN 0b0..No Freeze mode request. 0b1..Enters Freeze mode if the FRZ bit is asserted.

◆ CAN_MCR_HALT [5/5]

#define CAN_MCR_HALT ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)

HALT - Halt FlexCAN 0b0..No Freeze mode request. 0b1..Enters Freeze mode if the FRZ bit is asserted.

◆ CAN_MCR_IDAM [1/6]

#define CAN_MCR_IDAM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

IDAM - ID Acceptance Mode 0b00..Format A: One full ID (standard and extended) per ID Filter Table element. 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element. 0b11..Format D: All frames rejected.

◆ CAN_MCR_IDAM [2/6]

#define CAN_MCR_IDAM ( x)    (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)

IDAM - ID Acceptance Mode 0b00..Format A: One full ID (standard and extended) per ID Filter Table element. 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element. 0b11..Format D: All frames rejected.

◆ CAN_MCR_IDAM [3/6]

#define CAN_MCR_IDAM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

IDAM - ID Acceptance Mode 0b00..Format A: One full ID (standard and extended) per ID Filter Table element. 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element. 0b11..Format D: All frames rejected.

◆ CAN_MCR_IDAM [4/6]

#define CAN_MCR_IDAM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

IDAM - ID Acceptance Mode 0b00..Format A: One full ID (standard and extended) per ID Filter Table element. 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element. 0b11..Format D: All frames rejected.

◆ CAN_MCR_IDAM [5/6]

#define CAN_MCR_IDAM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

IDAM - ID Acceptance Mode 0b00..Format A: One full ID (standard and extended) per ID Filter Table element. 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element. 0b11..Format D: All frames rejected.

◆ CAN_MCR_IDAM [6/6]

#define CAN_MCR_IDAM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)

IDAM - ID Acceptance Mode 0b00..Format A: One full ID (standard and extended) per ID Filter Table element. 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element. 0b11..Format D: All frames rejected.

◆ CAN_MCR_IRMQ [1/5]

#define CAN_MCR_IRMQ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

IRMQ - Individual Rx Masking And Queue Enable 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 0b1..Individual Rx masking and queue feature are enabled.

◆ CAN_MCR_IRMQ [2/5]

#define CAN_MCR_IRMQ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

IRMQ - Individual Rx Masking And Queue Enable 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 0b1..Individual Rx masking and queue feature are enabled.

◆ CAN_MCR_IRMQ [3/5]

#define CAN_MCR_IRMQ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

IRMQ - Individual Rx Masking And Queue Enable 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 0b1..Individual Rx masking and queue feature are enabled.

◆ CAN_MCR_IRMQ [4/5]

#define CAN_MCR_IRMQ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

IRMQ - Individual Rx Masking And Queue Enable 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 0b1..Individual Rx masking and queue feature are enabled.

◆ CAN_MCR_IRMQ [5/5]

#define CAN_MCR_IRMQ ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)

IRMQ - Individual Rx Masking And Queue Enable 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. 0b1..Individual Rx masking and queue feature are enabled.

◆ CAN_MCR_LPMACK [1/5]

#define CAN_MCR_LPMACK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

LPMACK - Low-Power Mode Acknowledge 0b0..FlexCAN is not in a low-power mode. 0b1..FlexCAN is in a low-power mode.

◆ CAN_MCR_LPMACK [2/5]

#define CAN_MCR_LPMACK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

LPMACK - Low-Power Mode Acknowledge 0b0..FlexCAN is not in a low-power mode. 0b1..FlexCAN is in a low-power mode.

◆ CAN_MCR_LPMACK [3/5]

#define CAN_MCR_LPMACK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

LPMACK - Low-Power Mode Acknowledge 0b0..FlexCAN is not in a low-power mode. 0b1..FlexCAN is in a low-power mode.

◆ CAN_MCR_LPMACK [4/5]

#define CAN_MCR_LPMACK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

LPMACK - Low-Power Mode Acknowledge 0b0..FlexCAN is not in a low-power mode. 0b1..FlexCAN is in a low-power mode.

◆ CAN_MCR_LPMACK [5/5]

#define CAN_MCR_LPMACK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)

LPMACK - Low-Power Mode Acknowledge 0b0..FlexCAN is not in a low-power mode. 0b1..FlexCAN is in a low-power mode.

◆ CAN_MCR_LPRIOEN [1/5]

#define CAN_MCR_LPRIOEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

LPRIOEN - Local Priority Enable 0b0..Local Priority disabled. 0b1..Local Priority enabled.

◆ CAN_MCR_LPRIOEN [2/5]

#define CAN_MCR_LPRIOEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

LPRIOEN - Local Priority Enable 0b0..Local Priority disabled. 0b1..Local Priority enabled.

◆ CAN_MCR_LPRIOEN [3/5]

#define CAN_MCR_LPRIOEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

LPRIOEN - Local Priority Enable 0b0..Local Priority disabled. 0b1..Local Priority enabled.

◆ CAN_MCR_LPRIOEN [4/5]

#define CAN_MCR_LPRIOEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

LPRIOEN - Local Priority Enable 0b0..Local Priority disabled. 0b1..Local Priority enabled.

◆ CAN_MCR_LPRIOEN [5/5]

#define CAN_MCR_LPRIOEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)

LPRIOEN - Local Priority Enable 0b0..Local Priority disabled. 0b1..Local Priority enabled.

◆ CAN_MCR_MDIS [1/5]

#define CAN_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enable the FlexCAN module. 0b1..Disable the FlexCAN module.

◆ CAN_MCR_MDIS [2/5]

#define CAN_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enable the FlexCAN module. 0b1..Disable the FlexCAN module.

◆ CAN_MCR_MDIS [3/5]

#define CAN_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enable the FlexCAN module. 0b1..Disable the FlexCAN module.

◆ CAN_MCR_MDIS [4/5]

#define CAN_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enable the FlexCAN module. 0b1..Disable the FlexCAN module.

◆ CAN_MCR_MDIS [5/5]

#define CAN_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enable the FlexCAN module. 0b1..Disable the FlexCAN module.

◆ CAN_MCR_NOTRDY [1/5]

#define CAN_MCR_NOTRDY ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode , Stop mode or Freeze mode.

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode.

◆ CAN_MCR_NOTRDY [2/5]

#define CAN_MCR_NOTRDY ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode , Stop mode or Freeze mode.

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode.

◆ CAN_MCR_NOTRDY [3/5]

#define CAN_MCR_NOTRDY ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode , Stop mode or Freeze mode.

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode.

◆ CAN_MCR_NOTRDY [4/5]

#define CAN_MCR_NOTRDY ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode , Stop mode or Freeze mode.

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode.

◆ CAN_MCR_NOTRDY [5/5]

#define CAN_MCR_NOTRDY ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)

NOTRDY - FlexCAN Not Ready 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. 0b1..FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode.

◆ CAN_MCR_RFEN [1/5]

#define CAN_MCR_RFEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

RFEN - Rx FIFO Enable 0b0..Rx FIFO not enabled. 0b1..Rx FIFO enabled.

◆ CAN_MCR_RFEN [2/5]

#define CAN_MCR_RFEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

RFEN - Rx FIFO Enable 0b0..Rx FIFO not enabled. 0b1..Rx FIFO enabled.

◆ CAN_MCR_RFEN [3/5]

#define CAN_MCR_RFEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

RFEN - Rx FIFO Enable 0b0..Rx FIFO not enabled. 0b1..Rx FIFO enabled.

◆ CAN_MCR_RFEN [4/5]

#define CAN_MCR_RFEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

RFEN - Rx FIFO Enable 0b0..Rx FIFO not enabled. 0b1..Rx FIFO enabled.

◆ CAN_MCR_RFEN [5/5]

#define CAN_MCR_RFEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)

RFEN - Rx FIFO Enable 0b0..Rx FIFO not enabled. 0b1..Rx FIFO enabled.

◆ CAN_MCR_SLFWAK [1/5]

#define CAN_MCR_SLFWAK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

SLFWAK - Self Wake Up 0b0..FlexCAN Self Wake Up feature is disabled. 0b1..FlexCAN Self Wake Up feature is enabled.

◆ CAN_MCR_SLFWAK [2/5]

#define CAN_MCR_SLFWAK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

SLFWAK - Self Wake Up 0b0..FlexCAN Self Wake Up feature is disabled. 0b1..FlexCAN Self Wake Up feature is enabled.

◆ CAN_MCR_SLFWAK [3/5]

#define CAN_MCR_SLFWAK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

SLFWAK - Self Wake Up 0b0..FlexCAN Self Wake Up feature is disabled. 0b1..FlexCAN Self Wake Up feature is enabled.

◆ CAN_MCR_SLFWAK [4/5]

#define CAN_MCR_SLFWAK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

SLFWAK - Self Wake Up 0b0..FlexCAN Self Wake Up feature is disabled. 0b1..FlexCAN Self Wake Up feature is enabled.

◆ CAN_MCR_SLFWAK [5/5]

#define CAN_MCR_SLFWAK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)

SLFWAK - Self Wake Up 0b0..FlexCAN Self Wake Up feature is disabled. 0b1..FlexCAN Self Wake Up feature is enabled.

◆ CAN_MCR_SOFTRST [1/5]

#define CAN_MCR_SOFTRST ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

SOFTRST - Soft Reset 0b0..No reset request. 0b1..Resets the registers affected by soft reset.

◆ CAN_MCR_SOFTRST [2/5]

#define CAN_MCR_SOFTRST ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

SOFTRST - Soft Reset 0b0..No reset request. 0b1..Resets the registers affected by soft reset.

◆ CAN_MCR_SOFTRST [3/5]

#define CAN_MCR_SOFTRST ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

SOFTRST - Soft Reset 0b0..No reset request. 0b1..Resets the registers affected by soft reset.

◆ CAN_MCR_SOFTRST [4/5]

#define CAN_MCR_SOFTRST ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

SOFTRST - Soft Reset 0b0..No reset request. 0b1..Resets the registers affected by soft reset.

◆ CAN_MCR_SOFTRST [5/5]

#define CAN_MCR_SOFTRST ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)

SOFTRST - Soft Reset 0b0..No reset request. 0b1..Resets the registers affected by soft reset.

◆ CAN_MCR_SRXDIS [1/5]

#define CAN_MCR_SRXDIS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

SRXDIS - Self Reception Disable 0b0..Self reception enabled. 0b1..Self reception disabled.

◆ CAN_MCR_SRXDIS [2/5]

#define CAN_MCR_SRXDIS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

SRXDIS - Self Reception Disable 0b0..Self reception enabled. 0b1..Self reception disabled.

◆ CAN_MCR_SRXDIS [3/5]

#define CAN_MCR_SRXDIS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

SRXDIS - Self Reception Disable 0b0..Self reception enabled. 0b1..Self reception disabled.

◆ CAN_MCR_SRXDIS [4/5]

#define CAN_MCR_SRXDIS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

SRXDIS - Self Reception Disable 0b0..Self reception enabled. 0b1..Self reception disabled.

◆ CAN_MCR_SRXDIS [5/5]

#define CAN_MCR_SRXDIS ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)

SRXDIS - Self Reception Disable 0b0..Self reception enabled. 0b1..Self reception disabled.

◆ CAN_MCR_SUPV [1/5]

#define CAN_MCR_SUPV ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses . 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location .

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location.

◆ CAN_MCR_SUPV [2/5]

#define CAN_MCR_SUPV ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses . 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location .

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location.

◆ CAN_MCR_SUPV [3/5]

#define CAN_MCR_SUPV ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses . 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location .

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location.

◆ CAN_MCR_SUPV [4/5]

#define CAN_MCR_SUPV ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses . 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location .

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location.

◆ CAN_MCR_SUPV [5/5]

#define CAN_MCR_SUPV ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)

SUPV - Supervisor Mode 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location.

◆ CAN_MCR_WAKMSK [1/5]

#define CAN_MCR_WAKMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

WAKMSK - Wake Up Interrupt Mask 0b0..Wake Up Interrupt is disabled. 0b1..Wake Up Interrupt is enabled.

◆ CAN_MCR_WAKMSK [2/5]

#define CAN_MCR_WAKMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

WAKMSK - Wake Up Interrupt Mask 0b0..Wake Up Interrupt is disabled. 0b1..Wake Up Interrupt is enabled.

◆ CAN_MCR_WAKMSK [3/5]

#define CAN_MCR_WAKMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

WAKMSK - Wake Up Interrupt Mask 0b0..Wake Up Interrupt is disabled. 0b1..Wake Up Interrupt is enabled.

◆ CAN_MCR_WAKMSK [4/5]

#define CAN_MCR_WAKMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

WAKMSK - Wake Up Interrupt Mask 0b0..Wake Up Interrupt is disabled. 0b1..Wake Up Interrupt is enabled.

◆ CAN_MCR_WAKMSK [5/5]

#define CAN_MCR_WAKMSK ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)

WAKMSK - Wake Up Interrupt Mask 0b0..Wake Up Interrupt is disabled. 0b1..Wake Up Interrupt is enabled.

◆ CAN_MCR_WAKSRC [1/5]

#define CAN_MCR_WAKSRC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

WAKSRC - Wake Up Source 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.

◆ CAN_MCR_WAKSRC [2/5]

#define CAN_MCR_WAKSRC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

WAKSRC - Wake Up Source 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.

◆ CAN_MCR_WAKSRC [3/5]

#define CAN_MCR_WAKSRC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

WAKSRC - Wake Up Source 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.

◆ CAN_MCR_WAKSRC [4/5]

#define CAN_MCR_WAKSRC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

WAKSRC - Wake Up Source 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.

◆ CAN_MCR_WAKSRC [5/5]

#define CAN_MCR_WAKSRC ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)

WAKSRC - Wake Up Source 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.

◆ CAN_MCR_WRNEN [1/5]

#define CAN_MCR_WRNEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

WRNEN - Warning Interrupt Enable 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.

◆ CAN_MCR_WRNEN [2/5]

#define CAN_MCR_WRNEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

WRNEN - Warning Interrupt Enable 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.

◆ CAN_MCR_WRNEN [3/5]

#define CAN_MCR_WRNEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

WRNEN - Warning Interrupt Enable 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.

◆ CAN_MCR_WRNEN [4/5]

#define CAN_MCR_WRNEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

WRNEN - Warning Interrupt Enable 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.

◆ CAN_MCR_WRNEN [5/5]

#define CAN_MCR_WRNEN ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)

WRNEN - Warning Interrupt Enable 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.

◆ CAN_RX14MASK_RX14M [1/6]

#define CAN_RX14MASK_RX14M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX14M - Rx Buffer 14 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX14MASK_RX14M [2/6]

#define CAN_RX14MASK_RX14M ( x)    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)

RX14M - Rx Buffer 14 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX14MASK_RX14M [3/6]

#define CAN_RX14MASK_RX14M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX14M - Rx Buffer 14 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX14MASK_RX14M [4/6]

#define CAN_RX14MASK_RX14M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX14M - Rx Buffer 14 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX14MASK_RX14M [5/6]

#define CAN_RX14MASK_RX14M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX14M - Rx Buffer 14 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX14MASK_RX14M [6/6]

#define CAN_RX14MASK_RX14M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)

RX14M - Rx Buffer 14 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX15MASK_RX15M [1/6]

#define CAN_RX15MASK_RX15M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

RX15M - Rx Buffer 15 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX15MASK_RX15M [2/6]

#define CAN_RX15MASK_RX15M ( x)    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)

RX15M - Rx Buffer 15 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX15MASK_RX15M [3/6]

#define CAN_RX15MASK_RX15M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

RX15M - Rx Buffer 15 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX15MASK_RX15M [4/6]

#define CAN_RX15MASK_RX15M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

RX15M - Rx Buffer 15 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX15MASK_RX15M [5/6]

#define CAN_RX15MASK_RX15M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

RX15M - Rx Buffer 15 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RX15MASK_RX15M [6/6]

#define CAN_RX15MASK_RX15M ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)

RX15M - Rx Buffer 15 Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_Rx_Warning_IRQS

#define CAN_Rx_Warning_IRQS   { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }

Interrupt vectors for the CAN peripheral type

◆ CAN_RXFGMASK_FGM [1/6]

#define CAN_RXFGMASK_FGM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

FGM - Rx FIFO Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXFGMASK_FGM [2/6]

#define CAN_RXFGMASK_FGM ( x)    (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)

FGM - Rx FIFO Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXFGMASK_FGM [3/6]

#define CAN_RXFGMASK_FGM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

FGM - Rx FIFO Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXFGMASK_FGM [4/6]

#define CAN_RXFGMASK_FGM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

FGM - Rx FIFO Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXFGMASK_FGM [5/6]

#define CAN_RXFGMASK_FGM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

FGM - Rx FIFO Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXFGMASK_FGM [6/6]

#define CAN_RXFGMASK_FGM ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)

FGM - Rx FIFO Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXIMR_MI [1/6]

#define CAN_RXIMR_MI ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MI - Individual Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXIMR_MI [2/6]

#define CAN_RXIMR_MI ( x)    (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)

MI - Individual Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXIMR_MI [3/6]

#define CAN_RXIMR_MI ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MI - Individual Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXIMR_MI [4/6]

#define CAN_RXIMR_MI ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MI - Individual Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXIMR_MI [5/6]

#define CAN_RXIMR_MI ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MI - Individual Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXIMR_MI [6/6]

#define CAN_RXIMR_MI ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)

MI - Individual Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXMGMASK_MG [1/6]

#define CAN_RXMGMASK_MG ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

MG - Rx Mailboxes Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXMGMASK_MG [2/6]

#define CAN_RXMGMASK_MG ( x)    (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)

MG - Rx Mailboxes Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXMGMASK_MG [3/6]

#define CAN_RXMGMASK_MG ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

MG - Rx Mailboxes Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXMGMASK_MG [4/6]

#define CAN_RXMGMASK_MG ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

MG - Rx Mailboxes Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXMGMASK_MG [5/6]

#define CAN_RXMGMASK_MG ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

MG - Rx Mailboxes Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ CAN_RXMGMASK_MG [6/6]

#define CAN_RXMGMASK_MG ( x)    (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)

MG - Rx Mailboxes Global Mask Bits 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care." 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.

◆ ENC_CTRL2_DIR

#define ENC_CTRL2_DIR ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

DIR - Count Direction Flag 0b0..Last count was in the down direction 0b1..Last count was in the up direction

◆ ENC_CTRL2_MOD

#define ENC_CTRL2_MOD ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

MOD - Enable Modulo Counting 0b0..Disable modulo counting 0b1..Enable modulo counting

◆ ENC_CTRL2_OUTCTL

#define ENC_CTRL2_OUTCTL ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

OUTCTL - Output Control 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read.

◆ ENC_CTRL2_REVMOD

#define ENC_CTRL2_REVMOD ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

REVMOD - Revolution Counter Modulus Enable 0b0..Use INDEX pulse to increment/decrement revolution counter (REV). 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV).

◆ ENC_CTRL2_ROIE

#define ENC_CTRL2_ROIE ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

ROIE - Roll-over Interrupt Enable 0b0..Roll-over interrupt is disabled 0b1..Roll-over interrupt is enabled

◆ ENC_CTRL2_ROIRQ

#define ENC_CTRL2_ROIRQ ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

ROIRQ - Roll-over Interrupt Request 0b0..No roll-over has occurred 0b1..Roll-over has occurred

◆ ENC_CTRL2_RUIE

#define ENC_CTRL2_RUIE ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

RUIE - Roll-under Interrupt Enable 0b0..Roll-under interrupt is disabled 0b1..Roll-under interrupt is enabled

◆ ENC_CTRL2_RUIRQ

#define ENC_CTRL2_RUIRQ ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

RUIRQ - Roll-under Interrupt Request 0b0..No roll-under has occurred 0b1..Roll-under has occurred

◆ ENC_CTRL2_SABIE

#define ENC_CTRL2_SABIE ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled. 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled.

◆ ENC_CTRL2_SABIRQ

#define ENC_CTRL2_SABIRQ ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)

SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request 0b0..No simultaneous change of PHASEA and PHASEB has occurred. 0b1..A simultaneous change of PHASEA and PHASEB has occurred.

◆ ENC_CTRL2_UPDHLD

#define ENC_CTRL2_UPDHLD ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

UPDHLD - Update Hold Registers 0b0..Disable updates of hold registers on rising edge of TRIGGER 0b1..Enable updates of hold registers on rising edge of TRIGGER

◆ ENC_CTRL2_UPDPOS

#define ENC_CTRL2_UPDPOS ( x)    (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

UPDPOS - Update Position Registers 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER

◆ PWM_CTRL2_CLK_SEL

#define PWM_CTRL2_CLK_SEL ( x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)

CLK_SEL - Clock Source Select 0b00..The IPBus clock is used as the clock for the local prescaler and counter. 0b01..EXT_CLK is used as the clock for the local prescaler and counter. 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0b11..reserved

◆ PWM_CTRL2_FORCE_SEL

#define PWM_CTRL2_FORCE_SEL ( x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)

FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b100..The local sync signal from this submodule is used to force updates. 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.

◆ PWM_CTRL2_FRCEN

#define PWM_CTRL2_FRCEN ( x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)

FRCEN 0b0..Initialization from a FORCE_OUT is disabled. 0b1..Initialization from a FORCE_OUT is enabled.

◆ PWM_CTRL2_INDEP

#define PWM_CTRL2_INDEP ( x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)

INDEP - Independent or Complementary Pair Operation 0b0..PWM_A and PWM_B form a complementary PWM pair. 0b1..PWM_A and PWM_B outputs are independent PWMs.

◆ PWM_CTRL2_INIT_SEL

#define PWM_CTRL2_INIT_SEL ( x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)

INIT_SEL - Initialization Control Select 0b00..Local sync (PWM_X) causes initialization. 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0b11..EXT_SYNC causes initialization.

◆ PWM_CTRL2_RELOAD_SEL

#define PWM_CTRL2_RELOAD_SEL ( x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)

RELOAD_SEL - Reload Source Select 0b0..The local RELOAD signal is used to reload registers. 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.

◆ SPI_MCR_CLR_RXF [1/5]

#define SPI_MCR_CLR_RXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)

CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

CLR_RXF - CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

◆ SPI_MCR_CLR_RXF [2/5]

#define SPI_MCR_CLR_RXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)

CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

CLR_RXF - CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

◆ SPI_MCR_CLR_RXF [3/5]

#define SPI_MCR_CLR_RXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)

CLR_RXF - CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

◆ SPI_MCR_CLR_RXF [4/5]

#define SPI_MCR_CLR_RXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)

CLR_RXF - CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

◆ SPI_MCR_CLR_RXF [5/5]

#define SPI_MCR_CLR_RXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)

CLR_RXF - CLR_RXF 0b0..Do not clear the RX FIFO counter. 0b1..Clear the RX FIFO counter.

◆ SPI_MCR_CLR_TXF [1/5]

#define SPI_MCR_CLR_TXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)

CLR_TXF - Clear TX FIFO 0b0..Do not clear the TX FIFO counter. 0b1..Clear the TX FIFO counter.

◆ SPI_MCR_CLR_TXF [2/5]

#define SPI_MCR_CLR_TXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)

CLR_TXF - Clear TX FIFO 0b0..Do not clear the TX FIFO counter. 0b1..Clear the TX FIFO counter.

◆ SPI_MCR_CLR_TXF [3/5]

#define SPI_MCR_CLR_TXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)

CLR_TXF - Clear TX FIFO 0b0..Do not clear the TX FIFO counter. 0b1..Clear the TX FIFO counter.

◆ SPI_MCR_CLR_TXF [4/5]

#define SPI_MCR_CLR_TXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)

CLR_TXF - Clear TX FIFO 0b0..Do not clear the TX FIFO counter. 0b1..Clear the TX FIFO counter.

◆ SPI_MCR_CLR_TXF [5/5]

#define SPI_MCR_CLR_TXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)

CLR_TXF - Clear TX FIFO 0b0..Do not clear the TX FIFO counter. 0b1..Clear the TX FIFO counter.

◆ SPI_MCR_CONT_SCKE [1/5]

#define SPI_MCR_CONT_SCKE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)

CONT_SCKE - Continuous SCK Enable 0b0..Continuous SCK disabled. 0b1..Continuous SCK enabled.

◆ SPI_MCR_CONT_SCKE [2/5]

#define SPI_MCR_CONT_SCKE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)

CONT_SCKE - Continuous SCK Enable 0b0..Continuous SCK disabled. 0b1..Continuous SCK enabled.

◆ SPI_MCR_CONT_SCKE [3/5]

#define SPI_MCR_CONT_SCKE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)

CONT_SCKE - Continuous SCK Enable 0b0..Continuous SCK disabled. 0b1..Continuous SCK enabled.

◆ SPI_MCR_CONT_SCKE [4/5]

#define SPI_MCR_CONT_SCKE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)

CONT_SCKE - Continuous SCK Enable 0b0..Continuous SCK disabled. 0b1..Continuous SCK enabled.

◆ SPI_MCR_CONT_SCKE [5/5]

#define SPI_MCR_CONT_SCKE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)

CONT_SCKE - Continuous SCK Enable 0b0..Continuous SCK disabled. 0b1..Continuous SCK enabled.

◆ SPI_MCR_DCONF [1/6]

#define SPI_MCR_DCONF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

◆ SPI_MCR_DCONF [2/6]

#define SPI_MCR_DCONF ( x)    (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

◆ SPI_MCR_DCONF [3/6]

#define SPI_MCR_DCONF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

◆ SPI_MCR_DCONF [4/6]

#define SPI_MCR_DCONF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

◆ SPI_MCR_DCONF [5/6]

#define SPI_MCR_DCONF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

◆ SPI_MCR_DCONF [6/6]

#define SPI_MCR_DCONF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)

DCONF - SPI Configuration. 0b00..SPI 0b01..Reserved 0b10..Reserved 0b11..Reserved

◆ SPI_MCR_DIS_RXF [1/5]

#define SPI_MCR_DIS_RXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)

DIS_RXF - Disable Receive FIFO 0b0..RX FIFO is enabled. 0b1..RX FIFO is disabled.

◆ SPI_MCR_DIS_RXF [2/5]

#define SPI_MCR_DIS_RXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)

DIS_RXF - Disable Receive FIFO 0b0..RX FIFO is enabled. 0b1..RX FIFO is disabled.

◆ SPI_MCR_DIS_RXF [3/5]

#define SPI_MCR_DIS_RXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)

DIS_RXF - Disable Receive FIFO 0b0..RX FIFO is enabled. 0b1..RX FIFO is disabled.

◆ SPI_MCR_DIS_RXF [4/5]

#define SPI_MCR_DIS_RXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)

DIS_RXF - Disable Receive FIFO 0b0..RX FIFO is enabled. 0b1..RX FIFO is disabled.

◆ SPI_MCR_DIS_RXF [5/5]

#define SPI_MCR_DIS_RXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)

DIS_RXF - Disable Receive FIFO 0b0..RX FIFO is enabled. 0b1..RX FIFO is disabled.

◆ SPI_MCR_DIS_TXF [1/5]

#define SPI_MCR_DIS_TXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)

DIS_TXF - Disable Transmit FIFO 0b0..TX FIFO is enabled. 0b1..TX FIFO is disabled.

◆ SPI_MCR_DIS_TXF [2/5]

#define SPI_MCR_DIS_TXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)

DIS_TXF - Disable Transmit FIFO 0b0..TX FIFO is enabled. 0b1..TX FIFO is disabled.

◆ SPI_MCR_DIS_TXF [3/5]

#define SPI_MCR_DIS_TXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)

DIS_TXF - Disable Transmit FIFO 0b0..TX FIFO is enabled. 0b1..TX FIFO is disabled.

◆ SPI_MCR_DIS_TXF [4/5]

#define SPI_MCR_DIS_TXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)

DIS_TXF - Disable Transmit FIFO 0b0..TX FIFO is enabled. 0b1..TX FIFO is disabled.

◆ SPI_MCR_DIS_TXF [5/5]

#define SPI_MCR_DIS_TXF ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)

DIS_TXF - Disable Transmit FIFO 0b0..TX FIFO is enabled. 0b1..TX FIFO is disabled.

◆ SPI_MCR_DOZE [1/5]

#define SPI_MCR_DOZE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)

DOZE - Doze Enable 0b0..Doze mode has no effect on the module. 0b1..Doze mode disables the module.

◆ SPI_MCR_DOZE [2/5]

#define SPI_MCR_DOZE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)

DOZE - Doze Enable 0b0..Doze mode has no effect on the module. 0b1..Doze mode disables the module.

◆ SPI_MCR_DOZE [3/5]

#define SPI_MCR_DOZE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)

DOZE - Doze Enable 0b0..Doze mode has no effect on the module. 0b1..Doze mode disables the module.

◆ SPI_MCR_DOZE [4/5]

#define SPI_MCR_DOZE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)

DOZE - Doze Enable 0b0..Doze mode has no effect on the module. 0b1..Doze mode disables the module.

◆ SPI_MCR_DOZE [5/5]

#define SPI_MCR_DOZE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)

DOZE - Doze Enable 0b0..Doze mode has no effect on the module. 0b1..Doze mode disables the module.

◆ SPI_MCR_FRZ [1/5]

#define SPI_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Do not halt serial transfers in Debug mode. 0b1..Halt serial transfers in Debug mode.

◆ SPI_MCR_FRZ [2/5]

#define SPI_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Do not halt serial transfers in Debug mode. 0b1..Halt serial transfers in Debug mode.

◆ SPI_MCR_FRZ [3/5]

#define SPI_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Do not halt serial transfers in Debug mode. 0b1..Halt serial transfers in Debug mode.

◆ SPI_MCR_FRZ [4/5]

#define SPI_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Do not halt serial transfers in Debug mode. 0b1..Halt serial transfers in Debug mode.

◆ SPI_MCR_FRZ [5/5]

#define SPI_MCR_FRZ ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)

FRZ - Freeze 0b0..Do not halt serial transfers in Debug mode. 0b1..Halt serial transfers in Debug mode.

◆ SPI_MCR_HALT [1/5]

#define SPI_MCR_HALT ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)

HALT - Halt 0b0..Start transfers. 0b1..Stop transfers.

◆ SPI_MCR_HALT [2/5]

#define SPI_MCR_HALT ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)

HALT - Halt 0b0..Start transfers. 0b1..Stop transfers.

◆ SPI_MCR_HALT [3/5]

#define SPI_MCR_HALT ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)

HALT - Halt 0b0..Start transfers. 0b1..Stop transfers.

◆ SPI_MCR_HALT [4/5]

#define SPI_MCR_HALT ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)

HALT - Halt 0b0..Start transfers. 0b1..Stop transfers.

◆ SPI_MCR_HALT [5/5]

#define SPI_MCR_HALT ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)

HALT - Halt 0b0..Start transfers. 0b1..Stop transfers.

◆ SPI_MCR_MDIS [1/5]

#define SPI_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enables the module clocks. 0b1..Allows external logic to disable the module clocks.

◆ SPI_MCR_MDIS [2/5]

#define SPI_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enables the module clocks. 0b1..Allows external logic to disable the module clocks.

◆ SPI_MCR_MDIS [3/5]

#define SPI_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enables the module clocks. 0b1..Allows external logic to disable the module clocks.

◆ SPI_MCR_MDIS [4/5]

#define SPI_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enables the module clocks. 0b1..Allows external logic to disable the module clocks.

◆ SPI_MCR_MDIS [5/5]

#define SPI_MCR_MDIS ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)

MDIS - Module Disable 0b0..Enables the module clocks. 0b1..Allows external logic to disable the module clocks.

◆ SPI_MCR_MSTR [1/5]

#define SPI_MCR_MSTR ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

MSTR - Master/Slave Mode Select 0b0..Enables Slave mode 0b1..Enables Master mode

◆ SPI_MCR_MSTR [2/5]

#define SPI_MCR_MSTR ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

MSTR - Master/Slave Mode Select 0b0..Enables Slave mode 0b1..Enables Master mode

◆ SPI_MCR_MSTR [3/5]

#define SPI_MCR_MSTR ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

MSTR - Master/Slave Mode Select 0b0..Enables Slave mode 0b1..Enables Master mode

◆ SPI_MCR_MSTR [4/5]

#define SPI_MCR_MSTR ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

MSTR - Master/Slave Mode Select 0b0..Enables Slave mode 0b1..Enables Master mode

◆ SPI_MCR_MSTR [5/5]

#define SPI_MCR_MSTR ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)

MSTR - Master/Slave Mode Select 0b0..Enables Slave mode 0b1..Enables Master mode

◆ SPI_MCR_MTFE [1/5]

#define SPI_MCR_MTFE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)

MTFE - Modified Timing Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

MTFE - Modified Transfer Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

◆ SPI_MCR_MTFE [2/5]

#define SPI_MCR_MTFE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)

MTFE - Modified Timing Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

MTFE - Modified Transfer Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

◆ SPI_MCR_MTFE [3/5]

#define SPI_MCR_MTFE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)

MTFE - Modified Transfer Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

◆ SPI_MCR_MTFE [4/5]

#define SPI_MCR_MTFE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)

MTFE - Modified Transfer Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

◆ SPI_MCR_MTFE [5/5]

#define SPI_MCR_MTFE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)

MTFE - Modified Transfer Format Enable 0b0..Modified SPI transfer format disabled. 0b1..Modified SPI transfer format enabled.

◆ SPI_MCR_PCSIS [1/6]

#define SPI_MCR_PCSIS ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

◆ SPI_MCR_PCSIS [2/6]

#define SPI_MCR_PCSIS ( x)    (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

◆ SPI_MCR_PCSIS [3/6]

#define SPI_MCR_PCSIS ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

◆ SPI_MCR_PCSIS [4/6]

#define SPI_MCR_PCSIS ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

◆ SPI_MCR_PCSIS [5/6]

#define SPI_MCR_PCSIS ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

◆ SPI_MCR_PCSIS [6/6]

#define SPI_MCR_PCSIS ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)

PCSIS - Peripheral Chip Select x Inactive State 0b000000..The inactive state of PCSx is low. 0b000001..The inactive state of PCSx is high.

◆ SPI_MCR_PCSSE [1/5]

#define SPI_MCR_PCSSE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)

PCSSE - Peripheral Chip Select Strobe Enable 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.

◆ SPI_MCR_PCSSE [2/5]

#define SPI_MCR_PCSSE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)

PCSSE - Peripheral Chip Select Strobe Enable 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.

◆ SPI_MCR_PCSSE [3/5]

#define SPI_MCR_PCSSE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)

PCSSE - Peripheral Chip Select Strobe Enable 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.

◆ SPI_MCR_PCSSE [4/5]

#define SPI_MCR_PCSSE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)

PCSSE - Peripheral Chip Select Strobe Enable 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.

◆ SPI_MCR_PCSSE [5/5]

#define SPI_MCR_PCSSE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)

PCSSE - Peripheral Chip Select Strobe Enable 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.

◆ SPI_MCR_ROOE [1/5]

#define SPI_MCR_ROOE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)

ROOE - Receive FIFO Overflow Overwrite Enable 0b0..Incoming data is ignored. 0b1..Incoming data is shifted into the shift register.

◆ SPI_MCR_ROOE [2/5]

#define SPI_MCR_ROOE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)

ROOE - Receive FIFO Overflow Overwrite Enable 0b0..Incoming data is ignored. 0b1..Incoming data is shifted into the shift register.

◆ SPI_MCR_ROOE [3/5]

#define SPI_MCR_ROOE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)

ROOE - Receive FIFO Overflow Overwrite Enable 0b0..Incoming data is ignored. 0b1..Incoming data is shifted into the shift register.

◆ SPI_MCR_ROOE [4/5]

#define SPI_MCR_ROOE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)

ROOE - Receive FIFO Overflow Overwrite Enable 0b0..Incoming data is ignored. 0b1..Incoming data is shifted into the shift register.

◆ SPI_MCR_ROOE [5/5]

#define SPI_MCR_ROOE ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)

ROOE - Receive FIFO Overflow Overwrite Enable 0b0..Incoming data is ignored. 0b1..Incoming data is shifted into the shift register.

◆ SPI_MCR_SMPL_PT [1/6]

#define SPI_MCR_SMPL_PT ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

◆ SPI_MCR_SMPL_PT [2/6]

#define SPI_MCR_SMPL_PT ( x)    (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

◆ SPI_MCR_SMPL_PT [3/6]

#define SPI_MCR_SMPL_PT ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

◆ SPI_MCR_SMPL_PT [4/6]

#define SPI_MCR_SMPL_PT ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

◆ SPI_MCR_SMPL_PT [5/6]

#define SPI_MCR_SMPL_PT ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved

◆ SPI_MCR_SMPL_PT [6/6]

#define SPI_MCR_SMPL_PT ( x)    (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)

SMPL_PT - Sample Point 0b00..0 protocol clock cycles between SCK edge and SIN sample 0b01..1 protocol clock cycle between SCK edge and SIN sample 0b10..2 protocol clock cycles between SCK edge and SIN sample 0b11..Reserved