CAU Register Masks

Macros
#define	CAU_BASE   (0xE0081000u)
#define	CAU   ((CAU_Type *)CAU_BASE)
#define	CAU_BASE_ADDRS   { CAU_BASE }
#define	CAU_BASE_PTRS   { CAU }
#define	CAU_DIRECT_COUNT   (16U)
#define	CAU_LDR_CA_COUNT   (9U)
#define	CAU_STR_CA_COUNT   (9U)
#define	CAU_ADR_CA_COUNT   (9U)
#define	CAU_RADR_CA_COUNT   (9U)
#define	CAU_XOR_CA_COUNT   (9U)
#define	CAU_ROTL_CA_COUNT   (9U)
#define	CAU_AESC_CA_COUNT   (9U)
#define	CAU_AESIC_CA_COUNT   (9U)
#define	CAU_DIRECT_COUNT   (16U)
#define	CAU_LDR_CA_COUNT   (9U)
#define	CAU_STR_CA_COUNT   (9U)
#define	CAU_ADR_CA_COUNT   (9U)
#define	CAU_RADR_CA_COUNT   (9U)
#define	CAU_XOR_CA_COUNT   (9U)
#define	CAU_ROTL_CA_COUNT   (9U)
#define	CAU_AESC_CA_COUNT   (9U)
#define	CAU_AESIC_CA_COUNT   (9U)
#define	CAU_DIRECT_COUNT   (16U)
#define	CAU_LDR_CA_COUNT   (9U)
#define	CAU_STR_CA_COUNT   (9U)
#define	CAU_ADR_CA_COUNT   (9U)
#define	CAU_RADR_CA_COUNT   (9U)
#define	CAU_XOR_CA_COUNT   (9U)
#define	CAU_ROTL_CA_COUNT   (9U)
#define	CAU_AESC_CA_COUNT   (9U)
#define	CAU_AESIC_CA_COUNT   (9U)
#define	CAU_DIRECT_COUNT   (16U)
#define	CAU_LDR_CA_COUNT   (9U)
#define	CAU_STR_CA_COUNT   (9U)
#define	CAU_ADR_CA_COUNT   (9U)
#define	CAU_RADR_CA_COUNT   (9U)
#define	CAU_XOR_CA_COUNT   (9U)
#define	CAU_ROTL_CA_COUNT   (9U)
#define	CAU_AESC_CA_COUNT   (9U)
#define	CAU_AESIC_CA_COUNT   (9U)

DIRECT - Direct access register 0..Direct access register 15
#define	CAU_DIRECT_CAU_DIRECT0_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT0_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
#define	CAU_DIRECT_CAU_DIRECT1_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT1_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
#define	CAU_DIRECT_CAU_DIRECT2_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT2_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
#define	CAU_DIRECT_CAU_DIRECT3_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT3_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
#define	CAU_DIRECT_CAU_DIRECT4_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT4_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
#define	CAU_DIRECT_CAU_DIRECT5_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT5_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
#define	CAU_DIRECT_CAU_DIRECT6_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT6_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
#define	CAU_DIRECT_CAU_DIRECT7_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT7_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
#define	CAU_DIRECT_CAU_DIRECT8_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT8_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
#define	CAU_DIRECT_CAU_DIRECT9_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT9_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT9(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
#define	CAU_DIRECT_CAU_DIRECT10_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT10_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT10(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
#define	CAU_DIRECT_CAU_DIRECT11_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT11_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT11(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
#define	CAU_DIRECT_CAU_DIRECT12_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT12_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT12(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
#define	CAU_DIRECT_CAU_DIRECT13_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT13_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT13(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
#define	CAU_DIRECT_CAU_DIRECT14_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT14_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT14(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
#define	CAU_DIRECT_CAU_DIRECT15_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT15_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT15(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
#define	CAU_DIRECT_CAU_DIRECT0_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT0_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
#define	CAU_DIRECT_CAU_DIRECT1_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT1_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
#define	CAU_DIRECT_CAU_DIRECT2_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT2_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
#define	CAU_DIRECT_CAU_DIRECT3_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT3_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
#define	CAU_DIRECT_CAU_DIRECT4_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT4_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
#define	CAU_DIRECT_CAU_DIRECT5_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT5_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
#define	CAU_DIRECT_CAU_DIRECT6_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT6_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
#define	CAU_DIRECT_CAU_DIRECT7_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT7_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
#define	CAU_DIRECT_CAU_DIRECT8_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT8_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
#define	CAU_DIRECT_CAU_DIRECT9_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT9_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT9(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
#define	CAU_DIRECT_CAU_DIRECT10_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT10_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT10(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
#define	CAU_DIRECT_CAU_DIRECT11_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT11_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT11(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
#define	CAU_DIRECT_CAU_DIRECT12_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT12_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT12(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
#define	CAU_DIRECT_CAU_DIRECT13_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT13_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT13(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
#define	CAU_DIRECT_CAU_DIRECT14_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT14_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT14(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
#define	CAU_DIRECT_CAU_DIRECT15_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT15_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT15(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
#define	CAU_DIRECT_CAU_DIRECT0_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT0_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
#define	CAU_DIRECT_CAU_DIRECT1_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT1_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
#define	CAU_DIRECT_CAU_DIRECT2_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT2_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
#define	CAU_DIRECT_CAU_DIRECT3_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT3_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
#define	CAU_DIRECT_CAU_DIRECT4_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT4_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
#define	CAU_DIRECT_CAU_DIRECT5_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT5_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
#define	CAU_DIRECT_CAU_DIRECT6_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT6_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
#define	CAU_DIRECT_CAU_DIRECT7_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT7_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
#define	CAU_DIRECT_CAU_DIRECT8_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT8_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
#define	CAU_DIRECT_CAU_DIRECT9_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT9_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT9(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
#define	CAU_DIRECT_CAU_DIRECT10_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT10_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT10(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
#define	CAU_DIRECT_CAU_DIRECT11_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT11_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT11(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
#define	CAU_DIRECT_CAU_DIRECT12_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT12_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT12(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
#define	CAU_DIRECT_CAU_DIRECT13_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT13_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT13(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
#define	CAU_DIRECT_CAU_DIRECT14_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT14_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT14(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
#define	CAU_DIRECT_CAU_DIRECT15_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT15_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT15(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
#define	CAU_DIRECT_CAU_DIRECT0_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT0_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
#define	CAU_DIRECT_CAU_DIRECT1_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT1_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
#define	CAU_DIRECT_CAU_DIRECT2_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT2_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
#define	CAU_DIRECT_CAU_DIRECT3_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT3_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
#define	CAU_DIRECT_CAU_DIRECT4_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT4_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
#define	CAU_DIRECT_CAU_DIRECT5_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT5_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
#define	CAU_DIRECT_CAU_DIRECT6_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT6_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
#define	CAU_DIRECT_CAU_DIRECT7_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT7_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
#define	CAU_DIRECT_CAU_DIRECT8_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT8_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
#define	CAU_DIRECT_CAU_DIRECT9_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT9_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT9(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
#define	CAU_DIRECT_CAU_DIRECT10_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT10_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT10(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
#define	CAU_DIRECT_CAU_DIRECT11_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT11_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT11(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
#define	CAU_DIRECT_CAU_DIRECT12_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT12_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT12(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
#define	CAU_DIRECT_CAU_DIRECT13_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT13_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT13(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
#define	CAU_DIRECT_CAU_DIRECT14_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT14_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT14(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
#define	CAU_DIRECT_CAU_DIRECT15_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT15_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT15(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
#define	CAU_DIRECT_CAU_DIRECT0_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT0_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
#define	CAU_DIRECT_CAU_DIRECT1_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT1_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
#define	CAU_DIRECT_CAU_DIRECT2_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT2_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
#define	CAU_DIRECT_CAU_DIRECT3_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT3_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
#define	CAU_DIRECT_CAU_DIRECT4_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT4_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
#define	CAU_DIRECT_CAU_DIRECT5_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT5_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
#define	CAU_DIRECT_CAU_DIRECT6_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT6_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
#define	CAU_DIRECT_CAU_DIRECT7_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT7_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
#define	CAU_DIRECT_CAU_DIRECT8_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT8_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
#define	CAU_DIRECT_CAU_DIRECT9_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT9_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT9(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
#define	CAU_DIRECT_CAU_DIRECT10_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT10_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT10(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
#define	CAU_DIRECT_CAU_DIRECT11_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT11_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT11(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
#define	CAU_DIRECT_CAU_DIRECT12_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT12_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT12(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
#define	CAU_DIRECT_CAU_DIRECT13_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT13_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT13(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
#define	CAU_DIRECT_CAU_DIRECT14_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT14_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT14(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
#define	CAU_DIRECT_CAU_DIRECT15_MASK   (0xFFFFFFFFU)
#define	CAU_DIRECT_CAU_DIRECT15_SHIFT   (0U)
#define	CAU_DIRECT_CAU_DIRECT15(x)   (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)

DIRECT - Direct access register 0..Direct access register 15
#define	CAU_DIRECT_COUNT   (16U)

LDR_CASR - Status register - Load Register command
#define	CAU_LDR_CASR_IC_MASK   (0x1U)
#define	CAU_LDR_CASR_IC_SHIFT   (0U)
#define	CAU_LDR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
#define	CAU_LDR_CASR_DPE_MASK   (0x2U)
#define	CAU_LDR_CASR_DPE_SHIFT   (1U)
#define	CAU_LDR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
#define	CAU_LDR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_LDR_CASR_VER_SHIFT   (28U)
#define	CAU_LDR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
#define	CAU_LDR_CASR_IC_MASK   0x1u
#define	CAU_LDR_CASR_IC_SHIFT   0
#define	CAU_LDR_CASR_DPE_MASK   0x2u
#define	CAU_LDR_CASR_DPE_SHIFT   1
#define	CAU_LDR_CASR_VER_MASK   0xF0000000u
#define	CAU_LDR_CASR_VER_SHIFT   28
#define	CAU_LDR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
#define	CAU_LDR_CASR_IC_MASK   (0x1U)
#define	CAU_LDR_CASR_IC_SHIFT   (0U)
#define	CAU_LDR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
#define	CAU_LDR_CASR_DPE_MASK   (0x2U)
#define	CAU_LDR_CASR_DPE_SHIFT   (1U)
#define	CAU_LDR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
#define	CAU_LDR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_LDR_CASR_VER_SHIFT   (28U)
#define	CAU_LDR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
#define	CAU_LDR_CASR_IC_MASK   (0x1U)
#define	CAU_LDR_CASR_IC_SHIFT   (0U)
#define	CAU_LDR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
#define	CAU_LDR_CASR_DPE_MASK   (0x2U)
#define	CAU_LDR_CASR_DPE_SHIFT   (1U)
#define	CAU_LDR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
#define	CAU_LDR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_LDR_CASR_VER_SHIFT   (28U)
#define	CAU_LDR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
#define	CAU_LDR_CASR_IC_MASK   (0x1U)
#define	CAU_LDR_CASR_IC_SHIFT   (0U)
#define	CAU_LDR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
#define	CAU_LDR_CASR_DPE_MASK   (0x2U)
#define	CAU_LDR_CASR_DPE_SHIFT   (1U)
#define	CAU_LDR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
#define	CAU_LDR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_LDR_CASR_VER_SHIFT   (28U)
#define	CAU_LDR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
#define	CAU_LDR_CASR_IC_MASK   (0x1U)
#define	CAU_LDR_CASR_IC_SHIFT   (0U)
#define	CAU_LDR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
#define	CAU_LDR_CASR_DPE_MASK   (0x2U)
#define	CAU_LDR_CASR_DPE_SHIFT   (1U)
#define	CAU_LDR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
#define	CAU_LDR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_LDR_CASR_VER_SHIFT   (28U)
#define	CAU_LDR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)

LDR_CAA - Accumulator register - Load Register command
#define	CAU_LDR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CAA_ACC_SHIFT   (0U)
#define	CAU_LDR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
#define	CAU_LDR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CAA_ACC_SHIFT   (0U)
#define	CAU_LDR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
#define	CAU_LDR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CAA_ACC_SHIFT   (0U)
#define	CAU_LDR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
#define	CAU_LDR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CAA_ACC_SHIFT   (0U)
#define	CAU_LDR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
#define	CAU_LDR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CAA_ACC_SHIFT   (0U)
#define	CAU_LDR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)

LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command
#define	CAU_LDR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA0_SHIFT   (0U)
#define	CAU_LDR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
#define	CAU_LDR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA1_SHIFT   (0U)
#define	CAU_LDR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
#define	CAU_LDR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA2_SHIFT   (0U)
#define	CAU_LDR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
#define	CAU_LDR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA3_SHIFT   (0U)
#define	CAU_LDR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
#define	CAU_LDR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA4_SHIFT   (0U)
#define	CAU_LDR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
#define	CAU_LDR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA5_SHIFT   (0U)
#define	CAU_LDR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
#define	CAU_LDR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA6_SHIFT   (0U)
#define	CAU_LDR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
#define	CAU_LDR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA7_SHIFT   (0U)
#define	CAU_LDR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
#define	CAU_LDR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA8_SHIFT   (0U)
#define	CAU_LDR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
#define	CAU_LDR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA0_SHIFT   (0U)
#define	CAU_LDR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
#define	CAU_LDR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA1_SHIFT   (0U)
#define	CAU_LDR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
#define	CAU_LDR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA2_SHIFT   (0U)
#define	CAU_LDR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
#define	CAU_LDR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA3_SHIFT   (0U)
#define	CAU_LDR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
#define	CAU_LDR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA4_SHIFT   (0U)
#define	CAU_LDR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
#define	CAU_LDR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA5_SHIFT   (0U)
#define	CAU_LDR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
#define	CAU_LDR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA6_SHIFT   (0U)
#define	CAU_LDR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
#define	CAU_LDR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA7_SHIFT   (0U)
#define	CAU_LDR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
#define	CAU_LDR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA8_SHIFT   (0U)
#define	CAU_LDR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
#define	CAU_LDR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA0_SHIFT   (0U)
#define	CAU_LDR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
#define	CAU_LDR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA1_SHIFT   (0U)
#define	CAU_LDR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
#define	CAU_LDR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA2_SHIFT   (0U)
#define	CAU_LDR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
#define	CAU_LDR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA3_SHIFT   (0U)
#define	CAU_LDR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
#define	CAU_LDR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA4_SHIFT   (0U)
#define	CAU_LDR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
#define	CAU_LDR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA5_SHIFT   (0U)
#define	CAU_LDR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
#define	CAU_LDR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA6_SHIFT   (0U)
#define	CAU_LDR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
#define	CAU_LDR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA7_SHIFT   (0U)
#define	CAU_LDR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
#define	CAU_LDR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA8_SHIFT   (0U)
#define	CAU_LDR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
#define	CAU_LDR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA0_SHIFT   (0U)
#define	CAU_LDR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
#define	CAU_LDR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA1_SHIFT   (0U)
#define	CAU_LDR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
#define	CAU_LDR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA2_SHIFT   (0U)
#define	CAU_LDR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
#define	CAU_LDR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA3_SHIFT   (0U)
#define	CAU_LDR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
#define	CAU_LDR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA4_SHIFT   (0U)
#define	CAU_LDR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
#define	CAU_LDR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA5_SHIFT   (0U)
#define	CAU_LDR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
#define	CAU_LDR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA6_SHIFT   (0U)
#define	CAU_LDR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
#define	CAU_LDR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA7_SHIFT   (0U)
#define	CAU_LDR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
#define	CAU_LDR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA8_SHIFT   (0U)
#define	CAU_LDR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
#define	CAU_LDR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA0_SHIFT   (0U)
#define	CAU_LDR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
#define	CAU_LDR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA1_SHIFT   (0U)
#define	CAU_LDR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
#define	CAU_LDR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA2_SHIFT   (0U)
#define	CAU_LDR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
#define	CAU_LDR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA3_SHIFT   (0U)
#define	CAU_LDR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
#define	CAU_LDR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA4_SHIFT   (0U)
#define	CAU_LDR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
#define	CAU_LDR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA5_SHIFT   (0U)
#define	CAU_LDR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
#define	CAU_LDR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA6_SHIFT   (0U)
#define	CAU_LDR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
#define	CAU_LDR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA7_SHIFT   (0U)
#define	CAU_LDR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
#define	CAU_LDR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_LDR_CA_CA8_SHIFT   (0U)
#define	CAU_LDR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)

LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command
#define	CAU_LDR_CA_COUNT   (9U)

STR_CASR - Status register - Store Register command
#define	CAU_STR_CASR_IC_MASK   (0x1U)
#define	CAU_STR_CASR_IC_SHIFT   (0U)
#define	CAU_STR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
#define	CAU_STR_CASR_DPE_MASK   (0x2U)
#define	CAU_STR_CASR_DPE_SHIFT   (1U)
#define	CAU_STR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
#define	CAU_STR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_STR_CASR_VER_SHIFT   (28U)
#define	CAU_STR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
#define	CAU_STR_CASR_IC_MASK   0x1u
#define	CAU_STR_CASR_IC_SHIFT   0
#define	CAU_STR_CASR_DPE_MASK   0x2u
#define	CAU_STR_CASR_DPE_SHIFT   1
#define	CAU_STR_CASR_VER_MASK   0xF0000000u
#define	CAU_STR_CASR_VER_SHIFT   28
#define	CAU_STR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
#define	CAU_STR_CASR_IC_MASK   (0x1U)
#define	CAU_STR_CASR_IC_SHIFT   (0U)
#define	CAU_STR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
#define	CAU_STR_CASR_DPE_MASK   (0x2U)
#define	CAU_STR_CASR_DPE_SHIFT   (1U)
#define	CAU_STR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
#define	CAU_STR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_STR_CASR_VER_SHIFT   (28U)
#define	CAU_STR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
#define	CAU_STR_CASR_IC_MASK   (0x1U)
#define	CAU_STR_CASR_IC_SHIFT   (0U)
#define	CAU_STR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
#define	CAU_STR_CASR_DPE_MASK   (0x2U)
#define	CAU_STR_CASR_DPE_SHIFT   (1U)
#define	CAU_STR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
#define	CAU_STR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_STR_CASR_VER_SHIFT   (28U)
#define	CAU_STR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
#define	CAU_STR_CASR_IC_MASK   (0x1U)
#define	CAU_STR_CASR_IC_SHIFT   (0U)
#define	CAU_STR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
#define	CAU_STR_CASR_DPE_MASK   (0x2U)
#define	CAU_STR_CASR_DPE_SHIFT   (1U)
#define	CAU_STR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
#define	CAU_STR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_STR_CASR_VER_SHIFT   (28U)
#define	CAU_STR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
#define	CAU_STR_CASR_IC_MASK   (0x1U)
#define	CAU_STR_CASR_IC_SHIFT   (0U)
#define	CAU_STR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
#define	CAU_STR_CASR_DPE_MASK   (0x2U)
#define	CAU_STR_CASR_DPE_SHIFT   (1U)
#define	CAU_STR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
#define	CAU_STR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_STR_CASR_VER_SHIFT   (28U)
#define	CAU_STR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)

STR_CAA - Accumulator register - Store Register command
#define	CAU_STR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CAA_ACC_SHIFT   (0U)
#define	CAU_STR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
#define	CAU_STR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CAA_ACC_SHIFT   (0U)
#define	CAU_STR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
#define	CAU_STR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CAA_ACC_SHIFT   (0U)
#define	CAU_STR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
#define	CAU_STR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CAA_ACC_SHIFT   (0U)
#define	CAU_STR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
#define	CAU_STR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CAA_ACC_SHIFT   (0U)
#define	CAU_STR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)

STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command
#define	CAU_STR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA0_SHIFT   (0U)
#define	CAU_STR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
#define	CAU_STR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA1_SHIFT   (0U)
#define	CAU_STR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
#define	CAU_STR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA2_SHIFT   (0U)
#define	CAU_STR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
#define	CAU_STR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA3_SHIFT   (0U)
#define	CAU_STR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
#define	CAU_STR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA4_SHIFT   (0U)
#define	CAU_STR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
#define	CAU_STR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA5_SHIFT   (0U)
#define	CAU_STR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
#define	CAU_STR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA6_SHIFT   (0U)
#define	CAU_STR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
#define	CAU_STR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA7_SHIFT   (0U)
#define	CAU_STR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
#define	CAU_STR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA8_SHIFT   (0U)
#define	CAU_STR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
#define	CAU_STR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA0_SHIFT   (0U)
#define	CAU_STR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
#define	CAU_STR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA1_SHIFT   (0U)
#define	CAU_STR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
#define	CAU_STR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA2_SHIFT   (0U)
#define	CAU_STR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
#define	CAU_STR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA3_SHIFT   (0U)
#define	CAU_STR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
#define	CAU_STR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA4_SHIFT   (0U)
#define	CAU_STR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
#define	CAU_STR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA5_SHIFT   (0U)
#define	CAU_STR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
#define	CAU_STR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA6_SHIFT   (0U)
#define	CAU_STR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
#define	CAU_STR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA7_SHIFT   (0U)
#define	CAU_STR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
#define	CAU_STR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA8_SHIFT   (0U)
#define	CAU_STR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
#define	CAU_STR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA0_SHIFT   (0U)
#define	CAU_STR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
#define	CAU_STR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA1_SHIFT   (0U)
#define	CAU_STR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
#define	CAU_STR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA2_SHIFT   (0U)
#define	CAU_STR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
#define	CAU_STR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA3_SHIFT   (0U)
#define	CAU_STR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
#define	CAU_STR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA4_SHIFT   (0U)
#define	CAU_STR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
#define	CAU_STR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA5_SHIFT   (0U)
#define	CAU_STR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
#define	CAU_STR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA6_SHIFT   (0U)
#define	CAU_STR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
#define	CAU_STR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA7_SHIFT   (0U)
#define	CAU_STR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
#define	CAU_STR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA8_SHIFT   (0U)
#define	CAU_STR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
#define	CAU_STR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA0_SHIFT   (0U)
#define	CAU_STR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
#define	CAU_STR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA1_SHIFT   (0U)
#define	CAU_STR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
#define	CAU_STR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA2_SHIFT   (0U)
#define	CAU_STR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
#define	CAU_STR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA3_SHIFT   (0U)
#define	CAU_STR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
#define	CAU_STR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA4_SHIFT   (0U)
#define	CAU_STR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
#define	CAU_STR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA5_SHIFT   (0U)
#define	CAU_STR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
#define	CAU_STR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA6_SHIFT   (0U)
#define	CAU_STR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
#define	CAU_STR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA7_SHIFT   (0U)
#define	CAU_STR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
#define	CAU_STR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA8_SHIFT   (0U)
#define	CAU_STR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
#define	CAU_STR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA0_SHIFT   (0U)
#define	CAU_STR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
#define	CAU_STR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA1_SHIFT   (0U)
#define	CAU_STR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
#define	CAU_STR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA2_SHIFT   (0U)
#define	CAU_STR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
#define	CAU_STR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA3_SHIFT   (0U)
#define	CAU_STR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
#define	CAU_STR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA4_SHIFT   (0U)
#define	CAU_STR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
#define	CAU_STR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA5_SHIFT   (0U)
#define	CAU_STR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
#define	CAU_STR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA6_SHIFT   (0U)
#define	CAU_STR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
#define	CAU_STR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA7_SHIFT   (0U)
#define	CAU_STR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
#define	CAU_STR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_STR_CA_CA8_SHIFT   (0U)
#define	CAU_STR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)

STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command
#define	CAU_STR_CA_COUNT   (9U)

ADR_CASR - Status register - Add Register command
#define	CAU_ADR_CASR_IC_MASK   (0x1U)
#define	CAU_ADR_CASR_IC_SHIFT   (0U)
#define	CAU_ADR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
#define	CAU_ADR_CASR_DPE_MASK   (0x2U)
#define	CAU_ADR_CASR_DPE_SHIFT   (1U)
#define	CAU_ADR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
#define	CAU_ADR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_ADR_CASR_VER_SHIFT   (28U)
#define	CAU_ADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
#define	CAU_ADR_CASR_IC_MASK   0x1u
#define	CAU_ADR_CASR_IC_SHIFT   0
#define	CAU_ADR_CASR_DPE_MASK   0x2u
#define	CAU_ADR_CASR_DPE_SHIFT   1
#define	CAU_ADR_CASR_VER_MASK   0xF0000000u
#define	CAU_ADR_CASR_VER_SHIFT   28
#define	CAU_ADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
#define	CAU_ADR_CASR_IC_MASK   (0x1U)
#define	CAU_ADR_CASR_IC_SHIFT   (0U)
#define	CAU_ADR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
#define	CAU_ADR_CASR_DPE_MASK   (0x2U)
#define	CAU_ADR_CASR_DPE_SHIFT   (1U)
#define	CAU_ADR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
#define	CAU_ADR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_ADR_CASR_VER_SHIFT   (28U)
#define	CAU_ADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
#define	CAU_ADR_CASR_IC_MASK   (0x1U)
#define	CAU_ADR_CASR_IC_SHIFT   (0U)
#define	CAU_ADR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
#define	CAU_ADR_CASR_DPE_MASK   (0x2U)
#define	CAU_ADR_CASR_DPE_SHIFT   (1U)
#define	CAU_ADR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
#define	CAU_ADR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_ADR_CASR_VER_SHIFT   (28U)
#define	CAU_ADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
#define	CAU_ADR_CASR_IC_MASK   (0x1U)
#define	CAU_ADR_CASR_IC_SHIFT   (0U)
#define	CAU_ADR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
#define	CAU_ADR_CASR_DPE_MASK   (0x2U)
#define	CAU_ADR_CASR_DPE_SHIFT   (1U)
#define	CAU_ADR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
#define	CAU_ADR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_ADR_CASR_VER_SHIFT   (28U)
#define	CAU_ADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
#define	CAU_ADR_CASR_IC_MASK   (0x1U)
#define	CAU_ADR_CASR_IC_SHIFT   (0U)
#define	CAU_ADR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
#define	CAU_ADR_CASR_DPE_MASK   (0x2U)
#define	CAU_ADR_CASR_DPE_SHIFT   (1U)
#define	CAU_ADR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
#define	CAU_ADR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_ADR_CASR_VER_SHIFT   (28U)
#define	CAU_ADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)

ADR_CAA - Accumulator register - Add to register command
#define	CAU_ADR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CAA_ACC_SHIFT   (0U)
#define	CAU_ADR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
#define	CAU_ADR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CAA_ACC_SHIFT   (0U)
#define	CAU_ADR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
#define	CAU_ADR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CAA_ACC_SHIFT   (0U)
#define	CAU_ADR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
#define	CAU_ADR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CAA_ACC_SHIFT   (0U)
#define	CAU_ADR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
#define	CAU_ADR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CAA_ACC_SHIFT   (0U)
#define	CAU_ADR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)

ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command
#define	CAU_ADR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA0_SHIFT   (0U)
#define	CAU_ADR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
#define	CAU_ADR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA1_SHIFT   (0U)
#define	CAU_ADR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
#define	CAU_ADR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA2_SHIFT   (0U)
#define	CAU_ADR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
#define	CAU_ADR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA3_SHIFT   (0U)
#define	CAU_ADR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
#define	CAU_ADR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA4_SHIFT   (0U)
#define	CAU_ADR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
#define	CAU_ADR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA5_SHIFT   (0U)
#define	CAU_ADR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
#define	CAU_ADR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA6_SHIFT   (0U)
#define	CAU_ADR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
#define	CAU_ADR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA7_SHIFT   (0U)
#define	CAU_ADR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
#define	CAU_ADR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA8_SHIFT   (0U)
#define	CAU_ADR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
#define	CAU_ADR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA0_SHIFT   (0U)
#define	CAU_ADR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
#define	CAU_ADR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA1_SHIFT   (0U)
#define	CAU_ADR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
#define	CAU_ADR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA2_SHIFT   (0U)
#define	CAU_ADR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
#define	CAU_ADR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA3_SHIFT   (0U)
#define	CAU_ADR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
#define	CAU_ADR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA4_SHIFT   (0U)
#define	CAU_ADR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
#define	CAU_ADR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA5_SHIFT   (0U)
#define	CAU_ADR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
#define	CAU_ADR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA6_SHIFT   (0U)
#define	CAU_ADR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
#define	CAU_ADR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA7_SHIFT   (0U)
#define	CAU_ADR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
#define	CAU_ADR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA8_SHIFT   (0U)
#define	CAU_ADR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
#define	CAU_ADR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA0_SHIFT   (0U)
#define	CAU_ADR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
#define	CAU_ADR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA1_SHIFT   (0U)
#define	CAU_ADR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
#define	CAU_ADR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA2_SHIFT   (0U)
#define	CAU_ADR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
#define	CAU_ADR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA3_SHIFT   (0U)
#define	CAU_ADR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
#define	CAU_ADR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA4_SHIFT   (0U)
#define	CAU_ADR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
#define	CAU_ADR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA5_SHIFT   (0U)
#define	CAU_ADR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
#define	CAU_ADR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA6_SHIFT   (0U)
#define	CAU_ADR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
#define	CAU_ADR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA7_SHIFT   (0U)
#define	CAU_ADR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
#define	CAU_ADR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA8_SHIFT   (0U)
#define	CAU_ADR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
#define	CAU_ADR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA0_SHIFT   (0U)
#define	CAU_ADR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
#define	CAU_ADR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA1_SHIFT   (0U)
#define	CAU_ADR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
#define	CAU_ADR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA2_SHIFT   (0U)
#define	CAU_ADR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
#define	CAU_ADR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA3_SHIFT   (0U)
#define	CAU_ADR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
#define	CAU_ADR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA4_SHIFT   (0U)
#define	CAU_ADR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
#define	CAU_ADR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA5_SHIFT   (0U)
#define	CAU_ADR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
#define	CAU_ADR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA6_SHIFT   (0U)
#define	CAU_ADR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
#define	CAU_ADR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA7_SHIFT   (0U)
#define	CAU_ADR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
#define	CAU_ADR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA8_SHIFT   (0U)
#define	CAU_ADR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
#define	CAU_ADR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA0_SHIFT   (0U)
#define	CAU_ADR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
#define	CAU_ADR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA1_SHIFT   (0U)
#define	CAU_ADR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
#define	CAU_ADR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA2_SHIFT   (0U)
#define	CAU_ADR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
#define	CAU_ADR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA3_SHIFT   (0U)
#define	CAU_ADR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
#define	CAU_ADR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA4_SHIFT   (0U)
#define	CAU_ADR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
#define	CAU_ADR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA5_SHIFT   (0U)
#define	CAU_ADR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
#define	CAU_ADR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA6_SHIFT   (0U)
#define	CAU_ADR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
#define	CAU_ADR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA7_SHIFT   (0U)
#define	CAU_ADR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
#define	CAU_ADR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_ADR_CA_CA8_SHIFT   (0U)
#define	CAU_ADR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)

ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command
#define	CAU_ADR_CA_COUNT   (9U)

RADR_CASR - Status register - Reverse and Add to Register command
#define	CAU_RADR_CASR_IC_MASK   (0x1U)
#define	CAU_RADR_CASR_IC_SHIFT   (0U)
#define	CAU_RADR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
#define	CAU_RADR_CASR_DPE_MASK   (0x2U)
#define	CAU_RADR_CASR_DPE_SHIFT   (1U)
#define	CAU_RADR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
#define	CAU_RADR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_RADR_CASR_VER_SHIFT   (28U)
#define	CAU_RADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
#define	CAU_RADR_CASR_IC_MASK   0x1u
#define	CAU_RADR_CASR_IC_SHIFT   0
#define	CAU_RADR_CASR_DPE_MASK   0x2u
#define	CAU_RADR_CASR_DPE_SHIFT   1
#define	CAU_RADR_CASR_VER_MASK   0xF0000000u
#define	CAU_RADR_CASR_VER_SHIFT   28
#define	CAU_RADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
#define	CAU_RADR_CASR_IC_MASK   (0x1U)
#define	CAU_RADR_CASR_IC_SHIFT   (0U)
#define	CAU_RADR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
#define	CAU_RADR_CASR_DPE_MASK   (0x2U)
#define	CAU_RADR_CASR_DPE_SHIFT   (1U)
#define	CAU_RADR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
#define	CAU_RADR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_RADR_CASR_VER_SHIFT   (28U)
#define	CAU_RADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
#define	CAU_RADR_CASR_IC_MASK   (0x1U)
#define	CAU_RADR_CASR_IC_SHIFT   (0U)
#define	CAU_RADR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
#define	CAU_RADR_CASR_DPE_MASK   (0x2U)
#define	CAU_RADR_CASR_DPE_SHIFT   (1U)
#define	CAU_RADR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
#define	CAU_RADR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_RADR_CASR_VER_SHIFT   (28U)
#define	CAU_RADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
#define	CAU_RADR_CASR_IC_MASK   (0x1U)
#define	CAU_RADR_CASR_IC_SHIFT   (0U)
#define	CAU_RADR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
#define	CAU_RADR_CASR_DPE_MASK   (0x2U)
#define	CAU_RADR_CASR_DPE_SHIFT   (1U)
#define	CAU_RADR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
#define	CAU_RADR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_RADR_CASR_VER_SHIFT   (28U)
#define	CAU_RADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
#define	CAU_RADR_CASR_IC_MASK   (0x1U)
#define	CAU_RADR_CASR_IC_SHIFT   (0U)
#define	CAU_RADR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
#define	CAU_RADR_CASR_DPE_MASK   (0x2U)
#define	CAU_RADR_CASR_DPE_SHIFT   (1U)
#define	CAU_RADR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
#define	CAU_RADR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_RADR_CASR_VER_SHIFT   (28U)
#define	CAU_RADR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)

RADR_CAA - Accumulator register - Reverse and Add to Register command
#define	CAU_RADR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CAA_ACC_SHIFT   (0U)
#define	CAU_RADR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
#define	CAU_RADR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CAA_ACC_SHIFT   (0U)
#define	CAU_RADR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
#define	CAU_RADR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CAA_ACC_SHIFT   (0U)
#define	CAU_RADR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
#define	CAU_RADR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CAA_ACC_SHIFT   (0U)
#define	CAU_RADR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
#define	CAU_RADR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CAA_ACC_SHIFT   (0U)
#define	CAU_RADR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)

RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command
#define	CAU_RADR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA0_SHIFT   (0U)
#define	CAU_RADR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
#define	CAU_RADR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA1_SHIFT   (0U)
#define	CAU_RADR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
#define	CAU_RADR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA2_SHIFT   (0U)
#define	CAU_RADR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
#define	CAU_RADR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA3_SHIFT   (0U)
#define	CAU_RADR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
#define	CAU_RADR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA4_SHIFT   (0U)
#define	CAU_RADR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
#define	CAU_RADR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA5_SHIFT   (0U)
#define	CAU_RADR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
#define	CAU_RADR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA6_SHIFT   (0U)
#define	CAU_RADR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
#define	CAU_RADR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA7_SHIFT   (0U)
#define	CAU_RADR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
#define	CAU_RADR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA8_SHIFT   (0U)
#define	CAU_RADR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
#define	CAU_RADR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA0_SHIFT   (0U)
#define	CAU_RADR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
#define	CAU_RADR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA1_SHIFT   (0U)
#define	CAU_RADR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
#define	CAU_RADR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA2_SHIFT   (0U)
#define	CAU_RADR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
#define	CAU_RADR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA3_SHIFT   (0U)
#define	CAU_RADR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
#define	CAU_RADR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA4_SHIFT   (0U)
#define	CAU_RADR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
#define	CAU_RADR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA5_SHIFT   (0U)
#define	CAU_RADR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
#define	CAU_RADR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA6_SHIFT   (0U)
#define	CAU_RADR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
#define	CAU_RADR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA7_SHIFT   (0U)
#define	CAU_RADR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
#define	CAU_RADR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA8_SHIFT   (0U)
#define	CAU_RADR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
#define	CAU_RADR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA0_SHIFT   (0U)
#define	CAU_RADR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
#define	CAU_RADR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA1_SHIFT   (0U)
#define	CAU_RADR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
#define	CAU_RADR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA2_SHIFT   (0U)
#define	CAU_RADR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
#define	CAU_RADR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA3_SHIFT   (0U)
#define	CAU_RADR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
#define	CAU_RADR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA4_SHIFT   (0U)
#define	CAU_RADR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
#define	CAU_RADR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA5_SHIFT   (0U)
#define	CAU_RADR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
#define	CAU_RADR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA6_SHIFT   (0U)
#define	CAU_RADR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
#define	CAU_RADR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA7_SHIFT   (0U)
#define	CAU_RADR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
#define	CAU_RADR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA8_SHIFT   (0U)
#define	CAU_RADR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
#define	CAU_RADR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA0_SHIFT   (0U)
#define	CAU_RADR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
#define	CAU_RADR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA1_SHIFT   (0U)
#define	CAU_RADR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
#define	CAU_RADR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA2_SHIFT   (0U)
#define	CAU_RADR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
#define	CAU_RADR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA3_SHIFT   (0U)
#define	CAU_RADR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
#define	CAU_RADR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA4_SHIFT   (0U)
#define	CAU_RADR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
#define	CAU_RADR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA5_SHIFT   (0U)
#define	CAU_RADR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
#define	CAU_RADR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA6_SHIFT   (0U)
#define	CAU_RADR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
#define	CAU_RADR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA7_SHIFT   (0U)
#define	CAU_RADR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
#define	CAU_RADR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA8_SHIFT   (0U)
#define	CAU_RADR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
#define	CAU_RADR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA0_SHIFT   (0U)
#define	CAU_RADR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
#define	CAU_RADR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA1_SHIFT   (0U)
#define	CAU_RADR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
#define	CAU_RADR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA2_SHIFT   (0U)
#define	CAU_RADR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
#define	CAU_RADR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA3_SHIFT   (0U)
#define	CAU_RADR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
#define	CAU_RADR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA4_SHIFT   (0U)
#define	CAU_RADR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
#define	CAU_RADR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA5_SHIFT   (0U)
#define	CAU_RADR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
#define	CAU_RADR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA6_SHIFT   (0U)
#define	CAU_RADR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
#define	CAU_RADR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA7_SHIFT   (0U)
#define	CAU_RADR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
#define	CAU_RADR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_RADR_CA_CA8_SHIFT   (0U)
#define	CAU_RADR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)

RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command
#define	CAU_RADR_CA_COUNT   (9U)

XOR_CASR - Status register - Exclusive Or command
#define	CAU_XOR_CASR_IC_MASK   (0x1U)
#define	CAU_XOR_CASR_IC_SHIFT   (0U)
#define	CAU_XOR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
#define	CAU_XOR_CASR_DPE_MASK   (0x2U)
#define	CAU_XOR_CASR_DPE_SHIFT   (1U)
#define	CAU_XOR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
#define	CAU_XOR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_XOR_CASR_VER_SHIFT   (28U)
#define	CAU_XOR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
#define	CAU_XOR_CASR_IC_MASK   0x1u
#define	CAU_XOR_CASR_IC_SHIFT   0
#define	CAU_XOR_CASR_DPE_MASK   0x2u
#define	CAU_XOR_CASR_DPE_SHIFT   1
#define	CAU_XOR_CASR_VER_MASK   0xF0000000u
#define	CAU_XOR_CASR_VER_SHIFT   28
#define	CAU_XOR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
#define	CAU_XOR_CASR_IC_MASK   (0x1U)
#define	CAU_XOR_CASR_IC_SHIFT   (0U)
#define	CAU_XOR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
#define	CAU_XOR_CASR_DPE_MASK   (0x2U)
#define	CAU_XOR_CASR_DPE_SHIFT   (1U)
#define	CAU_XOR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
#define	CAU_XOR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_XOR_CASR_VER_SHIFT   (28U)
#define	CAU_XOR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
#define	CAU_XOR_CASR_IC_MASK   (0x1U)
#define	CAU_XOR_CASR_IC_SHIFT   (0U)
#define	CAU_XOR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
#define	CAU_XOR_CASR_DPE_MASK   (0x2U)
#define	CAU_XOR_CASR_DPE_SHIFT   (1U)
#define	CAU_XOR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
#define	CAU_XOR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_XOR_CASR_VER_SHIFT   (28U)
#define	CAU_XOR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
#define	CAU_XOR_CASR_IC_MASK   (0x1U)
#define	CAU_XOR_CASR_IC_SHIFT   (0U)
#define	CAU_XOR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
#define	CAU_XOR_CASR_DPE_MASK   (0x2U)
#define	CAU_XOR_CASR_DPE_SHIFT   (1U)
#define	CAU_XOR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
#define	CAU_XOR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_XOR_CASR_VER_SHIFT   (28U)
#define	CAU_XOR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
#define	CAU_XOR_CASR_IC_MASK   (0x1U)
#define	CAU_XOR_CASR_IC_SHIFT   (0U)
#define	CAU_XOR_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
#define	CAU_XOR_CASR_DPE_MASK   (0x2U)
#define	CAU_XOR_CASR_DPE_SHIFT   (1U)
#define	CAU_XOR_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
#define	CAU_XOR_CASR_VER_MASK   (0xF0000000U)
#define	CAU_XOR_CASR_VER_SHIFT   (28U)
#define	CAU_XOR_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)

XOR_CAA - Accumulator register - Exclusive Or command
#define	CAU_XOR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CAA_ACC_SHIFT   (0U)
#define	CAU_XOR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
#define	CAU_XOR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CAA_ACC_SHIFT   (0U)
#define	CAU_XOR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
#define	CAU_XOR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CAA_ACC_SHIFT   (0U)
#define	CAU_XOR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
#define	CAU_XOR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CAA_ACC_SHIFT   (0U)
#define	CAU_XOR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
#define	CAU_XOR_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CAA_ACC_SHIFT   (0U)
#define	CAU_XOR_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)

XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command
#define	CAU_XOR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA0_SHIFT   (0U)
#define	CAU_XOR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
#define	CAU_XOR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA1_SHIFT   (0U)
#define	CAU_XOR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
#define	CAU_XOR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA2_SHIFT   (0U)
#define	CAU_XOR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
#define	CAU_XOR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA3_SHIFT   (0U)
#define	CAU_XOR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
#define	CAU_XOR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA4_SHIFT   (0U)
#define	CAU_XOR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
#define	CAU_XOR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA5_SHIFT   (0U)
#define	CAU_XOR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
#define	CAU_XOR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA6_SHIFT   (0U)
#define	CAU_XOR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
#define	CAU_XOR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA7_SHIFT   (0U)
#define	CAU_XOR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
#define	CAU_XOR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA8_SHIFT   (0U)
#define	CAU_XOR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
#define	CAU_XOR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA0_SHIFT   (0U)
#define	CAU_XOR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
#define	CAU_XOR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA1_SHIFT   (0U)
#define	CAU_XOR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
#define	CAU_XOR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA2_SHIFT   (0U)
#define	CAU_XOR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
#define	CAU_XOR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA3_SHIFT   (0U)
#define	CAU_XOR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
#define	CAU_XOR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA4_SHIFT   (0U)
#define	CAU_XOR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
#define	CAU_XOR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA5_SHIFT   (0U)
#define	CAU_XOR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
#define	CAU_XOR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA6_SHIFT   (0U)
#define	CAU_XOR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
#define	CAU_XOR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA7_SHIFT   (0U)
#define	CAU_XOR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
#define	CAU_XOR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA8_SHIFT   (0U)
#define	CAU_XOR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
#define	CAU_XOR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA0_SHIFT   (0U)
#define	CAU_XOR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
#define	CAU_XOR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA1_SHIFT   (0U)
#define	CAU_XOR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
#define	CAU_XOR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA2_SHIFT   (0U)
#define	CAU_XOR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
#define	CAU_XOR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA3_SHIFT   (0U)
#define	CAU_XOR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
#define	CAU_XOR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA4_SHIFT   (0U)
#define	CAU_XOR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
#define	CAU_XOR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA5_SHIFT   (0U)
#define	CAU_XOR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
#define	CAU_XOR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA6_SHIFT   (0U)
#define	CAU_XOR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
#define	CAU_XOR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA7_SHIFT   (0U)
#define	CAU_XOR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
#define	CAU_XOR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA8_SHIFT   (0U)
#define	CAU_XOR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
#define	CAU_XOR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA0_SHIFT   (0U)
#define	CAU_XOR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
#define	CAU_XOR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA1_SHIFT   (0U)
#define	CAU_XOR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
#define	CAU_XOR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA2_SHIFT   (0U)
#define	CAU_XOR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
#define	CAU_XOR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA3_SHIFT   (0U)
#define	CAU_XOR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
#define	CAU_XOR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA4_SHIFT   (0U)
#define	CAU_XOR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
#define	CAU_XOR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA5_SHIFT   (0U)
#define	CAU_XOR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
#define	CAU_XOR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA6_SHIFT   (0U)
#define	CAU_XOR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
#define	CAU_XOR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA7_SHIFT   (0U)
#define	CAU_XOR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
#define	CAU_XOR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA8_SHIFT   (0U)
#define	CAU_XOR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
#define	CAU_XOR_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA0_SHIFT   (0U)
#define	CAU_XOR_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
#define	CAU_XOR_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA1_SHIFT   (0U)
#define	CAU_XOR_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
#define	CAU_XOR_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA2_SHIFT   (0U)
#define	CAU_XOR_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
#define	CAU_XOR_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA3_SHIFT   (0U)
#define	CAU_XOR_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
#define	CAU_XOR_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA4_SHIFT   (0U)
#define	CAU_XOR_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
#define	CAU_XOR_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA5_SHIFT   (0U)
#define	CAU_XOR_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
#define	CAU_XOR_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA6_SHIFT   (0U)
#define	CAU_XOR_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
#define	CAU_XOR_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA7_SHIFT   (0U)
#define	CAU_XOR_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
#define	CAU_XOR_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_XOR_CA_CA8_SHIFT   (0U)
#define	CAU_XOR_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)

XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command
#define	CAU_XOR_CA_COUNT   (9U)

ROTL_CASR - Status register - Rotate Left command
#define	CAU_ROTL_CASR_IC_MASK   (0x1U)
#define	CAU_ROTL_CASR_IC_SHIFT   (0U)
#define	CAU_ROTL_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
#define	CAU_ROTL_CASR_DPE_MASK   (0x2U)
#define	CAU_ROTL_CASR_DPE_SHIFT   (1U)
#define	CAU_ROTL_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
#define	CAU_ROTL_CASR_VER_MASK   (0xF0000000U)
#define	CAU_ROTL_CASR_VER_SHIFT   (28U)
#define	CAU_ROTL_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
#define	CAU_ROTL_CASR_IC_MASK   0x1u
#define	CAU_ROTL_CASR_IC_SHIFT   0
#define	CAU_ROTL_CASR_DPE_MASK   0x2u
#define	CAU_ROTL_CASR_DPE_SHIFT   1
#define	CAU_ROTL_CASR_VER_MASK   0xF0000000u
#define	CAU_ROTL_CASR_VER_SHIFT   28
#define	CAU_ROTL_CASR_VER(x)   (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
#define	CAU_ROTL_CASR_IC_MASK   (0x1U)
#define	CAU_ROTL_CASR_IC_SHIFT   (0U)
#define	CAU_ROTL_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
#define	CAU_ROTL_CASR_DPE_MASK   (0x2U)
#define	CAU_ROTL_CASR_DPE_SHIFT   (1U)
#define	CAU_ROTL_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
#define	CAU_ROTL_CASR_VER_MASK   (0xF0000000U)
#define	CAU_ROTL_CASR_VER_SHIFT   (28U)
#define	CAU_ROTL_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
#define	CAU_ROTL_CASR_IC_MASK   (0x1U)
#define	CAU_ROTL_CASR_IC_SHIFT   (0U)
#define	CAU_ROTL_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
#define	CAU_ROTL_CASR_DPE_MASK   (0x2U)
#define	CAU_ROTL_CASR_DPE_SHIFT   (1U)
#define	CAU_ROTL_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
#define	CAU_ROTL_CASR_VER_MASK   (0xF0000000U)
#define	CAU_ROTL_CASR_VER_SHIFT   (28U)
#define	CAU_ROTL_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
#define	CAU_ROTL_CASR_IC_MASK   (0x1U)
#define	CAU_ROTL_CASR_IC_SHIFT   (0U)
#define	CAU_ROTL_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
#define	CAU_ROTL_CASR_DPE_MASK   (0x2U)
#define	CAU_ROTL_CASR_DPE_SHIFT   (1U)
#define	CAU_ROTL_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
#define	CAU_ROTL_CASR_VER_MASK   (0xF0000000U)
#define	CAU_ROTL_CASR_VER_SHIFT   (28U)
#define	CAU_ROTL_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
#define	CAU_ROTL_CASR_IC_MASK   (0x1U)
#define	CAU_ROTL_CASR_IC_SHIFT   (0U)
#define	CAU_ROTL_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
#define	CAU_ROTL_CASR_DPE_MASK   (0x2U)
#define	CAU_ROTL_CASR_DPE_SHIFT   (1U)
#define	CAU_ROTL_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
#define	CAU_ROTL_CASR_VER_MASK   (0xF0000000U)
#define	CAU_ROTL_CASR_VER_SHIFT   (28U)
#define	CAU_ROTL_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)

ROTL_CAA - Accumulator register - Rotate Left command
#define	CAU_ROTL_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CAA_ACC_SHIFT   (0U)
#define	CAU_ROTL_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
#define	CAU_ROTL_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CAA_ACC_SHIFT   (0U)
#define	CAU_ROTL_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
#define	CAU_ROTL_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CAA_ACC_SHIFT   (0U)
#define	CAU_ROTL_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
#define	CAU_ROTL_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CAA_ACC_SHIFT   (0U)
#define	CAU_ROTL_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
#define	CAU_ROTL_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CAA_ACC_SHIFT   (0U)
#define	CAU_ROTL_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)

ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command
#define	CAU_ROTL_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA0_SHIFT   (0U)
#define	CAU_ROTL_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
#define	CAU_ROTL_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA1_SHIFT   (0U)
#define	CAU_ROTL_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
#define	CAU_ROTL_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA2_SHIFT   (0U)
#define	CAU_ROTL_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
#define	CAU_ROTL_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA3_SHIFT   (0U)
#define	CAU_ROTL_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
#define	CAU_ROTL_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA4_SHIFT   (0U)
#define	CAU_ROTL_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
#define	CAU_ROTL_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA5_SHIFT   (0U)
#define	CAU_ROTL_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
#define	CAU_ROTL_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA6_SHIFT   (0U)
#define	CAU_ROTL_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
#define	CAU_ROTL_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA7_SHIFT   (0U)
#define	CAU_ROTL_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
#define	CAU_ROTL_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA8_SHIFT   (0U)
#define	CAU_ROTL_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
#define	CAU_ROTL_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA0_SHIFT   (0U)
#define	CAU_ROTL_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
#define	CAU_ROTL_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA1_SHIFT   (0U)
#define	CAU_ROTL_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
#define	CAU_ROTL_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA2_SHIFT   (0U)
#define	CAU_ROTL_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
#define	CAU_ROTL_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA3_SHIFT   (0U)
#define	CAU_ROTL_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
#define	CAU_ROTL_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA4_SHIFT   (0U)
#define	CAU_ROTL_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
#define	CAU_ROTL_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA5_SHIFT   (0U)
#define	CAU_ROTL_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
#define	CAU_ROTL_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA6_SHIFT   (0U)
#define	CAU_ROTL_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
#define	CAU_ROTL_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA7_SHIFT   (0U)
#define	CAU_ROTL_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
#define	CAU_ROTL_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA8_SHIFT   (0U)
#define	CAU_ROTL_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
#define	CAU_ROTL_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA0_SHIFT   (0U)
#define	CAU_ROTL_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
#define	CAU_ROTL_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA1_SHIFT   (0U)
#define	CAU_ROTL_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
#define	CAU_ROTL_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA2_SHIFT   (0U)
#define	CAU_ROTL_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
#define	CAU_ROTL_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA3_SHIFT   (0U)
#define	CAU_ROTL_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
#define	CAU_ROTL_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA4_SHIFT   (0U)
#define	CAU_ROTL_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
#define	CAU_ROTL_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA5_SHIFT   (0U)
#define	CAU_ROTL_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
#define	CAU_ROTL_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA6_SHIFT   (0U)
#define	CAU_ROTL_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
#define	CAU_ROTL_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA7_SHIFT   (0U)
#define	CAU_ROTL_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
#define	CAU_ROTL_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA8_SHIFT   (0U)
#define	CAU_ROTL_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
#define	CAU_ROTL_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA0_SHIFT   (0U)
#define	CAU_ROTL_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
#define	CAU_ROTL_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA1_SHIFT   (0U)
#define	CAU_ROTL_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
#define	CAU_ROTL_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA2_SHIFT   (0U)
#define	CAU_ROTL_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
#define	CAU_ROTL_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA3_SHIFT   (0U)
#define	CAU_ROTL_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
#define	CAU_ROTL_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA4_SHIFT   (0U)
#define	CAU_ROTL_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
#define	CAU_ROTL_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA5_SHIFT   (0U)
#define	CAU_ROTL_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
#define	CAU_ROTL_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA6_SHIFT   (0U)
#define	CAU_ROTL_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
#define	CAU_ROTL_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA7_SHIFT   (0U)
#define	CAU_ROTL_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
#define	CAU_ROTL_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA8_SHIFT   (0U)
#define	CAU_ROTL_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
#define	CAU_ROTL_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA0_SHIFT   (0U)
#define	CAU_ROTL_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
#define	CAU_ROTL_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA1_SHIFT   (0U)
#define	CAU_ROTL_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
#define	CAU_ROTL_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA2_SHIFT   (0U)
#define	CAU_ROTL_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
#define	CAU_ROTL_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA3_SHIFT   (0U)
#define	CAU_ROTL_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
#define	CAU_ROTL_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA4_SHIFT   (0U)
#define	CAU_ROTL_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
#define	CAU_ROTL_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA5_SHIFT   (0U)
#define	CAU_ROTL_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
#define	CAU_ROTL_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA6_SHIFT   (0U)
#define	CAU_ROTL_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
#define	CAU_ROTL_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA7_SHIFT   (0U)
#define	CAU_ROTL_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
#define	CAU_ROTL_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_ROTL_CA_CA8_SHIFT   (0U)
#define	CAU_ROTL_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)

ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command
#define	CAU_ROTL_CA_COUNT   (9U)

AESC_CASR - Status register - AES Column Operation command
#define	CAU_AESC_CASR_IC_MASK   (0x1U)
#define	CAU_AESC_CASR_IC_SHIFT   (0U)
#define	CAU_AESC_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
#define	CAU_AESC_CASR_DPE_MASK   (0x2U)
#define	CAU_AESC_CASR_DPE_SHIFT   (1U)
#define	CAU_AESC_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
#define	CAU_AESC_CASR_VER_MASK   (0xF0000000U)
#define	CAU_AESC_CASR_VER_SHIFT   (28U)
#define	CAU_AESC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
#define	CAU_AESC_CASR_IC_MASK   0x1u
#define	CAU_AESC_CASR_IC_SHIFT   0
#define	CAU_AESC_CASR_DPE_MASK   0x2u
#define	CAU_AESC_CASR_DPE_SHIFT   1
#define	CAU_AESC_CASR_VER_MASK   0xF0000000u
#define	CAU_AESC_CASR_VER_SHIFT   28
#define	CAU_AESC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
#define	CAU_AESC_CASR_IC_MASK   (0x1U)
#define	CAU_AESC_CASR_IC_SHIFT   (0U)
#define	CAU_AESC_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
#define	CAU_AESC_CASR_DPE_MASK   (0x2U)
#define	CAU_AESC_CASR_DPE_SHIFT   (1U)
#define	CAU_AESC_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
#define	CAU_AESC_CASR_VER_MASK   (0xF0000000U)
#define	CAU_AESC_CASR_VER_SHIFT   (28U)
#define	CAU_AESC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
#define	CAU_AESC_CASR_IC_MASK   (0x1U)
#define	CAU_AESC_CASR_IC_SHIFT   (0U)
#define	CAU_AESC_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
#define	CAU_AESC_CASR_DPE_MASK   (0x2U)
#define	CAU_AESC_CASR_DPE_SHIFT   (1U)
#define	CAU_AESC_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
#define	CAU_AESC_CASR_VER_MASK   (0xF0000000U)
#define	CAU_AESC_CASR_VER_SHIFT   (28U)
#define	CAU_AESC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
#define	CAU_AESC_CASR_IC_MASK   (0x1U)
#define	CAU_AESC_CASR_IC_SHIFT   (0U)
#define	CAU_AESC_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
#define	CAU_AESC_CASR_DPE_MASK   (0x2U)
#define	CAU_AESC_CASR_DPE_SHIFT   (1U)
#define	CAU_AESC_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
#define	CAU_AESC_CASR_VER_MASK   (0xF0000000U)
#define	CAU_AESC_CASR_VER_SHIFT   (28U)
#define	CAU_AESC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
#define	CAU_AESC_CASR_IC_MASK   (0x1U)
#define	CAU_AESC_CASR_IC_SHIFT   (0U)
#define	CAU_AESC_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
#define	CAU_AESC_CASR_DPE_MASK   (0x2U)
#define	CAU_AESC_CASR_DPE_SHIFT   (1U)
#define	CAU_AESC_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
#define	CAU_AESC_CASR_VER_MASK   (0xF0000000U)
#define	CAU_AESC_CASR_VER_SHIFT   (28U)
#define	CAU_AESC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)

AESC_CAA - Accumulator register - AES Column Operation command
#define	CAU_AESC_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CAA_ACC_SHIFT   (0U)
#define	CAU_AESC_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
#define	CAU_AESC_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CAA_ACC_SHIFT   (0U)
#define	CAU_AESC_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
#define	CAU_AESC_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CAA_ACC_SHIFT   (0U)
#define	CAU_AESC_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
#define	CAU_AESC_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CAA_ACC_SHIFT   (0U)
#define	CAU_AESC_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
#define	CAU_AESC_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CAA_ACC_SHIFT   (0U)
#define	CAU_AESC_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)

AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command
#define	CAU_AESC_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA0_SHIFT   (0U)
#define	CAU_AESC_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
#define	CAU_AESC_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA1_SHIFT   (0U)
#define	CAU_AESC_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
#define	CAU_AESC_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA2_SHIFT   (0U)
#define	CAU_AESC_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
#define	CAU_AESC_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA3_SHIFT   (0U)
#define	CAU_AESC_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
#define	CAU_AESC_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA4_SHIFT   (0U)
#define	CAU_AESC_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
#define	CAU_AESC_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA5_SHIFT   (0U)
#define	CAU_AESC_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
#define	CAU_AESC_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA6_SHIFT   (0U)
#define	CAU_AESC_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
#define	CAU_AESC_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA7_SHIFT   (0U)
#define	CAU_AESC_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
#define	CAU_AESC_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA8_SHIFT   (0U)
#define	CAU_AESC_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
#define	CAU_AESC_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA0_SHIFT   (0U)
#define	CAU_AESC_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
#define	CAU_AESC_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA1_SHIFT   (0U)
#define	CAU_AESC_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
#define	CAU_AESC_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA2_SHIFT   (0U)
#define	CAU_AESC_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
#define	CAU_AESC_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA3_SHIFT   (0U)
#define	CAU_AESC_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
#define	CAU_AESC_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA4_SHIFT   (0U)
#define	CAU_AESC_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
#define	CAU_AESC_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA5_SHIFT   (0U)
#define	CAU_AESC_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
#define	CAU_AESC_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA6_SHIFT   (0U)
#define	CAU_AESC_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
#define	CAU_AESC_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA7_SHIFT   (0U)
#define	CAU_AESC_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
#define	CAU_AESC_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA8_SHIFT   (0U)
#define	CAU_AESC_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
#define	CAU_AESC_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA0_SHIFT   (0U)
#define	CAU_AESC_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
#define	CAU_AESC_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA1_SHIFT   (0U)
#define	CAU_AESC_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
#define	CAU_AESC_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA2_SHIFT   (0U)
#define	CAU_AESC_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
#define	CAU_AESC_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA3_SHIFT   (0U)
#define	CAU_AESC_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
#define	CAU_AESC_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA4_SHIFT   (0U)
#define	CAU_AESC_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
#define	CAU_AESC_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA5_SHIFT   (0U)
#define	CAU_AESC_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
#define	CAU_AESC_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA6_SHIFT   (0U)
#define	CAU_AESC_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
#define	CAU_AESC_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA7_SHIFT   (0U)
#define	CAU_AESC_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
#define	CAU_AESC_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA8_SHIFT   (0U)
#define	CAU_AESC_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
#define	CAU_AESC_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA0_SHIFT   (0U)
#define	CAU_AESC_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
#define	CAU_AESC_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA1_SHIFT   (0U)
#define	CAU_AESC_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
#define	CAU_AESC_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA2_SHIFT   (0U)
#define	CAU_AESC_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
#define	CAU_AESC_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA3_SHIFT   (0U)
#define	CAU_AESC_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
#define	CAU_AESC_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA4_SHIFT   (0U)
#define	CAU_AESC_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
#define	CAU_AESC_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA5_SHIFT   (0U)
#define	CAU_AESC_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
#define	CAU_AESC_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA6_SHIFT   (0U)
#define	CAU_AESC_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
#define	CAU_AESC_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA7_SHIFT   (0U)
#define	CAU_AESC_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
#define	CAU_AESC_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA8_SHIFT   (0U)
#define	CAU_AESC_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
#define	CAU_AESC_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA0_SHIFT   (0U)
#define	CAU_AESC_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
#define	CAU_AESC_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA1_SHIFT   (0U)
#define	CAU_AESC_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
#define	CAU_AESC_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA2_SHIFT   (0U)
#define	CAU_AESC_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
#define	CAU_AESC_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA3_SHIFT   (0U)
#define	CAU_AESC_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
#define	CAU_AESC_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA4_SHIFT   (0U)
#define	CAU_AESC_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
#define	CAU_AESC_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA5_SHIFT   (0U)
#define	CAU_AESC_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
#define	CAU_AESC_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA6_SHIFT   (0U)
#define	CAU_AESC_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
#define	CAU_AESC_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA7_SHIFT   (0U)
#define	CAU_AESC_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
#define	CAU_AESC_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_AESC_CA_CA8_SHIFT   (0U)
#define	CAU_AESC_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)

AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command
#define	CAU_AESC_CA_COUNT   (9U)

AESIC_CASR - Status register - AES Inverse Column Operation command
#define	CAU_AESIC_CASR_IC_MASK   (0x1U)
#define	CAU_AESIC_CASR_IC_SHIFT   (0U)
#define	CAU_AESIC_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
#define	CAU_AESIC_CASR_DPE_MASK   (0x2U)
#define	CAU_AESIC_CASR_DPE_SHIFT   (1U)
#define	CAU_AESIC_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
#define	CAU_AESIC_CASR_VER_MASK   (0xF0000000U)
#define	CAU_AESIC_CASR_VER_SHIFT   (28U)
#define	CAU_AESIC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
#define	CAU_AESIC_CASR_IC_MASK   0x1u
#define	CAU_AESIC_CASR_IC_SHIFT   0
#define	CAU_AESIC_CASR_DPE_MASK   0x2u
#define	CAU_AESIC_CASR_DPE_SHIFT   1
#define	CAU_AESIC_CASR_VER_MASK   0xF0000000u
#define	CAU_AESIC_CASR_VER_SHIFT   28
#define	CAU_AESIC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
#define	CAU_AESIC_CASR_IC_MASK   (0x1U)
#define	CAU_AESIC_CASR_IC_SHIFT   (0U)
#define	CAU_AESIC_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
#define	CAU_AESIC_CASR_DPE_MASK   (0x2U)
#define	CAU_AESIC_CASR_DPE_SHIFT   (1U)
#define	CAU_AESIC_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
#define	CAU_AESIC_CASR_VER_MASK   (0xF0000000U)
#define	CAU_AESIC_CASR_VER_SHIFT   (28U)
#define	CAU_AESIC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
#define	CAU_AESIC_CASR_IC_MASK   (0x1U)
#define	CAU_AESIC_CASR_IC_SHIFT   (0U)
#define	CAU_AESIC_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
#define	CAU_AESIC_CASR_DPE_MASK   (0x2U)
#define	CAU_AESIC_CASR_DPE_SHIFT   (1U)
#define	CAU_AESIC_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
#define	CAU_AESIC_CASR_VER_MASK   (0xF0000000U)
#define	CAU_AESIC_CASR_VER_SHIFT   (28U)
#define	CAU_AESIC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
#define	CAU_AESIC_CASR_IC_MASK   (0x1U)
#define	CAU_AESIC_CASR_IC_SHIFT   (0U)
#define	CAU_AESIC_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
#define	CAU_AESIC_CASR_DPE_MASK   (0x2U)
#define	CAU_AESIC_CASR_DPE_SHIFT   (1U)
#define	CAU_AESIC_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
#define	CAU_AESIC_CASR_VER_MASK   (0xF0000000U)
#define	CAU_AESIC_CASR_VER_SHIFT   (28U)
#define	CAU_AESIC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
#define	CAU_AESIC_CASR_IC_MASK   (0x1U)
#define	CAU_AESIC_CASR_IC_SHIFT   (0U)
#define	CAU_AESIC_CASR_IC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
#define	CAU_AESIC_CASR_DPE_MASK   (0x2U)
#define	CAU_AESIC_CASR_DPE_SHIFT   (1U)
#define	CAU_AESIC_CASR_DPE(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
#define	CAU_AESIC_CASR_VER_MASK   (0xF0000000U)
#define	CAU_AESIC_CASR_VER_SHIFT   (28U)
#define	CAU_AESIC_CASR_VER(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)

AESIC_CAA - Accumulator register - AES Inverse Column Operation command
#define	CAU_AESIC_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CAA_ACC_SHIFT   (0U)
#define	CAU_AESIC_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
#define	CAU_AESIC_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CAA_ACC_SHIFT   (0U)
#define	CAU_AESIC_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
#define	CAU_AESIC_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CAA_ACC_SHIFT   (0U)
#define	CAU_AESIC_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
#define	CAU_AESIC_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CAA_ACC_SHIFT   (0U)
#define	CAU_AESIC_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
#define	CAU_AESIC_CAA_ACC_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CAA_ACC_SHIFT   (0U)
#define	CAU_AESIC_CAA_ACC(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)

AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command
#define	CAU_AESIC_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA0_SHIFT   (0U)
#define	CAU_AESIC_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
#define	CAU_AESIC_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA1_SHIFT   (0U)
#define	CAU_AESIC_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
#define	CAU_AESIC_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA2_SHIFT   (0U)
#define	CAU_AESIC_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
#define	CAU_AESIC_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA3_SHIFT   (0U)
#define	CAU_AESIC_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
#define	CAU_AESIC_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA4_SHIFT   (0U)
#define	CAU_AESIC_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
#define	CAU_AESIC_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA5_SHIFT   (0U)
#define	CAU_AESIC_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
#define	CAU_AESIC_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA6_SHIFT   (0U)
#define	CAU_AESIC_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
#define	CAU_AESIC_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA7_SHIFT   (0U)
#define	CAU_AESIC_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
#define	CAU_AESIC_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA8_SHIFT   (0U)
#define	CAU_AESIC_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
#define	CAU_AESIC_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA0_SHIFT   (0U)
#define	CAU_AESIC_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
#define	CAU_AESIC_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA1_SHIFT   (0U)
#define	CAU_AESIC_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
#define	CAU_AESIC_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA2_SHIFT   (0U)
#define	CAU_AESIC_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
#define	CAU_AESIC_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA3_SHIFT   (0U)
#define	CAU_AESIC_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
#define	CAU_AESIC_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA4_SHIFT   (0U)
#define	CAU_AESIC_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
#define	CAU_AESIC_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA5_SHIFT   (0U)
#define	CAU_AESIC_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
#define	CAU_AESIC_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA6_SHIFT   (0U)
#define	CAU_AESIC_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
#define	CAU_AESIC_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA7_SHIFT   (0U)
#define	CAU_AESIC_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
#define	CAU_AESIC_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA8_SHIFT   (0U)
#define	CAU_AESIC_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
#define	CAU_AESIC_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA0_SHIFT   (0U)
#define	CAU_AESIC_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
#define	CAU_AESIC_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA1_SHIFT   (0U)
#define	CAU_AESIC_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
#define	CAU_AESIC_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA2_SHIFT   (0U)
#define	CAU_AESIC_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
#define	CAU_AESIC_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA3_SHIFT   (0U)
#define	CAU_AESIC_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
#define	CAU_AESIC_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA4_SHIFT   (0U)
#define	CAU_AESIC_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
#define	CAU_AESIC_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA5_SHIFT   (0U)
#define	CAU_AESIC_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
#define	CAU_AESIC_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA6_SHIFT   (0U)
#define	CAU_AESIC_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
#define	CAU_AESIC_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA7_SHIFT   (0U)
#define	CAU_AESIC_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
#define	CAU_AESIC_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA8_SHIFT   (0U)
#define	CAU_AESIC_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
#define	CAU_AESIC_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA0_SHIFT   (0U)
#define	CAU_AESIC_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
#define	CAU_AESIC_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA1_SHIFT   (0U)
#define	CAU_AESIC_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
#define	CAU_AESIC_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA2_SHIFT   (0U)
#define	CAU_AESIC_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
#define	CAU_AESIC_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA3_SHIFT   (0U)
#define	CAU_AESIC_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
#define	CAU_AESIC_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA4_SHIFT   (0U)
#define	CAU_AESIC_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
#define	CAU_AESIC_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA5_SHIFT   (0U)
#define	CAU_AESIC_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
#define	CAU_AESIC_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA6_SHIFT   (0U)
#define	CAU_AESIC_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
#define	CAU_AESIC_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA7_SHIFT   (0U)
#define	CAU_AESIC_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
#define	CAU_AESIC_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA8_SHIFT   (0U)
#define	CAU_AESIC_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
#define	CAU_AESIC_CA_CA0_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA0_SHIFT   (0U)
#define	CAU_AESIC_CA_CA0(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
#define	CAU_AESIC_CA_CA1_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA1_SHIFT   (0U)
#define	CAU_AESIC_CA_CA1(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
#define	CAU_AESIC_CA_CA2_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA2_SHIFT   (0U)
#define	CAU_AESIC_CA_CA2(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
#define	CAU_AESIC_CA_CA3_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA3_SHIFT   (0U)
#define	CAU_AESIC_CA_CA3(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
#define	CAU_AESIC_CA_CA4_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA4_SHIFT   (0U)
#define	CAU_AESIC_CA_CA4(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
#define	CAU_AESIC_CA_CA5_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA5_SHIFT   (0U)
#define	CAU_AESIC_CA_CA5(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
#define	CAU_AESIC_CA_CA6_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA6_SHIFT   (0U)
#define	CAU_AESIC_CA_CA6(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
#define	CAU_AESIC_CA_CA7_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA7_SHIFT   (0U)
#define	CAU_AESIC_CA_CA7(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
#define	CAU_AESIC_CA_CA8_MASK   (0xFFFFFFFFU)
#define	CAU_AESIC_CA_CA8_SHIFT   (0U)
#define	CAU_AESIC_CA_CA8(x)   (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)

AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command
#define	CAU_AESIC_CA_COUNT   (9U)

Macro Definition Documentation

CAU

#define CAU   ((CAU_Type *)CAU_BASE)

Peripheral CAU base pointer

CAU_ADR_CASR_DPE [1/5]

#define CAU_ADR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_ADR_CASR_DPE [2/5]

#define CAU_ADR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_ADR_CASR_DPE [3/5]

#define CAU_ADR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_ADR_CASR_DPE [4/5]

#define CAU_ADR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_ADR_CASR_DPE [5/5]

#define CAU_ADR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_ADR_CASR_IC [1/5]

#define CAU_ADR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_ADR_CASR_IC [2/5]

#define CAU_ADR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_ADR_CASR_IC [3/5]

#define CAU_ADR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_ADR_CASR_IC [4/5]

#define CAU_ADR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_ADR_CASR_IC [5/5]

#define CAU_ADR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_ADR_CASR_VER [1/6]

#define CAU_ADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ADR_CASR_VER [2/6]

#define CAU_ADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ADR_CASR_VER [3/6]

#define CAU_ADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ADR_CASR_VER [4/6]

#define CAU_ADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ADR_CASR_VER [5/6]

#define CAU_ADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ADR_CASR_VER [6/6]

#define CAU_ADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESC_CASR_DPE [1/5]

#define CAU_AESC_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_AESC_CASR_DPE [2/5]

#define CAU_AESC_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_AESC_CASR_DPE [3/5]

#define CAU_AESC_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_AESC_CASR_DPE [4/5]

#define CAU_AESC_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_AESC_CASR_DPE [5/5]

#define CAU_AESC_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_AESC_CASR_IC [1/5]

#define CAU_AESC_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_AESC_CASR_IC [2/5]

#define CAU_AESC_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_AESC_CASR_IC [3/5]

#define CAU_AESC_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_AESC_CASR_IC [4/5]

#define CAU_AESC_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_AESC_CASR_IC [5/5]

#define CAU_AESC_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_AESC_CASR_VER [1/6]

#define CAU_AESC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESC_CASR_VER [2/6]

#define CAU_AESC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESC_CASR_VER [3/6]

#define CAU_AESC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESC_CASR_VER [4/6]

#define CAU_AESC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESC_CASR_VER [5/6]

#define CAU_AESC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESC_CASR_VER [6/6]

#define CAU_AESC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESIC_CASR_DPE [1/5]

#define CAU_AESIC_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_AESIC_CASR_DPE [2/5]

#define CAU_AESIC_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_AESIC_CASR_DPE [3/5]

#define CAU_AESIC_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_AESIC_CASR_DPE [4/5]

#define CAU_AESIC_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_AESIC_CASR_DPE [5/5]

#define CAU_AESIC_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_AESIC_CASR_IC [1/5]

#define CAU_AESIC_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_AESIC_CASR_IC [2/5]

#define CAU_AESIC_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_AESIC_CASR_IC [3/5]

#define CAU_AESIC_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_AESIC_CASR_IC [4/5]

#define CAU_AESIC_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_AESIC_CASR_IC [5/5]

#define CAU_AESIC_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_AESIC_CASR_VER [1/6]

#define CAU_AESIC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESIC_CASR_VER [2/6]

#define CAU_AESIC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESIC_CASR_VER [3/6]

#define CAU_AESIC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESIC_CASR_VER [4/6]

#define CAU_AESIC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESIC_CASR_VER [5/6]

#define CAU_AESIC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_AESIC_CASR_VER [6/6]

#define CAU_AESIC_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_BASE

#define CAU_BASE   (0xE0081000u)

Peripheral CAU base address

CAU_BASE_ADDRS

#define CAU_BASE_ADDRS   { CAU_BASE }

Array initializer of CAU peripheral base addresses

CAU_BASE_PTRS

#define CAU_BASE_PTRS   { CAU }

Array initializer of CAU peripheral base pointers

CAU_LDR_CASR_DPE [1/5]

#define CAU_LDR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_LDR_CASR_DPE [2/5]

#define CAU_LDR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_LDR_CASR_DPE [3/5]

#define CAU_LDR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_LDR_CASR_DPE [4/5]

#define CAU_LDR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_LDR_CASR_DPE [5/5]

#define CAU_LDR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_LDR_CASR_IC [1/5]

#define CAU_LDR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_LDR_CASR_IC [2/5]

#define CAU_LDR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_LDR_CASR_IC [3/5]

#define CAU_LDR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_LDR_CASR_IC [4/5]

#define CAU_LDR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_LDR_CASR_IC [5/5]

#define CAU_LDR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_LDR_CASR_VER [1/6]

#define CAU_LDR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_LDR_CASR_VER [2/6]

#define CAU_LDR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_LDR_CASR_VER [3/6]

#define CAU_LDR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_LDR_CASR_VER [4/6]

#define CAU_LDR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_LDR_CASR_VER [5/6]

#define CAU_LDR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_LDR_CASR_VER [6/6]

#define CAU_LDR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_RADR_CASR_DPE [1/5]

#define CAU_RADR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_RADR_CASR_DPE [2/5]

#define CAU_RADR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_RADR_CASR_DPE [3/5]

#define CAU_RADR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_RADR_CASR_DPE [4/5]

#define CAU_RADR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_RADR_CASR_DPE [5/5]

#define CAU_RADR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_RADR_CASR_IC [1/5]

#define CAU_RADR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_RADR_CASR_IC [2/5]

#define CAU_RADR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_RADR_CASR_IC [3/5]

#define CAU_RADR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_RADR_CASR_IC [4/5]

#define CAU_RADR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_RADR_CASR_IC [5/5]

#define CAU_RADR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_RADR_CASR_VER [1/6]

#define CAU_RADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_RADR_CASR_VER [2/6]

#define CAU_RADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_RADR_CASR_VER [3/6]

#define CAU_RADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_RADR_CASR_VER [4/6]

#define CAU_RADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_RADR_CASR_VER [5/6]

#define CAU_RADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_RADR_CASR_VER [6/6]

#define CAU_RADR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ROTL_CASR_DPE [1/5]

#define CAU_ROTL_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_ROTL_CASR_DPE [2/5]

#define CAU_ROTL_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_ROTL_CASR_DPE [3/5]

#define CAU_ROTL_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_ROTL_CASR_DPE [4/5]

#define CAU_ROTL_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_ROTL_CASR_DPE [5/5]

#define CAU_ROTL_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_ROTL_CASR_IC [1/5]

#define CAU_ROTL_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_ROTL_CASR_IC [2/5]

#define CAU_ROTL_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_ROTL_CASR_IC [3/5]

#define CAU_ROTL_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_ROTL_CASR_IC [4/5]

#define CAU_ROTL_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_ROTL_CASR_IC [5/5]

#define CAU_ROTL_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_ROTL_CASR_VER [1/6]

#define CAU_ROTL_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ROTL_CASR_VER [2/6]

#define CAU_ROTL_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ROTL_CASR_VER [3/6]

#define CAU_ROTL_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ROTL_CASR_VER [4/6]

#define CAU_ROTL_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ROTL_CASR_VER [5/6]

#define CAU_ROTL_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_ROTL_CASR_VER [6/6]

#define CAU_ROTL_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_STR_CASR_DPE [1/5]

#define CAU_STR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_STR_CASR_DPE [2/5]

#define CAU_STR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_STR_CASR_DPE [3/5]

#define CAU_STR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_STR_CASR_DPE [4/5]

#define CAU_STR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_STR_CASR_DPE [5/5]

#define CAU_STR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_STR_CASR_IC [1/5]

#define CAU_STR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_STR_CASR_IC [2/5]

#define CAU_STR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_STR_CASR_IC [3/5]

#define CAU_STR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_STR_CASR_IC [4/5]

#define CAU_STR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_STR_CASR_IC [5/5]

#define CAU_STR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_STR_CASR_VER [1/6]

#define CAU_STR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_STR_CASR_VER [2/6]

#define CAU_STR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_STR_CASR_VER [3/6]

#define CAU_STR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_STR_CASR_VER [4/6]

#define CAU_STR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_STR_CASR_VER [5/6]

#define CAU_STR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_STR_CASR_VER [6/6]

#define CAU_STR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_XOR_CASR_DPE [1/5]

#define CAU_XOR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_XOR_CASR_DPE [2/5]

#define CAU_XOR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_XOR_CASR_DPE [3/5]

#define CAU_XOR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_XOR_CASR_DPE [4/5]

#define CAU_XOR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_XOR_CASR_DPE [5/5]

#define CAU_XOR_CASR_DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)

DPE 0b0..No error detected 0b1..DES key parity error detected

CAU_XOR_CASR_IC [1/5]

#define CAU_XOR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_XOR_CASR_IC [2/5]

#define CAU_XOR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_XOR_CASR_IC [3/5]

#define CAU_XOR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_XOR_CASR_IC [4/5]

#define CAU_XOR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_XOR_CASR_IC [5/5]

#define CAU_XOR_CASR_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)

IC 0b0..No illegal commands issued 0b1..Illegal command issued

CAU_XOR_CASR_VER [1/6]

#define CAU_XOR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_XOR_CASR_VER [2/6]

#define CAU_XOR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_XOR_CASR_VER [3/6]

#define CAU_XOR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_XOR_CASR_VER [4/6]

#define CAU_XOR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_XOR_CASR_VER [5/6]

#define CAU_XOR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)

CAU_XOR_CASR_VER [6/6]

#define CAU_XOR_CASR_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)

VER - CAU version 0b0001..Initial CAU version 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)