CTRL - Control Register
#define	ENC_CTRL_CMPIE_MASK (0x1U)

#define	ENC_CTRL_CMPIE_SHIFT (0U)

#define	ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)

#define	ENC_CTRL_CMPIRQ_MASK (0x2U)

#define	ENC_CTRL_CMPIRQ_SHIFT (1U)

#define	ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)

#define	ENC_CTRL_WDE_MASK (0x4U)

#define	ENC_CTRL_WDE_SHIFT (2U)

#define	ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)

#define	ENC_CTRL_DIE_MASK (0x8U)

#define	ENC_CTRL_DIE_SHIFT (3U)

#define	ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)

#define	ENC_CTRL_DIRQ_MASK (0x10U)

#define	ENC_CTRL_DIRQ_SHIFT (4U)

#define	ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)

#define	ENC_CTRL_XNE_MASK (0x20U)

#define	ENC_CTRL_XNE_SHIFT (5U)

#define	ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)

#define	ENC_CTRL_XIP_MASK (0x40U)

#define	ENC_CTRL_XIP_SHIFT (6U)

#define	ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)

#define	ENC_CTRL_XIE_MASK (0x80U)

#define	ENC_CTRL_XIE_SHIFT (7U)

#define	ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)

#define	ENC_CTRL_XIRQ_MASK (0x100U)

#define	ENC_CTRL_XIRQ_SHIFT (8U)

#define	ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)

#define	ENC_CTRL_PH1_MASK (0x200U)

#define	ENC_CTRL_PH1_SHIFT (9U)

#define	ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)

#define	ENC_CTRL_REV_MASK (0x400U)

#define	ENC_CTRL_REV_SHIFT (10U)

#define	ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)

#define	ENC_CTRL_SWIP_MASK (0x800U)

#define	ENC_CTRL_SWIP_SHIFT (11U)

#define	ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)

#define	ENC_CTRL_HNE_MASK (0x1000U)

#define	ENC_CTRL_HNE_SHIFT (12U)

#define	ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)

#define	ENC_CTRL_HIP_MASK (0x2000U)

#define	ENC_CTRL_HIP_SHIFT (13U)

#define	ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)

#define	ENC_CTRL_HIE_MASK (0x4000U)

#define	ENC_CTRL_HIE_SHIFT (14U)

#define	ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)

#define	ENC_CTRL_HIRQ_MASK (0x8000U)

#define	ENC_CTRL_HIRQ_SHIFT (15U)

#define	ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)

#define	EWM_CTRL_EWMEN_MASK (0x1U)

#define	EWM_CTRL_EWMEN_SHIFT (0U)

#define	EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)

#define	EWM_CTRL_ASSIN_MASK (0x2U)

#define	EWM_CTRL_ASSIN_SHIFT (1U)

#define	EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)

#define	EWM_CTRL_INEN_MASK (0x4U)

#define	EWM_CTRL_INEN_SHIFT (2U)

#define	EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)

#define	EWM_CTRL_INTEN_MASK (0x8U)

#define	EWM_CTRL_INTEN_SHIFT (3U)

#define	EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)

#define	PWM_CTRL_DBLEN_MASK (0x1U)

#define	PWM_CTRL_DBLEN_SHIFT (0U)

#define	PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)

#define	PWM_CTRL_DBLX_MASK (0x2U)

#define	PWM_CTRL_DBLX_SHIFT (1U)

#define	PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)

#define	PWM_CTRL_LDMOD_MASK (0x4U)

#define	PWM_CTRL_LDMOD_SHIFT (2U)

#define	PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)

#define	PWM_CTRL_PRSC_MASK (0x70U)

#define	PWM_CTRL_PRSC_SHIFT (4U)

#define	PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)

#define	PWM_CTRL_DT_MASK (0x300U)

#define	PWM_CTRL_DT_SHIFT (8U)

#define	PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)

#define	PWM_CTRL_FULL_MASK (0x400U)

#define	PWM_CTRL_FULL_SHIFT (10U)

#define	PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)

#define	PWM_CTRL_HALF_MASK (0x800U)

#define	PWM_CTRL_HALF_SHIFT (11U)

#define	PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)

#define	PWM_CTRL_LDFQ_MASK (0xF000U)

#define	PWM_CTRL_LDFQ_SHIFT (12U)

#define	PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)

FILT - Input Filter Register
#define	ENC_FILT_FILT_PER_MASK (0xFFU)

#define	ENC_FILT_FILT_PER_SHIFT (0U)

#define	ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)

#define	ENC_FILT_FILT_CNT_MASK (0x700U)

#define	ENC_FILT_FILT_CNT_SHIFT (8U)

#define	ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)

WTR - Watchdog Timeout Register
#define	ENC_WTR_WDOG_MASK (0xFFFFU)

#define	ENC_WTR_WDOG_SHIFT (0U)

#define	ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)

POSD - Position Difference Counter Register
#define	ENC_POSD_POSD_MASK (0xFFFFU)

#define	ENC_POSD_POSD_SHIFT (0U)

#define	ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)

POSDH - Position Difference Hold Register
#define	ENC_POSDH_POSDH_MASK (0xFFFFU)

#define	ENC_POSDH_POSDH_SHIFT (0U)

#define	ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)

REV - Revolution Counter Register
#define	ENC_REV_REV_MASK (0xFFFFU)

#define	ENC_REV_REV_SHIFT (0U)

#define	ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)

REVH - Revolution Hold Register
#define	ENC_REVH_REVH_MASK (0xFFFFU)

#define	ENC_REVH_REVH_SHIFT (0U)

#define	ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)

UPOS - Upper Position Counter Register
#define	ENC_UPOS_POS_MASK (0xFFFFU)

#define	ENC_UPOS_POS_SHIFT (0U)

#define	ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)

LPOS - Lower Position Counter Register
#define	ENC_LPOS_POS_MASK (0xFFFFU)

#define	ENC_LPOS_POS_SHIFT (0U)

#define	ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)

UPOSH - Upper Position Hold Register
#define	ENC_UPOSH_POSH_MASK (0xFFFFU)

#define	ENC_UPOSH_POSH_SHIFT (0U)

#define	ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)

LPOSH - Lower Position Hold Register
#define	ENC_LPOSH_POSH_MASK (0xFFFFU)

#define	ENC_LPOSH_POSH_SHIFT (0U)

#define	ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)

UINIT - Upper Initialization Register
#define	ENC_UINIT_INIT_MASK (0xFFFFU)

#define	ENC_UINIT_INIT_SHIFT (0U)

#define	ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)

LINIT - Lower Initialization Register
#define	ENC_LINIT_INIT_MASK (0xFFFFU)

#define	ENC_LINIT_INIT_SHIFT (0U)

#define	ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)

IMR - Input Monitor Register
#define	ENC_IMR_HOME_MASK (0x1U)

#define	ENC_IMR_HOME_SHIFT (0U)

#define	ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)

#define	ENC_IMR_INDEX_MASK (0x2U)

#define	ENC_IMR_INDEX_SHIFT (1U)

#define	ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)

#define	ENC_IMR_PHB_MASK (0x4U)

#define	ENC_IMR_PHB_SHIFT (2U)

#define	ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)

#define	ENC_IMR_PHA_MASK (0x8U)

#define	ENC_IMR_PHA_SHIFT (3U)

#define	ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)

#define	ENC_IMR_FHOM_MASK (0x10U)

#define	ENC_IMR_FHOM_SHIFT (4U)

#define	ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)

#define	ENC_IMR_FIND_MASK (0x20U)

#define	ENC_IMR_FIND_SHIFT (5U)

#define	ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)

#define	ENC_IMR_FPHB_MASK (0x40U)

#define	ENC_IMR_FPHB_SHIFT (6U)

#define	ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)

#define	ENC_IMR_FPHA_MASK (0x80U)

#define	ENC_IMR_FPHA_SHIFT (7U)

#define	ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)

TST - Test Register
#define	ENC_TST_TEST_COUNT_MASK (0xFFU)

#define	ENC_TST_TEST_COUNT_SHIFT (0U)

#define	ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)

#define	ENC_TST_TEST_PERIOD_MASK (0x1F00U)

#define	ENC_TST_TEST_PERIOD_SHIFT (8U)

#define	ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)

#define	ENC_TST_QDN_MASK (0x2000U)

#define	ENC_TST_QDN_SHIFT (13U)

#define	ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)

#define	ENC_TST_TCE_MASK (0x4000U)

#define	ENC_TST_TCE_SHIFT (14U)

#define	ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)

#define	ENC_TST_TEN_MASK (0x8000U)

#define	ENC_TST_TEN_SHIFT (15U)

#define	ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)

CTRL2 - Control 2 register
#define	ENC_CTRL2_UPDHLD_MASK (0x1U)

#define	ENC_CTRL2_UPDHLD_SHIFT (0U)

#define	ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

#define	ENC_CTRL2_UPDPOS_MASK (0x2U)

#define	ENC_CTRL2_UPDPOS_SHIFT (1U)

#define	ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

#define	ENC_CTRL2_MOD_MASK (0x4U)

#define	ENC_CTRL2_MOD_SHIFT (2U)

#define	ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

#define	ENC_CTRL2_DIR_MASK (0x8U)

#define	ENC_CTRL2_DIR_SHIFT (3U)

#define	ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

#define	ENC_CTRL2_RUIE_MASK (0x10U)

#define	ENC_CTRL2_RUIE_SHIFT (4U)

#define	ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

#define	ENC_CTRL2_RUIRQ_MASK (0x20U)

#define	ENC_CTRL2_RUIRQ_SHIFT (5U)

#define	ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

#define	ENC_CTRL2_ROIE_MASK (0x40U)

#define	ENC_CTRL2_ROIE_SHIFT (6U)

#define	ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

#define	ENC_CTRL2_ROIRQ_MASK (0x80U)

#define	ENC_CTRL2_ROIRQ_SHIFT (7U)

#define	ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

#define	ENC_CTRL2_REVMOD_MASK (0x100U)

#define	ENC_CTRL2_REVMOD_SHIFT (8U)

#define	ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

#define	ENC_CTRL2_OUTCTL_MASK (0x200U)

#define	ENC_CTRL2_OUTCTL_SHIFT (9U)

#define	ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

#define	ENC_CTRL2_SABIE_MASK (0x400U)

#define	ENC_CTRL2_SABIE_SHIFT (10U)

#define	ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

#define	ENC_CTRL2_SABIRQ_MASK (0x800U)

#define	ENC_CTRL2_SABIRQ_SHIFT (11U)

#define	ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)

UMOD - Upper Modulus Register
#define	ENC_UMOD_MOD_MASK (0xFFFFU)

#define	ENC_UMOD_MOD_SHIFT (0U)

#define	ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)

LMOD - Lower Modulus Register
#define	ENC_LMOD_MOD_MASK (0xFFFFU)

#define	ENC_LMOD_MOD_SHIFT (0U)

#define	ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)

UCOMP - Upper Position Compare Register
#define	ENC_UCOMP_COMP_MASK (0xFFFFU)

#define	ENC_UCOMP_COMP_SHIFT (0U)

#define	ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)

LCOMP - Lower Position Compare Register
#define	ENC_LCOMP_COMP_MASK (0xFFFFU)

#define	ENC_LCOMP_COMP_SHIFT (0U)

#define	ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)

Macro Definition Documentation

◆ ENC_CTRL2_DIR

#define ENC_CTRL2_DIR ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)

DIR - Count Direction Flag 0b0..Last count was in the down direction 0b1..Last count was in the up direction

◆ ENC_CTRL2_MOD

#define ENC_CTRL2_MOD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)

MOD - Enable Modulo Counting 0b0..Disable modulo counting 0b1..Enable modulo counting

◆ ENC_CTRL2_OUTCTL

#define ENC_CTRL2_OUTCTL ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)

OUTCTL - Output Control 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read.

◆ ENC_CTRL2_REVMOD

#define ENC_CTRL2_REVMOD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)

REVMOD - Revolution Counter Modulus Enable 0b0..Use INDEX pulse to increment/decrement revolution counter (REV). 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV).

◆ ENC_CTRL2_ROIE

#define ENC_CTRL2_ROIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)

ROIE - Roll-over Interrupt Enable 0b0..Roll-over interrupt is disabled 0b1..Roll-over interrupt is enabled

◆ ENC_CTRL2_ROIRQ

#define ENC_CTRL2_ROIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)

ROIRQ - Roll-over Interrupt Request 0b0..No roll-over has occurred 0b1..Roll-over has occurred

◆ ENC_CTRL2_RUIE

#define ENC_CTRL2_RUIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)

RUIE - Roll-under Interrupt Enable 0b0..Roll-under interrupt is disabled 0b1..Roll-under interrupt is enabled

◆ ENC_CTRL2_RUIRQ

#define ENC_CTRL2_RUIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)

RUIRQ - Roll-under Interrupt Request 0b0..No roll-under has occurred 0b1..Roll-under has occurred

◆ ENC_CTRL2_SABIE

#define ENC_CTRL2_SABIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)

SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled. 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled.

◆ ENC_CTRL2_SABIRQ

#define ENC_CTRL2_SABIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)

SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request 0b0..No simultaneous change of PHASEA and PHASEB has occurred. 0b1..A simultaneous change of PHASEA and PHASEB has occurred.

◆ ENC_CTRL2_UPDHLD

#define ENC_CTRL2_UPDHLD ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)

UPDHLD - Update Hold Registers 0b0..Disable updates of hold registers on rising edge of TRIGGER 0b1..Enable updates of hold registers on rising edge of TRIGGER

◆ ENC_CTRL2_UPDPOS

#define ENC_CTRL2_UPDPOS ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)

UPDPOS - Update Position Registers 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER

◆ ENC_CTRL_CMPIE

#define ENC_CTRL_CMPIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)

CMPIE - Compare Interrupt Enable 0b0..Compare interrupt is disabled 0b1..Compare interrupt is enabled

◆ ENC_CTRL_CMPIRQ

#define ENC_CTRL_CMPIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)

CMPIRQ - Compare Interrupt Request 0b0..No match has occurred 0b1..COMP match has occurred

◆ ENC_CTRL_DIE

#define ENC_CTRL_DIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)

DIE - Watchdog Timeout Interrupt Enable 0b0..Watchdog timer interrupt is disabled 0b1..Watchdog timer interrupt is enabled

◆ ENC_CTRL_DIRQ

#define ENC_CTRL_DIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)

DIRQ - Watchdog Timeout Interrupt Request 0b0..No interrupt has occurred 0b1..Watchdog timeout interrupt has occurred

◆ ENC_CTRL_HIE

#define ENC_CTRL_HIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)

HIE - HOME Interrupt Enable 0b0..Disable HOME interrupts 0b1..Enable HOME interrupts

◆ ENC_CTRL_HIP

#define ENC_CTRL_HIP ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)

HIP - Enable HOME to Initialize Position Counters UPOS and LPOS 0b0..No action 0b1..HOME signal initializes the position counter

◆ ENC_CTRL_HIRQ

#define ENC_CTRL_HIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)

HIRQ - HOME Signal Transition Interrupt Request 0b0..No interrupt 0b1..HOME signal transition interrupt request

◆ ENC_CTRL_HNE

#define ENC_CTRL_HNE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)

HNE - Use Negative Edge of HOME Input 0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS 0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS

◆ ENC_CTRL_PH1

#define ENC_CTRL_PH1 ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)

PH1 - Enable Signal Phase Count Mode 0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up

◆ ENC_CTRL_REV

#define ENC_CTRL_REV ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)

REV - Enable Reverse Direction Counting 0b0..Count normally 0b1..Count in the reverse direction

◆ ENC_CTRL_SWIP

#define ENC_CTRL_SWIP ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)

SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS 0b0..No action 0b1..Initialize position counter

◆ ENC_CTRL_WDE

#define ENC_CTRL_WDE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)

WDE - Watchdog Enable 0b0..Watchdog timer is disabled 0b1..Watchdog timer is enabled

◆ ENC_CTRL_XIE

#define ENC_CTRL_XIE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)

XIE - INDEX Pulse Interrupt Enable 0b0..INDEX pulse interrupt is disabled 0b1..INDEX pulse interrupt is enabled

◆ ENC_CTRL_XIP

#define ENC_CTRL_XIP ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)

XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS 0b0..No action 0b1..INDEX pulse initializes the position counter

◆ ENC_CTRL_XIRQ

#define ENC_CTRL_XIRQ ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)

XIRQ - INDEX Pulse Interrupt Request 0b0..No interrupt has occurred 0b1..INDEX pulse interrupt has occurred

◆ ENC_CTRL_XNE

#define ENC_CTRL_XNE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)

XNE - Use Negative Edge of INDEX Pulse 0b0..Use positive transition edge of INDEX pulse 0b1..Use negative transition edge of INDEX pulse

◆ ENC_TST_QDN

#define ENC_TST_QDN ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)

QDN - Quadrature Decoder Negative Signal 0b0..Leaves quadrature decoder signal in a positive direction 0b1..Generates a negative quadrature decoder signal

◆ ENC_TST_TCE

#define ENC_TST_TCE ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)

TCE - Test Counter Enable 0b0..Test count is not enabled 0b1..Test count is enabled

◆ ENC_TST_TEN

#define ENC_TST_TEN ( x ) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)

TEN - Test Mode Enable 0b0..Test module is not enabled 0b1..Test module is enabled

◆ PWM_CTRL_DBLEN

#define PWM_CTRL_DBLEN ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)

DBLEN - Double Switching Enable 0b0..Double switching disabled. 0b1..Double switching enabled.

◆ PWM_CTRL_DBLX

#define PWM_CTRL_DBLX ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)

DBLX - PWMX Double Switching Enable 0b0..PWMX double pulse disabled. 0b1..PWMX double pulse enabled.

◆ PWM_CTRL_FULL

#define PWM_CTRL_FULL ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)

FULL - Full Cycle Reload 0b0..Full-cycle reloads disabled. 0b1..Full-cycle reloads enabled.

◆ PWM_CTRL_HALF

#define PWM_CTRL_HALF ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)

HALF - Half Cycle Reload 0b0..Half-cycle reloads disabled. 0b1..Half-cycle reloads enabled.

◆ PWM_CTRL_LDFQ

#define PWM_CTRL_LDFQ ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)

LDFQ - Load Frequency 0b0000..Every PWM opportunity 0b0001..Every 2 PWM opportunities 0b0010..Every 3 PWM opportunities 0b0011..Every 4 PWM opportunities 0b0100..Every 5 PWM opportunities 0b0101..Every 6 PWM opportunities 0b0110..Every 7 PWM opportunities 0b0111..Every 8 PWM opportunities 0b1000..Every 9 PWM opportunities 0b1001..Every 10 PWM opportunities 0b1010..Every 11 PWM opportunities 0b1011..Every 12 PWM opportunities 0b1100..Every 13 PWM opportunities 0b1101..Every 14 PWM opportunities 0b1110..Every 15 PWM opportunities 0b1111..Every 16 PWM opportunities

◆ PWM_CTRL_LDMOD

#define PWM_CTRL_LDMOD ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)

LDMOD - Load Mode Select 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL0[LDOK] is set. 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL0[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].

◆ PWM_CTRL_PRSC

#define PWM_CTRL_PRSC ( x ) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)

PRSC - Prescaler 0b000..PWM clock frequency = fclk 0b001..PWM clock frequency = fclk/2 0b010..PWM clock frequency = fclk/4 0b011..PWM clock frequency = fclk/8 0b100..PWM clock frequency = fclk/16 0b101..PWM clock frequency = fclk/32 0b110..PWM clock frequency = fclk/64 0b111..PWM clock frequency = fclk/128

CTRL - Control Register

FILT - Input Filter Register

WTR - Watchdog Timeout Register

POSD - Position Difference Counter Register

POSDH - Position Difference Hold Register

REV - Revolution Counter Register

REVH - Revolution Hold Register

UPOS - Upper Position Counter Register

LPOS - Lower Position Counter Register

UPOSH - Upper Position Hold Register

LPOSH - Lower Position Hold Register

UINIT - Upper Initialization Register

LINIT - Lower Initialization Register

IMR - Input Monitor Register

TST - Test Register

CTRL2 - Control 2 register

UMOD - Upper Modulus Register

LMOD - Lower Modulus Register

UCOMP - Upper Position Compare Register

LCOMP - Lower Position Compare Register