VREF Peripheral Access Layer

Topics
	VREF Register Masks
	WDOG Peripheral Access Layer
	Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
	SDK Compatibility

Data Structures
struct	VREF_Type

Macros
#define	VREF_BASE   (0x40074000u)
#define	VREF   ((VREF_Type *)VREF_BASE)
#define	VREF_BASE   (0x40074000u)
#define	VREF   ((VREF_Type *)VREF_BASE)
#define	VREF_BASE_ADDRS   { VREF_BASE }
#define	VREF_BASE_PTRS   { VREF }
#define	VREF_BASE   (0x40074000u)
#define	VREF   ((VREF_Type *)VREF_BASE)
#define	VREF_BASE_ADDRS   { VREF_BASE }
#define	VREF_BASE_PTRS   { VREF }
#define	VREF_BASE   (0x40074000u)
#define	VREF   ((VREF_Type *)VREF_BASE)
#define	VREF_BASE_ADDRS   { VREF_BASE }
#define	VREF_BASE_PTRS   { VREF }

Variables
__IO uint32_t	ADC_Type::SC1 [2]
__IO uint32_t	ADC_Type::CFG1
__IO uint32_t	ADC_Type::CFG2
__I uint32_t	ADC_Type::R [2]
__IO uint32_t	ADC_Type::CV1
__IO uint32_t	ADC_Type::CV2
__IO uint32_t	ADC_Type::SC2
__IO uint32_t	ADC_Type::SC3
__IO uint32_t	ADC_Type::OFS
__IO uint32_t	ADC_Type::PG
__IO uint32_t	ADC_Type::MG
__IO uint32_t	ADC_Type::CLPD
__IO uint32_t	ADC_Type::CLPS
__IO uint32_t	ADC_Type::CLP4
__IO uint32_t	ADC_Type::CLP3
__IO uint32_t	ADC_Type::CLP2
__IO uint32_t	ADC_Type::CLP1
__IO uint32_t	ADC_Type::CLP0
__IO uint32_t	ADC_Type::PGA
__IO uint32_t	ADC_Type::CLMD
__IO uint32_t	ADC_Type::CLMS
__IO uint32_t	ADC_Type::CLM4
__IO uint32_t	ADC_Type::CLM3
__IO uint32_t	ADC_Type::CLM2
__IO uint32_t	ADC_Type::CLM1
__IO uint32_t	ADC_Type::CLM0
__IO uint32_t	AIPS_Type::MPRA
uint8_t	AIPS_Type::RESERVED_0 [28]
__IO uint32_t	AIPS_Type::PACRA
__IO uint32_t	AIPS_Type::PACRB
__IO uint32_t	AIPS_Type::PACRC
__IO uint32_t	AIPS_Type::PACRD
uint8_t	AIPS_Type::RESERVED_1 [16]
__IO uint32_t	AIPS_Type::PACRE
__IO uint32_t	AIPS_Type::PACRF
__IO uint32_t	AIPS_Type::PACRG
__IO uint32_t	AIPS_Type::PACRH
__IO uint32_t	AIPS_Type::PACRI
__IO uint32_t	AIPS_Type::PACRJ
__IO uint32_t	AIPS_Type::PACRK
__IO uint32_t	AIPS_Type::PACRL
__IO uint32_t	AIPS_Type::PACRM
__IO uint32_t	AIPS_Type::PACRN
__IO uint32_t	AIPS_Type::PACRO
__IO uint32_t	AIPS_Type::PACRP
__IO uint32_t   AXBS_Type::PRS
uint8_t   AXBS_Type::RESERVED_0 [12]
__IO uint32_t   AXBS_Type::CRS
uint8_t   AXBS_Type::RESERVED_1 [236]
struct {
}	AXBS_Type::SLAVE [5]
__IO uint32_t	AXBS_Type::MGPCR0
__IO uint32_t	AXBS_Type::MGPCR1
uint8_t	AXBS_Type::RESERVED_2 [252]
__IO uint32_t	AXBS_Type::MGPCR2
uint8_t	AXBS_Type::RESERVED_3 [252]
__IO uint32_t	AXBS_Type::MGPCR3
uint8_t	AXBS_Type::RESERVED_4 [252]
__IO uint32_t	AXBS_Type::MGPCR4
uint8_t	AXBS_Type::RESERVED_5 [252]
__IO uint32_t	AXBS_Type::MGPCR5
__IO uint32_t	CAN_Type::MCR
__IO uint32_t	CAN_Type::CTRL1
__IO uint32_t	CAN_Type::TIMER
uint8_t	CAN_Type::RESERVED_0 [4]
__IO uint32_t	CAN_Type::RXMGMASK
__IO uint32_t	CAN_Type::RX14MASK
__IO uint32_t	CAN_Type::RX15MASK
__IO uint32_t	CAN_Type::ECR
__IO uint32_t	CAN_Type::ESR1
uint8_t	CAN_Type::RESERVED_1 [4]
__IO uint32_t	CAN_Type::IMASK1
uint8_t	CAN_Type::RESERVED_2 [4]
__IO uint32_t	CAN_Type::IFLAG1
__IO uint32_t	CAN_Type::CTRL2
__I uint32_t	CAN_Type::ESR2
uint8_t	CAN_Type::RESERVED_3 [8]
__I uint32_t	CAN_Type::CRCR
__IO uint32_t	CAN_Type::RXFGMASK
__I uint32_t	CAN_Type::RXFIR
uint8_t	CAN_Type::RESERVED_4 [48]
__IO uint32_t   CAN_Type::CS
__IO uint32_t   CAN_Type::ID
__IO uint32_t   CAN_Type::WORD0
__IO uint32_t   CAN_Type::WORD1
struct {
}	CAN_Type::MB [16]
uint8_t	CAN_Type::RESERVED_5 [1792]
__IO uint32_t	CAN_Type::RXIMR [16]
__O uint32_t	CAU_Type::DIRECT [16]
uint8_t	CAU_Type::RESERVED_0 [2048]
__O uint32_t	CAU_Type::LDR_CASR
__O uint32_t	CAU_Type::LDR_CAA
__O uint32_t	CAU_Type::LDR_CA [9]
uint8_t	CAU_Type::RESERVED_1 [20]
__I uint32_t	CAU_Type::STR_CASR
__I uint32_t	CAU_Type::STR_CAA
__I uint32_t	CAU_Type::STR_CA [9]
uint8_t	CAU_Type::RESERVED_2 [20]
__O uint32_t	CAU_Type::ADR_CASR
__O uint32_t	CAU_Type::ADR_CAA
__O uint32_t	CAU_Type::ADR_CA [9]
uint8_t	CAU_Type::RESERVED_3 [20]
__O uint32_t	CAU_Type::RADR_CASR
__O uint32_t	CAU_Type::RADR_CAA
__O uint32_t	CAU_Type::RADR_CA [9]
uint8_t	CAU_Type::RESERVED_4 [84]
__O uint32_t	CAU_Type::XOR_CASR
__O uint32_t	CAU_Type::XOR_CAA
__O uint32_t	CAU_Type::XOR_CA [9]
uint8_t	CAU_Type::RESERVED_5 [20]
__O uint32_t	CAU_Type::ROTL_CASR
__O uint32_t	CAU_Type::ROTL_CAA
__O uint32_t	CAU_Type::ROTL_CA [9]
uint8_t	CAU_Type::RESERVED_6 [276]
__O uint32_t	CAU_Type::AESC_CASR
__O uint32_t	CAU_Type::AESC_CAA
__O uint32_t	CAU_Type::AESC_CA [9]
uint8_t	CAU_Type::RESERVED_7 [20]
__O uint32_t	CAU_Type::AESIC_CASR
__O uint32_t	CAU_Type::AESIC_CAA
__O uint32_t	CAU_Type::AESIC_CA [9]
__IO uint8_t	CMP_Type::CR0
__IO uint8_t	CMP_Type::CR1
__IO uint8_t	CMP_Type::FPR
__IO uint8_t	CMP_Type::SCR
__IO uint8_t	CMP_Type::DACCR
__IO uint8_t	CMP_Type::MUXCR
__IO uint8_t	CMT_Type::CGH1
__IO uint8_t	CMT_Type::CGL1
__IO uint8_t	CMT_Type::CGH2
__IO uint8_t	CMT_Type::CGL2
__IO uint8_t	CMT_Type::OC
__IO uint8_t	CMT_Type::MSC
__IO uint8_t	CMT_Type::CMD1
__IO uint8_t	CMT_Type::CMD2
__IO uint8_t	CMT_Type::CMD3
__IO uint8_t	CMT_Type::CMD4
__IO uint8_t	CMT_Type::PPS
__IO uint8_t	CMT_Type::DMA
__IO uint16_t   CRC_Type::CRCL
__IO uint16_t   CRC_Type::CRCH
struct {
}   CRC_Type::ACCESS16BIT
__IO uint32_t   CRC_Type::CRC
__IO uint8_t   CRC_Type::CRCLL
__IO uint8_t   CRC_Type::CRCLU
__IO uint8_t   CRC_Type::CRCHL
__IO uint8_t   CRC_Type::CRCHU
struct {
}   CRC_Type::ACCESS8BIT
union {
};
__IO uint16_t   CRC_Type::GPOLYL
__IO uint16_t   CRC_Type::GPOLYH
struct {
}   CRC_Type::GPOLY_ACCESS16BIT
__IO uint32_t   CRC_Type::GPOLY
__IO uint8_t   CRC_Type::GPOLYLL
__IO uint8_t   CRC_Type::GPOLYLU
__IO uint8_t   CRC_Type::GPOLYHL
__IO uint8_t   CRC_Type::GPOLYHU
struct {
}   CRC_Type::GPOLY_ACCESS8BIT
union {
};
__IO uint32_t   CRC_Type::CTRL
uint8_t   CRC_Type::RESERVED_0 [3]
__IO uint8_t   CRC_Type::CTRLHU
struct {
}   CRC_Type::CTRL_ACCESS8BIT
union {
};
__IO uint8_t   DAC_Type::DATL
__IO uint8_t   DAC_Type::DATH
struct {
}	DAC_Type::DAT [16]
__IO uint8_t	DAC_Type::SR
__IO uint8_t	DAC_Type::C0
__IO uint8_t	DAC_Type::C1
__IO uint8_t	DAC_Type::C2
__IO uint32_t	DMA_Type::CR
__I uint32_t	DMA_Type::ES
uint8_t	DMA_Type::RESERVED_0 [4]
__IO uint32_t	DMA_Type::ERQ
uint8_t	DMA_Type::RESERVED_1 [4]
__IO uint32_t	DMA_Type::EEI
__O uint8_t	DMA_Type::CEEI
__O uint8_t	DMA_Type::SEEI
__O uint8_t	DMA_Type::CERQ
__O uint8_t	DMA_Type::SERQ
__O uint8_t	DMA_Type::CDNE
__O uint8_t	DMA_Type::SSRT
__O uint8_t	DMA_Type::CERR
__O uint8_t	DMA_Type::CINT
uint8_t	DMA_Type::RESERVED_2 [4]
__IO uint32_t	DMA_Type::INT
uint8_t	DMA_Type::RESERVED_3 [4]
__IO uint32_t	DMA_Type::ERR
uint8_t	DMA_Type::RESERVED_4 [4]
__IO uint32_t	DMA_Type::HRS
uint8_t	DMA_Type::RESERVED_5 [200]
__IO uint8_t	DMA_Type::DCHPRI3
__IO uint8_t	DMA_Type::DCHPRI2
__IO uint8_t	DMA_Type::DCHPRI1
__IO uint8_t	DMA_Type::DCHPRI0
__IO uint8_t	DMA_Type::DCHPRI7
__IO uint8_t	DMA_Type::DCHPRI6
__IO uint8_t	DMA_Type::DCHPRI5
__IO uint8_t	DMA_Type::DCHPRI4
__IO uint8_t	DMA_Type::DCHPRI11
__IO uint8_t	DMA_Type::DCHPRI10
__IO uint8_t	DMA_Type::DCHPRI9
__IO uint8_t	DMA_Type::DCHPRI8
__IO uint8_t	DMA_Type::DCHPRI15
__IO uint8_t	DMA_Type::DCHPRI14
__IO uint8_t	DMA_Type::DCHPRI13
__IO uint8_t	DMA_Type::DCHPRI12
uint8_t	DMA_Type::RESERVED_6 [3824]
__IO uint32_t   DMA_Type::SADDR
__IO uint16_t   DMA_Type::SOFF
__IO uint16_t   DMA_Type::ATTR
__IO uint32_t   DMA_Type::NBYTES_MLNO
__IO uint32_t   DMA_Type::NBYTES_MLOFFNO
__IO uint32_t   DMA_Type::NBYTES_MLOFFYES
union {
}
__IO uint32_t   DMA_Type::SLAST
__IO uint32_t   DMA_Type::DADDR
__IO uint16_t   DMA_Type::DOFF
__IO uint16_t   DMA_Type::CITER_ELINKNO
__IO uint16_t   DMA_Type::CITER_ELINKYES
union {
}
__IO uint32_t   DMA_Type::DLAST_SGA
__IO uint16_t   DMA_Type::CSR
__IO uint16_t   DMA_Type::BITER_ELINKNO
__IO uint16_t   DMA_Type::BITER_ELINKYES
union {
}
struct {
}	DMA_Type::TCD [16]
__IO uint8_t	DMAMUX_Type::CHCFG [16]
uint8_t	ENET_Type::RESERVED_0 [4]
__IO uint32_t	ENET_Type::EIR
__IO uint32_t	ENET_Type::EIMR
uint8_t	ENET_Type::RESERVED_1 [4]
__IO uint32_t	ENET_Type::RDAR
__IO uint32_t	ENET_Type::TDAR
uint8_t	ENET_Type::RESERVED_2 [12]
__IO uint32_t	ENET_Type::ECR
uint8_t	ENET_Type::RESERVED_3 [24]
__IO uint32_t	ENET_Type::MMFR
__IO uint32_t	ENET_Type::MSCR
uint8_t	ENET_Type::RESERVED_4 [28]
__IO uint32_t	ENET_Type::MIBC
uint8_t	ENET_Type::RESERVED_5 [28]
__IO uint32_t	ENET_Type::RCR
uint8_t	ENET_Type::RESERVED_6 [60]
__IO uint32_t	ENET_Type::TCR
uint8_t	ENET_Type::RESERVED_7 [28]
__IO uint32_t	ENET_Type::PALR
__IO uint32_t	ENET_Type::PAUR
__IO uint32_t	ENET_Type::OPD
uint8_t	ENET_Type::RESERVED_8 [40]
__IO uint32_t	ENET_Type::IAUR
__IO uint32_t	ENET_Type::IALR
__IO uint32_t	ENET_Type::GAUR
__IO uint32_t	ENET_Type::GALR
uint8_t	ENET_Type::RESERVED_9 [28]
__IO uint32_t	ENET_Type::TFWR
uint8_t	ENET_Type::RESERVED_10 [56]
__IO uint32_t	ENET_Type::RDSR
__IO uint32_t	ENET_Type::TDSR
__IO uint32_t	ENET_Type::MRBR
uint8_t	ENET_Type::RESERVED_11 [4]
__IO uint32_t	ENET_Type::RSFL
__IO uint32_t	ENET_Type::RSEM
__IO uint32_t	ENET_Type::RAEM
__IO uint32_t	ENET_Type::RAFL
__IO uint32_t	ENET_Type::TSEM
__IO uint32_t	ENET_Type::TAEM
__IO uint32_t	ENET_Type::TAFL
__IO uint32_t	ENET_Type::TIPG
__IO uint32_t	ENET_Type::FTRL
uint8_t	ENET_Type::RESERVED_12 [12]
__IO uint32_t	ENET_Type::TACC
__IO uint32_t	ENET_Type::RACC
uint8_t	ENET_Type::RESERVED_13 [56]
__IO uint32_t	ENET_Type::RMON_T_DROP
__IO uint32_t	ENET_Type::RMON_T_PACKETS
__IO uint32_t	ENET_Type::RMON_T_BC_PKT
__IO uint32_t	ENET_Type::RMON_T_MC_PKT
__IO uint32_t	ENET_Type::RMON_T_CRC_ALIGN
__IO uint32_t	ENET_Type::RMON_T_UNDERSIZE
__IO uint32_t	ENET_Type::RMON_T_OVERSIZE
__IO uint32_t	ENET_Type::RMON_T_FRAG
__IO uint32_t	ENET_Type::RMON_T_JAB
__IO uint32_t	ENET_Type::RMON_T_COL
__IO uint32_t	ENET_Type::RMON_T_P64
__IO uint32_t	ENET_Type::RMON_T_P65TO127
__IO uint32_t	ENET_Type::RMON_T_P128TO255
__IO uint32_t	ENET_Type::RMON_T_P256TO511
__IO uint32_t	ENET_Type::RMON_T_P512TO1023
__IO uint32_t	ENET_Type::RMON_T_P1024TO2047
__IO uint32_t	ENET_Type::RMON_T_P_GTE2048
__I uint32_t	ENET_Type::RMON_T_OCTETS
__IO uint32_t	ENET_Type::IEEE_T_DROP
__IO uint32_t	ENET_Type::IEEE_T_FRAME_OK
__IO uint32_t	ENET_Type::IEEE_T_1COL
__IO uint32_t	ENET_Type::IEEE_T_MCOL
__IO uint32_t	ENET_Type::IEEE_T_DEF
__IO uint32_t	ENET_Type::IEEE_T_LCOL
__IO uint32_t	ENET_Type::IEEE_T_EXCOL
__IO uint32_t	ENET_Type::IEEE_T_MACERR
__IO uint32_t	ENET_Type::IEEE_T_CSERR
__IO uint32_t	ENET_Type::IEEE_T_SQE
__IO uint32_t	ENET_Type::IEEE_T_FDXFC
__I uint32_t	ENET_Type::IEEE_T_OCTETS_OK
uint8_t	ENET_Type::RESERVED_14 [12]
__IO uint32_t	ENET_Type::RMON_R_PACKETS
__IO uint32_t	ENET_Type::RMON_R_BC_PKT
__IO uint32_t	ENET_Type::RMON_R_MC_PKT
__IO uint32_t	ENET_Type::RMON_R_CRC_ALIGN
__IO uint32_t	ENET_Type::RMON_R_UNDERSIZE
__IO uint32_t	ENET_Type::RMON_R_OVERSIZE
__IO uint32_t	ENET_Type::RMON_R_FRAG
__IO uint32_t	ENET_Type::RMON_R_JAB
__IO uint32_t	ENET_Type::RMON_R_RESVD_0
__IO uint32_t	ENET_Type::RMON_R_P64
__IO uint32_t	ENET_Type::RMON_R_P65TO127
__IO uint32_t	ENET_Type::RMON_R_P128TO255
__IO uint32_t	ENET_Type::RMON_R_P256TO511
__IO uint32_t	ENET_Type::RMON_R_P512TO1023
__IO uint32_t	ENET_Type::RMON_R_P1024TO2047
__IO uint32_t	ENET_Type::RMON_R_P_GTE2048
__I uint32_t	ENET_Type::RMON_R_OCTETS
__IO uint32_t	ENET_Type::IEEE_R_DROP
__IO uint32_t	ENET_Type::IEEE_R_FRAME_OK
__IO uint32_t	ENET_Type::IEEE_R_CRC
__IO uint32_t	ENET_Type::IEEE_R_ALIGN
__IO uint32_t	ENET_Type::IEEE_R_MACERR
__IO uint32_t	ENET_Type::IEEE_R_FDXFC
__I uint32_t	ENET_Type::IEEE_R_OCTETS_OK
uint8_t	ENET_Type::RESERVED_15 [284]
__IO uint32_t	ENET_Type::ATCR
__IO uint32_t	ENET_Type::ATVR
__IO uint32_t	ENET_Type::ATOFF
__IO uint32_t	ENET_Type::ATPER
__IO uint32_t	ENET_Type::ATCOR
__IO uint32_t	ENET_Type::ATINC
__IO uint32_t	ENET_Type::ATSTMP
uint8_t	ENET_Type::RESERVED_16 [488]
__IO uint32_t	ENET_Type::TGSR
__IO uint32_t   ENET_Type::TCSR
__IO uint32_t   ENET_Type::TCCR
struct {
}	ENET_Type::CHANNEL [4]
__IO uint8_t	EWM_Type::CTRL
__O uint8_t	EWM_Type::SERV
__IO uint8_t	EWM_Type::CMPL
__IO uint8_t	EWM_Type::CMPH
uint8_t	EWM_Type::RESERVED_0 [1]
__IO uint8_t	EWM_Type::CLKPRESCALER
__IO uint32_t   FB_Type::CSAR
__IO uint32_t   FB_Type::CSMR
__IO uint32_t   FB_Type::CSCR
struct {
}	FB_Type::CS [6]
uint8_t	FB_Type::RESERVED_0 [24]
__IO uint32_t	FB_Type::CSPMCR
__IO uint32_t	FMC_Type::PFAPR
__IO uint32_t	FMC_Type::PFB0CR
__IO uint32_t	FMC_Type::PFB1CR
uint8_t	FMC_Type::RESERVED_0 [244]
__IO uint32_t	FMC_Type::TAGVD [4][8]
uint8_t	FMC_Type::RESERVED_1 [128]
__IO uint32_t   FMC_Type::DATA_U
__IO uint32_t   FMC_Type::DATA_L
struct {
}	FMC_Type::SET [4][8]
__IO uint8_t	FTFL_Type::FSTAT
__IO uint8_t	FTFL_Type::FCNFG
__I uint8_t	FTFL_Type::FSEC
__I uint8_t	FTFL_Type::FOPT
__IO uint8_t	FTFL_Type::FCCOB3
__IO uint8_t	FTFL_Type::FCCOB2
__IO uint8_t	FTFL_Type::FCCOB1
__IO uint8_t	FTFL_Type::FCCOB0
__IO uint8_t	FTFL_Type::FCCOB7
__IO uint8_t	FTFL_Type::FCCOB6
__IO uint8_t	FTFL_Type::FCCOB5
__IO uint8_t	FTFL_Type::FCCOB4
__IO uint8_t	FTFL_Type::FCCOBB
__IO uint8_t	FTFL_Type::FCCOBA
__IO uint8_t	FTFL_Type::FCCOB9
__IO uint8_t	FTFL_Type::FCCOB8
__IO uint8_t	FTFL_Type::FPROT3
__IO uint8_t	FTFL_Type::FPROT2
__IO uint8_t	FTFL_Type::FPROT1
__IO uint8_t	FTFL_Type::FPROT0
uint8_t	FTFL_Type::RESERVED_0 [2]
__IO uint8_t	FTFL_Type::FEPROT
__IO uint8_t	FTFL_Type::FDPROT
__IO uint32_t	FTM_Type::SC
__IO uint32_t	FTM_Type::CNT
__IO uint32_t	FTM_Type::MOD
__IO uint32_t   FTM_Type::CnSC
__IO uint32_t   FTM_Type::CnV
struct {
}	FTM_Type::CONTROLS [8]
__IO uint32_t	FTM_Type::CNTIN
__IO uint32_t	FTM_Type::STATUS
__IO uint32_t	FTM_Type::MODE
__IO uint32_t	FTM_Type::SYNC
__IO uint32_t	FTM_Type::OUTINIT
__IO uint32_t	FTM_Type::OUTMASK
__IO uint32_t	FTM_Type::COMBINE
__IO uint32_t	FTM_Type::DEADTIME
__IO uint32_t	FTM_Type::EXTTRIG
__IO uint32_t	FTM_Type::POL
__IO uint32_t	FTM_Type::FMS
__IO uint32_t	FTM_Type::FILTER
__IO uint32_t	FTM_Type::FLTCTRL
__IO uint32_t	FTM_Type::QDCTRL
__IO uint32_t	FTM_Type::CONF
__IO uint32_t	FTM_Type::FLTPOL
__IO uint32_t	FTM_Type::SYNCONF
__IO uint32_t	FTM_Type::INVCTRL
__IO uint32_t	FTM_Type::SWOCTRL
__IO uint32_t	FTM_Type::PWMLOAD
__IO uint32_t	GPIO_Type::PDOR
__O uint32_t	GPIO_Type::PSOR
__O uint32_t	GPIO_Type::PCOR
__O uint32_t	GPIO_Type::PTOR
__I uint32_t	GPIO_Type::PDIR
__IO uint32_t	GPIO_Type::PDDR
__IO uint8_t	I2C_Type::A1
__IO uint8_t	I2C_Type::F
__IO uint8_t	I2C_Type::C1
__IO uint8_t	I2C_Type::S
__IO uint8_t	I2C_Type::D
__IO uint8_t	I2C_Type::C2
__IO uint8_t	I2C_Type::FLT
__IO uint8_t	I2C_Type::RA
__IO uint8_t	I2C_Type::SMB
__IO uint8_t	I2C_Type::A2
__IO uint8_t	I2C_Type::SLTH
__IO uint8_t	I2C_Type::SLTL
__IO uint32_t	I2S_Type::TCSR
__IO uint32_t	I2S_Type::TCR1
__IO uint32_t	I2S_Type::TCR2
__IO uint32_t	I2S_Type::TCR3
__IO uint32_t	I2S_Type::TCR4
__IO uint32_t	I2S_Type::TCR5
uint8_t	I2S_Type::RESERVED_0 [8]
__O uint32_t	I2S_Type::TDR [2]
uint8_t	I2S_Type::RESERVED_1 [24]
__I uint32_t	I2S_Type::TFR [2]
uint8_t	I2S_Type::RESERVED_2 [24]
__IO uint32_t	I2S_Type::TMR
uint8_t	I2S_Type::RESERVED_3 [28]
__IO uint32_t	I2S_Type::RCSR
__IO uint32_t	I2S_Type::RCR1
__IO uint32_t	I2S_Type::RCR2
__IO uint32_t	I2S_Type::RCR3
__IO uint32_t	I2S_Type::RCR4
__IO uint32_t	I2S_Type::RCR5
uint8_t	I2S_Type::RESERVED_4 [8]
__I uint32_t	I2S_Type::RDR [2]
uint8_t	I2S_Type::RESERVED_5 [24]
__I uint32_t	I2S_Type::RFR [2]
uint8_t	I2S_Type::RESERVED_6 [24]
__IO uint32_t	I2S_Type::RMR
uint8_t	I2S_Type::RESERVED_7 [28]
__IO uint32_t	I2S_Type::MCR
__IO uint32_t	I2S_Type::MDR
__IO uint8_t	LLWU_Type::PE1
__IO uint8_t	LLWU_Type::PE2
__IO uint8_t	LLWU_Type::PE3
__IO uint8_t	LLWU_Type::PE4
__IO uint8_t	LLWU_Type::ME
__IO uint8_t	LLWU_Type::F1
__IO uint8_t	LLWU_Type::F2
__I uint8_t	LLWU_Type::F3
__IO uint8_t	LLWU_Type::FILT1
__IO uint8_t	LLWU_Type::FILT2
__IO uint8_t	LLWU_Type::RST
__IO uint32_t	LPTMR_Type::CSR
__IO uint32_t	LPTMR_Type::PSR
__IO uint32_t	LPTMR_Type::CMR
__IO uint32_t	LPTMR_Type::CNR
__IO uint8_t	MCG_Type::C1
__IO uint8_t	MCG_Type::C2
__IO uint8_t	MCG_Type::C3
__IO uint8_t	MCG_Type::C4
__IO uint8_t	MCG_Type::C5
__IO uint8_t	MCG_Type::C6
__IO uint8_t	MCG_Type::S
uint8_t	MCG_Type::RESERVED_0 [1]
__IO uint8_t	MCG_Type::SC
uint8_t	MCG_Type::RESERVED_1 [1]
__IO uint8_t	MCG_Type::ATCVH
__IO uint8_t	MCG_Type::ATCVL
__IO uint8_t	MCG_Type::C7
__IO uint8_t	MCG_Type::C8
__I uint8_t	MCG_Type::C9
__I uint8_t	MCG_Type::C10
uint8_t	MCM_Type::RESERVED_0 [8]
__I uint16_t	MCM_Type::PLASC
__I uint16_t	MCM_Type::PLAMC
__IO uint32_t	MCM_Type::CR
__IO uint32_t	MCM_Type::ISR
__IO uint32_t	MCM_Type::ETBCC
__IO uint32_t	MCM_Type::ETBRL
__I uint32_t	MCM_Type::ETBCNT
uint8_t	MCM_Type::RESERVED_1 [16]
__IO uint32_t	MCM_Type::PID
__I uint8_t	NV_Type::BACKKEY3
__I uint8_t	NV_Type::BACKKEY2
__I uint8_t	NV_Type::BACKKEY1
__I uint8_t	NV_Type::BACKKEY0
__I uint8_t	NV_Type::BACKKEY7
__I uint8_t	NV_Type::BACKKEY6
__I uint8_t	NV_Type::BACKKEY5
__I uint8_t	NV_Type::BACKKEY4
__I uint8_t	NV_Type::FPROT3
__I uint8_t	NV_Type::FPROT2
__I uint8_t	NV_Type::FPROT1
__I uint8_t	NV_Type::FPROT0
__I uint8_t	NV_Type::FSEC
__I uint8_t	NV_Type::FOPT
__I uint8_t	NV_Type::FEPROT
__I uint8_t	NV_Type::FDPROT
__IO uint8_t	OSC_Type::CR
__IO uint32_t	PDB_Type::SC
__IO uint32_t	PDB_Type::MOD
__I uint32_t	PDB_Type::CNT
__IO uint32_t	PDB_Type::IDLY
__IO uint32_t   PDB_Type::C1
__IO uint32_t   PDB_Type::S
__IO uint32_t   PDB_Type::DLY [2]
uint8_t   PDB_Type::RESERVED_0 [24]
struct {
}	PDB_Type::CH [2]
__IO uint32_t   PDB_Type::INTC
__IO uint32_t   PDB_Type::INT
struct {
}	PDB_Type::DAC [2]
uint8_t	PDB_Type::RESERVED_1 [48]
__IO uint32_t	PDB_Type::POEN
__IO uint32_t	PDB_Type::PODLY [3]
__IO uint32_t	PIT_Type::MCR
uint8_t	PIT_Type::RESERVED_0 [252]
__IO uint32_t   PIT_Type::LDVAL
__I uint32_t   PIT_Type::CVAL
__IO uint32_t   PIT_Type::TCTRL
__IO uint32_t   PIT_Type::TFLG
struct {
}	PIT_Type::CHANNEL [4]
__IO uint8_t	PMC_Type::LVDSC1
__IO uint8_t	PMC_Type::LVDSC2
__IO uint8_t	PMC_Type::REGSC
__IO uint32_t	PORT_Type::PCR [32]
__O uint32_t	PORT_Type::GPCLR
__O uint32_t	PORT_Type::GPCHR
uint8_t	PORT_Type::RESERVED_0 [24]
__IO uint32_t	PORT_Type::ISFR
uint8_t	PORT_Type::RESERVED_1 [28]
__IO uint32_t	PORT_Type::DFER
__IO uint32_t	PORT_Type::DFCR
__IO uint32_t	PORT_Type::DFWR
__I uint8_t	RCM_Type::SRS0
__I uint8_t	RCM_Type::SRS1
uint8_t	RCM_Type::RESERVED_0 [2]
__IO uint8_t	RCM_Type::RPFC
__IO uint8_t	RCM_Type::RPFW
uint8_t	RCM_Type::RESERVED_1 [1]
__I uint8_t	RCM_Type::MR
__IO uint32_t	RFSYS_Type::REG [8]
__IO uint32_t	RFVBAT_Type::REG [8]
__IO uint32_t	RNG_Type::CR
__I uint32_t	RNG_Type::SR
__O uint32_t	RNG_Type::ER
__I uint32_t	RNG_Type::OR
__IO uint32_t	RTC_Type::TSR
__IO uint32_t	RTC_Type::TPR
__IO uint32_t	RTC_Type::TAR
__IO uint32_t	RTC_Type::TCR
__IO uint32_t	RTC_Type::CR
__IO uint32_t	RTC_Type::SR
__IO uint32_t	RTC_Type::LR
__IO uint32_t	RTC_Type::IER
uint8_t	RTC_Type::RESERVED_0 [2016]
__IO uint32_t	RTC_Type::WAR
__IO uint32_t	RTC_Type::RAR
__IO uint32_t	SDHC_Type::DSADDR
__IO uint32_t	SDHC_Type::BLKATTR
__IO uint32_t	SDHC_Type::CMDARG
__IO uint32_t	SDHC_Type::XFERTYP
__I uint32_t	SDHC_Type::CMDRSP [4]
__IO uint32_t	SDHC_Type::DATPORT
__I uint32_t	SDHC_Type::PRSSTAT
__IO uint32_t	SDHC_Type::PROCTL
__IO uint32_t	SDHC_Type::SYSCTL
__IO uint32_t	SDHC_Type::IRQSTAT
__IO uint32_t	SDHC_Type::IRQSTATEN
__IO uint32_t	SDHC_Type::IRQSIGEN
__I uint32_t	SDHC_Type::AC12ERR
__I uint32_t	SDHC_Type::HTCAPBLT
__IO uint32_t	SDHC_Type::WML
uint8_t	SDHC_Type::RESERVED_0 [8]
__O uint32_t	SDHC_Type::FEVT
__I uint32_t	SDHC_Type::ADMAES
__IO uint32_t	SDHC_Type::ADSADDR
uint8_t	SDHC_Type::RESERVED_1 [100]
__IO uint32_t	SDHC_Type::VENDOR
__IO uint32_t	SDHC_Type::MMCBOOT
uint8_t	SDHC_Type::RESERVED_2 [52]
__I uint32_t	SDHC_Type::HOSTVER
__IO uint32_t	SIM_Type::SOPT1
__IO uint32_t	SIM_Type::SOPT1CFG
uint8_t	SIM_Type::RESERVED_0 [4092]
__IO uint32_t	SIM_Type::SOPT2
uint8_t	SIM_Type::RESERVED_1 [4]
__IO uint32_t	SIM_Type::SOPT4
__IO uint32_t	SIM_Type::SOPT5
uint8_t	SIM_Type::RESERVED_2 [4]
__IO uint32_t	SIM_Type::SOPT7
uint8_t	SIM_Type::RESERVED_3 [8]
__I uint32_t	SIM_Type::SDID
__IO uint32_t	SIM_Type::SCGC1
__IO uint32_t	SIM_Type::SCGC2
__IO uint32_t	SIM_Type::SCGC3
__IO uint32_t	SIM_Type::SCGC4
__IO uint32_t	SIM_Type::SCGC5
__IO uint32_t	SIM_Type::SCGC6
__IO uint32_t	SIM_Type::SCGC7
__IO uint32_t	SIM_Type::CLKDIV1
__IO uint32_t	SIM_Type::CLKDIV2
__IO uint32_t	SIM_Type::FCFG1
__I uint32_t	SIM_Type::FCFG2
__I uint32_t	SIM_Type::UIDH
__I uint32_t	SIM_Type::UIDMH
__I uint32_t	SIM_Type::UIDML
__I uint32_t	SIM_Type::UIDL
__IO uint8_t	SMC_Type::PMPROT
__IO uint8_t	SMC_Type::PMCTRL
__IO uint8_t	SMC_Type::VLLSCTRL
__I uint8_t	SMC_Type::PMSTAT
__IO uint32_t	SPI_Type::MCR
uint8_t	SPI_Type::RESERVED_0 [4]
__IO uint32_t	SPI_Type::TCR
__IO uint32_t   SPI_Type::CTAR [2]
__IO uint32_t   SPI_Type::CTAR_SLAVE [1]
union {
};
uint8_t	SPI_Type::RESERVED_1 [24]
__IO uint32_t	SPI_Type::SR
__IO uint32_t	SPI_Type::RSER
__IO uint32_t   SPI_Type::PUSHR
__IO uint32_t   SPI_Type::PUSHR_SLAVE
union {
};
__I uint32_t	SPI_Type::POPR
__I uint32_t	SPI_Type::TXFR0
__I uint32_t	SPI_Type::TXFR1
__I uint32_t	SPI_Type::TXFR2
__I uint32_t	SPI_Type::TXFR3
uint8_t	SPI_Type::RESERVED_2 [48]
__I uint32_t	SPI_Type::RXFR0
__I uint32_t	SPI_Type::RXFR1
__I uint32_t	SPI_Type::RXFR2
__I uint32_t	SPI_Type::RXFR3
__IO uint32_t	SYSMPU_Type::CESR
uint8_t	SYSMPU_Type::RESERVED_0 [12]
__I uint32_t   SYSMPU_Type::EAR
__I uint32_t   SYSMPU_Type::EDR
struct {
}	SYSMPU_Type::SP [5]
uint8_t	SYSMPU_Type::RESERVED_1 [968]
__IO uint32_t	SYSMPU_Type::WORD [12][4]
uint8_t	SYSMPU_Type::RESERVED_2 [832]
__IO uint32_t	SYSMPU_Type::RGDAAC [12]
__IO uint32_t	TSI_Type::GENCS
__IO uint32_t	TSI_Type::SCANC
__IO uint32_t	TSI_Type::PEN
__I uint32_t	TSI_Type::WUCNTR
uint8_t	TSI_Type::RESERVED_0 [240]
__I uint32_t	TSI_Type::CNTR1
__I uint32_t	TSI_Type::CNTR3
__I uint32_t	TSI_Type::CNTR5
__I uint32_t	TSI_Type::CNTR7
__I uint32_t	TSI_Type::CNTR9
__I uint32_t	TSI_Type::CNTR11
__I uint32_t	TSI_Type::CNTR13
__I uint32_t	TSI_Type::CNTR15
__IO uint32_t	TSI_Type::THRESHOLD
__IO uint8_t	UART_Type::BDH
__IO uint8_t	UART_Type::BDL
__IO uint8_t	UART_Type::C1
__IO uint8_t	UART_Type::C2
__I uint8_t	UART_Type::S1
__IO uint8_t	UART_Type::S2
__IO uint8_t	UART_Type::C3
__IO uint8_t	UART_Type::D
__IO uint8_t	UART_Type::MA1
__IO uint8_t	UART_Type::MA2
__IO uint8_t	UART_Type::C4
__IO uint8_t	UART_Type::C5
__I uint8_t	UART_Type::ED
__IO uint8_t	UART_Type::MODEM
__IO uint8_t	UART_Type::IR
uint8_t	UART_Type::RESERVED_0 [1]
__IO uint8_t	UART_Type::PFIFO
__IO uint8_t	UART_Type::CFIFO
__IO uint8_t	UART_Type::SFIFO
__IO uint8_t	UART_Type::TWFIFO
__I uint8_t	UART_Type::TCFIFO
__IO uint8_t	UART_Type::RWFIFO
__I uint8_t	UART_Type::RCFIFO
uint8_t	UART_Type::RESERVED_1 [1]
__IO uint8_t	UART_Type::C7816
__IO uint8_t	UART_Type::IE7816
__IO uint8_t	UART_Type::IS7816
__IO uint8_t   UART_Type::WP7816T0
__IO uint8_t   UART_Type::WP7816T1
union {
};
__IO uint8_t	UART_Type::WN7816
__IO uint8_t	UART_Type::WF7816
__IO uint8_t	UART_Type::ET7816
__IO uint8_t	UART_Type::TL7816
uint8_t	UART_Type::RESERVED_2 [1]
__IO uint8_t	UART_Type::C6
__IO uint8_t	UART_Type::PCTH
__IO uint8_t	UART_Type::PCTL
__IO uint8_t	UART_Type::B1T
__IO uint8_t	UART_Type::SDTH
__IO uint8_t	UART_Type::SDTL
__IO uint8_t	UART_Type::PRE
__IO uint8_t	UART_Type::TPL
__IO uint8_t	UART_Type::IE
__IO uint8_t	UART_Type::WB
__IO uint8_t	UART_Type::S3
__IO uint8_t	UART_Type::S4
__I uint8_t	UART_Type::RPL
__I uint8_t	UART_Type::RPREL
__IO uint8_t	UART_Type::CPW
__IO uint8_t	UART_Type::RIDT
__IO uint8_t	UART_Type::TIDT
__I uint8_t	USB_Type::PERID
uint8_t	USB_Type::RESERVED_0 [3]
__I uint8_t	USB_Type::IDCOMP
uint8_t	USB_Type::RESERVED_1 [3]
__I uint8_t	USB_Type::REV
uint8_t	USB_Type::RESERVED_2 [3]
__I uint8_t	USB_Type::ADDINFO
uint8_t	USB_Type::RESERVED_3 [3]
__IO uint8_t	USB_Type::OTGISTAT
uint8_t	USB_Type::RESERVED_4 [3]
__IO uint8_t	USB_Type::OTGICR
uint8_t	USB_Type::RESERVED_5 [3]
__IO uint8_t	USB_Type::OTGSTAT
uint8_t	USB_Type::RESERVED_6 [3]
__IO uint8_t	USB_Type::OTGCTL
uint8_t	USB_Type::RESERVED_7 [99]
__IO uint8_t	USB_Type::ISTAT
uint8_t	USB_Type::RESERVED_8 [3]
__IO uint8_t	USB_Type::INTEN
uint8_t	USB_Type::RESERVED_9 [3]
__IO uint8_t	USB_Type::ERRSTAT
uint8_t	USB_Type::RESERVED_10 [3]
__IO uint8_t	USB_Type::ERREN
uint8_t	USB_Type::RESERVED_11 [3]
__I uint8_t	USB_Type::STAT
uint8_t	USB_Type::RESERVED_12 [3]
__IO uint8_t	USB_Type::CTL
uint8_t	USB_Type::RESERVED_13 [3]
__IO uint8_t	USB_Type::ADDR
uint8_t	USB_Type::RESERVED_14 [3]
__IO uint8_t	USB_Type::BDTPAGE1
uint8_t	USB_Type::RESERVED_15 [3]
__IO uint8_t	USB_Type::FRMNUML
uint8_t	USB_Type::RESERVED_16 [3]
__IO uint8_t	USB_Type::FRMNUMH
uint8_t	USB_Type::RESERVED_17 [3]
__IO uint8_t	USB_Type::TOKEN
uint8_t	USB_Type::RESERVED_18 [3]
__IO uint8_t	USB_Type::SOFTHLD
uint8_t	USB_Type::RESERVED_19 [3]
__IO uint8_t	USB_Type::BDTPAGE2
uint8_t	USB_Type::RESERVED_20 [3]
__IO uint8_t	USB_Type::BDTPAGE3
uint8_t	USB_Type::RESERVED_21 [11]
__IO uint8_t   USB_Type::ENDPT
uint8_t   USB_Type::RESERVED_0 [3]
struct {
}	USB_Type::ENDPOINT [16]
__IO uint8_t	USB_Type::USBCTRL
uint8_t	USB_Type::RESERVED_22 [3]
__I uint8_t	USB_Type::OBSERVE
uint8_t	USB_Type::RESERVED_23 [3]
__IO uint8_t	USB_Type::CONTROL
uint8_t	USB_Type::RESERVED_24 [3]
__IO uint8_t	USB_Type::USBTRC0
uint8_t	USB_Type::RESERVED_25 [7]
__IO uint8_t	USB_Type::USBFRMADJUST
__IO uint32_t	USBDCD_Type::CONTROL
__IO uint32_t	USBDCD_Type::CLOCK
__I uint32_t	USBDCD_Type::STATUS
uint8_t	USBDCD_Type::RESERVED_0 [4]
__IO uint32_t	USBDCD_Type::TIMER0
__IO uint32_t	USBDCD_Type::TIMER1
__IO uint32_t	USBDCD_Type::TIMER2
__IO uint8_t	VREF_Type::TRM
__IO uint8_t	VREF_Type::SC
__IO uint16_t	WDOG_Type::STCTRLH
__IO uint16_t	WDOG_Type::STCTRLL
__IO uint16_t	WDOG_Type::TOVALH
__IO uint16_t	WDOG_Type::TOVALL
__IO uint16_t	WDOG_Type::WINH
__IO uint16_t	WDOG_Type::WINL
__IO uint16_t	WDOG_Type::REFRESH
__IO uint16_t	WDOG_Type::UNLOCK
__IO uint16_t	WDOG_Type::TMROUTH
__IO uint16_t	WDOG_Type::TMROUTL
__IO uint16_t	WDOG_Type::RSTCNT
__IO uint16_t	WDOG_Type::PRESC

Macro Definition Documentation

VREF [1/4]

#define VREF   ((VREF_Type *)VREF_BASE)

Peripheral VREF base pointer

VREF [2/4]

#define VREF   ((VREF_Type *)VREF_BASE)

Peripheral VREF base pointer

VREF [3/4]

#define VREF   ((VREF_Type *)VREF_BASE)

Peripheral VREF base pointer

VREF [4/4]

#define VREF   ((VREF_Type *)VREF_BASE)

Peripheral VREF base pointer

VREF_BASE [1/4]

#define VREF_BASE   (0x40074000u)

Peripheral VREF base address

VREF_BASE [2/4]

#define VREF_BASE   (0x40074000u)

Peripheral VREF base address

VREF_BASE [3/4]

#define VREF_BASE   (0x40074000u)

Peripheral VREF base address

VREF_BASE [4/4]

#define VREF_BASE   (0x40074000u)

Peripheral VREF base address

VREF_BASE_ADDRS [1/3]

#define VREF_BASE_ADDRS   { VREF_BASE }

Array initializer of VREF peripheral base addresses

VREF_BASE_ADDRS [2/3]

#define VREF_BASE_ADDRS   { VREF_BASE }

Array initializer of VREF peripheral base addresses

VREF_BASE_ADDRS [3/3]

#define VREF_BASE_ADDRS   { VREF_BASE }

Array initializer of VREF peripheral base addresses

VREF_BASE_PTRS [1/3]

#define VREF_BASE_PTRS   { VREF }

Array initializer of VREF peripheral base pointers

VREF_BASE_PTRS [2/3]

#define VREF_BASE_PTRS   { VREF }

Array initializer of VREF peripheral base pointers

VREF_BASE_PTRS [3/3]

#define VREF_BASE_PTRS   { VREF }

Array initializer of VREF peripheral base pointers

Variable Documentation

A1

__IO uint8_t I2C_Type::A1

I2C Address Register 1, offset: 0x0

A2

__IO uint8_t I2C_Type::A2

I2C Address Register 2, offset: 0x9

AC12ERR

__I uint32_t SDHC_Type::AC12ERR

Auto CMD12 Error Status Register, offset: 0x3C

ADDINFO

__I uint8_t USB_Type::ADDINFO

Peripheral Additional Info register, offset: 0xC

Peripheral Additional Info Register, offset: 0xC

ADDR

__IO uint8_t USB_Type::ADDR

Address register, offset: 0x98

Address Register, offset: 0x98

ADMAES

__I uint32_t SDHC_Type::ADMAES

ADMA Error Status register, offset: 0x54

ADMA Error Status Register, offset: 0x54

ADR_CA

__O uint32_t CAU_Type::ADR_CA

General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4

ADR_CAA

__O uint32_t CAU_Type::ADR_CAA

Accumulator register - Add to register command, offset: 0x8C4

ADR_CASR

__O uint32_t CAU_Type::ADR_CASR

Status register - Add Register command, offset: 0x8C0

ADSADDR

__IO uint32_t SDHC_Type::ADSADDR

ADMA System Addressregister, offset: 0x58

ADMA System Address Register, offset: 0x58

AESC_CA

__O uint32_t CAU_Type::AESC_CA

General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4

AESC_CAA

__O uint32_t CAU_Type::AESC_CAA

Accumulator register - AES Column Operation command, offset: 0xB04

AESC_CASR

__O uint32_t CAU_Type::AESC_CASR

Status register - AES Column Operation command, offset: 0xB00

AESIC_CA

__O uint32_t CAU_Type::AESIC_CA

General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4

AESIC_CAA

__O uint32_t CAU_Type::AESIC_CAA

Accumulator register - AES Inverse Column Operation command, offset: 0xB44

AESIC_CASR

__O uint32_t CAU_Type::AESIC_CASR

Status register - AES Inverse Column Operation command, offset: 0xB40

ATCOR

__IO uint32_t ENET_Type::ATCOR

Timer Correction Register, offset: 0x410

ATCR

__IO uint32_t ENET_Type::ATCR

Timer Control Register, offset: 0x400

Adjustable Timer Control Register, offset: 0x400

ATCVH

__IO uint8_t MCG_Type::ATCVH

MCG Auto Trim Compare Value High Register, offset: 0xA

ATCVL

__IO uint8_t MCG_Type::ATCVL

MCG Auto Trim Compare Value Low Register, offset: 0xB

ATINC

__IO uint32_t ENET_Type::ATINC

Time-Stamping Clock Period Register, offset: 0x414

ATOFF

__IO uint32_t ENET_Type::ATOFF

Timer Offset Register, offset: 0x408

ATPER

__IO uint32_t ENET_Type::ATPER

Timer Period Register, offset: 0x40C

ATSTMP

__I uint32_t ENET_Type::ATSTMP

Timestamp of Last Transmitted Frame, offset: 0x418

[] [1/2]

__IO uint16_t { ... } ::ATTR

TCD Transfer Attributes, array offset: 0x1006, array step: 0x20

ATTR [2/2]

__IO uint16_t DMA_Type::ATTR

TCD Transfer Attributes, array offset: 0x1006, array step: 0x20

ATVR

__IO uint32_t ENET_Type::ATVR

Timer Value Register, offset: 0x404

B1T

__IO uint8_t UART_Type::B1T

UART CEA709.1-B Beta1 Timer, offset: 0x24

BACKKEY0

__I uint8_t NV_Type::BACKKEY0

Backdoor Comparison Key 0., offset: 0x3

BACKKEY1

__I uint8_t NV_Type::BACKKEY1

Backdoor Comparison Key 1., offset: 0x2

BACKKEY2

__I uint8_t NV_Type::BACKKEY2

Backdoor Comparison Key 2., offset: 0x1

BACKKEY3

__I uint8_t NV_Type::BACKKEY3

Backdoor Comparison Key 3., offset: 0x0

BACKKEY4

__I uint8_t NV_Type::BACKKEY4

Backdoor Comparison Key 4., offset: 0x7

BACKKEY5

__I uint8_t NV_Type::BACKKEY5

Backdoor Comparison Key 5., offset: 0x6

BACKKEY6

__I uint8_t NV_Type::BACKKEY6

Backdoor Comparison Key 6., offset: 0x5

BACKKEY7

__I uint8_t NV_Type::BACKKEY7

Backdoor Comparison Key 7., offset: 0x4

BDH

__IO uint8_t UART_Type::BDH

UART Baud Rate Registers: High, offset: 0x0

UART Baud Rate Registers:High, offset: 0x0

BDL

__IO uint8_t UART_Type::BDL

UART Baud Rate Registers: Low, offset: 0x1

BDTPAGE1

__IO uint8_t USB_Type::BDTPAGE1

BDT Page Register 1, offset: 0x9C

BDT Page register 1, offset: 0x9C

BDTPAGE2

__IO uint8_t USB_Type::BDTPAGE2

BDT Page Register 2, offset: 0xB0

BDTPAGE3

__IO uint8_t USB_Type::BDTPAGE3

BDT Page Register 3, offset: 0xB4

[] [1/2]

__IO uint16_t { ... } ::BITER_ELINKNO

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20

BITER_ELINKNO [2/2]

__IO uint16_t DMA_Type::BITER_ELINKNO

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20

[] [1/2]

__IO uint16_t { ... } ::BITER_ELINKYES

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20

BITER_ELINKYES [2/2]

__IO uint16_t DMA_Type::BITER_ELINKYES

TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20

BLKATTR

__IO uint32_t SDHC_Type::BLKATTR

Block Attributes register, offset: 0x4

Block Attributes Register, offset: 0x4

C0

__IO uint8_t DAC_Type::C0

DAC Control Register, offset: 0x21

C1 [1/6]

__IO uint8_t DAC_Type::C1

DAC Control Register 1, offset: 0x22

C1 [2/6]

__IO uint8_t I2C_Type::C1

I2C Control Register 1, offset: 0x2

C1 [3/6]

__IO uint8_t MCG_Type::C1

MCG Control 1 Register, offset: 0x0

C1 [4/6]

__IO uint32_t PDB_Type::C1

Channel n Control Register 1, array offset: 0x10, array step: 0x28

Channel n Control register 1, array offset: 0x10, array step: 0x28

[] [5/6]

__IO uint32_t { ... } ::C1

Channel n Control Register 1, array offset: 0x10, array step: 0x28

C1 [6/6]

__IO uint8_t UART_Type::C1

UART Control Register 1, offset: 0x2

C10

__I uint8_t MCG_Type::C10

MCG Control 10 Register, offset: 0xF

C2 [1/4]

__IO uint8_t DAC_Type::C2

DAC Control Register 2, offset: 0x23

C2 [2/4]

__IO uint8_t I2C_Type::C2

I2C Control Register 2, offset: 0x5

C2 [3/4]

__IO uint8_t MCG_Type::C2

MCG Control 2 Register, offset: 0x1

C2 [4/4]

__IO uint8_t UART_Type::C2

UART Control Register 2, offset: 0x3

C3 [1/2]

__IO uint8_t MCG_Type::C3

MCG Control 3 Register, offset: 0x2

C3 [2/2]

__IO uint8_t UART_Type::C3

UART Control Register 3, offset: 0x6

C4 [1/2]

__IO uint8_t MCG_Type::C4

MCG Control 4 Register, offset: 0x3

C4 [2/2]

__IO uint8_t UART_Type::C4

UART Control Register 4, offset: 0xA

C5 [1/2]

__IO uint8_t MCG_Type::C5

MCG Control 5 Register, offset: 0x4

C5 [2/2]

__IO uint8_t UART_Type::C5

UART Control Register 5, offset: 0xB

C6 [1/2]

__IO uint8_t MCG_Type::C6

MCG Control 6 Register, offset: 0x5

C6 [2/2]

__IO uint8_t UART_Type::C6

UART CEA709.1-B Control Register 6, offset: 0x21

C7

__IO uint8_t MCG_Type::C7

MCG Control 7 Register, offset: 0xC

C7816

__IO uint8_t UART_Type::C7816

UART 7816 Control Register, offset: 0x18

C8

__IO uint8_t MCG_Type::C8

MCG Control 8 Register, offset: 0xD

C9

__IO uint8_t MCG_Type::C9

MCG Control 9 Register, offset: 0xE

CDNE

__O uint8_t DMA_Type::CDNE

Clear DONE Status Bit Register, offset: 0x1C

CEEI

__O uint8_t DMA_Type::CEEI

Clear Enable Error Interrupt Register, offset: 0x18

CERQ

__O uint8_t DMA_Type::CERQ

Clear Enable Request Register, offset: 0x1A

CERR

__O uint8_t DMA_Type::CERR

Clear Error Register, offset: 0x1E

CESR

__IO uint32_t SYSMPU_Type::CESR

Control/Error Status Register, offset: 0x0

CFG1

__IO uint32_t ADC_Type::CFG1

ADC Configuration Register 1, offset: 0x8

ADC configuration register 1, offset: 0x8

CFG2

__IO uint32_t ADC_Type::CFG2

ADC Configuration Register 2, offset: 0xC

Configuration register 2, offset: 0xC

CFIFO

__IO uint8_t UART_Type::CFIFO

UART FIFO Control Register, offset: 0x11

CGH1

__IO uint8_t CMT_Type::CGH1

CMT Carrier Generator High Data Register 1, offset: 0x0

CGH2

__IO uint8_t CMT_Type::CGH2

CMT Carrier Generator High Data Register 2, offset: 0x2

CGL1

__IO uint8_t CMT_Type::CGL1

CMT Carrier Generator Low Data Register 1, offset: 0x1

CGL2

__IO uint8_t CMT_Type::CGL2

CMT Carrier Generator Low Data Register 2, offset: 0x3

CHCFG

__IO uint8_t DMAMUX_Type::CHCFG

Channel Configuration register, array offset: 0x0, array step: 0x1

Channel Configuration Register, array offset: 0x0, array step: 0x1

CINT

__O uint8_t DMA_Type::CINT

Clear Interrupt Request Register, offset: 0x1F

[] [1/2]

__IO uint16_t { ... } ::CITER_ELINKNO

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20

CITER_ELINKNO [2/2]

__IO uint16_t DMA_Type::CITER_ELINKNO

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20

[] [1/2]

__IO uint16_t { ... } ::CITER_ELINKYES

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20

CITER_ELINKYES [2/2]

__IO uint16_t DMA_Type::CITER_ELINKYES

TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20

CLKDIV1

__IO uint32_t SIM_Type::CLKDIV1

System Clock Divider Register 1, offset: 0x1044

CLKDIV2

__IO uint32_t SIM_Type::CLKDIV2

System Clock Divider Register 2, offset: 0x1048

CLKPRESCALER

__IO uint8_t EWM_Type::CLKPRESCALER

Clock Prescaler Register, offset: 0x5

CLM0

__IO uint32_t ADC_Type::CLM0

ADC Minus-Side General Calibration Value Register, offset: 0x6C

ADC minus-side general calibration value register, offset: 0x6C

CLM1

__IO uint32_t ADC_Type::CLM1

ADC Minus-Side General Calibration Value Register, offset: 0x68

ADC minus-side general calibration value register, offset: 0x68

CLM2

__IO uint32_t ADC_Type::CLM2

ADC Minus-Side General Calibration Value Register, offset: 0x64

ADC minus-side general calibration value register, offset: 0x64

CLM3

__IO uint32_t ADC_Type::CLM3

ADC Minus-Side General Calibration Value Register, offset: 0x60

ADC minus-side general calibration value register, offset: 0x60

CLM4

__IO uint32_t ADC_Type::CLM4

ADC Minus-Side General Calibration Value Register, offset: 0x5C

ADC minus-side general calibration value register, offset: 0x5C

CLMD

__IO uint32_t ADC_Type::CLMD

ADC Minus-Side General Calibration Value Register, offset: 0x54

ADC minus-side general calibration value register, offset: 0x54

CLMS

__IO uint32_t ADC_Type::CLMS

ADC Minus-Side General Calibration Value Register, offset: 0x58

ADC minus-side general calibration value register, offset: 0x58

CLOCK

__IO uint32_t USBDCD_Type::CLOCK

Clock register, offset: 0x4

Clock Register, offset: 0x4

CLP0

__IO uint32_t ADC_Type::CLP0

ADC Plus-Side General Calibration Value Register, offset: 0x4C

ADC plus-side general calibration value register, offset: 0x4C

CLP1

__IO uint32_t ADC_Type::CLP1

ADC Plus-Side General Calibration Value Register, offset: 0x48

ADC plus-side general calibration value register, offset: 0x48

CLP2

__IO uint32_t ADC_Type::CLP2

ADC Plus-Side General Calibration Value Register, offset: 0x44

ADC plus-side general calibration value register, offset: 0x44

CLP3

__IO uint32_t ADC_Type::CLP3

ADC Plus-Side General Calibration Value Register, offset: 0x40

ADC plus-side general calibration value register, offset: 0x40

CLP4

__IO uint32_t ADC_Type::CLP4

ADC Plus-Side General Calibration Value Register, offset: 0x3C

ADC plus-side general calibration value register, offset: 0x3C

CLPD

__IO uint32_t ADC_Type::CLPD

ADC Plus-Side General Calibration Value Register, offset: 0x34

ADC plus-side general calibration value register, offset: 0x34

CLPS

__IO uint32_t ADC_Type::CLPS

ADC Plus-Side General Calibration Value Register, offset: 0x38

ADC plus-side general calibration value register, offset: 0x38

CMD1

__IO uint8_t CMT_Type::CMD1

CMT Modulator Data Register Mark High, offset: 0x6

CMD2

__IO uint8_t CMT_Type::CMD2

CMT Modulator Data Register Mark Low, offset: 0x7

CMD3

__IO uint8_t CMT_Type::CMD3

CMT Modulator Data Register Space High, offset: 0x8

CMD4

__IO uint8_t CMT_Type::CMD4

CMT Modulator Data Register Space Low, offset: 0x9

CMDARG

__IO uint32_t SDHC_Type::CMDARG

Command Argument register, offset: 0x8

Command Argument Register, offset: 0x8

CMDRSP

__I uint32_t SDHC_Type::CMDRSP

Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4

CMPH

__IO uint8_t EWM_Type::CMPH

Compare High Register, offset: 0x3

CMPL

__IO uint8_t EWM_Type::CMPL

Compare Low Register, offset: 0x2

CMR

__IO uint32_t LPTMR_Type::CMR

Low Power Timer Compare Register, offset: 0x8

CNR

__IO uint32_t LPTMR_Type::CNR

Low Power Timer Counter Register, offset: 0xC

[] [1/2]

__IO uint32_t { ... } ::CnSC

Channel (n) Status And Control, array offset: 0xC, array step: 0x8

CnSC [2/2]

__IO uint32_t FTM_Type::CnSC

Channel (n) Status And Control, array offset: 0xC, array step: 0x8

Channel (n) Status and Control, array offset: 0xC, array step: 0x8

CNT [1/2]

__IO uint32_t FTM_Type::CNT

Counter, offset: 0x4

CNT [2/2]

__I uint32_t PDB_Type::CNT

Counter Register, offset: 0x8

Counter register, offset: 0x8

CNTIN

__IO uint32_t FTM_Type::CNTIN

Counter Initial Value, offset: 0x4C

CNTR1

__I uint32_t TSI_Type::CNTR1

Counter Register, offset: 0x100

CNTR11

__I uint32_t TSI_Type::CNTR11

Counter Register, offset: 0x114

CNTR13

__I uint32_t TSI_Type::CNTR13

Counter Register, offset: 0x118

CNTR15

__I uint32_t TSI_Type::CNTR15

Counter Register, offset: 0x11C

CNTR3

__I uint32_t TSI_Type::CNTR3

Counter Register, offset: 0x104

CNTR5

__I uint32_t TSI_Type::CNTR5

Counter Register, offset: 0x108

CNTR7

__I uint32_t TSI_Type::CNTR7

Counter Register, offset: 0x10C

CNTR9

__I uint32_t TSI_Type::CNTR9

Counter Register, offset: 0x110

CnV [1/2]

__IO uint32_t FTM_Type::CnV

Channel (n) Value, array offset: 0x10, array step: 0x8

[] [2/2]

__IO uint32_t { ... } ::CnV

Channel (n) Value, array offset: 0x10, array step: 0x8

COMBINE

__IO uint32_t FTM_Type::COMBINE

Function For Linked Channels, offset: 0x64

Function for Linked Channels, offset: 0x64

CONF

__IO uint32_t FTM_Type::CONF

Configuration, offset: 0x84

CONTROL [1/2]

__IO uint8_t USB_Type::CONTROL

USB OTG Control register, offset: 0x108

USB OTG Control Register, offset: 0x108

CONTROL [2/2]

__IO uint32_t USBDCD_Type::CONTROL

Control register, offset: 0x0

Control Register, offset: 0x0

CPW

__IO uint8_t UART_Type::CPW

UART CEA709.1-B Collision Pulse Width, offset: 0x2F

CR [1/5]

__IO uint32_t DMA_Type::CR

Control Register, offset: 0x0

CR [2/5]

__IO uint32_t MCM_Type::CR

Control Register, offset: 0xC

CR [3/5]

__IO uint8_t OSC_Type::CR

OSC Control Register, offset: 0x0

CR [4/5]

__IO uint32_t RNG_Type::CR

RNGA Control Register, offset: 0x0

RNGB Control Register, offset: 0x8

CR [5/5]

__IO uint32_t RTC_Type::CR

RTC Control Register, offset: 0x10

CR0

__IO uint8_t CMP_Type::CR0

CMP Control Register 0, offset: 0x0

CR1

__IO uint8_t CMP_Type::CR1

CMP Control Register 1, offset: 0x1

[] [1/2]

__IO uint32_t { ... } ::CRC

CRC Data register, offset: 0x0

CRC [2/2]

__IO uint32_t CRC_Type::CRC

CRC Data register, offset: 0x0

CRC Data Register, offset: 0x0

[] [1/2]

__IO uint16_t { ... } ::CRCH

CRC_CRCH register., offset: 0x2

CRCH [2/2]

__IO uint16_t CRC_Type::CRCH

CRC_CRCH register., offset: 0x2

CRCHL [1/2]

__IO uint8_t CRC_Type::CRCHL

CRC_CRCHL register., offset: 0x2

[] [2/2]

__IO uint8_t { ... } ::CRCHL

CRC_CRCHL register., offset: 0x2

CRCHU [1/2]

__IO uint8_t CRC_Type::CRCHU

CRC_CRCHU register., offset: 0x3

[] [2/2]

__IO uint8_t { ... } ::CRCHU

CRC_CRCHU register., offset: 0x3

[] [1/2]

__IO uint16_t { ... } ::CRCL

CRC_CRCL register., offset: 0x0

CRCL [2/2]

__IO uint16_t CRC_Type::CRCL

CRC_CRCL register., offset: 0x0

[] [1/2]

__IO uint8_t { ... } ::CRCLL

CRC_CRCLL register., offset: 0x0

CRCLL [2/2]

__IO uint8_t CRC_Type::CRCLL

CRC_CRCLL register., offset: 0x0

[] [1/2]

__IO uint8_t { ... } ::CRCLU

CRC_CRCLU register., offset: 0x1

CRCLU [2/2]

__IO uint8_t CRC_Type::CRCLU

CRC_CRCLU register., offset: 0x1

CRCR

__I uint32_t CAN_Type::CRCR

CRC Register, offset: 0x44

[] [1/2]

__IO uint32_t { ... } ::CRS

Control Register, array offset: 0x10, array step: 0x100

CRS [2/2]

__IO uint32_t AXBS_Type::CRS

Control Register, array offset: 0x10, array step: 0x100

[] [1/2]

__IO uint32_t { ... } ::CS

Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10

CS [2/2]

__IO uint32_t CAN_Type::CS

Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10

[] [1/2]

__IO uint32_t { ... } ::CSAR

Chip Select Address Register, array offset: 0x0, array step: 0xC

CSAR [2/2]

__IO uint32_t FB_Type::CSAR

Chip Select Address Register, array offset: 0x0, array step: 0xC

Chip select address register, array offset: 0x0, array step: 0xC

CSCR [1/2]

__IO uint32_t FB_Type::CSCR

Chip Select Control Register, array offset: 0x8, array step: 0xC

Chip select control register, array offset: 0x8, array step: 0xC

[] [2/2]

__IO uint32_t { ... } ::CSCR

Chip Select Control Register, array offset: 0x8, array step: 0xC

[] [1/2]

__IO uint32_t { ... } ::CSMR

Chip Select Mask Register, array offset: 0x4, array step: 0xC

CSMR [2/2]

__IO uint32_t FB_Type::CSMR

Chip Select Mask Register, array offset: 0x4, array step: 0xC

Chip select mask register, array offset: 0x4, array step: 0xC

CSPMCR

__IO uint32_t FB_Type::CSPMCR

Chip Select port Multiplexing Control Register, offset: 0x60

Chip select port multiplexing control register, offset: 0x60

CSR [1/3]

__IO uint16_t DMA_Type::CSR

TCD Control and Status, array offset: 0x101C, array step: 0x20

[] [2/3]

__IO uint16_t { ... } ::CSR

TCD Control and Status, array offset: 0x101C, array step: 0x20

CSR [3/3]

__IO uint32_t LPTMR_Type::CSR

Low Power Timer Control Status Register, offset: 0x0

[] [1/2]

__IO uint32_t { ... } ::CTAR[2]

DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4

CTAR [2/2]

__IO uint32_t SPI_Type::CTAR[2]

DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4

Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4

[] [1/2]

__IO uint32_t { ... } ::CTAR_SLAVE[1]

Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4

CTAR_SLAVE [2/2]

__IO uint32_t SPI_Type::CTAR_SLAVE[1]

Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4

DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4

CTL

__IO uint8_t USB_Type::CTL

Control register, offset: 0x94

Control Register, offset: 0x94

[] [1/3]

__IO uint32_t { ... } ::CTRL

CRC Control register, offset: 0x8

CTRL [2/3]

__IO uint32_t CRC_Type::CTRL

CRC Control register, offset: 0x8

CRC Control Register, offset: 0x8

CTRL [3/3]

__IO uint8_t EWM_Type::CTRL

Control Register, offset: 0x0

CTRL1

__IO uint32_t CAN_Type::CTRL1

Control 1 register, offset: 0x4

Control 1 Register, offset: 0x4

CTRL2

__IO uint32_t CAN_Type::CTRL2

Control 2 register, offset: 0x34

Control 2 Register, offset: 0x34

[] [1/2]

__IO uint8_t { ... } ::CTRLHU

CRC_CTRLHU register., offset: 0xB

CTRLHU [2/2]

__IO uint8_t CRC_Type::CTRLHU

CRC_CTRLHU register., offset: 0xB

CV1

__IO uint32_t ADC_Type::CV1

Compare Value Registers, offset: 0x18

Compare value registers, offset: 0x18

CV2

__IO uint32_t ADC_Type::CV2

Compare Value Registers, offset: 0x1C

Compare value registers, offset: 0x1C

CVAL [1/2]

__I uint32_t PIT_Type::CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

[] [2/2]

__I uint32_t { ... } ::CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

D [1/2]

__IO uint8_t I2C_Type::D

I2C Data I/O register, offset: 0x4

D [2/2]

__IO uint8_t UART_Type::D

UART Data Register, offset: 0x7

DACCR

__IO uint8_t CMP_Type::DACCR

DAC Control Register, offset: 0x4

DADDR [1/2]

__IO uint32_t DMA_Type::DADDR

TCD Destination Address, array offset: 0x1010, array step: 0x20

[] [2/2]

__IO uint32_t { ... } ::DADDR

TCD Destination Address, array offset: 0x1010, array step: 0x20

[] [1/2]

__IO uint32_t { ... } ::DATA_L

Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8

DATA_L [2/2]

__IO uint32_t FMC_Type::DATA_L

Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8

Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8

[] [1/2]

__IO uint32_t { ... } ::DATA_U

Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8

DATA_U [2/2]

__IO uint32_t FMC_Type::DATA_U

Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8

Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8

DATH [1/2]

__IO uint8_t DAC_Type::DATH

DAC Data High Register, array offset: 0x1, array step: 0x2

[] [2/2]

__IO uint8_t { ... } ::DATH

DAC Data High Register, array offset: 0x1, array step: 0x2

DATL [1/2]

__IO uint8_t DAC_Type::DATL

DAC Data Low Register, array offset: 0x0, array step: 0x2

[] [2/2]

__IO uint8_t { ... } ::DATL

DAC Data Low Register, array offset: 0x0, array step: 0x2

DATPORT

__IO uint32_t SDHC_Type::DATPORT

Buffer Data Port register, offset: 0x20

Buffer Data Port Register, offset: 0x20

DCHPRI0

__IO uint8_t DMA_Type::DCHPRI0

Channel n Priority Register, offset: 0x103

DCHPRI1

__IO uint8_t DMA_Type::DCHPRI1

Channel n Priority Register, offset: 0x102

DCHPRI10

__IO uint8_t DMA_Type::DCHPRI10

Channel n Priority Register, offset: 0x109

DCHPRI11

__IO uint8_t DMA_Type::DCHPRI11

Channel n Priority Register, offset: 0x108

DCHPRI12

__IO uint8_t DMA_Type::DCHPRI12

Channel n Priority Register, offset: 0x10F

DCHPRI13

__IO uint8_t DMA_Type::DCHPRI13

Channel n Priority Register, offset: 0x10E

DCHPRI14

__IO uint8_t DMA_Type::DCHPRI14

Channel n Priority Register, offset: 0x10D

DCHPRI15

__IO uint8_t DMA_Type::DCHPRI15

Channel n Priority Register, offset: 0x10C

DCHPRI2

__IO uint8_t DMA_Type::DCHPRI2

Channel n Priority Register, offset: 0x101

DCHPRI3

__IO uint8_t DMA_Type::DCHPRI3

Channel n Priority Register, offset: 0x100

DCHPRI4

__IO uint8_t DMA_Type::DCHPRI4

Channel n Priority Register, offset: 0x107

DCHPRI5

__IO uint8_t DMA_Type::DCHPRI5

Channel n Priority Register, offset: 0x106

DCHPRI6

__IO uint8_t DMA_Type::DCHPRI6

Channel n Priority Register, offset: 0x105

DCHPRI7

__IO uint8_t DMA_Type::DCHPRI7

Channel n Priority Register, offset: 0x104

DCHPRI8

__IO uint8_t DMA_Type::DCHPRI8

Channel n Priority Register, offset: 0x10B

DCHPRI9

__IO uint8_t DMA_Type::DCHPRI9

Channel n Priority Register, offset: 0x10A

DEADTIME

__IO uint32_t FTM_Type::DEADTIME

Deadtime Insertion Control, offset: 0x68

DFCR

__IO uint32_t PORT_Type::DFCR

Digital Filter Clock Register, offset: 0xC4

DFER

__IO uint32_t PORT_Type::DFER

Digital Filter Enable Register, offset: 0xC0

DFWR

__IO uint32_t PORT_Type::DFWR

Digital Filter Width Register, offset: 0xC8

DIRECT

__O uint32_t CAU_Type::DIRECT

Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4

DLAST_SGA [1/2]

__IO uint32_t DMA_Type::DLAST_SGA

TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20

[] [2/2]

__IO uint32_t { ... } ::DLAST_SGA

TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20

[] [1/2]

__IO uint32_t { ... } ::DLY[2]

Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4

DLY [2/2]

__IO uint32_t PDB_Type::DLY[2]

Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4

Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4

DMA

__IO uint8_t CMT_Type::DMA

CMT Direct Memory Access Register, offset: 0xB

CMT Direct Memory Access, offset: 0xB

DOFF [1/2]

__IO uint16_t DMA_Type::DOFF

TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20

[] [2/2]

__IO uint16_t { ... } ::DOFF

TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20

DSADDR

__IO uint32_t SDHC_Type::DSADDR

DMA System Address register, offset: 0x0

DMA System Address Register, offset: 0x0

[] [1/2]

__I uint32_t { ... } ::EAR

Error Address Register, slave port n, array offset: 0x10, array step: 0x8

EAR [2/2]

__I uint32_t SYSMPU_Type::EAR

Error Address Register, slave port n, array offset: 0x10, array step: 0x8

ECR [1/2]

__IO uint32_t CAN_Type::ECR

Error Counter, offset: 0x1C

ECR [2/2]

__IO uint32_t ENET_Type::ECR

Ethernet Control Register, offset: 0x24

ED

__I uint8_t UART_Type::ED

UART Extended Data Register, offset: 0xC

EDR [1/2]

__I uint32_t SYSMPU_Type::EDR

Error Detail Register, slave port n, array offset: 0x14, array step: 0x8

[] [2/2]

__I uint32_t { ... } ::EDR

Error Detail Register, slave port n, array offset: 0x14, array step: 0x8

EEI

__IO uint32_t DMA_Type::EEI

Enable Error Interrupt Register, offset: 0x14

EIMR

__IO uint32_t ENET_Type::EIMR

Interrupt Mask Register, offset: 0x8

EIR

__IO uint32_t ENET_Type::EIR

Interrupt Event Register, offset: 0x4

ENDPT [1/2]

__IO uint8_t USB_Type::ENDPT

Endpoint Control register, array offset: 0xC0, array step: 0x4

Endpoint Control Register, array offset: 0xC0, array step: 0x4

[] [2/2]

__IO uint8_t { ... } ::ENDPT

Endpoint Control register, array offset: 0xC0, array step: 0x4

ER

__O uint32_t RNG_Type::ER

RNGA Entropy Register, offset: 0x8

ERQ

__IO uint32_t DMA_Type::ERQ

Enable Request Register, offset: 0xC

ERR

__IO uint32_t DMA_Type::ERR

Error Register, offset: 0x2C

ERREN

__IO uint8_t USB_Type::ERREN

Error Interrupt Enable register, offset: 0x8C

Error Interrupt Enable Register, offset: 0x8C

ERRSTAT

__IO uint8_t USB_Type::ERRSTAT

Error Interrupt Status register, offset: 0x88

Error Interrupt Status Register, offset: 0x88

ES

__I uint32_t DMA_Type::ES

Error Status Register, offset: 0x4

ESR1

__IO uint32_t CAN_Type::ESR1

Error and Status 1 register, offset: 0x20

Error and Status 1 Register, offset: 0x20

ESR2

__I uint32_t CAN_Type::ESR2

Error and Status 2 register, offset: 0x38

Error and Status 2 Register, offset: 0x38

ET7816

__IO uint8_t UART_Type::ET7816

UART 7816 Error Threshold Register, offset: 0x1E

ETBCC

__IO uint32_t MCM_Type::ETBCC

ETB Counter Control register, offset: 0x14

ETB counter control register, offset: 0x14

ETBCNT

__I uint32_t MCM_Type::ETBCNT

ETB Counter Value register, offset: 0x1C

ETB counter value register, offset: 0x1C

ETBRL

__IO uint32_t MCM_Type::ETBRL

ETB Reload register, offset: 0x18

ETB reload register, offset: 0x18

EXTTRIG

__IO uint32_t FTM_Type::EXTTRIG

FTM External Trigger, offset: 0x6C

F

__IO uint8_t I2C_Type::F

I2C Frequency Divider register, offset: 0x1

F1

__IO uint8_t LLWU_Type::F1

LLWU Flag 1 register, offset: 0x5

LLWU Flag 1 Register, offset: 0x5

F2

__IO uint8_t LLWU_Type::F2

LLWU Flag 2 register, offset: 0x6

LLWU Flag 2 Register, offset: 0x6

F3

__I uint8_t LLWU_Type::F3

LLWU Flag 3 register, offset: 0x7

FCCOB0

__IO uint8_t FTFL_Type::FCCOB0

Flash Common Command Object Registers, offset: 0x7

FCCOB1

__IO uint8_t FTFL_Type::FCCOB1

Flash Common Command Object Registers, offset: 0x6

FCCOB2

__IO uint8_t FTFL_Type::FCCOB2

Flash Common Command Object Registers, offset: 0x5

FCCOB3

__IO uint8_t FTFL_Type::FCCOB3

Flash Common Command Object Registers, offset: 0x4

FCCOB4

__IO uint8_t FTFL_Type::FCCOB4

Flash Common Command Object Registers, offset: 0xB

FCCOB5

__IO uint8_t FTFL_Type::FCCOB5

Flash Common Command Object Registers, offset: 0xA

FCCOB6

__IO uint8_t FTFL_Type::FCCOB6

Flash Common Command Object Registers, offset: 0x9

FCCOB7

__IO uint8_t FTFL_Type::FCCOB7

Flash Common Command Object Registers, offset: 0x8

FCCOB8

__IO uint8_t FTFL_Type::FCCOB8

Flash Common Command Object Registers, offset: 0xF

FCCOB9

__IO uint8_t FTFL_Type::FCCOB9

Flash Common Command Object Registers, offset: 0xE

FCCOBA

__IO uint8_t FTFL_Type::FCCOBA

Flash Common Command Object Registers, offset: 0xD

FCCOBB

__IO uint8_t FTFL_Type::FCCOBB

Flash Common Command Object Registers, offset: 0xC

FCFG1

__IO uint32_t SIM_Type::FCFG1

Flash Configuration Register 1, offset: 0x104C

FCFG2

__I uint32_t SIM_Type::FCFG2

Flash Configuration Register 2, offset: 0x1050

FCNFG

__IO uint8_t FTFL_Type::FCNFG

Flash Configuration Register, offset: 0x1

FDPROT [1/2]

__IO uint8_t FTFL_Type::FDPROT

Data Flash Protection Register, offset: 0x17

FDPROT [2/2]

__I uint8_t NV_Type::FDPROT

Non-volatile D-Flash Protection Register, offset: 0xF

FEPROT [1/2]

__IO uint8_t FTFL_Type::FEPROT

EEPROM Protection Register, offset: 0x16

FEPROT [2/2]

__I uint8_t NV_Type::FEPROT

Non-volatile EERAM Protection Register, offset: 0xE

FEVT

__O uint32_t SDHC_Type::FEVT

Force Event register, offset: 0x50

Force Event Register, offset: 0x50

FILT1

__IO uint8_t LLWU_Type::FILT1

LLWU Pin Filter 1 register, offset: 0x8

LLWU Pin Filter 1 register, offset: 0xE

FILT2

__IO uint8_t LLWU_Type::FILT2

LLWU Pin Filter 2 register, offset: 0x9

LLWU Pin Filter 2 register, offset: 0xF

FILTER

__IO uint32_t FTM_Type::FILTER

Input Capture Filter Control, offset: 0x78

FLT

__IO uint8_t I2C_Type::FLT

I2C Programmable Input Glitch Filter register, offset: 0x6

I2C Programmable Input Glitch Filter Register, offset: 0x6

FLTCTRL

__IO uint32_t FTM_Type::FLTCTRL

Fault Control, offset: 0x7C

FLTPOL

__IO uint32_t FTM_Type::FLTPOL

FTM Fault Input Polarity, offset: 0x88

FMS

__IO uint32_t FTM_Type::FMS

Fault Mode Status, offset: 0x74

FOPT [1/2]

__I uint8_t FTFL_Type::FOPT

Flash Option Register, offset: 0x3

FOPT [2/2]

__I uint8_t NV_Type::FOPT

Non-volatile Flash Option Register, offset: 0xD

FPR

__IO uint8_t CMP_Type::FPR

CMP Filter Period Register, offset: 0x2

FPROT0 [1/2]

__IO uint8_t FTFL_Type::FPROT0

Program Flash Protection Registers, offset: 0x13

FPROT0 [2/2]

__I uint8_t NV_Type::FPROT0

Non-volatile P-Flash Protection 0 - High Register, offset: 0xB

FPROT1 [1/2]

__IO uint8_t FTFL_Type::FPROT1

Program Flash Protection Registers, offset: 0x12

FPROT1 [2/2]

__I uint8_t NV_Type::FPROT1

Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA

FPROT2 [1/2]

__IO uint8_t FTFL_Type::FPROT2

Program Flash Protection Registers, offset: 0x11

FPROT2 [2/2]

__I uint8_t NV_Type::FPROT2

Non-volatile P-Flash Protection 1 - High Register, offset: 0x9

FPROT3 [1/2]

__IO uint8_t FTFL_Type::FPROT3

Program Flash Protection Registers, offset: 0x10

FPROT3 [2/2]

__I uint8_t NV_Type::FPROT3

Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8

FRMNUMH

__IO uint8_t USB_Type::FRMNUMH

Frame Number Register High, offset: 0xA4

Frame Number register High, offset: 0xA4

FRMNUML

__IO uint8_t USB_Type::FRMNUML

Frame Number Register Low, offset: 0xA0

Frame Number register Low, offset: 0xA0

FSEC [1/2]

__I uint8_t FTFL_Type::FSEC

Flash Security Register, offset: 0x2

FSEC [2/2]

__I uint8_t NV_Type::FSEC

Non-volatile Flash Security Register, offset: 0xC

FSTAT

__IO uint8_t FTFL_Type::FSTAT

Flash Status Register, offset: 0x0

FTRL

__IO uint32_t ENET_Type::FTRL

Frame Truncation Length, offset: 0x1B0

GALR

__IO uint32_t ENET_Type::GALR

Descriptor Group Lower Address Register, offset: 0x124

GAUR

__IO uint32_t ENET_Type::GAUR

Descriptor Group Upper Address Register, offset: 0x120

GENCS

__IO uint32_t TSI_Type::GENCS

General Control and Status register, offset: 0x0

General Control and Status Register, offset: 0x0

TSI General Control and Status Register, offset: 0x0

GPCHR

__O uint32_t PORT_Type::GPCHR

Global Pin Control High Register, offset: 0x84

GPCLR

__O uint32_t PORT_Type::GPCLR

Global Pin Control Low Register, offset: 0x80

[] [1/2]

__IO uint32_t { ... } ::GPOLY

CRC Polynomial register, offset: 0x4

GPOLY [2/2]

__IO uint32_t CRC_Type::GPOLY

CRC Polynomial register, offset: 0x4

CRC Polynomial Register, offset: 0x4

GPOLYH [1/2]

__IO uint16_t CRC_Type::GPOLYH

CRC_GPOLYH register., offset: 0x6

[] [2/2]

__IO uint16_t { ... } ::GPOLYH

CRC_GPOLYH register., offset: 0x6

[] [1/2]

__IO uint8_t { ... } ::GPOLYHL

CRC_GPOLYHL register., offset: 0x6

GPOLYHL [2/2]

__IO uint8_t CRC_Type::GPOLYHL

CRC_GPOLYHL register., offset: 0x6

GPOLYHU [1/2]

__IO uint8_t CRC_Type::GPOLYHU

CRC_GPOLYHU register., offset: 0x7

[] [2/2]

__IO uint8_t { ... } ::GPOLYHU

CRC_GPOLYHU register., offset: 0x7

[] [1/2]

__IO uint16_t { ... } ::GPOLYL

CRC_GPOLYL register., offset: 0x4

GPOLYL [2/2]

__IO uint16_t CRC_Type::GPOLYL

CRC_GPOLYL register., offset: 0x4

[] [1/2]

__IO uint8_t { ... } ::GPOLYLL

CRC_GPOLYLL register., offset: 0x4

GPOLYLL [2/2]

__IO uint8_t CRC_Type::GPOLYLL

CRC_GPOLYLL register., offset: 0x4

[] [1/2]

__IO uint8_t { ... } ::GPOLYLU

CRC_GPOLYLU register., offset: 0x5

GPOLYLU [2/2]

__IO uint8_t CRC_Type::GPOLYLU

CRC_GPOLYLU register., offset: 0x5

HOSTVER

__I uint32_t SDHC_Type::HOSTVER

Host Controller Version, offset: 0xFC

HRS

__I uint32_t DMA_Type::HRS

Hardware Request Status Register, offset: 0x34

HTCAPBLT

__I uint32_t SDHC_Type::HTCAPBLT

Host Controller Capabilities, offset: 0x40

IALR

__IO uint32_t ENET_Type::IALR

Descriptor Individual Lower Address Register, offset: 0x11C

IAUR

__IO uint32_t ENET_Type::IAUR

Descriptor Individual Upper Address Register, offset: 0x118

ID [1/2]

__IO uint32_t CAN_Type::ID

Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10

[] [2/2]

__IO uint32_t { ... } ::ID

Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10

IDCOMP

__I uint8_t USB_Type::IDCOMP

Peripheral ID Complement register, offset: 0x4

Peripheral ID Complement Register, offset: 0x4

IDLY

__IO uint32_t PDB_Type::IDLY

Interrupt Delay Register, offset: 0xC

Interrupt Delay register, offset: 0xC

IE

__IO uint8_t UART_Type::IE

UART CEA709.1-B Interrupt Enable Register, offset: 0x29

IE7816

__IO uint8_t UART_Type::IE7816

UART 7816 Interrupt Enable Register, offset: 0x19

IEEE_R_ALIGN

__I uint32_t ENET_Type::IEEE_R_ALIGN

Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4

Frames Received with Alignment Error Statistic Register, offset: 0x2D4

IEEE_R_CRC

__I uint32_t ENET_Type::IEEE_R_CRC

Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0

Frames Received with CRC Error Statistic Register, offset: 0x2D0

IEEE_R_DROP

__I uint32_t ENET_Type::IEEE_R_DROP

Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8

Frames not Counted Correctly Statistic Register, offset: 0x2C8

IEEE_R_FDXFC

__I uint32_t ENET_Type::IEEE_R_FDXFC

Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC

Flow Control Pause Frames Received Statistic Register, offset: 0x2DC

IEEE_R_FRAME_OK

__I uint32_t ENET_Type::IEEE_R_FRAME_OK

Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC

Frames Received OK Statistic Register, offset: 0x2CC

IEEE_R_MACERR

__I uint32_t ENET_Type::IEEE_R_MACERR

Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8

Receive FIFO Overflow Count Statistic Register, offset: 0x2D8

IEEE_R_OCTETS_OK

__I uint32_t ENET_Type::IEEE_R_OCTETS_OK

Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0

Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0

IEEE_T_1COL

__I uint32_t ENET_Type::IEEE_T_1COL

Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250

Frames Transmitted with Single Collision Statistic Register, offset: 0x250

IEEE_T_CSERR

__I uint32_t ENET_Type::IEEE_T_CSERR

Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268

Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268

IEEE_T_DEF

__I uint32_t ENET_Type::IEEE_T_DEF

Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258

Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258

IEEE_T_DROP

uint32_t ENET_Type::IEEE_T_DROP

Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248

IEEE_T_DROP Reserved Statistic Register, offset: 0x248

Reserved Statistic Register, offset: 0x248

IEEE_T_EXCOL

__I uint32_t ENET_Type::IEEE_T_EXCOL

Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260

Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260

IEEE_T_FDXFC

__I uint32_t ENET_Type::IEEE_T_FDXFC

Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270

Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270

IEEE_T_FRAME_OK

__I uint32_t ENET_Type::IEEE_T_FRAME_OK

Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C

Frames Transmitted OK Statistic Register, offset: 0x24C

IEEE_T_LCOL

__I uint32_t ENET_Type::IEEE_T_LCOL

Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C

Frames Transmitted with Late Collision Statistic Register, offset: 0x25C

IEEE_T_MACERR

__I uint32_t ENET_Type::IEEE_T_MACERR

Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264

Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264

IEEE_T_MCOL

__I uint32_t ENET_Type::IEEE_T_MCOL

Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254

Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254

IEEE_T_OCTETS_OK

__I uint32_t ENET_Type::IEEE_T_OCTETS_OK

Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274

Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274

IEEE_T_SQE

__I uint32_t ENET_Type::IEEE_T_SQE

Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C

, offset: 0x26C

Reserved Statistic Register, offset: 0x26C

IER

__IO uint32_t RTC_Type::IER

RTC Interrupt Enable Register, offset: 0x1C

IFLAG1

__IO uint32_t CAN_Type::IFLAG1

Interrupt Flags 1 register, offset: 0x30

Interrupt Flags 1 Register, offset: 0x30

IMASK1

__IO uint32_t CAN_Type::IMASK1

Interrupt Masks 1 register, offset: 0x28

Interrupt Masks 1 Register, offset: 0x28

INT [1/3]

__IO uint32_t DMA_Type::INT

Interrupt Request Register, offset: 0x24

[] [2/3]

__IO uint32_t { ... } ::INT

DAC Interval n Register, array offset: 0x154, array step: 0x8

INT [3/3]

__IO uint32_t PDB_Type::INT

DAC Interval n Register, array offset: 0x154, array step: 0x8

DAC Interval n register, array offset: 0x154, array step: 0x8

[] [1/2]

__IO uint32_t { ... } ::INTC

DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8

INTC [2/2]

__IO uint32_t PDB_Type::INTC

DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8

DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8

INTEN

__IO uint8_t USB_Type::INTEN

Interrupt Enable register, offset: 0x84

Interrupt Enable Register, offset: 0x84

INVCTRL

__IO uint32_t FTM_Type::INVCTRL

FTM Inverting Control, offset: 0x90

IR

__IO uint8_t UART_Type::IR

UART Infrared Register, offset: 0xE

IRQSIGEN

__IO uint32_t SDHC_Type::IRQSIGEN

Interrupt Signal Enable register, offset: 0x38

Interrupt Signal Enable Register, offset: 0x38

IRQSTAT

__IO uint32_t SDHC_Type::IRQSTAT

Interrupt Status register, offset: 0x30

Interrupt Status Register, offset: 0x30

IRQSTATEN

__IO uint32_t SDHC_Type::IRQSTATEN

Interrupt Status Enable register, offset: 0x34

Interrupt Status Enable Register, offset: 0x34

IS7816

__IO uint8_t UART_Type::IS7816

UART 7816 Interrupt Status Register, offset: 0x1A

ISFR

__IO uint32_t PORT_Type::ISFR

Interrupt Status Flag Register, offset: 0xA0

ISR

__IO uint32_t MCM_Type::ISR

Interrupt Status Register, offset: 0x10

Interrupt status register, offset: 0x10

ISTAT

__IO uint8_t USB_Type::ISTAT

Interrupt Status register, offset: 0x80

Interrupt Status Register, offset: 0x80

LDR_CA

__O uint32_t CAU_Type::LDR_CA

General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4

LDR_CAA

__O uint32_t CAU_Type::LDR_CAA

Accumulator register - Load Register command, offset: 0x844

LDR_CASR

__O uint32_t CAU_Type::LDR_CASR

Status register - Load Register command, offset: 0x840

LDVAL [1/2]

__IO uint32_t PIT_Type::LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

[] [2/2]

__IO uint32_t { ... } ::LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

LR

__IO uint32_t RTC_Type::LR

RTC Lock Register, offset: 0x18

LVDSC1

__IO uint8_t PMC_Type::LVDSC1

Low Voltage Detect Status And Control 1 register, offset: 0x0

Low Voltage Detect Status and Control 1 Register, offset: 0x0

LVDSC2

__IO uint8_t PMC_Type::LVDSC2

Low Voltage Detect Status And Control 2 register, offset: 0x1

Low Voltage Detect Status and Control 2 Register, offset: 0x1

MA1

__IO uint8_t UART_Type::MA1

UART Match Address Registers 1, offset: 0x8

MA2

__IO uint8_t UART_Type::MA2

UART Match Address Registers 2, offset: 0x9

MCR [1/4]

__IO uint32_t CAN_Type::MCR

Module Configuration Register, offset: 0x0

MCR [2/4]

__IO uint32_t I2S_Type::MCR

SAI MCLK Control Register, offset: 0x100

MCR [3/4]

__IO uint32_t PIT_Type::MCR

PIT Module Control Register, offset: 0x0

MCR [4/4]

__IO uint32_t SPI_Type::MCR

Module Configuration Register, offset: 0x0

DSPI Module Configuration Register, offset: 0x0

MDR

__IO uint32_t I2S_Type::MDR

SAI MCLK Divide Register, offset: 0x104

ME

__IO uint8_t LLWU_Type::ME

LLWU Module Enable register, offset: 0x4

LLWU Module Enable Register, offset: 0x4

LLWU Module Enable register, offset: 0x8

MG

__IO uint32_t ADC_Type::MG

ADC Minus-Side Gain Register, offset: 0x30

ADC minus-side gain register, offset: 0x30

MGPCR0

__IO uint32_t AXBS_Type::MGPCR0

Master General Purpose Control Register, offset: 0x800

MGPCR1

__IO uint32_t AXBS_Type::MGPCR1

Master General Purpose Control Register, offset: 0x900

MGPCR2

__IO uint32_t AXBS_Type::MGPCR2

Master General Purpose Control Register, offset: 0xA00

MGPCR3

__IO uint32_t AXBS_Type::MGPCR3

Master General Purpose Control Register, offset: 0xB00

MGPCR4

__IO uint32_t AXBS_Type::MGPCR4

Master General Purpose Control Register, offset: 0xC00

MGPCR5

__IO uint32_t AXBS_Type::MGPCR5

Master General Purpose Control Register, offset: 0xD00

MIBC

__IO uint32_t ENET_Type::MIBC

MIB Control Register, offset: 0x64

MMCBOOT

__IO uint32_t SDHC_Type::MMCBOOT

MMC Boot register, offset: 0xC4

MMC Boot Register, offset: 0xC4

MMFR

__IO uint32_t ENET_Type::MMFR

MII Management Frame Register, offset: 0x40

MOD [1/2]

__IO uint32_t FTM_Type::MOD

Modulo, offset: 0x8

MOD [2/2]

__IO uint32_t PDB_Type::MOD

Modulus Register, offset: 0x4

Modulus register, offset: 0x4

MODE

__IO uint32_t FTM_Type::MODE

Features Mode Selection, offset: 0x54

MODEM

__IO uint8_t UART_Type::MODEM

UART Modem Register, offset: 0xD

MPRA

__IO uint32_t AIPS_Type::MPRA

Master Privilege Register A, offset: 0x0

MR

__I uint8_t RCM_Type::MR

Mode Register, offset: 0x7

MRBR

__IO uint32_t ENET_Type::MRBR

Maximum Receive Buffer Size Register, offset: 0x188

MSC

__IO uint8_t CMT_Type::MSC

CMT Modulator Status and Control Register, offset: 0x5

MSCR

__IO uint32_t ENET_Type::MSCR

MII Speed Control Register, offset: 0x44

MUXCR

__IO uint8_t CMP_Type::MUXCR

MUX Control Register, offset: 0x5

NBYTES_MLNO [1/2]

__IO uint32_t DMA_Type::NBYTES_MLNO

TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20

TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20

[] [2/2]

__IO uint32_t { ... } ::NBYTES_MLNO

TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20

NBYTES_MLOFFNO [1/2]

__IO uint32_t DMA_Type::NBYTES_MLOFFNO

TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20

TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20

[] [2/2]

__IO uint32_t { ... } ::NBYTES_MLOFFNO

TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20

[] [1/2]

__IO uint32_t { ... } ::NBYTES_MLOFFYES

TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20

NBYTES_MLOFFYES [2/2]

__IO uint32_t DMA_Type::NBYTES_MLOFFYES

TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20

TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20

OBSERVE

__I uint8_t USB_Type::OBSERVE

USB OTG Observe register, offset: 0x104

USB OTG Observe Register, offset: 0x104

OC

__IO uint8_t CMT_Type::OC

CMT Output Control Register, offset: 0x4

OFS

__IO uint32_t ADC_Type::OFS

ADC Offset Correction Register, offset: 0x28

ADC offset correction register, offset: 0x28

OPD

__IO uint32_t ENET_Type::OPD

Opcode/Pause Duration Register, offset: 0xEC

OR

__I uint32_t RNG_Type::OR

RNGA Output Register, offset: 0xC

OTGCTL

__IO uint8_t USB_Type::OTGCTL

OTG Control register, offset: 0x1C

OTG Control Register, offset: 0x1C

OTGICR

__IO uint8_t USB_Type::OTGICR

OTG Interrupt Control Register, offset: 0x14

OTG Interrupt Control register, offset: 0x14

OTGISTAT

__IO uint8_t USB_Type::OTGISTAT

OTG Interrupt Status register, offset: 0x10

OTG Interrupt Status Register, offset: 0x10

OTGSTAT

__IO uint8_t USB_Type::OTGSTAT

OTG Status register, offset: 0x18

OTG Status Register, offset: 0x18

OUTINIT

__IO uint32_t FTM_Type::OUTINIT

Initial State For Channels Output, offset: 0x5C

Initial State for Channels Output, offset: 0x5C

OUTMASK

__IO uint32_t FTM_Type::OUTMASK

Output Mask, offset: 0x60

PACRA

__IO uint32_t AIPS_Type::PACRA

Peripheral Access Control Register, offset: 0x20

PACRB

__IO uint32_t AIPS_Type::PACRB

Peripheral Access Control Register, offset: 0x24

PACRC

__IO uint32_t AIPS_Type::PACRC

Peripheral Access Control Register, offset: 0x28

PACRD

__IO uint32_t AIPS_Type::PACRD

Peripheral Access Control Register, offset: 0x2C

PACRE

__IO uint32_t AIPS_Type::PACRE

Peripheral Access Control Register, offset: 0x40

PACRF

__IO uint32_t AIPS_Type::PACRF

Peripheral Access Control Register, offset: 0x44

PACRG

__IO uint32_t AIPS_Type::PACRG

Peripheral Access Control Register, offset: 0x48

PACRH

__IO uint32_t AIPS_Type::PACRH

Peripheral Access Control Register, offset: 0x4C

PACRI

__IO uint32_t AIPS_Type::PACRI

Peripheral Access Control Register, offset: 0x50

PACRJ

__IO uint32_t AIPS_Type::PACRJ

Peripheral Access Control Register, offset: 0x54

PACRK

__IO uint32_t AIPS_Type::PACRK

Peripheral Access Control Register, offset: 0x58

PACRL

__IO uint32_t AIPS_Type::PACRL

Peripheral Access Control Register, offset: 0x5C

PACRM

__IO uint32_t AIPS_Type::PACRM

Peripheral Access Control Register, offset: 0x60

PACRN

__IO uint32_t AIPS_Type::PACRN

Peripheral Access Control Register, offset: 0x64

PACRO

__IO uint32_t AIPS_Type::PACRO

Peripheral Access Control Register, offset: 0x68

PACRP

__IO uint32_t AIPS_Type::PACRP

Peripheral Access Control Register, offset: 0x6C

PALR

__IO uint32_t ENET_Type::PALR

Physical Address Lower Register, offset: 0xE4

PAUR

__IO uint32_t ENET_Type::PAUR

Physical Address Upper Register, offset: 0xE8

PCOR

__O uint32_t GPIO_Type::PCOR

Port Clear Output Register, offset: 0x8

PCR

__IO uint32_t PORT_Type::PCR

Pin Control Register n, array offset: 0x0, array step: 0x4

PCTH

__IO uint8_t UART_Type::PCTH

UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22

PCTL

__IO uint8_t UART_Type::PCTL

UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23

PDDR

__IO uint32_t GPIO_Type::PDDR

Port Data Direction Register, offset: 0x14

PDIR

__I uint32_t GPIO_Type::PDIR

Port Data Input Register, offset: 0x10

PDOR

__IO uint32_t GPIO_Type::PDOR

Port Data Output Register, offset: 0x0

PE1

__IO uint8_t LLWU_Type::PE1

LLWU Pin Enable 1 register, offset: 0x0

LLWU Pin Enable 1 Register, offset: 0x0

PE2

__IO uint8_t LLWU_Type::PE2

LLWU Pin Enable 2 register, offset: 0x1

LLWU Pin Enable 2 Register, offset: 0x1

PE3

__IO uint8_t LLWU_Type::PE3

LLWU Pin Enable 3 register, offset: 0x2

LLWU Pin Enable 3 Register, offset: 0x2

PE4

__IO uint8_t LLWU_Type::PE4

LLWU Pin Enable 4 register, offset: 0x3

LLWU Pin Enable 4 Register, offset: 0x3

PEN

__IO uint32_t TSI_Type::PEN

Pin Enable register, offset: 0x8

Pin enable register, offset: 0x8

PERID

__I uint8_t USB_Type::PERID

Peripheral ID register, offset: 0x0

Peripheral ID Register, offset: 0x0

PFAPR

__IO uint32_t FMC_Type::PFAPR

Flash Access Protection Register, offset: 0x0

PFB0CR

__IO uint32_t FMC_Type::PFB0CR

Flash Bank 0 Control Register, offset: 0x4

PFB1CR

__IO uint32_t FMC_Type::PFB1CR

Flash Bank 1 Control Register, offset: 0x8

PFIFO

__IO uint8_t UART_Type::PFIFO

UART FIFO Parameters, offset: 0x10

PG

__IO uint32_t ADC_Type::PG

ADC Plus-Side Gain Register, offset: 0x2C

ADC plus-side gain register, offset: 0x2C

PGA

__IO uint32_t ADC_Type::PGA

ADC PGA Register, offset: 0x50

ADC PGA register, offset: 0x50

PID

__IO uint32_t MCM_Type::PID

Process ID register, offset: 0x30

PLAMC

__I uint16_t MCM_Type::PLAMC

Crossbar Switch (AXBS) Master Configuration, offset: 0xA

Crossbar switch (AXBS) master configuration, offset: 0xA

PLASC

__I uint16_t MCM_Type::PLASC

Crossbar Switch (AXBS) Slave Configuration, offset: 0x8

Crossbar switch (AXBS) slave configuration, offset: 0x8

PMCTRL

__IO uint8_t SMC_Type::PMCTRL

Power Mode Control register, offset: 0x1

PMPROT

__IO uint8_t SMC_Type::PMPROT

Power Mode Protection register, offset: 0x0

PMSTAT

__I uint8_t SMC_Type::PMSTAT

Power Mode Status register, offset: 0x3

PODLY

__IO uint32_t PDB_Type::PODLY

Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4

Pulse-Out n Delay Register, offset: 0x194

Pulse-Out n Delay register, array offset: 0x194, array step: 0x4

POEN

__IO uint32_t PDB_Type::POEN

Pulse-Out n Enable Register, offset: 0x190

Pulse-Out n Enable register, offset: 0x190

POL

__IO uint32_t FTM_Type::POL

Channels Polarity, offset: 0x70

POPR

__I uint32_t SPI_Type::POPR

POP RX FIFO Register, offset: 0x38

DSPI POP RX FIFO Register, offset: 0x38

PPS

__IO uint8_t CMT_Type::PPS

CMT Primary Prescaler Register, offset: 0xA

PRE

__IO uint8_t UART_Type::PRE

UART CEA709.1-B Preamble, offset: 0x27

PRESC

__IO uint16_t WDOG_Type::PRESC

Watchdog Prescaler register, offset: 0x16

Watchdog Prescaler Register, offset: 0x16

PROCTL

__IO uint32_t SDHC_Type::PROCTL

Protocol Control register, offset: 0x28

Protocol Control Register, offset: 0x28

[] [1/2]

__IO uint32_t { ... } ::PRS

Priority Registers Slave, array offset: 0x0, array step: 0x100

PRS [2/2]

__IO uint32_t AXBS_Type::PRS

Priority Registers Slave, array offset: 0x0, array step: 0x100

PRSSTAT

__I uint32_t SDHC_Type::PRSSTAT

Present State register, offset: 0x24

Present State Register, offset: 0x24

PSOR

__O uint32_t GPIO_Type::PSOR

Port Set Output Register, offset: 0x4

PSR

__IO uint32_t LPTMR_Type::PSR

Low Power Timer Prescale Register, offset: 0x4

PTOR

__O uint32_t GPIO_Type::PTOR

Port Toggle Output Register, offset: 0xC

[] [1/2]

__IO uint32_t { ... } ::PUSHR

PUSH TX FIFO Register In Master Mode, offset: 0x34

PUSHR [2/2]

__IO uint32_t SPI_Type::PUSHR

PUSH TX FIFO Register In Master Mode, offset: 0x34

DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34

PUSHR_SLAVE [1/2]

__IO uint32_t SPI_Type::PUSHR_SLAVE

PUSH TX FIFO Register In Slave Mode, offset: 0x34

DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34

[] [2/2]

__IO uint32_t { ... } ::PUSHR_SLAVE

PUSH TX FIFO Register In Slave Mode, offset: 0x34

PWMLOAD

__IO uint32_t FTM_Type::PWMLOAD

FTM PWM Load, offset: 0x98

QDCTRL

__IO uint32_t FTM_Type::QDCTRL

Quadrature Decoder Control And Status, offset: 0x80

Quadrature Decoder Control and Status, offset: 0x80

R

__I uint32_t ADC_Type::R

ADC Data Result Register, array offset: 0x10, array step: 0x4

ADC data result register, array offset: 0x10, array step: 0x4

RA

__IO uint8_t I2C_Type::RA

I2C Range Address register, offset: 0x7

RACC

__IO uint32_t ENET_Type::RACC

Receive Accelerator Function Configuration, offset: 0x1C4

RADR_CA

__O uint32_t CAU_Type::RADR_CA

General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4

RADR_CAA

__O uint32_t CAU_Type::RADR_CAA

Accumulator register - Reverse and Add to Register command, offset: 0x904

RADR_CASR

__O uint32_t CAU_Type::RADR_CASR

Status register - Reverse and Add to Register command, offset: 0x900

RAEM

__IO uint32_t ENET_Type::RAEM

Receive FIFO Almost Empty Threshold, offset: 0x198

RAFL

__IO uint32_t ENET_Type::RAFL

Receive FIFO Almost Full Threshold, offset: 0x19C

RAR

__IO uint32_t RTC_Type::RAR

RTC Read Access Register, offset: 0x804

RCFIFO

__I uint8_t UART_Type::RCFIFO

UART FIFO Receive Count, offset: 0x16

RCR

__IO uint32_t ENET_Type::RCR

Receive Control Register, offset: 0x84

RCR1

__IO uint32_t I2S_Type::RCR1

SAI Receive Configuration 1 Register, offset: 0x84

RCR2

__IO uint32_t I2S_Type::RCR2

SAI Receive Configuration 2 Register, offset: 0x88

RCR3

__IO uint32_t I2S_Type::RCR3

SAI Receive Configuration 3 Register, offset: 0x8C

RCR4

__IO uint32_t I2S_Type::RCR4

SAI Receive Configuration 4 Register, offset: 0x90

RCR5

__IO uint32_t I2S_Type::RCR5

SAI Receive Configuration 5 Register, offset: 0x94

RCSR

__IO uint32_t I2S_Type::RCSR

SAI Receive Control Register, offset: 0x80

RDAR

__IO uint32_t ENET_Type::RDAR

Receive Descriptor Active Register, offset: 0x10

RDR

__I uint32_t I2S_Type::RDR

SAI Receive Data Register, array offset: 0xA0, array step: 0x4

RDSR

__IO uint32_t ENET_Type::RDSR

Receive Descriptor Ring Start Register, offset: 0x180

REFRESH

__IO uint16_t WDOG_Type::REFRESH

Watchdog Refresh register, offset: 0xC

Watchdog Refresh Register, offset: 0xC

REG [1/2]

__IO uint32_t RFSYS_Type::REG

Register file register, array offset: 0x0, array step: 0x4

REG [2/2]

__IO uint32_t RFVBAT_Type::REG

VBAT register file register, array offset: 0x0, array step: 0x4

REGSC

__IO uint8_t PMC_Type::REGSC

Regulator Status And Control register, offset: 0x2

Regulator Status and Control Register, offset: 0x2

REV

__I uint8_t USB_Type::REV

Peripheral Revision register, offset: 0x8

Peripheral Revision Register, offset: 0x8

RFR

__I uint32_t I2S_Type::RFR

SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4

RGDAAC

__IO uint32_t SYSMPU_Type::RGDAAC

Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4

RIDT

__IO uint8_t UART_Type::RIDT

UART CEA709.1-B Receive Indeterminate Time, offset: 0x30

RMON_R_BC_PKT

__I uint32_t ENET_Type::RMON_R_BC_PKT

RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288

Rx Broadcast Packets Statistic Register, offset: 0x288

RMON_R_CRC_ALIGN

__I uint32_t ENET_Type::RMON_R_CRC_ALIGN

RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290

Rx Packets with CRC/Align Error Statistic Register, offset: 0x290

RMON_R_FRAG

__I uint32_t ENET_Type::RMON_R_FRAG

RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C

Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C

RMON_R_JAB

__I uint32_t ENET_Type::RMON_R_JAB

RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0

Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0

RMON_R_MC_PKT

__I uint32_t ENET_Type::RMON_R_MC_PKT

RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C

Rx Multicast Packets Statistic Register, offset: 0x28C

RMON_R_OCTETS

__I uint32_t ENET_Type::RMON_R_OCTETS

RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4

Rx Octets Statistic Register, offset: 0x2C4

RMON_R_OVERSIZE

__I uint32_t ENET_Type::RMON_R_OVERSIZE

RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298

Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298

RMON_R_P1024TO2047

__I uint32_t ENET_Type::RMON_R_P1024TO2047

RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC

Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC

RMON_R_P128TO255

__I uint32_t ENET_Type::RMON_R_P128TO255

RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0

Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0

RMON_R_P256TO511

__I uint32_t ENET_Type::RMON_R_P256TO511

RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4

Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4

RMON_R_P512TO1023

__I uint32_t ENET_Type::RMON_R_P512TO1023

RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8

Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8

RMON_R_P64

__I uint32_t ENET_Type::RMON_R_P64

RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8

Rx 64-Byte Packets Statistic Register, offset: 0x2A8

RMON_R_P65TO127

__I uint32_t ENET_Type::RMON_R_P65TO127

RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC

Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC

RMON_R_P_GTE2048

__I uint32_t ENET_Type::RMON_R_P_GTE2048

RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0

Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0

RMON_R_PACKETS

__I uint32_t ENET_Type::RMON_R_PACKETS

RMON Rx packet count (RMON_R_PACKETS), offset: 0x284

Rx Packet Count Statistic Register, offset: 0x284

RMON_R_RESVD_0

uint32_t ENET_Type::RMON_R_RESVD_0

Reserved (RMON_R_RESVD_0), offset: 0x2A4

Reserved Statistic Register, offset: 0x2A4

RMON_R_UNDERSIZE

__I uint32_t ENET_Type::RMON_R_UNDERSIZE

RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294

Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294

RMON_T_BC_PKT

__I uint32_t ENET_Type::RMON_T_BC_PKT

RMON Tx Broadcast Packets (RMON_T_BC_PKT), offset: 0x208

Tx Broadcast Packets Statistic Register, offset: 0x208

RMON_T_COL

__I uint32_t ENET_Type::RMON_T_COL

RMON Tx collision count (RMON_T_COL), offset: 0x224

Tx Collision Count Statistic Register, offset: 0x224

RMON_T_CRC_ALIGN

__I uint32_t ENET_Type::RMON_T_CRC_ALIGN

RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN), offset: 0x210

Tx Packets with CRC/Align Error Statistic Register, offset: 0x210

RMON_T_DROP

uint32_t ENET_Type::RMON_T_DROP

Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x200

Reserved Statistic Register, offset: 0x200

RMON_T_FRAG

__I uint32_t ENET_Type::RMON_T_FRAG

RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C

Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C

RMON_T_JAB

__I uint32_t ENET_Type::RMON_T_JAB

RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220

Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220

RMON_T_MC_PKT

__I uint32_t ENET_Type::RMON_T_MC_PKT

RMON Tx Multicast Packets (RMON_T_MC_PKT), offset: 0x20C

Tx Multicast Packets Statistic Register, offset: 0x20C

RMON_T_OCTETS

__I uint32_t ENET_Type::RMON_T_OCTETS

RMON Tx Octets (RMON_T_OCTETS), offset: 0x244

Tx Octets Statistic Register, offset: 0x244

RMON_T_OVERSIZE

__I uint32_t ENET_Type::RMON_T_OVERSIZE

RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218

Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218

RMON_T_P1024TO2047

__I uint32_t ENET_Type::RMON_T_P1024TO2047

RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C

Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C

RMON_T_P128TO255

__I uint32_t ENET_Type::RMON_T_P128TO255

RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230

Tx 128- to 255-byte Packets Statistic Register, offset: 0x230

RMON_T_P256TO511

__I uint32_t ENET_Type::RMON_T_P256TO511

RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234

Tx 256- to 511-byte Packets Statistic Register, offset: 0x234

RMON_T_P512TO1023

__I uint32_t ENET_Type::RMON_T_P512TO1023

RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238

Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238

RMON_T_P64

__I uint32_t ENET_Type::RMON_T_P64

RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228

Tx 64-Byte Packets Statistic Register, offset: 0x228

RMON_T_P65TO127

__I uint32_t ENET_Type::RMON_T_P65TO127

RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C

Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C

RMON_T_P_GTE2048

__I uint32_t ENET_Type::RMON_T_P_GTE2048

RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240

Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240

RMON_T_PACKETS

__I uint32_t ENET_Type::RMON_T_PACKETS

RMON Tx packet count (RMON_T_PACKETS), offset: 0x204

Tx Packet Count Statistic Register, offset: 0x204

RMON_T_UNDERSIZE

__I uint32_t ENET_Type::RMON_T_UNDERSIZE

RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE), offset: 0x214

Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214

RMR

__IO uint32_t I2S_Type::RMR

SAI Receive Mask Register, offset: 0xE0

ROTL_CA

__O uint32_t CAU_Type::ROTL_CA

General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4

ROTL_CAA

__O uint32_t CAU_Type::ROTL_CAA

Accumulator register - Rotate Left command, offset: 0x9C4

ROTL_CASR

__O uint32_t CAU_Type::ROTL_CASR

Status register - Rotate Left command, offset: 0x9C0

RPFC

__IO uint8_t RCM_Type::RPFC

Reset Pin Filter Control register, offset: 0x4

RPFW

__IO uint8_t RCM_Type::RPFW

Reset Pin Filter Width register, offset: 0x5

RPL

__I uint8_t UART_Type::RPL

UART CEA709.1-B Received Packet Length, offset: 0x2D

RPREL

__I uint8_t UART_Type::RPREL

UART CEA709.1-B Received Preamble Length, offset: 0x2E

RSEM

__IO uint32_t ENET_Type::RSEM

Receive FIFO Section Empty Threshold, offset: 0x194

RSER

__IO uint32_t SPI_Type::RSER

DMA/Interrupt Request Select and Enable Register, offset: 0x30

DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30

RSFL

__IO uint32_t ENET_Type::RSFL

Receive FIFO Section Full Threshold, offset: 0x190

RST

__IO uint8_t LLWU_Type::RST

LLWU Reset Enable register, offset: 0xA

RSTCNT

__IO uint16_t WDOG_Type::RSTCNT

Watchdog Reset Count register, offset: 0x14

Watchdog Reset Count Register, offset: 0x14

RWFIFO

__IO uint8_t UART_Type::RWFIFO

UART FIFO Receive Watermark, offset: 0x15

RX14MASK

__IO uint32_t CAN_Type::RX14MASK

Rx 14 Mask register, offset: 0x14

Rx 14 Mask Register, offset: 0x14

RX15MASK

__IO uint32_t CAN_Type::RX15MASK

Rx 15 Mask register, offset: 0x18

Rx 15 Mask Register, offset: 0x18

RXFGMASK

__IO uint32_t CAN_Type::RXFGMASK

Rx FIFO Global Mask register, offset: 0x48

Rx FIFO Global Mask Register, offset: 0x48

RXFIR

__I uint32_t CAN_Type::RXFIR

Rx FIFO Information Register, offset: 0x4C

RXFR0

__I uint32_t SPI_Type::RXFR0

DSPI Receive FIFO Registers, offset: 0x7C

Receive FIFO Registers, offset: 0x7C

RXFR1

__I uint32_t SPI_Type::RXFR1

DSPI Receive FIFO Registers, offset: 0x80

Receive FIFO Registers, offset: 0x80

RXFR2

__I uint32_t SPI_Type::RXFR2

DSPI Receive FIFO Registers, offset: 0x84

Receive FIFO Registers, offset: 0x84

RXFR3

__I uint32_t SPI_Type::RXFR3

DSPI Receive FIFO Registers, offset: 0x88

Receive FIFO Registers, offset: 0x88

RXIMR

__IO uint32_t CAN_Type::RXIMR

Rx Individual Mask Registers, array offset: 0x880, array step: 0x4

RXMGMASK

__IO uint32_t CAN_Type::RXMGMASK

Rx Mailboxes Global Mask Register, offset: 0x10

S [1/4]

__IO uint8_t I2C_Type::S

I2C Status register, offset: 0x3

I2C Status Register, offset: 0x3

S [2/4]

__IO uint8_t MCG_Type::S

MCG Status Register, offset: 0x6

[] [3/4]

__IO uint32_t { ... } ::S

Channel n Status Register, array offset: 0x14, array step: 0x28

S [4/4]

__IO uint32_t PDB_Type::S

Channel n Status Register, array offset: 0x14, array step: 0x28

Channel n Status register, array offset: 0x14, array step: 0x28

S1

__I uint8_t UART_Type::S1

UART Status Register 1, offset: 0x4

S2

__IO uint8_t UART_Type::S2

UART Status Register 2, offset: 0x5

S3

__IO uint8_t UART_Type::S3

UART CEA709.1-B Status Register, offset: 0x2B

S4

__IO uint8_t UART_Type::S4

UART CEA709.1-B Status Register, offset: 0x2C

SADDR [1/2]

__IO uint32_t DMA_Type::SADDR

TCD Source Address, array offset: 0x1000, array step: 0x20

[] [2/2]

__IO uint32_t { ... } ::SADDR

TCD Source Address, array offset: 0x1000, array step: 0x20

SC [1/4]

__IO uint32_t FTM_Type::SC

Status And Control, offset: 0x0

Status and Control, offset: 0x0

SC [2/4]

__IO uint8_t MCG_Type::SC

MCG Status and Control Register, offset: 0x8

SC [3/4]

__IO uint32_t PDB_Type::SC

Status and Control Register, offset: 0x0

Status and Control register, offset: 0x0

SC [4/4]

__IO uint8_t VREF_Type::SC

VREF Status and Control Register, offset: 0x1

SC1

__IO uint32_t ADC_Type::SC1

ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4

ADC status and control registers 1, array offset: 0x0, array step: 0x4

SC2

__IO uint32_t ADC_Type::SC2

Status and Control Register 2, offset: 0x20

Status and control register 2, offset: 0x20

SC3

__IO uint32_t ADC_Type::SC3

Status and Control Register 3, offset: 0x24

Status and control register 3, offset: 0x24

SCANC

__IO uint32_t TSI_Type::SCANC

SCAN Control register, offset: 0x4

SCAN control register, offset: 0x4

SCGC1

__IO uint32_t SIM_Type::SCGC1

System Clock Gating Control Register 1, offset: 0x1028

SCGC2

__IO uint32_t SIM_Type::SCGC2

System Clock Gating Control Register 2, offset: 0x102C

SCGC3

__IO uint32_t SIM_Type::SCGC3

System Clock Gating Control Register 3, offset: 0x1030

SCGC4

__IO uint32_t SIM_Type::SCGC4

System Clock Gating Control Register 4, offset: 0x1034

SCGC5

__IO uint32_t SIM_Type::SCGC5

System Clock Gating Control Register 5, offset: 0x1038

SCGC6

__IO uint32_t SIM_Type::SCGC6

System Clock Gating Control Register 6, offset: 0x103C

SCGC7

__IO uint32_t SIM_Type::SCGC7

System Clock Gating Control Register 7, offset: 0x1040

SCR

__IO uint8_t CMP_Type::SCR

CMP Status and Control Register, offset: 0x3

SDID

__I uint32_t SIM_Type::SDID

System Device Identification Register, offset: 0x1024

SDTH

__IO uint8_t UART_Type::SDTH

UART CEA709.1-B Secondary Delay Timer High, offset: 0x25

SDTL

__IO uint8_t UART_Type::SDTL

UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26

SEEI

__O uint8_t DMA_Type::SEEI

Set Enable Error Interrupt Register, offset: 0x19

SERQ

__O uint8_t DMA_Type::SERQ

Set Enable Request Register, offset: 0x1B

SERV

__O uint8_t EWM_Type::SERV

Service Register, offset: 0x1

SFIFO

__IO uint8_t UART_Type::SFIFO

UART FIFO Status Register, offset: 0x12

[] [1/2]

__IO uint32_t { ... } ::SLAST

TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20

SLAST [2/2]

__IO uint32_t DMA_Type::SLAST

TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20

SLTH

__IO uint8_t I2C_Type::SLTH

I2C SCL Low Timeout Register High, offset: 0xA

SLTL

__IO uint8_t I2C_Type::SLTL

I2C SCL Low Timeout Register Low, offset: 0xB

SMB

__IO uint8_t I2C_Type::SMB

I2C SMBus Control and Status register, offset: 0x8

SOFF [1/2]

__IO uint16_t DMA_Type::SOFF

TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20

[] [2/2]

__IO uint16_t { ... } ::SOFF

TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20

SOFTHLD

__IO uint8_t USB_Type::SOFTHLD

SOF Threshold Register, offset: 0xAC

SOF Threshold register, offset: 0xAC

SOPT1

__IO uint32_t SIM_Type::SOPT1

System Options Register 1, offset: 0x0

SOPT1CFG

__IO uint32_t SIM_Type::SOPT1CFG

SOPT1 Configuration Register, offset: 0x4

SOPT2

__IO uint32_t SIM_Type::SOPT2

System Options Register 2, offset: 0x1004

SOPT4

__IO uint32_t SIM_Type::SOPT4

System Options Register 4, offset: 0x100C

SOPT5

__IO uint32_t SIM_Type::SOPT5

System Options Register 5, offset: 0x1010

SOPT7

__IO uint32_t SIM_Type::SOPT7

System Options Register 7, offset: 0x1018

SR [1/4]

__IO uint8_t DAC_Type::SR

DAC Status Register, offset: 0x20

SR [2/4]

__I uint32_t RNG_Type::SR

RNGA Status Register, offset: 0x4

RNGB Status Register, offset: 0xC

SR [3/4]

__IO uint32_t RTC_Type::SR

RTC Status Register, offset: 0x14

SR [4/4]

__IO uint32_t SPI_Type::SR

DSPI Status Register, offset: 0x2C

Status Register, offset: 0x2C

SRS0

__I uint8_t RCM_Type::SRS0

System Reset Status Register 0, offset: 0x0

SRS1

__I uint8_t RCM_Type::SRS1

System Reset Status Register 1, offset: 0x1

SSRT

__O uint8_t DMA_Type::SSRT

Set START Bit Register, offset: 0x1D

STAT

__I uint8_t USB_Type::STAT

Status register, offset: 0x90

Status Register, offset: 0x90

STATUS [1/2]

__IO uint32_t FTM_Type::STATUS

Capture And Compare Status, offset: 0x50

STATUS [2/2]

__I uint32_t USBDCD_Type::STATUS

Status register, offset: 0x8

Status Register, offset: 0x8

STCTRLH

__IO uint16_t WDOG_Type::STCTRLH

Watchdog Status and Control Register High, offset: 0x0

STCTRLL

__IO uint16_t WDOG_Type::STCTRLL

Watchdog Status and Control Register Low, offset: 0x2

STR_CA

__I uint32_t CAU_Type::STR_CA

General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4

STR_CAA

__I uint32_t CAU_Type::STR_CAA

Accumulator register - Store Register command, offset: 0x884

STR_CASR

__I uint32_t CAU_Type::STR_CASR

Status register - Store Register command, offset: 0x880

SWOCTRL

__IO uint32_t FTM_Type::SWOCTRL

FTM Software Output Control, offset: 0x94

SYNC

__IO uint32_t FTM_Type::SYNC

Synchronization, offset: 0x58

SYNCONF

__IO uint32_t FTM_Type::SYNCONF

Synchronization Configuration, offset: 0x8C

SYSCTL

__IO uint32_t SDHC_Type::SYSCTL

System Control register, offset: 0x2C

System Control Register, offset: 0x2C

TACC

__IO uint32_t ENET_Type::TACC

Transmit Accelerator Function Configuration, offset: 0x1C0

TAEM

__IO uint32_t ENET_Type::TAEM

Transmit FIFO Almost Empty Threshold, offset: 0x1A4

TAFL

__IO uint32_t ENET_Type::TAFL

Transmit FIFO Almost Full Threshold, offset: 0x1A8

TAGVD

__IO uint32_t FMC_Type::TAGVD

Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4

Cache Directory Storage, array offset: 0x100, array step: index*0x20, index2*0x4

TAR

__IO uint32_t RTC_Type::TAR

RTC Time Alarm Register, offset: 0x8

[] [1/2]

__IO uint32_t { ... } ::TCCR

Timer Compare Capture Register, array offset: 0x60C, array step: 0x8

TCCR [2/2]

__IO uint32_t ENET_Type::TCCR

Timer Compare Capture Register, array offset: 0x60C, array step: 0x8

TCFIFO

__I uint8_t UART_Type::TCFIFO

UART FIFO Transmit Count, offset: 0x14

TCR [1/3]

__IO uint32_t ENET_Type::TCR

Transmit Control Register, offset: 0xC4

TCR [2/3]

__IO uint32_t RTC_Type::TCR

RTC Time Compensation Register, offset: 0xC

TCR [3/3]

__IO uint32_t SPI_Type::TCR

Transfer Count Register, offset: 0x8

DSPI Transfer Count Register, offset: 0x8

TCR1

__IO uint32_t I2S_Type::TCR1

SAI Transmit Configuration 1 Register, offset: 0x4

TCR2

__IO uint32_t I2S_Type::TCR2

SAI Transmit Configuration 2 Register, offset: 0x8

TCR3

__IO uint32_t I2S_Type::TCR3

SAI Transmit Configuration 3 Register, offset: 0xC

TCR4

__IO uint32_t I2S_Type::TCR4

SAI Transmit Configuration 4 Register, offset: 0x10

TCR5

__IO uint32_t I2S_Type::TCR5

SAI Transmit Configuration 5 Register, offset: 0x14

[] [1/3]

__IO uint32_t { ... } ::TCSR

Timer Control Status Register, array offset: 0x608, array step: 0x8

TCSR [2/3]

__IO uint32_t ENET_Type::TCSR

Timer Control Status Register, array offset: 0x608, array step: 0x8

TCSR [3/3]

__IO uint32_t I2S_Type::TCSR

SAI Transmit Control Register, offset: 0x0

TCTRL [1/2]

__IO uint32_t PIT_Type::TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

[] [2/2]

__IO uint32_t { ... } ::TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

TDAR

__IO uint32_t ENET_Type::TDAR

Transmit Descriptor Active Register, offset: 0x14

TDR

__O uint32_t I2S_Type::TDR

SAI Transmit Data Register, array offset: 0x20, array step: 0x4

TDSR

__IO uint32_t ENET_Type::TDSR

Transmit Buffer Descriptor Ring Start Register, offset: 0x184

[] [1/2]

__IO uint32_t { ... } ::TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

TFLG [2/2]

__IO uint32_t PIT_Type::TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

TFR

__I uint32_t I2S_Type::TFR

SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4

TFWR

__IO uint32_t ENET_Type::TFWR

Transmit FIFO Watermark Register, offset: 0x144

TGSR

__IO uint32_t ENET_Type::TGSR

Timer Global Status Register, offset: 0x604

THRESHOLD

__IO uint32_t TSI_Type::THRESHOLD

Low-Power Channel Threshold register, offset: 0x120

TIDT

__IO uint8_t UART_Type::TIDT

UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31

TIMER

__IO uint32_t CAN_Type::TIMER

Free Running Timer, offset: 0x8

TIMER0

__IO uint32_t USBDCD_Type::TIMER0

TIMER0 register, offset: 0x10

TIMER0 Register, offset: 0x10

TIMER1

__IO uint32_t USBDCD_Type::TIMER1

TIMER1 register, offset: 0x14

, offset: 0x14

TIMER2

__IO uint32_t USBDCD_Type::TIMER2

TIMER2 register, offset: 0x18

, offset: 0x18

TIPG

__IO uint32_t ENET_Type::TIPG

Transmit Inter-Packet Gap, offset: 0x1AC

TL7816

__IO uint8_t UART_Type::TL7816

UART 7816 Transmit Length Register, offset: 0x1F

TMR

__IO uint32_t I2S_Type::TMR

SAI Transmit Mask Register, offset: 0x60

TMROUTH

__IO uint16_t WDOG_Type::TMROUTH

Watchdog Timer Output Register High, offset: 0x10

TMROUTL

__IO uint16_t WDOG_Type::TMROUTL

Watchdog Timer Output Register Low, offset: 0x12

TOKEN

__IO uint8_t USB_Type::TOKEN

Token register, offset: 0xA8

Token Register, offset: 0xA8

TOVALH

__IO uint16_t WDOG_Type::TOVALH

Watchdog Time-out Value Register High, offset: 0x4

TOVALL

__IO uint16_t WDOG_Type::TOVALL

Watchdog Time-out Value Register Low, offset: 0x6

TPL

__IO uint8_t UART_Type::TPL

UART CEA709.1-B Transmit Packet Length, offset: 0x28

TPR

__IO uint32_t RTC_Type::TPR

RTC Time Prescaler Register, offset: 0x4

TRM

__IO uint8_t VREF_Type::TRM

VREF Trim Register, offset: 0x0

TSEM

__IO uint32_t ENET_Type::TSEM

Transmit FIFO Section Empty Threshold, offset: 0x1A0

TSR

__IO uint32_t RTC_Type::TSR

RTC Time Seconds Register, offset: 0x0

TWFIFO

__IO uint8_t UART_Type::TWFIFO

UART FIFO Transmit Watermark, offset: 0x13

TXFR0

__I uint32_t SPI_Type::TXFR0

DSPI Transmit FIFO Registers, offset: 0x3C

Transmit FIFO Registers, offset: 0x3C

TXFR1

__I uint32_t SPI_Type::TXFR1

DSPI Transmit FIFO Registers, offset: 0x40

Transmit FIFO Registers, offset: 0x40

TXFR2

__I uint32_t SPI_Type::TXFR2

DSPI Transmit FIFO Registers, offset: 0x44

Transmit FIFO Registers, offset: 0x44

TXFR3

__I uint32_t SPI_Type::TXFR3

DSPI Transmit FIFO Registers, offset: 0x48

Transmit FIFO Registers, offset: 0x48

UIDH

__I uint32_t SIM_Type::UIDH

Unique Identification Register High, offset: 0x1054

UIDL

__I uint32_t SIM_Type::UIDL

Unique Identification Register Low, offset: 0x1060

UIDMH

__I uint32_t SIM_Type::UIDMH

Unique Identification Register Mid-High, offset: 0x1058

UIDML

__I uint32_t SIM_Type::UIDML

Unique Identification Register Mid Low, offset: 0x105C

UNLOCK

__IO uint16_t WDOG_Type::UNLOCK

Watchdog Unlock register, offset: 0xE

Watchdog Unlock Register, offset: 0xE

USBCTRL

__IO uint8_t USB_Type::USBCTRL

USB Control register, offset: 0x100

USB Control Register, offset: 0x100

USBFRMADJUST

__IO uint8_t USB_Type::USBFRMADJUST

Frame Adjust Register, offset: 0x114

USBTRC0

__IO uint8_t USB_Type::USBTRC0

USB Transceiver Control Register 0, offset: 0x10C

USB Transceiver Control register 0, offset: 0x10C

VENDOR

__IO uint32_t SDHC_Type::VENDOR

Vendor Specific register, offset: 0xC0

Vendor Specific Register, offset: 0xC0

VLLSCTRL

__IO uint8_t SMC_Type::VLLSCTRL

VLLS Control register, offset: 0x2

WAR

__IO uint32_t RTC_Type::WAR

RTC Write Access Register, offset: 0x800

WB

__IO uint8_t UART_Type::WB

UART CEA709.1-B WBASE, offset: 0x2A

WF7816

__IO uint8_t UART_Type::WF7816

UART 7816 Wait FD Register, offset: 0x1D

WINH

__IO uint16_t WDOG_Type::WINH

Watchdog Window Register High, offset: 0x8

WINL

__IO uint16_t WDOG_Type::WINL

Watchdog Window Register Low, offset: 0xA

WML

__IO uint32_t SDHC_Type::WML

Watermark Level Register, offset: 0x44

WN7816

__IO uint8_t UART_Type::WN7816

UART 7816 Wait N Register, offset: 0x1C

WORD

__IO uint32_t SYSMPU_Type::WORD

Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4

[] [1/2]

__IO uint32_t { ... } ::WORD0

Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10

WORD0 [2/2]

__IO uint32_t CAN_Type::WORD0

Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10

[] [1/2]

__IO uint32_t { ... } ::WORD1

Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10

WORD1 [2/2]

__IO uint32_t CAN_Type::WORD1

Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10

[] [1/2]

__IO uint8_t { ... } ::WP7816T0

UART 7816 Wait Parameter Register, offset: 0x1B

WP7816T0 [2/2]

__IO uint8_t UART_Type::WP7816T0

UART 7816 Wait Parameter Register, offset: 0x1B

[] [1/2]

__IO uint8_t { ... } ::WP7816T1

UART 7816 Wait Parameter Register, offset: 0x1B

WP7816T1 [2/2]

__IO uint8_t UART_Type::WP7816T1

UART 7816 Wait Parameter Register, offset: 0x1B

WUCNTR

__I uint32_t TSI_Type::WUCNTR

Wake-Up Channel Counter Register, offset: 0xC

XFERTYP

__IO uint32_t SDHC_Type::XFERTYP

Transfer Type register, offset: 0xC

Transfer Type Register, offset: 0xC

XOR_CA

__O uint32_t CAU_Type::XOR_CA

General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4

XOR_CAA

__O uint32_t CAU_Type::XOR_CAA

Accumulator register - Exclusive Or command, offset: 0x984

XOR_CASR

__O uint32_t CAU_Type::XOR_CASR

Status register - Exclusive Or command, offset: 0x980