|
mikroSDK Reference Manual
|
Topics | |
| VREF Register Masks | |
| WDOG Peripheral Access Layer | |
| Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). | |
| SDK Compatibility | |
Data Structures | |
| struct | VREF_Type |
Macros | |
| #define | VREF_BASE (0x40074000u) |
| #define | VREF ((VREF_Type *)VREF_BASE) |
| #define | VREF_BASE (0x40074000u) |
| #define | VREF ((VREF_Type *)VREF_BASE) |
| #define | VREF_BASE_ADDRS { VREF_BASE } |
| #define | VREF_BASE_PTRS { VREF } |
| #define | VREF_BASE (0x40074000u) |
| #define | VREF ((VREF_Type *)VREF_BASE) |
| #define | VREF_BASE_ADDRS { VREF_BASE } |
| #define | VREF_BASE_PTRS { VREF } |
| #define | VREF_BASE (0x40074000u) |
| #define | VREF ((VREF_Type *)VREF_BASE) |
| #define | VREF_BASE_ADDRS { VREF_BASE } |
| #define | VREF_BASE_PTRS { VREF } |
| #define VREF_BASE (0x40074000u) |
Peripheral VREF base address
| #define VREF_BASE (0x40074000u) |
Peripheral VREF base address
| #define VREF_BASE (0x40074000u) |
Peripheral VREF base address
| #define VREF_BASE (0x40074000u) |
Peripheral VREF base address
| #define VREF_BASE_ADDRS { VREF_BASE } |
Array initializer of VREF peripheral base addresses
| #define VREF_BASE_ADDRS { VREF_BASE } |
Array initializer of VREF peripheral base addresses
| #define VREF_BASE_ADDRS { VREF_BASE } |
Array initializer of VREF peripheral base addresses
| #define VREF_BASE_PTRS { VREF } |
Array initializer of VREF peripheral base pointers
| #define VREF_BASE_PTRS { VREF } |
Array initializer of VREF peripheral base pointers
| #define VREF_BASE_PTRS { VREF } |
Array initializer of VREF peripheral base pointers
| __IO uint8_t I2C_Type::A1 |
I2C Address Register 1, offset: 0x0
| __IO uint8_t I2C_Type::A2 |
I2C Address Register 2, offset: 0x9
| __I uint32_t SDHC_Type::AC12ERR |
Auto CMD12 Error Status Register, offset: 0x3C
| __I uint8_t USB_Type::ADDINFO |
Peripheral Additional Info register, offset: 0xC
Peripheral Additional Info Register, offset: 0xC
| __IO uint8_t USB_Type::ADDR |
Address register, offset: 0x98
Address Register, offset: 0x98
| __I uint32_t SDHC_Type::ADMAES |
ADMA Error Status register, offset: 0x54
ADMA Error Status Register, offset: 0x54
| __O uint32_t CAU_Type::ADR_CA |
General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4
| __O uint32_t CAU_Type::ADR_CAA |
Accumulator register - Add to register command, offset: 0x8C4
| __O uint32_t CAU_Type::ADR_CASR |
Status register - Add Register command, offset: 0x8C0
| __IO uint32_t SDHC_Type::ADSADDR |
ADMA System Addressregister, offset: 0x58
ADMA System Address Register, offset: 0x58
| __O uint32_t CAU_Type::AESC_CA |
General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4
| __O uint32_t CAU_Type::AESC_CAA |
Accumulator register - AES Column Operation command, offset: 0xB04
| __O uint32_t CAU_Type::AESC_CASR |
Status register - AES Column Operation command, offset: 0xB00
| __O uint32_t CAU_Type::AESIC_CA |
General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4
| __O uint32_t CAU_Type::AESIC_CAA |
Accumulator register - AES Inverse Column Operation command, offset: 0xB44
| __O uint32_t CAU_Type::AESIC_CASR |
Status register - AES Inverse Column Operation command, offset: 0xB40
| __IO uint32_t ENET_Type::ATCOR |
Timer Correction Register, offset: 0x410
| __IO uint32_t ENET_Type::ATCR |
Timer Control Register, offset: 0x400
Adjustable Timer Control Register, offset: 0x400
| __IO uint8_t MCG_Type::ATCVH |
MCG Auto Trim Compare Value High Register, offset: 0xA
| __IO uint8_t MCG_Type::ATCVL |
MCG Auto Trim Compare Value Low Register, offset: 0xB
| __IO uint32_t ENET_Type::ATINC |
Time-Stamping Clock Period Register, offset: 0x414
| __IO uint32_t ENET_Type::ATOFF |
Timer Offset Register, offset: 0x408
| __IO uint32_t ENET_Type::ATPER |
Timer Period Register, offset: 0x40C
| __I uint32_t ENET_Type::ATSTMP |
Timestamp of Last Transmitted Frame, offset: 0x418
| __IO uint16_t { ... } ::ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
| __IO uint16_t DMA_Type::ATTR |
TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
| __IO uint32_t ENET_Type::ATVR |
Timer Value Register, offset: 0x404
| __IO uint8_t UART_Type::B1T |
UART CEA709.1-B Beta1 Timer, offset: 0x24
| __I uint8_t NV_Type::BACKKEY0 |
Backdoor Comparison Key 0., offset: 0x3
| __I uint8_t NV_Type::BACKKEY1 |
Backdoor Comparison Key 1., offset: 0x2
| __I uint8_t NV_Type::BACKKEY2 |
Backdoor Comparison Key 2., offset: 0x1
| __I uint8_t NV_Type::BACKKEY3 |
Backdoor Comparison Key 3., offset: 0x0
| __I uint8_t NV_Type::BACKKEY4 |
Backdoor Comparison Key 4., offset: 0x7
| __I uint8_t NV_Type::BACKKEY5 |
Backdoor Comparison Key 5., offset: 0x6
| __I uint8_t NV_Type::BACKKEY6 |
Backdoor Comparison Key 6., offset: 0x5
| __I uint8_t NV_Type::BACKKEY7 |
Backdoor Comparison Key 7., offset: 0x4
| __IO uint8_t UART_Type::BDH |
UART Baud Rate Registers: High, offset: 0x0
UART Baud Rate Registers:High, offset: 0x0
| __IO uint8_t UART_Type::BDL |
UART Baud Rate Registers: Low, offset: 0x1
| __IO uint8_t USB_Type::BDTPAGE1 |
BDT Page Register 1, offset: 0x9C
BDT Page register 1, offset: 0x9C
| __IO uint8_t USB_Type::BDTPAGE2 |
BDT Page Register 2, offset: 0xB0
| __IO uint8_t USB_Type::BDTPAGE3 |
BDT Page Register 3, offset: 0xB4
| __IO uint16_t { ... } ::BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t DMA_Type::BITER_ELINKNO |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t { ... } ::BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20
| __IO uint16_t DMA_Type::BITER_ELINKYES |
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20
| __IO uint32_t SDHC_Type::BLKATTR |
Block Attributes register, offset: 0x4
Block Attributes Register, offset: 0x4
| __IO uint8_t DAC_Type::C0 |
DAC Control Register, offset: 0x21
| __IO uint8_t DAC_Type::C1 |
DAC Control Register 1, offset: 0x22
| __IO uint8_t I2C_Type::C1 |
I2C Control Register 1, offset: 0x2
| __IO uint8_t MCG_Type::C1 |
MCG Control 1 Register, offset: 0x0
| __IO uint32_t PDB_Type::C1 |
Channel n Control Register 1, array offset: 0x10, array step: 0x28
Channel n Control register 1, array offset: 0x10, array step: 0x28
| __IO uint32_t { ... } ::C1 |
Channel n Control Register 1, array offset: 0x10, array step: 0x28
| __IO uint8_t UART_Type::C1 |
UART Control Register 1, offset: 0x2
| __I uint8_t MCG_Type::C10 |
MCG Control 10 Register, offset: 0xF
| __IO uint8_t DAC_Type::C2 |
DAC Control Register 2, offset: 0x23
| __IO uint8_t I2C_Type::C2 |
I2C Control Register 2, offset: 0x5
| __IO uint8_t MCG_Type::C2 |
MCG Control 2 Register, offset: 0x1
| __IO uint8_t UART_Type::C2 |
UART Control Register 2, offset: 0x3
| __IO uint8_t MCG_Type::C3 |
MCG Control 3 Register, offset: 0x2
| __IO uint8_t UART_Type::C3 |
UART Control Register 3, offset: 0x6
| __IO uint8_t MCG_Type::C4 |
MCG Control 4 Register, offset: 0x3
| __IO uint8_t UART_Type::C4 |
UART Control Register 4, offset: 0xA
| __IO uint8_t MCG_Type::C5 |
MCG Control 5 Register, offset: 0x4
| __IO uint8_t UART_Type::C5 |
UART Control Register 5, offset: 0xB
| __IO uint8_t MCG_Type::C6 |
MCG Control 6 Register, offset: 0x5
| __IO uint8_t UART_Type::C6 |
UART CEA709.1-B Control Register 6, offset: 0x21
| __IO uint8_t MCG_Type::C7 |
MCG Control 7 Register, offset: 0xC
| __IO uint8_t UART_Type::C7816 |
UART 7816 Control Register, offset: 0x18
| __IO uint8_t MCG_Type::C8 |
MCG Control 8 Register, offset: 0xD
| __IO uint8_t MCG_Type::C9 |
MCG Control 9 Register, offset: 0xE
| __O uint8_t DMA_Type::CDNE |
Clear DONE Status Bit Register, offset: 0x1C
| __O uint8_t DMA_Type::CEEI |
Clear Enable Error Interrupt Register, offset: 0x18
| __O uint8_t DMA_Type::CERQ |
Clear Enable Request Register, offset: 0x1A
| __O uint8_t DMA_Type::CERR |
Clear Error Register, offset: 0x1E
| __IO uint32_t SYSMPU_Type::CESR |
Control/Error Status Register, offset: 0x0
| __IO uint32_t ADC_Type::CFG1 |
ADC Configuration Register 1, offset: 0x8
ADC configuration register 1, offset: 0x8
| __IO uint32_t ADC_Type::CFG2 |
ADC Configuration Register 2, offset: 0xC
Configuration register 2, offset: 0xC
| __IO uint8_t UART_Type::CFIFO |
UART FIFO Control Register, offset: 0x11
| __IO uint8_t CMT_Type::CGH1 |
CMT Carrier Generator High Data Register 1, offset: 0x0
| __IO uint8_t CMT_Type::CGH2 |
CMT Carrier Generator High Data Register 2, offset: 0x2
| __IO uint8_t CMT_Type::CGL1 |
CMT Carrier Generator Low Data Register 1, offset: 0x1
| __IO uint8_t CMT_Type::CGL2 |
CMT Carrier Generator Low Data Register 2, offset: 0x3
| __IO uint8_t DMAMUX_Type::CHCFG |
Channel Configuration register, array offset: 0x0, array step: 0x1
Channel Configuration Register, array offset: 0x0, array step: 0x1
| __O uint8_t DMA_Type::CINT |
Clear Interrupt Request Register, offset: 0x1F
| __IO uint16_t { ... } ::CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t DMA_Type::CITER_ELINKNO |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t { ... } ::CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20
| __IO uint16_t DMA_Type::CITER_ELINKYES |
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20
| __IO uint32_t SIM_Type::CLKDIV1 |
System Clock Divider Register 1, offset: 0x1044
| __IO uint32_t SIM_Type::CLKDIV2 |
System Clock Divider Register 2, offset: 0x1048
| __IO uint8_t EWM_Type::CLKPRESCALER |
Clock Prescaler Register, offset: 0x5
| __IO uint32_t ADC_Type::CLM0 |
ADC Minus-Side General Calibration Value Register, offset: 0x6C
ADC minus-side general calibration value register, offset: 0x6C
| __IO uint32_t ADC_Type::CLM1 |
ADC Minus-Side General Calibration Value Register, offset: 0x68
ADC minus-side general calibration value register, offset: 0x68
| __IO uint32_t ADC_Type::CLM2 |
ADC Minus-Side General Calibration Value Register, offset: 0x64
ADC minus-side general calibration value register, offset: 0x64
| __IO uint32_t ADC_Type::CLM3 |
ADC Minus-Side General Calibration Value Register, offset: 0x60
ADC minus-side general calibration value register, offset: 0x60
| __IO uint32_t ADC_Type::CLM4 |
ADC Minus-Side General Calibration Value Register, offset: 0x5C
ADC minus-side general calibration value register, offset: 0x5C
| __IO uint32_t ADC_Type::CLMD |
ADC Minus-Side General Calibration Value Register, offset: 0x54
ADC minus-side general calibration value register, offset: 0x54
| __IO uint32_t ADC_Type::CLMS |
ADC Minus-Side General Calibration Value Register, offset: 0x58
ADC minus-side general calibration value register, offset: 0x58
| __IO uint32_t USBDCD_Type::CLOCK |
Clock register, offset: 0x4
Clock Register, offset: 0x4
| __IO uint32_t ADC_Type::CLP0 |
ADC Plus-Side General Calibration Value Register, offset: 0x4C
ADC plus-side general calibration value register, offset: 0x4C
| __IO uint32_t ADC_Type::CLP1 |
ADC Plus-Side General Calibration Value Register, offset: 0x48
ADC plus-side general calibration value register, offset: 0x48
| __IO uint32_t ADC_Type::CLP2 |
ADC Plus-Side General Calibration Value Register, offset: 0x44
ADC plus-side general calibration value register, offset: 0x44
| __IO uint32_t ADC_Type::CLP3 |
ADC Plus-Side General Calibration Value Register, offset: 0x40
ADC plus-side general calibration value register, offset: 0x40
| __IO uint32_t ADC_Type::CLP4 |
ADC Plus-Side General Calibration Value Register, offset: 0x3C
ADC plus-side general calibration value register, offset: 0x3C
| __IO uint32_t ADC_Type::CLPD |
ADC Plus-Side General Calibration Value Register, offset: 0x34
ADC plus-side general calibration value register, offset: 0x34
| __IO uint32_t ADC_Type::CLPS |
ADC Plus-Side General Calibration Value Register, offset: 0x38
ADC plus-side general calibration value register, offset: 0x38
| __IO uint8_t CMT_Type::CMD1 |
CMT Modulator Data Register Mark High, offset: 0x6
| __IO uint8_t CMT_Type::CMD2 |
CMT Modulator Data Register Mark Low, offset: 0x7
| __IO uint8_t CMT_Type::CMD3 |
CMT Modulator Data Register Space High, offset: 0x8
| __IO uint8_t CMT_Type::CMD4 |
CMT Modulator Data Register Space Low, offset: 0x9
| __IO uint32_t SDHC_Type::CMDARG |
Command Argument register, offset: 0x8
Command Argument Register, offset: 0x8
| __I uint32_t SDHC_Type::CMDRSP |
Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4
| __IO uint8_t EWM_Type::CMPH |
Compare High Register, offset: 0x3
| __IO uint8_t EWM_Type::CMPL |
Compare Low Register, offset: 0x2
| __IO uint32_t LPTMR_Type::CMR |
Low Power Timer Compare Register, offset: 0x8
| __IO uint32_t LPTMR_Type::CNR |
Low Power Timer Counter Register, offset: 0xC
| __IO uint32_t { ... } ::CnSC |
Channel (n) Status And Control, array offset: 0xC, array step: 0x8
| __IO uint32_t FTM_Type::CnSC |
Channel (n) Status And Control, array offset: 0xC, array step: 0x8
Channel (n) Status and Control, array offset: 0xC, array step: 0x8
| __IO uint32_t FTM_Type::CNT |
Counter, offset: 0x4
| __I uint32_t PDB_Type::CNT |
Counter Register, offset: 0x8
Counter register, offset: 0x8
| __IO uint32_t FTM_Type::CNTIN |
Counter Initial Value, offset: 0x4C
| __I uint32_t TSI_Type::CNTR1 |
Counter Register, offset: 0x100
| __I uint32_t TSI_Type::CNTR11 |
Counter Register, offset: 0x114
| __I uint32_t TSI_Type::CNTR13 |
Counter Register, offset: 0x118
| __I uint32_t TSI_Type::CNTR15 |
Counter Register, offset: 0x11C
| __I uint32_t TSI_Type::CNTR3 |
Counter Register, offset: 0x104
| __I uint32_t TSI_Type::CNTR5 |
Counter Register, offset: 0x108
| __I uint32_t TSI_Type::CNTR7 |
Counter Register, offset: 0x10C
| __I uint32_t TSI_Type::CNTR9 |
Counter Register, offset: 0x110
| __IO uint32_t FTM_Type::CnV |
Channel (n) Value, array offset: 0x10, array step: 0x8
| __IO uint32_t { ... } ::CnV |
Channel (n) Value, array offset: 0x10, array step: 0x8
| __IO uint32_t FTM_Type::COMBINE |
Function For Linked Channels, offset: 0x64
Function for Linked Channels, offset: 0x64
| __IO uint32_t FTM_Type::CONF |
Configuration, offset: 0x84
| __IO uint8_t USB_Type::CONTROL |
USB OTG Control register, offset: 0x108
USB OTG Control Register, offset: 0x108
| __IO uint32_t USBDCD_Type::CONTROL |
Control register, offset: 0x0
Control Register, offset: 0x0
| __IO uint8_t UART_Type::CPW |
UART CEA709.1-B Collision Pulse Width, offset: 0x2F
| __IO uint32_t DMA_Type::CR |
Control Register, offset: 0x0
| __IO uint32_t MCM_Type::CR |
Control Register, offset: 0xC
| __IO uint8_t OSC_Type::CR |
OSC Control Register, offset: 0x0
| __IO uint32_t RNG_Type::CR |
RNGA Control Register, offset: 0x0
RNGB Control Register, offset: 0x8
| __IO uint32_t RTC_Type::CR |
RTC Control Register, offset: 0x10
| __IO uint8_t CMP_Type::CR0 |
CMP Control Register 0, offset: 0x0
| __IO uint8_t CMP_Type::CR1 |
CMP Control Register 1, offset: 0x1
| __IO uint32_t { ... } ::CRC |
CRC Data register, offset: 0x0
| __IO uint32_t CRC_Type::CRC |
CRC Data register, offset: 0x0
CRC Data Register, offset: 0x0
| __IO uint16_t { ... } ::CRCH |
CRC_CRCH register., offset: 0x2
| __IO uint16_t CRC_Type::CRCH |
CRC_CRCH register., offset: 0x2
| __IO uint8_t CRC_Type::CRCHL |
CRC_CRCHL register., offset: 0x2
| __IO uint8_t { ... } ::CRCHL |
CRC_CRCHL register., offset: 0x2
| __IO uint8_t CRC_Type::CRCHU |
CRC_CRCHU register., offset: 0x3
| __IO uint8_t { ... } ::CRCHU |
CRC_CRCHU register., offset: 0x3
| __IO uint16_t { ... } ::CRCL |
CRC_CRCL register., offset: 0x0
| __IO uint16_t CRC_Type::CRCL |
CRC_CRCL register., offset: 0x0
| __IO uint8_t { ... } ::CRCLL |
CRC_CRCLL register., offset: 0x0
| __IO uint8_t CRC_Type::CRCLL |
CRC_CRCLL register., offset: 0x0
| __IO uint8_t { ... } ::CRCLU |
CRC_CRCLU register., offset: 0x1
| __IO uint8_t CRC_Type::CRCLU |
CRC_CRCLU register., offset: 0x1
| __I uint32_t CAN_Type::CRCR |
CRC Register, offset: 0x44
| __IO uint32_t { ... } ::CRS |
Control Register, array offset: 0x10, array step: 0x100
| __IO uint32_t AXBS_Type::CRS |
Control Register, array offset: 0x10, array step: 0x100
| __IO uint32_t { ... } ::CS |
Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t CAN_Type::CS |
Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10
| __IO uint32_t { ... } ::CSAR |
Chip Select Address Register, array offset: 0x0, array step: 0xC
| __IO uint32_t FB_Type::CSAR |
Chip Select Address Register, array offset: 0x0, array step: 0xC
Chip select address register, array offset: 0x0, array step: 0xC
| __IO uint32_t FB_Type::CSCR |
Chip Select Control Register, array offset: 0x8, array step: 0xC
Chip select control register, array offset: 0x8, array step: 0xC
| __IO uint32_t { ... } ::CSCR |
Chip Select Control Register, array offset: 0x8, array step: 0xC
| __IO uint32_t { ... } ::CSMR |
Chip Select Mask Register, array offset: 0x4, array step: 0xC
| __IO uint32_t FB_Type::CSMR |
Chip Select Mask Register, array offset: 0x4, array step: 0xC
Chip select mask register, array offset: 0x4, array step: 0xC
| __IO uint32_t FB_Type::CSPMCR |
Chip Select port Multiplexing Control Register, offset: 0x60
Chip select port multiplexing control register, offset: 0x60
| __IO uint16_t DMA_Type::CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20
| __IO uint16_t { ... } ::CSR |
TCD Control and Status, array offset: 0x101C, array step: 0x20
| __IO uint32_t LPTMR_Type::CSR |
Low Power Timer Control Status Register, offset: 0x0
| __IO uint32_t { ... } ::CTAR[2] |
DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t SPI_Type::CTAR[2] |
DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4
Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t { ... } ::CTAR_SLAVE[1] |
Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4
| __IO uint32_t SPI_Type::CTAR_SLAVE[1] |
Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4
DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4
| __IO uint8_t USB_Type::CTL |
Control register, offset: 0x94
Control Register, offset: 0x94
| __IO uint32_t { ... } ::CTRL |
CRC Control register, offset: 0x8
| __IO uint32_t CRC_Type::CTRL |
CRC Control register, offset: 0x8
CRC Control Register, offset: 0x8
| __IO uint8_t EWM_Type::CTRL |
Control Register, offset: 0x0
| __IO uint32_t CAN_Type::CTRL1 |
Control 1 register, offset: 0x4
Control 1 Register, offset: 0x4
| __IO uint32_t CAN_Type::CTRL2 |
Control 2 register, offset: 0x34
Control 2 Register, offset: 0x34
| __IO uint8_t { ... } ::CTRLHU |
CRC_CTRLHU register., offset: 0xB
| __IO uint8_t CRC_Type::CTRLHU |
CRC_CTRLHU register., offset: 0xB
| __IO uint32_t ADC_Type::CV1 |
Compare Value Registers, offset: 0x18
Compare value registers, offset: 0x18
| __IO uint32_t ADC_Type::CV2 |
Compare Value Registers, offset: 0x1C
Compare value registers, offset: 0x1C
| __I uint32_t PIT_Type::CVAL |
Current Timer Value Register, array offset: 0x104, array step: 0x10
| __I uint32_t { ... } ::CVAL |
Current Timer Value Register, array offset: 0x104, array step: 0x10
| __IO uint8_t I2C_Type::D |
I2C Data I/O register, offset: 0x4
| __IO uint8_t UART_Type::D |
UART Data Register, offset: 0x7
| __IO uint8_t CMP_Type::DACCR |
DAC Control Register, offset: 0x4
| __IO uint32_t DMA_Type::DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20
| __IO uint32_t { ... } ::DADDR |
TCD Destination Address, array offset: 0x1010, array step: 0x20
| __IO uint32_t { ... } ::DATA_L |
Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8
| __IO uint32_t FMC_Type::DATA_L |
Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8
Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8
| __IO uint32_t { ... } ::DATA_U |
Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8
| __IO uint32_t FMC_Type::DATA_U |
Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8
Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8
| __IO uint8_t DAC_Type::DATH |
DAC Data High Register, array offset: 0x1, array step: 0x2
| __IO uint8_t { ... } ::DATH |
DAC Data High Register, array offset: 0x1, array step: 0x2
| __IO uint8_t DAC_Type::DATL |
DAC Data Low Register, array offset: 0x0, array step: 0x2
| __IO uint8_t { ... } ::DATL |
DAC Data Low Register, array offset: 0x0, array step: 0x2
| __IO uint32_t SDHC_Type::DATPORT |
Buffer Data Port register, offset: 0x20
Buffer Data Port Register, offset: 0x20
| __IO uint8_t DMA_Type::DCHPRI0 |
Channel n Priority Register, offset: 0x103
| __IO uint8_t DMA_Type::DCHPRI1 |
Channel n Priority Register, offset: 0x102
| __IO uint8_t DMA_Type::DCHPRI10 |
Channel n Priority Register, offset: 0x109
| __IO uint8_t DMA_Type::DCHPRI11 |
Channel n Priority Register, offset: 0x108
| __IO uint8_t DMA_Type::DCHPRI12 |
Channel n Priority Register, offset: 0x10F
| __IO uint8_t DMA_Type::DCHPRI13 |
Channel n Priority Register, offset: 0x10E
| __IO uint8_t DMA_Type::DCHPRI14 |
Channel n Priority Register, offset: 0x10D
| __IO uint8_t DMA_Type::DCHPRI15 |
Channel n Priority Register, offset: 0x10C
| __IO uint8_t DMA_Type::DCHPRI2 |
Channel n Priority Register, offset: 0x101
| __IO uint8_t DMA_Type::DCHPRI3 |
Channel n Priority Register, offset: 0x100
| __IO uint8_t DMA_Type::DCHPRI4 |
Channel n Priority Register, offset: 0x107
| __IO uint8_t DMA_Type::DCHPRI5 |
Channel n Priority Register, offset: 0x106
| __IO uint8_t DMA_Type::DCHPRI6 |
Channel n Priority Register, offset: 0x105
| __IO uint8_t DMA_Type::DCHPRI7 |
Channel n Priority Register, offset: 0x104
| __IO uint8_t DMA_Type::DCHPRI8 |
Channel n Priority Register, offset: 0x10B
| __IO uint8_t DMA_Type::DCHPRI9 |
Channel n Priority Register, offset: 0x10A
| __IO uint32_t FTM_Type::DEADTIME |
Deadtime Insertion Control, offset: 0x68
| __IO uint32_t PORT_Type::DFCR |
Digital Filter Clock Register, offset: 0xC4
| __IO uint32_t PORT_Type::DFER |
Digital Filter Enable Register, offset: 0xC0
| __IO uint32_t PORT_Type::DFWR |
Digital Filter Width Register, offset: 0xC8
| __O uint32_t CAU_Type::DIRECT |
Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4
| __IO uint32_t DMA_Type::DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
| __IO uint32_t { ... } ::DLAST_SGA |
TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
| __IO uint32_t { ... } ::DLY[2] |
Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4
| __IO uint32_t PDB_Type::DLY[2] |
Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4
Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4
| __IO uint8_t CMT_Type::DMA |
CMT Direct Memory Access Register, offset: 0xB
CMT Direct Memory Access, offset: 0xB
| __IO uint16_t DMA_Type::DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
| __IO uint16_t { ... } ::DOFF |
TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
| __IO uint32_t SDHC_Type::DSADDR |
DMA System Address register, offset: 0x0
DMA System Address Register, offset: 0x0
| __I uint32_t { ... } ::EAR |
Error Address Register, slave port n, array offset: 0x10, array step: 0x8
| __I uint32_t SYSMPU_Type::EAR |
Error Address Register, slave port n, array offset: 0x10, array step: 0x8
| __IO uint32_t CAN_Type::ECR |
Error Counter, offset: 0x1C
| __IO uint32_t ENET_Type::ECR |
Ethernet Control Register, offset: 0x24
| __I uint8_t UART_Type::ED |
UART Extended Data Register, offset: 0xC
| __I uint32_t SYSMPU_Type::EDR |
Error Detail Register, slave port n, array offset: 0x14, array step: 0x8
| __I uint32_t { ... } ::EDR |
Error Detail Register, slave port n, array offset: 0x14, array step: 0x8
| __IO uint32_t DMA_Type::EEI |
Enable Error Interrupt Register, offset: 0x14
| __IO uint32_t ENET_Type::EIMR |
Interrupt Mask Register, offset: 0x8
| __IO uint32_t ENET_Type::EIR |
Interrupt Event Register, offset: 0x4
| __IO uint8_t USB_Type::ENDPT |
Endpoint Control register, array offset: 0xC0, array step: 0x4
Endpoint Control Register, array offset: 0xC0, array step: 0x4
| __IO uint8_t { ... } ::ENDPT |
Endpoint Control register, array offset: 0xC0, array step: 0x4
| __O uint32_t RNG_Type::ER |
RNGA Entropy Register, offset: 0x8
| __IO uint32_t DMA_Type::ERQ |
Enable Request Register, offset: 0xC
| __IO uint32_t DMA_Type::ERR |
Error Register, offset: 0x2C
| __IO uint8_t USB_Type::ERREN |
Error Interrupt Enable register, offset: 0x8C
Error Interrupt Enable Register, offset: 0x8C
| __IO uint8_t USB_Type::ERRSTAT |
Error Interrupt Status register, offset: 0x88
Error Interrupt Status Register, offset: 0x88
| __I uint32_t DMA_Type::ES |
Error Status Register, offset: 0x4
| __IO uint32_t CAN_Type::ESR1 |
Error and Status 1 register, offset: 0x20
Error and Status 1 Register, offset: 0x20
| __I uint32_t CAN_Type::ESR2 |
Error and Status 2 register, offset: 0x38
Error and Status 2 Register, offset: 0x38
| __IO uint8_t UART_Type::ET7816 |
UART 7816 Error Threshold Register, offset: 0x1E
| __IO uint32_t MCM_Type::ETBCC |
ETB Counter Control register, offset: 0x14
ETB counter control register, offset: 0x14
| __I uint32_t MCM_Type::ETBCNT |
ETB Counter Value register, offset: 0x1C
ETB counter value register, offset: 0x1C
| __IO uint32_t MCM_Type::ETBRL |
ETB Reload register, offset: 0x18
ETB reload register, offset: 0x18
| __IO uint32_t FTM_Type::EXTTRIG |
FTM External Trigger, offset: 0x6C
| __IO uint8_t I2C_Type::F |
I2C Frequency Divider register, offset: 0x1
| __IO uint8_t LLWU_Type::F1 |
LLWU Flag 1 register, offset: 0x5
LLWU Flag 1 Register, offset: 0x5
| __IO uint8_t LLWU_Type::F2 |
LLWU Flag 2 register, offset: 0x6
LLWU Flag 2 Register, offset: 0x6
| __I uint8_t LLWU_Type::F3 |
LLWU Flag 3 register, offset: 0x7
| __IO uint8_t FTFL_Type::FCCOB0 |
Flash Common Command Object Registers, offset: 0x7
| __IO uint8_t FTFL_Type::FCCOB1 |
Flash Common Command Object Registers, offset: 0x6
| __IO uint8_t FTFL_Type::FCCOB2 |
Flash Common Command Object Registers, offset: 0x5
| __IO uint8_t FTFL_Type::FCCOB3 |
Flash Common Command Object Registers, offset: 0x4
| __IO uint8_t FTFL_Type::FCCOB4 |
Flash Common Command Object Registers, offset: 0xB
| __IO uint8_t FTFL_Type::FCCOB5 |
Flash Common Command Object Registers, offset: 0xA
| __IO uint8_t FTFL_Type::FCCOB6 |
Flash Common Command Object Registers, offset: 0x9
| __IO uint8_t FTFL_Type::FCCOB7 |
Flash Common Command Object Registers, offset: 0x8
| __IO uint8_t FTFL_Type::FCCOB8 |
Flash Common Command Object Registers, offset: 0xF
| __IO uint8_t FTFL_Type::FCCOB9 |
Flash Common Command Object Registers, offset: 0xE
| __IO uint8_t FTFL_Type::FCCOBA |
Flash Common Command Object Registers, offset: 0xD
| __IO uint8_t FTFL_Type::FCCOBB |
Flash Common Command Object Registers, offset: 0xC
| __IO uint32_t SIM_Type::FCFG1 |
Flash Configuration Register 1, offset: 0x104C
| __I uint32_t SIM_Type::FCFG2 |
Flash Configuration Register 2, offset: 0x1050
| __IO uint8_t FTFL_Type::FCNFG |
Flash Configuration Register, offset: 0x1
| __IO uint8_t FTFL_Type::FDPROT |
Data Flash Protection Register, offset: 0x17
| __I uint8_t NV_Type::FDPROT |
Non-volatile D-Flash Protection Register, offset: 0xF
| __IO uint8_t FTFL_Type::FEPROT |
EEPROM Protection Register, offset: 0x16
| __I uint8_t NV_Type::FEPROT |
Non-volatile EERAM Protection Register, offset: 0xE
| __O uint32_t SDHC_Type::FEVT |
Force Event register, offset: 0x50
Force Event Register, offset: 0x50
| __IO uint8_t LLWU_Type::FILT1 |
LLWU Pin Filter 1 register, offset: 0x8
LLWU Pin Filter 1 register, offset: 0xE
| __IO uint8_t LLWU_Type::FILT2 |
LLWU Pin Filter 2 register, offset: 0x9
LLWU Pin Filter 2 register, offset: 0xF
| __IO uint32_t FTM_Type::FILTER |
Input Capture Filter Control, offset: 0x78
| __IO uint8_t I2C_Type::FLT |
I2C Programmable Input Glitch Filter register, offset: 0x6
I2C Programmable Input Glitch Filter Register, offset: 0x6
| __IO uint32_t FTM_Type::FLTCTRL |
Fault Control, offset: 0x7C
| __IO uint32_t FTM_Type::FLTPOL |
FTM Fault Input Polarity, offset: 0x88
| __IO uint32_t FTM_Type::FMS |
Fault Mode Status, offset: 0x74
| __I uint8_t FTFL_Type::FOPT |
Flash Option Register, offset: 0x3
| __I uint8_t NV_Type::FOPT |
Non-volatile Flash Option Register, offset: 0xD
| __IO uint8_t CMP_Type::FPR |
CMP Filter Period Register, offset: 0x2
| __IO uint8_t FTFL_Type::FPROT0 |
Program Flash Protection Registers, offset: 0x13
| __I uint8_t NV_Type::FPROT0 |
Non-volatile P-Flash Protection 0 - High Register, offset: 0xB
| __IO uint8_t FTFL_Type::FPROT1 |
Program Flash Protection Registers, offset: 0x12
| __I uint8_t NV_Type::FPROT1 |
Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA
| __IO uint8_t FTFL_Type::FPROT2 |
Program Flash Protection Registers, offset: 0x11
| __I uint8_t NV_Type::FPROT2 |
Non-volatile P-Flash Protection 1 - High Register, offset: 0x9
| __IO uint8_t FTFL_Type::FPROT3 |
Program Flash Protection Registers, offset: 0x10
| __I uint8_t NV_Type::FPROT3 |
Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8
| __IO uint8_t USB_Type::FRMNUMH |
Frame Number Register High, offset: 0xA4
Frame Number register High, offset: 0xA4
| __IO uint8_t USB_Type::FRMNUML |
Frame Number Register Low, offset: 0xA0
Frame Number register Low, offset: 0xA0
| __I uint8_t FTFL_Type::FSEC |
Flash Security Register, offset: 0x2
| __I uint8_t NV_Type::FSEC |
Non-volatile Flash Security Register, offset: 0xC
| __IO uint8_t FTFL_Type::FSTAT |
Flash Status Register, offset: 0x0
| __IO uint32_t ENET_Type::FTRL |
Frame Truncation Length, offset: 0x1B0
| __IO uint32_t ENET_Type::GALR |
Descriptor Group Lower Address Register, offset: 0x124
| __IO uint32_t ENET_Type::GAUR |
Descriptor Group Upper Address Register, offset: 0x120
| __IO uint32_t TSI_Type::GENCS |
General Control and Status register, offset: 0x0
General Control and Status Register, offset: 0x0
TSI General Control and Status Register, offset: 0x0
| __O uint32_t PORT_Type::GPCHR |
Global Pin Control High Register, offset: 0x84
| __O uint32_t PORT_Type::GPCLR |
Global Pin Control Low Register, offset: 0x80
| __IO uint32_t { ... } ::GPOLY |
CRC Polynomial register, offset: 0x4
| __IO uint32_t CRC_Type::GPOLY |
CRC Polynomial register, offset: 0x4
CRC Polynomial Register, offset: 0x4
| __IO uint16_t CRC_Type::GPOLYH |
CRC_GPOLYH register., offset: 0x6
| __IO uint16_t { ... } ::GPOLYH |
CRC_GPOLYH register., offset: 0x6
| __IO uint8_t { ... } ::GPOLYHL |
CRC_GPOLYHL register., offset: 0x6
| __IO uint8_t CRC_Type::GPOLYHL |
CRC_GPOLYHL register., offset: 0x6
| __IO uint8_t CRC_Type::GPOLYHU |
CRC_GPOLYHU register., offset: 0x7
| __IO uint8_t { ... } ::GPOLYHU |
CRC_GPOLYHU register., offset: 0x7
| __IO uint16_t { ... } ::GPOLYL |
CRC_GPOLYL register., offset: 0x4
| __IO uint16_t CRC_Type::GPOLYL |
CRC_GPOLYL register., offset: 0x4
| __IO uint8_t { ... } ::GPOLYLL |
CRC_GPOLYLL register., offset: 0x4
| __IO uint8_t CRC_Type::GPOLYLL |
CRC_GPOLYLL register., offset: 0x4
| __IO uint8_t { ... } ::GPOLYLU |
CRC_GPOLYLU register., offset: 0x5
| __IO uint8_t CRC_Type::GPOLYLU |
CRC_GPOLYLU register., offset: 0x5
| __I uint32_t SDHC_Type::HOSTVER |
Host Controller Version, offset: 0xFC
| __I uint32_t DMA_Type::HRS |
Hardware Request Status Register, offset: 0x34
| __I uint32_t SDHC_Type::HTCAPBLT |
Host Controller Capabilities, offset: 0x40
| __IO uint32_t ENET_Type::IALR |
Descriptor Individual Lower Address Register, offset: 0x11C
| __IO uint32_t ENET_Type::IAUR |
Descriptor Individual Upper Address Register, offset: 0x118
| __IO uint32_t CAN_Type::ID |
Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10
| __IO uint32_t { ... } ::ID |
Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10
| __I uint8_t USB_Type::IDCOMP |
Peripheral ID Complement register, offset: 0x4
Peripheral ID Complement Register, offset: 0x4
| __IO uint32_t PDB_Type::IDLY |
Interrupt Delay Register, offset: 0xC
Interrupt Delay register, offset: 0xC
| __IO uint8_t UART_Type::IE |
UART CEA709.1-B Interrupt Enable Register, offset: 0x29
| __IO uint8_t UART_Type::IE7816 |
UART 7816 Interrupt Enable Register, offset: 0x19
| __I uint32_t ENET_Type::IEEE_R_ALIGN |
Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4
Frames Received with Alignment Error Statistic Register, offset: 0x2D4
| __I uint32_t ENET_Type::IEEE_R_CRC |
Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0
Frames Received with CRC Error Statistic Register, offset: 0x2D0
| __I uint32_t ENET_Type::IEEE_R_DROP |
Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8
Frames not Counted Correctly Statistic Register, offset: 0x2C8
| __I uint32_t ENET_Type::IEEE_R_FDXFC |
Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC
Flow Control Pause Frames Received Statistic Register, offset: 0x2DC
| __I uint32_t ENET_Type::IEEE_R_FRAME_OK |
Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC
Frames Received OK Statistic Register, offset: 0x2CC
| __I uint32_t ENET_Type::IEEE_R_MACERR |
Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8
Receive FIFO Overflow Count Statistic Register, offset: 0x2D8
| __I uint32_t ENET_Type::IEEE_R_OCTETS_OK |
Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0
Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0
| __I uint32_t ENET_Type::IEEE_T_1COL |
Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250
Frames Transmitted with Single Collision Statistic Register, offset: 0x250
| __I uint32_t ENET_Type::IEEE_T_CSERR |
Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268
Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268
| __I uint32_t ENET_Type::IEEE_T_DEF |
Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258
Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258
| uint32_t ENET_Type::IEEE_T_DROP |
Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248
IEEE_T_DROP Reserved Statistic Register, offset: 0x248
Reserved Statistic Register, offset: 0x248
| __I uint32_t ENET_Type::IEEE_T_EXCOL |
Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260
Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260
| __I uint32_t ENET_Type::IEEE_T_FDXFC |
Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270
Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270
| __I uint32_t ENET_Type::IEEE_T_FRAME_OK |
Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C
Frames Transmitted OK Statistic Register, offset: 0x24C
| __I uint32_t ENET_Type::IEEE_T_LCOL |
Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C
Frames Transmitted with Late Collision Statistic Register, offset: 0x25C
| __I uint32_t ENET_Type::IEEE_T_MACERR |
Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264
Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264
| __I uint32_t ENET_Type::IEEE_T_MCOL |
Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254
Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254
| __I uint32_t ENET_Type::IEEE_T_OCTETS_OK |
Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274
Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274
| __I uint32_t ENET_Type::IEEE_T_SQE |
Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C
, offset: 0x26C
Reserved Statistic Register, offset: 0x26C
| __IO uint32_t RTC_Type::IER |
RTC Interrupt Enable Register, offset: 0x1C
| __IO uint32_t CAN_Type::IFLAG1 |
Interrupt Flags 1 register, offset: 0x30
Interrupt Flags 1 Register, offset: 0x30
| __IO uint32_t CAN_Type::IMASK1 |
Interrupt Masks 1 register, offset: 0x28
Interrupt Masks 1 Register, offset: 0x28
| __IO uint32_t DMA_Type::INT |
Interrupt Request Register, offset: 0x24
| __IO uint32_t { ... } ::INT |
DAC Interval n Register, array offset: 0x154, array step: 0x8
| __IO uint32_t PDB_Type::INT |
DAC Interval n Register, array offset: 0x154, array step: 0x8
DAC Interval n register, array offset: 0x154, array step: 0x8
| __IO uint32_t { ... } ::INTC |
DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8
| __IO uint32_t PDB_Type::INTC |
DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8
DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8
| __IO uint8_t USB_Type::INTEN |
Interrupt Enable register, offset: 0x84
Interrupt Enable Register, offset: 0x84
| __IO uint32_t FTM_Type::INVCTRL |
FTM Inverting Control, offset: 0x90
| __IO uint8_t UART_Type::IR |
UART Infrared Register, offset: 0xE
| __IO uint32_t SDHC_Type::IRQSIGEN |
Interrupt Signal Enable register, offset: 0x38
Interrupt Signal Enable Register, offset: 0x38
| __IO uint32_t SDHC_Type::IRQSTAT |
Interrupt Status register, offset: 0x30
Interrupt Status Register, offset: 0x30
| __IO uint32_t SDHC_Type::IRQSTATEN |
Interrupt Status Enable register, offset: 0x34
Interrupt Status Enable Register, offset: 0x34
| __IO uint8_t UART_Type::IS7816 |
UART 7816 Interrupt Status Register, offset: 0x1A
| __IO uint32_t PORT_Type::ISFR |
Interrupt Status Flag Register, offset: 0xA0
| __IO uint32_t MCM_Type::ISR |
Interrupt Status Register, offset: 0x10
Interrupt status register, offset: 0x10
| __IO uint8_t USB_Type::ISTAT |
Interrupt Status register, offset: 0x80
Interrupt Status Register, offset: 0x80
| __O uint32_t CAU_Type::LDR_CA |
General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4
| __O uint32_t CAU_Type::LDR_CAA |
Accumulator register - Load Register command, offset: 0x844
| __O uint32_t CAU_Type::LDR_CASR |
Status register - Load Register command, offset: 0x840
| __IO uint32_t PIT_Type::LDVAL |
Timer Load Value Register, array offset: 0x100, array step: 0x10
| __IO uint32_t { ... } ::LDVAL |
Timer Load Value Register, array offset: 0x100, array step: 0x10
| __IO uint32_t RTC_Type::LR |
RTC Lock Register, offset: 0x18
| __IO uint8_t PMC_Type::LVDSC1 |
Low Voltage Detect Status And Control 1 register, offset: 0x0
Low Voltage Detect Status and Control 1 Register, offset: 0x0
| __IO uint8_t PMC_Type::LVDSC2 |
Low Voltage Detect Status And Control 2 register, offset: 0x1
Low Voltage Detect Status and Control 2 Register, offset: 0x1
| __IO uint8_t UART_Type::MA1 |
UART Match Address Registers 1, offset: 0x8
| __IO uint8_t UART_Type::MA2 |
UART Match Address Registers 2, offset: 0x9
| __IO uint32_t CAN_Type::MCR |
Module Configuration Register, offset: 0x0
| __IO uint32_t I2S_Type::MCR |
SAI MCLK Control Register, offset: 0x100
| __IO uint32_t PIT_Type::MCR |
PIT Module Control Register, offset: 0x0
| __IO uint32_t SPI_Type::MCR |
Module Configuration Register, offset: 0x0
DSPI Module Configuration Register, offset: 0x0
| __IO uint32_t I2S_Type::MDR |
SAI MCLK Divide Register, offset: 0x104
| __IO uint8_t LLWU_Type::ME |
LLWU Module Enable register, offset: 0x4
LLWU Module Enable Register, offset: 0x4
LLWU Module Enable register, offset: 0x8
| __IO uint32_t ADC_Type::MG |
ADC Minus-Side Gain Register, offset: 0x30
ADC minus-side gain register, offset: 0x30
| __IO uint32_t AXBS_Type::MGPCR0 |
Master General Purpose Control Register, offset: 0x800
| __IO uint32_t AXBS_Type::MGPCR1 |
Master General Purpose Control Register, offset: 0x900
| __IO uint32_t AXBS_Type::MGPCR2 |
Master General Purpose Control Register, offset: 0xA00
| __IO uint32_t AXBS_Type::MGPCR3 |
Master General Purpose Control Register, offset: 0xB00
| __IO uint32_t AXBS_Type::MGPCR4 |
Master General Purpose Control Register, offset: 0xC00
| __IO uint32_t AXBS_Type::MGPCR5 |
Master General Purpose Control Register, offset: 0xD00
| __IO uint32_t ENET_Type::MIBC |
MIB Control Register, offset: 0x64
| __IO uint32_t SDHC_Type::MMCBOOT |
MMC Boot register, offset: 0xC4
MMC Boot Register, offset: 0xC4
| __IO uint32_t ENET_Type::MMFR |
MII Management Frame Register, offset: 0x40
| __IO uint32_t FTM_Type::MOD |
Modulo, offset: 0x8
| __IO uint32_t PDB_Type::MOD |
Modulus Register, offset: 0x4
Modulus register, offset: 0x4
| __IO uint32_t FTM_Type::MODE |
Features Mode Selection, offset: 0x54
| __IO uint8_t UART_Type::MODEM |
UART Modem Register, offset: 0xD
| __IO uint32_t AIPS_Type::MPRA |
Master Privilege Register A, offset: 0x0
| __I uint8_t RCM_Type::MR |
Mode Register, offset: 0x7
| __IO uint32_t ENET_Type::MRBR |
Maximum Receive Buffer Size Register, offset: 0x188
| __IO uint8_t CMT_Type::MSC |
CMT Modulator Status and Control Register, offset: 0x5
| __IO uint32_t ENET_Type::MSCR |
MII Speed Control Register, offset: 0x44
| __IO uint8_t CMP_Type::MUXCR |
MUX Control Register, offset: 0x5
| __IO uint32_t DMA_Type::NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20
TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLNO |
TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t DMA_Type::NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFNO |
TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t { ... } ::NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20
| __IO uint32_t DMA_Type::NBYTES_MLOFFYES |
TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20
| __I uint8_t USB_Type::OBSERVE |
USB OTG Observe register, offset: 0x104
USB OTG Observe Register, offset: 0x104
| __IO uint8_t CMT_Type::OC |
CMT Output Control Register, offset: 0x4
| __IO uint32_t ADC_Type::OFS |
ADC Offset Correction Register, offset: 0x28
ADC offset correction register, offset: 0x28
| __IO uint32_t ENET_Type::OPD |
Opcode/Pause Duration Register, offset: 0xEC
| __I uint32_t RNG_Type::OR |
RNGA Output Register, offset: 0xC
| __IO uint8_t USB_Type::OTGCTL |
OTG Control register, offset: 0x1C
OTG Control Register, offset: 0x1C
| __IO uint8_t USB_Type::OTGICR |
OTG Interrupt Control Register, offset: 0x14
OTG Interrupt Control register, offset: 0x14
| __IO uint8_t USB_Type::OTGISTAT |
OTG Interrupt Status register, offset: 0x10
OTG Interrupt Status Register, offset: 0x10
| __IO uint8_t USB_Type::OTGSTAT |
OTG Status register, offset: 0x18
OTG Status Register, offset: 0x18
| __IO uint32_t FTM_Type::OUTINIT |
Initial State For Channels Output, offset: 0x5C
Initial State for Channels Output, offset: 0x5C
| __IO uint32_t FTM_Type::OUTMASK |
Output Mask, offset: 0x60
| __IO uint32_t AIPS_Type::PACRA |
Peripheral Access Control Register, offset: 0x20
| __IO uint32_t AIPS_Type::PACRB |
Peripheral Access Control Register, offset: 0x24
| __IO uint32_t AIPS_Type::PACRC |
Peripheral Access Control Register, offset: 0x28
| __IO uint32_t AIPS_Type::PACRD |
Peripheral Access Control Register, offset: 0x2C
| __IO uint32_t AIPS_Type::PACRE |
Peripheral Access Control Register, offset: 0x40
| __IO uint32_t AIPS_Type::PACRF |
Peripheral Access Control Register, offset: 0x44
| __IO uint32_t AIPS_Type::PACRG |
Peripheral Access Control Register, offset: 0x48
| __IO uint32_t AIPS_Type::PACRH |
Peripheral Access Control Register, offset: 0x4C
| __IO uint32_t AIPS_Type::PACRI |
Peripheral Access Control Register, offset: 0x50
| __IO uint32_t AIPS_Type::PACRJ |
Peripheral Access Control Register, offset: 0x54
| __IO uint32_t AIPS_Type::PACRK |
Peripheral Access Control Register, offset: 0x58
| __IO uint32_t AIPS_Type::PACRL |
Peripheral Access Control Register, offset: 0x5C
| __IO uint32_t AIPS_Type::PACRM |
Peripheral Access Control Register, offset: 0x60
| __IO uint32_t AIPS_Type::PACRN |
Peripheral Access Control Register, offset: 0x64
| __IO uint32_t AIPS_Type::PACRO |
Peripheral Access Control Register, offset: 0x68
| __IO uint32_t AIPS_Type::PACRP |
Peripheral Access Control Register, offset: 0x6C
| __IO uint32_t ENET_Type::PALR |
Physical Address Lower Register, offset: 0xE4
| __IO uint32_t ENET_Type::PAUR |
Physical Address Upper Register, offset: 0xE8
| __O uint32_t GPIO_Type::PCOR |
Port Clear Output Register, offset: 0x8
| __IO uint32_t PORT_Type::PCR |
Pin Control Register n, array offset: 0x0, array step: 0x4
| __IO uint8_t UART_Type::PCTH |
UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22
| __IO uint8_t UART_Type::PCTL |
UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23
| __IO uint32_t GPIO_Type::PDDR |
Port Data Direction Register, offset: 0x14
| __I uint32_t GPIO_Type::PDIR |
Port Data Input Register, offset: 0x10
| __IO uint32_t GPIO_Type::PDOR |
Port Data Output Register, offset: 0x0
| __IO uint8_t LLWU_Type::PE1 |
LLWU Pin Enable 1 register, offset: 0x0
LLWU Pin Enable 1 Register, offset: 0x0
| __IO uint8_t LLWU_Type::PE2 |
LLWU Pin Enable 2 register, offset: 0x1
LLWU Pin Enable 2 Register, offset: 0x1
| __IO uint8_t LLWU_Type::PE3 |
LLWU Pin Enable 3 register, offset: 0x2
LLWU Pin Enable 3 Register, offset: 0x2
| __IO uint8_t LLWU_Type::PE4 |
LLWU Pin Enable 4 register, offset: 0x3
LLWU Pin Enable 4 Register, offset: 0x3
| __IO uint32_t TSI_Type::PEN |
Pin Enable register, offset: 0x8
Pin enable register, offset: 0x8
| __I uint8_t USB_Type::PERID |
Peripheral ID register, offset: 0x0
Peripheral ID Register, offset: 0x0
| __IO uint32_t FMC_Type::PFAPR |
Flash Access Protection Register, offset: 0x0
| __IO uint32_t FMC_Type::PFB0CR |
Flash Bank 0 Control Register, offset: 0x4
| __IO uint32_t FMC_Type::PFB1CR |
Flash Bank 1 Control Register, offset: 0x8
| __IO uint8_t UART_Type::PFIFO |
UART FIFO Parameters, offset: 0x10
| __IO uint32_t ADC_Type::PG |
ADC Plus-Side Gain Register, offset: 0x2C
ADC plus-side gain register, offset: 0x2C
| __IO uint32_t ADC_Type::PGA |
ADC PGA Register, offset: 0x50
ADC PGA register, offset: 0x50
| __IO uint32_t MCM_Type::PID |
Process ID register, offset: 0x30
| __I uint16_t MCM_Type::PLAMC |
Crossbar Switch (AXBS) Master Configuration, offset: 0xA
Crossbar switch (AXBS) master configuration, offset: 0xA
| __I uint16_t MCM_Type::PLASC |
Crossbar Switch (AXBS) Slave Configuration, offset: 0x8
Crossbar switch (AXBS) slave configuration, offset: 0x8
| __IO uint8_t SMC_Type::PMCTRL |
Power Mode Control register, offset: 0x1
| __IO uint8_t SMC_Type::PMPROT |
Power Mode Protection register, offset: 0x0
| __I uint8_t SMC_Type::PMSTAT |
Power Mode Status register, offset: 0x3
| __IO uint32_t PDB_Type::PODLY |
Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4
Pulse-Out n Delay Register, offset: 0x194
Pulse-Out n Delay register, array offset: 0x194, array step: 0x4
| __IO uint32_t PDB_Type::POEN |
Pulse-Out n Enable Register, offset: 0x190
Pulse-Out n Enable register, offset: 0x190
| __IO uint32_t FTM_Type::POL |
Channels Polarity, offset: 0x70
| __I uint32_t SPI_Type::POPR |
POP RX FIFO Register, offset: 0x38
DSPI POP RX FIFO Register, offset: 0x38
| __IO uint8_t CMT_Type::PPS |
CMT Primary Prescaler Register, offset: 0xA
| __IO uint8_t UART_Type::PRE |
UART CEA709.1-B Preamble, offset: 0x27
| __IO uint16_t WDOG_Type::PRESC |
Watchdog Prescaler register, offset: 0x16
Watchdog Prescaler Register, offset: 0x16
| __IO uint32_t SDHC_Type::PROCTL |
Protocol Control register, offset: 0x28
Protocol Control Register, offset: 0x28
| __IO uint32_t { ... } ::PRS |
Priority Registers Slave, array offset: 0x0, array step: 0x100
| __IO uint32_t AXBS_Type::PRS |
Priority Registers Slave, array offset: 0x0, array step: 0x100
| __I uint32_t SDHC_Type::PRSSTAT |
Present State register, offset: 0x24
Present State Register, offset: 0x24
| __O uint32_t GPIO_Type::PSOR |
Port Set Output Register, offset: 0x4
| __IO uint32_t LPTMR_Type::PSR |
Low Power Timer Prescale Register, offset: 0x4
| __O uint32_t GPIO_Type::PTOR |
Port Toggle Output Register, offset: 0xC
| __IO uint32_t { ... } ::PUSHR |
PUSH TX FIFO Register In Master Mode, offset: 0x34
| __IO uint32_t SPI_Type::PUSHR |
PUSH TX FIFO Register In Master Mode, offset: 0x34
DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34
| __IO uint32_t SPI_Type::PUSHR_SLAVE |
PUSH TX FIFO Register In Slave Mode, offset: 0x34
DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34
| __IO uint32_t { ... } ::PUSHR_SLAVE |
PUSH TX FIFO Register In Slave Mode, offset: 0x34
| __IO uint32_t FTM_Type::PWMLOAD |
FTM PWM Load, offset: 0x98
| __IO uint32_t FTM_Type::QDCTRL |
Quadrature Decoder Control And Status, offset: 0x80
Quadrature Decoder Control and Status, offset: 0x80
| __I uint32_t ADC_Type::R |
ADC Data Result Register, array offset: 0x10, array step: 0x4
ADC data result register, array offset: 0x10, array step: 0x4
| __IO uint8_t I2C_Type::RA |
I2C Range Address register, offset: 0x7
| __IO uint32_t ENET_Type::RACC |
Receive Accelerator Function Configuration, offset: 0x1C4
| __O uint32_t CAU_Type::RADR_CA |
General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4
| __O uint32_t CAU_Type::RADR_CAA |
Accumulator register - Reverse and Add to Register command, offset: 0x904
| __O uint32_t CAU_Type::RADR_CASR |
Status register - Reverse and Add to Register command, offset: 0x900
| __IO uint32_t ENET_Type::RAEM |
Receive FIFO Almost Empty Threshold, offset: 0x198
| __IO uint32_t ENET_Type::RAFL |
Receive FIFO Almost Full Threshold, offset: 0x19C
| __IO uint32_t RTC_Type::RAR |
RTC Read Access Register, offset: 0x804
| __I uint8_t UART_Type::RCFIFO |
UART FIFO Receive Count, offset: 0x16
| __IO uint32_t ENET_Type::RCR |
Receive Control Register, offset: 0x84
| __IO uint32_t I2S_Type::RCR1 |
SAI Receive Configuration 1 Register, offset: 0x84
| __IO uint32_t I2S_Type::RCR2 |
SAI Receive Configuration 2 Register, offset: 0x88
| __IO uint32_t I2S_Type::RCR3 |
SAI Receive Configuration 3 Register, offset: 0x8C
| __IO uint32_t I2S_Type::RCR4 |
SAI Receive Configuration 4 Register, offset: 0x90
| __IO uint32_t I2S_Type::RCR5 |
SAI Receive Configuration 5 Register, offset: 0x94
| __IO uint32_t I2S_Type::RCSR |
SAI Receive Control Register, offset: 0x80
| __IO uint32_t ENET_Type::RDAR |
Receive Descriptor Active Register, offset: 0x10
| __I uint32_t I2S_Type::RDR |
SAI Receive Data Register, array offset: 0xA0, array step: 0x4
| __IO uint32_t ENET_Type::RDSR |
Receive Descriptor Ring Start Register, offset: 0x180
| __IO uint16_t WDOG_Type::REFRESH |
Watchdog Refresh register, offset: 0xC
Watchdog Refresh Register, offset: 0xC
| __IO uint32_t RFSYS_Type::REG |
Register file register, array offset: 0x0, array step: 0x4
| __IO uint32_t RFVBAT_Type::REG |
VBAT register file register, array offset: 0x0, array step: 0x4
| __IO uint8_t PMC_Type::REGSC |
Regulator Status And Control register, offset: 0x2
Regulator Status and Control Register, offset: 0x2
| __I uint8_t USB_Type::REV |
Peripheral Revision register, offset: 0x8
Peripheral Revision Register, offset: 0x8
| __I uint32_t I2S_Type::RFR |
SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4
| __IO uint32_t SYSMPU_Type::RGDAAC |
Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4
| __IO uint8_t UART_Type::RIDT |
UART CEA709.1-B Receive Indeterminate Time, offset: 0x30
| __I uint32_t ENET_Type::RMON_R_BC_PKT |
RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288
Rx Broadcast Packets Statistic Register, offset: 0x288
| __I uint32_t ENET_Type::RMON_R_CRC_ALIGN |
RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290
Rx Packets with CRC/Align Error Statistic Register, offset: 0x290
| __I uint32_t ENET_Type::RMON_R_FRAG |
RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C
Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C
| __I uint32_t ENET_Type::RMON_R_JAB |
RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0
Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0
| __I uint32_t ENET_Type::RMON_R_MC_PKT |
RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C
Rx Multicast Packets Statistic Register, offset: 0x28C
| __I uint32_t ENET_Type::RMON_R_OCTETS |
RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4
Rx Octets Statistic Register, offset: 0x2C4
| __I uint32_t ENET_Type::RMON_R_OVERSIZE |
RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298
Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298
| __I uint32_t ENET_Type::RMON_R_P1024TO2047 |
RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC
Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC
| __I uint32_t ENET_Type::RMON_R_P128TO255 |
RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0
Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0
| __I uint32_t ENET_Type::RMON_R_P256TO511 |
RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4
Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4
| __I uint32_t ENET_Type::RMON_R_P512TO1023 |
RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8
Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8
| __I uint32_t ENET_Type::RMON_R_P64 |
RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8
Rx 64-Byte Packets Statistic Register, offset: 0x2A8
| __I uint32_t ENET_Type::RMON_R_P65TO127 |
RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC
Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC
| __I uint32_t ENET_Type::RMON_R_P_GTE2048 |
RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0
Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0
| __I uint32_t ENET_Type::RMON_R_PACKETS |
RMON Rx packet count (RMON_R_PACKETS), offset: 0x284
Rx Packet Count Statistic Register, offset: 0x284
| uint32_t ENET_Type::RMON_R_RESVD_0 |
Reserved (RMON_R_RESVD_0), offset: 0x2A4
Reserved Statistic Register, offset: 0x2A4
| __I uint32_t ENET_Type::RMON_R_UNDERSIZE |
RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294
Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294
| __I uint32_t ENET_Type::RMON_T_BC_PKT |
RMON Tx Broadcast Packets (RMON_T_BC_PKT), offset: 0x208
Tx Broadcast Packets Statistic Register, offset: 0x208
| __I uint32_t ENET_Type::RMON_T_COL |
RMON Tx collision count (RMON_T_COL), offset: 0x224
Tx Collision Count Statistic Register, offset: 0x224
| __I uint32_t ENET_Type::RMON_T_CRC_ALIGN |
RMON Tx Packets w CRC/Align error (RMON_T_CRC_ALIGN), offset: 0x210
Tx Packets with CRC/Align Error Statistic Register, offset: 0x210
| uint32_t ENET_Type::RMON_T_DROP |
Count of frames not counted correctly (RMON_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x200
Reserved Statistic Register, offset: 0x200
| __I uint32_t ENET_Type::RMON_T_FRAG |
RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C
Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C
| __I uint32_t ENET_Type::RMON_T_JAB |
RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220
Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220
| __I uint32_t ENET_Type::RMON_T_MC_PKT |
RMON Tx Multicast Packets (RMON_T_MC_PKT), offset: 0x20C
Tx Multicast Packets Statistic Register, offset: 0x20C
| __I uint32_t ENET_Type::RMON_T_OCTETS |
RMON Tx Octets (RMON_T_OCTETS), offset: 0x244
Tx Octets Statistic Register, offset: 0x244
| __I uint32_t ENET_Type::RMON_T_OVERSIZE |
RMON Tx Packets > MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218
Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218
| __I uint32_t ENET_Type::RMON_T_P1024TO2047 |
RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C
Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C
| __I uint32_t ENET_Type::RMON_T_P128TO255 |
RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230
Tx 128- to 255-byte Packets Statistic Register, offset: 0x230
| __I uint32_t ENET_Type::RMON_T_P256TO511 |
RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234
Tx 256- to 511-byte Packets Statistic Register, offset: 0x234
| __I uint32_t ENET_Type::RMON_T_P512TO1023 |
RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238
Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238
| __I uint32_t ENET_Type::RMON_T_P64 |
RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228
Tx 64-Byte Packets Statistic Register, offset: 0x228
| __I uint32_t ENET_Type::RMON_T_P65TO127 |
RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C
Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C
| __I uint32_t ENET_Type::RMON_T_P_GTE2048 |
RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240
Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240
| __I uint32_t ENET_Type::RMON_T_PACKETS |
RMON Tx packet count (RMON_T_PACKETS), offset: 0x204
Tx Packet Count Statistic Register, offset: 0x204
| __I uint32_t ENET_Type::RMON_T_UNDERSIZE |
RMON Tx Packets < 64 bytes, good CRC (RMON_T_UNDERSIZE), offset: 0x214
Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214
| __IO uint32_t I2S_Type::RMR |
SAI Receive Mask Register, offset: 0xE0
| __O uint32_t CAU_Type::ROTL_CA |
General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4
| __O uint32_t CAU_Type::ROTL_CAA |
Accumulator register - Rotate Left command, offset: 0x9C4
| __O uint32_t CAU_Type::ROTL_CASR |
Status register - Rotate Left command, offset: 0x9C0
| __IO uint8_t RCM_Type::RPFC |
Reset Pin Filter Control register, offset: 0x4
| __IO uint8_t RCM_Type::RPFW |
Reset Pin Filter Width register, offset: 0x5
| __I uint8_t UART_Type::RPL |
UART CEA709.1-B Received Packet Length, offset: 0x2D
| __I uint8_t UART_Type::RPREL |
UART CEA709.1-B Received Preamble Length, offset: 0x2E
| __IO uint32_t ENET_Type::RSEM |
Receive FIFO Section Empty Threshold, offset: 0x194
| __IO uint32_t SPI_Type::RSER |
DMA/Interrupt Request Select and Enable Register, offset: 0x30
DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30
| __IO uint32_t ENET_Type::RSFL |
Receive FIFO Section Full Threshold, offset: 0x190
| __IO uint8_t LLWU_Type::RST |
LLWU Reset Enable register, offset: 0xA
| __IO uint16_t WDOG_Type::RSTCNT |
Watchdog Reset Count register, offset: 0x14
Watchdog Reset Count Register, offset: 0x14
| __IO uint8_t UART_Type::RWFIFO |
UART FIFO Receive Watermark, offset: 0x15
| __IO uint32_t CAN_Type::RX14MASK |
Rx 14 Mask register, offset: 0x14
Rx 14 Mask Register, offset: 0x14
| __IO uint32_t CAN_Type::RX15MASK |
Rx 15 Mask register, offset: 0x18
Rx 15 Mask Register, offset: 0x18
| __IO uint32_t CAN_Type::RXFGMASK |
Rx FIFO Global Mask register, offset: 0x48
Rx FIFO Global Mask Register, offset: 0x48
| __I uint32_t CAN_Type::RXFIR |
Rx FIFO Information Register, offset: 0x4C
| __I uint32_t SPI_Type::RXFR0 |
DSPI Receive FIFO Registers, offset: 0x7C
Receive FIFO Registers, offset: 0x7C
| __I uint32_t SPI_Type::RXFR1 |
DSPI Receive FIFO Registers, offset: 0x80
Receive FIFO Registers, offset: 0x80
| __I uint32_t SPI_Type::RXFR2 |
DSPI Receive FIFO Registers, offset: 0x84
Receive FIFO Registers, offset: 0x84
| __I uint32_t SPI_Type::RXFR3 |
DSPI Receive FIFO Registers, offset: 0x88
Receive FIFO Registers, offset: 0x88
| __IO uint32_t CAN_Type::RXIMR |
Rx Individual Mask Registers, array offset: 0x880, array step: 0x4
| __IO uint32_t CAN_Type::RXMGMASK |
Rx Mailboxes Global Mask Register, offset: 0x10
| __IO uint8_t I2C_Type::S |
I2C Status register, offset: 0x3
I2C Status Register, offset: 0x3
| __IO uint8_t MCG_Type::S |
MCG Status Register, offset: 0x6
| __IO uint32_t { ... } ::S |
Channel n Status Register, array offset: 0x14, array step: 0x28
| __IO uint32_t PDB_Type::S |
Channel n Status Register, array offset: 0x14, array step: 0x28
Channel n Status register, array offset: 0x14, array step: 0x28
| __I uint8_t UART_Type::S1 |
UART Status Register 1, offset: 0x4
| __IO uint8_t UART_Type::S2 |
UART Status Register 2, offset: 0x5
| __IO uint8_t UART_Type::S3 |
UART CEA709.1-B Status Register, offset: 0x2B
| __IO uint8_t UART_Type::S4 |
UART CEA709.1-B Status Register, offset: 0x2C
| __IO uint32_t DMA_Type::SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20
| __IO uint32_t { ... } ::SADDR |
TCD Source Address, array offset: 0x1000, array step: 0x20
| __IO uint32_t FTM_Type::SC |
Status And Control, offset: 0x0
Status and Control, offset: 0x0
| __IO uint8_t MCG_Type::SC |
MCG Status and Control Register, offset: 0x8
| __IO uint32_t PDB_Type::SC |
Status and Control Register, offset: 0x0
Status and Control register, offset: 0x0
| __IO uint8_t VREF_Type::SC |
VREF Status and Control Register, offset: 0x1
| __IO uint32_t ADC_Type::SC1 |
ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4
ADC status and control registers 1, array offset: 0x0, array step: 0x4
| __IO uint32_t ADC_Type::SC2 |
Status and Control Register 2, offset: 0x20
Status and control register 2, offset: 0x20
| __IO uint32_t ADC_Type::SC3 |
Status and Control Register 3, offset: 0x24
Status and control register 3, offset: 0x24
| __IO uint32_t TSI_Type::SCANC |
SCAN Control register, offset: 0x4
SCAN control register, offset: 0x4
| __IO uint32_t SIM_Type::SCGC1 |
System Clock Gating Control Register 1, offset: 0x1028
| __IO uint32_t SIM_Type::SCGC2 |
System Clock Gating Control Register 2, offset: 0x102C
| __IO uint32_t SIM_Type::SCGC3 |
System Clock Gating Control Register 3, offset: 0x1030
| __IO uint32_t SIM_Type::SCGC4 |
System Clock Gating Control Register 4, offset: 0x1034
| __IO uint32_t SIM_Type::SCGC5 |
System Clock Gating Control Register 5, offset: 0x1038
| __IO uint32_t SIM_Type::SCGC6 |
System Clock Gating Control Register 6, offset: 0x103C
| __IO uint32_t SIM_Type::SCGC7 |
System Clock Gating Control Register 7, offset: 0x1040
| __IO uint8_t CMP_Type::SCR |
CMP Status and Control Register, offset: 0x3
| __I uint32_t SIM_Type::SDID |
System Device Identification Register, offset: 0x1024
| __IO uint8_t UART_Type::SDTH |
UART CEA709.1-B Secondary Delay Timer High, offset: 0x25
| __IO uint8_t UART_Type::SDTL |
UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26
| __O uint8_t DMA_Type::SEEI |
Set Enable Error Interrupt Register, offset: 0x19
| __O uint8_t DMA_Type::SERQ |
Set Enable Request Register, offset: 0x1B
| __O uint8_t EWM_Type::SERV |
Service Register, offset: 0x1
| __IO uint8_t UART_Type::SFIFO |
UART FIFO Status Register, offset: 0x12
| __IO uint32_t { ... } ::SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
| __IO uint32_t DMA_Type::SLAST |
TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
| __IO uint8_t I2C_Type::SLTH |
I2C SCL Low Timeout Register High, offset: 0xA
| __IO uint8_t I2C_Type::SLTL |
I2C SCL Low Timeout Register Low, offset: 0xB
| __IO uint8_t I2C_Type::SMB |
I2C SMBus Control and Status register, offset: 0x8
| __IO uint16_t DMA_Type::SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
| __IO uint16_t { ... } ::SOFF |
TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
| __IO uint8_t USB_Type::SOFTHLD |
SOF Threshold Register, offset: 0xAC
SOF Threshold register, offset: 0xAC
| __IO uint32_t SIM_Type::SOPT1 |
System Options Register 1, offset: 0x0
| __IO uint32_t SIM_Type::SOPT1CFG |
SOPT1 Configuration Register, offset: 0x4
| __IO uint32_t SIM_Type::SOPT2 |
System Options Register 2, offset: 0x1004
| __IO uint32_t SIM_Type::SOPT4 |
System Options Register 4, offset: 0x100C
| __IO uint32_t SIM_Type::SOPT5 |
System Options Register 5, offset: 0x1010
| __IO uint32_t SIM_Type::SOPT7 |
System Options Register 7, offset: 0x1018
| __IO uint8_t DAC_Type::SR |
DAC Status Register, offset: 0x20
| __I uint32_t RNG_Type::SR |
RNGA Status Register, offset: 0x4
RNGB Status Register, offset: 0xC
| __IO uint32_t RTC_Type::SR |
RTC Status Register, offset: 0x14
| __IO uint32_t SPI_Type::SR |
DSPI Status Register, offset: 0x2C
Status Register, offset: 0x2C
| __I uint8_t RCM_Type::SRS0 |
System Reset Status Register 0, offset: 0x0
| __I uint8_t RCM_Type::SRS1 |
System Reset Status Register 1, offset: 0x1
| __O uint8_t DMA_Type::SSRT |
Set START Bit Register, offset: 0x1D
| __I uint8_t USB_Type::STAT |
Status register, offset: 0x90
Status Register, offset: 0x90
| __IO uint32_t FTM_Type::STATUS |
Capture And Compare Status, offset: 0x50
| __I uint32_t USBDCD_Type::STATUS |
Status register, offset: 0x8
Status Register, offset: 0x8
| __IO uint16_t WDOG_Type::STCTRLH |
Watchdog Status and Control Register High, offset: 0x0
| __IO uint16_t WDOG_Type::STCTRLL |
Watchdog Status and Control Register Low, offset: 0x2
| __I uint32_t CAU_Type::STR_CA |
General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4
| __I uint32_t CAU_Type::STR_CAA |
Accumulator register - Store Register command, offset: 0x884
| __I uint32_t CAU_Type::STR_CASR |
Status register - Store Register command, offset: 0x880
| __IO uint32_t FTM_Type::SWOCTRL |
FTM Software Output Control, offset: 0x94
| __IO uint32_t FTM_Type::SYNC |
Synchronization, offset: 0x58
| __IO uint32_t FTM_Type::SYNCONF |
Synchronization Configuration, offset: 0x8C
| __IO uint32_t SDHC_Type::SYSCTL |
System Control register, offset: 0x2C
System Control Register, offset: 0x2C
| __IO uint32_t ENET_Type::TACC |
Transmit Accelerator Function Configuration, offset: 0x1C0
| __IO uint32_t ENET_Type::TAEM |
Transmit FIFO Almost Empty Threshold, offset: 0x1A4
| __IO uint32_t ENET_Type::TAFL |
Transmit FIFO Almost Full Threshold, offset: 0x1A8
| __IO uint32_t FMC_Type::TAGVD |
Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4
Cache Directory Storage, array offset: 0x100, array step: index*0x20, index2*0x4
| __IO uint32_t RTC_Type::TAR |
RTC Time Alarm Register, offset: 0x8
| __IO uint32_t { ... } ::TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
| __IO uint32_t ENET_Type::TCCR |
Timer Compare Capture Register, array offset: 0x60C, array step: 0x8
| __I uint8_t UART_Type::TCFIFO |
UART FIFO Transmit Count, offset: 0x14
| __IO uint32_t ENET_Type::TCR |
Transmit Control Register, offset: 0xC4
| __IO uint32_t RTC_Type::TCR |
RTC Time Compensation Register, offset: 0xC
| __IO uint32_t SPI_Type::TCR |
Transfer Count Register, offset: 0x8
DSPI Transfer Count Register, offset: 0x8
| __IO uint32_t I2S_Type::TCR1 |
SAI Transmit Configuration 1 Register, offset: 0x4
| __IO uint32_t I2S_Type::TCR2 |
SAI Transmit Configuration 2 Register, offset: 0x8
| __IO uint32_t I2S_Type::TCR3 |
SAI Transmit Configuration 3 Register, offset: 0xC
| __IO uint32_t I2S_Type::TCR4 |
SAI Transmit Configuration 4 Register, offset: 0x10
| __IO uint32_t I2S_Type::TCR5 |
SAI Transmit Configuration 5 Register, offset: 0x14
| __IO uint32_t { ... } ::TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8
| __IO uint32_t ENET_Type::TCSR |
Timer Control Status Register, array offset: 0x608, array step: 0x8
| __IO uint32_t I2S_Type::TCSR |
SAI Transmit Control Register, offset: 0x0
| __IO uint32_t PIT_Type::TCTRL |
Timer Control Register, array offset: 0x108, array step: 0x10
| __IO uint32_t { ... } ::TCTRL |
Timer Control Register, array offset: 0x108, array step: 0x10
| __IO uint32_t ENET_Type::TDAR |
Transmit Descriptor Active Register, offset: 0x14
| __O uint32_t I2S_Type::TDR |
SAI Transmit Data Register, array offset: 0x20, array step: 0x4
| __IO uint32_t ENET_Type::TDSR |
Transmit Buffer Descriptor Ring Start Register, offset: 0x184
| __IO uint32_t { ... } ::TFLG |
Timer Flag Register, array offset: 0x10C, array step: 0x10
| __IO uint32_t PIT_Type::TFLG |
Timer Flag Register, array offset: 0x10C, array step: 0x10
| __I uint32_t I2S_Type::TFR |
SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4
| __IO uint32_t ENET_Type::TFWR |
Transmit FIFO Watermark Register, offset: 0x144
| __IO uint32_t ENET_Type::TGSR |
Timer Global Status Register, offset: 0x604
| __IO uint32_t TSI_Type::THRESHOLD |
Low-Power Channel Threshold register, offset: 0x120
| __IO uint8_t UART_Type::TIDT |
UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31
| __IO uint32_t CAN_Type::TIMER |
Free Running Timer, offset: 0x8
| __IO uint32_t USBDCD_Type::TIMER0 |
TIMER0 register, offset: 0x10
TIMER0 Register, offset: 0x10
| __IO uint32_t USBDCD_Type::TIMER1 |
TIMER1 register, offset: 0x14
, offset: 0x14
| __IO uint32_t USBDCD_Type::TIMER2 |
TIMER2 register, offset: 0x18
, offset: 0x18
| __IO uint32_t ENET_Type::TIPG |
Transmit Inter-Packet Gap, offset: 0x1AC
| __IO uint8_t UART_Type::TL7816 |
UART 7816 Transmit Length Register, offset: 0x1F
| __IO uint32_t I2S_Type::TMR |
SAI Transmit Mask Register, offset: 0x60
| __IO uint16_t WDOG_Type::TMROUTH |
Watchdog Timer Output Register High, offset: 0x10
| __IO uint16_t WDOG_Type::TMROUTL |
Watchdog Timer Output Register Low, offset: 0x12
| __IO uint8_t USB_Type::TOKEN |
Token register, offset: 0xA8
Token Register, offset: 0xA8
| __IO uint16_t WDOG_Type::TOVALH |
Watchdog Time-out Value Register High, offset: 0x4
| __IO uint16_t WDOG_Type::TOVALL |
Watchdog Time-out Value Register Low, offset: 0x6
| __IO uint8_t UART_Type::TPL |
UART CEA709.1-B Transmit Packet Length, offset: 0x28
| __IO uint32_t RTC_Type::TPR |
RTC Time Prescaler Register, offset: 0x4
| __IO uint8_t VREF_Type::TRM |
VREF Trim Register, offset: 0x0
| __IO uint32_t ENET_Type::TSEM |
Transmit FIFO Section Empty Threshold, offset: 0x1A0
| __IO uint32_t RTC_Type::TSR |
RTC Time Seconds Register, offset: 0x0
| __IO uint8_t UART_Type::TWFIFO |
UART FIFO Transmit Watermark, offset: 0x13
| __I uint32_t SPI_Type::TXFR0 |
DSPI Transmit FIFO Registers, offset: 0x3C
Transmit FIFO Registers, offset: 0x3C
| __I uint32_t SPI_Type::TXFR1 |
DSPI Transmit FIFO Registers, offset: 0x40
Transmit FIFO Registers, offset: 0x40
| __I uint32_t SPI_Type::TXFR2 |
DSPI Transmit FIFO Registers, offset: 0x44
Transmit FIFO Registers, offset: 0x44
| __I uint32_t SPI_Type::TXFR3 |
DSPI Transmit FIFO Registers, offset: 0x48
Transmit FIFO Registers, offset: 0x48
| __I uint32_t SIM_Type::UIDH |
Unique Identification Register High, offset: 0x1054
| __I uint32_t SIM_Type::UIDL |
Unique Identification Register Low, offset: 0x1060
| __I uint32_t SIM_Type::UIDMH |
Unique Identification Register Mid-High, offset: 0x1058
| __I uint32_t SIM_Type::UIDML |
Unique Identification Register Mid Low, offset: 0x105C
| __IO uint16_t WDOG_Type::UNLOCK |
Watchdog Unlock register, offset: 0xE
Watchdog Unlock Register, offset: 0xE
| __IO uint8_t USB_Type::USBCTRL |
USB Control register, offset: 0x100
USB Control Register, offset: 0x100
| __IO uint8_t USB_Type::USBFRMADJUST |
Frame Adjust Register, offset: 0x114
| __IO uint8_t USB_Type::USBTRC0 |
USB Transceiver Control Register 0, offset: 0x10C
USB Transceiver Control register 0, offset: 0x10C
| __IO uint32_t SDHC_Type::VENDOR |
Vendor Specific register, offset: 0xC0
Vendor Specific Register, offset: 0xC0
| __IO uint8_t SMC_Type::VLLSCTRL |
VLLS Control register, offset: 0x2
| __IO uint32_t RTC_Type::WAR |
RTC Write Access Register, offset: 0x800
| __IO uint8_t UART_Type::WB |
UART CEA709.1-B WBASE, offset: 0x2A
| __IO uint8_t UART_Type::WF7816 |
UART 7816 Wait FD Register, offset: 0x1D
| __IO uint16_t WDOG_Type::WINH |
Watchdog Window Register High, offset: 0x8
| __IO uint16_t WDOG_Type::WINL |
Watchdog Window Register Low, offset: 0xA
| __IO uint32_t SDHC_Type::WML |
Watermark Level Register, offset: 0x44
| __IO uint8_t UART_Type::WN7816 |
UART 7816 Wait N Register, offset: 0x1C
| __IO uint32_t SYSMPU_Type::WORD |
Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4
| __IO uint32_t { ... } ::WORD0 |
Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10
| __IO uint32_t CAN_Type::WORD0 |
Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10
| __IO uint32_t { ... } ::WORD1 |
Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10
| __IO uint32_t CAN_Type::WORD1 |
Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10
| __IO uint8_t { ... } ::WP7816T0 |
UART 7816 Wait Parameter Register, offset: 0x1B
| __IO uint8_t UART_Type::WP7816T0 |
UART 7816 Wait Parameter Register, offset: 0x1B
| __IO uint8_t { ... } ::WP7816T1 |
UART 7816 Wait Parameter Register, offset: 0x1B
| __IO uint8_t UART_Type::WP7816T1 |
UART 7816 Wait Parameter Register, offset: 0x1B
| __I uint32_t TSI_Type::WUCNTR |
Wake-Up Channel Counter Register, offset: 0xC
| __IO uint32_t SDHC_Type::XFERTYP |
Transfer Type register, offset: 0xC
Transfer Type Register, offset: 0xC
| __O uint32_t CAU_Type::XOR_CA |
General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4
| __O uint32_t CAU_Type::XOR_CAA |
Accumulator register - Exclusive Or command, offset: 0x984
| __O uint32_t CAU_Type::XOR_CASR |
Status register - Exclusive Or command, offset: 0x980