mikroSDK Reference Manual
stm32f407xx.h
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1
33#ifndef __STM32F407xx_H
34#define __STM32F407xx_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
65typedef enum
66{
67/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68 NonMaskableInt_IRQn = -14,
69 MemoryManagement_IRQn = -12,
70 BusFault_IRQn = -11,
71 UsageFault_IRQn = -10,
72 SVCall_IRQn = -5,
73 DebugMonitor_IRQn = -4,
74 PendSV_IRQn = -2,
75 SysTick_IRQn = -1,
76/****** STM32 specific Interrupt Numbers **********************************************************************/
77 WWDG_IRQn = 0,
78 PVD_IRQn = 1,
79 TAMP_STAMP_IRQn = 2,
80 RTC_WKUP_IRQn = 3,
81 FLASH_IRQn = 4,
82 RCC_IRQn = 5,
83 EXTI0_IRQn = 6,
84 EXTI1_IRQn = 7,
85 EXTI2_IRQn = 8,
86 EXTI3_IRQn = 9,
87 EXTI4_IRQn = 10,
88 DMA1_Stream0_IRQn = 11,
89 DMA1_Stream1_IRQn = 12,
90 DMA1_Stream2_IRQn = 13,
91 DMA1_Stream3_IRQn = 14,
92 DMA1_Stream4_IRQn = 15,
93 DMA1_Stream5_IRQn = 16,
94 DMA1_Stream6_IRQn = 17,
95 ADC_IRQn = 18,
96 CAN1_TX_IRQn = 19,
97 CAN1_RX0_IRQn = 20,
98 CAN1_RX1_IRQn = 21,
99 CAN1_SCE_IRQn = 22,
100 EXTI9_5_IRQn = 23,
101 TIM1_BRK_TIM9_IRQn = 24,
102 TIM1_UP_TIM10_IRQn = 25,
103 TIM1_TRG_COM_TIM11_IRQn = 26,
104 TIM1_CC_IRQn = 27,
105 TIM2_IRQn = 28,
106 TIM3_IRQn = 29,
107 TIM4_IRQn = 30,
108 I2C1_EV_IRQn = 31,
109 I2C1_ER_IRQn = 32,
110 I2C2_EV_IRQn = 33,
111 I2C2_ER_IRQn = 34,
112 SPI1_IRQn = 35,
113 SPI2_IRQn = 36,
114 USART1_IRQn = 37,
115 USART2_IRQn = 38,
116 USART3_IRQn = 39,
117 EXTI15_10_IRQn = 40,
118 RTC_Alarm_IRQn = 41,
119 OTG_FS_WKUP_IRQn = 42,
120 TIM8_BRK_TIM12_IRQn = 43,
121 TIM8_UP_TIM13_IRQn = 44,
122 TIM8_TRG_COM_TIM14_IRQn = 45,
123 TIM8_CC_IRQn = 46,
124 DMA1_Stream7_IRQn = 47,
125 FSMC_IRQn = 48,
126 SDIO_IRQn = 49,
127 TIM5_IRQn = 50,
128 SPI3_IRQn = 51,
129 UART4_IRQn = 52,
130 UART5_IRQn = 53,
131 TIM6_DAC_IRQn = 54,
132 TIM7_IRQn = 55,
133 DMA2_Stream0_IRQn = 56,
134 DMA2_Stream1_IRQn = 57,
135 DMA2_Stream2_IRQn = 58,
136 DMA2_Stream3_IRQn = 59,
137 DMA2_Stream4_IRQn = 60,
138 ETH_IRQn = 61,
139 ETH_WKUP_IRQn = 62,
140 CAN2_TX_IRQn = 63,
141 CAN2_RX0_IRQn = 64,
142 CAN2_RX1_IRQn = 65,
143 CAN2_SCE_IRQn = 66,
144 OTG_FS_IRQn = 67,
145 DMA2_Stream5_IRQn = 68,
146 DMA2_Stream6_IRQn = 69,
147 DMA2_Stream7_IRQn = 70,
148 USART6_IRQn = 71,
149 I2C3_EV_IRQn = 72,
150 I2C3_ER_IRQn = 73,
151 OTG_HS_EP1_OUT_IRQn = 74,
152 OTG_HS_EP1_IN_IRQn = 75,
153 OTG_HS_WKUP_IRQn = 76,
154 OTG_HS_IRQn = 77,
155 DCMI_IRQn = 78,
156 RNG_IRQn = 80,
157 FPU_IRQn = 81
158} IRQn_Type;
159/* Legacy define */
160#define HASH_RNG_IRQn RNG_IRQn
161
166#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
167#include "system_stm32f4xx.h"
168#include <stdint.h>
169
178typedef struct
179{
180 __IO uint32_t SR;
181 __IO uint32_t CR1;
182 __IO uint32_t CR2;
183 __IO uint32_t SMPR1;
184 __IO uint32_t SMPR2;
185 __IO uint32_t JOFR1;
186 __IO uint32_t JOFR2;
187 __IO uint32_t JOFR3;
188 __IO uint32_t JOFR4;
189 __IO uint32_t HTR;
190 __IO uint32_t LTR;
191 __IO uint32_t SQR1;
192 __IO uint32_t SQR2;
193 __IO uint32_t SQR3;
194 __IO uint32_t JSQR;
195 __IO uint32_t JDR1;
196 __IO uint32_t JDR2;
197 __IO uint32_t JDR3;
198 __IO uint32_t JDR4;
199 __IO uint32_t DR;
200} ADC_TypeDef;
201
202typedef struct
203{
204 __IO uint32_t CSR;
205 __IO uint32_t CCR;
206 __IO uint32_t CDR;
208} ADC_Common_TypeDef;
209
210
215typedef struct
216{
217 __IO uint32_t TIR;
218 __IO uint32_t TDTR;
219 __IO uint32_t TDLR;
220 __IO uint32_t TDHR;
221} CAN_TxMailBox_TypeDef;
222
227typedef struct
228{
229 __IO uint32_t RIR;
230 __IO uint32_t RDTR;
231 __IO uint32_t RDLR;
232 __IO uint32_t RDHR;
233} CAN_FIFOMailBox_TypeDef;
234
239typedef struct
240{
241 __IO uint32_t FR1;
242 __IO uint32_t FR2;
243} CAN_FilterRegister_TypeDef;
244
249typedef struct
250{
251 __IO uint32_t MCR;
252 __IO uint32_t MSR;
253 __IO uint32_t TSR;
254 __IO uint32_t RF0R;
255 __IO uint32_t RF1R;
256 __IO uint32_t IER;
257 __IO uint32_t ESR;
258 __IO uint32_t BTR;
259 uint32_t RESERVED0[88];
260 CAN_TxMailBox_TypeDef sTxMailBox[3];
261 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
262 uint32_t RESERVED1[12];
263 __IO uint32_t FMR;
264 __IO uint32_t FM1R;
265 uint32_t RESERVED2;
266 __IO uint32_t FS1R;
267 uint32_t RESERVED3;
268 __IO uint32_t FFA1R;
269 uint32_t RESERVED4;
270 __IO uint32_t FA1R;
271 uint32_t RESERVED5[8];
272 CAN_FilterRegister_TypeDef sFilterRegister[28];
273} CAN_TypeDef;
274
279typedef struct
280{
281 __IO uint32_t DR;
282 __IO uint8_t IDR;
283 uint8_t RESERVED0;
284 uint16_t RESERVED1;
285 __IO uint32_t CR;
286} CRC_TypeDef;
287
292typedef struct
293{
294 __IO uint32_t CR;
295 __IO uint32_t SWTRIGR;
296 __IO uint32_t DHR12R1;
297 __IO uint32_t DHR12L1;
298 __IO uint32_t DHR8R1;
299 __IO uint32_t DHR12R2;
300 __IO uint32_t DHR12L2;
301 __IO uint32_t DHR8R2;
302 __IO uint32_t DHR12RD;
303 __IO uint32_t DHR12LD;
304 __IO uint32_t DHR8RD;
305 __IO uint32_t DOR1;
306 __IO uint32_t DOR2;
307 __IO uint32_t SR;
308} DAC_TypeDef;
309
314typedef struct
315{
316 __IO uint32_t IDCODE;
317 __IO uint32_t CR;
318 __IO uint32_t APB1FZ;
319 __IO uint32_t APB2FZ;
320}DBGMCU_TypeDef;
321
326typedef struct
327{
328 __IO uint32_t CR;
329 __IO uint32_t SR;
330 __IO uint32_t RISR;
331 __IO uint32_t IER;
332 __IO uint32_t MISR;
333 __IO uint32_t ICR;
334 __IO uint32_t ESCR;
335 __IO uint32_t ESUR;
336 __IO uint32_t CWSTRTR;
337 __IO uint32_t CWSIZER;
338 __IO uint32_t DR;
339} DCMI_TypeDef;
340
345typedef struct
346{
347 __IO uint32_t CR;
348 __IO uint32_t NDTR;
349 __IO uint32_t PAR;
350 __IO uint32_t M0AR;
351 __IO uint32_t M1AR;
352 __IO uint32_t FCR;
353} DMA_Stream_TypeDef;
354
355typedef struct
356{
357 __IO uint32_t LISR;
358 __IO uint32_t HISR;
359 __IO uint32_t LIFCR;
360 __IO uint32_t HIFCR;
361} DMA_TypeDef;
362
367typedef struct
368{
369 __IO uint32_t MACCR;
370 __IO uint32_t MACFFR;
371 __IO uint32_t MACHTHR;
372 __IO uint32_t MACHTLR;
373 __IO uint32_t MACMIIAR;
374 __IO uint32_t MACMIIDR;
375 __IO uint32_t MACFCR;
376 __IO uint32_t MACVLANTR; /* 8 */
377 uint32_t RESERVED0[2];
378 __IO uint32_t MACRWUFFR; /* 11 */
379 __IO uint32_t MACPMTCSR;
380 uint32_t RESERVED1;
381 __IO uint32_t MACDBGR;
382 __IO uint32_t MACSR; /* 15 */
383 __IO uint32_t MACIMR;
384 __IO uint32_t MACA0HR;
385 __IO uint32_t MACA0LR;
386 __IO uint32_t MACA1HR;
387 __IO uint32_t MACA1LR;
388 __IO uint32_t MACA2HR;
389 __IO uint32_t MACA2LR;
390 __IO uint32_t MACA3HR;
391 __IO uint32_t MACA3LR; /* 24 */
392 uint32_t RESERVED2[40];
393 __IO uint32_t MMCCR; /* 65 */
394 __IO uint32_t MMCRIR;
395 __IO uint32_t MMCTIR;
396 __IO uint32_t MMCRIMR;
397 __IO uint32_t MMCTIMR; /* 69 */
398 uint32_t RESERVED3[14];
399 __IO uint32_t MMCTGFSCCR; /* 84 */
400 __IO uint32_t MMCTGFMSCCR;
401 uint32_t RESERVED4[5];
402 __IO uint32_t MMCTGFCR;
403 uint32_t RESERVED5[10];
404 __IO uint32_t MMCRFCECR;
405 __IO uint32_t MMCRFAECR;
406 uint32_t RESERVED6[10];
407 __IO uint32_t MMCRGUFCR;
408 uint32_t RESERVED7[334];
409 __IO uint32_t PTPTSCR;
410 __IO uint32_t PTPSSIR;
411 __IO uint32_t PTPTSHR;
412 __IO uint32_t PTPTSLR;
413 __IO uint32_t PTPTSHUR;
414 __IO uint32_t PTPTSLUR;
415 __IO uint32_t PTPTSAR;
416 __IO uint32_t PTPTTHR;
417 __IO uint32_t PTPTTLR;
418 __IO uint32_t RESERVED8;
419 __IO uint32_t PTPTSSR;
420 uint32_t RESERVED9[565];
421 __IO uint32_t DMABMR;
422 __IO uint32_t DMATPDR;
423 __IO uint32_t DMARPDR;
424 __IO uint32_t DMARDLAR;
425 __IO uint32_t DMATDLAR;
426 __IO uint32_t DMASR;
427 __IO uint32_t DMAOMR;
428 __IO uint32_t DMAIER;
429 __IO uint32_t DMAMFBOCR;
430 __IO uint32_t DMARSWTR;
431 uint32_t RESERVED10[8];
432 __IO uint32_t DMACHTDR;
433 __IO uint32_t DMACHRDR;
434 __IO uint32_t DMACHTBAR;
435 __IO uint32_t DMACHRBAR;
436} ETH_TypeDef;
437
442typedef struct
443{
444 __IO uint32_t IMR;
445 __IO uint32_t EMR;
446 __IO uint32_t RTSR;
447 __IO uint32_t FTSR;
448 __IO uint32_t SWIER;
449 __IO uint32_t PR;
450} EXTI_TypeDef;
451
456typedef struct
457{
458 __IO uint32_t ACR;
459 __IO uint32_t KEYR;
460 __IO uint32_t OPTKEYR;
461 __IO uint32_t SR;
462 __IO uint32_t CR;
463 __IO uint32_t OPTCR;
464 __IO uint32_t OPTCR1;
465} FLASH_TypeDef;
466
467
468
473typedef struct
474{
475 __IO uint32_t BTCR[8];
476} FSMC_Bank1_TypeDef;
477
482typedef struct
483{
484 __IO uint32_t BWTR[7];
485} FSMC_Bank1E_TypeDef;
486
491typedef struct
492{
493 __IO uint32_t PCR2;
494 __IO uint32_t SR2;
495 __IO uint32_t PMEM2;
496 __IO uint32_t PATT2;
497 uint32_t RESERVED0;
498 __IO uint32_t ECCR2;
499 uint32_t RESERVED1;
500 uint32_t RESERVED2;
501 __IO uint32_t PCR3;
502 __IO uint32_t SR3;
503 __IO uint32_t PMEM3;
504 __IO uint32_t PATT3;
505 uint32_t RESERVED3;
506 __IO uint32_t ECCR3;
507} FSMC_Bank2_3_TypeDef;
508
513typedef struct
514{
515 __IO uint32_t PCR4;
516 __IO uint32_t SR4;
517 __IO uint32_t PMEM4;
518 __IO uint32_t PATT4;
519 __IO uint32_t PIO4;
520} FSMC_Bank4_TypeDef;
521
526typedef struct
527{
528 __IO uint32_t MODER;
529 __IO uint32_t OTYPER;
530 __IO uint32_t OSPEEDR;
531 __IO uint32_t PUPDR;
532 __IO uint32_t IDR;
533 __IO uint32_t ODR;
534 __IO uint32_t BSRR;
535 __IO uint32_t LCKR;
536 __IO uint32_t AFR[2];
537} GPIO_TypeDef;
538
543typedef struct
544{
545 __IO uint32_t MEMRMP;
546 __IO uint32_t PMC;
547 __IO uint32_t EXTICR[4];
548 uint32_t RESERVED[2];
549 __IO uint32_t CMPCR;
550} SYSCFG_TypeDef;
551
556typedef struct
557{
558 __IO uint32_t CR1;
559 __IO uint32_t CR2;
560 __IO uint32_t OAR1;
561 __IO uint32_t OAR2;
562 __IO uint32_t DR;
563 __IO uint32_t SR1;
564 __IO uint32_t SR2;
565 __IO uint32_t CCR;
566 __IO uint32_t TRISE;
567} I2C_TypeDef;
568
573typedef struct
574{
575 __IO uint32_t KR;
576 __IO uint32_t PR;
577 __IO uint32_t RLR;
578 __IO uint32_t SR;
579} IWDG_TypeDef;
580
581
586typedef struct
587{
588 __IO uint32_t CR;
589 __IO uint32_t CSR;
590} PWR_TypeDef;
591
596typedef struct
597{
598 __IO uint32_t CR;
599 __IO uint32_t PLLCFGR;
600 __IO uint32_t CFGR;
601 __IO uint32_t CIR;
602 __IO uint32_t AHB1RSTR;
603 __IO uint32_t AHB2RSTR;
604 __IO uint32_t AHB3RSTR;
605 uint32_t RESERVED0;
606 __IO uint32_t APB1RSTR;
607 __IO uint32_t APB2RSTR;
608 uint32_t RESERVED1[2];
609 __IO uint32_t AHB1ENR;
610 __IO uint32_t AHB2ENR;
611 __IO uint32_t AHB3ENR;
612 uint32_t RESERVED2;
613 __IO uint32_t APB1ENR;
614 __IO uint32_t APB2ENR;
615 uint32_t RESERVED3[2];
616 __IO uint32_t AHB1LPENR;
617 __IO uint32_t AHB2LPENR;
618 __IO uint32_t AHB3LPENR;
619 uint32_t RESERVED4;
620 __IO uint32_t APB1LPENR;
621 __IO uint32_t APB2LPENR;
622 uint32_t RESERVED5[2];
623 __IO uint32_t BDCR;
624 __IO uint32_t CSR;
625 uint32_t RESERVED6[2];
626 __IO uint32_t SSCGR;
627 __IO uint32_t PLLI2SCFGR;
628} RCC_TypeDef;
629
634typedef struct
635{
636 __IO uint32_t TR;
637 __IO uint32_t DR;
638 __IO uint32_t CR;
639 __IO uint32_t ISR;
640 __IO uint32_t PRER;
641 __IO uint32_t WUTR;
642 __IO uint32_t CALIBR;
643 __IO uint32_t ALRMAR;
644 __IO uint32_t ALRMBR;
645 __IO uint32_t WPR;
646 __IO uint32_t SSR;
647 __IO uint32_t SHIFTR;
648 __IO uint32_t TSTR;
649 __IO uint32_t TSDR;
650 __IO uint32_t TSSSR;
651 __IO uint32_t CALR;
652 __IO uint32_t TAFCR;
653 __IO uint32_t ALRMASSR;
654 __IO uint32_t ALRMBSSR;
655 uint32_t RESERVED7;
656 __IO uint32_t BKP0R;
657 __IO uint32_t BKP1R;
658 __IO uint32_t BKP2R;
659 __IO uint32_t BKP3R;
660 __IO uint32_t BKP4R;
661 __IO uint32_t BKP5R;
662 __IO uint32_t BKP6R;
663 __IO uint32_t BKP7R;
664 __IO uint32_t BKP8R;
665 __IO uint32_t BKP9R;
666 __IO uint32_t BKP10R;
667 __IO uint32_t BKP11R;
668 __IO uint32_t BKP12R;
669 __IO uint32_t BKP13R;
670 __IO uint32_t BKP14R;
671 __IO uint32_t BKP15R;
672 __IO uint32_t BKP16R;
673 __IO uint32_t BKP17R;
674 __IO uint32_t BKP18R;
675 __IO uint32_t BKP19R;
676} RTC_TypeDef;
677
682typedef struct
683{
684 __IO uint32_t POWER;
685 __IO uint32_t CLKCR;
686 __IO uint32_t ARG;
687 __IO uint32_t CMD;
688 __IO const uint32_t RESPCMD;
689 __IO const uint32_t RESP1;
690 __IO const uint32_t RESP2;
691 __IO const uint32_t RESP3;
692 __IO const uint32_t RESP4;
693 __IO uint32_t DTIMER;
694 __IO uint32_t DLEN;
695 __IO uint32_t DCTRL;
696 __IO const uint32_t DCOUNT;
697 __IO const uint32_t STA;
698 __IO uint32_t ICR;
699 __IO uint32_t MASK;
700 uint32_t RESERVED0[2];
701 __IO const uint32_t FIFOCNT;
702 uint32_t RESERVED1[13];
703 __IO uint32_t FIFO;
704} SDIO_TypeDef;
705
710typedef struct
711{
712 __IO uint32_t CR1;
713 __IO uint32_t CR2;
714 __IO uint32_t SR;
715 __IO uint32_t DR;
716 __IO uint32_t CRCPR;
717 __IO uint32_t RXCRCR;
718 __IO uint32_t TXCRCR;
719 __IO uint32_t I2SCFGR;
720 __IO uint32_t I2SPR;
721} SPI_TypeDef;
722
723
728typedef struct
729{
730 __IO uint32_t CR1;
731 __IO uint32_t CR2;
732 __IO uint32_t SMCR;
733 __IO uint32_t DIER;
734 __IO uint32_t SR;
735 __IO uint32_t EGR;
736 __IO uint32_t CCMR1;
737 __IO uint32_t CCMR2;
738 __IO uint32_t CCER;
739 __IO uint32_t CNT;
740 __IO uint32_t PSC;
741 __IO uint32_t ARR;
742 __IO uint32_t RCR;
743 __IO uint32_t CCR1;
744 __IO uint32_t CCR2;
745 __IO uint32_t CCR3;
746 __IO uint32_t CCR4;
747 __IO uint32_t BDTR;
748 __IO uint32_t DCR;
749 __IO uint32_t DMAR;
750 __IO uint32_t OR;
751} TIM_TypeDef;
752
757typedef struct
758{
759 __IO uint32_t SR;
760 __IO uint32_t DR;
761 __IO uint32_t BRR;
762 __IO uint32_t CR1;
763 __IO uint32_t CR2;
764 __IO uint32_t CR3;
765 __IO uint32_t GTPR;
766} USART_TypeDef;
767
772typedef struct
773{
774 __IO uint32_t CR;
775 __IO uint32_t CFR;
776 __IO uint32_t SR;
777} WWDG_TypeDef;
778
783typedef struct
784{
785 __IO uint32_t CR;
786 __IO uint32_t SR;
787 __IO uint32_t DR;
788} RNG_TypeDef;
789
793typedef struct
794{
795 __IO uint32_t GOTGCTL;
796 __IO uint32_t GOTGINT;
797 __IO uint32_t GAHBCFG;
798 __IO uint32_t GUSBCFG;
799 __IO uint32_t GRSTCTL;
800 __IO uint32_t GINTSTS;
801 __IO uint32_t GINTMSK;
802 __IO uint32_t GRXSTSR;
803 __IO uint32_t GRXSTSP;
804 __IO uint32_t GRXFSIZ;
805 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
806 __IO uint32_t HNPTXSTS;
807 uint32_t Reserved30[2];
808 __IO uint32_t GCCFG;
809 __IO uint32_t CID;
810 uint32_t Reserved40[48];
811 __IO uint32_t HPTXFSIZ;
812 __IO uint32_t DIEPTXF[0x0F];
813} USB_OTG_GlobalTypeDef;
814
818typedef struct
819{
820 __IO uint32_t DCFG;
821 __IO uint32_t DCTL;
822 __IO uint32_t DSTS;
823 uint32_t Reserved0C;
824 __IO uint32_t DIEPMSK;
825 __IO uint32_t DOEPMSK;
826 __IO uint32_t DAINT;
827 __IO uint32_t DAINTMSK;
828 uint32_t Reserved20;
829 uint32_t Reserved9;
830 __IO uint32_t DVBUSDIS;
831 __IO uint32_t DVBUSPULSE;
832 __IO uint32_t DTHRCTL;
833 __IO uint32_t DIEPEMPMSK;
834 __IO uint32_t DEACHINT;
835 __IO uint32_t DEACHMSK;
836 uint32_t Reserved40;
837 __IO uint32_t DINEP1MSK;
838 uint32_t Reserved44[15];
839 __IO uint32_t DOUTEP1MSK;
840} USB_OTG_DeviceTypeDef;
841
845typedef struct
846{
847 __IO uint32_t DIEPCTL;
848 uint32_t Reserved04;
849 __IO uint32_t DIEPINT;
850 uint32_t Reserved0C;
851 __IO uint32_t DIEPTSIZ;
852 __IO uint32_t DIEPDMA;
853 __IO uint32_t DTXFSTS;
854 uint32_t Reserved18;
855} USB_OTG_INEndpointTypeDef;
856
860typedef struct
861{
862 __IO uint32_t DOEPCTL;
863 uint32_t Reserved04;
864 __IO uint32_t DOEPINT;
865 uint32_t Reserved0C;
866 __IO uint32_t DOEPTSIZ;
867 __IO uint32_t DOEPDMA;
868 uint32_t Reserved18[2];
869} USB_OTG_OUTEndpointTypeDef;
870
874typedef struct
875{
876 __IO uint32_t HCFG;
877 __IO uint32_t HFIR;
878 __IO uint32_t HFNUM;
879 uint32_t Reserved40C;
880 __IO uint32_t HPTXSTS;
881 __IO uint32_t HAINT;
882 __IO uint32_t HAINTMSK;
883} USB_OTG_HostTypeDef;
884
888typedef struct
889{
890 __IO uint32_t HCCHAR;
891 __IO uint32_t HCSPLT;
892 __IO uint32_t HCINT;
893 __IO uint32_t HCINTMSK;
894 __IO uint32_t HCTSIZ;
895 __IO uint32_t HCDMA;
896 uint32_t Reserved[2];
897} USB_OTG_HostChannelTypeDef;
898
906#define FLASH_BASE 0x08000000UL
907#define CCMDATARAM_BASE 0x10000000UL
908#define SRAM1_BASE 0x20000000UL
909#define SRAM2_BASE 0x2001C000UL
910#define PERIPH_BASE 0x40000000UL
911#define BKPSRAM_BASE 0x40024000UL
912#define FSMC_R_BASE 0xA0000000UL
913#define SRAM1_BB_BASE 0x22000000UL
914#define SRAM2_BB_BASE 0x22380000UL
915#define PERIPH_BB_BASE 0x42000000UL
916#define BKPSRAM_BB_BASE 0x42480000UL
917#define FLASH_END 0x080FFFFFUL
918#define FLASH_OTP_BASE 0x1FFF7800UL
919#define FLASH_OTP_END 0x1FFF7A0FUL
920#define CCMDATARAM_END 0x1000FFFFUL
922/* Legacy defines */
923#define SRAM_BASE SRAM1_BASE
924#define SRAM_BB_BASE SRAM1_BB_BASE
925
927#define APB1PERIPH_BASE PERIPH_BASE
928#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
929#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
930#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
931
933#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
934#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
935#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
936#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
937#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
938#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
939#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
940#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
941#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
942#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
943#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
944#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
945#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
946#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
947#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
948#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
949#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
950#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
951#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
952#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
953#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
954#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
955#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
956#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
957#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
958#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
959#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
960
962#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
963#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
964#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
965#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
966#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
967#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
968#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
969#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
970/* Legacy define */
971#define ADC_BASE ADC123_COMMON_BASE
972#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
973#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
974#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
975#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
976#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
977#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
978#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
979
981#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
982#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
983#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
984#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
985#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
986#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
987#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
988#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
989#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
990#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
991#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
992#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
993#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
994#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
995#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
996#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
997#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
998#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
999#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1000#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1001#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1002#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1003#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1004#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1005#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1006#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1007#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1008#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1009#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1010#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1011#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
1012#define ETH_MAC_BASE (ETH_BASE)
1013#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
1014#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
1015#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
1016
1018#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1019#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1020
1022#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)
1023#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)
1024#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL)
1025#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL)
1026
1027
1029#define DBGMCU_BASE 0xE0042000UL
1031#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1032#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1033
1034#define USB_OTG_GLOBAL_BASE 0x000UL
1035#define USB_OTG_DEVICE_BASE 0x800UL
1036#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
1037#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
1038#define USB_OTG_EP_REG_SIZE 0x20UL
1039#define USB_OTG_HOST_BASE 0x400UL
1040#define USB_OTG_HOST_PORT_BASE 0x440UL
1041#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
1042#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
1043#define USB_OTG_PCGCCTL_BASE 0xE00UL
1044#define USB_OTG_FIFO_BASE 0x1000UL
1045#define USB_OTG_FIFO_SIZE 0x1000UL
1046
1047#define UID_BASE 0x1FFF7A10UL
1048#define FLASHSIZE_BASE 0x1FFF7A22UL
1049#define PACKAGE_BASE 0x1FFF7BF0UL
1057#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1058#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1059#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1060#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1061#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1062#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1063#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1064#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1065#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1066#define RTC ((RTC_TypeDef *) RTC_BASE)
1067#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1068#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1069#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1070#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1071#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1072#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1073#define USART2 ((USART_TypeDef *) USART2_BASE)
1074#define USART3 ((USART_TypeDef *) USART3_BASE)
1075#define UART4 ((USART_TypeDef *) UART4_BASE)
1076#define UART5 ((USART_TypeDef *) UART5_BASE)
1077#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1078#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1079#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1080#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1081#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1082#define PWR ((PWR_TypeDef *) PWR_BASE)
1083#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1084#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1085#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1086#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1087#define USART1 ((USART_TypeDef *) USART1_BASE)
1088#define USART6 ((USART_TypeDef *) USART6_BASE)
1089#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1090#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1091#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1092#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1093/* Legacy define */
1094#define ADC ADC123_COMMON
1095#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1096#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1097#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1098#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1099#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1100#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1101#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1102#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1103#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1104#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1105#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1106#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1107#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1108#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1109#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1110#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1111#define CRC ((CRC_TypeDef *) CRC_BASE)
1112#define RCC ((RCC_TypeDef *) RCC_BASE)
1113#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1114#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1115#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1116#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1117#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1118#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1119#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1120#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1121#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1122#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1123#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1124#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1125#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1126#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1127#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1128#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1129#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1130#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1131#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1132#define ETH ((ETH_TypeDef *) ETH_BASE)
1133#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1134#define RNG ((RNG_TypeDef *) RNG_BASE)
1135#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1136#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1137#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1138#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1139#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1140#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1141#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1142
1154#define LSI_STARTUP_TIME 40U
1163/******************************************************************************/
1164/* Peripheral Registers_Bits_Definition */
1165/******************************************************************************/
1166
1167/******************************************************************************/
1168/* */
1169/* Analog to Digital Converter */
1170/* */
1171/******************************************************************************/
1172/*
1173 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1174 */
1175#define ADC_MULTIMODE_SUPPORT
1177/******************** Bit definition for ADC_SR register ********************/
1178#define ADC_SR_AWD_Pos (0U)
1179#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1180#define ADC_SR_AWD ADC_SR_AWD_Msk
1181#define ADC_SR_EOC_Pos (1U)
1182#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1183#define ADC_SR_EOC ADC_SR_EOC_Msk
1184#define ADC_SR_JEOC_Pos (2U)
1185#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1186#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1187#define ADC_SR_JSTRT_Pos (3U)
1188#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1189#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1190#define ADC_SR_STRT_Pos (4U)
1191#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1192#define ADC_SR_STRT ADC_SR_STRT_Msk
1193#define ADC_SR_OVR_Pos (5U)
1194#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1195#define ADC_SR_OVR ADC_SR_OVR_Msk
1197/******************* Bit definition for ADC_CR1 register ********************/
1198#define ADC_CR1_AWDCH_Pos (0U)
1199#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1200#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1201#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1202#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1203#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1204#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1205#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1206#define ADC_CR1_EOCIE_Pos (5U)
1207#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1208#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1209#define ADC_CR1_AWDIE_Pos (6U)
1210#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1211#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1212#define ADC_CR1_JEOCIE_Pos (7U)
1213#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1214#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1215#define ADC_CR1_SCAN_Pos (8U)
1216#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1217#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1218#define ADC_CR1_AWDSGL_Pos (9U)
1219#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1220#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1221#define ADC_CR1_JAUTO_Pos (10U)
1222#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1223#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1224#define ADC_CR1_DISCEN_Pos (11U)
1225#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1226#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1227#define ADC_CR1_JDISCEN_Pos (12U)
1228#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1229#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1230#define ADC_CR1_DISCNUM_Pos (13U)
1231#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1232#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1233#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1234#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1235#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1236#define ADC_CR1_JAWDEN_Pos (22U)
1237#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1238#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1239#define ADC_CR1_AWDEN_Pos (23U)
1240#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1241#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1242#define ADC_CR1_RES_Pos (24U)
1243#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1244#define ADC_CR1_RES ADC_CR1_RES_Msk
1245#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1246#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1247#define ADC_CR1_OVRIE_Pos (26U)
1248#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1249#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1251/******************* Bit definition for ADC_CR2 register ********************/
1252#define ADC_CR2_ADON_Pos (0U)
1253#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1254#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1255#define ADC_CR2_CONT_Pos (1U)
1256#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1257#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1258#define ADC_CR2_DMA_Pos (8U)
1259#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1260#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1261#define ADC_CR2_DDS_Pos (9U)
1262#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1263#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1264#define ADC_CR2_EOCS_Pos (10U)
1265#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1266#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1267#define ADC_CR2_ALIGN_Pos (11U)
1268#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1269#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1270#define ADC_CR2_JEXTSEL_Pos (16U)
1271#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1272#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1273#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1274#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1275#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1276#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1277#define ADC_CR2_JEXTEN_Pos (20U)
1278#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1279#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1280#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1281#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1282#define ADC_CR2_JSWSTART_Pos (22U)
1283#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1284#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1285#define ADC_CR2_EXTSEL_Pos (24U)
1286#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1287#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1288#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1289#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1290#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1291#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1292#define ADC_CR2_EXTEN_Pos (28U)
1293#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1294#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1295#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1296#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1297#define ADC_CR2_SWSTART_Pos (30U)
1298#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1299#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1301/****************** Bit definition for ADC_SMPR1 register *******************/
1302#define ADC_SMPR1_SMP10_Pos (0U)
1303#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1304#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1305#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1306#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1307#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1308#define ADC_SMPR1_SMP11_Pos (3U)
1309#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1310#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1311#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1312#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1313#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1314#define ADC_SMPR1_SMP12_Pos (6U)
1315#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1316#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1317#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1318#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1319#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1320#define ADC_SMPR1_SMP13_Pos (9U)
1321#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1322#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1323#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1324#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1325#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1326#define ADC_SMPR1_SMP14_Pos (12U)
1327#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1328#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1329#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1330#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1331#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1332#define ADC_SMPR1_SMP15_Pos (15U)
1333#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1334#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1335#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1336#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1337#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1338#define ADC_SMPR1_SMP16_Pos (18U)
1339#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1340#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1341#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1342#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1343#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1344#define ADC_SMPR1_SMP17_Pos (21U)
1345#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1346#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1347#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1348#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1349#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1350#define ADC_SMPR1_SMP18_Pos (24U)
1351#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1352#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1353#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1354#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1355#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1357/****************** Bit definition for ADC_SMPR2 register *******************/
1358#define ADC_SMPR2_SMP0_Pos (0U)
1359#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1360#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1361#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1362#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1363#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1364#define ADC_SMPR2_SMP1_Pos (3U)
1365#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1366#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1367#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1368#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1369#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1370#define ADC_SMPR2_SMP2_Pos (6U)
1371#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1372#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1373#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1374#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1375#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1376#define ADC_SMPR2_SMP3_Pos (9U)
1377#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1378#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1379#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1380#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1381#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1382#define ADC_SMPR2_SMP4_Pos (12U)
1383#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1384#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1385#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1386#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1387#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1388#define ADC_SMPR2_SMP5_Pos (15U)
1389#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1390#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1391#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1392#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1393#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1394#define ADC_SMPR2_SMP6_Pos (18U)
1395#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1396#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1397#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1398#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1399#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1400#define ADC_SMPR2_SMP7_Pos (21U)
1401#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1402#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1403#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1404#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1405#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1406#define ADC_SMPR2_SMP8_Pos (24U)
1407#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1408#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1409#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1410#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1411#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1412#define ADC_SMPR2_SMP9_Pos (27U)
1413#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1414#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1415#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1416#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1417#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1419/****************** Bit definition for ADC_JOFR1 register *******************/
1420#define ADC_JOFR1_JOFFSET1_Pos (0U)
1421#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1422#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1424/****************** Bit definition for ADC_JOFR2 register *******************/
1425#define ADC_JOFR2_JOFFSET2_Pos (0U)
1426#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1427#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1429/****************** Bit definition for ADC_JOFR3 register *******************/
1430#define ADC_JOFR3_JOFFSET3_Pos (0U)
1431#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1432#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1434/****************** Bit definition for ADC_JOFR4 register *******************/
1435#define ADC_JOFR4_JOFFSET4_Pos (0U)
1436#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1437#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1439/******************* Bit definition for ADC_HTR register ********************/
1440#define ADC_HTR_HT_Pos (0U)
1441#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1442#define ADC_HTR_HT ADC_HTR_HT_Msk
1444/******************* Bit definition for ADC_LTR register ********************/
1445#define ADC_LTR_LT_Pos (0U)
1446#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1447#define ADC_LTR_LT ADC_LTR_LT_Msk
1449/******************* Bit definition for ADC_SQR1 register *******************/
1450#define ADC_SQR1_SQ13_Pos (0U)
1451#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1452#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1453#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1454#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1455#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1456#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1457#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1458#define ADC_SQR1_SQ14_Pos (5U)
1459#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1460#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1461#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1462#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1463#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1464#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1465#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1466#define ADC_SQR1_SQ15_Pos (10U)
1467#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1468#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1469#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1470#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1471#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1472#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1473#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1474#define ADC_SQR1_SQ16_Pos (15U)
1475#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1476#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1477#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1478#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1479#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1480#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1481#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1482#define ADC_SQR1_L_Pos (20U)
1483#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1484#define ADC_SQR1_L ADC_SQR1_L_Msk
1485#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1486#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1487#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1488#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1490/******************* Bit definition for ADC_SQR2 register *******************/
1491#define ADC_SQR2_SQ7_Pos (0U)
1492#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1493#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1494#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1495#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1496#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1497#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1498#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1499#define ADC_SQR2_SQ8_Pos (5U)
1500#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1501#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1502#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1503#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1504#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1505#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1506#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1507#define ADC_SQR2_SQ9_Pos (10U)
1508#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1509#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1510#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1511#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1512#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1513#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1514#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1515#define ADC_SQR2_SQ10_Pos (15U)
1516#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1517#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1518#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1519#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1520#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1521#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1522#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1523#define ADC_SQR2_SQ11_Pos (20U)
1524#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1525#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1526#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1527#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1528#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1529#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1530#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1531#define ADC_SQR2_SQ12_Pos (25U)
1532#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1533#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1534#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1535#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1536#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1537#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1538#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1540/******************* Bit definition for ADC_SQR3 register *******************/
1541#define ADC_SQR3_SQ1_Pos (0U)
1542#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1543#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1544#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1545#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1546#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1547#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1548#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1549#define ADC_SQR3_SQ2_Pos (5U)
1550#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1551#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1552#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1553#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1554#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1555#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1556#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1557#define ADC_SQR3_SQ3_Pos (10U)
1558#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1559#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1560#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1561#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1562#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1563#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1564#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1565#define ADC_SQR3_SQ4_Pos (15U)
1566#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1567#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1568#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1569#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1570#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1571#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1572#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1573#define ADC_SQR3_SQ5_Pos (20U)
1574#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1575#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1576#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1577#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1578#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1579#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1580#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1581#define ADC_SQR3_SQ6_Pos (25U)
1582#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1583#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1584#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1585#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1586#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1587#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1588#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1590/******************* Bit definition for ADC_JSQR register *******************/
1591#define ADC_JSQR_JSQ1_Pos (0U)
1592#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1593#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1594#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1595#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1596#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1597#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1598#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1599#define ADC_JSQR_JSQ2_Pos (5U)
1600#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1601#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1602#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1603#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1604#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1605#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1606#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1607#define ADC_JSQR_JSQ3_Pos (10U)
1608#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1609#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1610#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1611#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1612#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1613#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1614#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1615#define ADC_JSQR_JSQ4_Pos (15U)
1616#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1617#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1618#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1619#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1620#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1621#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1622#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1623#define ADC_JSQR_JL_Pos (20U)
1624#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1625#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1626#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1627#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1629/******************* Bit definition for ADC_JDR1 register *******************/
1630#define ADC_JDR1_JDATA_Pos (0U)
1631#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1632#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1634/******************* Bit definition for ADC_JDR2 register *******************/
1635#define ADC_JDR2_JDATA_Pos (0U)
1636#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1637#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1639/******************* Bit definition for ADC_JDR3 register *******************/
1640#define ADC_JDR3_JDATA_Pos (0U)
1641#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1642#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1644/******************* Bit definition for ADC_JDR4 register *******************/
1645#define ADC_JDR4_JDATA_Pos (0U)
1646#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1647#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1649/******************** Bit definition for ADC_DR register ********************/
1650#define ADC_DR_DATA_Pos (0U)
1651#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1652#define ADC_DR_DATA ADC_DR_DATA_Msk
1653#define ADC_DR_ADC2DATA_Pos (16U)
1654#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1655#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1657/******************* Bit definition for ADC_CSR register ********************/
1658#define ADC_CSR_AWD1_Pos (0U)
1659#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1660#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1661#define ADC_CSR_EOC1_Pos (1U)
1662#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1663#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1664#define ADC_CSR_JEOC1_Pos (2U)
1665#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1666#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1667#define ADC_CSR_JSTRT1_Pos (3U)
1668#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1669#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1670#define ADC_CSR_STRT1_Pos (4U)
1671#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1672#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1673#define ADC_CSR_OVR1_Pos (5U)
1674#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1675#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1676#define ADC_CSR_AWD2_Pos (8U)
1677#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1678#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1679#define ADC_CSR_EOC2_Pos (9U)
1680#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1681#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1682#define ADC_CSR_JEOC2_Pos (10U)
1683#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1684#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
1685#define ADC_CSR_JSTRT2_Pos (11U)
1686#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
1687#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
1688#define ADC_CSR_STRT2_Pos (12U)
1689#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
1690#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
1691#define ADC_CSR_OVR2_Pos (13U)
1692#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
1693#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
1694#define ADC_CSR_AWD3_Pos (16U)
1695#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
1696#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
1697#define ADC_CSR_EOC3_Pos (17U)
1698#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
1699#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
1700#define ADC_CSR_JEOC3_Pos (18U)
1701#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
1702#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
1703#define ADC_CSR_JSTRT3_Pos (19U)
1704#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
1705#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
1706#define ADC_CSR_STRT3_Pos (20U)
1707#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
1708#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
1709#define ADC_CSR_OVR3_Pos (21U)
1710#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
1711#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
1713/* Legacy defines */
1714#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1715#define ADC_CSR_DOVR2 ADC_CSR_OVR2
1716#define ADC_CSR_DOVR3 ADC_CSR_OVR3
1717
1718/******************* Bit definition for ADC_CCR register ********************/
1719#define ADC_CCR_MULTI_Pos (0U)
1720#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1721#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1722#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1723#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1724#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1725#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1726#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1727#define ADC_CCR_DELAY_Pos (8U)
1728#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1729#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1730#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1731#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1732#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1733#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1734#define ADC_CCR_DDS_Pos (13U)
1735#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1736#define ADC_CCR_DDS ADC_CCR_DDS_Msk
1737#define ADC_CCR_DMA_Pos (14U)
1738#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1739#define ADC_CCR_DMA ADC_CCR_DMA_Msk
1740#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1741#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1742#define ADC_CCR_ADCPRE_Pos (16U)
1743#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1744#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1745#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1746#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1747#define ADC_CCR_VBATE_Pos (22U)
1748#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1749#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1750#define ADC_CCR_TSVREFE_Pos (23U)
1751#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1752#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1754/******************* Bit definition for ADC_CDR register ********************/
1755#define ADC_CDR_DATA1_Pos (0U)
1756#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1757#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1758#define ADC_CDR_DATA2_Pos (16U)
1759#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1760#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1762/* Legacy defines */
1763#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1764#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1765
1766/******************************************************************************/
1767/* */
1768/* Controller Area Network */
1769/* */
1770/******************************************************************************/
1772/******************* Bit definition for CAN_MCR register ********************/
1773#define CAN_MCR_INRQ_Pos (0U)
1774#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1775#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1776#define CAN_MCR_SLEEP_Pos (1U)
1777#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1778#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1779#define CAN_MCR_TXFP_Pos (2U)
1780#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1781#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1782#define CAN_MCR_RFLM_Pos (3U)
1783#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1784#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1785#define CAN_MCR_NART_Pos (4U)
1786#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1787#define CAN_MCR_NART CAN_MCR_NART_Msk
1788#define CAN_MCR_AWUM_Pos (5U)
1789#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1790#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1791#define CAN_MCR_ABOM_Pos (6U)
1792#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1793#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1794#define CAN_MCR_TTCM_Pos (7U)
1795#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1796#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1797#define CAN_MCR_RESET_Pos (15U)
1798#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1799#define CAN_MCR_RESET CAN_MCR_RESET_Msk
1800#define CAN_MCR_DBF_Pos (16U)
1801#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
1802#define CAN_MCR_DBF CAN_MCR_DBF_Msk
1803/******************* Bit definition for CAN_MSR register ********************/
1804#define CAN_MSR_INAK_Pos (0U)
1805#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1806#define CAN_MSR_INAK CAN_MSR_INAK_Msk
1807#define CAN_MSR_SLAK_Pos (1U)
1808#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
1809#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
1810#define CAN_MSR_ERRI_Pos (2U)
1811#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
1812#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
1813#define CAN_MSR_WKUI_Pos (3U)
1814#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
1815#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
1816#define CAN_MSR_SLAKI_Pos (4U)
1817#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
1818#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
1819#define CAN_MSR_TXM_Pos (8U)
1820#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
1821#define CAN_MSR_TXM CAN_MSR_TXM_Msk
1822#define CAN_MSR_RXM_Pos (9U)
1823#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
1824#define CAN_MSR_RXM CAN_MSR_RXM_Msk
1825#define CAN_MSR_SAMP_Pos (10U)
1826#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
1827#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
1828#define CAN_MSR_RX_Pos (11U)
1829#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
1830#define CAN_MSR_RX CAN_MSR_RX_Msk
1832/******************* Bit definition for CAN_TSR register ********************/
1833#define CAN_TSR_RQCP0_Pos (0U)
1834#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
1835#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
1836#define CAN_TSR_TXOK0_Pos (1U)
1837#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
1838#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
1839#define CAN_TSR_ALST0_Pos (2U)
1840#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
1841#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
1842#define CAN_TSR_TERR0_Pos (3U)
1843#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
1844#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
1845#define CAN_TSR_ABRQ0_Pos (7U)
1846#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
1847#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
1848#define CAN_TSR_RQCP1_Pos (8U)
1849#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
1850#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
1851#define CAN_TSR_TXOK1_Pos (9U)
1852#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
1853#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
1854#define CAN_TSR_ALST1_Pos (10U)
1855#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
1856#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
1857#define CAN_TSR_TERR1_Pos (11U)
1858#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
1859#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
1860#define CAN_TSR_ABRQ1_Pos (15U)
1861#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
1862#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
1863#define CAN_TSR_RQCP2_Pos (16U)
1864#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
1865#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
1866#define CAN_TSR_TXOK2_Pos (17U)
1867#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
1868#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
1869#define CAN_TSR_ALST2_Pos (18U)
1870#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
1871#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
1872#define CAN_TSR_TERR2_Pos (19U)
1873#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
1874#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
1875#define CAN_TSR_ABRQ2_Pos (23U)
1876#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
1877#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
1878#define CAN_TSR_CODE_Pos (24U)
1879#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
1880#define CAN_TSR_CODE CAN_TSR_CODE_Msk
1882#define CAN_TSR_TME_Pos (26U)
1883#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
1884#define CAN_TSR_TME CAN_TSR_TME_Msk
1885#define CAN_TSR_TME0_Pos (26U)
1886#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
1887#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
1888#define CAN_TSR_TME1_Pos (27U)
1889#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
1890#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
1891#define CAN_TSR_TME2_Pos (28U)
1892#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
1893#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
1895#define CAN_TSR_LOW_Pos (29U)
1896#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
1897#define CAN_TSR_LOW CAN_TSR_LOW_Msk
1898#define CAN_TSR_LOW0_Pos (29U)
1899#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
1900#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
1901#define CAN_TSR_LOW1_Pos (30U)
1902#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
1903#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
1904#define CAN_TSR_LOW2_Pos (31U)
1905#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
1906#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
1908/******************* Bit definition for CAN_RF0R register *******************/
1909#define CAN_RF0R_FMP0_Pos (0U)
1910#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
1911#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
1912#define CAN_RF0R_FULL0_Pos (3U)
1913#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
1914#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
1915#define CAN_RF0R_FOVR0_Pos (4U)
1916#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
1917#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
1918#define CAN_RF0R_RFOM0_Pos (5U)
1919#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
1920#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
1922/******************* Bit definition for CAN_RF1R register *******************/
1923#define CAN_RF1R_FMP1_Pos (0U)
1924#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
1925#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
1926#define CAN_RF1R_FULL1_Pos (3U)
1927#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
1928#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
1929#define CAN_RF1R_FOVR1_Pos (4U)
1930#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
1931#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
1932#define CAN_RF1R_RFOM1_Pos (5U)
1933#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
1934#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
1936/******************** Bit definition for CAN_IER register *******************/
1937#define CAN_IER_TMEIE_Pos (0U)
1938#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
1939#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
1940#define CAN_IER_FMPIE0_Pos (1U)
1941#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
1942#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
1943#define CAN_IER_FFIE0_Pos (2U)
1944#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
1945#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
1946#define CAN_IER_FOVIE0_Pos (3U)
1947#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
1948#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
1949#define CAN_IER_FMPIE1_Pos (4U)
1950#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
1951#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
1952#define CAN_IER_FFIE1_Pos (5U)
1953#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
1954#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
1955#define CAN_IER_FOVIE1_Pos (6U)
1956#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
1957#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
1958#define CAN_IER_EWGIE_Pos (8U)
1959#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
1960#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
1961#define CAN_IER_EPVIE_Pos (9U)
1962#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
1963#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
1964#define CAN_IER_BOFIE_Pos (10U)
1965#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
1966#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
1967#define CAN_IER_LECIE_Pos (11U)
1968#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
1969#define CAN_IER_LECIE CAN_IER_LECIE_Msk
1970#define CAN_IER_ERRIE_Pos (15U)
1971#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
1972#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
1973#define CAN_IER_WKUIE_Pos (16U)
1974#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
1975#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
1976#define CAN_IER_SLKIE_Pos (17U)
1977#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
1978#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
1979#define CAN_IER_EWGIE_Pos (8U)
1980
1981/******************** Bit definition for CAN_ESR register *******************/
1982#define CAN_ESR_EWGF_Pos (0U)
1983#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
1984#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
1985#define CAN_ESR_EPVF_Pos (1U)
1986#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
1987#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
1988#define CAN_ESR_BOFF_Pos (2U)
1989#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
1990#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
1992#define CAN_ESR_LEC_Pos (4U)
1993#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
1994#define CAN_ESR_LEC CAN_ESR_LEC_Msk
1995#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
1996#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
1997#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
1999#define CAN_ESR_TEC_Pos (16U)
2000#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2001#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2002#define CAN_ESR_REC_Pos (24U)
2003#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2004#define CAN_ESR_REC CAN_ESR_REC_Msk
2006/******************* Bit definition for CAN_BTR register ********************/
2007#define CAN_BTR_BRP_Pos (0U)
2008#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2009#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2010#define CAN_BTR_TS1_Pos (16U)
2011#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2012#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2013#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2014#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2015#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2016#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2017#define CAN_BTR_TS2_Pos (20U)
2018#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2019#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2020#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2021#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2022#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2023#define CAN_BTR_SJW_Pos (24U)
2024#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2025#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2026#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2027#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2028#define CAN_BTR_LBKM_Pos (30U)
2029#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2030#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2031#define CAN_BTR_SILM_Pos (31U)
2032#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2033#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2037/****************** Bit definition for CAN_TI0R register ********************/
2038#define CAN_TI0R_TXRQ_Pos (0U)
2039#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2040#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2041#define CAN_TI0R_RTR_Pos (1U)
2042#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2043#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2044#define CAN_TI0R_IDE_Pos (2U)
2045#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2046#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2047#define CAN_TI0R_EXID_Pos (3U)
2048#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2049#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2050#define CAN_TI0R_STID_Pos (21U)
2051#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2052#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2054/****************** Bit definition for CAN_TDT0R register *******************/
2055#define CAN_TDT0R_DLC_Pos (0U)
2056#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2057#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2058#define CAN_TDT0R_TGT_Pos (8U)
2059#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2060#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2061#define CAN_TDT0R_TIME_Pos (16U)
2062#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2063#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2065/****************** Bit definition for CAN_TDL0R register *******************/
2066#define CAN_TDL0R_DATA0_Pos (0U)
2067#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2068#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2069#define CAN_TDL0R_DATA1_Pos (8U)
2070#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2071#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2072#define CAN_TDL0R_DATA2_Pos (16U)
2073#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2074#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2075#define CAN_TDL0R_DATA3_Pos (24U)
2076#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2077#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2079/****************** Bit definition for CAN_TDH0R register *******************/
2080#define CAN_TDH0R_DATA4_Pos (0U)
2081#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2082#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2083#define CAN_TDH0R_DATA5_Pos (8U)
2084#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2085#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2086#define CAN_TDH0R_DATA6_Pos (16U)
2087#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2088#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2089#define CAN_TDH0R_DATA7_Pos (24U)
2090#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2091#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2093/******************* Bit definition for CAN_TI1R register *******************/
2094#define CAN_TI1R_TXRQ_Pos (0U)
2095#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2096#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2097#define CAN_TI1R_RTR_Pos (1U)
2098#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2099#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2100#define CAN_TI1R_IDE_Pos (2U)
2101#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2102#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2103#define CAN_TI1R_EXID_Pos (3U)
2104#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2105#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2106#define CAN_TI1R_STID_Pos (21U)
2107#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2108#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2110/******************* Bit definition for CAN_TDT1R register ******************/
2111#define CAN_TDT1R_DLC_Pos (0U)
2112#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2113#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2114#define CAN_TDT1R_TGT_Pos (8U)
2115#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2116#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2117#define CAN_TDT1R_TIME_Pos (16U)
2118#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2119#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2121/******************* Bit definition for CAN_TDL1R register ******************/
2122#define CAN_TDL1R_DATA0_Pos (0U)
2123#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2124#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2125#define CAN_TDL1R_DATA1_Pos (8U)
2126#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2127#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2128#define CAN_TDL1R_DATA2_Pos (16U)
2129#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2130#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2131#define CAN_TDL1R_DATA3_Pos (24U)
2132#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2133#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2135/******************* Bit definition for CAN_TDH1R register ******************/
2136#define CAN_TDH1R_DATA4_Pos (0U)
2137#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2138#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2139#define CAN_TDH1R_DATA5_Pos (8U)
2140#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2141#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2142#define CAN_TDH1R_DATA6_Pos (16U)
2143#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2144#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2145#define CAN_TDH1R_DATA7_Pos (24U)
2146#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2147#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2149/******************* Bit definition for CAN_TI2R register *******************/
2150#define CAN_TI2R_TXRQ_Pos (0U)
2151#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2152#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2153#define CAN_TI2R_RTR_Pos (1U)
2154#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2155#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2156#define CAN_TI2R_IDE_Pos (2U)
2157#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2158#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2159#define CAN_TI2R_EXID_Pos (3U)
2160#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2161#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2162#define CAN_TI2R_STID_Pos (21U)
2163#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2164#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2166/******************* Bit definition for CAN_TDT2R register ******************/
2167#define CAN_TDT2R_DLC_Pos (0U)
2168#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2169#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2170#define CAN_TDT2R_TGT_Pos (8U)
2171#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2172#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2173#define CAN_TDT2R_TIME_Pos (16U)
2174#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2175#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2177/******************* Bit definition for CAN_TDL2R register ******************/
2178#define CAN_TDL2R_DATA0_Pos (0U)
2179#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2180#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2181#define CAN_TDL2R_DATA1_Pos (8U)
2182#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2183#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2184#define CAN_TDL2R_DATA2_Pos (16U)
2185#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2186#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2187#define CAN_TDL2R_DATA3_Pos (24U)
2188#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2189#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2191/******************* Bit definition for CAN_TDH2R register ******************/
2192#define CAN_TDH2R_DATA4_Pos (0U)
2193#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2194#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2195#define CAN_TDH2R_DATA5_Pos (8U)
2196#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2197#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2198#define CAN_TDH2R_DATA6_Pos (16U)
2199#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2200#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2201#define CAN_TDH2R_DATA7_Pos (24U)
2202#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2203#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2205/******************* Bit definition for CAN_RI0R register *******************/
2206#define CAN_RI0R_RTR_Pos (1U)
2207#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2208#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2209#define CAN_RI0R_IDE_Pos (2U)
2210#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2211#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2212#define CAN_RI0R_EXID_Pos (3U)
2213#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2214#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2215#define CAN_RI0R_STID_Pos (21U)
2216#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2217#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2219/******************* Bit definition for CAN_RDT0R register ******************/
2220#define CAN_RDT0R_DLC_Pos (0U)
2221#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2222#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2223#define CAN_RDT0R_FMI_Pos (8U)
2224#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2225#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2226#define CAN_RDT0R_TIME_Pos (16U)
2227#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2228#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2230/******************* Bit definition for CAN_RDL0R register ******************/
2231#define CAN_RDL0R_DATA0_Pos (0U)
2232#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2233#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2234#define CAN_RDL0R_DATA1_Pos (8U)
2235#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2236#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2237#define CAN_RDL0R_DATA2_Pos (16U)
2238#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2239#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2240#define CAN_RDL0R_DATA3_Pos (24U)
2241#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2242#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2244/******************* Bit definition for CAN_RDH0R register ******************/
2245#define CAN_RDH0R_DATA4_Pos (0U)
2246#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2247#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2248#define CAN_RDH0R_DATA5_Pos (8U)
2249#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2250#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2251#define CAN_RDH0R_DATA6_Pos (16U)
2252#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2253#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2254#define CAN_RDH0R_DATA7_Pos (24U)
2255#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2256#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2258/******************* Bit definition for CAN_RI1R register *******************/
2259#define CAN_RI1R_RTR_Pos (1U)
2260#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2261#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2262#define CAN_RI1R_IDE_Pos (2U)
2263#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2264#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2265#define CAN_RI1R_EXID_Pos (3U)
2266#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2267#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2268#define CAN_RI1R_STID_Pos (21U)
2269#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2270#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2272/******************* Bit definition for CAN_RDT1R register ******************/
2273#define CAN_RDT1R_DLC_Pos (0U)
2274#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2275#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2276#define CAN_RDT1R_FMI_Pos (8U)
2277#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2278#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2279#define CAN_RDT1R_TIME_Pos (16U)
2280#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2281#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2283/******************* Bit definition for CAN_RDL1R register ******************/
2284#define CAN_RDL1R_DATA0_Pos (0U)
2285#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2286#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2287#define CAN_RDL1R_DATA1_Pos (8U)
2288#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2289#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2290#define CAN_RDL1R_DATA2_Pos (16U)
2291#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2292#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2293#define CAN_RDL1R_DATA3_Pos (24U)
2294#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2295#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2297/******************* Bit definition for CAN_RDH1R register ******************/
2298#define CAN_RDH1R_DATA4_Pos (0U)
2299#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2300#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2301#define CAN_RDH1R_DATA5_Pos (8U)
2302#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2303#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2304#define CAN_RDH1R_DATA6_Pos (16U)
2305#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2306#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2307#define CAN_RDH1R_DATA7_Pos (24U)
2308#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2309#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2312/******************* Bit definition for CAN_FMR register ********************/
2313#define CAN_FMR_FINIT_Pos (0U)
2314#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2315#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2316#define CAN_FMR_CAN2SB_Pos (8U)
2317#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2318#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2320/******************* Bit definition for CAN_FM1R register *******************/
2321#define CAN_FM1R_FBM_Pos (0U)
2322#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2323#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2324#define CAN_FM1R_FBM0_Pos (0U)
2325#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2326#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2327#define CAN_FM1R_FBM1_Pos (1U)
2328#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2329#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2330#define CAN_FM1R_FBM2_Pos (2U)
2331#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2332#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2333#define CAN_FM1R_FBM3_Pos (3U)
2334#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2335#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2336#define CAN_FM1R_FBM4_Pos (4U)
2337#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2338#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2339#define CAN_FM1R_FBM5_Pos (5U)
2340#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2341#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2342#define CAN_FM1R_FBM6_Pos (6U)
2343#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2344#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2345#define CAN_FM1R_FBM7_Pos (7U)
2346#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2347#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2348#define CAN_FM1R_FBM8_Pos (8U)
2349#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2350#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2351#define CAN_FM1R_FBM9_Pos (9U)
2352#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2353#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2354#define CAN_FM1R_FBM10_Pos (10U)
2355#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2356#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2357#define CAN_FM1R_FBM11_Pos (11U)
2358#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2359#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2360#define CAN_FM1R_FBM12_Pos (12U)
2361#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2362#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2363#define CAN_FM1R_FBM13_Pos (13U)
2364#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2365#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2366#define CAN_FM1R_FBM14_Pos (14U)
2367#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2368#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2369#define CAN_FM1R_FBM15_Pos (15U)
2370#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2371#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2372#define CAN_FM1R_FBM16_Pos (16U)
2373#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2374#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2375#define CAN_FM1R_FBM17_Pos (17U)
2376#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2377#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2378#define CAN_FM1R_FBM18_Pos (18U)
2379#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2380#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2381#define CAN_FM1R_FBM19_Pos (19U)
2382#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2383#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2384#define CAN_FM1R_FBM20_Pos (20U)
2385#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2386#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2387#define CAN_FM1R_FBM21_Pos (21U)
2388#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2389#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2390#define CAN_FM1R_FBM22_Pos (22U)
2391#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2392#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2393#define CAN_FM1R_FBM23_Pos (23U)
2394#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2395#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2396#define CAN_FM1R_FBM24_Pos (24U)
2397#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2398#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2399#define CAN_FM1R_FBM25_Pos (25U)
2400#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2401#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2402#define CAN_FM1R_FBM26_Pos (26U)
2403#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2404#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2405#define CAN_FM1R_FBM27_Pos (27U)
2406#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2407#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2409/******************* Bit definition for CAN_FS1R register *******************/
2410#define CAN_FS1R_FSC_Pos (0U)
2411#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2412#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2413#define CAN_FS1R_FSC0_Pos (0U)
2414#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2415#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2416#define CAN_FS1R_FSC1_Pos (1U)
2417#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2418#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2419#define CAN_FS1R_FSC2_Pos (2U)
2420#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2421#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2422#define CAN_FS1R_FSC3_Pos (3U)
2423#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2424#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2425#define CAN_FS1R_FSC4_Pos (4U)
2426#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2427#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2428#define CAN_FS1R_FSC5_Pos (5U)
2429#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2430#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2431#define CAN_FS1R_FSC6_Pos (6U)
2432#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2433#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2434#define CAN_FS1R_FSC7_Pos (7U)
2435#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2436#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2437#define CAN_FS1R_FSC8_Pos (8U)
2438#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2439#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2440#define CAN_FS1R_FSC9_Pos (9U)
2441#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2442#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2443#define CAN_FS1R_FSC10_Pos (10U)
2444#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2445#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2446#define CAN_FS1R_FSC11_Pos (11U)
2447#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2448#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2449#define CAN_FS1R_FSC12_Pos (12U)
2450#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2451#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2452#define CAN_FS1R_FSC13_Pos (13U)
2453#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2454#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2455#define CAN_FS1R_FSC14_Pos (14U)
2456#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2457#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2458#define CAN_FS1R_FSC15_Pos (15U)
2459#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2460#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2461#define CAN_FS1R_FSC16_Pos (16U)
2462#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2463#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2464#define CAN_FS1R_FSC17_Pos (17U)
2465#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2466#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2467#define CAN_FS1R_FSC18_Pos (18U)
2468#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2469#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2470#define CAN_FS1R_FSC19_Pos (19U)
2471#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2472#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2473#define CAN_FS1R_FSC20_Pos (20U)
2474#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2475#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2476#define CAN_FS1R_FSC21_Pos (21U)
2477#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2478#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2479#define CAN_FS1R_FSC22_Pos (22U)
2480#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2481#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2482#define CAN_FS1R_FSC23_Pos (23U)
2483#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2484#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2485#define CAN_FS1R_FSC24_Pos (24U)
2486#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2487#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2488#define CAN_FS1R_FSC25_Pos (25U)
2489#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2490#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2491#define CAN_FS1R_FSC26_Pos (26U)
2492#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2493#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2494#define CAN_FS1R_FSC27_Pos (27U)
2495#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2496#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2498/****************** Bit definition for CAN_FFA1R register *******************/
2499#define CAN_FFA1R_FFA_Pos (0U)
2500#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2501#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2502#define CAN_FFA1R_FFA0_Pos (0U)
2503#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2504#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2505#define CAN_FFA1R_FFA1_Pos (1U)
2506#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2507#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2508#define CAN_FFA1R_FFA2_Pos (2U)
2509#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2510#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2511#define CAN_FFA1R_FFA3_Pos (3U)
2512#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2513#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2514#define CAN_FFA1R_FFA4_Pos (4U)
2515#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2516#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2517#define CAN_FFA1R_FFA5_Pos (5U)
2518#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2519#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2520#define CAN_FFA1R_FFA6_Pos (6U)
2521#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2522#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2523#define CAN_FFA1R_FFA7_Pos (7U)
2524#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2525#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2526#define CAN_FFA1R_FFA8_Pos (8U)
2527#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2528#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2529#define CAN_FFA1R_FFA9_Pos (9U)
2530#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2531#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2532#define CAN_FFA1R_FFA10_Pos (10U)
2533#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2534#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2535#define CAN_FFA1R_FFA11_Pos (11U)
2536#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2537#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2538#define CAN_FFA1R_FFA12_Pos (12U)
2539#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2540#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2541#define CAN_FFA1R_FFA13_Pos (13U)
2542#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2543#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2544#define CAN_FFA1R_FFA14_Pos (14U)
2545#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2546#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2547#define CAN_FFA1R_FFA15_Pos (15U)
2548#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2549#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2550#define CAN_FFA1R_FFA16_Pos (16U)
2551#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2552#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2553#define CAN_FFA1R_FFA17_Pos (17U)
2554#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2555#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2556#define CAN_FFA1R_FFA18_Pos (18U)
2557#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2558#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2559#define CAN_FFA1R_FFA19_Pos (19U)
2560#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2561#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2562#define CAN_FFA1R_FFA20_Pos (20U)
2563#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2564#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2565#define CAN_FFA1R_FFA21_Pos (21U)
2566#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2567#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2568#define CAN_FFA1R_FFA22_Pos (22U)
2569#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2570#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2571#define CAN_FFA1R_FFA23_Pos (23U)
2572#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2573#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2574#define CAN_FFA1R_FFA24_Pos (24U)
2575#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2576#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2577#define CAN_FFA1R_FFA25_Pos (25U)
2578#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2579#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2580#define CAN_FFA1R_FFA26_Pos (26U)
2581#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2582#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2583#define CAN_FFA1R_FFA27_Pos (27U)
2584#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2585#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2587/******************* Bit definition for CAN_FA1R register *******************/
2588#define CAN_FA1R_FACT_Pos (0U)
2589#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2590#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2591#define CAN_FA1R_FACT0_Pos (0U)
2592#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2593#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2594#define CAN_FA1R_FACT1_Pos (1U)
2595#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2596#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2597#define CAN_FA1R_FACT2_Pos (2U)
2598#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2599#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2600#define CAN_FA1R_FACT3_Pos (3U)
2601#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2602#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2603#define CAN_FA1R_FACT4_Pos (4U)
2604#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2605#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2606#define CAN_FA1R_FACT5_Pos (5U)
2607#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2608#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2609#define CAN_FA1R_FACT6_Pos (6U)
2610#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2611#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2612#define CAN_FA1R_FACT7_Pos (7U)
2613#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2614#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2615#define CAN_FA1R_FACT8_Pos (8U)
2616#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2617#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2618#define CAN_FA1R_FACT9_Pos (9U)
2619#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2620#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2621#define CAN_FA1R_FACT10_Pos (10U)
2622#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2623#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2624#define CAN_FA1R_FACT11_Pos (11U)
2625#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2626#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2627#define CAN_FA1R_FACT12_Pos (12U)
2628#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2629#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2630#define CAN_FA1R_FACT13_Pos (13U)
2631#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2632#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2633#define CAN_FA1R_FACT14_Pos (14U)
2634#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2635#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2636#define CAN_FA1R_FACT15_Pos (15U)
2637#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2638#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2639#define CAN_FA1R_FACT16_Pos (16U)
2640#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2641#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2642#define CAN_FA1R_FACT17_Pos (17U)
2643#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2644#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2645#define CAN_FA1R_FACT18_Pos (18U)
2646#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2647#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2648#define CAN_FA1R_FACT19_Pos (19U)
2649#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2650#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2651#define CAN_FA1R_FACT20_Pos (20U)
2652#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2653#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2654#define CAN_FA1R_FACT21_Pos (21U)
2655#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2656#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2657#define CAN_FA1R_FACT22_Pos (22U)
2658#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2659#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2660#define CAN_FA1R_FACT23_Pos (23U)
2661#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2662#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2663#define CAN_FA1R_FACT24_Pos (24U)
2664#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2665#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2666#define CAN_FA1R_FACT25_Pos (25U)
2667#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2668#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2669#define CAN_FA1R_FACT26_Pos (26U)
2670#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2671#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2672#define CAN_FA1R_FACT27_Pos (27U)
2673#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2674#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2677/******************* Bit definition for CAN_F0R1 register *******************/
2678#define CAN_F0R1_FB0_Pos (0U)
2679#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2680#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2681#define CAN_F0R1_FB1_Pos (1U)
2682#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2683#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2684#define CAN_F0R1_FB2_Pos (2U)
2685#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2686#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2687#define CAN_F0R1_FB3_Pos (3U)
2688#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2689#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2690#define CAN_F0R1_FB4_Pos (4U)
2691#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2692#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2693#define CAN_F0R1_FB5_Pos (5U)
2694#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2695#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2696#define CAN_F0R1_FB6_Pos (6U)
2697#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2698#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2699#define CAN_F0R1_FB7_Pos (7U)
2700#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2701#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2702#define CAN_F0R1_FB8_Pos (8U)
2703#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2704#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2705#define CAN_F0R1_FB9_Pos (9U)
2706#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2707#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2708#define CAN_F0R1_FB10_Pos (10U)
2709#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2710#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2711#define CAN_F0R1_FB11_Pos (11U)
2712#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2713#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2714#define CAN_F0R1_FB12_Pos (12U)
2715#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2716#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2717#define CAN_F0R1_FB13_Pos (13U)
2718#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2719#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2720#define CAN_F0R1_FB14_Pos (14U)
2721#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2722#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2723#define CAN_F0R1_FB15_Pos (15U)
2724#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2725#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2726#define CAN_F0R1_FB16_Pos (16U)
2727#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2728#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2729#define CAN_F0R1_FB17_Pos (17U)
2730#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2731#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2732#define CAN_F0R1_FB18_Pos (18U)
2733#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2734#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2735#define CAN_F0R1_FB19_Pos (19U)
2736#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2737#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2738#define CAN_F0R1_FB20_Pos (20U)
2739#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2740#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2741#define CAN_F0R1_FB21_Pos (21U)
2742#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2743#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2744#define CAN_F0R1_FB22_Pos (22U)
2745#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2746#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2747#define CAN_F0R1_FB23_Pos (23U)
2748#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2749#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2750#define CAN_F0R1_FB24_Pos (24U)
2751#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2752#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2753#define CAN_F0R1_FB25_Pos (25U)
2754#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2755#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2756#define CAN_F0R1_FB26_Pos (26U)
2757#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2758#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2759#define CAN_F0R1_FB27_Pos (27U)
2760#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2761#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2762#define CAN_F0R1_FB28_Pos (28U)
2763#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2764#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2765#define CAN_F0R1_FB29_Pos (29U)
2766#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2767#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2768#define CAN_F0R1_FB30_Pos (30U)
2769#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2770#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2771#define CAN_F0R1_FB31_Pos (31U)
2772#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2773#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2775/******************* Bit definition for CAN_F1R1 register *******************/
2776#define CAN_F1R1_FB0_Pos (0U)
2777#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2778#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2779#define CAN_F1R1_FB1_Pos (1U)
2780#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2781#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2782#define CAN_F1R1_FB2_Pos (2U)
2783#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2784#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2785#define CAN_F1R1_FB3_Pos (3U)
2786#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2787#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2788#define CAN_F1R1_FB4_Pos (4U)
2789#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2790#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2791#define CAN_F1R1_FB5_Pos (5U)
2792#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2793#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2794#define CAN_F1R1_FB6_Pos (6U)
2795#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2796#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2797#define CAN_F1R1_FB7_Pos (7U)
2798#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2799#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2800#define CAN_F1R1_FB8_Pos (8U)
2801#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2802#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2803#define CAN_F1R1_FB9_Pos (9U)
2804#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2805#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2806#define CAN_F1R1_FB10_Pos (10U)
2807#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2808#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2809#define CAN_F1R1_FB11_Pos (11U)
2810#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2811#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2812#define CAN_F1R1_FB12_Pos (12U)
2813#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2814#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2815#define CAN_F1R1_FB13_Pos (13U)
2816#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2817#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2818#define CAN_F1R1_FB14_Pos (14U)
2819#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2820#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2821#define CAN_F1R1_FB15_Pos (15U)
2822#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2823#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2824#define CAN_F1R1_FB16_Pos (16U)
2825#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2826#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2827#define CAN_F1R1_FB17_Pos (17U)
2828#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2829#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2830#define CAN_F1R1_FB18_Pos (18U)
2831#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2832#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2833#define CAN_F1R1_FB19_Pos (19U)
2834#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2835#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2836#define CAN_F1R1_FB20_Pos (20U)
2837#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2838#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2839#define CAN_F1R1_FB21_Pos (21U)
2840#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2841#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2842#define CAN_F1R1_FB22_Pos (22U)
2843#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2844#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2845#define CAN_F1R1_FB23_Pos (23U)
2846#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2847#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2848#define CAN_F1R1_FB24_Pos (24U)
2849#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2850#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2851#define CAN_F1R1_FB25_Pos (25U)
2852#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2853#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2854#define CAN_F1R1_FB26_Pos (26U)
2855#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2856#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2857#define CAN_F1R1_FB27_Pos (27U)
2858#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
2859#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
2860#define CAN_F1R1_FB28_Pos (28U)
2861#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
2862#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
2863#define CAN_F1R1_FB29_Pos (29U)
2864#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
2865#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
2866#define CAN_F1R1_FB30_Pos (30U)
2867#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
2868#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
2869#define CAN_F1R1_FB31_Pos (31U)
2870#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
2871#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
2873/******************* Bit definition for CAN_F2R1 register *******************/
2874#define CAN_F2R1_FB0_Pos (0U)
2875#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
2876#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
2877#define CAN_F2R1_FB1_Pos (1U)
2878#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
2879#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
2880#define CAN_F2R1_FB2_Pos (2U)
2881#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
2882#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
2883#define CAN_F2R1_FB3_Pos (3U)
2884#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
2885#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
2886#define CAN_F2R1_FB4_Pos (4U)
2887#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
2888#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
2889#define CAN_F2R1_FB5_Pos (5U)
2890#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
2891#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
2892#define CAN_F2R1_FB6_Pos (6U)
2893#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
2894#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
2895#define CAN_F2R1_FB7_Pos (7U)
2896#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
2897#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
2898#define CAN_F2R1_FB8_Pos (8U)
2899#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
2900#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
2901#define CAN_F2R1_FB9_Pos (9U)
2902#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
2903#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
2904#define CAN_F2R1_FB10_Pos (10U)
2905#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
2906#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
2907#define CAN_F2R1_FB11_Pos (11U)
2908#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
2909#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
2910#define CAN_F2R1_FB12_Pos (12U)
2911#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
2912#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
2913#define CAN_F2R1_FB13_Pos (13U)
2914#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
2915#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
2916#define CAN_F2R1_FB14_Pos (14U)
2917#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
2918#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
2919#define CAN_F2R1_FB15_Pos (15U)
2920#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
2921#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
2922#define CAN_F2R1_FB16_Pos (16U)
2923#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
2924#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
2925#define CAN_F2R1_FB17_Pos (17U)
2926#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
2927#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
2928#define CAN_F2R1_FB18_Pos (18U)
2929#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
2930#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
2931#define CAN_F2R1_FB19_Pos (19U)
2932#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
2933#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
2934#define CAN_F2R1_FB20_Pos (20U)
2935#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
2936#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
2937#define CAN_F2R1_FB21_Pos (21U)
2938#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
2939#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
2940#define CAN_F2R1_FB22_Pos (22U)
2941#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
2942#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
2943#define CAN_F2R1_FB23_Pos (23U)
2944#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
2945#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
2946#define CAN_F2R1_FB24_Pos (24U)
2947#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
2948#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
2949#define CAN_F2R1_FB25_Pos (25U)
2950#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
2951#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
2952#define CAN_F2R1_FB26_Pos (26U)
2953#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
2954#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
2955#define CAN_F2R1_FB27_Pos (27U)
2956#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
2957#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
2958#define CAN_F2R1_FB28_Pos (28U)
2959#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
2960#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
2961#define CAN_F2R1_FB29_Pos (29U)
2962#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
2963#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
2964#define CAN_F2R1_FB30_Pos (30U)
2965#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
2966#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
2967#define CAN_F2R1_FB31_Pos (31U)
2968#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
2969#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
2971/******************* Bit definition for CAN_F3R1 register *******************/
2972#define CAN_F3R1_FB0_Pos (0U)
2973#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
2974#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
2975#define CAN_F3R1_FB1_Pos (1U)
2976#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
2977#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
2978#define CAN_F3R1_FB2_Pos (2U)
2979#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
2980#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
2981#define CAN_F3R1_FB3_Pos (3U)
2982#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
2983#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
2984#define CAN_F3R1_FB4_Pos (4U)
2985#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
2986#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
2987#define CAN_F3R1_FB5_Pos (5U)
2988#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
2989#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
2990#define CAN_F3R1_FB6_Pos (6U)
2991#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
2992#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
2993#define CAN_F3R1_FB7_Pos (7U)
2994#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
2995#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
2996#define CAN_F3R1_FB8_Pos (8U)
2997#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
2998#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
2999#define CAN_F3R1_FB9_Pos (9U)
3000#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3001#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3002#define CAN_F3R1_FB10_Pos (10U)
3003#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3004#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3005#define CAN_F3R1_FB11_Pos (11U)
3006#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3007#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3008#define CAN_F3R1_FB12_Pos (12U)
3009#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3010#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3011#define CAN_F3R1_FB13_Pos (13U)
3012#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3013#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3014#define CAN_F3R1_FB14_Pos (14U)
3015#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3016#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3017#define CAN_F3R1_FB15_Pos (15U)
3018#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3019#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3020#define CAN_F3R1_FB16_Pos (16U)
3021#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3022#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3023#define CAN_F3R1_FB17_Pos (17U)
3024#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3025#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3026#define CAN_F3R1_FB18_Pos (18U)
3027#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3028#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3029#define CAN_F3R1_FB19_Pos (19U)
3030#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3031#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3032#define CAN_F3R1_FB20_Pos (20U)
3033#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3034#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3035#define CAN_F3R1_FB21_Pos (21U)
3036#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3037#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3038#define CAN_F3R1_FB22_Pos (22U)
3039#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3040#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3041#define CAN_F3R1_FB23_Pos (23U)
3042#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3043#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3044#define CAN_F3R1_FB24_Pos (24U)
3045#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3046#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3047#define CAN_F3R1_FB25_Pos (25U)
3048#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3049#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3050#define CAN_F3R1_FB26_Pos (26U)
3051#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3052#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3053#define CAN_F3R1_FB27_Pos (27U)
3054#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3055#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3056#define CAN_F3R1_FB28_Pos (28U)
3057#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3058#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3059#define CAN_F3R1_FB29_Pos (29U)
3060#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3061#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3062#define CAN_F3R1_FB30_Pos (30U)
3063#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3064#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3065#define CAN_F3R1_FB31_Pos (31U)
3066#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3067#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3069/******************* Bit definition for CAN_F4R1 register *******************/
3070#define CAN_F4R1_FB0_Pos (0U)
3071#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3072#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3073#define CAN_F4R1_FB1_Pos (1U)
3074#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3075#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3076#define CAN_F4R1_FB2_Pos (2U)
3077#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3078#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3079#define CAN_F4R1_FB3_Pos (3U)
3080#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3081#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3082#define CAN_F4R1_FB4_Pos (4U)
3083#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3084#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3085#define CAN_F4R1_FB5_Pos (5U)
3086#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3087#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3088#define CAN_F4R1_FB6_Pos (6U)
3089#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3090#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3091#define CAN_F4R1_FB7_Pos (7U)
3092#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3093#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3094#define CAN_F4R1_FB8_Pos (8U)
3095#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3096#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3097#define CAN_F4R1_FB9_Pos (9U)
3098#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3099#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3100#define CAN_F4R1_FB10_Pos (10U)
3101#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3102#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3103#define CAN_F4R1_FB11_Pos (11U)
3104#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3105#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3106#define CAN_F4R1_FB12_Pos (12U)
3107#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3108#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3109#define CAN_F4R1_FB13_Pos (13U)
3110#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3111#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3112#define CAN_F4R1_FB14_Pos (14U)
3113#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3114#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3115#define CAN_F4R1_FB15_Pos (15U)
3116#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3117#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3118#define CAN_F4R1_FB16_Pos (16U)
3119#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3120#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3121#define CAN_F4R1_FB17_Pos (17U)
3122#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3123#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3124#define CAN_F4R1_FB18_Pos (18U)
3125#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3126#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3127#define CAN_F4R1_FB19_Pos (19U)
3128#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3129#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3130#define CAN_F4R1_FB20_Pos (20U)
3131#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3132#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3133#define CAN_F4R1_FB21_Pos (21U)
3134#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3135#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3136#define CAN_F4R1_FB22_Pos (22U)
3137#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3138#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3139#define CAN_F4R1_FB23_Pos (23U)
3140#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3141#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3142#define CAN_F4R1_FB24_Pos (24U)
3143#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3144#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3145#define CAN_F4R1_FB25_Pos (25U)
3146#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3147#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3148#define CAN_F4R1_FB26_Pos (26U)
3149#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3150#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3151#define CAN_F4R1_FB27_Pos (27U)
3152#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3153#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3154#define CAN_F4R1_FB28_Pos (28U)
3155#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3156#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3157#define CAN_F4R1_FB29_Pos (29U)
3158#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3159#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3160#define CAN_F4R1_FB30_Pos (30U)
3161#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3162#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3163#define CAN_F4R1_FB31_Pos (31U)
3164#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3165#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3167/******************* Bit definition for CAN_F5R1 register *******************/
3168#define CAN_F5R1_FB0_Pos (0U)
3169#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3170#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3171#define CAN_F5R1_FB1_Pos (1U)
3172#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3173#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3174#define CAN_F5R1_FB2_Pos (2U)
3175#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3176#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3177#define CAN_F5R1_FB3_Pos (3U)
3178#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3179#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3180#define CAN_F5R1_FB4_Pos (4U)
3181#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3182#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3183#define CAN_F5R1_FB5_Pos (5U)
3184#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3185#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3186#define CAN_F5R1_FB6_Pos (6U)
3187#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3188#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3189#define CAN_F5R1_FB7_Pos (7U)
3190#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3191#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3192#define CAN_F5R1_FB8_Pos (8U)
3193#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3194#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3195#define CAN_F5R1_FB9_Pos (9U)
3196#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3197#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3198#define CAN_F5R1_FB10_Pos (10U)
3199#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3200#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3201#define CAN_F5R1_FB11_Pos (11U)
3202#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3203#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3204#define CAN_F5R1_FB12_Pos (12U)
3205#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3206#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3207#define CAN_F5R1_FB13_Pos (13U)
3208#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3209#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3210#define CAN_F5R1_FB14_Pos (14U)
3211#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3212#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3213#define CAN_F5R1_FB15_Pos (15U)
3214#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3215#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3216#define CAN_F5R1_FB16_Pos (16U)
3217#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3218#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3219#define CAN_F5R1_FB17_Pos (17U)
3220#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3221#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3222#define CAN_F5R1_FB18_Pos (18U)
3223#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3224#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3225#define CAN_F5R1_FB19_Pos (19U)
3226#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3227#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3228#define CAN_F5R1_FB20_Pos (20U)
3229#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3230#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3231#define CAN_F5R1_FB21_Pos (21U)
3232#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3233#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3234#define CAN_F5R1_FB22_Pos (22U)
3235#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3236#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3237#define CAN_F5R1_FB23_Pos (23U)
3238#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3239#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3240#define CAN_F5R1_FB24_Pos (24U)
3241#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3242#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3243#define CAN_F5R1_FB25_Pos (25U)
3244#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3245#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3246#define CAN_F5R1_FB26_Pos (26U)
3247#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3248#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3249#define CAN_F5R1_FB27_Pos (27U)
3250#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3251#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3252#define CAN_F5R1_FB28_Pos (28U)
3253#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3254#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3255#define CAN_F5R1_FB29_Pos (29U)
3256#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3257#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3258#define CAN_F5R1_FB30_Pos (30U)
3259#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3260#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3261#define CAN_F5R1_FB31_Pos (31U)
3262#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3263#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3265/******************* Bit definition for CAN_F6R1 register *******************/
3266#define CAN_F6R1_FB0_Pos (0U)
3267#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3268#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3269#define CAN_F6R1_FB1_Pos (1U)
3270#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3271#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3272#define CAN_F6R1_FB2_Pos (2U)
3273#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3274#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3275#define CAN_F6R1_FB3_Pos (3U)
3276#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3277#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3278#define CAN_F6R1_FB4_Pos (4U)
3279#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3280#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3281#define CAN_F6R1_FB5_Pos (5U)
3282#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3283#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3284#define CAN_F6R1_FB6_Pos (6U)
3285#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3286#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3287#define CAN_F6R1_FB7_Pos (7U)
3288#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3289#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3290#define CAN_F6R1_FB8_Pos (8U)
3291#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3292#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3293#define CAN_F6R1_FB9_Pos (9U)
3294#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3295#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3296#define CAN_F6R1_FB10_Pos (10U)
3297#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3298#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3299#define CAN_F6R1_FB11_Pos (11U)
3300#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3301#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3302#define CAN_F6R1_FB12_Pos (12U)
3303#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3304#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3305#define CAN_F6R1_FB13_Pos (13U)
3306#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3307#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3308#define CAN_F6R1_FB14_Pos (14U)
3309#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3310#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3311#define CAN_F6R1_FB15_Pos (15U)
3312#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3313#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3314#define CAN_F6R1_FB16_Pos (16U)
3315#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3316#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3317#define CAN_F6R1_FB17_Pos (17U)
3318#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3319#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3320#define CAN_F6R1_FB18_Pos (18U)
3321#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3322#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3323#define CAN_F6R1_FB19_Pos (19U)
3324#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3325#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3326#define CAN_F6R1_FB20_Pos (20U)
3327#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3328#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3329#define CAN_F6R1_FB21_Pos (21U)
3330#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3331#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3332#define CAN_F6R1_FB22_Pos (22U)
3333#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3334#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3335#define CAN_F6R1_FB23_Pos (23U)
3336#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3337#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3338#define CAN_F6R1_FB24_Pos (24U)
3339#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3340#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3341#define CAN_F6R1_FB25_Pos (25U)
3342#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3343#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3344#define CAN_F6R1_FB26_Pos (26U)
3345#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3346#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3347#define CAN_F6R1_FB27_Pos (27U)
3348#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3349#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3350#define CAN_F6R1_FB28_Pos (28U)
3351#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3352#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3353#define CAN_F6R1_FB29_Pos (29U)
3354#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3355#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3356#define CAN_F6R1_FB30_Pos (30U)
3357#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3358#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3359#define CAN_F6R1_FB31_Pos (31U)
3360#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3361#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3363/******************* Bit definition for CAN_F7R1 register *******************/
3364#define CAN_F7R1_FB0_Pos (0U)
3365#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3366#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3367#define CAN_F7R1_FB1_Pos (1U)
3368#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3369#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3370#define CAN_F7R1_FB2_Pos (2U)
3371#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3372#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3373#define CAN_F7R1_FB3_Pos (3U)
3374#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3375#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3376#define CAN_F7R1_FB4_Pos (4U)
3377#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3378#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3379#define CAN_F7R1_FB5_Pos (5U)
3380#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3381#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3382#define CAN_F7R1_FB6_Pos (6U)
3383#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3384#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3385#define CAN_F7R1_FB7_Pos (7U)
3386#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3387#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3388#define CAN_F7R1_FB8_Pos (8U)
3389#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3390#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3391#define CAN_F7R1_FB9_Pos (9U)
3392#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3393#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3394#define CAN_F7R1_FB10_Pos (10U)
3395#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3396#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3397#define CAN_F7R1_FB11_Pos (11U)
3398#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3399#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3400#define CAN_F7R1_FB12_Pos (12U)
3401#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3402#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3403#define CAN_F7R1_FB13_Pos (13U)
3404#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3405#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3406#define CAN_F7R1_FB14_Pos (14U)
3407#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3408#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3409#define CAN_F7R1_FB15_Pos (15U)
3410#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3411#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3412#define CAN_F7R1_FB16_Pos (16U)
3413#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3414#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3415#define CAN_F7R1_FB17_Pos (17U)
3416#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3417#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3418#define CAN_F7R1_FB18_Pos (18U)
3419#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3420#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3421#define CAN_F7R1_FB19_Pos (19U)
3422#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3423#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3424#define CAN_F7R1_FB20_Pos (20U)
3425#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3426#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3427#define CAN_F7R1_FB21_Pos (21U)
3428#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3429#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3430#define CAN_F7R1_FB22_Pos (22U)
3431#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3432#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3433#define CAN_F7R1_FB23_Pos (23U)
3434#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3435#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3436#define CAN_F7R1_FB24_Pos (24U)
3437#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3438#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3439#define CAN_F7R1_FB25_Pos (25U)
3440#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3441#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3442#define CAN_F7R1_FB26_Pos (26U)
3443#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3444#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3445#define CAN_F7R1_FB27_Pos (27U)
3446#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3447#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3448#define CAN_F7R1_FB28_Pos (28U)
3449#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3450#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3451#define CAN_F7R1_FB29_Pos (29U)
3452#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3453#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3454#define CAN_F7R1_FB30_Pos (30U)
3455#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3456#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3457#define CAN_F7R1_FB31_Pos (31U)
3458#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3459#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3461/******************* Bit definition for CAN_F8R1 register *******************/
3462#define CAN_F8R1_FB0_Pos (0U)
3463#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3464#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3465#define CAN_F8R1_FB1_Pos (1U)
3466#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3467#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3468#define CAN_F8R1_FB2_Pos (2U)
3469#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3470#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3471#define CAN_F8R1_FB3_Pos (3U)
3472#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3473#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3474#define CAN_F8R1_FB4_Pos (4U)
3475#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3476#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3477#define CAN_F8R1_FB5_Pos (5U)
3478#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3479#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3480#define CAN_F8R1_FB6_Pos (6U)
3481#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3482#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3483#define CAN_F8R1_FB7_Pos (7U)
3484#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3485#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3486#define CAN_F8R1_FB8_Pos (8U)
3487#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3488#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3489#define CAN_F8R1_FB9_Pos (9U)
3490#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3491#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3492#define CAN_F8R1_FB10_Pos (10U)
3493#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3494#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3495#define CAN_F8R1_FB11_Pos (11U)
3496#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3497#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3498#define CAN_F8R1_FB12_Pos (12U)
3499#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3500#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3501#define CAN_F8R1_FB13_Pos (13U)
3502#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3503#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3504#define CAN_F8R1_FB14_Pos (14U)
3505#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3506#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3507#define CAN_F8R1_FB15_Pos (15U)
3508#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3509#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3510#define CAN_F8R1_FB16_Pos (16U)
3511#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3512#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3513#define CAN_F8R1_FB17_Pos (17U)
3514#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3515#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3516#define CAN_F8R1_FB18_Pos (18U)
3517#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3518#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3519#define CAN_F8R1_FB19_Pos (19U)
3520#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3521#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3522#define CAN_F8R1_FB20_Pos (20U)
3523#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3524#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3525#define CAN_F8R1_FB21_Pos (21U)
3526#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3527#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3528#define CAN_F8R1_FB22_Pos (22U)
3529#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3530#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3531#define CAN_F8R1_FB23_Pos (23U)
3532#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3533#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3534#define CAN_F8R1_FB24_Pos (24U)
3535#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3536#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3537#define CAN_F8R1_FB25_Pos (25U)
3538#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3539#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3540#define CAN_F8R1_FB26_Pos (26U)
3541#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3542#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3543#define CAN_F8R1_FB27_Pos (27U)
3544#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3545#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3546#define CAN_F8R1_FB28_Pos (28U)
3547#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3548#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3549#define CAN_F8R1_FB29_Pos (29U)
3550#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3551#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3552#define CAN_F8R1_FB30_Pos (30U)
3553#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3554#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3555#define CAN_F8R1_FB31_Pos (31U)
3556#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3557#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3559/******************* Bit definition for CAN_F9R1 register *******************/
3560#define CAN_F9R1_FB0_Pos (0U)
3561#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3562#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3563#define CAN_F9R1_FB1_Pos (1U)
3564#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3565#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3566#define CAN_F9R1_FB2_Pos (2U)
3567#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3568#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3569#define CAN_F9R1_FB3_Pos (3U)
3570#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3571#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3572#define CAN_F9R1_FB4_Pos (4U)
3573#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3574#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3575#define CAN_F9R1_FB5_Pos (5U)
3576#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3577#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3578#define CAN_F9R1_FB6_Pos (6U)
3579#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3580#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3581#define CAN_F9R1_FB7_Pos (7U)
3582#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3583#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3584#define CAN_F9R1_FB8_Pos (8U)
3585#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3586#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3587#define CAN_F9R1_FB9_Pos (9U)
3588#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3589#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3590#define CAN_F9R1_FB10_Pos (10U)
3591#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3592#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3593#define CAN_F9R1_FB11_Pos (11U)
3594#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3595#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3596#define CAN_F9R1_FB12_Pos (12U)
3597#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3598#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3599#define CAN_F9R1_FB13_Pos (13U)
3600#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3601#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3602#define CAN_F9R1_FB14_Pos (14U)
3603#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3604#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3605#define CAN_F9R1_FB15_Pos (15U)
3606#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3607#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3608#define CAN_F9R1_FB16_Pos (16U)
3609#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3610#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3611#define CAN_F9R1_FB17_Pos (17U)
3612#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3613#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3614#define CAN_F9R1_FB18_Pos (18U)
3615#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3616#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3617#define CAN_F9R1_FB19_Pos (19U)
3618#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3619#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3620#define CAN_F9R1_FB20_Pos (20U)
3621#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3622#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3623#define CAN_F9R1_FB21_Pos (21U)
3624#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3625#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3626#define CAN_F9R1_FB22_Pos (22U)
3627#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3628#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3629#define CAN_F9R1_FB23_Pos (23U)
3630#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3631#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3632#define CAN_F9R1_FB24_Pos (24U)
3633#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3634#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3635#define CAN_F9R1_FB25_Pos (25U)
3636#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3637#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3638#define CAN_F9R1_FB26_Pos (26U)
3639#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3640#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3641#define CAN_F9R1_FB27_Pos (27U)
3642#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3643#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3644#define CAN_F9R1_FB28_Pos (28U)
3645#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3646#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3647#define CAN_F9R1_FB29_Pos (29U)
3648#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3649#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3650#define CAN_F9R1_FB30_Pos (30U)
3651#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3652#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3653#define CAN_F9R1_FB31_Pos (31U)
3654#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3655#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3657/******************* Bit definition for CAN_F10R1 register ******************/
3658#define CAN_F10R1_FB0_Pos (0U)
3659#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3660#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3661#define CAN_F10R1_FB1_Pos (1U)
3662#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3663#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3664#define CAN_F10R1_FB2_Pos (2U)
3665#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3666#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3667#define CAN_F10R1_FB3_Pos (3U)
3668#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3669#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3670#define CAN_F10R1_FB4_Pos (4U)
3671#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3672#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3673#define CAN_F10R1_FB5_Pos (5U)
3674#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3675#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3676#define CAN_F10R1_FB6_Pos (6U)
3677#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3678#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3679#define CAN_F10R1_FB7_Pos (7U)
3680#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3681#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3682#define CAN_F10R1_FB8_Pos (8U)
3683#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3684#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3685#define CAN_F10R1_FB9_Pos (9U)
3686#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3687#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3688#define CAN_F10R1_FB10_Pos (10U)
3689#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3690#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3691#define CAN_F10R1_FB11_Pos (11U)
3692#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3693#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3694#define CAN_F10R1_FB12_Pos (12U)
3695#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3696#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3697#define CAN_F10R1_FB13_Pos (13U)
3698#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3699#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3700#define CAN_F10R1_FB14_Pos (14U)
3701#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3702#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3703#define CAN_F10R1_FB15_Pos (15U)
3704#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3705#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3706#define CAN_F10R1_FB16_Pos (16U)
3707#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3708#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3709#define CAN_F10R1_FB17_Pos (17U)
3710#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3711#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3712#define CAN_F10R1_FB18_Pos (18U)
3713#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3714#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3715#define CAN_F10R1_FB19_Pos (19U)
3716#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3717#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3718#define CAN_F10R1_FB20_Pos (20U)
3719#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3720#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3721#define CAN_F10R1_FB21_Pos (21U)
3722#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3723#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3724#define CAN_F10R1_FB22_Pos (22U)
3725#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3726#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3727#define CAN_F10R1_FB23_Pos (23U)
3728#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3729#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3730#define CAN_F10R1_FB24_Pos (24U)
3731#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3732#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3733#define CAN_F10R1_FB25_Pos (25U)
3734#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3735#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3736#define CAN_F10R1_FB26_Pos (26U)
3737#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3738#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3739#define CAN_F10R1_FB27_Pos (27U)
3740#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3741#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3742#define CAN_F10R1_FB28_Pos (28U)
3743#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3744#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3745#define CAN_F10R1_FB29_Pos (29U)
3746#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3747#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3748#define CAN_F10R1_FB30_Pos (30U)
3749#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3750#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3751#define CAN_F10R1_FB31_Pos (31U)
3752#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3753#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3755/******************* Bit definition for CAN_F11R1 register ******************/
3756#define CAN_F11R1_FB0_Pos (0U)
3757#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3758#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3759#define CAN_F11R1_FB1_Pos (1U)
3760#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3761#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3762#define CAN_F11R1_FB2_Pos (2U)
3763#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3764#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3765#define CAN_F11R1_FB3_Pos (3U)
3766#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3767#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3768#define CAN_F11R1_FB4_Pos (4U)
3769#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3770#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3771#define CAN_F11R1_FB5_Pos (5U)
3772#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3773#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3774#define CAN_F11R1_FB6_Pos (6U)
3775#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3776#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3777#define CAN_F11R1_FB7_Pos (7U)
3778#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3779#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3780#define CAN_F11R1_FB8_Pos (8U)
3781#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3782#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3783#define CAN_F11R1_FB9_Pos (9U)
3784#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3785#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3786#define CAN_F11R1_FB10_Pos (10U)
3787#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3788#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3789#define CAN_F11R1_FB11_Pos (11U)
3790#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3791#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3792#define CAN_F11R1_FB12_Pos (12U)
3793#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3794#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3795#define CAN_F11R1_FB13_Pos (13U)
3796#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3797#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3798#define CAN_F11R1_FB14_Pos (14U)
3799#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3800#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3801#define CAN_F11R1_FB15_Pos (15U)
3802#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3803#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3804#define CAN_F11R1_FB16_Pos (16U)
3805#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3806#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3807#define CAN_F11R1_FB17_Pos (17U)
3808#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3809#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3810#define CAN_F11R1_FB18_Pos (18U)
3811#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3812#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3813#define CAN_F11R1_FB19_Pos (19U)
3814#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3815#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3816#define CAN_F11R1_FB20_Pos (20U)
3817#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3818#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3819#define CAN_F11R1_FB21_Pos (21U)
3820#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3821#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3822#define CAN_F11R1_FB22_Pos (22U)
3823#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3824#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3825#define CAN_F11R1_FB23_Pos (23U)
3826#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3827#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3828#define CAN_F11R1_FB24_Pos (24U)
3829#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3830#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3831#define CAN_F11R1_FB25_Pos (25U)
3832#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3833#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3834#define CAN_F11R1_FB26_Pos (26U)
3835#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3836#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3837#define CAN_F11R1_FB27_Pos (27U)
3838#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3839#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3840#define CAN_F11R1_FB28_Pos (28U)
3841#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3842#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3843#define CAN_F11R1_FB29_Pos (29U)
3844#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3845#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3846#define CAN_F11R1_FB30_Pos (30U)
3847#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3848#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3849#define CAN_F11R1_FB31_Pos (31U)
3850#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3851#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3853/******************* Bit definition for CAN_F12R1 register ******************/
3854#define CAN_F12R1_FB0_Pos (0U)
3855#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3856#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3857#define CAN_F12R1_FB1_Pos (1U)
3858#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
3859#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
3860#define CAN_F12R1_FB2_Pos (2U)
3861#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
3862#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
3863#define CAN_F12R1_FB3_Pos (3U)
3864#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
3865#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
3866#define CAN_F12R1_FB4_Pos (4U)
3867#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
3868#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
3869#define CAN_F12R1_FB5_Pos (5U)
3870#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
3871#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
3872#define CAN_F12R1_FB6_Pos (6U)
3873#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
3874#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
3875#define CAN_F12R1_FB7_Pos (7U)
3876#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
3877#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
3878#define CAN_F12R1_FB8_Pos (8U)
3879#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
3880#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
3881#define CAN_F12R1_FB9_Pos (9U)
3882#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
3883#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
3884#define CAN_F12R1_FB10_Pos (10U)
3885#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
3886#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
3887#define CAN_F12R1_FB11_Pos (11U)
3888#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
3889#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
3890#define CAN_F12R1_FB12_Pos (12U)
3891#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
3892#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
3893#define CAN_F12R1_FB13_Pos (13U)
3894#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
3895#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
3896#define CAN_F12R1_FB14_Pos (14U)
3897#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
3898#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
3899#define CAN_F12R1_FB15_Pos (15U)
3900#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
3901#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
3902#define CAN_F12R1_FB16_Pos (16U)
3903#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
3904#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
3905#define CAN_F12R1_FB17_Pos (17U)
3906#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
3907#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
3908#define CAN_F12R1_FB18_Pos (18U)
3909#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
3910#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
3911#define CAN_F12R1_FB19_Pos (19U)
3912#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
3913#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
3914#define CAN_F12R1_FB20_Pos (20U)
3915#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
3916#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
3917#define CAN_F12R1_FB21_Pos (21U)
3918#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
3919#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
3920#define CAN_F12R1_FB22_Pos (22U)
3921#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
3922#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
3923#define CAN_F12R1_FB23_Pos (23U)
3924#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
3925#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
3926#define CAN_F12R1_FB24_Pos (24U)
3927#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
3928#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
3929#define CAN_F12R1_FB25_Pos (25U)
3930#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
3931#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
3932#define CAN_F12R1_FB26_Pos (26U)
3933#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
3934#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
3935#define CAN_F12R1_FB27_Pos (27U)
3936#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
3937#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
3938#define CAN_F12R1_FB28_Pos (28U)
3939#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
3940#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
3941#define CAN_F12R1_FB29_Pos (29U)
3942#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
3943#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
3944#define CAN_F12R1_FB30_Pos (30U)
3945#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
3946#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
3947#define CAN_F12R1_FB31_Pos (31U)
3948#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
3949#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
3951/******************* Bit definition for CAN_F13R1 register ******************/
3952#define CAN_F13R1_FB0_Pos (0U)
3953#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
3954#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
3955#define CAN_F13R1_FB1_Pos (1U)
3956#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
3957#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
3958#define CAN_F13R1_FB2_Pos (2U)
3959#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
3960#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
3961#define CAN_F13R1_FB3_Pos (3U)
3962#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
3963#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
3964#define CAN_F13R1_FB4_Pos (4U)
3965#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
3966#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
3967#define CAN_F13R1_FB5_Pos (5U)
3968#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
3969#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
3970#define CAN_F13R1_FB6_Pos (6U)
3971#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
3972#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
3973#define CAN_F13R1_FB7_Pos (7U)
3974#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
3975#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
3976#define CAN_F13R1_FB8_Pos (8U)
3977#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
3978#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
3979#define CAN_F13R1_FB9_Pos (9U)
3980#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
3981#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
3982#define CAN_F13R1_FB10_Pos (10U)
3983#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
3984#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
3985#define CAN_F13R1_FB11_Pos (11U)
3986#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
3987#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
3988#define CAN_F13R1_FB12_Pos (12U)
3989#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
3990#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
3991#define CAN_F13R1_FB13_Pos (13U)
3992#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
3993#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
3994#define CAN_F13R1_FB14_Pos (14U)
3995#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
3996#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
3997#define CAN_F13R1_FB15_Pos (15U)
3998#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
3999#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4000#define CAN_F13R1_FB16_Pos (16U)
4001#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4002#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4003#define CAN_F13R1_FB17_Pos (17U)
4004#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4005#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4006#define CAN_F13R1_FB18_Pos (18U)
4007#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4008#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4009#define CAN_F13R1_FB19_Pos (19U)
4010#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4011#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4012#define CAN_F13R1_FB20_Pos (20U)
4013#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4014#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4015#define CAN_F13R1_FB21_Pos (21U)
4016#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4017#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4018#define CAN_F13R1_FB22_Pos (22U)
4019#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4020#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4021#define CAN_F13R1_FB23_Pos (23U)
4022#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4023#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4024#define CAN_F13R1_FB24_Pos (24U)
4025#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4026#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4027#define CAN_F13R1_FB25_Pos (25U)
4028#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4029#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4030#define CAN_F13R1_FB26_Pos (26U)
4031#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4032#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4033#define CAN_F13R1_FB27_Pos (27U)
4034#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4035#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4036#define CAN_F13R1_FB28_Pos (28U)
4037#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4038#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4039#define CAN_F13R1_FB29_Pos (29U)
4040#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4041#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4042#define CAN_F13R1_FB30_Pos (30U)
4043#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4044#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4045#define CAN_F13R1_FB31_Pos (31U)
4046#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4047#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4049/******************* Bit definition for CAN_F0R2 register *******************/
4050#define CAN_F0R2_FB0_Pos (0U)
4051#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4052#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4053#define CAN_F0R2_FB1_Pos (1U)
4054#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4055#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4056#define CAN_F0R2_FB2_Pos (2U)
4057#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4058#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4059#define CAN_F0R2_FB3_Pos (3U)
4060#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4061#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4062#define CAN_F0R2_FB4_Pos (4U)
4063#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4064#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4065#define CAN_F0R2_FB5_Pos (5U)
4066#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4067#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4068#define CAN_F0R2_FB6_Pos (6U)
4069#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4070#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4071#define CAN_F0R2_FB7_Pos (7U)
4072#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4073#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4074#define CAN_F0R2_FB8_Pos (8U)
4075#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4076#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4077#define CAN_F0R2_FB9_Pos (9U)
4078#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4079#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4080#define CAN_F0R2_FB10_Pos (10U)
4081#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4082#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4083#define CAN_F0R2_FB11_Pos (11U)
4084#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4085#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4086#define CAN_F0R2_FB12_Pos (12U)
4087#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4088#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4089#define CAN_F0R2_FB13_Pos (13U)
4090#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4091#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4092#define CAN_F0R2_FB14_Pos (14U)
4093#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4094#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4095#define CAN_F0R2_FB15_Pos (15U)
4096#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4097#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4098#define CAN_F0R2_FB16_Pos (16U)
4099#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4100#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4101#define CAN_F0R2_FB17_Pos (17U)
4102#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4103#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4104#define CAN_F0R2_FB18_Pos (18U)
4105#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4106#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4107#define CAN_F0R2_FB19_Pos (19U)
4108#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4109#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4110#define CAN_F0R2_FB20_Pos (20U)
4111#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4112#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4113#define CAN_F0R2_FB21_Pos (21U)
4114#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4115#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4116#define CAN_F0R2_FB22_Pos (22U)
4117#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4118#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4119#define CAN_F0R2_FB23_Pos (23U)
4120#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4121#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4122#define CAN_F0R2_FB24_Pos (24U)
4123#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4124#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4125#define CAN_F0R2_FB25_Pos (25U)
4126#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4127#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4128#define CAN_F0R2_FB26_Pos (26U)
4129#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4130#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4131#define CAN_F0R2_FB27_Pos (27U)
4132#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4133#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4134#define CAN_F0R2_FB28_Pos (28U)
4135#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4136#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4137#define CAN_F0R2_FB29_Pos (29U)
4138#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4139#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4140#define CAN_F0R2_FB30_Pos (30U)
4141#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4142#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4143#define CAN_F0R2_FB31_Pos (31U)
4144#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4145#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4147/******************* Bit definition for CAN_F1R2 register *******************/
4148#define CAN_F1R2_FB0_Pos (0U)
4149#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4150#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4151#define CAN_F1R2_FB1_Pos (1U)
4152#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4153#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4154#define CAN_F1R2_FB2_Pos (2U)
4155#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4156#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4157#define CAN_F1R2_FB3_Pos (3U)
4158#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4159#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4160#define CAN_F1R2_FB4_Pos (4U)
4161#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4162#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4163#define CAN_F1R2_FB5_Pos (5U)
4164#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4165#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4166#define CAN_F1R2_FB6_Pos (6U)
4167#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4168#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4169#define CAN_F1R2_FB7_Pos (7U)
4170#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4171#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4172#define CAN_F1R2_FB8_Pos (8U)
4173#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4174#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4175#define CAN_F1R2_FB9_Pos (9U)
4176#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4177#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4178#define CAN_F1R2_FB10_Pos (10U)
4179#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4180#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4181#define CAN_F1R2_FB11_Pos (11U)
4182#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4183#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4184#define CAN_F1R2_FB12_Pos (12U)
4185#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4186#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4187#define CAN_F1R2_FB13_Pos (13U)
4188#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4189#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4190#define CAN_F1R2_FB14_Pos (14U)
4191#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4192#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4193#define CAN_F1R2_FB15_Pos (15U)
4194#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4195#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4196#define CAN_F1R2_FB16_Pos (16U)
4197#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4198#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4199#define CAN_F1R2_FB17_Pos (17U)
4200#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4201#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4202#define CAN_F1R2_FB18_Pos (18U)
4203#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4204#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4205#define CAN_F1R2_FB19_Pos (19U)
4206#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4207#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4208#define CAN_F1R2_FB20_Pos (20U)
4209#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4210#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4211#define CAN_F1R2_FB21_Pos (21U)
4212#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4213#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4214#define CAN_F1R2_FB22_Pos (22U)
4215#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4216#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4217#define CAN_F1R2_FB23_Pos (23U)
4218#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4219#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4220#define CAN_F1R2_FB24_Pos (24U)
4221#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4222#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4223#define CAN_F1R2_FB25_Pos (25U)
4224#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4225#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4226#define CAN_F1R2_FB26_Pos (26U)
4227#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4228#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4229#define CAN_F1R2_FB27_Pos (27U)
4230#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4231#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4232#define CAN_F1R2_FB28_Pos (28U)
4233#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4234#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4235#define CAN_F1R2_FB29_Pos (29U)
4236#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4237#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4238#define CAN_F1R2_FB30_Pos (30U)
4239#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4240#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4241#define CAN_F1R2_FB31_Pos (31U)
4242#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4243#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4245/******************* Bit definition for CAN_F2R2 register *******************/
4246#define CAN_F2R2_FB0_Pos (0U)
4247#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4248#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4249#define CAN_F2R2_FB1_Pos (1U)
4250#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4251#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4252#define CAN_F2R2_FB2_Pos (2U)
4253#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4254#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4255#define CAN_F2R2_FB3_Pos (3U)
4256#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4257#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4258#define CAN_F2R2_FB4_Pos (4U)
4259#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4260#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4261#define CAN_F2R2_FB5_Pos (5U)
4262#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4263#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4264#define CAN_F2R2_FB6_Pos (6U)
4265#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4266#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4267#define CAN_F2R2_FB7_Pos (7U)
4268#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4269#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4270#define CAN_F2R2_FB8_Pos (8U)
4271#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4272#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4273#define CAN_F2R2_FB9_Pos (9U)
4274#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4275#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4276#define CAN_F2R2_FB10_Pos (10U)
4277#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4278#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4279#define CAN_F2R2_FB11_Pos (11U)
4280#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4281#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4282#define CAN_F2R2_FB12_Pos (12U)
4283#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4284#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4285#define CAN_F2R2_FB13_Pos (13U)
4286#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4287#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4288#define CAN_F2R2_FB14_Pos (14U)
4289#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4290#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4291#define CAN_F2R2_FB15_Pos (15U)
4292#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4293#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4294#define CAN_F2R2_FB16_Pos (16U)
4295#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4296#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4297#define CAN_F2R2_FB17_Pos (17U)
4298#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4299#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4300#define CAN_F2R2_FB18_Pos (18U)
4301#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4302#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4303#define CAN_F2R2_FB19_Pos (19U)
4304#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4305#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4306#define CAN_F2R2_FB20_Pos (20U)
4307#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4308#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4309#define CAN_F2R2_FB21_Pos (21U)
4310#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4311#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4312#define CAN_F2R2_FB22_Pos (22U)
4313#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4314#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4315#define CAN_F2R2_FB23_Pos (23U)
4316#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4317#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4318#define CAN_F2R2_FB24_Pos (24U)
4319#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4320#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4321#define CAN_F2R2_FB25_Pos (25U)
4322#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4323#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4324#define CAN_F2R2_FB26_Pos (26U)
4325#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4326#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4327#define CAN_F2R2_FB27_Pos (27U)
4328#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4329#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4330#define CAN_F2R2_FB28_Pos (28U)
4331#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4332#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4333#define CAN_F2R2_FB29_Pos (29U)
4334#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4335#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4336#define CAN_F2R2_FB30_Pos (30U)
4337#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4338#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4339#define CAN_F2R2_FB31_Pos (31U)
4340#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4341#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4343/******************* Bit definition for CAN_F3R2 register *******************/
4344#define CAN_F3R2_FB0_Pos (0U)
4345#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4346#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4347#define CAN_F3R2_FB1_Pos (1U)
4348#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4349#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4350#define CAN_F3R2_FB2_Pos (2U)
4351#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4352#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4353#define CAN_F3R2_FB3_Pos (3U)
4354#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4355#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4356#define CAN_F3R2_FB4_Pos (4U)
4357#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4358#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4359#define CAN_F3R2_FB5_Pos (5U)
4360#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4361#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4362#define CAN_F3R2_FB6_Pos (6U)
4363#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4364#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4365#define CAN_F3R2_FB7_Pos (7U)
4366#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4367#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4368#define CAN_F3R2_FB8_Pos (8U)
4369#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4370#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4371#define CAN_F3R2_FB9_Pos (9U)
4372#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4373#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4374#define CAN_F3R2_FB10_Pos (10U)
4375#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4376#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4377#define CAN_F3R2_FB11_Pos (11U)
4378#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4379#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4380#define CAN_F3R2_FB12_Pos (12U)
4381#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4382#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4383#define CAN_F3R2_FB13_Pos (13U)
4384#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4385#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4386#define CAN_F3R2_FB14_Pos (14U)
4387#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4388#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4389#define CAN_F3R2_FB15_Pos (15U)
4390#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4391#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4392#define CAN_F3R2_FB16_Pos (16U)
4393#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4394#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4395#define CAN_F3R2_FB17_Pos (17U)
4396#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4397#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4398#define CAN_F3R2_FB18_Pos (18U)
4399#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4400#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4401#define CAN_F3R2_FB19_Pos (19U)
4402#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4403#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4404#define CAN_F3R2_FB20_Pos (20U)
4405#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4406#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4407#define CAN_F3R2_FB21_Pos (21U)
4408#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4409#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4410#define CAN_F3R2_FB22_Pos (22U)
4411#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4412#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4413#define CAN_F3R2_FB23_Pos (23U)
4414#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4415#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4416#define CAN_F3R2_FB24_Pos (24U)
4417#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4418#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4419#define CAN_F3R2_FB25_Pos (25U)
4420#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4421#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4422#define CAN_F3R2_FB26_Pos (26U)
4423#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4424#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4425#define CAN_F3R2_FB27_Pos (27U)
4426#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4427#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4428#define CAN_F3R2_FB28_Pos (28U)
4429#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4430#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4431#define CAN_F3R2_FB29_Pos (29U)
4432#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4433#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4434#define CAN_F3R2_FB30_Pos (30U)
4435#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4436#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4437#define CAN_F3R2_FB31_Pos (31U)
4438#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4439#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4441/******************* Bit definition for CAN_F4R2 register *******************/
4442#define CAN_F4R2_FB0_Pos (0U)
4443#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4444#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4445#define CAN_F4R2_FB1_Pos (1U)
4446#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4447#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4448#define CAN_F4R2_FB2_Pos (2U)
4449#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4450#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4451#define CAN_F4R2_FB3_Pos (3U)
4452#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4453#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4454#define CAN_F4R2_FB4_Pos (4U)
4455#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4456#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4457#define CAN_F4R2_FB5_Pos (5U)
4458#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4459#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4460#define CAN_F4R2_FB6_Pos (6U)
4461#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4462#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4463#define CAN_F4R2_FB7_Pos (7U)
4464#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4465#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4466#define CAN_F4R2_FB8_Pos (8U)
4467#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4468#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4469#define CAN_F4R2_FB9_Pos (9U)
4470#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4471#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4472#define CAN_F4R2_FB10_Pos (10U)
4473#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4474#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4475#define CAN_F4R2_FB11_Pos (11U)
4476#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4477#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4478#define CAN_F4R2_FB12_Pos (12U)
4479#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4480#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4481#define CAN_F4R2_FB13_Pos (13U)
4482#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4483#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4484#define CAN_F4R2_FB14_Pos (14U)
4485#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4486#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4487#define CAN_F4R2_FB15_Pos (15U)
4488#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4489#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4490#define CAN_F4R2_FB16_Pos (16U)
4491#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4492#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4493#define CAN_F4R2_FB17_Pos (17U)
4494#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4495#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4496#define CAN_F4R2_FB18_Pos (18U)
4497#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4498#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4499#define CAN_F4R2_FB19_Pos (19U)
4500#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4501#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4502#define CAN_F4R2_FB20_Pos (20U)
4503#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4504#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4505#define CAN_F4R2_FB21_Pos (21U)
4506#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4507#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4508#define CAN_F4R2_FB22_Pos (22U)
4509#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4510#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4511#define CAN_F4R2_FB23_Pos (23U)
4512#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4513#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4514#define CAN_F4R2_FB24_Pos (24U)
4515#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4516#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4517#define CAN_F4R2_FB25_Pos (25U)
4518#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4519#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4520#define CAN_F4R2_FB26_Pos (26U)
4521#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4522#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4523#define CAN_F4R2_FB27_Pos (27U)
4524#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4525#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4526#define CAN_F4R2_FB28_Pos (28U)
4527#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4528#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4529#define CAN_F4R2_FB29_Pos (29U)
4530#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4531#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4532#define CAN_F4R2_FB30_Pos (30U)
4533#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4534#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4535#define CAN_F4R2_FB31_Pos (31U)
4536#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4537#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4539/******************* Bit definition for CAN_F5R2 register *******************/
4540#define CAN_F5R2_FB0_Pos (0U)
4541#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4542#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4543#define CAN_F5R2_FB1_Pos (1U)
4544#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4545#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4546#define CAN_F5R2_FB2_Pos (2U)
4547#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4548#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4549#define CAN_F5R2_FB3_Pos (3U)
4550#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4551#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4552#define CAN_F5R2_FB4_Pos (4U)
4553#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4554#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4555#define CAN_F5R2_FB5_Pos (5U)
4556#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4557#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4558#define CAN_F5R2_FB6_Pos (6U)
4559#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4560#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4561#define CAN_F5R2_FB7_Pos (7U)
4562#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4563#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4564#define CAN_F5R2_FB8_Pos (8U)
4565#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4566#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4567#define CAN_F5R2_FB9_Pos (9U)
4568#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4569#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4570#define CAN_F5R2_FB10_Pos (10U)
4571#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4572#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4573#define CAN_F5R2_FB11_Pos (11U)
4574#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4575#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4576#define CAN_F5R2_FB12_Pos (12U)
4577#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4578#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4579#define CAN_F5R2_FB13_Pos (13U)
4580#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4581#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4582#define CAN_F5R2_FB14_Pos (14U)
4583#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4584#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4585#define CAN_F5R2_FB15_Pos (15U)
4586#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4587#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4588#define CAN_F5R2_FB16_Pos (16U)
4589#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4590#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4591#define CAN_F5R2_FB17_Pos (17U)
4592#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4593#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4594#define CAN_F5R2_FB18_Pos (18U)
4595#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4596#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4597#define CAN_F5R2_FB19_Pos (19U)
4598#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4599#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4600#define CAN_F5R2_FB20_Pos (20U)
4601#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4602#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4603#define CAN_F5R2_FB21_Pos (21U)
4604#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4605#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4606#define CAN_F5R2_FB22_Pos (22U)
4607#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4608#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4609#define CAN_F5R2_FB23_Pos (23U)
4610#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4611#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4612#define CAN_F5R2_FB24_Pos (24U)
4613#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4614#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4615#define CAN_F5R2_FB25_Pos (25U)
4616#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4617#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4618#define CAN_F5R2_FB26_Pos (26U)
4619#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4620#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4621#define CAN_F5R2_FB27_Pos (27U)
4622#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4623#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4624#define CAN_F5R2_FB28_Pos (28U)
4625#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4626#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4627#define CAN_F5R2_FB29_Pos (29U)
4628#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4629#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4630#define CAN_F5R2_FB30_Pos (30U)
4631#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4632#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4633#define CAN_F5R2_FB31_Pos (31U)
4634#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4635#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4637/******************* Bit definition for CAN_F6R2 register *******************/
4638#define CAN_F6R2_FB0_Pos (0U)
4639#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4640#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4641#define CAN_F6R2_FB1_Pos (1U)
4642#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4643#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4644#define CAN_F6R2_FB2_Pos (2U)
4645#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4646#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4647#define CAN_F6R2_FB3_Pos (3U)
4648#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4649#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4650#define CAN_F6R2_FB4_Pos (4U)
4651#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4652#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4653#define CAN_F6R2_FB5_Pos (5U)
4654#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4655#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4656#define CAN_F6R2_FB6_Pos (6U)
4657#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4658#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4659#define CAN_F6R2_FB7_Pos (7U)
4660#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4661#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4662#define CAN_F6R2_FB8_Pos (8U)
4663#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4664#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4665#define CAN_F6R2_FB9_Pos (9U)
4666#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4667#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4668#define CAN_F6R2_FB10_Pos (10U)
4669#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4670#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4671#define CAN_F6R2_FB11_Pos (11U)
4672#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4673#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4674#define CAN_F6R2_FB12_Pos (12U)
4675#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4676#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4677#define CAN_F6R2_FB13_Pos (13U)
4678#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4679#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4680#define CAN_F6R2_FB14_Pos (14U)
4681#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4682#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4683#define CAN_F6R2_FB15_Pos (15U)
4684#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4685#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4686#define CAN_F6R2_FB16_Pos (16U)
4687#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4688#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4689#define CAN_F6R2_FB17_Pos (17U)
4690#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4691#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4692#define CAN_F6R2_FB18_Pos (18U)
4693#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4694#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4695#define CAN_F6R2_FB19_Pos (19U)
4696#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4697#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4698#define CAN_F6R2_FB20_Pos (20U)
4699#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4700#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4701#define CAN_F6R2_FB21_Pos (21U)
4702#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4703#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4704#define CAN_F6R2_FB22_Pos (22U)
4705#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4706#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4707#define CAN_F6R2_FB23_Pos (23U)
4708#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4709#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4710#define CAN_F6R2_FB24_Pos (24U)
4711#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4712#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4713#define CAN_F6R2_FB25_Pos (25U)
4714#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4715#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4716#define CAN_F6R2_FB26_Pos (26U)
4717#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4718#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4719#define CAN_F6R2_FB27_Pos (27U)
4720#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4721#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4722#define CAN_F6R2_FB28_Pos (28U)
4723#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4724#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4725#define CAN_F6R2_FB29_Pos (29U)
4726#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4727#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4728#define CAN_F6R2_FB30_Pos (30U)
4729#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4730#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4731#define CAN_F6R2_FB31_Pos (31U)
4732#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4733#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4735/******************* Bit definition for CAN_F7R2 register *******************/
4736#define CAN_F7R2_FB0_Pos (0U)
4737#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4738#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4739#define CAN_F7R2_FB1_Pos (1U)
4740#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4741#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4742#define CAN_F7R2_FB2_Pos (2U)
4743#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4744#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4745#define CAN_F7R2_FB3_Pos (3U)
4746#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4747#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4748#define CAN_F7R2_FB4_Pos (4U)
4749#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4750#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4751#define CAN_F7R2_FB5_Pos (5U)
4752#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4753#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4754#define CAN_F7R2_FB6_Pos (6U)
4755#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4756#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4757#define CAN_F7R2_FB7_Pos (7U)
4758#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4759#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4760#define CAN_F7R2_FB8_Pos (8U)
4761#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4762#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4763#define CAN_F7R2_FB9_Pos (9U)
4764#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4765#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4766#define CAN_F7R2_FB10_Pos (10U)
4767#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4768#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4769#define CAN_F7R2_FB11_Pos (11U)
4770#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4771#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4772#define CAN_F7R2_FB12_Pos (12U)
4773#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4774#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4775#define CAN_F7R2_FB13_Pos (13U)
4776#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4777#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4778#define CAN_F7R2_FB14_Pos (14U)
4779#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4780#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4781#define CAN_F7R2_FB15_Pos (15U)
4782#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4783#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4784#define CAN_F7R2_FB16_Pos (16U)
4785#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4786#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4787#define CAN_F7R2_FB17_Pos (17U)
4788#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4789#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4790#define CAN_F7R2_FB18_Pos (18U)
4791#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4792#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4793#define CAN_F7R2_FB19_Pos (19U)
4794#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4795#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4796#define CAN_F7R2_FB20_Pos (20U)
4797#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4798#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4799#define CAN_F7R2_FB21_Pos (21U)
4800#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4801#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4802#define CAN_F7R2_FB22_Pos (22U)
4803#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4804#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4805#define CAN_F7R2_FB23_Pos (23U)
4806#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4807#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4808#define CAN_F7R2_FB24_Pos (24U)
4809#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4810#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4811#define CAN_F7R2_FB25_Pos (25U)
4812#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4813#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4814#define CAN_F7R2_FB26_Pos (26U)
4815#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4816#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4817#define CAN_F7R2_FB27_Pos (27U)
4818#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4819#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4820#define CAN_F7R2_FB28_Pos (28U)
4821#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4822#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4823#define CAN_F7R2_FB29_Pos (29U)
4824#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4825#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4826#define CAN_F7R2_FB30_Pos (30U)
4827#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4828#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4829#define CAN_F7R2_FB31_Pos (31U)
4830#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4831#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4833/******************* Bit definition for CAN_F8R2 register *******************/
4834#define CAN_F8R2_FB0_Pos (0U)
4835#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4836#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4837#define CAN_F8R2_FB1_Pos (1U)
4838#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4839#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4840#define CAN_F8R2_FB2_Pos (2U)
4841#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4842#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4843#define CAN_F8R2_FB3_Pos (3U)
4844#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4845#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4846#define CAN_F8R2_FB4_Pos (4U)
4847#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4848#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4849#define CAN_F8R2_FB5_Pos (5U)
4850#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4851#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4852#define CAN_F8R2_FB6_Pos (6U)
4853#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4854#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4855#define CAN_F8R2_FB7_Pos (7U)
4856#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4857#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4858#define CAN_F8R2_FB8_Pos (8U)
4859#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
4860#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
4861#define CAN_F8R2_FB9_Pos (9U)
4862#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
4863#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
4864#define CAN_F8R2_FB10_Pos (10U)
4865#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
4866#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
4867#define CAN_F8R2_FB11_Pos (11U)
4868#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
4869#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
4870#define CAN_F8R2_FB12_Pos (12U)
4871#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
4872#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
4873#define CAN_F8R2_FB13_Pos (13U)
4874#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
4875#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
4876#define CAN_F8R2_FB14_Pos (14U)
4877#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
4878#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
4879#define CAN_F8R2_FB15_Pos (15U)
4880#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
4881#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
4882#define CAN_F8R2_FB16_Pos (16U)
4883#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
4884#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
4885#define CAN_F8R2_FB17_Pos (17U)
4886#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
4887#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
4888#define CAN_F8R2_FB18_Pos (18U)
4889#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
4890#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
4891#define CAN_F8R2_FB19_Pos (19U)
4892#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
4893#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
4894#define CAN_F8R2_FB20_Pos (20U)
4895#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
4896#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
4897#define CAN_F8R2_FB21_Pos (21U)
4898#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
4899#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
4900#define CAN_F8R2_FB22_Pos (22U)
4901#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
4902#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
4903#define CAN_F8R2_FB23_Pos (23U)
4904#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
4905#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
4906#define CAN_F8R2_FB24_Pos (24U)
4907#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
4908#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
4909#define CAN_F8R2_FB25_Pos (25U)
4910#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
4911#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
4912#define CAN_F8R2_FB26_Pos (26U)
4913#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
4914#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
4915#define CAN_F8R2_FB27_Pos (27U)
4916#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
4917#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
4918#define CAN_F8R2_FB28_Pos (28U)
4919#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
4920#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
4921#define CAN_F8R2_FB29_Pos (29U)
4922#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
4923#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
4924#define CAN_F8R2_FB30_Pos (30U)
4925#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
4926#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
4927#define CAN_F8R2_FB31_Pos (31U)
4928#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
4929#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
4931/******************* Bit definition for CAN_F9R2 register *******************/
4932#define CAN_F9R2_FB0_Pos (0U)
4933#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
4934#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
4935#define CAN_F9R2_FB1_Pos (1U)
4936#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
4937#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
4938#define CAN_F9R2_FB2_Pos (2U)
4939#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
4940#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
4941#define CAN_F9R2_FB3_Pos (3U)
4942#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
4943#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
4944#define CAN_F9R2_FB4_Pos (4U)
4945#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
4946#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
4947#define CAN_F9R2_FB5_Pos (5U)
4948#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
4949#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
4950#define CAN_F9R2_FB6_Pos (6U)
4951#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
4952#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
4953#define CAN_F9R2_FB7_Pos (7U)
4954#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
4955#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
4956#define CAN_F9R2_FB8_Pos (8U)
4957#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
4958#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
4959#define CAN_F9R2_FB9_Pos (9U)
4960#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
4961#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
4962#define CAN_F9R2_FB10_Pos (10U)
4963#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
4964#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
4965#define CAN_F9R2_FB11_Pos (11U)
4966#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
4967#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
4968#define CAN_F9R2_FB12_Pos (12U)
4969#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
4970#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
4971#define CAN_F9R2_FB13_Pos (13U)
4972#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
4973#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
4974#define CAN_F9R2_FB14_Pos (14U)
4975#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
4976#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
4977#define CAN_F9R2_FB15_Pos (15U)
4978#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
4979#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
4980#define CAN_F9R2_FB16_Pos (16U)
4981#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
4982#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
4983#define CAN_F9R2_FB17_Pos (17U)
4984#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
4985#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
4986#define CAN_F9R2_FB18_Pos (18U)
4987#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
4988#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
4989#define CAN_F9R2_FB19_Pos (19U)
4990#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
4991#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
4992#define CAN_F9R2_FB20_Pos (20U)
4993#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
4994#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
4995#define CAN_F9R2_FB21_Pos (21U)
4996#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
4997#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
4998#define CAN_F9R2_FB22_Pos (22U)
4999#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5000#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5001#define CAN_F9R2_FB23_Pos (23U)
5002#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5003#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5004#define CAN_F9R2_FB24_Pos (24U)
5005#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5006#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5007#define CAN_F9R2_FB25_Pos (25U)
5008#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5009#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5010#define CAN_F9R2_FB26_Pos (26U)
5011#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5012#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5013#define CAN_F9R2_FB27_Pos (27U)
5014#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5015#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5016#define CAN_F9R2_FB28_Pos (28U)
5017#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5018#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5019#define CAN_F9R2_FB29_Pos (29U)
5020#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5021#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5022#define CAN_F9R2_FB30_Pos (30U)
5023#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5024#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5025#define CAN_F9R2_FB31_Pos (31U)
5026#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5027#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5029/******************* Bit definition for CAN_F10R2 register ******************/
5030#define CAN_F10R2_FB0_Pos (0U)
5031#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5032#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5033#define CAN_F10R2_FB1_Pos (1U)
5034#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5035#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5036#define CAN_F10R2_FB2_Pos (2U)
5037#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5038#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5039#define CAN_F10R2_FB3_Pos (3U)
5040#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5041#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5042#define CAN_F10R2_FB4_Pos (4U)
5043#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5044#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5045#define CAN_F10R2_FB5_Pos (5U)
5046#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5047#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5048#define CAN_F10R2_FB6_Pos (6U)
5049#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5050#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5051#define CAN_F10R2_FB7_Pos (7U)
5052#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5053#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5054#define CAN_F10R2_FB8_Pos (8U)
5055#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5056#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5057#define CAN_F10R2_FB9_Pos (9U)
5058#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5059#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5060#define CAN_F10R2_FB10_Pos (10U)
5061#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5062#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5063#define CAN_F10R2_FB11_Pos (11U)
5064#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5065#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5066#define CAN_F10R2_FB12_Pos (12U)
5067#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5068#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5069#define CAN_F10R2_FB13_Pos (13U)
5070#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5071#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5072#define CAN_F10R2_FB14_Pos (14U)
5073#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5074#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5075#define CAN_F10R2_FB15_Pos (15U)
5076#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5077#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5078#define CAN_F10R2_FB16_Pos (16U)
5079#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5080#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5081#define CAN_F10R2_FB17_Pos (17U)
5082#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5083#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5084#define CAN_F10R2_FB18_Pos (18U)
5085#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5086#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5087#define CAN_F10R2_FB19_Pos (19U)
5088#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5089#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5090#define CAN_F10R2_FB20_Pos (20U)
5091#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5092#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5093#define CAN_F10R2_FB21_Pos (21U)
5094#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5095#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5096#define CAN_F10R2_FB22_Pos (22U)
5097#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5098#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5099#define CAN_F10R2_FB23_Pos (23U)
5100#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5101#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5102#define CAN_F10R2_FB24_Pos (24U)
5103#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5104#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5105#define CAN_F10R2_FB25_Pos (25U)
5106#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5107#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5108#define CAN_F10R2_FB26_Pos (26U)
5109#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5110#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5111#define CAN_F10R2_FB27_Pos (27U)
5112#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5113#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5114#define CAN_F10R2_FB28_Pos (28U)
5115#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5116#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5117#define CAN_F10R2_FB29_Pos (29U)
5118#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5119#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5120#define CAN_F10R2_FB30_Pos (30U)
5121#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5122#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5123#define CAN_F10R2_FB31_Pos (31U)
5124#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5125#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5127/******************* Bit definition for CAN_F11R2 register ******************/
5128#define CAN_F11R2_FB0_Pos (0U)
5129#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5130#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5131#define CAN_F11R2_FB1_Pos (1U)
5132#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5133#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5134#define CAN_F11R2_FB2_Pos (2U)
5135#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5136#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5137#define CAN_F11R2_FB3_Pos (3U)
5138#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5139#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5140#define CAN_F11R2_FB4_Pos (4U)
5141#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5142#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5143#define CAN_F11R2_FB5_Pos (5U)
5144#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5145#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5146#define CAN_F11R2_FB6_Pos (6U)
5147#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5148#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5149#define CAN_F11R2_FB7_Pos (7U)
5150#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5151#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5152#define CAN_F11R2_FB8_Pos (8U)
5153#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5154#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5155#define CAN_F11R2_FB9_Pos (9U)
5156#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5157#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5158#define CAN_F11R2_FB10_Pos (10U)
5159#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5160#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5161#define CAN_F11R2_FB11_Pos (11U)
5162#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5163#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5164#define CAN_F11R2_FB12_Pos (12U)
5165#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5166#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5167#define CAN_F11R2_FB13_Pos (13U)
5168#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5169#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5170#define CAN_F11R2_FB14_Pos (14U)
5171#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5172#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5173#define CAN_F11R2_FB15_Pos (15U)
5174#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5175#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5176#define CAN_F11R2_FB16_Pos (16U)
5177#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5178#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5179#define CAN_F11R2_FB17_Pos (17U)
5180#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5181#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5182#define CAN_F11R2_FB18_Pos (18U)
5183#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5184#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5185#define CAN_F11R2_FB19_Pos (19U)
5186#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5187#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5188#define CAN_F11R2_FB20_Pos (20U)
5189#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5190#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5191#define CAN_F11R2_FB21_Pos (21U)
5192#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5193#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5194#define CAN_F11R2_FB22_Pos (22U)
5195#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5196#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5197#define CAN_F11R2_FB23_Pos (23U)
5198#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5199#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5200#define CAN_F11R2_FB24_Pos (24U)
5201#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5202#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5203#define CAN_F11R2_FB25_Pos (25U)
5204#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5205#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5206#define CAN_F11R2_FB26_Pos (26U)
5207#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5208#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5209#define CAN_F11R2_FB27_Pos (27U)
5210#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5211#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5212#define CAN_F11R2_FB28_Pos (28U)
5213#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5214#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5215#define CAN_F11R2_FB29_Pos (29U)
5216#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5217#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5218#define CAN_F11R2_FB30_Pos (30U)
5219#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5220#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5221#define CAN_F11R2_FB31_Pos (31U)
5222#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5223#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5225/******************* Bit definition for CAN_F12R2 register ******************/
5226#define CAN_F12R2_FB0_Pos (0U)
5227#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5228#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5229#define CAN_F12R2_FB1_Pos (1U)
5230#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5231#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5232#define CAN_F12R2_FB2_Pos (2U)
5233#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5234#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5235#define CAN_F12R2_FB3_Pos (3U)
5236#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5237#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5238#define CAN_F12R2_FB4_Pos (4U)
5239#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5240#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5241#define CAN_F12R2_FB5_Pos (5U)
5242#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5243#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5244#define CAN_F12R2_FB6_Pos (6U)
5245#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5246#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5247#define CAN_F12R2_FB7_Pos (7U)
5248#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5249#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5250#define CAN_F12R2_FB8_Pos (8U)
5251#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5252#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5253#define CAN_F12R2_FB9_Pos (9U)
5254#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5255#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5256#define CAN_F12R2_FB10_Pos (10U)
5257#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5258#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5259#define CAN_F12R2_FB11_Pos (11U)
5260#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5261#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5262#define CAN_F12R2_FB12_Pos (12U)
5263#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5264#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5265#define CAN_F12R2_FB13_Pos (13U)
5266#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5267#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5268#define CAN_F12R2_FB14_Pos (14U)
5269#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5270#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5271#define CAN_F12R2_FB15_Pos (15U)
5272#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5273#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5274#define CAN_F12R2_FB16_Pos (16U)
5275#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5276#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5277#define CAN_F12R2_FB17_Pos (17U)
5278#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5279#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5280#define CAN_F12R2_FB18_Pos (18U)
5281#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5282#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5283#define CAN_F12R2_FB19_Pos (19U)
5284#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5285#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5286#define CAN_F12R2_FB20_Pos (20U)
5287#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5288#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5289#define CAN_F12R2_FB21_Pos (21U)
5290#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5291#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5292#define CAN_F12R2_FB22_Pos (22U)
5293#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5294#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5295#define CAN_F12R2_FB23_Pos (23U)
5296#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5297#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5298#define CAN_F12R2_FB24_Pos (24U)
5299#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5300#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5301#define CAN_F12R2_FB25_Pos (25U)
5302#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5303#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5304#define CAN_F12R2_FB26_Pos (26U)
5305#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5306#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5307#define CAN_F12R2_FB27_Pos (27U)
5308#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5309#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5310#define CAN_F12R2_FB28_Pos (28U)
5311#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5312#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5313#define CAN_F12R2_FB29_Pos (29U)
5314#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5315#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5316#define CAN_F12R2_FB30_Pos (30U)
5317#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5318#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5319#define CAN_F12R2_FB31_Pos (31U)
5320#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5321#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5323/******************* Bit definition for CAN_F13R2 register ******************/
5324#define CAN_F13R2_FB0_Pos (0U)
5325#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5326#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5327#define CAN_F13R2_FB1_Pos (1U)
5328#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5329#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5330#define CAN_F13R2_FB2_Pos (2U)
5331#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5332#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5333#define CAN_F13R2_FB3_Pos (3U)
5334#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5335#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5336#define CAN_F13R2_FB4_Pos (4U)
5337#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5338#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5339#define CAN_F13R2_FB5_Pos (5U)
5340#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5341#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5342#define CAN_F13R2_FB6_Pos (6U)
5343#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5344#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5345#define CAN_F13R2_FB7_Pos (7U)
5346#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5347#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5348#define CAN_F13R2_FB8_Pos (8U)
5349#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5350#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5351#define CAN_F13R2_FB9_Pos (9U)
5352#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5353#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5354#define CAN_F13R2_FB10_Pos (10U)
5355#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5356#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5357#define CAN_F13R2_FB11_Pos (11U)
5358#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5359#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5360#define CAN_F13R2_FB12_Pos (12U)
5361#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5362#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5363#define CAN_F13R2_FB13_Pos (13U)
5364#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5365#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5366#define CAN_F13R2_FB14_Pos (14U)
5367#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5368#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5369#define CAN_F13R2_FB15_Pos (15U)
5370#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5371#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5372#define CAN_F13R2_FB16_Pos (16U)
5373#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5374#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5375#define CAN_F13R2_FB17_Pos (17U)
5376#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5377#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5378#define CAN_F13R2_FB18_Pos (18U)
5379#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5380#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5381#define CAN_F13R2_FB19_Pos (19U)
5382#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5383#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5384#define CAN_F13R2_FB20_Pos (20U)
5385#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5386#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5387#define CAN_F13R2_FB21_Pos (21U)
5388#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5389#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5390#define CAN_F13R2_FB22_Pos (22U)
5391#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5392#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5393#define CAN_F13R2_FB23_Pos (23U)
5394#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5395#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5396#define CAN_F13R2_FB24_Pos (24U)
5397#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5398#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5399#define CAN_F13R2_FB25_Pos (25U)
5400#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5401#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5402#define CAN_F13R2_FB26_Pos (26U)
5403#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5404#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5405#define CAN_F13R2_FB27_Pos (27U)
5406#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5407#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5408#define CAN_F13R2_FB28_Pos (28U)
5409#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5410#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5411#define CAN_F13R2_FB29_Pos (29U)
5412#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5413#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5414#define CAN_F13R2_FB30_Pos (30U)
5415#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5416#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5417#define CAN_F13R2_FB31_Pos (31U)
5418#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5419#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5421/******************************************************************************/
5422/* */
5423/* CRC calculation unit */
5424/* */
5425/******************************************************************************/
5426/******************* Bit definition for CRC_DR register *********************/
5427#define CRC_DR_DR_Pos (0U)
5428#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5429#define CRC_DR_DR CRC_DR_DR_Msk
5432/******************* Bit definition for CRC_IDR register ********************/
5433#define CRC_IDR_IDR_Pos (0U)
5434#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5435#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5438/******************** Bit definition for CRC_CR register ********************/
5439#define CRC_CR_RESET_Pos (0U)
5440#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5441#define CRC_CR_RESET CRC_CR_RESET_Msk
5443/******************************************************************************/
5444/* */
5445/* Digital to Analog Converter */
5446/* */
5447/******************************************************************************/
5448/*
5449 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5450 */
5451#define DAC_CHANNEL2_SUPPORT
5452/******************** Bit definition for DAC_CR register ********************/
5453#define DAC_CR_EN1_Pos (0U)
5454#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5455#define DAC_CR_EN1 DAC_CR_EN1_Msk
5456#define DAC_CR_BOFF1_Pos (1U)
5457#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5458#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5459#define DAC_CR_TEN1_Pos (2U)
5460#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5461#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5463#define DAC_CR_TSEL1_Pos (3U)
5464#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5465#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5466#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5467#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5468#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5470#define DAC_CR_WAVE1_Pos (6U)
5471#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5472#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5473#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5474#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5476#define DAC_CR_MAMP1_Pos (8U)
5477#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5478#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5479#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5480#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5481#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5482#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5484#define DAC_CR_DMAEN1_Pos (12U)
5485#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5486#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5487#define DAC_CR_DMAUDRIE1_Pos (13U)
5488#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5489#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5490#define DAC_CR_EN2_Pos (16U)
5491#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5492#define DAC_CR_EN2 DAC_CR_EN2_Msk
5493#define DAC_CR_BOFF2_Pos (17U)
5494#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5495#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5496#define DAC_CR_TEN2_Pos (18U)
5497#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5498#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5500#define DAC_CR_TSEL2_Pos (19U)
5501#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5502#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5503#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5504#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5505#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5507#define DAC_CR_WAVE2_Pos (22U)
5508#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5509#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5510#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5511#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5513#define DAC_CR_MAMP2_Pos (24U)
5514#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5515#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5516#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5517#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5518#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5519#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5521#define DAC_CR_DMAEN2_Pos (28U)
5522#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5523#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5524#define DAC_CR_DMAUDRIE2_Pos (29U)
5525#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5526#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5528/***************** Bit definition for DAC_SWTRIGR register ******************/
5529#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5530#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5531#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5532#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5533#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5534#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5536/***************** Bit definition for DAC_DHR12R1 register ******************/
5537#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5538#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5539#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5541/***************** Bit definition for DAC_DHR12L1 register ******************/
5542#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5543#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5544#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5546/****************** Bit definition for DAC_DHR8R1 register ******************/
5547#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5548#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5549#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5551/***************** Bit definition for DAC_DHR12R2 register ******************/
5552#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5553#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5554#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5556/***************** Bit definition for DAC_DHR12L2 register ******************/
5557#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5558#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5559#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5561/****************** Bit definition for DAC_DHR8R2 register ******************/
5562#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5563#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5564#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5566/***************** Bit definition for DAC_DHR12RD register ******************/
5567#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5568#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5569#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5570#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5571#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5572#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5574/***************** Bit definition for DAC_DHR12LD register ******************/
5575#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5576#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5577#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5578#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5579#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5580#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5582/****************** Bit definition for DAC_DHR8RD register ******************/
5583#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5584#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5585#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5586#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5587#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5588#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5590/******************* Bit definition for DAC_DOR1 register *******************/
5591#define DAC_DOR1_DACC1DOR_Pos (0U)
5592#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5593#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5595/******************* Bit definition for DAC_DOR2 register *******************/
5596#define DAC_DOR2_DACC2DOR_Pos (0U)
5597#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5598#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5600/******************** Bit definition for DAC_SR register ********************/
5601#define DAC_SR_DMAUDR1_Pos (13U)
5602#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5603#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5604#define DAC_SR_DMAUDR2_Pos (29U)
5605#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5606#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5608/******************************************************************************/
5609/* */
5610/* DCMI */
5611/* */
5612/******************************************************************************/
5613/******************** Bits definition for DCMI_CR register ******************/
5614#define DCMI_CR_CAPTURE_Pos (0U)
5615#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
5616#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5617#define DCMI_CR_CM_Pos (1U)
5618#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
5619#define DCMI_CR_CM DCMI_CR_CM_Msk
5620#define DCMI_CR_CROP_Pos (2U)
5621#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
5622#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5623#define DCMI_CR_JPEG_Pos (3U)
5624#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
5625#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5626#define DCMI_CR_ESS_Pos (4U)
5627#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
5628#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5629#define DCMI_CR_PCKPOL_Pos (5U)
5630#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
5631#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5632#define DCMI_CR_HSPOL_Pos (6U)
5633#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
5634#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5635#define DCMI_CR_VSPOL_Pos (7U)
5636#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
5637#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5638#define DCMI_CR_FCRC_0 0x00000100U
5639#define DCMI_CR_FCRC_1 0x00000200U
5640#define DCMI_CR_EDM_0 0x00000400U
5641#define DCMI_CR_EDM_1 0x00000800U
5642#define DCMI_CR_CRE_Pos (12U)
5643#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
5644#define DCMI_CR_CRE DCMI_CR_CRE_Msk
5645#define DCMI_CR_ENABLE_Pos (14U)
5646#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
5647#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5648
5649/******************** Bits definition for DCMI_SR register ******************/
5650#define DCMI_SR_HSYNC_Pos (0U)
5651#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
5652#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5653#define DCMI_SR_VSYNC_Pos (1U)
5654#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
5655#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5656#define DCMI_SR_FNE_Pos (2U)
5657#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
5658#define DCMI_SR_FNE DCMI_SR_FNE_Msk
5659
5660/******************** Bits definition for DCMI_RIS register *****************/
5661#define DCMI_RIS_FRAME_RIS_Pos (0U)
5662#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
5663#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5664#define DCMI_RIS_OVR_RIS_Pos (1U)
5665#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
5666#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5667#define DCMI_RIS_ERR_RIS_Pos (2U)
5668#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
5669#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5670#define DCMI_RIS_VSYNC_RIS_Pos (3U)
5671#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
5672#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5673#define DCMI_RIS_LINE_RIS_Pos (4U)
5674#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
5675#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5676/* Legacy defines */
5677#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5678#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
5679#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5680#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5681#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5682#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5683
5684/******************** Bits definition for DCMI_IER register *****************/
5685#define DCMI_IER_FRAME_IE_Pos (0U)
5686#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
5687#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5688#define DCMI_IER_OVR_IE_Pos (1U)
5689#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
5690#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5691#define DCMI_IER_ERR_IE_Pos (2U)
5692#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
5693#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5694#define DCMI_IER_VSYNC_IE_Pos (3U)
5695#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
5696#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5697#define DCMI_IER_LINE_IE_Pos (4U)
5698#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
5699#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5700/* Legacy defines */
5701#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5702
5703/******************** Bits definition for DCMI_MIS register *****************/
5704#define DCMI_MIS_FRAME_MIS_Pos (0U)
5705#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
5706#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5707#define DCMI_MIS_OVR_MIS_Pos (1U)
5708#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
5709#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5710#define DCMI_MIS_ERR_MIS_Pos (2U)
5711#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
5712#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5713#define DCMI_MIS_VSYNC_MIS_Pos (3U)
5714#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
5715#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5716#define DCMI_MIS_LINE_MIS_Pos (4U)
5717#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
5718#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5719
5720/* Legacy defines */
5721#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5722#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5723#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5724#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5725#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5726
5727/******************** Bits definition for DCMI_ICR register *****************/
5728#define DCMI_ICR_FRAME_ISC_Pos (0U)
5729#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
5730#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5731#define DCMI_ICR_OVR_ISC_Pos (1U)
5732#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
5733#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5734#define DCMI_ICR_ERR_ISC_Pos (2U)
5735#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
5736#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5737#define DCMI_ICR_VSYNC_ISC_Pos (3U)
5738#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
5739#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5740#define DCMI_ICR_LINE_ISC_Pos (4U)
5741#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
5742#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5743
5744/* Legacy defines */
5745#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5746
5747/******************** Bits definition for DCMI_ESCR register ******************/
5748#define DCMI_ESCR_FSC_Pos (0U)
5749#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
5750#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5751#define DCMI_ESCR_LSC_Pos (8U)
5752#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
5753#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5754#define DCMI_ESCR_LEC_Pos (16U)
5755#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
5756#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5757#define DCMI_ESCR_FEC_Pos (24U)
5758#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
5759#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5760
5761/******************** Bits definition for DCMI_ESUR register ******************/
5762#define DCMI_ESUR_FSU_Pos (0U)
5763#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
5764#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5765#define DCMI_ESUR_LSU_Pos (8U)
5766#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
5767#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5768#define DCMI_ESUR_LEU_Pos (16U)
5769#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
5770#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5771#define DCMI_ESUR_FEU_Pos (24U)
5772#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
5773#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5774
5775/******************** Bits definition for DCMI_CWSTRT register ******************/
5776#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5777#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
5778#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5779#define DCMI_CWSTRT_VST_Pos (16U)
5780#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
5781#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5782
5783/******************** Bits definition for DCMI_CWSIZE register ******************/
5784#define DCMI_CWSIZE_CAPCNT_Pos (0U)
5785#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
5786#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5787#define DCMI_CWSIZE_VLINE_Pos (16U)
5788#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
5789#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5790
5791/******************** Bits definition for DCMI_DR register *********************/
5792#define DCMI_DR_BYTE0_Pos (0U)
5793#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
5794#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5795#define DCMI_DR_BYTE1_Pos (8U)
5796#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
5797#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5798#define DCMI_DR_BYTE2_Pos (16U)
5799#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
5800#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5801#define DCMI_DR_BYTE3_Pos (24U)
5802#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
5803#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5804
5805/******************************************************************************/
5806/* */
5807/* DMA Controller */
5808/* */
5809/******************************************************************************/
5810/******************** Bits definition for DMA_SxCR register *****************/
5811#define DMA_SxCR_CHSEL_Pos (25U)
5812#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
5813#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5814#define DMA_SxCR_CHSEL_0 0x02000000U
5815#define DMA_SxCR_CHSEL_1 0x04000000U
5816#define DMA_SxCR_CHSEL_2 0x08000000U
5817#define DMA_SxCR_MBURST_Pos (23U)
5818#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
5819#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5820#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
5821#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
5822#define DMA_SxCR_PBURST_Pos (21U)
5823#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
5824#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5825#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
5826#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
5827#define DMA_SxCR_CT_Pos (19U)
5828#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
5829#define DMA_SxCR_CT DMA_SxCR_CT_Msk
5830#define DMA_SxCR_DBM_Pos (18U)
5831#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
5832#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5833#define DMA_SxCR_PL_Pos (16U)
5834#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
5835#define DMA_SxCR_PL DMA_SxCR_PL_Msk
5836#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
5837#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
5838#define DMA_SxCR_PINCOS_Pos (15U)
5839#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
5840#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5841#define DMA_SxCR_MSIZE_Pos (13U)
5842#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
5843#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5844#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
5845#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
5846#define DMA_SxCR_PSIZE_Pos (11U)
5847#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
5848#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5849#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
5850#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
5851#define DMA_SxCR_MINC_Pos (10U)
5852#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
5853#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
5854#define DMA_SxCR_PINC_Pos (9U)
5855#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
5856#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
5857#define DMA_SxCR_CIRC_Pos (8U)
5858#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
5859#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
5860#define DMA_SxCR_DIR_Pos (6U)
5861#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
5862#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
5863#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
5864#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
5865#define DMA_SxCR_PFCTRL_Pos (5U)
5866#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
5867#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
5868#define DMA_SxCR_TCIE_Pos (4U)
5869#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
5870#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
5871#define DMA_SxCR_HTIE_Pos (3U)
5872#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
5873#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
5874#define DMA_SxCR_TEIE_Pos (2U)
5875#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
5876#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
5877#define DMA_SxCR_DMEIE_Pos (1U)
5878#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
5879#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
5880#define DMA_SxCR_EN_Pos (0U)
5881#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
5882#define DMA_SxCR_EN DMA_SxCR_EN_Msk
5883
5884/* Legacy defines */
5885#define DMA_SxCR_ACK_Pos (20U)
5886#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
5887#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
5888
5889/******************** Bits definition for DMA_SxCNDTR register **************/
5890#define DMA_SxNDT_Pos (0U)
5891#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
5892#define DMA_SxNDT DMA_SxNDT_Msk
5893#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
5894#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
5895#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
5896#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
5897#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
5898#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
5899#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
5900#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
5901#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
5902#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
5903#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
5904#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
5905#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
5906#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
5907#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
5908#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
5910/******************** Bits definition for DMA_SxFCR register ****************/
5911#define DMA_SxFCR_FEIE_Pos (7U)
5912#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
5913#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
5914#define DMA_SxFCR_FS_Pos (3U)
5915#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
5916#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
5917#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
5918#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
5919#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
5920#define DMA_SxFCR_DMDIS_Pos (2U)
5921#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
5922#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
5923#define DMA_SxFCR_FTH_Pos (0U)
5924#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
5925#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
5926#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
5927#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
5929/******************** Bits definition for DMA_LISR register *****************/
5930#define DMA_LISR_TCIF3_Pos (27U)
5931#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
5932#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
5933#define DMA_LISR_HTIF3_Pos (26U)
5934#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
5935#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
5936#define DMA_LISR_TEIF3_Pos (25U)
5937#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
5938#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
5939#define DMA_LISR_DMEIF3_Pos (24U)
5940#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
5941#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
5942#define DMA_LISR_FEIF3_Pos (22U)
5943#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
5944#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
5945#define DMA_LISR_TCIF2_Pos (21U)
5946#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
5947#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
5948#define DMA_LISR_HTIF2_Pos (20U)
5949#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
5950#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
5951#define DMA_LISR_TEIF2_Pos (19U)
5952#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
5953#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
5954#define DMA_LISR_DMEIF2_Pos (18U)
5955#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
5956#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
5957#define DMA_LISR_FEIF2_Pos (16U)
5958#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
5959#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
5960#define DMA_LISR_TCIF1_Pos (11U)
5961#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
5962#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
5963#define DMA_LISR_HTIF1_Pos (10U)
5964#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
5965#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
5966#define DMA_LISR_TEIF1_Pos (9U)
5967#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
5968#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
5969#define DMA_LISR_DMEIF1_Pos (8U)
5970#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
5971#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
5972#define DMA_LISR_FEIF1_Pos (6U)
5973#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
5974#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
5975#define DMA_LISR_TCIF0_Pos (5U)
5976#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
5977#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
5978#define DMA_LISR_HTIF0_Pos (4U)
5979#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
5980#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
5981#define DMA_LISR_TEIF0_Pos (3U)
5982#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
5983#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
5984#define DMA_LISR_DMEIF0_Pos (2U)
5985#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
5986#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
5987#define DMA_LISR_FEIF0_Pos (0U)
5988#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
5989#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
5990
5991/******************** Bits definition for DMA_HISR register *****************/
5992#define DMA_HISR_TCIF7_Pos (27U)
5993#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
5994#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
5995#define DMA_HISR_HTIF7_Pos (26U)
5996#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
5997#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
5998#define DMA_HISR_TEIF7_Pos (25U)
5999#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6000#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6001#define DMA_HISR_DMEIF7_Pos (24U)
6002#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6003#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6004#define DMA_HISR_FEIF7_Pos (22U)
6005#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6006#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6007#define DMA_HISR_TCIF6_Pos (21U)
6008#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6009#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6010#define DMA_HISR_HTIF6_Pos (20U)
6011#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6012#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6013#define DMA_HISR_TEIF6_Pos (19U)
6014#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6015#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6016#define DMA_HISR_DMEIF6_Pos (18U)
6017#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6018#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6019#define DMA_HISR_FEIF6_Pos (16U)
6020#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6021#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6022#define DMA_HISR_TCIF5_Pos (11U)
6023#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6024#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6025#define DMA_HISR_HTIF5_Pos (10U)
6026#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6027#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6028#define DMA_HISR_TEIF5_Pos (9U)
6029#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6030#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6031#define DMA_HISR_DMEIF5_Pos (8U)
6032#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6033#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6034#define DMA_HISR_FEIF5_Pos (6U)
6035#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6036#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6037#define DMA_HISR_TCIF4_Pos (5U)
6038#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6039#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6040#define DMA_HISR_HTIF4_Pos (4U)
6041#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6042#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6043#define DMA_HISR_TEIF4_Pos (3U)
6044#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6045#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6046#define DMA_HISR_DMEIF4_Pos (2U)
6047#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6048#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6049#define DMA_HISR_FEIF4_Pos (0U)
6050#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6051#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6052
6053/******************** Bits definition for DMA_LIFCR register ****************/
6054#define DMA_LIFCR_CTCIF3_Pos (27U)
6055#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6056#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6057#define DMA_LIFCR_CHTIF3_Pos (26U)
6058#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6059#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6060#define DMA_LIFCR_CTEIF3_Pos (25U)
6061#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6062#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6063#define DMA_LIFCR_CDMEIF3_Pos (24U)
6064#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6065#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6066#define DMA_LIFCR_CFEIF3_Pos (22U)
6067#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6068#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6069#define DMA_LIFCR_CTCIF2_Pos (21U)
6070#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6071#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6072#define DMA_LIFCR_CHTIF2_Pos (20U)
6073#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6074#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6075#define DMA_LIFCR_CTEIF2_Pos (19U)
6076#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6077#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6078#define DMA_LIFCR_CDMEIF2_Pos (18U)
6079#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6080#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6081#define DMA_LIFCR_CFEIF2_Pos (16U)
6082#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6083#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6084#define DMA_LIFCR_CTCIF1_Pos (11U)
6085#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6086#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6087#define DMA_LIFCR_CHTIF1_Pos (10U)
6088#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6089#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6090#define DMA_LIFCR_CTEIF1_Pos (9U)
6091#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6092#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6093#define DMA_LIFCR_CDMEIF1_Pos (8U)
6094#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6095#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6096#define DMA_LIFCR_CFEIF1_Pos (6U)
6097#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6098#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6099#define DMA_LIFCR_CTCIF0_Pos (5U)
6100#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6101#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6102#define DMA_LIFCR_CHTIF0_Pos (4U)
6103#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6104#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6105#define DMA_LIFCR_CTEIF0_Pos (3U)
6106#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6107#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6108#define DMA_LIFCR_CDMEIF0_Pos (2U)
6109#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6110#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6111#define DMA_LIFCR_CFEIF0_Pos (0U)
6112#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6113#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6114
6115/******************** Bits definition for DMA_HIFCR register ****************/
6116#define DMA_HIFCR_CTCIF7_Pos (27U)
6117#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6118#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6119#define DMA_HIFCR_CHTIF7_Pos (26U)
6120#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6121#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6122#define DMA_HIFCR_CTEIF7_Pos (25U)
6123#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6124#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6125#define DMA_HIFCR_CDMEIF7_Pos (24U)
6126#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6127#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6128#define DMA_HIFCR_CFEIF7_Pos (22U)
6129#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6130#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6131#define DMA_HIFCR_CTCIF6_Pos (21U)
6132#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6133#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6134#define DMA_HIFCR_CHTIF6_Pos (20U)
6135#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6136#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6137#define DMA_HIFCR_CTEIF6_Pos (19U)
6138#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6139#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6140#define DMA_HIFCR_CDMEIF6_Pos (18U)
6141#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6142#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6143#define DMA_HIFCR_CFEIF6_Pos (16U)
6144#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6145#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6146#define DMA_HIFCR_CTCIF5_Pos (11U)
6147#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6148#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6149#define DMA_HIFCR_CHTIF5_Pos (10U)
6150#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6151#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6152#define DMA_HIFCR_CTEIF5_Pos (9U)
6153#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6154#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6155#define DMA_HIFCR_CDMEIF5_Pos (8U)
6156#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6157#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6158#define DMA_HIFCR_CFEIF5_Pos (6U)
6159#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6160#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6161#define DMA_HIFCR_CTCIF4_Pos (5U)
6162#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6163#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6164#define DMA_HIFCR_CHTIF4_Pos (4U)
6165#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6166#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6167#define DMA_HIFCR_CTEIF4_Pos (3U)
6168#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6169#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6170#define DMA_HIFCR_CDMEIF4_Pos (2U)
6171#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6172#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6173#define DMA_HIFCR_CFEIF4_Pos (0U)
6174#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6175#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6176
6177/****************** Bit definition for DMA_SxPAR register ********************/
6178#define DMA_SxPAR_PA_Pos (0U)
6179#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6180#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6182/****************** Bit definition for DMA_SxM0AR register ********************/
6183#define DMA_SxM0AR_M0A_Pos (0U)
6184#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6185#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6187/****************** Bit definition for DMA_SxM1AR register ********************/
6188#define DMA_SxM1AR_M1A_Pos (0U)
6189#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6190#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6193/******************************************************************************/
6194/* */
6195/* External Interrupt/Event Controller */
6196/* */
6197/******************************************************************************/
6198/******************* Bit definition for EXTI_IMR register *******************/
6199#define EXTI_IMR_MR0_Pos (0U)
6200#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6201#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6202#define EXTI_IMR_MR1_Pos (1U)
6203#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6204#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6205#define EXTI_IMR_MR2_Pos (2U)
6206#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6207#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6208#define EXTI_IMR_MR3_Pos (3U)
6209#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6210#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6211#define EXTI_IMR_MR4_Pos (4U)
6212#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6213#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6214#define EXTI_IMR_MR5_Pos (5U)
6215#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6216#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6217#define EXTI_IMR_MR6_Pos (6U)
6218#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6219#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6220#define EXTI_IMR_MR7_Pos (7U)
6221#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6222#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6223#define EXTI_IMR_MR8_Pos (8U)
6224#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6225#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6226#define EXTI_IMR_MR9_Pos (9U)
6227#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6228#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6229#define EXTI_IMR_MR10_Pos (10U)
6230#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6231#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6232#define EXTI_IMR_MR11_Pos (11U)
6233#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6234#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6235#define EXTI_IMR_MR12_Pos (12U)
6236#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6237#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6238#define EXTI_IMR_MR13_Pos (13U)
6239#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6240#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6241#define EXTI_IMR_MR14_Pos (14U)
6242#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6243#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6244#define EXTI_IMR_MR15_Pos (15U)
6245#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6246#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6247#define EXTI_IMR_MR16_Pos (16U)
6248#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6249#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6250#define EXTI_IMR_MR17_Pos (17U)
6251#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6252#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6253#define EXTI_IMR_MR18_Pos (18U)
6254#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6255#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6256#define EXTI_IMR_MR19_Pos (19U)
6257#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6258#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6259#define EXTI_IMR_MR20_Pos (20U)
6260#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6261#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6262#define EXTI_IMR_MR21_Pos (21U)
6263#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6264#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6265#define EXTI_IMR_MR22_Pos (22U)
6266#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6267#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6269/* Reference Defines */
6270#define EXTI_IMR_IM0 EXTI_IMR_MR0
6271#define EXTI_IMR_IM1 EXTI_IMR_MR1
6272#define EXTI_IMR_IM2 EXTI_IMR_MR2
6273#define EXTI_IMR_IM3 EXTI_IMR_MR3
6274#define EXTI_IMR_IM4 EXTI_IMR_MR4
6275#define EXTI_IMR_IM5 EXTI_IMR_MR5
6276#define EXTI_IMR_IM6 EXTI_IMR_MR6
6277#define EXTI_IMR_IM7 EXTI_IMR_MR7
6278#define EXTI_IMR_IM8 EXTI_IMR_MR8
6279#define EXTI_IMR_IM9 EXTI_IMR_MR9
6280#define EXTI_IMR_IM10 EXTI_IMR_MR10
6281#define EXTI_IMR_IM11 EXTI_IMR_MR11
6282#define EXTI_IMR_IM12 EXTI_IMR_MR12
6283#define EXTI_IMR_IM13 EXTI_IMR_MR13
6284#define EXTI_IMR_IM14 EXTI_IMR_MR14
6285#define EXTI_IMR_IM15 EXTI_IMR_MR15
6286#define EXTI_IMR_IM16 EXTI_IMR_MR16
6287#define EXTI_IMR_IM17 EXTI_IMR_MR17
6288#define EXTI_IMR_IM18 EXTI_IMR_MR18
6289#define EXTI_IMR_IM19 EXTI_IMR_MR19
6290#define EXTI_IMR_IM20 EXTI_IMR_MR20
6291#define EXTI_IMR_IM21 EXTI_IMR_MR21
6292#define EXTI_IMR_IM22 EXTI_IMR_MR22
6293#define EXTI_IMR_IM_Pos (0U)
6294#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
6295#define EXTI_IMR_IM EXTI_IMR_IM_Msk
6297/******************* Bit definition for EXTI_EMR register *******************/
6298#define EXTI_EMR_MR0_Pos (0U)
6299#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6300#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6301#define EXTI_EMR_MR1_Pos (1U)
6302#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6303#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6304#define EXTI_EMR_MR2_Pos (2U)
6305#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6306#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6307#define EXTI_EMR_MR3_Pos (3U)
6308#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6309#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6310#define EXTI_EMR_MR4_Pos (4U)
6311#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6312#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6313#define EXTI_EMR_MR5_Pos (5U)
6314#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6315#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6316#define EXTI_EMR_MR6_Pos (6U)
6317#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6318#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6319#define EXTI_EMR_MR7_Pos (7U)
6320#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6321#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6322#define EXTI_EMR_MR8_Pos (8U)
6323#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6324#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6325#define EXTI_EMR_MR9_Pos (9U)
6326#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6327#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6328#define EXTI_EMR_MR10_Pos (10U)
6329#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6330#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6331#define EXTI_EMR_MR11_Pos (11U)
6332#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6333#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6334#define EXTI_EMR_MR12_Pos (12U)
6335#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6336#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6337#define EXTI_EMR_MR13_Pos (13U)
6338#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6339#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6340#define EXTI_EMR_MR14_Pos (14U)
6341#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6342#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6343#define EXTI_EMR_MR15_Pos (15U)
6344#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6345#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6346#define EXTI_EMR_MR16_Pos (16U)
6347#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6348#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6349#define EXTI_EMR_MR17_Pos (17U)
6350#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6351#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6352#define EXTI_EMR_MR18_Pos (18U)
6353#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6354#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6355#define EXTI_EMR_MR19_Pos (19U)
6356#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6357#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6358#define EXTI_EMR_MR20_Pos (20U)
6359#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6360#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6361#define EXTI_EMR_MR21_Pos (21U)
6362#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6363#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6364#define EXTI_EMR_MR22_Pos (22U)
6365#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6366#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6368/* Reference Defines */
6369#define EXTI_EMR_EM0 EXTI_EMR_MR0
6370#define EXTI_EMR_EM1 EXTI_EMR_MR1
6371#define EXTI_EMR_EM2 EXTI_EMR_MR2
6372#define EXTI_EMR_EM3 EXTI_EMR_MR3
6373#define EXTI_EMR_EM4 EXTI_EMR_MR4
6374#define EXTI_EMR_EM5 EXTI_EMR_MR5
6375#define EXTI_EMR_EM6 EXTI_EMR_MR6
6376#define EXTI_EMR_EM7 EXTI_EMR_MR7
6377#define EXTI_EMR_EM8 EXTI_EMR_MR8
6378#define EXTI_EMR_EM9 EXTI_EMR_MR9
6379#define EXTI_EMR_EM10 EXTI_EMR_MR10
6380#define EXTI_EMR_EM11 EXTI_EMR_MR11
6381#define EXTI_EMR_EM12 EXTI_EMR_MR12
6382#define EXTI_EMR_EM13 EXTI_EMR_MR13
6383#define EXTI_EMR_EM14 EXTI_EMR_MR14
6384#define EXTI_EMR_EM15 EXTI_EMR_MR15
6385#define EXTI_EMR_EM16 EXTI_EMR_MR16
6386#define EXTI_EMR_EM17 EXTI_EMR_MR17
6387#define EXTI_EMR_EM18 EXTI_EMR_MR18
6388#define EXTI_EMR_EM19 EXTI_EMR_MR19
6389#define EXTI_EMR_EM20 EXTI_EMR_MR20
6390#define EXTI_EMR_EM21 EXTI_EMR_MR21
6391#define EXTI_EMR_EM22 EXTI_EMR_MR22
6392
6393/****************** Bit definition for EXTI_RTSR register *******************/
6394#define EXTI_RTSR_TR0_Pos (0U)
6395#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6396#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6397#define EXTI_RTSR_TR1_Pos (1U)
6398#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6399#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6400#define EXTI_RTSR_TR2_Pos (2U)
6401#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6402#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6403#define EXTI_RTSR_TR3_Pos (3U)
6404#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6405#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6406#define EXTI_RTSR_TR4_Pos (4U)
6407#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6408#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6409#define EXTI_RTSR_TR5_Pos (5U)
6410#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6411#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6412#define EXTI_RTSR_TR6_Pos (6U)
6413#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6414#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6415#define EXTI_RTSR_TR7_Pos (7U)
6416#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6417#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6418#define EXTI_RTSR_TR8_Pos (8U)
6419#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6420#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6421#define EXTI_RTSR_TR9_Pos (9U)
6422#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6423#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6424#define EXTI_RTSR_TR10_Pos (10U)
6425#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6426#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6427#define EXTI_RTSR_TR11_Pos (11U)
6428#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6429#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6430#define EXTI_RTSR_TR12_Pos (12U)
6431#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6432#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6433#define EXTI_RTSR_TR13_Pos (13U)
6434#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6435#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6436#define EXTI_RTSR_TR14_Pos (14U)
6437#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6438#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6439#define EXTI_RTSR_TR15_Pos (15U)
6440#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6441#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6442#define EXTI_RTSR_TR16_Pos (16U)
6443#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6444#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6445#define EXTI_RTSR_TR17_Pos (17U)
6446#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6447#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6448#define EXTI_RTSR_TR18_Pos (18U)
6449#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6450#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6451#define EXTI_RTSR_TR19_Pos (19U)
6452#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6453#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6454#define EXTI_RTSR_TR20_Pos (20U)
6455#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6456#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6457#define EXTI_RTSR_TR21_Pos (21U)
6458#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6459#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6460#define EXTI_RTSR_TR22_Pos (22U)
6461#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6462#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6464/****************** Bit definition for EXTI_FTSR register *******************/
6465#define EXTI_FTSR_TR0_Pos (0U)
6466#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6467#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6468#define EXTI_FTSR_TR1_Pos (1U)
6469#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6470#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6471#define EXTI_FTSR_TR2_Pos (2U)
6472#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6473#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6474#define EXTI_FTSR_TR3_Pos (3U)
6475#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6476#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6477#define EXTI_FTSR_TR4_Pos (4U)
6478#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6479#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6480#define EXTI_FTSR_TR5_Pos (5U)
6481#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6482#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6483#define EXTI_FTSR_TR6_Pos (6U)
6484#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6485#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6486#define EXTI_FTSR_TR7_Pos (7U)
6487#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6488#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6489#define EXTI_FTSR_TR8_Pos (8U)
6490#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6491#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6492#define EXTI_FTSR_TR9_Pos (9U)
6493#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6494#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6495#define EXTI_FTSR_TR10_Pos (10U)
6496#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6497#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6498#define EXTI_FTSR_TR11_Pos (11U)
6499#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6500#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6501#define EXTI_FTSR_TR12_Pos (12U)
6502#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6503#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6504#define EXTI_FTSR_TR13_Pos (13U)
6505#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6506#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6507#define EXTI_FTSR_TR14_Pos (14U)
6508#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6509#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6510#define EXTI_FTSR_TR15_Pos (15U)
6511#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6512#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6513#define EXTI_FTSR_TR16_Pos (16U)
6514#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6515#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6516#define EXTI_FTSR_TR17_Pos (17U)
6517#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6518#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6519#define EXTI_FTSR_TR18_Pos (18U)
6520#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6521#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6522#define EXTI_FTSR_TR19_Pos (19U)
6523#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
6524#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
6525#define EXTI_FTSR_TR20_Pos (20U)
6526#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
6527#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
6528#define EXTI_FTSR_TR21_Pos (21U)
6529#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
6530#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
6531#define EXTI_FTSR_TR22_Pos (22U)
6532#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
6533#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
6535/****************** Bit definition for EXTI_SWIER register ******************/
6536#define EXTI_SWIER_SWIER0_Pos (0U)
6537#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
6538#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
6539#define EXTI_SWIER_SWIER1_Pos (1U)
6540#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
6541#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
6542#define EXTI_SWIER_SWIER2_Pos (2U)
6543#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
6544#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
6545#define EXTI_SWIER_SWIER3_Pos (3U)
6546#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
6547#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
6548#define EXTI_SWIER_SWIER4_Pos (4U)
6549#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
6550#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
6551#define EXTI_SWIER_SWIER5_Pos (5U)
6552#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
6553#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
6554#define EXTI_SWIER_SWIER6_Pos (6U)
6555#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
6556#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
6557#define EXTI_SWIER_SWIER7_Pos (7U)
6558#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
6559#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
6560#define EXTI_SWIER_SWIER8_Pos (8U)
6561#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
6562#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
6563#define EXTI_SWIER_SWIER9_Pos (9U)
6564#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
6565#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
6566#define EXTI_SWIER_SWIER10_Pos (10U)
6567#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
6568#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
6569#define EXTI_SWIER_SWIER11_Pos (11U)
6570#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
6571#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
6572#define EXTI_SWIER_SWIER12_Pos (12U)
6573#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
6574#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
6575#define EXTI_SWIER_SWIER13_Pos (13U)
6576#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
6577#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
6578#define EXTI_SWIER_SWIER14_Pos (14U)
6579#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
6580#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
6581#define EXTI_SWIER_SWIER15_Pos (15U)
6582#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
6583#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
6584#define EXTI_SWIER_SWIER16_Pos (16U)
6585#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
6586#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
6587#define EXTI_SWIER_SWIER17_Pos (17U)
6588#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
6589#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
6590#define EXTI_SWIER_SWIER18_Pos (18U)
6591#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
6592#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
6593#define EXTI_SWIER_SWIER19_Pos (19U)
6594#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
6595#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
6596#define EXTI_SWIER_SWIER20_Pos (20U)
6597#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
6598#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
6599#define EXTI_SWIER_SWIER21_Pos (21U)
6600#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
6601#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
6602#define EXTI_SWIER_SWIER22_Pos (22U)
6603#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
6604#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
6606/******************* Bit definition for EXTI_PR register ********************/
6607#define EXTI_PR_PR0_Pos (0U)
6608#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
6609#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
6610#define EXTI_PR_PR1_Pos (1U)
6611#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
6612#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
6613#define EXTI_PR_PR2_Pos (2U)
6614#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
6615#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
6616#define EXTI_PR_PR3_Pos (3U)
6617#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
6618#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
6619#define EXTI_PR_PR4_Pos (4U)
6620#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
6621#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
6622#define EXTI_PR_PR5_Pos (5U)
6623#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
6624#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
6625#define EXTI_PR_PR6_Pos (6U)
6626#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
6627#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
6628#define EXTI_PR_PR7_Pos (7U)
6629#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
6630#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
6631#define EXTI_PR_PR8_Pos (8U)
6632#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
6633#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
6634#define EXTI_PR_PR9_Pos (9U)
6635#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
6636#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
6637#define EXTI_PR_PR10_Pos (10U)
6638#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
6639#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
6640#define EXTI_PR_PR11_Pos (11U)
6641#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
6642#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
6643#define EXTI_PR_PR12_Pos (12U)
6644#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
6645#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
6646#define EXTI_PR_PR13_Pos (13U)
6647#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
6648#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
6649#define EXTI_PR_PR14_Pos (14U)
6650#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
6651#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
6652#define EXTI_PR_PR15_Pos (15U)
6653#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
6654#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
6655#define EXTI_PR_PR16_Pos (16U)
6656#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
6657#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
6658#define EXTI_PR_PR17_Pos (17U)
6659#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
6660#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
6661#define EXTI_PR_PR18_Pos (18U)
6662#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
6663#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
6664#define EXTI_PR_PR19_Pos (19U)
6665#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
6666#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
6667#define EXTI_PR_PR20_Pos (20U)
6668#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
6669#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
6670#define EXTI_PR_PR21_Pos (21U)
6671#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
6672#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
6673#define EXTI_PR_PR22_Pos (22U)
6674#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
6675#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
6677/******************************************************************************/
6678/* */
6679/* FLASH */
6680/* */
6681/******************************************************************************/
6682/******************* Bits definition for FLASH_ACR register *****************/
6683#define FLASH_ACR_LATENCY_Pos (0U)
6684#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
6685#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6686#define FLASH_ACR_LATENCY_0WS 0x00000000U
6687#define FLASH_ACR_LATENCY_1WS 0x00000001U
6688#define FLASH_ACR_LATENCY_2WS 0x00000002U
6689#define FLASH_ACR_LATENCY_3WS 0x00000003U
6690#define FLASH_ACR_LATENCY_4WS 0x00000004U
6691#define FLASH_ACR_LATENCY_5WS 0x00000005U
6692#define FLASH_ACR_LATENCY_6WS 0x00000006U
6693#define FLASH_ACR_LATENCY_7WS 0x00000007U
6694
6695
6696#define FLASH_ACR_PRFTEN_Pos (8U)
6697#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
6698#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6699#define FLASH_ACR_ICEN_Pos (9U)
6700#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
6701#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6702#define FLASH_ACR_DCEN_Pos (10U)
6703#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
6704#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6705#define FLASH_ACR_ICRST_Pos (11U)
6706#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
6707#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6708#define FLASH_ACR_DCRST_Pos (12U)
6709#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
6710#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6711#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
6712#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
6713#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
6714#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
6715#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
6716#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
6717
6718/******************* Bits definition for FLASH_SR register ******************/
6719#define FLASH_SR_EOP_Pos (0U)
6720#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6721#define FLASH_SR_EOP FLASH_SR_EOP_Msk
6722#define FLASH_SR_SOP_Pos (1U)
6723#define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos)
6724#define FLASH_SR_SOP FLASH_SR_SOP_Msk
6725#define FLASH_SR_WRPERR_Pos (4U)
6726#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
6727#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6728#define FLASH_SR_PGAERR_Pos (5U)
6729#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
6730#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6731#define FLASH_SR_PGPERR_Pos (6U)
6732#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
6733#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6734#define FLASH_SR_PGSERR_Pos (7U)
6735#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
6736#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6737#define FLASH_SR_BSY_Pos (16U)
6738#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6739#define FLASH_SR_BSY FLASH_SR_BSY_Msk
6740
6741/******************* Bits definition for FLASH_CR register ******************/
6742#define FLASH_CR_PG_Pos (0U)
6743#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6744#define FLASH_CR_PG FLASH_CR_PG_Msk
6745#define FLASH_CR_SER_Pos (1U)
6746#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
6747#define FLASH_CR_SER FLASH_CR_SER_Msk
6748#define FLASH_CR_MER_Pos (2U)
6749#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
6750#define FLASH_CR_MER FLASH_CR_MER_Msk
6751#define FLASH_CR_SNB_Pos (3U)
6752#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
6753#define FLASH_CR_SNB FLASH_CR_SNB_Msk
6754#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
6755#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
6756#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
6757#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
6758#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
6759#define FLASH_CR_PSIZE_Pos (8U)
6760#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
6761#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6762#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
6763#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
6764#define FLASH_CR_STRT_Pos (16U)
6765#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6766#define FLASH_CR_STRT FLASH_CR_STRT_Msk
6767#define FLASH_CR_EOPIE_Pos (24U)
6768#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6769#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6770#define FLASH_CR_ERRIE_Pos (25U)
6771#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
6772#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
6773#define FLASH_CR_LOCK_Pos (31U)
6774#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6775#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6776
6777/******************* Bits definition for FLASH_OPTCR register ***************/
6778#define FLASH_OPTCR_OPTLOCK_Pos (0U)
6779#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
6780#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6781#define FLASH_OPTCR_OPTSTRT_Pos (1U)
6782#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
6783#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6784
6785#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6786#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6787#define FLASH_OPTCR_BOR_LEV_Pos (2U)
6788#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
6789#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6790#define FLASH_OPTCR_WDG_SW_Pos (5U)
6791#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
6792#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6793#define FLASH_OPTCR_nRST_STOP_Pos (6U)
6794#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
6795#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6796#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6797#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
6798#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6799#define FLASH_OPTCR_RDP_Pos (8U)
6800#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
6801#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6802#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
6803#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
6804#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
6805#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
6806#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
6807#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
6808#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
6809#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
6810#define FLASH_OPTCR_nWRP_Pos (16U)
6811#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
6812#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6813#define FLASH_OPTCR_nWRP_0 0x00010000U
6814#define FLASH_OPTCR_nWRP_1 0x00020000U
6815#define FLASH_OPTCR_nWRP_2 0x00040000U
6816#define FLASH_OPTCR_nWRP_3 0x00080000U
6817#define FLASH_OPTCR_nWRP_4 0x00100000U
6818#define FLASH_OPTCR_nWRP_5 0x00200000U
6819#define FLASH_OPTCR_nWRP_6 0x00400000U
6820#define FLASH_OPTCR_nWRP_7 0x00800000U
6821#define FLASH_OPTCR_nWRP_8 0x01000000U
6822#define FLASH_OPTCR_nWRP_9 0x02000000U
6823#define FLASH_OPTCR_nWRP_10 0x04000000U
6824#define FLASH_OPTCR_nWRP_11 0x08000000U
6825
6826/****************** Bits definition for FLASH_OPTCR1 register ***************/
6827#define FLASH_OPTCR1_nWRP_Pos (16U)
6828#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
6829#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
6830#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
6831#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
6832#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
6833#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
6834#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
6835#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
6836#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
6837#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
6838#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
6839#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
6840#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
6841#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
6843/******************************************************************************/
6844/* */
6845/* Flexible Static Memory Controller */
6846/* */
6847/******************************************************************************/
6848/****************** Bit definition for FSMC_BCR1 register *******************/
6849#define FSMC_BCR1_MBKEN_Pos (0U)
6850#define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)
6851#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk
6852#define FSMC_BCR1_MUXEN_Pos (1U)
6853#define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)
6854#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk
6856#define FSMC_BCR1_MTYP_Pos (2U)
6857#define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)
6858#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk
6859#define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)
6860#define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)
6862#define FSMC_BCR1_MWID_Pos (4U)
6863#define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)
6864#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk
6865#define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)
6866#define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)
6868#define FSMC_BCR1_FACCEN_Pos (6U)
6869#define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)
6870#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk
6871#define FSMC_BCR1_BURSTEN_Pos (8U)
6872#define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)
6873#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk
6874#define FSMC_BCR1_WAITPOL_Pos (9U)
6875#define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)
6876#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk
6877#define FSMC_BCR1_WRAPMOD_Pos (10U)
6878#define FSMC_BCR1_WRAPMOD_Msk (0x1UL << FSMC_BCR1_WRAPMOD_Pos)
6879#define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk
6880#define FSMC_BCR1_WAITCFG_Pos (11U)
6881#define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)
6882#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk
6883#define FSMC_BCR1_WREN_Pos (12U)
6884#define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)
6885#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk
6886#define FSMC_BCR1_WAITEN_Pos (13U)
6887#define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)
6888#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk
6889#define FSMC_BCR1_EXTMOD_Pos (14U)
6890#define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)
6891#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk
6892#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
6893#define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
6894#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk
6895#define FSMC_BCR1_CPSIZE_Pos (16U)
6896#define FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos)
6897#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk
6898#define FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos)
6899#define FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos)
6900#define FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos)
6901#define FSMC_BCR1_CBURSTRW_Pos (19U)
6902#define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
6903#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk
6905/****************** Bit definition for FSMC_BCR2 register *******************/
6906#define FSMC_BCR2_MBKEN_Pos (0U)
6907#define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)
6908#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk
6909#define FSMC_BCR2_MUXEN_Pos (1U)
6910#define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)
6911#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk
6913#define FSMC_BCR2_MTYP_Pos (2U)
6914#define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)
6915#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk
6916#define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)
6917#define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)
6919#define FSMC_BCR2_MWID_Pos (4U)
6920#define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)
6921#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk
6922#define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)
6923#define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)
6925#define FSMC_BCR2_FACCEN_Pos (6U)
6926#define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)
6927#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk
6928#define FSMC_BCR2_BURSTEN_Pos (8U)
6929#define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)
6930#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk
6931#define FSMC_BCR2_WAITPOL_Pos (9U)
6932#define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)
6933#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk
6934#define FSMC_BCR2_WRAPMOD_Pos (10U)
6935#define FSMC_BCR2_WRAPMOD_Msk (0x1UL << FSMC_BCR2_WRAPMOD_Pos)
6936#define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk
6937#define FSMC_BCR2_WAITCFG_Pos (11U)
6938#define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)
6939#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk
6940#define FSMC_BCR2_WREN_Pos (12U)
6941#define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)
6942#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk
6943#define FSMC_BCR2_WAITEN_Pos (13U)
6944#define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)
6945#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk
6946#define FSMC_BCR2_EXTMOD_Pos (14U)
6947#define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)
6948#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk
6949#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
6950#define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
6951#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk
6952#define FSMC_BCR2_CPSIZE_Pos (16U)
6953#define FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos)
6954#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk
6955#define FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos)
6956#define FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos)
6957#define FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos)
6958#define FSMC_BCR2_CBURSTRW_Pos (19U)
6959#define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
6960#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk
6962/****************** Bit definition for FSMC_BCR3 register *******************/
6963#define FSMC_BCR3_MBKEN_Pos (0U)
6964#define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)
6965#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk
6966#define FSMC_BCR3_MUXEN_Pos (1U)
6967#define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)
6968#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk
6970#define FSMC_BCR3_MTYP_Pos (2U)
6971#define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)
6972#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk
6973#define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)
6974#define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)
6976#define FSMC_BCR3_MWID_Pos (4U)
6977#define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)
6978#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk
6979#define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)
6980#define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)
6982#define FSMC_BCR3_FACCEN_Pos (6U)
6983#define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)
6984#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk
6985#define FSMC_BCR3_BURSTEN_Pos (8U)
6986#define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)
6987#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk
6988#define FSMC_BCR3_WAITPOL_Pos (9U)
6989#define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)
6990#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk
6991#define FSMC_BCR3_WRAPMOD_Pos (10U)
6992#define FSMC_BCR3_WRAPMOD_Msk (0x1UL << FSMC_BCR3_WRAPMOD_Pos)
6993#define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk
6994#define FSMC_BCR3_WAITCFG_Pos (11U)
6995#define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)
6996#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk
6997#define FSMC_BCR3_WREN_Pos (12U)
6998#define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)
6999#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk
7000#define FSMC_BCR3_WAITEN_Pos (13U)
7001#define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)
7002#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk
7003#define FSMC_BCR3_EXTMOD_Pos (14U)
7004#define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)
7005#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk
7006#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
7007#define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
7008#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk
7009#define FSMC_BCR3_CPSIZE_Pos (16U)
7010#define FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos)
7011#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk
7012#define FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos)
7013#define FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos)
7014#define FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos)
7015#define FSMC_BCR3_CBURSTRW_Pos (19U)
7016#define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
7017#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk
7019/****************** Bit definition for FSMC_BCR4 register *******************/
7020#define FSMC_BCR4_MBKEN_Pos (0U)
7021#define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)
7022#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk
7023#define FSMC_BCR4_MUXEN_Pos (1U)
7024#define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)
7025#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk
7027#define FSMC_BCR4_MTYP_Pos (2U)
7028#define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)
7029#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk
7030#define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)
7031#define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)
7033#define FSMC_BCR4_MWID_Pos (4U)
7034#define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)
7035#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk
7036#define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)
7037#define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)
7039#define FSMC_BCR4_FACCEN_Pos (6U)
7040#define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)
7041#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk
7042#define FSMC_BCR4_BURSTEN_Pos (8U)
7043#define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)
7044#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk
7045#define FSMC_BCR4_WAITPOL_Pos (9U)
7046#define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)
7047#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk
7048#define FSMC_BCR4_WRAPMOD_Pos (10U)
7049#define FSMC_BCR4_WRAPMOD_Msk (0x1UL << FSMC_BCR4_WRAPMOD_Pos)
7050#define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk
7051#define FSMC_BCR4_WAITCFG_Pos (11U)
7052#define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)
7053#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk
7054#define FSMC_BCR4_WREN_Pos (12U)
7055#define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)
7056#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk
7057#define FSMC_BCR4_WAITEN_Pos (13U)
7058#define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)
7059#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk
7060#define FSMC_BCR4_EXTMOD_Pos (14U)
7061#define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)
7062#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk
7063#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
7064#define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
7065#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk
7066#define FSMC_BCR4_CPSIZE_Pos (16U)
7067#define FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos)
7068#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk
7069#define FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos)
7070#define FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos)
7071#define FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos)
7072#define FSMC_BCR4_CBURSTRW_Pos (19U)
7073#define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
7074#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk
7076/****************** Bit definition for FSMC_BTR1 register ******************/
7077#define FSMC_BTR1_ADDSET_Pos (0U)
7078#define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)
7079#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk
7080#define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)
7081#define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)
7082#define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)
7083#define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)
7085#define FSMC_BTR1_ADDHLD_Pos (4U)
7086#define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)
7087#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk
7088#define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)
7089#define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)
7090#define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)
7091#define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)
7093#define FSMC_BTR1_DATAST_Pos (8U)
7094#define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)
7095#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk
7096#define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)
7097#define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)
7098#define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)
7099#define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)
7100#define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)
7101#define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)
7102#define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)
7103#define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)
7105#define FSMC_BTR1_BUSTURN_Pos (16U)
7106#define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)
7107#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk
7108#define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)
7109#define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)
7110#define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)
7111#define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)
7113#define FSMC_BTR1_CLKDIV_Pos (20U)
7114#define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)
7115#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk
7116#define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)
7117#define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)
7118#define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)
7119#define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)
7121#define FSMC_BTR1_DATLAT_Pos (24U)
7122#define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)
7123#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk
7124#define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)
7125#define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)
7126#define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)
7127#define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)
7129#define FSMC_BTR1_ACCMOD_Pos (28U)
7130#define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)
7131#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk
7132#define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)
7133#define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)
7135/****************** Bit definition for FSMC_BTR2 register *******************/
7136#define FSMC_BTR2_ADDSET_Pos (0U)
7137#define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)
7138#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk
7139#define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)
7140#define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)
7141#define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)
7142#define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)
7144#define FSMC_BTR2_ADDHLD_Pos (4U)
7145#define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)
7146#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk
7147#define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)
7148#define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)
7149#define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)
7150#define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)
7152#define FSMC_BTR2_DATAST_Pos (8U)
7153#define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)
7154#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk
7155#define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)
7156#define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)
7157#define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)
7158#define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)
7159#define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)
7160#define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)
7161#define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)
7162#define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)
7164#define FSMC_BTR2_BUSTURN_Pos (16U)
7165#define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)
7166#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk
7167#define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)
7168#define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)
7169#define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)
7170#define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)
7172#define FSMC_BTR2_CLKDIV_Pos (20U)
7173#define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)
7174#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk
7175#define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)
7176#define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)
7177#define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)
7178#define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)
7180#define FSMC_BTR2_DATLAT_Pos (24U)
7181#define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)
7182#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk
7183#define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)
7184#define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)
7185#define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)
7186#define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)
7188#define FSMC_BTR2_ACCMOD_Pos (28U)
7189#define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)
7190#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk
7191#define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)
7192#define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)
7194/******************* Bit definition for FSMC_BTR3 register *******************/
7195#define FSMC_BTR3_ADDSET_Pos (0U)
7196#define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)
7197#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk
7198#define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)
7199#define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)
7200#define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)
7201#define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)
7203#define FSMC_BTR3_ADDHLD_Pos (4U)
7204#define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)
7205#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk
7206#define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)
7207#define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)
7208#define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)
7209#define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)
7211#define FSMC_BTR3_DATAST_Pos (8U)
7212#define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)
7213#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk
7214#define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)
7215#define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)
7216#define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)
7217#define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)
7218#define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)
7219#define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)
7220#define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)
7221#define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)
7223#define FSMC_BTR3_BUSTURN_Pos (16U)
7224#define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)
7225#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk
7226#define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)
7227#define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)
7228#define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)
7229#define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)
7231#define FSMC_BTR3_CLKDIV_Pos (20U)
7232#define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)
7233#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk
7234#define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)
7235#define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)
7236#define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)
7237#define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)
7239#define FSMC_BTR3_DATLAT_Pos (24U)
7240#define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)
7241#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk
7242#define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)
7243#define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)
7244#define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)
7245#define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)
7247#define FSMC_BTR3_ACCMOD_Pos (28U)
7248#define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)
7249#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk
7250#define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)
7251#define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)
7253/****************** Bit definition for FSMC_BTR4 register *******************/
7254#define FSMC_BTR4_ADDSET_Pos (0U)
7255#define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)
7256#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk
7257#define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)
7258#define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)
7259#define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)
7260#define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)
7262#define FSMC_BTR4_ADDHLD_Pos (4U)
7263#define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)
7264#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk
7265#define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)
7266#define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)
7267#define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)
7268#define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)
7270#define FSMC_BTR4_DATAST_Pos (8U)
7271#define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)
7272#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk
7273#define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)
7274#define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)
7275#define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)
7276#define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)
7277#define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)
7278#define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)
7279#define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)
7280#define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)
7282#define FSMC_BTR4_BUSTURN_Pos (16U)
7283#define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)
7284#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk
7285#define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)
7286#define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)
7287#define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)
7288#define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)
7290#define FSMC_BTR4_CLKDIV_Pos (20U)
7291#define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)
7292#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk
7293#define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)
7294#define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)
7295#define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)
7296#define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)
7298#define FSMC_BTR4_DATLAT_Pos (24U)
7299#define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)
7300#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk
7301#define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)
7302#define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)
7303#define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)
7304#define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)
7306#define FSMC_BTR4_ACCMOD_Pos (28U)
7307#define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)
7308#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk
7309#define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)
7310#define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)
7312/****************** Bit definition for FSMC_BWTR1 register ******************/
7313#define FSMC_BWTR1_ADDSET_Pos (0U)
7314#define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)
7315#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk
7316#define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)
7317#define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)
7318#define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)
7319#define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)
7321#define FSMC_BWTR1_ADDHLD_Pos (4U)
7322#define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
7323#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk
7324#define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
7325#define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
7326#define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
7327#define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
7329#define FSMC_BWTR1_DATAST_Pos (8U)
7330#define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)
7331#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk
7332#define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)
7333#define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)
7334#define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)
7335#define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)
7336#define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)
7337#define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)
7338#define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)
7339#define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)
7341#define FSMC_BWTR1_BUSTURN_Pos (16U)
7342#define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
7343#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk
7344#define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
7345#define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
7346#define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
7347#define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
7349#define FSMC_BWTR1_ACCMOD_Pos (28U)
7350#define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
7351#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk
7352#define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
7353#define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
7355/****************** Bit definition for FSMC_BWTR2 register ******************/
7356#define FSMC_BWTR2_ADDSET_Pos (0U)
7357#define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)
7358#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk
7359#define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)
7360#define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)
7361#define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)
7362#define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)
7364#define FSMC_BWTR2_ADDHLD_Pos (4U)
7365#define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
7366#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk
7367#define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
7368#define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
7369#define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
7370#define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
7372#define FSMC_BWTR2_DATAST_Pos (8U)
7373#define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)
7374#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk
7375#define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)
7376#define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)
7377#define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)
7378#define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)
7379#define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)
7380#define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)
7381#define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)
7382#define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)
7384#define FSMC_BWTR2_BUSTURN_Pos (16U)
7385#define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
7386#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk
7387#define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
7388#define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
7389#define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
7390#define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
7392#define FSMC_BWTR2_ACCMOD_Pos (28U)
7393#define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
7394#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk
7395#define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
7396#define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
7398/****************** Bit definition for FSMC_BWTR3 register ******************/
7399#define FSMC_BWTR3_ADDSET_Pos (0U)
7400#define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)
7401#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk
7402#define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)
7403#define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)
7404#define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)
7405#define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)
7407#define FSMC_BWTR3_ADDHLD_Pos (4U)
7408#define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
7409#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk
7410#define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
7411#define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
7412#define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
7413#define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
7415#define FSMC_BWTR3_DATAST_Pos (8U)
7416#define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)
7417#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk
7418#define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)
7419#define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)
7420#define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)
7421#define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)
7422#define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)
7423#define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)
7424#define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)
7425#define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)
7427#define FSMC_BWTR3_BUSTURN_Pos (16U)
7428#define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
7429#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk
7430#define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
7431#define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
7432#define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
7433#define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
7435#define FSMC_BWTR3_ACCMOD_Pos (28U)
7436#define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
7437#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk
7438#define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
7439#define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
7441/****************** Bit definition for FSMC_BWTR4 register ******************/
7442#define FSMC_BWTR4_ADDSET_Pos (0U)
7443#define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)
7444#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk
7445#define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)
7446#define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)
7447#define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)
7448#define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)
7450#define FSMC_BWTR4_ADDHLD_Pos (4U)
7451#define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
7452#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk
7453#define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
7454#define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
7455#define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
7456#define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
7458#define FSMC_BWTR4_DATAST_Pos (8U)
7459#define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)
7460#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk
7461#define FSMC_BWTR4_DATAST_0 0x00000100U
7462#define FSMC_BWTR4_DATAST_1 0x00000200U
7463#define FSMC_BWTR4_DATAST_2 0x00000400U
7464#define FSMC_BWTR4_DATAST_3 0x00000800U
7465#define FSMC_BWTR4_DATAST_4 0x00001000U
7466#define FSMC_BWTR4_DATAST_5 0x00002000U
7467#define FSMC_BWTR4_DATAST_6 0x00004000U
7468#define FSMC_BWTR4_DATAST_7 0x00008000U
7470#define FSMC_BWTR4_BUSTURN_Pos (16U)
7471#define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
7472#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk
7473#define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
7474#define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
7475#define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
7476#define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
7478#define FSMC_BWTR4_ACCMOD_Pos (28U)
7479#define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
7480#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk
7481#define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
7482#define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
7484/****************** Bit definition for FSMC_PCR2 register *******************/
7485#define FSMC_PCR2_PWAITEN_Pos (1U)
7486#define FSMC_PCR2_PWAITEN_Msk (0x1UL << FSMC_PCR2_PWAITEN_Pos)
7487#define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk
7488#define FSMC_PCR2_PBKEN_Pos (2U)
7489#define FSMC_PCR2_PBKEN_Msk (0x1UL << FSMC_PCR2_PBKEN_Pos)
7490#define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk
7491#define FSMC_PCR2_PTYP_Pos (3U)
7492#define FSMC_PCR2_PTYP_Msk (0x1UL << FSMC_PCR2_PTYP_Pos)
7493#define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk
7495#define FSMC_PCR2_PWID_Pos (4U)
7496#define FSMC_PCR2_PWID_Msk (0x3UL << FSMC_PCR2_PWID_Pos)
7497#define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk
7498#define FSMC_PCR2_PWID_0 (0x1UL << FSMC_PCR2_PWID_Pos)
7499#define FSMC_PCR2_PWID_1 (0x2UL << FSMC_PCR2_PWID_Pos)
7501#define FSMC_PCR2_ECCEN_Pos (6U)
7502#define FSMC_PCR2_ECCEN_Msk (0x1UL << FSMC_PCR2_ECCEN_Pos)
7503#define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk
7505#define FSMC_PCR2_TCLR_Pos (9U)
7506#define FSMC_PCR2_TCLR_Msk (0xFUL << FSMC_PCR2_TCLR_Pos)
7507#define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk
7508#define FSMC_PCR2_TCLR_0 (0x1UL << FSMC_PCR2_TCLR_Pos)
7509#define FSMC_PCR2_TCLR_1 (0x2UL << FSMC_PCR2_TCLR_Pos)
7510#define FSMC_PCR2_TCLR_2 (0x4UL << FSMC_PCR2_TCLR_Pos)
7511#define FSMC_PCR2_TCLR_3 (0x8UL << FSMC_PCR2_TCLR_Pos)
7513#define FSMC_PCR2_TAR_Pos (13U)
7514#define FSMC_PCR2_TAR_Msk (0xFUL << FSMC_PCR2_TAR_Pos)
7515#define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk
7516#define FSMC_PCR2_TAR_0 (0x1UL << FSMC_PCR2_TAR_Pos)
7517#define FSMC_PCR2_TAR_1 (0x2UL << FSMC_PCR2_TAR_Pos)
7518#define FSMC_PCR2_TAR_2 (0x4UL << FSMC_PCR2_TAR_Pos)
7519#define FSMC_PCR2_TAR_3 (0x8UL << FSMC_PCR2_TAR_Pos)
7521#define FSMC_PCR2_ECCPS_Pos (17U)
7522#define FSMC_PCR2_ECCPS_Msk (0x7UL << FSMC_PCR2_ECCPS_Pos)
7523#define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk
7524#define FSMC_PCR2_ECCPS_0 (0x1UL << FSMC_PCR2_ECCPS_Pos)
7525#define FSMC_PCR2_ECCPS_1 (0x2UL << FSMC_PCR2_ECCPS_Pos)
7526#define FSMC_PCR2_ECCPS_2 (0x4UL << FSMC_PCR2_ECCPS_Pos)
7528/****************** Bit definition for FSMC_PCR3 register *******************/
7529#define FSMC_PCR3_PWAITEN_Pos (1U)
7530#define FSMC_PCR3_PWAITEN_Msk (0x1UL << FSMC_PCR3_PWAITEN_Pos)
7531#define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk
7532#define FSMC_PCR3_PBKEN_Pos (2U)
7533#define FSMC_PCR3_PBKEN_Msk (0x1UL << FSMC_PCR3_PBKEN_Pos)
7534#define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk
7535#define FSMC_PCR3_PTYP_Pos (3U)
7536#define FSMC_PCR3_PTYP_Msk (0x1UL << FSMC_PCR3_PTYP_Pos)
7537#define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk
7539#define FSMC_PCR3_PWID_Pos (4U)
7540#define FSMC_PCR3_PWID_Msk (0x3UL << FSMC_PCR3_PWID_Pos)
7541#define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk
7542#define FSMC_PCR3_PWID_0 (0x1UL << FSMC_PCR3_PWID_Pos)
7543#define FSMC_PCR3_PWID_1 (0x2UL << FSMC_PCR3_PWID_Pos)
7545#define FSMC_PCR3_ECCEN_Pos (6U)
7546#define FSMC_PCR3_ECCEN_Msk (0x1UL << FSMC_PCR3_ECCEN_Pos)
7547#define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk
7549#define FSMC_PCR3_TCLR_Pos (9U)
7550#define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos)
7551#define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk
7552#define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos)
7553#define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos)
7554#define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos)
7555#define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos)
7557#define FSMC_PCR3_TAR_Pos (13U)
7558#define FSMC_PCR3_TAR_Msk (0xFUL << FSMC_PCR3_TAR_Pos)
7559#define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk
7560#define FSMC_PCR3_TAR_0 (0x1UL << FSMC_PCR3_TAR_Pos)
7561#define FSMC_PCR3_TAR_1 (0x2UL << FSMC_PCR3_TAR_Pos)
7562#define FSMC_PCR3_TAR_2 (0x4UL << FSMC_PCR3_TAR_Pos)
7563#define FSMC_PCR3_TAR_3 (0x8UL << FSMC_PCR3_TAR_Pos)
7565#define FSMC_PCR3_ECCPS_Pos (17U)
7566#define FSMC_PCR3_ECCPS_Msk (0x7UL << FSMC_PCR3_ECCPS_Pos)
7567#define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk
7568#define FSMC_PCR3_ECCPS_0 (0x1UL << FSMC_PCR3_ECCPS_Pos)
7569#define FSMC_PCR3_ECCPS_1 (0x2UL << FSMC_PCR3_ECCPS_Pos)
7570#define FSMC_PCR3_ECCPS_2 (0x4UL << FSMC_PCR3_ECCPS_Pos)
7572/****************** Bit definition for FSMC_PCR4 register *******************/
7573#define FSMC_PCR4_PWAITEN_Pos (1U)
7574#define FSMC_PCR4_PWAITEN_Msk (0x1UL << FSMC_PCR4_PWAITEN_Pos)
7575#define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk
7576#define FSMC_PCR4_PBKEN_Pos (2U)
7577#define FSMC_PCR4_PBKEN_Msk (0x1UL << FSMC_PCR4_PBKEN_Pos)
7578#define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk
7579#define FSMC_PCR4_PTYP_Pos (3U)
7580#define FSMC_PCR4_PTYP_Msk (0x1UL << FSMC_PCR4_PTYP_Pos)
7581#define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk
7583#define FSMC_PCR4_PWID_Pos (4U)
7584#define FSMC_PCR4_PWID_Msk (0x3UL << FSMC_PCR4_PWID_Pos)
7585#define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk
7586#define FSMC_PCR4_PWID_0 (0x1UL << FSMC_PCR4_PWID_Pos)
7587#define FSMC_PCR4_PWID_1 (0x2UL << FSMC_PCR4_PWID_Pos)
7589#define FSMC_PCR4_ECCEN_Pos (6U)
7590#define FSMC_PCR4_ECCEN_Msk (0x1UL << FSMC_PCR4_ECCEN_Pos)
7591#define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk
7593#define FSMC_PCR4_TCLR_Pos (9U)
7594#define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos)
7595#define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk
7596#define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos)
7597#define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos)
7598#define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos)
7599#define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos)
7601#define FSMC_PCR4_TAR_Pos (13U)
7602#define FSMC_PCR4_TAR_Msk (0xFUL << FSMC_PCR4_TAR_Pos)
7603#define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk
7604#define FSMC_PCR4_TAR_0 (0x1UL << FSMC_PCR4_TAR_Pos)
7605#define FSMC_PCR4_TAR_1 (0x2UL << FSMC_PCR4_TAR_Pos)
7606#define FSMC_PCR4_TAR_2 (0x4UL << FSMC_PCR4_TAR_Pos)
7607#define FSMC_PCR4_TAR_3 (0x8UL << FSMC_PCR4_TAR_Pos)
7609#define FSMC_PCR4_ECCPS_Pos (17U)
7610#define FSMC_PCR4_ECCPS_Msk (0x7UL << FSMC_PCR4_ECCPS_Pos)
7611#define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk
7612#define FSMC_PCR4_ECCPS_0 (0x1UL << FSMC_PCR4_ECCPS_Pos)
7613#define FSMC_PCR4_ECCPS_1 (0x2UL << FSMC_PCR4_ECCPS_Pos)
7614#define FSMC_PCR4_ECCPS_2 (0x4UL << FSMC_PCR4_ECCPS_Pos)
7616/******************* Bit definition for FSMC_SR2 register *******************/
7617#define FSMC_SR2_IRS_Pos (0U)
7618#define FSMC_SR2_IRS_Msk (0x1UL << FSMC_SR2_IRS_Pos)
7619#define FSMC_SR2_IRS FSMC_SR2_IRS_Msk
7620#define FSMC_SR2_ILS_Pos (1U)
7621#define FSMC_SR2_ILS_Msk (0x1UL << FSMC_SR2_ILS_Pos)
7622#define FSMC_SR2_ILS FSMC_SR2_ILS_Msk
7623#define FSMC_SR2_IFS_Pos (2U)
7624#define FSMC_SR2_IFS_Msk (0x1UL << FSMC_SR2_IFS_Pos)
7625#define FSMC_SR2_IFS FSMC_SR2_IFS_Msk
7626#define FSMC_SR2_IREN_Pos (3U)
7627#define FSMC_SR2_IREN_Msk (0x1UL << FSMC_SR2_IREN_Pos)
7628#define FSMC_SR2_IREN FSMC_SR2_IREN_Msk
7629#define FSMC_SR2_ILEN_Pos (4U)
7630#define FSMC_SR2_ILEN_Msk (0x1UL << FSMC_SR2_ILEN_Pos)
7631#define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk
7632#define FSMC_SR2_IFEN_Pos (5U)
7633#define FSMC_SR2_IFEN_Msk (0x1UL << FSMC_SR2_IFEN_Pos)
7634#define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk
7635#define FSMC_SR2_FEMPT_Pos (6U)
7636#define FSMC_SR2_FEMPT_Msk (0x1UL << FSMC_SR2_FEMPT_Pos)
7637#define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk
7639/******************* Bit definition for FSMC_SR3 register *******************/
7640#define FSMC_SR3_IRS_Pos (0U)
7641#define FSMC_SR3_IRS_Msk (0x1UL << FSMC_SR3_IRS_Pos)
7642#define FSMC_SR3_IRS FSMC_SR3_IRS_Msk
7643#define FSMC_SR3_ILS_Pos (1U)
7644#define FSMC_SR3_ILS_Msk (0x1UL << FSMC_SR3_ILS_Pos)
7645#define FSMC_SR3_ILS FSMC_SR3_ILS_Msk
7646#define FSMC_SR3_IFS_Pos (2U)
7647#define FSMC_SR3_IFS_Msk (0x1UL << FSMC_SR3_IFS_Pos)
7648#define FSMC_SR3_IFS FSMC_SR3_IFS_Msk
7649#define FSMC_SR3_IREN_Pos (3U)
7650#define FSMC_SR3_IREN_Msk (0x1UL << FSMC_SR3_IREN_Pos)
7651#define FSMC_SR3_IREN FSMC_SR3_IREN_Msk
7652#define FSMC_SR3_ILEN_Pos (4U)
7653#define FSMC_SR3_ILEN_Msk (0x1UL << FSMC_SR3_ILEN_Pos)
7654#define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk
7655#define FSMC_SR3_IFEN_Pos (5U)
7656#define FSMC_SR3_IFEN_Msk (0x1UL << FSMC_SR3_IFEN_Pos)
7657#define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk
7658#define FSMC_SR3_FEMPT_Pos (6U)
7659#define FSMC_SR3_FEMPT_Msk (0x1UL << FSMC_SR3_FEMPT_Pos)
7660#define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk
7662/******************* Bit definition for FSMC_SR4 register *******************/
7663#define FSMC_SR4_IRS_Pos (0U)
7664#define FSMC_SR4_IRS_Msk (0x1UL << FSMC_SR4_IRS_Pos)
7665#define FSMC_SR4_IRS FSMC_SR4_IRS_Msk
7666#define FSMC_SR4_ILS_Pos (1U)
7667#define FSMC_SR4_ILS_Msk (0x1UL << FSMC_SR4_ILS_Pos)
7668#define FSMC_SR4_ILS FSMC_SR4_ILS_Msk
7669#define FSMC_SR4_IFS_Pos (2U)
7670#define FSMC_SR4_IFS_Msk (0x1UL << FSMC_SR4_IFS_Pos)
7671#define FSMC_SR4_IFS FSMC_SR4_IFS_Msk
7672#define FSMC_SR4_IREN_Pos (3U)
7673#define FSMC_SR4_IREN_Msk (0x1UL << FSMC_SR4_IREN_Pos)
7674#define FSMC_SR4_IREN FSMC_SR4_IREN_Msk
7675#define FSMC_SR4_ILEN_Pos (4U)
7676#define FSMC_SR4_ILEN_Msk (0x1UL << FSMC_SR4_ILEN_Pos)
7677#define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk
7678#define FSMC_SR4_IFEN_Pos (5U)
7679#define FSMC_SR4_IFEN_Msk (0x1UL << FSMC_SR4_IFEN_Pos)
7680#define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk
7681#define FSMC_SR4_FEMPT_Pos (6U)
7682#define FSMC_SR4_FEMPT_Msk (0x1UL << FSMC_SR4_FEMPT_Pos)
7683#define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk
7685/****************** Bit definition for FSMC_PMEM2 register ******************/
7686#define FSMC_PMEM2_MEMSET2_Pos (0U)
7687#define FSMC_PMEM2_MEMSET2_Msk (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)
7688#define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk
7689#define FSMC_PMEM2_MEMSET2_0 (0x01UL << FSMC_PMEM2_MEMSET2_Pos)
7690#define FSMC_PMEM2_MEMSET2_1 (0x02UL << FSMC_PMEM2_MEMSET2_Pos)
7691#define FSMC_PMEM2_MEMSET2_2 (0x04UL << FSMC_PMEM2_MEMSET2_Pos)
7692#define FSMC_PMEM2_MEMSET2_3 (0x08UL << FSMC_PMEM2_MEMSET2_Pos)
7693#define FSMC_PMEM2_MEMSET2_4 (0x10UL << FSMC_PMEM2_MEMSET2_Pos)
7694#define FSMC_PMEM2_MEMSET2_5 (0x20UL << FSMC_PMEM2_MEMSET2_Pos)
7695#define FSMC_PMEM2_MEMSET2_6 (0x40UL << FSMC_PMEM2_MEMSET2_Pos)
7696#define FSMC_PMEM2_MEMSET2_7 (0x80UL << FSMC_PMEM2_MEMSET2_Pos)
7698#define FSMC_PMEM2_MEMWAIT2_Pos (8U)
7699#define FSMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)
7700#define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk
7701#define FSMC_PMEM2_MEMWAIT2_0 (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)
7702#define FSMC_PMEM2_MEMWAIT2_1 (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)
7703#define FSMC_PMEM2_MEMWAIT2_2 (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)
7704#define FSMC_PMEM2_MEMWAIT2_3 (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)
7705#define FSMC_PMEM2_MEMWAIT2_4 (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)
7706#define FSMC_PMEM2_MEMWAIT2_5 (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)
7707#define FSMC_PMEM2_MEMWAIT2_6 (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)
7708#define FSMC_PMEM2_MEMWAIT2_7 (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)
7710#define FSMC_PMEM2_MEMHOLD2_Pos (16U)
7711#define FSMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)
7712#define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk
7713#define FSMC_PMEM2_MEMHOLD2_0 (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)
7714#define FSMC_PMEM2_MEMHOLD2_1 (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)
7715#define FSMC_PMEM2_MEMHOLD2_2 (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)
7716#define FSMC_PMEM2_MEMHOLD2_3 (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)
7717#define FSMC_PMEM2_MEMHOLD2_4 (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)
7718#define FSMC_PMEM2_MEMHOLD2_5 (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)
7719#define FSMC_PMEM2_MEMHOLD2_6 (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)
7720#define FSMC_PMEM2_MEMHOLD2_7 (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)
7722#define FSMC_PMEM2_MEMHIZ2_Pos (24U)
7723#define FSMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)
7724#define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk
7725#define FSMC_PMEM2_MEMHIZ2_0 (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)
7726#define FSMC_PMEM2_MEMHIZ2_1 (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)
7727#define FSMC_PMEM2_MEMHIZ2_2 (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)
7728#define FSMC_PMEM2_MEMHIZ2_3 (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)
7729#define FSMC_PMEM2_MEMHIZ2_4 (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)
7730#define FSMC_PMEM2_MEMHIZ2_5 (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)
7731#define FSMC_PMEM2_MEMHIZ2_6 (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)
7732#define FSMC_PMEM2_MEMHIZ2_7 (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)
7734/****************** Bit definition for FSMC_PMEM3 register ******************/
7735#define FSMC_PMEM3_MEMSET3_Pos (0U)
7736#define FSMC_PMEM3_MEMSET3_Msk (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)
7737#define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk
7738#define FSMC_PMEM3_MEMSET3_0 (0x01UL << FSMC_PMEM3_MEMSET3_Pos)
7739#define FSMC_PMEM3_MEMSET3_1 (0x02UL << FSMC_PMEM3_MEMSET3_Pos)
7740#define FSMC_PMEM3_MEMSET3_2 (0x04UL << FSMC_PMEM3_MEMSET3_Pos)
7741#define FSMC_PMEM3_MEMSET3_3 (0x08UL << FSMC_PMEM3_MEMSET3_Pos)
7742#define FSMC_PMEM3_MEMSET3_4 (0x10UL << FSMC_PMEM3_MEMSET3_Pos)
7743#define FSMC_PMEM3_MEMSET3_5 (0x20UL << FSMC_PMEM3_MEMSET3_Pos)
7744#define FSMC_PMEM3_MEMSET3_6 (0x40UL << FSMC_PMEM3_MEMSET3_Pos)
7745#define FSMC_PMEM3_MEMSET3_7 (0x80UL << FSMC_PMEM3_MEMSET3_Pos)
7747#define FSMC_PMEM3_MEMWAIT3_Pos (8U)
7748#define FSMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)
7749#define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk
7750#define FSMC_PMEM3_MEMWAIT3_0 (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)
7751#define FSMC_PMEM3_MEMWAIT3_1 (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)
7752#define FSMC_PMEM3_MEMWAIT3_2 (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)
7753#define FSMC_PMEM3_MEMWAIT3_3 (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)
7754#define FSMC_PMEM3_MEMWAIT3_4 (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)
7755#define FSMC_PMEM3_MEMWAIT3_5 (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)
7756#define FSMC_PMEM3_MEMWAIT3_6 (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)
7757#define FSMC_PMEM3_MEMWAIT3_7 (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)
7759#define FSMC_PMEM3_MEMHOLD3_Pos (16U)
7760#define FSMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)
7761#define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk
7762#define FSMC_PMEM3_MEMHOLD3_0 (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)
7763#define FSMC_PMEM3_MEMHOLD3_1 (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)
7764#define FSMC_PMEM3_MEMHOLD3_2 (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)
7765#define FSMC_PMEM3_MEMHOLD3_3 (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)
7766#define FSMC_PMEM3_MEMHOLD3_4 (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)
7767#define FSMC_PMEM3_MEMHOLD3_5 (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)
7768#define FSMC_PMEM3_MEMHOLD3_6 (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)
7769#define FSMC_PMEM3_MEMHOLD3_7 (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)
7771#define FSMC_PMEM3_MEMHIZ3_Pos (24U)
7772#define FSMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)
7773#define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk
7774#define FSMC_PMEM3_MEMHIZ3_0 (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)
7775#define FSMC_PMEM3_MEMHIZ3_1 (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)
7776#define FSMC_PMEM3_MEMHIZ3_2 (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)
7777#define FSMC_PMEM3_MEMHIZ3_3 (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)
7778#define FSMC_PMEM3_MEMHIZ3_4 (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)
7779#define FSMC_PMEM3_MEMHIZ3_5 (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)
7780#define FSMC_PMEM3_MEMHIZ3_6 (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)
7781#define FSMC_PMEM3_MEMHIZ3_7 (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)
7783/****************** Bit definition for FSMC_PMEM4 register ******************/
7784#define FSMC_PMEM4_MEMSET4_Pos (0U)
7785#define FSMC_PMEM4_MEMSET4_Msk (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)
7786#define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk
7787#define FSMC_PMEM4_MEMSET4_0 (0x01UL << FSMC_PMEM4_MEMSET4_Pos)
7788#define FSMC_PMEM4_MEMSET4_1 (0x02UL << FSMC_PMEM4_MEMSET4_Pos)
7789#define FSMC_PMEM4_MEMSET4_2 (0x04UL << FSMC_PMEM4_MEMSET4_Pos)
7790#define FSMC_PMEM4_MEMSET4_3 (0x08UL << FSMC_PMEM4_MEMSET4_Pos)
7791#define FSMC_PMEM4_MEMSET4_4 (0x10UL << FSMC_PMEM4_MEMSET4_Pos)
7792#define FSMC_PMEM4_MEMSET4_5 (0x20UL << FSMC_PMEM4_MEMSET4_Pos)
7793#define FSMC_PMEM4_MEMSET4_6 (0x40UL << FSMC_PMEM4_MEMSET4_Pos)
7794#define FSMC_PMEM4_MEMSET4_7 (0x80UL << FSMC_PMEM4_MEMSET4_Pos)
7796#define FSMC_PMEM4_MEMWAIT4_Pos (8U)
7797#define FSMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)
7798#define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk
7799#define FSMC_PMEM4_MEMWAIT4_0 (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)
7800#define FSMC_PMEM4_MEMWAIT4_1 (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)
7801#define FSMC_PMEM4_MEMWAIT4_2 (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)
7802#define FSMC_PMEM4_MEMWAIT4_3 (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)
7803#define FSMC_PMEM4_MEMWAIT4_4 (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)
7804#define FSMC_PMEM4_MEMWAIT4_5 (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)
7805#define FSMC_PMEM4_MEMWAIT4_6 (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)
7806#define FSMC_PMEM4_MEMWAIT4_7 (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)
7808#define FSMC_PMEM4_MEMHOLD4_Pos (16U)
7809#define FSMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)
7810#define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk
7811#define FSMC_PMEM4_MEMHOLD4_0 (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)
7812#define FSMC_PMEM4_MEMHOLD4_1 (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)
7813#define FSMC_PMEM4_MEMHOLD4_2 (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)
7814#define FSMC_PMEM4_MEMHOLD4_3 (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)
7815#define FSMC_PMEM4_MEMHOLD4_4 (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)
7816#define FSMC_PMEM4_MEMHOLD4_5 (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)
7817#define FSMC_PMEM4_MEMHOLD4_6 (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)
7818#define FSMC_PMEM4_MEMHOLD4_7 (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)
7820#define FSMC_PMEM4_MEMHIZ4_Pos (24U)
7821#define FSMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)
7822#define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk
7823#define FSMC_PMEM4_MEMHIZ4_0 (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)
7824#define FSMC_PMEM4_MEMHIZ4_1 (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)
7825#define FSMC_PMEM4_MEMHIZ4_2 (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)
7826#define FSMC_PMEM4_MEMHIZ4_3 (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)
7827#define FSMC_PMEM4_MEMHIZ4_4 (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)
7828#define FSMC_PMEM4_MEMHIZ4_5 (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)
7829#define FSMC_PMEM4_MEMHIZ4_6 (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)
7830#define FSMC_PMEM4_MEMHIZ4_7 (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)
7832/****************** Bit definition for FSMC_PATT2 register ******************/
7833#define FSMC_PATT2_ATTSET2_Pos (0U)
7834#define FSMC_PATT2_ATTSET2_Msk (0xFFUL << FSMC_PATT2_ATTSET2_Pos)
7835#define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk
7836#define FSMC_PATT2_ATTSET2_0 (0x01UL << FSMC_PATT2_ATTSET2_Pos)
7837#define FSMC_PATT2_ATTSET2_1 (0x02UL << FSMC_PATT2_ATTSET2_Pos)
7838#define FSMC_PATT2_ATTSET2_2 (0x04UL << FSMC_PATT2_ATTSET2_Pos)
7839#define FSMC_PATT2_ATTSET2_3 (0x08UL << FSMC_PATT2_ATTSET2_Pos)
7840#define FSMC_PATT2_ATTSET2_4 (0x10UL << FSMC_PATT2_ATTSET2_Pos)
7841#define FSMC_PATT2_ATTSET2_5 (0x20UL << FSMC_PATT2_ATTSET2_Pos)
7842#define FSMC_PATT2_ATTSET2_6 (0x40UL << FSMC_PATT2_ATTSET2_Pos)
7843#define FSMC_PATT2_ATTSET2_7 (0x80UL << FSMC_PATT2_ATTSET2_Pos)
7845#define FSMC_PATT2_ATTWAIT2_Pos (8U)
7846#define FSMC_PATT2_ATTWAIT2_Msk (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)
7847#define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk
7848#define FSMC_PATT2_ATTWAIT2_0 (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)
7849#define FSMC_PATT2_ATTWAIT2_1 (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)
7850#define FSMC_PATT2_ATTWAIT2_2 (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)
7851#define FSMC_PATT2_ATTWAIT2_3 (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)
7852#define FSMC_PATT2_ATTWAIT2_4 (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)
7853#define FSMC_PATT2_ATTWAIT2_5 (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)
7854#define FSMC_PATT2_ATTWAIT2_6 (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)
7855#define FSMC_PATT2_ATTWAIT2_7 (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)
7857#define FSMC_PATT2_ATTHOLD2_Pos (16U)
7858#define FSMC_PATT2_ATTHOLD2_Msk (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)
7859#define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk
7860#define FSMC_PATT2_ATTHOLD2_0 (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)
7861#define FSMC_PATT2_ATTHOLD2_1 (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)
7862#define FSMC_PATT2_ATTHOLD2_2 (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)
7863#define FSMC_PATT2_ATTHOLD2_3 (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)
7864#define FSMC_PATT2_ATTHOLD2_4 (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)
7865#define FSMC_PATT2_ATTHOLD2_5 (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)
7866#define FSMC_PATT2_ATTHOLD2_6 (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)
7867#define FSMC_PATT2_ATTHOLD2_7 (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)
7869#define FSMC_PATT2_ATTHIZ2_Pos (24U)
7870#define FSMC_PATT2_ATTHIZ2_Msk (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)
7871#define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk
7872#define FSMC_PATT2_ATTHIZ2_0 (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)
7873#define FSMC_PATT2_ATTHIZ2_1 (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)
7874#define FSMC_PATT2_ATTHIZ2_2 (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)
7875#define FSMC_PATT2_ATTHIZ2_3 (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)
7876#define FSMC_PATT2_ATTHIZ2_4 (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)
7877#define FSMC_PATT2_ATTHIZ2_5 (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)
7878#define FSMC_PATT2_ATTHIZ2_6 (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)
7879#define FSMC_PATT2_ATTHIZ2_7 (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)
7881/****************** Bit definition for FSMC_PATT3 register ******************/
7882#define FSMC_PATT3_ATTSET3_Pos (0U)
7883#define FSMC_PATT3_ATTSET3_Msk (0xFFUL << FSMC_PATT3_ATTSET3_Pos)
7884#define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk
7885#define FSMC_PATT3_ATTSET3_0 (0x01UL << FSMC_PATT3_ATTSET3_Pos)
7886#define FSMC_PATT3_ATTSET3_1 (0x02UL << FSMC_PATT3_ATTSET3_Pos)
7887#define FSMC_PATT3_ATTSET3_2 (0x04UL << FSMC_PATT3_ATTSET3_Pos)
7888#define FSMC_PATT3_ATTSET3_3 (0x08UL << FSMC_PATT3_ATTSET3_Pos)
7889#define FSMC_PATT3_ATTSET3_4 (0x10UL << FSMC_PATT3_ATTSET3_Pos)
7890#define FSMC_PATT3_ATTSET3_5 (0x20UL << FSMC_PATT3_ATTSET3_Pos)
7891#define FSMC_PATT3_ATTSET3_6 (0x40UL << FSMC_PATT3_ATTSET3_Pos)
7892#define FSMC_PATT3_ATTSET3_7 (0x80UL << FSMC_PATT3_ATTSET3_Pos)
7894#define FSMC_PATT3_ATTWAIT3_Pos (8U)
7895#define FSMC_PATT3_ATTWAIT3_Msk (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)
7896#define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk
7897#define FSMC_PATT3_ATTWAIT3_0 (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)
7898#define FSMC_PATT3_ATTWAIT3_1 (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)
7899#define FSMC_PATT3_ATTWAIT3_2 (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)
7900#define FSMC_PATT3_ATTWAIT3_3 (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)
7901#define FSMC_PATT3_ATTWAIT3_4 (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)
7902#define FSMC_PATT3_ATTWAIT3_5 (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)
7903#define FSMC_PATT3_ATTWAIT3_6 (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)
7904#define FSMC_PATT3_ATTWAIT3_7 (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)
7906#define FSMC_PATT3_ATTHOLD3_Pos (16U)
7907#define FSMC_PATT3_ATTHOLD3_Msk (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)
7908#define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk
7909#define FSMC_PATT3_ATTHOLD3_0 (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)
7910#define FSMC_PATT3_ATTHOLD3_1 (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)
7911#define FSMC_PATT3_ATTHOLD3_2 (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)
7912#define FSMC_PATT3_ATTHOLD3_3 (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)
7913#define FSMC_PATT3_ATTHOLD3_4 (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)
7914#define FSMC_PATT3_ATTHOLD3_5 (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)
7915#define FSMC_PATT3_ATTHOLD3_6 (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)
7916#define FSMC_PATT3_ATTHOLD3_7 (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)
7918#define FSMC_PATT3_ATTHIZ3_Pos (24U)
7919#define FSMC_PATT3_ATTHIZ3_Msk (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)
7920#define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk
7921#define FSMC_PATT3_ATTHIZ3_0 (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)
7922#define FSMC_PATT3_ATTHIZ3_1 (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)
7923#define FSMC_PATT3_ATTHIZ3_2 (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)
7924#define FSMC_PATT3_ATTHIZ3_3 (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)
7925#define FSMC_PATT3_ATTHIZ3_4 (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)
7926#define FSMC_PATT3_ATTHIZ3_5 (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)
7927#define FSMC_PATT3_ATTHIZ3_6 (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)
7928#define FSMC_PATT3_ATTHIZ3_7 (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)
7930/****************** Bit definition for FSMC_PATT4 register ******************/
7931#define FSMC_PATT4_ATTSET4_Pos (0U)
7932#define FSMC_PATT4_ATTSET4_Msk (0xFFUL << FSMC_PATT4_ATTSET4_Pos)
7933#define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk
7934#define FSMC_PATT4_ATTSET4_0 (0x01UL << FSMC_PATT4_ATTSET4_Pos)
7935#define FSMC_PATT4_ATTSET4_1 (0x02UL << FSMC_PATT4_ATTSET4_Pos)
7936#define FSMC_PATT4_ATTSET4_2 (0x04UL << FSMC_PATT4_ATTSET4_Pos)
7937#define FSMC_PATT4_ATTSET4_3 (0x08UL << FSMC_PATT4_ATTSET4_Pos)
7938#define FSMC_PATT4_ATTSET4_4 (0x10UL << FSMC_PATT4_ATTSET4_Pos)
7939#define FSMC_PATT4_ATTSET4_5 (0x20UL << FSMC_PATT4_ATTSET4_Pos)
7940#define FSMC_PATT4_ATTSET4_6 (0x40UL << FSMC_PATT4_ATTSET4_Pos)
7941#define FSMC_PATT4_ATTSET4_7 (0x80UL << FSMC_PATT4_ATTSET4_Pos)
7943#define FSMC_PATT4_ATTWAIT4_Pos (8U)
7944#define FSMC_PATT4_ATTWAIT4_Msk (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)
7945#define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk
7946#define FSMC_PATT4_ATTWAIT4_0 (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)
7947#define FSMC_PATT4_ATTWAIT4_1 (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)
7948#define FSMC_PATT4_ATTWAIT4_2 (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)
7949#define FSMC_PATT4_ATTWAIT4_3 (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)
7950#define FSMC_PATT4_ATTWAIT4_4 (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)
7951#define FSMC_PATT4_ATTWAIT4_5 (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)
7952#define FSMC_PATT4_ATTWAIT4_6 (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)
7953#define FSMC_PATT4_ATTWAIT4_7 (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)
7955#define FSMC_PATT4_ATTHOLD4_Pos (16U)
7956#define FSMC_PATT4_ATTHOLD4_Msk (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)
7957#define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk
7958#define FSMC_PATT4_ATTHOLD4_0 (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)
7959#define FSMC_PATT4_ATTHOLD4_1 (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)
7960#define FSMC_PATT4_ATTHOLD4_2 (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)
7961#define FSMC_PATT4_ATTHOLD4_3 (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)
7962#define FSMC_PATT4_ATTHOLD4_4 (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)
7963#define FSMC_PATT4_ATTHOLD4_5 (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)
7964#define FSMC_PATT4_ATTHOLD4_6 (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)
7965#define FSMC_PATT4_ATTHOLD4_7 (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)
7967#define FSMC_PATT4_ATTHIZ4_Pos (24U)
7968#define FSMC_PATT4_ATTHIZ4_Msk (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)
7969#define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk
7970#define FSMC_PATT4_ATTHIZ4_0 (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)
7971#define FSMC_PATT4_ATTHIZ4_1 (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)
7972#define FSMC_PATT4_ATTHIZ4_2 (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)
7973#define FSMC_PATT4_ATTHIZ4_3 (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)
7974#define FSMC_PATT4_ATTHIZ4_4 (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)
7975#define FSMC_PATT4_ATTHIZ4_5 (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)
7976#define FSMC_PATT4_ATTHIZ4_6 (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)
7977#define FSMC_PATT4_ATTHIZ4_7 (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)
7979/****************** Bit definition for FSMC_PIO4 register *******************/
7980#define FSMC_PIO4_IOSET4_Pos (0U)
7981#define FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos)
7982#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk
7983#define FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos)
7984#define FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos)
7985#define FSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos)
7986#define FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos)
7987#define FSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos)
7988#define FSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos)
7989#define FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos)
7990#define FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos)
7992#define FSMC_PIO4_IOWAIT4_Pos (8U)
7993#define FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)
7994#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk
7995#define FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos)
7996#define FSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos)
7997#define FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos)
7998#define FSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos)
7999#define FSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos)
8000#define FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos)
8001#define FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos)
8002#define FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos)
8004#define FSMC_PIO4_IOHOLD4_Pos (16U)
8005#define FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)
8006#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk
8007#define FSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos)
8008#define FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos)
8009#define FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos)
8010#define FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos)
8011#define FSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos)
8012#define FSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos)
8013#define FSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos)
8014#define FSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos)
8016#define FSMC_PIO4_IOHIZ4_Pos (24U)
8017#define FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)
8018#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk
8019#define FSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos)
8020#define FSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos)
8021#define FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos)
8022#define FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos)
8023#define FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos)
8024#define FSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos)
8025#define FSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos)
8026#define FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos)
8028/****************** Bit definition for FSMC_ECCR2 register ******************/
8029#define FSMC_ECCR2_ECC2_Pos (0U)
8030#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)
8031#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk
8033/****************** Bit definition for FSMC_ECCR3 register ******************/
8034#define FSMC_ECCR3_ECC3_Pos (0U)
8035#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)
8036#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk
8038/******************************************************************************/
8039/* */
8040/* General Purpose I/O */
8041/* */
8042/******************************************************************************/
8043/****************** Bits definition for GPIO_MODER register *****************/
8044#define GPIO_MODER_MODER0_Pos (0U)
8045#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
8046#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8047#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
8048#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
8049#define GPIO_MODER_MODER1_Pos (2U)
8050#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
8051#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8052#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
8053#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
8054#define GPIO_MODER_MODER2_Pos (4U)
8055#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
8056#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8057#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
8058#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
8059#define GPIO_MODER_MODER3_Pos (6U)
8060#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
8061#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8062#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
8063#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
8064#define GPIO_MODER_MODER4_Pos (8U)
8065#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
8066#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8067#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
8068#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
8069#define GPIO_MODER_MODER5_Pos (10U)
8070#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
8071#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8072#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
8073#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
8074#define GPIO_MODER_MODER6_Pos (12U)
8075#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
8076#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8077#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
8078#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
8079#define GPIO_MODER_MODER7_Pos (14U)
8080#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
8081#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8082#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
8083#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
8084#define GPIO_MODER_MODER8_Pos (16U)
8085#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
8086#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8087#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
8088#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
8089#define GPIO_MODER_MODER9_Pos (18U)
8090#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
8091#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8092#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
8093#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
8094#define GPIO_MODER_MODER10_Pos (20U)
8095#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
8096#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8097#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
8098#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
8099#define GPIO_MODER_MODER11_Pos (22U)
8100#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
8101#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8102#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
8103#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
8104#define GPIO_MODER_MODER12_Pos (24U)
8105#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
8106#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8107#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
8108#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
8109#define GPIO_MODER_MODER13_Pos (26U)
8110#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
8111#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8112#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
8113#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
8114#define GPIO_MODER_MODER14_Pos (28U)
8115#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
8116#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8117#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
8118#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
8119#define GPIO_MODER_MODER15_Pos (30U)
8120#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
8121#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8122#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
8123#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
8125/* Legacy defines */
8126#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
8127#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
8128#define GPIO_MODER_MODE0 GPIO_MODER_MODER0
8129#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
8130#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
8131#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
8132#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
8133#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
8134#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
8135#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
8136#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
8137#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
8138#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
8139#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
8140#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
8141#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
8142#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
8143#define GPIO_MODER_MODE3 GPIO_MODER_MODER3
8144#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
8145#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
8146#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
8147#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
8148#define GPIO_MODER_MODE4 GPIO_MODER_MODER4
8149#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
8150#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
8151#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
8152#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
8153#define GPIO_MODER_MODE5 GPIO_MODER_MODER5
8154#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
8155#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
8156#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
8157#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
8158#define GPIO_MODER_MODE6 GPIO_MODER_MODER6
8159#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
8160#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
8161#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
8162#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
8163#define GPIO_MODER_MODE7 GPIO_MODER_MODER7
8164#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
8165#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
8166#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
8167#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
8168#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
8169#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
8170#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
8171#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
8172#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
8173#define GPIO_MODER_MODE9 GPIO_MODER_MODER9
8174#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
8175#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
8176#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
8177#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
8178#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
8179#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
8180#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
8181#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
8182#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
8183#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
8184#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
8185#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
8186#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
8187#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
8188#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
8189#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
8190#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
8191#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
8192#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
8193#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
8194#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
8195#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
8196#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
8197#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
8198#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
8199#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
8200#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
8201#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
8202#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
8203#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
8204#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
8205#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
8206
8207/****************** Bits definition for GPIO_OTYPER register ****************/
8208#define GPIO_OTYPER_OT0_Pos (0U)
8209#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
8210#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8211#define GPIO_OTYPER_OT1_Pos (1U)
8212#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
8213#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8214#define GPIO_OTYPER_OT2_Pos (2U)
8215#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
8216#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8217#define GPIO_OTYPER_OT3_Pos (3U)
8218#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
8219#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8220#define GPIO_OTYPER_OT4_Pos (4U)
8221#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
8222#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8223#define GPIO_OTYPER_OT5_Pos (5U)
8224#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
8225#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8226#define GPIO_OTYPER_OT6_Pos (6U)
8227#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
8228#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8229#define GPIO_OTYPER_OT7_Pos (7U)
8230#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
8231#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8232#define GPIO_OTYPER_OT8_Pos (8U)
8233#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
8234#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8235#define GPIO_OTYPER_OT9_Pos (9U)
8236#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
8237#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8238#define GPIO_OTYPER_OT10_Pos (10U)
8239#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
8240#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8241#define GPIO_OTYPER_OT11_Pos (11U)
8242#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
8243#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8244#define GPIO_OTYPER_OT12_Pos (12U)
8245#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
8246#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8247#define GPIO_OTYPER_OT13_Pos (13U)
8248#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
8249#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8250#define GPIO_OTYPER_OT14_Pos (14U)
8251#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
8252#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8253#define GPIO_OTYPER_OT15_Pos (15U)
8254#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
8255#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8256
8257/* Legacy defines */
8258#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8259#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8260#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8261#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8262#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8263#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8264#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8265#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8266#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8267#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8268#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8269#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8270#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8271#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8272#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8273#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8274
8275/****************** Bits definition for GPIO_OSPEEDR register ***************/
8276#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8277#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
8278#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8279#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
8280#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
8281#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8282#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
8283#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8284#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
8285#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
8286#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8287#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
8288#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8289#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
8290#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
8291#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8292#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
8293#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8294#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
8295#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
8296#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8297#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
8298#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8299#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
8300#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
8301#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8302#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
8303#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8304#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
8305#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
8306#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8307#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
8308#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8309#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
8310#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
8311#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8312#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
8313#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8314#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
8315#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
8316#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8317#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
8318#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8319#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
8320#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
8321#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8322#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
8323#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8324#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
8325#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
8326#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8327#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
8328#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8329#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
8330#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
8331#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8332#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
8333#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8334#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
8335#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
8336#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8337#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
8338#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8339#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
8340#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
8341#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8342#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
8343#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8344#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
8345#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
8346#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8347#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
8348#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8349#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
8350#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
8351#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8352#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
8353#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8354#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
8355#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
8357/* Legacy defines */
8358#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8359#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8360#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8361#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8362#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8363#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8364#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8365#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8366#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8367#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8368#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8369#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8370#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8371#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8372#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8373#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8374#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8375#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8376#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8377#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8378#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8379#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8380#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8381#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8382#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8383#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8384#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8385#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8386#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8387#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8388#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8389#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8390#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8391#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8392#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8393#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8394#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8395#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8396#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8397#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8398#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8399#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8400#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8401#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8402#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8403#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8404#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8405#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8406
8407/****************** Bits definition for GPIO_PUPDR register *****************/
8408#define GPIO_PUPDR_PUPD0_Pos (0U)
8409#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
8410#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8411#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
8412#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
8413#define GPIO_PUPDR_PUPD1_Pos (2U)
8414#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
8415#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8416#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
8417#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
8418#define GPIO_PUPDR_PUPD2_Pos (4U)
8419#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
8420#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8421#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
8422#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
8423#define GPIO_PUPDR_PUPD3_Pos (6U)
8424#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
8425#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8426#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
8427#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
8428#define GPIO_PUPDR_PUPD4_Pos (8U)
8429#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
8430#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8431#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
8432#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
8433#define GPIO_PUPDR_PUPD5_Pos (10U)
8434#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
8435#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8436#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
8437#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
8438#define GPIO_PUPDR_PUPD6_Pos (12U)
8439#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
8440#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8441#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
8442#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
8443#define GPIO_PUPDR_PUPD7_Pos (14U)
8444#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
8445#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8446#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
8447#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
8448#define GPIO_PUPDR_PUPD8_Pos (16U)
8449#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
8450#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8451#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
8452#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
8453#define GPIO_PUPDR_PUPD9_Pos (18U)
8454#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
8455#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8456#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
8457#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
8458#define GPIO_PUPDR_PUPD10_Pos (20U)
8459#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
8460#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8461#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
8462#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
8463#define GPIO_PUPDR_PUPD11_Pos (22U)
8464#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
8465#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8466#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
8467#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
8468#define GPIO_PUPDR_PUPD12_Pos (24U)
8469#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
8470#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8471#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
8472#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
8473#define GPIO_PUPDR_PUPD13_Pos (26U)
8474#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
8475#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8476#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
8477#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
8478#define GPIO_PUPDR_PUPD14_Pos (28U)
8479#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
8480#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8481#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
8482#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
8483#define GPIO_PUPDR_PUPD15_Pos (30U)
8484#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
8485#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8486#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
8487#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
8489/* Legacy defines */
8490#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8491#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8492#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8493#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8494#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8495#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8496#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8497#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8498#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8499#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8500#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8501#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8502#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8503#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8504#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8505#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8506#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8507#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8508#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8509#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8510#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8511#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8512#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8513#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8514#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8515#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8516#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8517#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8518#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8519#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8520#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8521#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8522#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8523#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8524#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8525#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8526#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8527#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8528#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8529#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8530#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8531#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8532#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8533#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8534#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8535#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8536#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8537#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8538
8539/****************** Bits definition for GPIO_IDR register *******************/
8540#define GPIO_IDR_ID0_Pos (0U)
8541#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
8542#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8543#define GPIO_IDR_ID1_Pos (1U)
8544#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
8545#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8546#define GPIO_IDR_ID2_Pos (2U)
8547#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
8548#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8549#define GPIO_IDR_ID3_Pos (3U)
8550#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
8551#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8552#define GPIO_IDR_ID4_Pos (4U)
8553#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
8554#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8555#define GPIO_IDR_ID5_Pos (5U)
8556#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
8557#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8558#define GPIO_IDR_ID6_Pos (6U)
8559#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
8560#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8561#define GPIO_IDR_ID7_Pos (7U)
8562#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
8563#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8564#define GPIO_IDR_ID8_Pos (8U)
8565#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
8566#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8567#define GPIO_IDR_ID9_Pos (9U)
8568#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
8569#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8570#define GPIO_IDR_ID10_Pos (10U)
8571#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
8572#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8573#define GPIO_IDR_ID11_Pos (11U)
8574#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
8575#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8576#define GPIO_IDR_ID12_Pos (12U)
8577#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
8578#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8579#define GPIO_IDR_ID13_Pos (13U)
8580#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
8581#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8582#define GPIO_IDR_ID14_Pos (14U)
8583#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
8584#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8585#define GPIO_IDR_ID15_Pos (15U)
8586#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
8587#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8588
8589/* Legacy defines */
8590#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8591#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8592#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8593#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8594#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8595#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8596#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8597#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8598#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8599#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8600#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8601#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8602#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8603#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8604#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8605#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8606
8607/****************** Bits definition for GPIO_ODR register *******************/
8608#define GPIO_ODR_OD0_Pos (0U)
8609#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
8610#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8611#define GPIO_ODR_OD1_Pos (1U)
8612#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
8613#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8614#define GPIO_ODR_OD2_Pos (2U)
8615#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
8616#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8617#define GPIO_ODR_OD3_Pos (3U)
8618#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
8619#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8620#define GPIO_ODR_OD4_Pos (4U)
8621#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
8622#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8623#define GPIO_ODR_OD5_Pos (5U)
8624#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
8625#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8626#define GPIO_ODR_OD6_Pos (6U)
8627#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
8628#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8629#define GPIO_ODR_OD7_Pos (7U)
8630#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
8631#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8632#define GPIO_ODR_OD8_Pos (8U)
8633#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
8634#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8635#define GPIO_ODR_OD9_Pos (9U)
8636#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
8637#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8638#define GPIO_ODR_OD10_Pos (10U)
8639#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
8640#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8641#define GPIO_ODR_OD11_Pos (11U)
8642#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
8643#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8644#define GPIO_ODR_OD12_Pos (12U)
8645#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
8646#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8647#define GPIO_ODR_OD13_Pos (13U)
8648#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
8649#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8650#define GPIO_ODR_OD14_Pos (14U)
8651#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
8652#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8653#define GPIO_ODR_OD15_Pos (15U)
8654#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
8655#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8656/* Legacy defines */
8657#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8658#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8659#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8660#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8661#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8662#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8663#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8664#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8665#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8666#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8667#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8668#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8669#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8670#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8671#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8672#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8673
8674/****************** Bits definition for GPIO_BSRR register ******************/
8675#define GPIO_BSRR_BS0_Pos (0U)
8676#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
8677#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8678#define GPIO_BSRR_BS1_Pos (1U)
8679#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
8680#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8681#define GPIO_BSRR_BS2_Pos (2U)
8682#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
8683#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8684#define GPIO_BSRR_BS3_Pos (3U)
8685#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
8686#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8687#define GPIO_BSRR_BS4_Pos (4U)
8688#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
8689#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8690#define GPIO_BSRR_BS5_Pos (5U)
8691#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
8692#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8693#define GPIO_BSRR_BS6_Pos (6U)
8694#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
8695#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8696#define GPIO_BSRR_BS7_Pos (7U)
8697#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
8698#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8699#define GPIO_BSRR_BS8_Pos (8U)
8700#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
8701#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8702#define GPIO_BSRR_BS9_Pos (9U)
8703#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
8704#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8705#define GPIO_BSRR_BS10_Pos (10U)
8706#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
8707#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8708#define GPIO_BSRR_BS11_Pos (11U)
8709#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
8710#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8711#define GPIO_BSRR_BS12_Pos (12U)
8712#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
8713#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8714#define GPIO_BSRR_BS13_Pos (13U)
8715#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
8716#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8717#define GPIO_BSRR_BS14_Pos (14U)
8718#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
8719#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8720#define GPIO_BSRR_BS15_Pos (15U)
8721#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
8722#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8723#define GPIO_BSRR_BR0_Pos (16U)
8724#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
8725#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8726#define GPIO_BSRR_BR1_Pos (17U)
8727#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
8728#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8729#define GPIO_BSRR_BR2_Pos (18U)
8730#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
8731#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8732#define GPIO_BSRR_BR3_Pos (19U)
8733#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
8734#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8735#define GPIO_BSRR_BR4_Pos (20U)
8736#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8737#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8738#define GPIO_BSRR_BR5_Pos (21U)
8739#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8740#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8741#define GPIO_BSRR_BR6_Pos (22U)
8742#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8743#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8744#define GPIO_BSRR_BR7_Pos (23U)
8745#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8746#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8747#define GPIO_BSRR_BR8_Pos (24U)
8748#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8749#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8750#define GPIO_BSRR_BR9_Pos (25U)
8751#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8752#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8753#define GPIO_BSRR_BR10_Pos (26U)
8754#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8755#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8756#define GPIO_BSRR_BR11_Pos (27U)
8757#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8758#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8759#define GPIO_BSRR_BR12_Pos (28U)
8760#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8761#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8762#define GPIO_BSRR_BR13_Pos (29U)
8763#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8764#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8765#define GPIO_BSRR_BR14_Pos (30U)
8766#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8767#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8768#define GPIO_BSRR_BR15_Pos (31U)
8769#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8770#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8771
8772/* Legacy defines */
8773#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8774#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8775#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8776#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8777#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8778#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8779#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8780#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8781#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8782#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8783#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8784#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8785#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8786#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8787#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8788#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8789#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8790#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8791#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8792#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8793#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8794#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8795#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8796#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8797#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8798#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8799#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8800#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8801#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8802#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8803#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8804#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8805#define GPIO_BRR_BR0 GPIO_BSRR_BR0
8806#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
8807#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
8808#define GPIO_BRR_BR1 GPIO_BSRR_BR1
8809#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
8810#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
8811#define GPIO_BRR_BR2 GPIO_BSRR_BR2
8812#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
8813#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
8814#define GPIO_BRR_BR3 GPIO_BSRR_BR3
8815#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
8816#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
8817#define GPIO_BRR_BR4 GPIO_BSRR_BR4
8818#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
8819#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
8820#define GPIO_BRR_BR5 GPIO_BSRR_BR5
8821#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
8822#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
8823#define GPIO_BRR_BR6 GPIO_BSRR_BR6
8824#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
8825#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
8826#define GPIO_BRR_BR7 GPIO_BSRR_BR7
8827#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
8828#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
8829#define GPIO_BRR_BR8 GPIO_BSRR_BR8
8830#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
8831#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
8832#define GPIO_BRR_BR9 GPIO_BSRR_BR9
8833#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
8834#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
8835#define GPIO_BRR_BR10 GPIO_BSRR_BR10
8836#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
8837#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
8838#define GPIO_BRR_BR11 GPIO_BSRR_BR11
8839#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
8840#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
8841#define GPIO_BRR_BR12 GPIO_BSRR_BR12
8842#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
8843#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
8844#define GPIO_BRR_BR13 GPIO_BSRR_BR13
8845#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
8846#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
8847#define GPIO_BRR_BR14 GPIO_BSRR_BR14
8848#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
8849#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
8850#define GPIO_BRR_BR15 GPIO_BSRR_BR15
8851#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
8852#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
8853/****************** Bit definition for GPIO_LCKR register *********************/
8854#define GPIO_LCKR_LCK0_Pos (0U)
8855#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8856#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8857#define GPIO_LCKR_LCK1_Pos (1U)
8858#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8859#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8860#define GPIO_LCKR_LCK2_Pos (2U)
8861#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8862#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8863#define GPIO_LCKR_LCK3_Pos (3U)
8864#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8865#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8866#define GPIO_LCKR_LCK4_Pos (4U)
8867#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8868#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8869#define GPIO_LCKR_LCK5_Pos (5U)
8870#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8871#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8872#define GPIO_LCKR_LCK6_Pos (6U)
8873#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8874#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8875#define GPIO_LCKR_LCK7_Pos (7U)
8876#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8877#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8878#define GPIO_LCKR_LCK8_Pos (8U)
8879#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8880#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8881#define GPIO_LCKR_LCK9_Pos (9U)
8882#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8883#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8884#define GPIO_LCKR_LCK10_Pos (10U)
8885#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8886#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8887#define GPIO_LCKR_LCK11_Pos (11U)
8888#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8889#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8890#define GPIO_LCKR_LCK12_Pos (12U)
8891#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8892#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8893#define GPIO_LCKR_LCK13_Pos (13U)
8894#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8895#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8896#define GPIO_LCKR_LCK14_Pos (14U)
8897#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8898#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8899#define GPIO_LCKR_LCK15_Pos (15U)
8900#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8901#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8902#define GPIO_LCKR_LCKK_Pos (16U)
8903#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8904#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8905/****************** Bit definition for GPIO_AFRL register *********************/
8906#define GPIO_AFRL_AFSEL0_Pos (0U)
8907#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
8908#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8909#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
8910#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
8911#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
8912#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
8913#define GPIO_AFRL_AFSEL1_Pos (4U)
8914#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
8915#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8916#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
8917#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
8918#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
8919#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
8920#define GPIO_AFRL_AFSEL2_Pos (8U)
8921#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
8922#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8923#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
8924#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
8925#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
8926#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
8927#define GPIO_AFRL_AFSEL3_Pos (12U)
8928#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
8929#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8930#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
8931#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
8932#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
8933#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
8934#define GPIO_AFRL_AFSEL4_Pos (16U)
8935#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
8936#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8937#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
8938#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
8939#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
8940#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
8941#define GPIO_AFRL_AFSEL5_Pos (20U)
8942#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
8943#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8944#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
8945#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
8946#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
8947#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
8948#define GPIO_AFRL_AFSEL6_Pos (24U)
8949#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
8950#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8951#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
8952#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
8953#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
8954#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
8955#define GPIO_AFRL_AFSEL7_Pos (28U)
8956#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
8957#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8958#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
8959#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
8960#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
8961#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
8963/* Legacy defines */
8964#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8965#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8966#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8967#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8968#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8969#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8970#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8971#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8972#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8973#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8974#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8975#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8976#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8977#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8978#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8979#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8980#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8981#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8982#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8983#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8984#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8985#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8986#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8987#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8988#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8989#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8990#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8991#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
8992#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
8993#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
8994#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8995#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
8996#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
8997#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
8998#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
8999#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
9000#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
9001#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
9002#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
9003#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
9004
9005/****************** Bit definition for GPIO_AFRH register *********************/
9006#define GPIO_AFRH_AFSEL8_Pos (0U)
9007#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
9008#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
9009#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
9010#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
9011#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
9012#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
9013#define GPIO_AFRH_AFSEL9_Pos (4U)
9014#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
9015#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
9016#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
9017#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
9018#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
9019#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
9020#define GPIO_AFRH_AFSEL10_Pos (8U)
9021#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
9022#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
9023#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
9024#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
9025#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
9026#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
9027#define GPIO_AFRH_AFSEL11_Pos (12U)
9028#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
9029#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
9030#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
9031#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
9032#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
9033#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
9034#define GPIO_AFRH_AFSEL12_Pos (16U)
9035#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
9036#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
9037#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
9038#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
9039#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
9040#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
9041#define GPIO_AFRH_AFSEL13_Pos (20U)
9042#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
9043#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
9044#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
9045#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
9046#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
9047#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
9048#define GPIO_AFRH_AFSEL14_Pos (24U)
9049#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
9050#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
9051#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
9052#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
9053#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
9054#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
9055#define GPIO_AFRH_AFSEL15_Pos (28U)
9056#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
9057#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
9058#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
9059#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
9060#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
9061#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
9063/* Legacy defines */
9064#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
9065#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
9066#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
9067#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
9068#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
9069#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
9070#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
9071#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
9072#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
9073#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
9074#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
9075#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
9076#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
9077#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
9078#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
9079#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
9080#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
9081#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
9082#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
9083#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
9084#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
9085#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
9086#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
9087#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
9088#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
9089#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
9090#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
9091#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
9092#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
9093#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
9094#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
9095#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
9096#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
9097#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
9098#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
9099#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
9100#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
9101#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
9102#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
9103#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
9104
9105
9106/******************************************************************************/
9107/* */
9108/* Inter-integrated Circuit Interface */
9109/* */
9110/******************************************************************************/
9111/******************* Bit definition for I2C_CR1 register ********************/
9112#define I2C_CR1_PE_Pos (0U)
9113#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
9114#define I2C_CR1_PE I2C_CR1_PE_Msk
9115#define I2C_CR1_SMBUS_Pos (1U)
9116#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
9117#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
9118#define I2C_CR1_SMBTYPE_Pos (3U)
9119#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
9120#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
9121#define I2C_CR1_ENARP_Pos (4U)
9122#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
9123#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
9124#define I2C_CR1_ENPEC_Pos (5U)
9125#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
9126#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
9127#define I2C_CR1_ENGC_Pos (6U)
9128#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
9129#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
9130#define I2C_CR1_NOSTRETCH_Pos (7U)
9131#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
9132#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
9133#define I2C_CR1_START_Pos (8U)
9134#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
9135#define I2C_CR1_START I2C_CR1_START_Msk
9136#define I2C_CR1_STOP_Pos (9U)
9137#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
9138#define I2C_CR1_STOP I2C_CR1_STOP_Msk
9139#define I2C_CR1_ACK_Pos (10U)
9140#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
9141#define I2C_CR1_ACK I2C_CR1_ACK_Msk
9142#define I2C_CR1_POS_Pos (11U)
9143#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
9144#define I2C_CR1_POS I2C_CR1_POS_Msk
9145#define I2C_CR1_PEC_Pos (12U)
9146#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
9147#define I2C_CR1_PEC I2C_CR1_PEC_Msk
9148#define I2C_CR1_ALERT_Pos (13U)
9149#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
9150#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
9151#define I2C_CR1_SWRST_Pos (15U)
9152#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
9153#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
9155/******************* Bit definition for I2C_CR2 register ********************/
9156#define I2C_CR2_FREQ_Pos (0U)
9157#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
9158#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
9159#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
9160#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
9161#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
9162#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
9163#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
9164#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
9166#define I2C_CR2_ITERREN_Pos (8U)
9167#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
9168#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
9169#define I2C_CR2_ITEVTEN_Pos (9U)
9170#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
9171#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
9172#define I2C_CR2_ITBUFEN_Pos (10U)
9173#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
9174#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
9175#define I2C_CR2_DMAEN_Pos (11U)
9176#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
9177#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
9178#define I2C_CR2_LAST_Pos (12U)
9179#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
9180#define I2C_CR2_LAST I2C_CR2_LAST_Msk
9182/******************* Bit definition for I2C_OAR1 register *******************/
9183#define I2C_OAR1_ADD1_7 0x000000FEU
9184#define I2C_OAR1_ADD8_9 0x00000300U
9186#define I2C_OAR1_ADD0_Pos (0U)
9187#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
9188#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
9189#define I2C_OAR1_ADD1_Pos (1U)
9190#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
9191#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
9192#define I2C_OAR1_ADD2_Pos (2U)
9193#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
9194#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
9195#define I2C_OAR1_ADD3_Pos (3U)
9196#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
9197#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
9198#define I2C_OAR1_ADD4_Pos (4U)
9199#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
9200#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
9201#define I2C_OAR1_ADD5_Pos (5U)
9202#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
9203#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
9204#define I2C_OAR1_ADD6_Pos (6U)
9205#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
9206#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
9207#define I2C_OAR1_ADD7_Pos (7U)
9208#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
9209#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
9210#define I2C_OAR1_ADD8_Pos (8U)
9211#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
9212#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
9213#define I2C_OAR1_ADD9_Pos (9U)
9214#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
9215#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
9217#define I2C_OAR1_ADDMODE_Pos (15U)
9218#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
9219#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
9221/******************* Bit definition for I2C_OAR2 register *******************/
9222#define I2C_OAR2_ENDUAL_Pos (0U)
9223#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
9224#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
9225#define I2C_OAR2_ADD2_Pos (1U)
9226#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
9227#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
9229/******************** Bit definition for I2C_DR register ********************/
9230#define I2C_DR_DR_Pos (0U)
9231#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
9232#define I2C_DR_DR I2C_DR_DR_Msk
9234/******************* Bit definition for I2C_SR1 register ********************/
9235#define I2C_SR1_SB_Pos (0U)
9236#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
9237#define I2C_SR1_SB I2C_SR1_SB_Msk
9238#define I2C_SR1_ADDR_Pos (1U)
9239#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
9240#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
9241#define I2C_SR1_BTF_Pos (2U)
9242#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
9243#define I2C_SR1_BTF I2C_SR1_BTF_Msk
9244#define I2C_SR1_ADD10_Pos (3U)
9245#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
9246#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
9247#define I2C_SR1_STOPF_Pos (4U)
9248#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
9249#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
9250#define I2C_SR1_RXNE_Pos (6U)
9251#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
9252#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
9253#define I2C_SR1_TXE_Pos (7U)
9254#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
9255#define I2C_SR1_TXE I2C_SR1_TXE_Msk
9256#define I2C_SR1_BERR_Pos (8U)
9257#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
9258#define I2C_SR1_BERR I2C_SR1_BERR_Msk
9259#define I2C_SR1_ARLO_Pos (9U)
9260#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
9261#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
9262#define I2C_SR1_AF_Pos (10U)
9263#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
9264#define I2C_SR1_AF I2C_SR1_AF_Msk
9265#define I2C_SR1_OVR_Pos (11U)
9266#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
9267#define I2C_SR1_OVR I2C_SR1_OVR_Msk
9268#define I2C_SR1_PECERR_Pos (12U)
9269#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
9270#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
9271#define I2C_SR1_TIMEOUT_Pos (14U)
9272#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
9273#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
9274#define I2C_SR1_SMBALERT_Pos (15U)
9275#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
9276#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
9278/******************* Bit definition for I2C_SR2 register ********************/
9279#define I2C_SR2_MSL_Pos (0U)
9280#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
9281#define I2C_SR2_MSL I2C_SR2_MSL_Msk
9282#define I2C_SR2_BUSY_Pos (1U)
9283#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
9284#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
9285#define I2C_SR2_TRA_Pos (2U)
9286#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
9287#define I2C_SR2_TRA I2C_SR2_TRA_Msk
9288#define I2C_SR2_GENCALL_Pos (4U)
9289#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
9290#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
9291#define I2C_SR2_SMBDEFAULT_Pos (5U)
9292#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
9293#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
9294#define I2C_SR2_SMBHOST_Pos (6U)
9295#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
9296#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
9297#define I2C_SR2_DUALF_Pos (7U)
9298#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
9299#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
9300#define I2C_SR2_PEC_Pos (8U)
9301#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
9302#define I2C_SR2_PEC I2C_SR2_PEC_Msk
9304/******************* Bit definition for I2C_CCR register ********************/
9305#define I2C_CCR_CCR_Pos (0U)
9306#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
9307#define I2C_CCR_CCR I2C_CCR_CCR_Msk
9308#define I2C_CCR_DUTY_Pos (14U)
9309#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
9310#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
9311#define I2C_CCR_FS_Pos (15U)
9312#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
9313#define I2C_CCR_FS I2C_CCR_FS_Msk
9315/****************** Bit definition for I2C_TRISE register *******************/
9316#define I2C_TRISE_TRISE_Pos (0U)
9317#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
9318#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
9321/******************************************************************************/
9322/* */
9323/* Independent WATCHDOG */
9324/* */
9325/******************************************************************************/
9326/******************* Bit definition for IWDG_KR register ********************/
9327#define IWDG_KR_KEY_Pos (0U)
9328#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
9329#define IWDG_KR_KEY IWDG_KR_KEY_Msk
9331/******************* Bit definition for IWDG_PR register ********************/
9332#define IWDG_PR_PR_Pos (0U)
9333#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
9334#define IWDG_PR_PR IWDG_PR_PR_Msk
9335#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
9336#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
9337#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
9339/******************* Bit definition for IWDG_RLR register *******************/
9340#define IWDG_RLR_RL_Pos (0U)
9341#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
9342#define IWDG_RLR_RL IWDG_RLR_RL_Msk
9344/******************* Bit definition for IWDG_SR register ********************/
9345#define IWDG_SR_PVU_Pos (0U)
9346#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
9347#define IWDG_SR_PVU IWDG_SR_PVU_Msk
9348#define IWDG_SR_RVU_Pos (1U)
9349#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
9350#define IWDG_SR_RVU IWDG_SR_RVU_Msk
9354/******************************************************************************/
9355/* */
9356/* Power Control */
9357/* */
9358/******************************************************************************/
9359/******************** Bit definition for PWR_CR register ********************/
9360#define PWR_CR_LPDS_Pos (0U)
9361#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
9362#define PWR_CR_LPDS PWR_CR_LPDS_Msk
9363#define PWR_CR_PDDS_Pos (1U)
9364#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
9365#define PWR_CR_PDDS PWR_CR_PDDS_Msk
9366#define PWR_CR_CWUF_Pos (2U)
9367#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
9368#define PWR_CR_CWUF PWR_CR_CWUF_Msk
9369#define PWR_CR_CSBF_Pos (3U)
9370#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
9371#define PWR_CR_CSBF PWR_CR_CSBF_Msk
9372#define PWR_CR_PVDE_Pos (4U)
9373#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
9374#define PWR_CR_PVDE PWR_CR_PVDE_Msk
9376#define PWR_CR_PLS_Pos (5U)
9377#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
9378#define PWR_CR_PLS PWR_CR_PLS_Msk
9379#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
9380#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
9381#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
9384#define PWR_CR_PLS_LEV0 0x00000000U
9385#define PWR_CR_PLS_LEV1 0x00000020U
9386#define PWR_CR_PLS_LEV2 0x00000040U
9387#define PWR_CR_PLS_LEV3 0x00000060U
9388#define PWR_CR_PLS_LEV4 0x00000080U
9389#define PWR_CR_PLS_LEV5 0x000000A0U
9390#define PWR_CR_PLS_LEV6 0x000000C0U
9391#define PWR_CR_PLS_LEV7 0x000000E0U
9392#define PWR_CR_DBP_Pos (8U)
9393#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
9394#define PWR_CR_DBP PWR_CR_DBP_Msk
9395#define PWR_CR_FPDS_Pos (9U)
9396#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
9397#define PWR_CR_FPDS PWR_CR_FPDS_Msk
9398#define PWR_CR_VOS_Pos (14U)
9399#define PWR_CR_VOS_Msk (0x1UL << PWR_CR_VOS_Pos)
9400#define PWR_CR_VOS PWR_CR_VOS_Msk
9402/* Legacy define */
9403#define PWR_CR_PMODE PWR_CR_VOS
9404
9405/******************* Bit definition for PWR_CSR register ********************/
9406#define PWR_CSR_WUF_Pos (0U)
9407#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
9408#define PWR_CSR_WUF PWR_CSR_WUF_Msk
9409#define PWR_CSR_SBF_Pos (1U)
9410#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
9411#define PWR_CSR_SBF PWR_CSR_SBF_Msk
9412#define PWR_CSR_PVDO_Pos (2U)
9413#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
9414#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
9415#define PWR_CSR_BRR_Pos (3U)
9416#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
9417#define PWR_CSR_BRR PWR_CSR_BRR_Msk
9418#define PWR_CSR_EWUP_Pos (8U)
9419#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
9420#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
9421#define PWR_CSR_BRE_Pos (9U)
9422#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
9423#define PWR_CSR_BRE PWR_CSR_BRE_Msk
9424#define PWR_CSR_VOSRDY_Pos (14U)
9425#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
9426#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
9428/* Legacy define */
9429#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
9430
9431/******************************************************************************/
9432/* */
9433/* Reset and Clock Control */
9434/* */
9435/******************************************************************************/
9436/******************** Bit definition for RCC_CR register ********************/
9437#define RCC_CR_HSION_Pos (0U)
9438#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
9439#define RCC_CR_HSION RCC_CR_HSION_Msk
9440#define RCC_CR_HSIRDY_Pos (1U)
9441#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
9442#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9443
9444#define RCC_CR_HSITRIM_Pos (3U)
9445#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
9446#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9447#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
9448#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
9449#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
9450#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
9451#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
9453#define RCC_CR_HSICAL_Pos (8U)
9454#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
9455#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9456#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
9457#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
9458#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
9459#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
9460#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
9461#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
9462#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
9463#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
9465#define RCC_CR_HSEON_Pos (16U)
9466#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
9467#define RCC_CR_HSEON RCC_CR_HSEON_Msk
9468#define RCC_CR_HSERDY_Pos (17U)
9469#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
9470#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9471#define RCC_CR_HSEBYP_Pos (18U)
9472#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
9473#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9474#define RCC_CR_CSSON_Pos (19U)
9475#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
9476#define RCC_CR_CSSON RCC_CR_CSSON_Msk
9477#define RCC_CR_PLLON_Pos (24U)
9478#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
9479#define RCC_CR_PLLON RCC_CR_PLLON_Msk
9480#define RCC_CR_PLLRDY_Pos (25U)
9481#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
9482#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9483/*
9484 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9485 */
9486#define RCC_PLLI2S_SUPPORT
9488#define RCC_CR_PLLI2SON_Pos (26U)
9489#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
9490#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9491#define RCC_CR_PLLI2SRDY_Pos (27U)
9492#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
9493#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9494
9495/******************** Bit definition for RCC_PLLCFGR register ***************/
9496#define RCC_PLLCFGR_PLLM_Pos (0U)
9497#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
9498#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9499#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
9500#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
9501#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
9502#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
9503#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
9504#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
9506#define RCC_PLLCFGR_PLLN_Pos (6U)
9507#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
9508#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9509#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
9510#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
9511#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
9512#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
9513#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
9514#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
9515#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
9516#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
9517#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
9519#define RCC_PLLCFGR_PLLP_Pos (16U)
9520#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
9521#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9522#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
9523#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
9525#define RCC_PLLCFGR_PLLSRC_Pos (22U)
9526#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
9527#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9528#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9529#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
9530#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9531#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9532
9533#define RCC_PLLCFGR_PLLQ_Pos (24U)
9534#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
9535#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9536#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
9537#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
9538#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
9539#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
9542/******************** Bit definition for RCC_CFGR register ******************/
9544#define RCC_CFGR_SW_Pos (0U)
9545#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
9546#define RCC_CFGR_SW RCC_CFGR_SW_Msk
9547#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
9548#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
9550#define RCC_CFGR_SW_HSI 0x00000000U
9551#define RCC_CFGR_SW_HSE 0x00000001U
9552#define RCC_CFGR_SW_PLL 0x00000002U
9555#define RCC_CFGR_SWS_Pos (2U)
9556#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
9557#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
9558#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
9559#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
9561#define RCC_CFGR_SWS_HSI 0x00000000U
9562#define RCC_CFGR_SWS_HSE 0x00000004U
9563#define RCC_CFGR_SWS_PLL 0x00000008U
9566#define RCC_CFGR_HPRE_Pos (4U)
9567#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
9568#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
9569#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
9570#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
9571#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
9572#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
9574#define RCC_CFGR_HPRE_DIV1 0x00000000U
9575#define RCC_CFGR_HPRE_DIV2 0x00000080U
9576#define RCC_CFGR_HPRE_DIV4 0x00000090U
9577#define RCC_CFGR_HPRE_DIV8 0x000000A0U
9578#define RCC_CFGR_HPRE_DIV16 0x000000B0U
9579#define RCC_CFGR_HPRE_DIV64 0x000000C0U
9580#define RCC_CFGR_HPRE_DIV128 0x000000D0U
9581#define RCC_CFGR_HPRE_DIV256 0x000000E0U
9582#define RCC_CFGR_HPRE_DIV512 0x000000F0U
9585#define RCC_CFGR_PPRE1_Pos (10U)
9586#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
9587#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
9588#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
9589#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
9590#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
9592#define RCC_CFGR_PPRE1_DIV1 0x00000000U
9593#define RCC_CFGR_PPRE1_DIV2 0x00001000U
9594#define RCC_CFGR_PPRE1_DIV4 0x00001400U
9595#define RCC_CFGR_PPRE1_DIV8 0x00001800U
9596#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
9599#define RCC_CFGR_PPRE2_Pos (13U)
9600#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
9601#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
9602#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
9603#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
9604#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
9606#define RCC_CFGR_PPRE2_DIV1 0x00000000U
9607#define RCC_CFGR_PPRE2_DIV2 0x00008000U
9608#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
9609#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
9610#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
9613#define RCC_CFGR_RTCPRE_Pos (16U)
9614#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
9615#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9616#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
9617#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
9618#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
9619#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
9620#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
9623#define RCC_CFGR_MCO1_Pos (21U)
9624#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
9625#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9626#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
9627#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
9629#define RCC_CFGR_I2SSRC_Pos (23U)
9630#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
9631#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
9632
9633#define RCC_CFGR_MCO1PRE_Pos (24U)
9634#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
9635#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9636#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
9637#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
9638#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
9640#define RCC_CFGR_MCO2PRE_Pos (27U)
9641#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
9642#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9643#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
9644#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
9645#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
9647#define RCC_CFGR_MCO2_Pos (30U)
9648#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
9649#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9650#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
9651#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
9653/******************** Bit definition for RCC_CIR register *******************/
9654#define RCC_CIR_LSIRDYF_Pos (0U)
9655#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
9656#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9657#define RCC_CIR_LSERDYF_Pos (1U)
9658#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
9659#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9660#define RCC_CIR_HSIRDYF_Pos (2U)
9661#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
9662#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9663#define RCC_CIR_HSERDYF_Pos (3U)
9664#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
9665#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9666#define RCC_CIR_PLLRDYF_Pos (4U)
9667#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
9668#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9669#define RCC_CIR_PLLI2SRDYF_Pos (5U)
9670#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
9671#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9672
9673#define RCC_CIR_CSSF_Pos (7U)
9674#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
9675#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9676#define RCC_CIR_LSIRDYIE_Pos (8U)
9677#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
9678#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9679#define RCC_CIR_LSERDYIE_Pos (9U)
9680#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
9681#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9682#define RCC_CIR_HSIRDYIE_Pos (10U)
9683#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
9684#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9685#define RCC_CIR_HSERDYIE_Pos (11U)
9686#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
9687#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9688#define RCC_CIR_PLLRDYIE_Pos (12U)
9689#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
9690#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9691#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9692#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
9693#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9694
9695#define RCC_CIR_LSIRDYC_Pos (16U)
9696#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
9697#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9698#define RCC_CIR_LSERDYC_Pos (17U)
9699#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
9700#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9701#define RCC_CIR_HSIRDYC_Pos (18U)
9702#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
9703#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9704#define RCC_CIR_HSERDYC_Pos (19U)
9705#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
9706#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9707#define RCC_CIR_PLLRDYC_Pos (20U)
9708#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
9709#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9710#define RCC_CIR_PLLI2SRDYC_Pos (21U)
9711#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
9712#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9713
9714#define RCC_CIR_CSSC_Pos (23U)
9715#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
9716#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9717
9718/******************** Bit definition for RCC_AHB1RSTR register **************/
9719#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9720#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
9721#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9722#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9723#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
9724#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9725#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9726#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
9727#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9728#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9729#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
9730#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9731#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9732#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
9733#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9734#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
9735#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
9736#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
9737#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
9738#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
9739#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
9740#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9741#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
9742#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9743#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
9744#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
9745#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
9746#define RCC_AHB1RSTR_CRCRST_Pos (12U)
9747#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
9748#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9749#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9750#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
9751#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9752#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9753#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
9754#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9755#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
9756#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
9757#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
9758#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
9759#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
9760#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
9761
9762/******************** Bit definition for RCC_AHB2RSTR register **************/
9763#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
9764#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
9765#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
9766#define RCC_AHB2RSTR_RNGRST_Pos (6U)
9767#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
9768#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9769#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9770#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
9771#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9772/******************** Bit definition for RCC_AHB3RSTR register **************/
9773#define RCC_AHB3RSTR_FSMCRST_Pos (0U)
9774#define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
9775#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
9776
9777
9778/******************** Bit definition for RCC_APB1RSTR register **************/
9779#define RCC_APB1RSTR_TIM2RST_Pos (0U)
9780#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
9781#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9782#define RCC_APB1RSTR_TIM3RST_Pos (1U)
9783#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
9784#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9785#define RCC_APB1RSTR_TIM4RST_Pos (2U)
9786#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
9787#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9788#define RCC_APB1RSTR_TIM5RST_Pos (3U)
9789#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
9790#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9791#define RCC_APB1RSTR_TIM6RST_Pos (4U)
9792#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
9793#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9794#define RCC_APB1RSTR_TIM7RST_Pos (5U)
9795#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
9796#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9797#define RCC_APB1RSTR_TIM12RST_Pos (6U)
9798#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
9799#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9800#define RCC_APB1RSTR_TIM13RST_Pos (7U)
9801#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
9802#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9803#define RCC_APB1RSTR_TIM14RST_Pos (8U)
9804#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
9805#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9806#define RCC_APB1RSTR_WWDGRST_Pos (11U)
9807#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
9808#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9809#define RCC_APB1RSTR_SPI2RST_Pos (14U)
9810#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
9811#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9812#define RCC_APB1RSTR_SPI3RST_Pos (15U)
9813#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
9814#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9815#define RCC_APB1RSTR_USART2RST_Pos (17U)
9816#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
9817#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9818#define RCC_APB1RSTR_USART3RST_Pos (18U)
9819#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
9820#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9821#define RCC_APB1RSTR_UART4RST_Pos (19U)
9822#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
9823#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
9824#define RCC_APB1RSTR_UART5RST_Pos (20U)
9825#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
9826#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
9827#define RCC_APB1RSTR_I2C1RST_Pos (21U)
9828#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
9829#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9830#define RCC_APB1RSTR_I2C2RST_Pos (22U)
9831#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
9832#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9833#define RCC_APB1RSTR_I2C3RST_Pos (23U)
9834#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
9835#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9836#define RCC_APB1RSTR_CAN1RST_Pos (25U)
9837#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
9838#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9839#define RCC_APB1RSTR_CAN2RST_Pos (26U)
9840#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
9841#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
9842#define RCC_APB1RSTR_PWRRST_Pos (28U)
9843#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
9844#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9845#define RCC_APB1RSTR_DACRST_Pos (29U)
9846#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
9847#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
9848
9849/******************** Bit definition for RCC_APB2RSTR register **************/
9850#define RCC_APB2RSTR_TIM1RST_Pos (0U)
9851#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
9852#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9853#define RCC_APB2RSTR_TIM8RST_Pos (1U)
9854#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
9855#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9856#define RCC_APB2RSTR_USART1RST_Pos (4U)
9857#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
9858#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9859#define RCC_APB2RSTR_USART6RST_Pos (5U)
9860#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
9861#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9862#define RCC_APB2RSTR_ADCRST_Pos (8U)
9863#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
9864#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9865#define RCC_APB2RSTR_SDIORST_Pos (11U)
9866#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
9867#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
9868#define RCC_APB2RSTR_SPI1RST_Pos (12U)
9869#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
9870#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9871#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9872#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
9873#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9874#define RCC_APB2RSTR_TIM9RST_Pos (16U)
9875#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
9876#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9877#define RCC_APB2RSTR_TIM10RST_Pos (17U)
9878#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
9879#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9880#define RCC_APB2RSTR_TIM11RST_Pos (18U)
9881#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
9882#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9883
9884/* Old SPI1RST bit definition, maintained for legacy purpose */
9885#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
9886
9887/******************** Bit definition for RCC_AHB1ENR register ***************/
9888#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9889#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
9890#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9891#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9892#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
9893#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9894#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9895#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
9896#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9897#define RCC_AHB1ENR_GPIODEN_Pos (3U)
9898#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
9899#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9900#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9901#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
9902#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9903#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
9904#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
9905#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
9906#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
9907#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
9908#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
9909#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
9910#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
9911#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
9912#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
9913#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
9914#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
9915#define RCC_AHB1ENR_CRCEN_Pos (12U)
9916#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
9917#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9918#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
9919#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
9920#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
9921#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
9922#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
9923#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
9924#define RCC_AHB1ENR_DMA1EN_Pos (21U)
9925#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
9926#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9927#define RCC_AHB1ENR_DMA2EN_Pos (22U)
9928#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
9929#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9930#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
9931#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
9932#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
9933#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
9934#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
9935#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
9936#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
9937#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
9938#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
9939#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
9940#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
9941#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
9942#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
9943#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
9944#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
9945#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
9946#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
9947#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
9948/******************** Bit definition for RCC_AHB2ENR register ***************/
9949/*
9950 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9951 */
9952#define RCC_AHB2_SUPPORT
9954#define RCC_AHB2ENR_DCMIEN_Pos (0U)
9955#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
9956#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
9957#define RCC_AHB2ENR_RNGEN_Pos (6U)
9958#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
9959#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9960#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
9961#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
9962#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
9963
9964/******************** Bit definition for RCC_AHB3ENR register ***************/
9965/*
9966 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9967 */
9968#define RCC_AHB3_SUPPORT
9970#define RCC_AHB3ENR_FSMCEN_Pos (0U)
9971#define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
9972#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
9973
9974/******************** Bit definition for RCC_APB1ENR register ***************/
9975#define RCC_APB1ENR_TIM2EN_Pos (0U)
9976#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
9977#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
9978#define RCC_APB1ENR_TIM3EN_Pos (1U)
9979#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
9980#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
9981#define RCC_APB1ENR_TIM4EN_Pos (2U)
9982#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
9983#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
9984#define RCC_APB1ENR_TIM5EN_Pos (3U)
9985#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
9986#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
9987#define RCC_APB1ENR_TIM6EN_Pos (4U)
9988#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
9989#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
9990#define RCC_APB1ENR_TIM7EN_Pos (5U)
9991#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
9992#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
9993#define RCC_APB1ENR_TIM12EN_Pos (6U)
9994#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
9995#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
9996#define RCC_APB1ENR_TIM13EN_Pos (7U)
9997#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
9998#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
9999#define RCC_APB1ENR_TIM14EN_Pos (8U)
10000#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
10001#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
10002#define RCC_APB1ENR_WWDGEN_Pos (11U)
10003#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
10004#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
10005#define RCC_APB1ENR_SPI2EN_Pos (14U)
10006#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
10007#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
10008#define RCC_APB1ENR_SPI3EN_Pos (15U)
10009#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
10010#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
10011#define RCC_APB1ENR_USART2EN_Pos (17U)
10012#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
10013#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
10014#define RCC_APB1ENR_USART3EN_Pos (18U)
10015#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
10016#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
10017#define RCC_APB1ENR_UART4EN_Pos (19U)
10018#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
10019#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
10020#define RCC_APB1ENR_UART5EN_Pos (20U)
10021#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
10022#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
10023#define RCC_APB1ENR_I2C1EN_Pos (21U)
10024#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
10025#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
10026#define RCC_APB1ENR_I2C2EN_Pos (22U)
10027#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
10028#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
10029#define RCC_APB1ENR_I2C3EN_Pos (23U)
10030#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
10031#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
10032#define RCC_APB1ENR_CAN1EN_Pos (25U)
10033#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
10034#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
10035#define RCC_APB1ENR_CAN2EN_Pos (26U)
10036#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
10037#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
10038#define RCC_APB1ENR_PWREN_Pos (28U)
10039#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
10040#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
10041#define RCC_APB1ENR_DACEN_Pos (29U)
10042#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
10043#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
10044
10045/******************** Bit definition for RCC_APB2ENR register ***************/
10046#define RCC_APB2ENR_TIM1EN_Pos (0U)
10047#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
10048#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
10049#define RCC_APB2ENR_TIM8EN_Pos (1U)
10050#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
10051#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
10052#define RCC_APB2ENR_USART1EN_Pos (4U)
10053#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
10054#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
10055#define RCC_APB2ENR_USART6EN_Pos (5U)
10056#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
10057#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
10058#define RCC_APB2ENR_ADC1EN_Pos (8U)
10059#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
10060#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
10061#define RCC_APB2ENR_ADC2EN_Pos (9U)
10062#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
10063#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
10064#define RCC_APB2ENR_ADC3EN_Pos (10U)
10065#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
10066#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
10067#define RCC_APB2ENR_SDIOEN_Pos (11U)
10068#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
10069#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
10070#define RCC_APB2ENR_SPI1EN_Pos (12U)
10071#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
10072#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
10073#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
10074#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
10075#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
10076#define RCC_APB2ENR_TIM9EN_Pos (16U)
10077#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
10078#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
10079#define RCC_APB2ENR_TIM10EN_Pos (17U)
10080#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
10081#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
10082#define RCC_APB2ENR_TIM11EN_Pos (18U)
10083#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
10084#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
10085
10086/******************** Bit definition for RCC_AHB1LPENR register *************/
10087#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
10088#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
10089#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
10090#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
10091#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
10092#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
10093#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
10094#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
10095#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
10096#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
10097#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
10098#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
10099#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
10100#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
10101#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
10102#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
10103#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
10104#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
10105#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
10106#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
10107#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
10108#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
10109#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
10110#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
10111#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
10112#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
10113#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
10114#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
10115#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
10116#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
10117#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
10118#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
10119#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
10120#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
10121#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
10122#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
10123#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
10124#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
10125#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
10126#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
10127#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
10128#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
10129#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
10130#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
10131#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
10132#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
10133#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
10134#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
10135
10136#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
10137#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
10138#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
10139#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
10140#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
10141#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
10142#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
10143#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
10144#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
10145#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
10146#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
10147#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
10148#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
10149#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
10150#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
10151#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
10152#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
10153#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
10154
10155/******************** Bit definition for RCC_AHB2LPENR register *************/
10156#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
10157#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
10158#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
10159#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
10160#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
10161#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
10162#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
10163#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
10164#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
10165
10166/******************** Bit definition for RCC_AHB3LPENR register *************/
10167#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
10168#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
10169#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
10170
10171/******************** Bit definition for RCC_APB1LPENR register *************/
10172#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
10173#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
10174#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
10175#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
10176#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
10177#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
10178#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
10179#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
10180#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
10181#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
10182#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
10183#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
10184#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
10185#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
10186#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
10187#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
10188#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
10189#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
10190#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
10191#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
10192#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
10193#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
10194#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
10195#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
10196#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
10197#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
10198#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
10199#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
10200#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
10201#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
10202#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
10203#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
10204#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
10205#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
10206#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
10207#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
10208#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
10209#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
10210#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
10211#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
10212#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
10213#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
10214#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
10215#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
10216#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
10217#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
10218#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
10219#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
10220#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
10221#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
10222#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
10223#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
10224#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
10225#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
10226#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
10227#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
10228#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
10229#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
10230#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
10231#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
10232#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
10233#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
10234#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
10235#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
10236#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
10237#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
10238#define RCC_APB1LPENR_DACLPEN_Pos (29U)
10239#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
10240#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
10241
10242/******************** Bit definition for RCC_APB2LPENR register *************/
10243#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
10244#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
10245#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
10246#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
10247#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
10248#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
10249#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
10250#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
10251#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
10252#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
10253#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
10254#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
10255#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
10256#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
10257#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
10258#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
10259#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
10260#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
10261#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
10262#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
10263#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
10264#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
10265#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
10266#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
10267#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
10268#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
10269#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
10270#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
10271#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
10272#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
10273#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
10274#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
10275#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
10276#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
10277#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
10278#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
10279#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
10280#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
10281#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
10282
10283/******************** Bit definition for RCC_BDCR register ******************/
10284#define RCC_BDCR_LSEON_Pos (0U)
10285#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
10286#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10287#define RCC_BDCR_LSERDY_Pos (1U)
10288#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
10289#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10290#define RCC_BDCR_LSEBYP_Pos (2U)
10291#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
10292#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10293
10294#define RCC_BDCR_RTCSEL_Pos (8U)
10295#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
10296#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10297#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
10298#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
10300#define RCC_BDCR_RTCEN_Pos (15U)
10301#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
10302#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10303#define RCC_BDCR_BDRST_Pos (16U)
10304#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
10305#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10306
10307/******************** Bit definition for RCC_CSR register *******************/
10308#define RCC_CSR_LSION_Pos (0U)
10309#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
10310#define RCC_CSR_LSION RCC_CSR_LSION_Msk
10311#define RCC_CSR_LSIRDY_Pos (1U)
10312#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
10313#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10314#define RCC_CSR_RMVF_Pos (24U)
10315#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
10316#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10317#define RCC_CSR_BORRSTF_Pos (25U)
10318#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
10319#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10320#define RCC_CSR_PINRSTF_Pos (26U)
10321#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
10322#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10323#define RCC_CSR_PORRSTF_Pos (27U)
10324#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
10325#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10326#define RCC_CSR_SFTRSTF_Pos (28U)
10327#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
10328#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10329#define RCC_CSR_IWDGRSTF_Pos (29U)
10330#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
10331#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10332#define RCC_CSR_WWDGRSTF_Pos (30U)
10333#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
10334#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10335#define RCC_CSR_LPWRRSTF_Pos (31U)
10336#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
10337#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10338/* Legacy defines */
10339#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10340#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10341
10342/******************** Bit definition for RCC_SSCGR register *****************/
10343#define RCC_SSCGR_MODPER_Pos (0U)
10344#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
10345#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10346#define RCC_SSCGR_INCSTEP_Pos (13U)
10347#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
10348#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10349#define RCC_SSCGR_SPREADSEL_Pos (30U)
10350#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
10351#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10352#define RCC_SSCGR_SSCGEN_Pos (31U)
10353#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
10354#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10355
10356/******************** Bit definition for RCC_PLLI2SCFGR register ************/
10357#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10358#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10359#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10360#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10361#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10362#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10363#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10364#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10365#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10366#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10367#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10368#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10370#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10371#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10372#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10373#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10374#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10375#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10378/******************************************************************************/
10379/* */
10380/* RNG */
10381/* */
10382/******************************************************************************/
10383/******************** Bits definition for RNG_CR register *******************/
10384#define RNG_CR_RNGEN_Pos (2U)
10385#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
10386#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10387#define RNG_CR_IE_Pos (3U)
10388#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
10389#define RNG_CR_IE RNG_CR_IE_Msk
10390
10391/******************** Bits definition for RNG_SR register *******************/
10392#define RNG_SR_DRDY_Pos (0U)
10393#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
10394#define RNG_SR_DRDY RNG_SR_DRDY_Msk
10395#define RNG_SR_CECS_Pos (1U)
10396#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
10397#define RNG_SR_CECS RNG_SR_CECS_Msk
10398#define RNG_SR_SECS_Pos (2U)
10399#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
10400#define RNG_SR_SECS RNG_SR_SECS_Msk
10401#define RNG_SR_CEIS_Pos (5U)
10402#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
10403#define RNG_SR_CEIS RNG_SR_CEIS_Msk
10404#define RNG_SR_SEIS_Pos (6U)
10405#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
10406#define RNG_SR_SEIS RNG_SR_SEIS_Msk
10407
10408/******************************************************************************/
10409/* */
10410/* Real-Time Clock (RTC) */
10411/* */
10412/******************************************************************************/
10413/*
10414 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10415 */
10416#define RTC_TAMPER2_SUPPORT
10417#define RTC_AF2_SUPPORT
10418/******************** Bits definition for RTC_TR register *******************/
10419#define RTC_TR_PM_Pos (22U)
10420#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
10421#define RTC_TR_PM RTC_TR_PM_Msk
10422#define RTC_TR_HT_Pos (20U)
10423#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
10424#define RTC_TR_HT RTC_TR_HT_Msk
10425#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
10426#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
10427#define RTC_TR_HU_Pos (16U)
10428#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
10429#define RTC_TR_HU RTC_TR_HU_Msk
10430#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
10431#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
10432#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
10433#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
10434#define RTC_TR_MNT_Pos (12U)
10435#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
10436#define RTC_TR_MNT RTC_TR_MNT_Msk
10437#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
10438#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
10439#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
10440#define RTC_TR_MNU_Pos (8U)
10441#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
10442#define RTC_TR_MNU RTC_TR_MNU_Msk
10443#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
10444#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
10445#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
10446#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
10447#define RTC_TR_ST_Pos (4U)
10448#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
10449#define RTC_TR_ST RTC_TR_ST_Msk
10450#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
10451#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
10452#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
10453#define RTC_TR_SU_Pos (0U)
10454#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
10455#define RTC_TR_SU RTC_TR_SU_Msk
10456#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
10457#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
10458#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
10459#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
10461/******************** Bits definition for RTC_DR register *******************/
10462#define RTC_DR_YT_Pos (20U)
10463#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
10464#define RTC_DR_YT RTC_DR_YT_Msk
10465#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
10466#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
10467#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
10468#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
10469#define RTC_DR_YU_Pos (16U)
10470#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
10471#define RTC_DR_YU RTC_DR_YU_Msk
10472#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
10473#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
10474#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
10475#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
10476#define RTC_DR_WDU_Pos (13U)
10477#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
10478#define RTC_DR_WDU RTC_DR_WDU_Msk
10479#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
10480#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
10481#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
10482#define RTC_DR_MT_Pos (12U)
10483#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
10484#define RTC_DR_MT RTC_DR_MT_Msk
10485#define RTC_DR_MU_Pos (8U)
10486#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
10487#define RTC_DR_MU RTC_DR_MU_Msk
10488#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
10489#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
10490#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
10491#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
10492#define RTC_DR_DT_Pos (4U)
10493#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
10494#define RTC_DR_DT RTC_DR_DT_Msk
10495#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
10496#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
10497#define RTC_DR_DU_Pos (0U)
10498#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
10499#define RTC_DR_DU RTC_DR_DU_Msk
10500#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
10501#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
10502#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
10503#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
10505/******************** Bits definition for RTC_CR register *******************/
10506#define RTC_CR_COE_Pos (23U)
10507#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
10508#define RTC_CR_COE RTC_CR_COE_Msk
10509#define RTC_CR_OSEL_Pos (21U)
10510#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
10511#define RTC_CR_OSEL RTC_CR_OSEL_Msk
10512#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
10513#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
10514#define RTC_CR_POL_Pos (20U)
10515#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
10516#define RTC_CR_POL RTC_CR_POL_Msk
10517#define RTC_CR_COSEL_Pos (19U)
10518#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
10519#define RTC_CR_COSEL RTC_CR_COSEL_Msk
10520#define RTC_CR_BKP_Pos (18U)
10521#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
10522#define RTC_CR_BKP RTC_CR_BKP_Msk
10523#define RTC_CR_SUB1H_Pos (17U)
10524#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
10525#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10526#define RTC_CR_ADD1H_Pos (16U)
10527#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
10528#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10529#define RTC_CR_TSIE_Pos (15U)
10530#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
10531#define RTC_CR_TSIE RTC_CR_TSIE_Msk
10532#define RTC_CR_WUTIE_Pos (14U)
10533#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
10534#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10535#define RTC_CR_ALRBIE_Pos (13U)
10536#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
10537#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10538#define RTC_CR_ALRAIE_Pos (12U)
10539#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
10540#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10541#define RTC_CR_TSE_Pos (11U)
10542#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
10543#define RTC_CR_TSE RTC_CR_TSE_Msk
10544#define RTC_CR_WUTE_Pos (10U)
10545#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
10546#define RTC_CR_WUTE RTC_CR_WUTE_Msk
10547#define RTC_CR_ALRBE_Pos (9U)
10548#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
10549#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10550#define RTC_CR_ALRAE_Pos (8U)
10551#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
10552#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10553#define RTC_CR_DCE_Pos (7U)
10554#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
10555#define RTC_CR_DCE RTC_CR_DCE_Msk
10556#define RTC_CR_FMT_Pos (6U)
10557#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
10558#define RTC_CR_FMT RTC_CR_FMT_Msk
10559#define RTC_CR_BYPSHAD_Pos (5U)
10560#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
10561#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10562#define RTC_CR_REFCKON_Pos (4U)
10563#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
10564#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10565#define RTC_CR_TSEDGE_Pos (3U)
10566#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
10567#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10568#define RTC_CR_WUCKSEL_Pos (0U)
10569#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
10570#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10571#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
10572#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
10573#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
10575/* Legacy defines */
10576#define RTC_CR_BCK RTC_CR_BKP
10577
10578/******************** Bits definition for RTC_ISR register ******************/
10579#define RTC_ISR_RECALPF_Pos (16U)
10580#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
10581#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10582#define RTC_ISR_TAMP1F_Pos (13U)
10583#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
10584#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10585#define RTC_ISR_TAMP2F_Pos (14U)
10586#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
10587#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10588#define RTC_ISR_TSOVF_Pos (12U)
10589#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
10590#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10591#define RTC_ISR_TSF_Pos (11U)
10592#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
10593#define RTC_ISR_TSF RTC_ISR_TSF_Msk
10594#define RTC_ISR_WUTF_Pos (10U)
10595#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
10596#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10597#define RTC_ISR_ALRBF_Pos (9U)
10598#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
10599#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10600#define RTC_ISR_ALRAF_Pos (8U)
10601#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
10602#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10603#define RTC_ISR_INIT_Pos (7U)
10604#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
10605#define RTC_ISR_INIT RTC_ISR_INIT_Msk
10606#define RTC_ISR_INITF_Pos (6U)
10607#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
10608#define RTC_ISR_INITF RTC_ISR_INITF_Msk
10609#define RTC_ISR_RSF_Pos (5U)
10610#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
10611#define RTC_ISR_RSF RTC_ISR_RSF_Msk
10612#define RTC_ISR_INITS_Pos (4U)
10613#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
10614#define RTC_ISR_INITS RTC_ISR_INITS_Msk
10615#define RTC_ISR_SHPF_Pos (3U)
10616#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
10617#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10618#define RTC_ISR_WUTWF_Pos (2U)
10619#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
10620#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10621#define RTC_ISR_ALRBWF_Pos (1U)
10622#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
10623#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10624#define RTC_ISR_ALRAWF_Pos (0U)
10625#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
10626#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10627
10628/******************** Bits definition for RTC_PRER register *****************/
10629#define RTC_PRER_PREDIV_A_Pos (16U)
10630#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
10631#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10632#define RTC_PRER_PREDIV_S_Pos (0U)
10633#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
10634#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10635
10636/******************** Bits definition for RTC_WUTR register *****************/
10637#define RTC_WUTR_WUT_Pos (0U)
10638#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
10639#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10640
10641/******************** Bits definition for RTC_CALIBR register ***************/
10642#define RTC_CALIBR_DCS_Pos (7U)
10643#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
10644#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
10645#define RTC_CALIBR_DC_Pos (0U)
10646#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
10647#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
10648
10649/******************** Bits definition for RTC_ALRMAR register ***************/
10650#define RTC_ALRMAR_MSK4_Pos (31U)
10651#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
10652#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10653#define RTC_ALRMAR_WDSEL_Pos (30U)
10654#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
10655#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10656#define RTC_ALRMAR_DT_Pos (28U)
10657#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
10658#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10659#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
10660#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
10661#define RTC_ALRMAR_DU_Pos (24U)
10662#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
10663#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10664#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
10665#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
10666#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
10667#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
10668#define RTC_ALRMAR_MSK3_Pos (23U)
10669#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
10670#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10671#define RTC_ALRMAR_PM_Pos (22U)
10672#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
10673#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10674#define RTC_ALRMAR_HT_Pos (20U)
10675#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
10676#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10677#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
10678#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
10679#define RTC_ALRMAR_HU_Pos (16U)
10680#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
10681#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10682#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
10683#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
10684#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
10685#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
10686#define RTC_ALRMAR_MSK2_Pos (15U)
10687#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
10688#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10689#define RTC_ALRMAR_MNT_Pos (12U)
10690#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
10691#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10692#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
10693#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
10694#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
10695#define RTC_ALRMAR_MNU_Pos (8U)
10696#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
10697#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10698#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
10699#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
10700#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
10701#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
10702#define RTC_ALRMAR_MSK1_Pos (7U)
10703#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
10704#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10705#define RTC_ALRMAR_ST_Pos (4U)
10706#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
10707#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10708#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
10709#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
10710#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
10711#define RTC_ALRMAR_SU_Pos (0U)
10712#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
10713#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10714#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
10715#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
10716#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
10717#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
10719/******************** Bits definition for RTC_ALRMBR register ***************/
10720#define RTC_ALRMBR_MSK4_Pos (31U)
10721#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
10722#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10723#define RTC_ALRMBR_WDSEL_Pos (30U)
10724#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
10725#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10726#define RTC_ALRMBR_DT_Pos (28U)
10727#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
10728#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10729#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
10730#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
10731#define RTC_ALRMBR_DU_Pos (24U)
10732#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
10733#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10734#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
10735#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
10736#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
10737#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
10738#define RTC_ALRMBR_MSK3_Pos (23U)
10739#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
10740#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10741#define RTC_ALRMBR_PM_Pos (22U)
10742#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
10743#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10744#define RTC_ALRMBR_HT_Pos (20U)
10745#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
10746#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10747#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
10748#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
10749#define RTC_ALRMBR_HU_Pos (16U)
10750#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
10751#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10752#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
10753#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
10754#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
10755#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
10756#define RTC_ALRMBR_MSK2_Pos (15U)
10757#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
10758#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10759#define RTC_ALRMBR_MNT_Pos (12U)
10760#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
10761#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10762#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
10763#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
10764#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
10765#define RTC_ALRMBR_MNU_Pos (8U)
10766#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
10767#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10768#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
10769#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
10770#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
10771#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
10772#define RTC_ALRMBR_MSK1_Pos (7U)
10773#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
10774#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10775#define RTC_ALRMBR_ST_Pos (4U)
10776#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
10777#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10778#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
10779#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
10780#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
10781#define RTC_ALRMBR_SU_Pos (0U)
10782#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
10783#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10784#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
10785#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
10786#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
10787#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
10789/******************** Bits definition for RTC_WPR register ******************/
10790#define RTC_WPR_KEY_Pos (0U)
10791#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
10792#define RTC_WPR_KEY RTC_WPR_KEY_Msk
10793
10794/******************** Bits definition for RTC_SSR register ******************/
10795#define RTC_SSR_SS_Pos (0U)
10796#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
10797#define RTC_SSR_SS RTC_SSR_SS_Msk
10798
10799/******************** Bits definition for RTC_SHIFTR register ***************/
10800#define RTC_SHIFTR_SUBFS_Pos (0U)
10801#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
10802#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
10803#define RTC_SHIFTR_ADD1S_Pos (31U)
10804#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
10805#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
10806
10807/******************** Bits definition for RTC_TSTR register *****************/
10808#define RTC_TSTR_PM_Pos (22U)
10809#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
10810#define RTC_TSTR_PM RTC_TSTR_PM_Msk
10811#define RTC_TSTR_HT_Pos (20U)
10812#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
10813#define RTC_TSTR_HT RTC_TSTR_HT_Msk
10814#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
10815#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
10816#define RTC_TSTR_HU_Pos (16U)
10817#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
10818#define RTC_TSTR_HU RTC_TSTR_HU_Msk
10819#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
10820#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
10821#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
10822#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
10823#define RTC_TSTR_MNT_Pos (12U)
10824#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
10825#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10826#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
10827#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
10828#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
10829#define RTC_TSTR_MNU_Pos (8U)
10830#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
10831#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10832#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
10833#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
10834#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
10835#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
10836#define RTC_TSTR_ST_Pos (4U)
10837#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
10838#define RTC_TSTR_ST RTC_TSTR_ST_Msk
10839#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
10840#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
10841#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
10842#define RTC_TSTR_SU_Pos (0U)
10843#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
10844#define RTC_TSTR_SU RTC_TSTR_SU_Msk
10845#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
10846#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
10847#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
10848#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
10850/******************** Bits definition for RTC_TSDR register *****************/
10851#define RTC_TSDR_WDU_Pos (13U)
10852#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
10853#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10854#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
10855#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
10856#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
10857#define RTC_TSDR_MT_Pos (12U)
10858#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
10859#define RTC_TSDR_MT RTC_TSDR_MT_Msk
10860#define RTC_TSDR_MU_Pos (8U)
10861#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
10862#define RTC_TSDR_MU RTC_TSDR_MU_Msk
10863#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
10864#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
10865#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
10866#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
10867#define RTC_TSDR_DT_Pos (4U)
10868#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
10869#define RTC_TSDR_DT RTC_TSDR_DT_Msk
10870#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
10871#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
10872#define RTC_TSDR_DU_Pos (0U)
10873#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
10874#define RTC_TSDR_DU RTC_TSDR_DU_Msk
10875#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
10876#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
10877#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
10878#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
10880/******************** Bits definition for RTC_TSSSR register ****************/
10881#define RTC_TSSSR_SS_Pos (0U)
10882#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
10883#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
10884
10885/******************** Bits definition for RTC_CAL register *****************/
10886#define RTC_CALR_CALP_Pos (15U)
10887#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
10888#define RTC_CALR_CALP RTC_CALR_CALP_Msk
10889#define RTC_CALR_CALW8_Pos (14U)
10890#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
10891#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
10892#define RTC_CALR_CALW16_Pos (13U)
10893#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
10894#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
10895#define RTC_CALR_CALM_Pos (0U)
10896#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
10897#define RTC_CALR_CALM RTC_CALR_CALM_Msk
10898#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
10899#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
10900#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
10901#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
10902#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
10903#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
10904#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
10905#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
10906#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
10908/******************** Bits definition for RTC_TAFCR register ****************/
10909#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
10910#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
10911#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
10912#define RTC_TAFCR_TSINSEL_Pos (17U)
10913#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
10914#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
10915#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
10916#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
10917#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
10918#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
10919#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
10920#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
10921#define RTC_TAFCR_TAMPPRCH_Pos (13U)
10922#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
10923#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
10924#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
10925#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
10926#define RTC_TAFCR_TAMPFLT_Pos (11U)
10927#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
10928#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
10929#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
10930#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
10931#define RTC_TAFCR_TAMPFREQ_Pos (8U)
10932#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
10933#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
10934#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
10935#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
10936#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
10937#define RTC_TAFCR_TAMPTS_Pos (7U)
10938#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
10939#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
10940#define RTC_TAFCR_TAMP2TRG_Pos (4U)
10941#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
10942#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
10943#define RTC_TAFCR_TAMP2E_Pos (3U)
10944#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
10945#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
10946#define RTC_TAFCR_TAMPIE_Pos (2U)
10947#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
10948#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
10949#define RTC_TAFCR_TAMP1TRG_Pos (1U)
10950#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
10951#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
10952#define RTC_TAFCR_TAMP1E_Pos (0U)
10953#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
10954#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
10955
10956/* Legacy defines */
10957#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
10958
10959/******************** Bits definition for RTC_ALRMASSR register *************/
10960#define RTC_ALRMASSR_MASKSS_Pos (24U)
10961#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
10962#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
10963#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
10964#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
10965#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
10966#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
10967#define RTC_ALRMASSR_SS_Pos (0U)
10968#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
10969#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
10970
10971/******************** Bits definition for RTC_ALRMBSSR register *************/
10972#define RTC_ALRMBSSR_MASKSS_Pos (24U)
10973#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
10974#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
10975#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
10976#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
10977#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
10978#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
10979#define RTC_ALRMBSSR_SS_Pos (0U)
10980#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
10981#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
10982
10983/******************** Bits definition for RTC_BKP0R register ****************/
10984#define RTC_BKP0R_Pos (0U)
10985#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
10986#define RTC_BKP0R RTC_BKP0R_Msk
10987
10988/******************** Bits definition for RTC_BKP1R register ****************/
10989#define RTC_BKP1R_Pos (0U)
10990#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
10991#define RTC_BKP1R RTC_BKP1R_Msk
10992
10993/******************** Bits definition for RTC_BKP2R register ****************/
10994#define RTC_BKP2R_Pos (0U)
10995#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
10996#define RTC_BKP2R RTC_BKP2R_Msk
10997
10998/******************** Bits definition for RTC_BKP3R register ****************/
10999#define RTC_BKP3R_Pos (0U)
11000#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
11001#define RTC_BKP3R RTC_BKP3R_Msk
11002
11003/******************** Bits definition for RTC_BKP4R register ****************/
11004#define RTC_BKP4R_Pos (0U)
11005#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
11006#define RTC_BKP4R RTC_BKP4R_Msk
11007
11008/******************** Bits definition for RTC_BKP5R register ****************/
11009#define RTC_BKP5R_Pos (0U)
11010#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
11011#define RTC_BKP5R RTC_BKP5R_Msk
11012
11013/******************** Bits definition for RTC_BKP6R register ****************/
11014#define RTC_BKP6R_Pos (0U)
11015#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
11016#define RTC_BKP6R RTC_BKP6R_Msk
11017
11018/******************** Bits definition for RTC_BKP7R register ****************/
11019#define RTC_BKP7R_Pos (0U)
11020#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
11021#define RTC_BKP7R RTC_BKP7R_Msk
11022
11023/******************** Bits definition for RTC_BKP8R register ****************/
11024#define RTC_BKP8R_Pos (0U)
11025#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
11026#define RTC_BKP8R RTC_BKP8R_Msk
11027
11028/******************** Bits definition for RTC_BKP9R register ****************/
11029#define RTC_BKP9R_Pos (0U)
11030#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
11031#define RTC_BKP9R RTC_BKP9R_Msk
11032
11033/******************** Bits definition for RTC_BKP10R register ***************/
11034#define RTC_BKP10R_Pos (0U)
11035#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
11036#define RTC_BKP10R RTC_BKP10R_Msk
11037
11038/******************** Bits definition for RTC_BKP11R register ***************/
11039#define RTC_BKP11R_Pos (0U)
11040#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
11041#define RTC_BKP11R RTC_BKP11R_Msk
11042
11043/******************** Bits definition for RTC_BKP12R register ***************/
11044#define RTC_BKP12R_Pos (0U)
11045#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
11046#define RTC_BKP12R RTC_BKP12R_Msk
11047
11048/******************** Bits definition for RTC_BKP13R register ***************/
11049#define RTC_BKP13R_Pos (0U)
11050#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
11051#define RTC_BKP13R RTC_BKP13R_Msk
11052
11053/******************** Bits definition for RTC_BKP14R register ***************/
11054#define RTC_BKP14R_Pos (0U)
11055#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
11056#define RTC_BKP14R RTC_BKP14R_Msk
11057
11058/******************** Bits definition for RTC_BKP15R register ***************/
11059#define RTC_BKP15R_Pos (0U)
11060#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
11061#define RTC_BKP15R RTC_BKP15R_Msk
11062
11063/******************** Bits definition for RTC_BKP16R register ***************/
11064#define RTC_BKP16R_Pos (0U)
11065#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
11066#define RTC_BKP16R RTC_BKP16R_Msk
11067
11068/******************** Bits definition for RTC_BKP17R register ***************/
11069#define RTC_BKP17R_Pos (0U)
11070#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
11071#define RTC_BKP17R RTC_BKP17R_Msk
11072
11073/******************** Bits definition for RTC_BKP18R register ***************/
11074#define RTC_BKP18R_Pos (0U)
11075#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
11076#define RTC_BKP18R RTC_BKP18R_Msk
11077
11078/******************** Bits definition for RTC_BKP19R register ***************/
11079#define RTC_BKP19R_Pos (0U)
11080#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
11081#define RTC_BKP19R RTC_BKP19R_Msk
11082
11083/******************** Number of backup registers ******************************/
11084#define RTC_BKP_NUMBER 0x000000014U
11085
11086
11087/******************************************************************************/
11088/* */
11089/* SD host Interface */
11090/* */
11091/******************************************************************************/
11092/****************** Bit definition for SDIO_POWER register ******************/
11093#define SDIO_POWER_PWRCTRL_Pos (0U)
11094#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
11095#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
11096#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
11097#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
11099/****************** Bit definition for SDIO_CLKCR register ******************/
11100#define SDIO_CLKCR_CLKDIV_Pos (0U)
11101#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
11102#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
11103#define SDIO_CLKCR_CLKEN_Pos (8U)
11104#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
11105#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
11106#define SDIO_CLKCR_PWRSAV_Pos (9U)
11107#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
11108#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
11109#define SDIO_CLKCR_BYPASS_Pos (10U)
11110#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
11111#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
11113#define SDIO_CLKCR_WIDBUS_Pos (11U)
11114#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
11115#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
11116#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
11117#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
11119#define SDIO_CLKCR_NEGEDGE_Pos (13U)
11120#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
11121#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
11122#define SDIO_CLKCR_HWFC_EN_Pos (14U)
11123#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
11124#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
11126/******************* Bit definition for SDIO_ARG register *******************/
11127#define SDIO_ARG_CMDARG_Pos (0U)
11128#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
11129#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
11131/******************* Bit definition for SDIO_CMD register *******************/
11132#define SDIO_CMD_CMDINDEX_Pos (0U)
11133#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
11134#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
11136#define SDIO_CMD_WAITRESP_Pos (6U)
11137#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
11138#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
11139#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
11140#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
11142#define SDIO_CMD_WAITINT_Pos (8U)
11143#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
11144#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
11145#define SDIO_CMD_WAITPEND_Pos (9U)
11146#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
11147#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
11148#define SDIO_CMD_CPSMEN_Pos (10U)
11149#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
11150#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
11151#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
11152#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
11153#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
11154#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
11155#define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
11156#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk
11157#define SDIO_CMD_NIEN_Pos (13U)
11158#define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)
11159#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk
11160#define SDIO_CMD_CEATACMD_Pos (14U)
11161#define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)
11162#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk
11164/***************** Bit definition for SDIO_RESPCMD register *****************/
11165#define SDIO_RESPCMD_RESPCMD_Pos (0U)
11166#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
11167#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
11169/****************** Bit definition for SDIO_RESP0 register ******************/
11170#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
11171#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
11172#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
11174/****************** Bit definition for SDIO_RESP1 register ******************/
11175#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
11176#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
11177#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
11179/****************** Bit definition for SDIO_RESP2 register ******************/
11180#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
11181#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
11182#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
11184/****************** Bit definition for SDIO_RESP3 register ******************/
11185#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
11186#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
11187#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
11189/****************** Bit definition for SDIO_RESP4 register ******************/
11190#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
11191#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
11192#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
11194/****************** Bit definition for SDIO_DTIMER register *****************/
11195#define SDIO_DTIMER_DATATIME_Pos (0U)
11196#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
11197#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
11199/****************** Bit definition for SDIO_DLEN register *******************/
11200#define SDIO_DLEN_DATALENGTH_Pos (0U)
11201#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
11202#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
11204/****************** Bit definition for SDIO_DCTRL register ******************/
11205#define SDIO_DCTRL_DTEN_Pos (0U)
11206#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
11207#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
11208#define SDIO_DCTRL_DTDIR_Pos (1U)
11209#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
11210#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
11211#define SDIO_DCTRL_DTMODE_Pos (2U)
11212#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
11213#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
11214#define SDIO_DCTRL_DMAEN_Pos (3U)
11215#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
11216#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
11218#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
11219#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11220#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
11221#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11222#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11223#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11224#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11226#define SDIO_DCTRL_RWSTART_Pos (8U)
11227#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
11228#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
11229#define SDIO_DCTRL_RWSTOP_Pos (9U)
11230#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
11231#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
11232#define SDIO_DCTRL_RWMOD_Pos (10U)
11233#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
11234#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
11235#define SDIO_DCTRL_SDIOEN_Pos (11U)
11236#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
11237#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
11239/****************** Bit definition for SDIO_DCOUNT register *****************/
11240#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
11241#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
11242#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
11244/****************** Bit definition for SDIO_STA register ********************/
11245#define SDIO_STA_CCRCFAIL_Pos (0U)
11246#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
11247#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
11248#define SDIO_STA_DCRCFAIL_Pos (1U)
11249#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
11250#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
11251#define SDIO_STA_CTIMEOUT_Pos (2U)
11252#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
11253#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
11254#define SDIO_STA_DTIMEOUT_Pos (3U)
11255#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
11256#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
11257#define SDIO_STA_TXUNDERR_Pos (4U)
11258#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
11259#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
11260#define SDIO_STA_RXOVERR_Pos (5U)
11261#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
11262#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
11263#define SDIO_STA_CMDREND_Pos (6U)
11264#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
11265#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
11266#define SDIO_STA_CMDSENT_Pos (7U)
11267#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
11268#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
11269#define SDIO_STA_DATAEND_Pos (8U)
11270#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
11271#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
11272#define SDIO_STA_STBITERR_Pos (9U)
11273#define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)
11274#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk
11275#define SDIO_STA_DBCKEND_Pos (10U)
11276#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
11277#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
11278#define SDIO_STA_CMDACT_Pos (11U)
11279#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
11280#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
11281#define SDIO_STA_TXACT_Pos (12U)
11282#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
11283#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
11284#define SDIO_STA_RXACT_Pos (13U)
11285#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
11286#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
11287#define SDIO_STA_TXFIFOHE_Pos (14U)
11288#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
11289#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
11290#define SDIO_STA_RXFIFOHF_Pos (15U)
11291#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
11292#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
11293#define SDIO_STA_TXFIFOF_Pos (16U)
11294#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
11295#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
11296#define SDIO_STA_RXFIFOF_Pos (17U)
11297#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
11298#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
11299#define SDIO_STA_TXFIFOE_Pos (18U)
11300#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
11301#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
11302#define SDIO_STA_RXFIFOE_Pos (19U)
11303#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
11304#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
11305#define SDIO_STA_TXDAVL_Pos (20U)
11306#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
11307#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
11308#define SDIO_STA_RXDAVL_Pos (21U)
11309#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
11310#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
11311#define SDIO_STA_SDIOIT_Pos (22U)
11312#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
11313#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
11314#define SDIO_STA_CEATAEND_Pos (23U)
11315#define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)
11316#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk
11318/******************* Bit definition for SDIO_ICR register *******************/
11319#define SDIO_ICR_CCRCFAILC_Pos (0U)
11320#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
11321#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
11322#define SDIO_ICR_DCRCFAILC_Pos (1U)
11323#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
11324#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
11325#define SDIO_ICR_CTIMEOUTC_Pos (2U)
11326#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
11327#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
11328#define SDIO_ICR_DTIMEOUTC_Pos (3U)
11329#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
11330#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
11331#define SDIO_ICR_TXUNDERRC_Pos (4U)
11332#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
11333#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
11334#define SDIO_ICR_RXOVERRC_Pos (5U)
11335#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
11336#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
11337#define SDIO_ICR_CMDRENDC_Pos (6U)
11338#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
11339#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
11340#define SDIO_ICR_CMDSENTC_Pos (7U)
11341#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
11342#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
11343#define SDIO_ICR_DATAENDC_Pos (8U)
11344#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
11345#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
11346#define SDIO_ICR_STBITERRC_Pos (9U)
11347#define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)
11348#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk
11349#define SDIO_ICR_DBCKENDC_Pos (10U)
11350#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
11351#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
11352#define SDIO_ICR_SDIOITC_Pos (22U)
11353#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
11354#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
11355#define SDIO_ICR_CEATAENDC_Pos (23U)
11356#define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)
11357#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk
11359/****************** Bit definition for SDIO_MASK register *******************/
11360#define SDIO_MASK_CCRCFAILIE_Pos (0U)
11361#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
11362#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
11363#define SDIO_MASK_DCRCFAILIE_Pos (1U)
11364#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
11365#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
11366#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
11367#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
11368#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
11369#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
11370#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
11371#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
11372#define SDIO_MASK_TXUNDERRIE_Pos (4U)
11373#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
11374#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
11375#define SDIO_MASK_RXOVERRIE_Pos (5U)
11376#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
11377#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
11378#define SDIO_MASK_CMDRENDIE_Pos (6U)
11379#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
11380#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
11381#define SDIO_MASK_CMDSENTIE_Pos (7U)
11382#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
11383#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
11384#define SDIO_MASK_DATAENDIE_Pos (8U)
11385#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
11386#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
11387#define SDIO_MASK_STBITERRIE_Pos (9U)
11388#define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)
11389#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk
11390#define SDIO_MASK_DBCKENDIE_Pos (10U)
11391#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
11392#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
11393#define SDIO_MASK_CMDACTIE_Pos (11U)
11394#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
11395#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
11396#define SDIO_MASK_TXACTIE_Pos (12U)
11397#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
11398#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
11399#define SDIO_MASK_RXACTIE_Pos (13U)
11400#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
11401#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
11402#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
11403#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
11404#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
11405#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
11406#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
11407#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
11408#define SDIO_MASK_TXFIFOFIE_Pos (16U)
11409#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
11410#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
11411#define SDIO_MASK_RXFIFOFIE_Pos (17U)
11412#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
11413#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
11414#define SDIO_MASK_TXFIFOEIE_Pos (18U)
11415#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
11416#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
11417#define SDIO_MASK_RXFIFOEIE_Pos (19U)
11418#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
11419#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
11420#define SDIO_MASK_TXDAVLIE_Pos (20U)
11421#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
11422#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
11423#define SDIO_MASK_RXDAVLIE_Pos (21U)
11424#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
11425#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
11426#define SDIO_MASK_SDIOITIE_Pos (22U)
11427#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
11428#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
11429#define SDIO_MASK_CEATAENDIE_Pos (23U)
11430#define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
11431#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk
11433/***************** Bit definition for SDIO_FIFOCNT register *****************/
11434#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
11435#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
11436#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
11438/****************** Bit definition for SDIO_FIFO register *******************/
11439#define SDIO_FIFO_FIFODATA_Pos (0U)
11440#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
11441#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
11443/******************************************************************************/
11444/* */
11445/* Serial Peripheral Interface */
11446/* */
11447/******************************************************************************/
11448#define SPI_I2S_FULLDUPLEX_SUPPORT
11450/******************* Bit definition for SPI_CR1 register ********************/
11451#define SPI_CR1_CPHA_Pos (0U)
11452#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
11453#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
11454#define SPI_CR1_CPOL_Pos (1U)
11455#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
11456#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
11457#define SPI_CR1_MSTR_Pos (2U)
11458#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
11459#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
11461#define SPI_CR1_BR_Pos (3U)
11462#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
11463#define SPI_CR1_BR SPI_CR1_BR_Msk
11464#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
11465#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
11466#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
11468#define SPI_CR1_SPE_Pos (6U)
11469#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
11470#define SPI_CR1_SPE SPI_CR1_SPE_Msk
11471#define SPI_CR1_LSBFIRST_Pos (7U)
11472#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
11473#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
11474#define SPI_CR1_SSI_Pos (8U)
11475#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
11476#define SPI_CR1_SSI SPI_CR1_SSI_Msk
11477#define SPI_CR1_SSM_Pos (9U)
11478#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
11479#define SPI_CR1_SSM SPI_CR1_SSM_Msk
11480#define SPI_CR1_RXONLY_Pos (10U)
11481#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
11482#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
11483#define SPI_CR1_DFF_Pos (11U)
11484#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
11485#define SPI_CR1_DFF SPI_CR1_DFF_Msk
11486#define SPI_CR1_CRCNEXT_Pos (12U)
11487#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
11488#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
11489#define SPI_CR1_CRCEN_Pos (13U)
11490#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
11491#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
11492#define SPI_CR1_BIDIOE_Pos (14U)
11493#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
11494#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
11495#define SPI_CR1_BIDIMODE_Pos (15U)
11496#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
11497#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
11499/******************* Bit definition for SPI_CR2 register ********************/
11500#define SPI_CR2_RXDMAEN_Pos (0U)
11501#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
11502#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
11503#define SPI_CR2_TXDMAEN_Pos (1U)
11504#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
11505#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
11506#define SPI_CR2_SSOE_Pos (2U)
11507#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
11508#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
11509#define SPI_CR2_FRF_Pos (4U)
11510#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
11511#define SPI_CR2_FRF SPI_CR2_FRF_Msk
11512#define SPI_CR2_ERRIE_Pos (5U)
11513#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
11514#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
11515#define SPI_CR2_RXNEIE_Pos (6U)
11516#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
11517#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
11518#define SPI_CR2_TXEIE_Pos (7U)
11519#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
11520#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
11522/******************** Bit definition for SPI_SR register ********************/
11523#define SPI_SR_RXNE_Pos (0U)
11524#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
11525#define SPI_SR_RXNE SPI_SR_RXNE_Msk
11526#define SPI_SR_TXE_Pos (1U)
11527#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
11528#define SPI_SR_TXE SPI_SR_TXE_Msk
11529#define SPI_SR_CHSIDE_Pos (2U)
11530#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
11531#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
11532#define SPI_SR_UDR_Pos (3U)
11533#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
11534#define SPI_SR_UDR SPI_SR_UDR_Msk
11535#define SPI_SR_CRCERR_Pos (4U)
11536#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
11537#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
11538#define SPI_SR_MODF_Pos (5U)
11539#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
11540#define SPI_SR_MODF SPI_SR_MODF_Msk
11541#define SPI_SR_OVR_Pos (6U)
11542#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
11543#define SPI_SR_OVR SPI_SR_OVR_Msk
11544#define SPI_SR_BSY_Pos (7U)
11545#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
11546#define SPI_SR_BSY SPI_SR_BSY_Msk
11547#define SPI_SR_FRE_Pos (8U)
11548#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
11549#define SPI_SR_FRE SPI_SR_FRE_Msk
11551/******************** Bit definition for SPI_DR register ********************/
11552#define SPI_DR_DR_Pos (0U)
11553#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
11554#define SPI_DR_DR SPI_DR_DR_Msk
11556/******************* Bit definition for SPI_CRCPR register ******************/
11557#define SPI_CRCPR_CRCPOLY_Pos (0U)
11558#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
11559#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
11561/****************** Bit definition for SPI_RXCRCR register ******************/
11562#define SPI_RXCRCR_RXCRC_Pos (0U)
11563#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
11564#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
11566/****************** Bit definition for SPI_TXCRCR register ******************/
11567#define SPI_TXCRCR_TXCRC_Pos (0U)
11568#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
11569#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
11571/****************** Bit definition for SPI_I2SCFGR register *****************/
11572#define SPI_I2SCFGR_CHLEN_Pos (0U)
11573#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
11574#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
11576#define SPI_I2SCFGR_DATLEN_Pos (1U)
11577#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
11578#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
11579#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
11580#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
11582#define SPI_I2SCFGR_CKPOL_Pos (3U)
11583#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
11584#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
11586#define SPI_I2SCFGR_I2SSTD_Pos (4U)
11587#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
11588#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
11589#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
11590#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
11592#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
11593#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
11594#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
11596#define SPI_I2SCFGR_I2SCFG_Pos (8U)
11597#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
11598#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
11599#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
11600#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
11602#define SPI_I2SCFGR_I2SE_Pos (10U)
11603#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
11604#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
11605#define SPI_I2SCFGR_I2SMOD_Pos (11U)
11606#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
11607#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
11609/****************** Bit definition for SPI_I2SPR register *******************/
11610#define SPI_I2SPR_I2SDIV_Pos (0U)
11611#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
11612#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
11613#define SPI_I2SPR_ODD_Pos (8U)
11614#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
11615#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
11616#define SPI_I2SPR_MCKOE_Pos (9U)
11617#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
11618#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
11620/******************************************************************************/
11621/* */
11622/* SYSCFG */
11623/* */
11624/******************************************************************************/
11625/****************** Bit definition for SYSCFG_MEMRMP register ***************/
11626#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
11627#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11628#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
11629#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11630#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
11631/****************** Bit definition for SYSCFG_PMC register ******************/
11632#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
11633#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
11634#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
11635/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
11636#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
11637
11638/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
11639#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
11640#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
11641#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
11642#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
11643#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
11644#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
11645#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
11646#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
11647#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
11648#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
11649#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
11650#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
11654#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
11655#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
11656#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
11657#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
11658#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
11659#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
11660#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
11661#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
11662#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
11667#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
11668#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
11669#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
11670#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
11671#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
11672#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
11673#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
11674#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
11675#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
11680#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
11681#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
11682#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
11683#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
11684#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
11685#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
11686#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
11687#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
11688#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
11693#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
11694#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
11695#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
11696#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
11697#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
11698#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
11699#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
11700#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
11701#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
11703/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
11704#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
11705#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
11706#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
11707#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
11708#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
11709#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
11710#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
11711#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
11712#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
11713#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
11714#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
11715#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
11720#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
11721#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
11722#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
11723#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
11724#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
11725#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
11726#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
11727#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
11728#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
11733#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
11734#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
11735#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
11736#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
11737#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
11738#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
11739#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
11740#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
11741#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
11746#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
11747#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
11748#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
11749#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
11750#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
11751#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
11752#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
11753#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
11754#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
11759#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
11760#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
11761#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
11762#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
11763#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
11764#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
11765#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
11766#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
11767#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
11769/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
11770#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
11771#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
11772#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
11773#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
11774#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
11775#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
11776#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
11777#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
11778#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
11779#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
11780#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
11781#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
11786#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
11787#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
11788#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
11789#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
11790#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
11791#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
11792#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
11793#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
11794#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
11799#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
11800#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
11801#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
11802#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
11803#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
11804#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
11805#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
11806#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
11807#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
11812#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
11813#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
11814#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
11815#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
11816#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
11817#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
11818#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
11819#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
11820#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
11825#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
11826#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
11827#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
11828#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
11829#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
11830#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
11831#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
11832#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
11833#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
11835/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
11836#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
11837#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
11838#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
11839#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
11840#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
11841#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
11842#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
11843#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
11844#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
11845#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
11846#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
11847#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
11852#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
11853#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
11854#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
11855#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
11856#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
11857#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
11858#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
11859#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
11864#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
11865#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
11866#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
11867#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
11868#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
11869#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
11870#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
11871#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
11876#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
11877#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
11878#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
11879#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
11880#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
11881#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
11882#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
11883#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
11888#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
11889#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
11890#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
11891#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
11892#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
11893#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
11894#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
11895#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
11897/****************** Bit definition for SYSCFG_CMPCR register ****************/
11898#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
11899#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
11900#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
11901#define SYSCFG_CMPCR_READY_Pos (8U)
11902#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
11903#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
11905/******************************************************************************/
11906/* */
11907/* TIM */
11908/* */
11909/******************************************************************************/
11910/******************* Bit definition for TIM_CR1 register ********************/
11911#define TIM_CR1_CEN_Pos (0U)
11912#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
11913#define TIM_CR1_CEN TIM_CR1_CEN_Msk
11914#define TIM_CR1_UDIS_Pos (1U)
11915#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
11916#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
11917#define TIM_CR1_URS_Pos (2U)
11918#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
11919#define TIM_CR1_URS TIM_CR1_URS_Msk
11920#define TIM_CR1_OPM_Pos (3U)
11921#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
11922#define TIM_CR1_OPM TIM_CR1_OPM_Msk
11923#define TIM_CR1_DIR_Pos (4U)
11924#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
11925#define TIM_CR1_DIR TIM_CR1_DIR_Msk
11927#define TIM_CR1_CMS_Pos (5U)
11928#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
11929#define TIM_CR1_CMS TIM_CR1_CMS_Msk
11930#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
11931#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
11933#define TIM_CR1_ARPE_Pos (7U)
11934#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
11935#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
11937#define TIM_CR1_CKD_Pos (8U)
11938#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
11939#define TIM_CR1_CKD TIM_CR1_CKD_Msk
11940#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
11941#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
11943/******************* Bit definition for TIM_CR2 register ********************/
11944#define TIM_CR2_CCPC_Pos (0U)
11945#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
11946#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
11947#define TIM_CR2_CCUS_Pos (2U)
11948#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
11949#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
11950#define TIM_CR2_CCDS_Pos (3U)
11951#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
11952#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
11954#define TIM_CR2_MMS_Pos (4U)
11955#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
11956#define TIM_CR2_MMS TIM_CR2_MMS_Msk
11957#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
11958#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
11959#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
11961#define TIM_CR2_TI1S_Pos (7U)
11962#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
11963#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
11964#define TIM_CR2_OIS1_Pos (8U)
11965#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
11966#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
11967#define TIM_CR2_OIS1N_Pos (9U)
11968#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
11969#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
11970#define TIM_CR2_OIS2_Pos (10U)
11971#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
11972#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
11973#define TIM_CR2_OIS2N_Pos (11U)
11974#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
11975#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
11976#define TIM_CR2_OIS3_Pos (12U)
11977#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
11978#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
11979#define TIM_CR2_OIS3N_Pos (13U)
11980#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
11981#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
11982#define TIM_CR2_OIS4_Pos (14U)
11983#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
11984#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
11986/******************* Bit definition for TIM_SMCR register *******************/
11987#define TIM_SMCR_SMS_Pos (0U)
11988#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
11989#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
11990#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
11991#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
11992#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
11994#define TIM_SMCR_TS_Pos (4U)
11995#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
11996#define TIM_SMCR_TS TIM_SMCR_TS_Msk
11997#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
11998#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
11999#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
12001#define TIM_SMCR_MSM_Pos (7U)
12002#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
12003#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
12005#define TIM_SMCR_ETF_Pos (8U)
12006#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
12007#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
12008#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
12009#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
12010#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
12011#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
12013#define TIM_SMCR_ETPS_Pos (12U)
12014#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
12015#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
12016#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
12017#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
12019#define TIM_SMCR_ECE_Pos (14U)
12020#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
12021#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
12022#define TIM_SMCR_ETP_Pos (15U)
12023#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
12024#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
12026/******************* Bit definition for TIM_DIER register *******************/
12027#define TIM_DIER_UIE_Pos (0U)
12028#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
12029#define TIM_DIER_UIE TIM_DIER_UIE_Msk
12030#define TIM_DIER_CC1IE_Pos (1U)
12031#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
12032#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
12033#define TIM_DIER_CC2IE_Pos (2U)
12034#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
12035#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
12036#define TIM_DIER_CC3IE_Pos (3U)
12037#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
12038#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
12039#define TIM_DIER_CC4IE_Pos (4U)
12040#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
12041#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
12042#define TIM_DIER_COMIE_Pos (5U)
12043#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
12044#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
12045#define TIM_DIER_TIE_Pos (6U)
12046#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
12047#define TIM_DIER_TIE TIM_DIER_TIE_Msk
12048#define TIM_DIER_BIE_Pos (7U)
12049#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
12050#define TIM_DIER_BIE TIM_DIER_BIE_Msk
12051#define TIM_DIER_UDE_Pos (8U)
12052#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
12053#define TIM_DIER_UDE TIM_DIER_UDE_Msk
12054#define TIM_DIER_CC1DE_Pos (9U)
12055#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
12056#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
12057#define TIM_DIER_CC2DE_Pos (10U)
12058#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
12059#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
12060#define TIM_DIER_CC3DE_Pos (11U)
12061#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
12062#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
12063#define TIM_DIER_CC4DE_Pos (12U)
12064#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
12065#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
12066#define TIM_DIER_COMDE_Pos (13U)
12067#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
12068#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
12069#define TIM_DIER_TDE_Pos (14U)
12070#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
12071#define TIM_DIER_TDE TIM_DIER_TDE_Msk
12073/******************** Bit definition for TIM_SR register ********************/
12074#define TIM_SR_UIF_Pos (0U)
12075#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
12076#define TIM_SR_UIF TIM_SR_UIF_Msk
12077#define TIM_SR_CC1IF_Pos (1U)
12078#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
12079#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
12080#define TIM_SR_CC2IF_Pos (2U)
12081#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
12082#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
12083#define TIM_SR_CC3IF_Pos (3U)
12084#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
12085#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
12086#define TIM_SR_CC4IF_Pos (4U)
12087#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
12088#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
12089#define TIM_SR_COMIF_Pos (5U)
12090#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
12091#define TIM_SR_COMIF TIM_SR_COMIF_Msk
12092#define TIM_SR_TIF_Pos (6U)
12093#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
12094#define TIM_SR_TIF TIM_SR_TIF_Msk
12095#define TIM_SR_BIF_Pos (7U)
12096#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
12097#define TIM_SR_BIF TIM_SR_BIF_Msk
12098#define TIM_SR_CC1OF_Pos (9U)
12099#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
12100#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
12101#define TIM_SR_CC2OF_Pos (10U)
12102#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
12103#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
12104#define TIM_SR_CC3OF_Pos (11U)
12105#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
12106#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
12107#define TIM_SR_CC4OF_Pos (12U)
12108#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
12109#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
12111/******************* Bit definition for TIM_EGR register ********************/
12112#define TIM_EGR_UG_Pos (0U)
12113#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
12114#define TIM_EGR_UG TIM_EGR_UG_Msk
12115#define TIM_EGR_CC1G_Pos (1U)
12116#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
12117#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
12118#define TIM_EGR_CC2G_Pos (2U)
12119#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
12120#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
12121#define TIM_EGR_CC3G_Pos (3U)
12122#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
12123#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
12124#define TIM_EGR_CC4G_Pos (4U)
12125#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
12126#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
12127#define TIM_EGR_COMG_Pos (5U)
12128#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
12129#define TIM_EGR_COMG TIM_EGR_COMG_Msk
12130#define TIM_EGR_TG_Pos (6U)
12131#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
12132#define TIM_EGR_TG TIM_EGR_TG_Msk
12133#define TIM_EGR_BG_Pos (7U)
12134#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
12135#define TIM_EGR_BG TIM_EGR_BG_Msk
12137/****************** Bit definition for TIM_CCMR1 register *******************/
12138#define TIM_CCMR1_CC1S_Pos (0U)
12139#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
12140#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
12141#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
12142#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
12144#define TIM_CCMR1_OC1FE_Pos (2U)
12145#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
12146#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
12147#define TIM_CCMR1_OC1PE_Pos (3U)
12148#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
12149#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
12151#define TIM_CCMR1_OC1M_Pos (4U)
12152#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
12153#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
12154#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
12155#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
12156#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
12158#define TIM_CCMR1_OC1CE_Pos (7U)
12159#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
12160#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
12162#define TIM_CCMR1_CC2S_Pos (8U)
12163#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
12164#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
12165#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
12166#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
12168#define TIM_CCMR1_OC2FE_Pos (10U)
12169#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
12170#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
12171#define TIM_CCMR1_OC2PE_Pos (11U)
12172#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
12173#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
12175#define TIM_CCMR1_OC2M_Pos (12U)
12176#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
12177#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
12178#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
12179#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
12180#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
12182#define TIM_CCMR1_OC2CE_Pos (15U)
12183#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
12184#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
12186/*----------------------------------------------------------------------------*/
12187
12188#define TIM_CCMR1_IC1PSC_Pos (2U)
12189#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
12190#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
12191#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
12192#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
12194#define TIM_CCMR1_IC1F_Pos (4U)
12195#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
12196#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
12197#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
12198#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
12199#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
12200#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
12202#define TIM_CCMR1_IC2PSC_Pos (10U)
12203#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
12204#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
12205#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
12206#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
12208#define TIM_CCMR1_IC2F_Pos (12U)
12209#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
12210#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
12211#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
12212#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
12213#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
12214#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
12216/****************** Bit definition for TIM_CCMR2 register *******************/
12217#define TIM_CCMR2_CC3S_Pos (0U)
12218#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
12219#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
12220#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
12221#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
12223#define TIM_CCMR2_OC3FE_Pos (2U)
12224#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
12225#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
12226#define TIM_CCMR2_OC3PE_Pos (3U)
12227#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
12228#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
12230#define TIM_CCMR2_OC3M_Pos (4U)
12231#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
12232#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
12233#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
12234#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
12235#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
12237#define TIM_CCMR2_OC3CE_Pos (7U)
12238#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
12239#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
12241#define TIM_CCMR2_CC4S_Pos (8U)
12242#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
12243#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
12244#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
12245#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
12247#define TIM_CCMR2_OC4FE_Pos (10U)
12248#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
12249#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
12250#define TIM_CCMR2_OC4PE_Pos (11U)
12251#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
12252#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
12254#define TIM_CCMR2_OC4M_Pos (12U)
12255#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
12256#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
12257#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
12258#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
12259#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
12261#define TIM_CCMR2_OC4CE_Pos (15U)
12262#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
12263#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
12265/*----------------------------------------------------------------------------*/
12266
12267#define TIM_CCMR2_IC3PSC_Pos (2U)
12268#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
12269#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
12270#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
12271#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
12273#define TIM_CCMR2_IC3F_Pos (4U)
12274#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
12275#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
12276#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
12277#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
12278#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
12279#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
12281#define TIM_CCMR2_IC4PSC_Pos (10U)
12282#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
12283#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
12284#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
12285#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
12287#define TIM_CCMR2_IC4F_Pos (12U)
12288#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
12289#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
12290#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
12291#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
12292#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
12293#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
12295/******************* Bit definition for TIM_CCER register *******************/
12296#define TIM_CCER_CC1E_Pos (0U)
12297#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
12298#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
12299#define TIM_CCER_CC1P_Pos (1U)
12300#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
12301#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
12302#define TIM_CCER_CC1NE_Pos (2U)
12303#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
12304#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
12305#define TIM_CCER_CC1NP_Pos (3U)
12306#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
12307#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
12308#define TIM_CCER_CC2E_Pos (4U)
12309#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
12310#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
12311#define TIM_CCER_CC2P_Pos (5U)
12312#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
12313#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
12314#define TIM_CCER_CC2NE_Pos (6U)
12315#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
12316#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
12317#define TIM_CCER_CC2NP_Pos (7U)
12318#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
12319#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
12320#define TIM_CCER_CC3E_Pos (8U)
12321#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
12322#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
12323#define TIM_CCER_CC3P_Pos (9U)
12324#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
12325#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
12326#define TIM_CCER_CC3NE_Pos (10U)
12327#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
12328#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
12329#define TIM_CCER_CC3NP_Pos (11U)
12330#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
12331#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
12332#define TIM_CCER_CC4E_Pos (12U)
12333#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
12334#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
12335#define TIM_CCER_CC4P_Pos (13U)
12336#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
12337#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
12338#define TIM_CCER_CC4NP_Pos (15U)
12339#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
12340#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
12342/******************* Bit definition for TIM_CNT register ********************/
12343#define TIM_CNT_CNT_Pos (0U)
12344#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
12345#define TIM_CNT_CNT TIM_CNT_CNT_Msk
12347/******************* Bit definition for TIM_PSC register ********************/
12348#define TIM_PSC_PSC_Pos (0U)
12349#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
12350#define TIM_PSC_PSC TIM_PSC_PSC_Msk
12352/******************* Bit definition for TIM_ARR register ********************/
12353#define TIM_ARR_ARR_Pos (0U)
12354#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
12355#define TIM_ARR_ARR TIM_ARR_ARR_Msk
12357/******************* Bit definition for TIM_RCR register ********************/
12358#define TIM_RCR_REP_Pos (0U)
12359#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
12360#define TIM_RCR_REP TIM_RCR_REP_Msk
12362/******************* Bit definition for TIM_CCR1 register *******************/
12363#define TIM_CCR1_CCR1_Pos (0U)
12364#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
12365#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
12367/******************* Bit definition for TIM_CCR2 register *******************/
12368#define TIM_CCR2_CCR2_Pos (0U)
12369#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
12370#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
12372/******************* Bit definition for TIM_CCR3 register *******************/
12373#define TIM_CCR3_CCR3_Pos (0U)
12374#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
12375#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
12377/******************* Bit definition for TIM_CCR4 register *******************/
12378#define TIM_CCR4_CCR4_Pos (0U)
12379#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
12380#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
12382/******************* Bit definition for TIM_BDTR register *******************/
12383#define TIM_BDTR_DTG_Pos (0U)
12384#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
12385#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
12386#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
12387#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
12388#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
12389#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
12390#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
12391#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
12392#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
12393#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
12395#define TIM_BDTR_LOCK_Pos (8U)
12396#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
12397#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
12398#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
12399#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
12401#define TIM_BDTR_OSSI_Pos (10U)
12402#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
12403#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
12404#define TIM_BDTR_OSSR_Pos (11U)
12405#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
12406#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
12407#define TIM_BDTR_BKE_Pos (12U)
12408#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
12409#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
12410#define TIM_BDTR_BKP_Pos (13U)
12411#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
12412#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
12413#define TIM_BDTR_AOE_Pos (14U)
12414#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
12415#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
12416#define TIM_BDTR_MOE_Pos (15U)
12417#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
12418#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
12420/******************* Bit definition for TIM_DCR register ********************/
12421#define TIM_DCR_DBA_Pos (0U)
12422#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
12423#define TIM_DCR_DBA TIM_DCR_DBA_Msk
12424#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
12425#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
12426#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
12427#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
12428#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
12430#define TIM_DCR_DBL_Pos (8U)
12431#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
12432#define TIM_DCR_DBL TIM_DCR_DBL_Msk
12433#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
12434#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
12435#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
12436#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
12437#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
12439/******************* Bit definition for TIM_DMAR register *******************/
12440#define TIM_DMAR_DMAB_Pos (0U)
12441#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
12442#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
12444/******************* Bit definition for TIM_OR register *********************/
12445#define TIM_OR_TI1_RMP_Pos (0U)
12446#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
12447#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
12448#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
12449#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
12451#define TIM_OR_TI4_RMP_Pos (6U)
12452#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
12453#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
12454#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
12455#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
12456#define TIM_OR_ITR1_RMP_Pos (10U)
12457#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
12458#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
12459#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
12460#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
12463/******************************************************************************/
12464/* */
12465/* Universal Synchronous Asynchronous Receiver Transmitter */
12466/* */
12467/******************************************************************************/
12468/******************* Bit definition for USART_SR register *******************/
12469#define USART_SR_PE_Pos (0U)
12470#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
12471#define USART_SR_PE USART_SR_PE_Msk
12472#define USART_SR_FE_Pos (1U)
12473#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
12474#define USART_SR_FE USART_SR_FE_Msk
12475#define USART_SR_NE_Pos (2U)
12476#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
12477#define USART_SR_NE USART_SR_NE_Msk
12478#define USART_SR_ORE_Pos (3U)
12479#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
12480#define USART_SR_ORE USART_SR_ORE_Msk
12481#define USART_SR_IDLE_Pos (4U)
12482#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
12483#define USART_SR_IDLE USART_SR_IDLE_Msk
12484#define USART_SR_RXNE_Pos (5U)
12485#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
12486#define USART_SR_RXNE USART_SR_RXNE_Msk
12487#define USART_SR_TC_Pos (6U)
12488#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
12489#define USART_SR_TC USART_SR_TC_Msk
12490#define USART_SR_TXE_Pos (7U)
12491#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
12492#define USART_SR_TXE USART_SR_TXE_Msk
12493#define USART_SR_LBD_Pos (8U)
12494#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
12495#define USART_SR_LBD USART_SR_LBD_Msk
12496#define USART_SR_CTS_Pos (9U)
12497#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
12498#define USART_SR_CTS USART_SR_CTS_Msk
12500/******************* Bit definition for USART_DR register *******************/
12501#define USART_DR_DR_Pos (0U)
12502#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
12503#define USART_DR_DR USART_DR_DR_Msk
12505/****************** Bit definition for USART_BRR register *******************/
12506#define USART_BRR_DIV_Fraction_Pos (0U)
12507#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
12508#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
12509#define USART_BRR_DIV_Mantissa_Pos (4U)
12510#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
12511#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
12513/****************** Bit definition for USART_CR1 register *******************/
12514#define USART_CR1_SBK_Pos (0U)
12515#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
12516#define USART_CR1_SBK USART_CR1_SBK_Msk
12517#define USART_CR1_RWU_Pos (1U)
12518#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
12519#define USART_CR1_RWU USART_CR1_RWU_Msk
12520#define USART_CR1_RE_Pos (2U)
12521#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
12522#define USART_CR1_RE USART_CR1_RE_Msk
12523#define USART_CR1_TE_Pos (3U)
12524#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
12525#define USART_CR1_TE USART_CR1_TE_Msk
12526#define USART_CR1_IDLEIE_Pos (4U)
12527#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
12528#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
12529#define USART_CR1_RXNEIE_Pos (5U)
12530#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
12531#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
12532#define USART_CR1_TCIE_Pos (6U)
12533#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
12534#define USART_CR1_TCIE USART_CR1_TCIE_Msk
12535#define USART_CR1_TXEIE_Pos (7U)
12536#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
12537#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
12538#define USART_CR1_PEIE_Pos (8U)
12539#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
12540#define USART_CR1_PEIE USART_CR1_PEIE_Msk
12541#define USART_CR1_PS_Pos (9U)
12542#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
12543#define USART_CR1_PS USART_CR1_PS_Msk
12544#define USART_CR1_PCE_Pos (10U)
12545#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
12546#define USART_CR1_PCE USART_CR1_PCE_Msk
12547#define USART_CR1_WAKE_Pos (11U)
12548#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
12549#define USART_CR1_WAKE USART_CR1_WAKE_Msk
12550#define USART_CR1_M_Pos (12U)
12551#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
12552#define USART_CR1_M USART_CR1_M_Msk
12553#define USART_CR1_UE_Pos (13U)
12554#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
12555#define USART_CR1_UE USART_CR1_UE_Msk
12556#define USART_CR1_OVER8_Pos (15U)
12557#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
12558#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
12560/****************** Bit definition for USART_CR2 register *******************/
12561#define USART_CR2_ADD_Pos (0U)
12562#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
12563#define USART_CR2_ADD USART_CR2_ADD_Msk
12564#define USART_CR2_LBDL_Pos (5U)
12565#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
12566#define USART_CR2_LBDL USART_CR2_LBDL_Msk
12567#define USART_CR2_LBDIE_Pos (6U)
12568#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
12569#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
12570#define USART_CR2_LBCL_Pos (8U)
12571#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
12572#define USART_CR2_LBCL USART_CR2_LBCL_Msk
12573#define USART_CR2_CPHA_Pos (9U)
12574#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
12575#define USART_CR2_CPHA USART_CR2_CPHA_Msk
12576#define USART_CR2_CPOL_Pos (10U)
12577#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
12578#define USART_CR2_CPOL USART_CR2_CPOL_Msk
12579#define USART_CR2_CLKEN_Pos (11U)
12580#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
12581#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
12583#define USART_CR2_STOP_Pos (12U)
12584#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
12585#define USART_CR2_STOP USART_CR2_STOP_Msk
12586#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
12587#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
12589#define USART_CR2_LINEN_Pos (14U)
12590#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
12591#define USART_CR2_LINEN USART_CR2_LINEN_Msk
12593/****************** Bit definition for USART_CR3 register *******************/
12594#define USART_CR3_EIE_Pos (0U)
12595#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
12596#define USART_CR3_EIE USART_CR3_EIE_Msk
12597#define USART_CR3_IREN_Pos (1U)
12598#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
12599#define USART_CR3_IREN USART_CR3_IREN_Msk
12600#define USART_CR3_IRLP_Pos (2U)
12601#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
12602#define USART_CR3_IRLP USART_CR3_IRLP_Msk
12603#define USART_CR3_HDSEL_Pos (3U)
12604#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
12605#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
12606#define USART_CR3_NACK_Pos (4U)
12607#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
12608#define USART_CR3_NACK USART_CR3_NACK_Msk
12609#define USART_CR3_SCEN_Pos (5U)
12610#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
12611#define USART_CR3_SCEN USART_CR3_SCEN_Msk
12612#define USART_CR3_DMAR_Pos (6U)
12613#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
12614#define USART_CR3_DMAR USART_CR3_DMAR_Msk
12615#define USART_CR3_DMAT_Pos (7U)
12616#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
12617#define USART_CR3_DMAT USART_CR3_DMAT_Msk
12618#define USART_CR3_RTSE_Pos (8U)
12619#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
12620#define USART_CR3_RTSE USART_CR3_RTSE_Msk
12621#define USART_CR3_CTSE_Pos (9U)
12622#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
12623#define USART_CR3_CTSE USART_CR3_CTSE_Msk
12624#define USART_CR3_CTSIE_Pos (10U)
12625#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
12626#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
12627#define USART_CR3_ONEBIT_Pos (11U)
12628#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
12629#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
12631/****************** Bit definition for USART_GTPR register ******************/
12632#define USART_GTPR_PSC_Pos (0U)
12633#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
12634#define USART_GTPR_PSC USART_GTPR_PSC_Msk
12635#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
12636#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
12637#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
12638#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
12639#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
12640#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
12641#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
12642#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
12644#define USART_GTPR_GT_Pos (8U)
12645#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
12646#define USART_GTPR_GT USART_GTPR_GT_Msk
12648/******************************************************************************/
12649/* */
12650/* Window WATCHDOG */
12651/* */
12652/******************************************************************************/
12653/******************* Bit definition for WWDG_CR register ********************/
12654#define WWDG_CR_T_Pos (0U)
12655#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
12656#define WWDG_CR_T WWDG_CR_T_Msk
12657#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
12658#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
12659#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
12660#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
12661#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
12662#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
12663#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
12664/* Legacy defines */
12665#define WWDG_CR_T0 WWDG_CR_T_0
12666#define WWDG_CR_T1 WWDG_CR_T_1
12667#define WWDG_CR_T2 WWDG_CR_T_2
12668#define WWDG_CR_T3 WWDG_CR_T_3
12669#define WWDG_CR_T4 WWDG_CR_T_4
12670#define WWDG_CR_T5 WWDG_CR_T_5
12671#define WWDG_CR_T6 WWDG_CR_T_6
12672
12673#define WWDG_CR_WDGA_Pos (7U)
12674#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
12675#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
12677/******************* Bit definition for WWDG_CFR register *******************/
12678#define WWDG_CFR_W_Pos (0U)
12679#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
12680#define WWDG_CFR_W WWDG_CFR_W_Msk
12681#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
12682#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
12683#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
12684#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
12685#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
12686#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
12687#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
12688/* Legacy defines */
12689#define WWDG_CFR_W0 WWDG_CFR_W_0
12690#define WWDG_CFR_W1 WWDG_CFR_W_1
12691#define WWDG_CFR_W2 WWDG_CFR_W_2
12692#define WWDG_CFR_W3 WWDG_CFR_W_3
12693#define WWDG_CFR_W4 WWDG_CFR_W_4
12694#define WWDG_CFR_W5 WWDG_CFR_W_5
12695#define WWDG_CFR_W6 WWDG_CFR_W_6
12696
12697#define WWDG_CFR_WDGTB_Pos (7U)
12698#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
12699#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
12700#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
12701#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
12702/* Legacy defines */
12703#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
12704#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
12705
12706#define WWDG_CFR_EWI_Pos (9U)
12707#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
12708#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
12710/******************* Bit definition for WWDG_SR register ********************/
12711#define WWDG_SR_EWIF_Pos (0U)
12712#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
12713#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
12716/******************************************************************************/
12717/* */
12718/* DBG */
12719/* */
12720/******************************************************************************/
12721/******************** Bit definition for DBGMCU_IDCODE register *************/
12722#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
12723#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
12724#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
12725#define DBGMCU_IDCODE_REV_ID_Pos (16U)
12726#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
12727#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
12728
12729/******************** Bit definition for DBGMCU_CR register *****************/
12730#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
12731#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
12732#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
12733#define DBGMCU_CR_DBG_STOP_Pos (1U)
12734#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
12735#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
12736#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
12737#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
12738#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
12739#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
12740#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
12741#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
12742
12743#define DBGMCU_CR_TRACE_MODE_Pos (6U)
12744#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
12745#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
12746#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
12747#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
12749/******************** Bit definition for DBGMCU_APB1_FZ register ************/
12750#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
12751#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
12752#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
12753#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
12754#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
12755#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
12756#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
12757#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
12758#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
12759#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
12760#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
12761#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
12762#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
12763#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
12764#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
12765#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
12766#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
12767#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
12768#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
12769#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
12770#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
12771#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
12772#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
12773#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
12774#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
12775#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
12776#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
12777#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
12778#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
12779#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
12780#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
12781#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
12782#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
12783#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
12784#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
12785#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
12786#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
12787#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
12788#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
12789#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
12790#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
12791#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
12792#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
12793#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
12794#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
12795#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
12796#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
12797#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
12798#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
12799#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
12800#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
12801/* Old IWDGSTOP bit definition, maintained for legacy purpose */
12802#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
12803
12804/******************** Bit definition for DBGMCU_APB2_FZ register ************/
12805#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
12806#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
12807#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
12808#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
12809#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
12810#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
12811#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
12812#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
12813#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
12814#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
12815#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
12816#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
12817#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
12818#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
12819#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
12820
12821/******************************************************************************/
12822/* */
12823/* Ethernet MAC Registers bits definitions */
12824/* */
12825/******************************************************************************/
12826/* Bit definition for Ethernet MAC Control Register register */
12827#define ETH_MACCR_WD_Pos (23U)
12828#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
12829#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
12830#define ETH_MACCR_JD_Pos (22U)
12831#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
12832#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
12833#define ETH_MACCR_IFG_Pos (17U)
12834#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
12835#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
12836#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
12837#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
12838#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
12839#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
12840#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
12841#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
12842#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
12843#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
12844#define ETH_MACCR_CSD_Pos (16U)
12845#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
12846#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
12847#define ETH_MACCR_FES_Pos (14U)
12848#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
12849#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
12850#define ETH_MACCR_ROD_Pos (13U)
12851#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
12852#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
12853#define ETH_MACCR_LM_Pos (12U)
12854#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
12855#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
12856#define ETH_MACCR_DM_Pos (11U)
12857#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
12858#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
12859#define ETH_MACCR_IPCO_Pos (10U)
12860#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
12861#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
12862#define ETH_MACCR_RD_Pos (9U)
12863#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
12864#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
12865#define ETH_MACCR_APCS_Pos (7U)
12866#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
12867#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
12868#define ETH_MACCR_BL_Pos (5U)
12869#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
12870#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
12871 a transmission attempt during retries after a collision: 0 =< r <2^k */
12872#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
12873#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
12874#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
12875#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
12876#define ETH_MACCR_DC_Pos (4U)
12877#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
12878#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
12879#define ETH_MACCR_TE_Pos (3U)
12880#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
12881#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
12882#define ETH_MACCR_RE_Pos (2U)
12883#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
12884#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
12885
12886/* Bit definition for Ethernet MAC Frame Filter Register */
12887#define ETH_MACFFR_RA_Pos (31U)
12888#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
12889#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
12890#define ETH_MACFFR_HPF_Pos (10U)
12891#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
12892#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
12893#define ETH_MACFFR_SAF_Pos (9U)
12894#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
12895#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
12896#define ETH_MACFFR_SAIF_Pos (8U)
12897#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
12898#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
12899#define ETH_MACFFR_PCF_Pos (6U)
12900#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
12901#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
12902#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
12903#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
12904#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
12905#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
12906#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
12907#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
12908#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
12909#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
12910#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
12911#define ETH_MACFFR_BFD_Pos (5U)
12912#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
12913#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
12914#define ETH_MACFFR_PAM_Pos (4U)
12915#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
12916#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
12917#define ETH_MACFFR_DAIF_Pos (3U)
12918#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
12919#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
12920#define ETH_MACFFR_HM_Pos (2U)
12921#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
12922#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
12923#define ETH_MACFFR_HU_Pos (1U)
12924#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
12925#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
12926#define ETH_MACFFR_PM_Pos (0U)
12927#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
12928#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
12929
12930/* Bit definition for Ethernet MAC Hash Table High Register */
12931#define ETH_MACHTHR_HTH_Pos (0U)
12932#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
12933#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
12934
12935/* Bit definition for Ethernet MAC Hash Table Low Register */
12936#define ETH_MACHTLR_HTL_Pos (0U)
12937#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
12938#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
12939
12940/* Bit definition for Ethernet MAC MII Address Register */
12941#define ETH_MACMIIAR_PA_Pos (11U)
12942#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
12943#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
12944#define ETH_MACMIIAR_MR_Pos (6U)
12945#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
12946#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
12947#define ETH_MACMIIAR_CR_Pos (2U)
12948#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
12949#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
12950#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
12951#define ETH_MACMIIAR_CR_Div62_Pos (2U)
12952#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
12953#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
12954#define ETH_MACMIIAR_CR_Div16_Pos (3U)
12955#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
12956#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
12957#define ETH_MACMIIAR_CR_Div26_Pos (2U)
12958#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
12959#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
12960#define ETH_MACMIIAR_CR_Div102_Pos (4U)
12961#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
12962#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
12963#define ETH_MACMIIAR_MW_Pos (1U)
12964#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
12965#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
12966#define ETH_MACMIIAR_MB_Pos (0U)
12967#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
12968#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
12969
12970/* Bit definition for Ethernet MAC MII Data Register */
12971#define ETH_MACMIIDR_MD_Pos (0U)
12972#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
12973#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
12974
12975/* Bit definition for Ethernet MAC Flow Control Register */
12976#define ETH_MACFCR_PT_Pos (16U)
12977#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
12978#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
12979#define ETH_MACFCR_ZQPD_Pos (7U)
12980#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
12981#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
12982#define ETH_MACFCR_PLT_Pos (4U)
12983#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
12984#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
12985#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
12986#define ETH_MACFCR_PLT_Minus28_Pos (4U)
12987#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
12988#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
12989#define ETH_MACFCR_PLT_Minus144_Pos (5U)
12990#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
12991#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
12992#define ETH_MACFCR_PLT_Minus256_Pos (4U)
12993#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
12994#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
12995#define ETH_MACFCR_UPFD_Pos (3U)
12996#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
12997#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
12998#define ETH_MACFCR_RFCE_Pos (2U)
12999#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
13000#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
13001#define ETH_MACFCR_TFCE_Pos (1U)
13002#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
13003#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
13004#define ETH_MACFCR_FCBBPA_Pos (0U)
13005#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
13006#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
13007
13008/* Bit definition for Ethernet MAC VLAN Tag Register */
13009#define ETH_MACVLANTR_VLANTC_Pos (16U)
13010#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
13011#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
13012#define ETH_MACVLANTR_VLANTI_Pos (0U)
13013#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
13014#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
13015
13016/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
13017#define ETH_MACRWUFFR_D_Pos (0U)
13018#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
13019#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
13020/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
13021 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
13022/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
13023 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
13024 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
13025 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
13026 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
13027 RSVD - Filter1 Command - RSVD - Filter0 Command
13028 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
13029 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
13030 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
13031
13032/* Bit definition for Ethernet MAC PMT Control and Status Register */
13033#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
13034#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
13035#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
13036#define ETH_MACPMTCSR_GU_Pos (9U)
13037#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
13038#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
13039#define ETH_MACPMTCSR_WFR_Pos (6U)
13040#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
13041#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
13042#define ETH_MACPMTCSR_MPR_Pos (5U)
13043#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
13044#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
13045#define ETH_MACPMTCSR_WFE_Pos (2U)
13046#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
13047#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
13048#define ETH_MACPMTCSR_MPE_Pos (1U)
13049#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
13050#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
13051#define ETH_MACPMTCSR_PD_Pos (0U)
13052#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
13053#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
13054
13055/* Bit definition for Ethernet MAC debug Register */
13056#define ETH_MACDBGR_TFF_Pos (25U)
13057#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
13058#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
13059#define ETH_MACDBGR_TFNE_Pos (24U)
13060#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
13061#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
13062#define ETH_MACDBGR_TFWA_Pos (22U)
13063#define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)
13064#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
13065#define ETH_MACDBGR_TFRS_Pos (20U)
13066#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
13067#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
13068#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
13069#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
13070#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
13071#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
13072#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
13073#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
13074#define ETH_MACDBGR_TFRS_READ_Pos (20U)
13075#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
13076#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
13077#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
13078#define ETH_MACDBGR_MTP_Pos (19U)
13079#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
13080#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
13081#define ETH_MACDBGR_MTFCS_Pos (17U)
13082#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
13083#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
13084#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
13085#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
13086#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
13087#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
13088#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
13089#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
13090#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
13091#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
13092#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
13093#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
13094#define ETH_MACDBGR_MMTEA_Pos (16U)
13095#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
13096#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
13097#define ETH_MACDBGR_RFFL_Pos (8U)
13098#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
13099#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
13100#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
13101#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
13102#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
13103#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
13104#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
13105#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
13106#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
13107#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
13108#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
13109#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
13110#define ETH_MACDBGR_RFRCS_Pos (5U)
13111#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
13112#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
13113#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
13114#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
13115#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
13116#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
13117#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
13118#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
13119#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
13120#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
13121#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
13122#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
13123#define ETH_MACDBGR_RFWRA_Pos (4U)
13124#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
13125#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
13126#define ETH_MACDBGR_MSFRWCS_Pos (1U)
13127#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
13128#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
13129#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
13130#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
13131#define ETH_MACDBGR_MMRPEA_Pos (0U)
13132#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
13133#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
13134
13135/* Bit definition for Ethernet MAC Status Register */
13136#define ETH_MACSR_TSTS_Pos (9U)
13137#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
13138#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
13139#define ETH_MACSR_MMCTS_Pos (6U)
13140#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
13141#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
13142#define ETH_MACSR_MMMCRS_Pos (5U)
13143#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
13144#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
13145#define ETH_MACSR_MMCS_Pos (4U)
13146#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
13147#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
13148#define ETH_MACSR_PMTS_Pos (3U)
13149#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
13150#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
13151
13152/* Bit definition for Ethernet MAC Interrupt Mask Register */
13153#define ETH_MACIMR_TSTIM_Pos (9U)
13154#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
13155#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
13156#define ETH_MACIMR_PMTIM_Pos (3U)
13157#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
13158#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
13159
13160/* Bit definition for Ethernet MAC Address0 High Register */
13161#define ETH_MACA0HR_MACA0H_Pos (0U)
13162#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
13163#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
13164
13165/* Bit definition for Ethernet MAC Address0 Low Register */
13166#define ETH_MACA0LR_MACA0L_Pos (0U)
13167#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
13168#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
13169
13170/* Bit definition for Ethernet MAC Address1 High Register */
13171#define ETH_MACA1HR_AE_Pos (31U)
13172#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
13173#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
13174#define ETH_MACA1HR_SA_Pos (30U)
13175#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
13176#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
13177#define ETH_MACA1HR_MBC_Pos (24U)
13178#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
13179#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
13180#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13181#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13182#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13183#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13184#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13185#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
13186#define ETH_MACA1HR_MACA1H_Pos (0U)
13187#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
13188#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
13189
13190/* Bit definition for Ethernet MAC Address1 Low Register */
13191#define ETH_MACA1LR_MACA1L_Pos (0U)
13192#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
13193#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
13194
13195/* Bit definition for Ethernet MAC Address2 High Register */
13196#define ETH_MACA2HR_AE_Pos (31U)
13197#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
13198#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
13199#define ETH_MACA2HR_SA_Pos (30U)
13200#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
13201#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
13202#define ETH_MACA2HR_MBC_Pos (24U)
13203#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
13204#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
13205#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13206#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13207#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13208#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13209#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13210#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
13211#define ETH_MACA2HR_MACA2H_Pos (0U)
13212#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
13213#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
13214
13215/* Bit definition for Ethernet MAC Address2 Low Register */
13216#define ETH_MACA2LR_MACA2L_Pos (0U)
13217#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
13218#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
13219
13220/* Bit definition for Ethernet MAC Address3 High Register */
13221#define ETH_MACA3HR_AE_Pos (31U)
13222#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
13223#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
13224#define ETH_MACA3HR_SA_Pos (30U)
13225#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
13226#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
13227#define ETH_MACA3HR_MBC_Pos (24U)
13228#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
13229#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
13230#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
13231#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
13232#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
13233#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
13234#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
13235#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
13236#define ETH_MACA3HR_MACA3H_Pos (0U)
13237#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
13238#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
13239
13240/* Bit definition for Ethernet MAC Address3 Low Register */
13241#define ETH_MACA3LR_MACA3L_Pos (0U)
13242#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
13243#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
13244
13245/******************************************************************************/
13246/* Ethernet MMC Registers bits definition */
13247/******************************************************************************/
13248
13249/* Bit definition for Ethernet MMC Control Register */
13250#define ETH_MMCCR_MCFHP_Pos (5U)
13251#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
13252#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
13253#define ETH_MMCCR_MCP_Pos (4U)
13254#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
13255#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
13256#define ETH_MMCCR_MCF_Pos (3U)
13257#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
13258#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
13259#define ETH_MMCCR_ROR_Pos (2U)
13260#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
13261#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
13262#define ETH_MMCCR_CSR_Pos (1U)
13263#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
13264#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
13265#define ETH_MMCCR_CR_Pos (0U)
13266#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
13267#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
13268
13269/* Bit definition for Ethernet MMC Receive Interrupt Register */
13270#define ETH_MMCRIR_RGUFS_Pos (17U)
13271#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
13272#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
13273#define ETH_MMCRIR_RFAES_Pos (6U)
13274#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
13275#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
13276#define ETH_MMCRIR_RFCES_Pos (5U)
13277#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
13278#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
13279
13280/* Bit definition for Ethernet MMC Transmit Interrupt Register */
13281#define ETH_MMCTIR_TGFS_Pos (21U)
13282#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
13283#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
13284#define ETH_MMCTIR_TGFMSCS_Pos (15U)
13285#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
13286#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
13287#define ETH_MMCTIR_TGFSCS_Pos (14U)
13288#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
13289#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
13290
13291/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
13292#define ETH_MMCRIMR_RGUFM_Pos (17U)
13293#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
13294#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
13295#define ETH_MMCRIMR_RFAEM_Pos (6U)
13296#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
13297#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
13298#define ETH_MMCRIMR_RFCEM_Pos (5U)
13299#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
13300#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
13301
13302/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
13303#define ETH_MMCTIMR_TGFM_Pos (21U)
13304#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
13305#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
13306#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
13307#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
13308#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
13309#define ETH_MMCTIMR_TGFSCM_Pos (14U)
13310#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
13311#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
13312
13313/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
13314#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
13315#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
13316#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
13317
13318/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
13319#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
13320#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
13321#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
13322
13323/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
13324#define ETH_MMCTGFCR_TGFC_Pos (0U)
13325#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
13326#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
13327
13328/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
13329#define ETH_MMCRFCECR_RFCEC_Pos (0U)
13330#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
13331#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
13332
13333/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
13334#define ETH_MMCRFAECR_RFAEC_Pos (0U)
13335#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
13336#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
13337
13338/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
13339#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
13340#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
13341#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
13342
13343/******************************************************************************/
13344/* Ethernet PTP Registers bits definition */
13345/******************************************************************************/
13346
13347/* Bit definition for Ethernet PTP Time Stamp Control Register */
13348#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
13349#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)
13350#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
13351#define ETH_PTPTSCR_TSCNT_Pos (16U)
13352#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
13353#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
13354#define ETH_PTPTSCR_TSSMRME_Pos (15U)
13355#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)
13356#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
13357#define ETH_PTPTSCR_TSSEME_Pos (14U)
13358#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos)
13359#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
13360#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
13361#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)
13362#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
13363#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
13364#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)
13365#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
13366#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
13367#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)
13368#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
13369#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
13370#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)
13371#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
13372#define ETH_PTPTSCR_TSSSR_Pos (9U)
13373#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos)
13374#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
13375#define ETH_PTPTSCR_TSSARFE_Pos (8U)
13376#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)
13377#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
13378
13379#define ETH_PTPTSCR_TSARU_Pos (5U)
13380#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
13381#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
13382#define ETH_PTPTSCR_TSITE_Pos (4U)
13383#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
13384#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
13385#define ETH_PTPTSCR_TSSTU_Pos (3U)
13386#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
13387#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
13388#define ETH_PTPTSCR_TSSTI_Pos (2U)
13389#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
13390#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
13391#define ETH_PTPTSCR_TSFCU_Pos (1U)
13392#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
13393#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
13394#define ETH_PTPTSCR_TSE_Pos (0U)
13395#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
13396#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
13397
13398/* Bit definition for Ethernet PTP Sub-Second Increment Register */
13399#define ETH_PTPSSIR_STSSI_Pos (0U)
13400#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
13401#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
13402
13403/* Bit definition for Ethernet PTP Time Stamp High Register */
13404#define ETH_PTPTSHR_STS_Pos (0U)
13405#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
13406#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
13407
13408/* Bit definition for Ethernet PTP Time Stamp Low Register */
13409#define ETH_PTPTSLR_STPNS_Pos (31U)
13410#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
13411#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
13412#define ETH_PTPTSLR_STSS_Pos (0U)
13413#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
13414#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
13415
13416/* Bit definition for Ethernet PTP Time Stamp High Update Register */
13417#define ETH_PTPTSHUR_TSUS_Pos (0U)
13418#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
13419#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
13420
13421/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
13422#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
13423#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
13424#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
13425#define ETH_PTPTSLUR_TSUSS_Pos (0U)
13426#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
13427#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
13428
13429/* Bit definition for Ethernet PTP Time Stamp Addend Register */
13430#define ETH_PTPTSAR_TSA_Pos (0U)
13431#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
13432#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
13433
13434/* Bit definition for Ethernet PTP Target Time High Register */
13435#define ETH_PTPTTHR_TTSH_Pos (0U)
13436#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
13437#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
13438
13439/* Bit definition for Ethernet PTP Target Time Low Register */
13440#define ETH_PTPTTLR_TTSL_Pos (0U)
13441#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
13442#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
13443
13444/* Bit definition for Ethernet PTP Time Stamp Status Register */
13445#define ETH_PTPTSSR_TSTTR_Pos (5U)
13446#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
13447#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
13448#define ETH_PTPTSSR_TSSO_Pos (4U)
13449#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
13450#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
13451
13452/******************************************************************************/
13453/* Ethernet DMA Registers bits definition */
13454/******************************************************************************/
13455
13456/* Bit definition for Ethernet DMA Bus Mode Register */
13457#define ETH_DMABMR_MB_Pos (26U)
13458#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos)
13459#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
13460#define ETH_DMABMR_AAB_Pos (25U)
13461#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
13462#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
13463#define ETH_DMABMR_FPM_Pos (24U)
13464#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
13465#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
13466#define ETH_DMABMR_USP_Pos (23U)
13467#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
13468#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
13469#define ETH_DMABMR_RDP_Pos (17U)
13470#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
13471#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
13472#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
13473#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
13474#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
13475#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
13476#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
13477#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
13478#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
13479#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
13480#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
13481#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
13482#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
13483#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
13484#define ETH_DMABMR_FB_Pos (16U)
13485#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
13486#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
13487#define ETH_DMABMR_RTPR_Pos (14U)
13488#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
13489#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
13490#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
13491#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
13492#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
13493#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
13494#define ETH_DMABMR_PBL_Pos (8U)
13495#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
13496#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
13497#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
13498#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
13499#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
13500#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
13501#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
13502#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
13503#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
13504#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
13505#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
13506#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
13507#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
13508#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
13509#define ETH_DMABMR_EDE_Pos (7U)
13510#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
13511#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
13512#define ETH_DMABMR_DSL_Pos (2U)
13513#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
13514#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
13515#define ETH_DMABMR_DA_Pos (1U)
13516#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
13517#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
13518#define ETH_DMABMR_SR_Pos (0U)
13519#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
13520#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
13521
13522/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
13523#define ETH_DMATPDR_TPD_Pos (0U)
13524#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
13525#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
13526
13527/* Bit definition for Ethernet DMA Receive Poll Demand Register */
13528#define ETH_DMARPDR_RPD_Pos (0U)
13529#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
13530#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
13531
13532/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
13533#define ETH_DMARDLAR_SRL_Pos (0U)
13534#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
13535#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
13536
13537/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
13538#define ETH_DMATDLAR_STL_Pos (0U)
13539#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
13540#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
13541
13542/* Bit definition for Ethernet DMA Status Register */
13543#define ETH_DMASR_TSTS_Pos (29U)
13544#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
13545#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
13546#define ETH_DMASR_PMTS_Pos (28U)
13547#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
13548#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
13549#define ETH_DMASR_MMCS_Pos (27U)
13550#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
13551#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
13552#define ETH_DMASR_EBS_Pos (23U)
13553#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
13554#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
13555 /* combination with EBS[2:0] for GetFlagStatus function */
13556#define ETH_DMASR_EBS_DescAccess_Pos (25U)
13557#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
13558#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
13559#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
13560#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
13561#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
13562#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
13563#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
13564#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
13565#define ETH_DMASR_TPS_Pos (20U)
13566#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
13567#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
13568#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
13569#define ETH_DMASR_TPS_Fetching_Pos (20U)
13570#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
13571#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
13572#define ETH_DMASR_TPS_Waiting_Pos (21U)
13573#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
13574#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
13575#define ETH_DMASR_TPS_Reading_Pos (20U)
13576#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
13577#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
13578#define ETH_DMASR_TPS_Suspended_Pos (21U)
13579#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
13580#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
13581#define ETH_DMASR_TPS_Closing_Pos (20U)
13582#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
13583#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
13584#define ETH_DMASR_RPS_Pos (17U)
13585#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
13586#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
13587#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
13588#define ETH_DMASR_RPS_Fetching_Pos (17U)
13589#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
13590#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
13591#define ETH_DMASR_RPS_Waiting_Pos (17U)
13592#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
13593#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
13594#define ETH_DMASR_RPS_Suspended_Pos (19U)
13595#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
13596#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
13597#define ETH_DMASR_RPS_Closing_Pos (17U)
13598#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
13599#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
13600#define ETH_DMASR_RPS_Queuing_Pos (17U)
13601#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
13602#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
13603#define ETH_DMASR_NIS_Pos (16U)
13604#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
13605#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
13606#define ETH_DMASR_AIS_Pos (15U)
13607#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
13608#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
13609#define ETH_DMASR_ERS_Pos (14U)
13610#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
13611#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
13612#define ETH_DMASR_FBES_Pos (13U)
13613#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
13614#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
13615#define ETH_DMASR_ETS_Pos (10U)
13616#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
13617#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
13618#define ETH_DMASR_RWTS_Pos (9U)
13619#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
13620#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
13621#define ETH_DMASR_RPSS_Pos (8U)
13622#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
13623#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
13624#define ETH_DMASR_RBUS_Pos (7U)
13625#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
13626#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
13627#define ETH_DMASR_RS_Pos (6U)
13628#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
13629#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
13630#define ETH_DMASR_TUS_Pos (5U)
13631#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
13632#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
13633#define ETH_DMASR_ROS_Pos (4U)
13634#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
13635#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
13636#define ETH_DMASR_TJTS_Pos (3U)
13637#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
13638#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
13639#define ETH_DMASR_TBUS_Pos (2U)
13640#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
13641#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
13642#define ETH_DMASR_TPSS_Pos (1U)
13643#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
13644#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
13645#define ETH_DMASR_TS_Pos (0U)
13646#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
13647#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
13648
13649/* Bit definition for Ethernet DMA Operation Mode Register */
13650#define ETH_DMAOMR_DTCEFD_Pos (26U)
13651#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
13652#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
13653#define ETH_DMAOMR_RSF_Pos (25U)
13654#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
13655#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
13656#define ETH_DMAOMR_DFRF_Pos (24U)
13657#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
13658#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
13659#define ETH_DMAOMR_TSF_Pos (21U)
13660#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
13661#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
13662#define ETH_DMAOMR_FTF_Pos (20U)
13663#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
13664#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
13665#define ETH_DMAOMR_TTC_Pos (14U)
13666#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
13667#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
13668#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
13669#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
13670#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
13671#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
13672#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
13673#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
13674#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
13675#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
13676#define ETH_DMAOMR_ST_Pos (13U)
13677#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
13678#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
13679#define ETH_DMAOMR_FEF_Pos (7U)
13680#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
13681#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
13682#define ETH_DMAOMR_FUGF_Pos (6U)
13683#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
13684#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
13685#define ETH_DMAOMR_RTC_Pos (3U)
13686#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
13687#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
13688#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
13689#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
13690#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
13691#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
13692#define ETH_DMAOMR_OSF_Pos (2U)
13693#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
13694#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
13695#define ETH_DMAOMR_SR_Pos (1U)
13696#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
13697#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
13698
13699/* Bit definition for Ethernet DMA Interrupt Enable Register */
13700#define ETH_DMAIER_NISE_Pos (16U)
13701#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
13702#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
13703#define ETH_DMAIER_AISE_Pos (15U)
13704#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
13705#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
13706#define ETH_DMAIER_ERIE_Pos (14U)
13707#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
13708#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
13709#define ETH_DMAIER_FBEIE_Pos (13U)
13710#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
13711#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
13712#define ETH_DMAIER_ETIE_Pos (10U)
13713#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
13714#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
13715#define ETH_DMAIER_RWTIE_Pos (9U)
13716#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
13717#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
13718#define ETH_DMAIER_RPSIE_Pos (8U)
13719#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
13720#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
13721#define ETH_DMAIER_RBUIE_Pos (7U)
13722#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
13723#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
13724#define ETH_DMAIER_RIE_Pos (6U)
13725#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
13726#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
13727#define ETH_DMAIER_TUIE_Pos (5U)
13728#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
13729#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
13730#define ETH_DMAIER_ROIE_Pos (4U)
13731#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
13732#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
13733#define ETH_DMAIER_TJTIE_Pos (3U)
13734#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
13735#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
13736#define ETH_DMAIER_TBUIE_Pos (2U)
13737#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
13738#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
13739#define ETH_DMAIER_TPSIE_Pos (1U)
13740#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
13741#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
13742#define ETH_DMAIER_TIE_Pos (0U)
13743#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
13744#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
13745
13746/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
13747#define ETH_DMAMFBOCR_OFOC_Pos (28U)
13748#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
13749#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
13750#define ETH_DMAMFBOCR_MFA_Pos (17U)
13751#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
13752#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
13753#define ETH_DMAMFBOCR_OMFC_Pos (16U)
13754#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
13755#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
13756#define ETH_DMAMFBOCR_MFC_Pos (0U)
13757#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
13758#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
13759
13760/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
13761#define ETH_DMACHTDR_HTDAP_Pos (0U)
13762#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
13763#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
13764
13765/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
13766#define ETH_DMACHRDR_HRDAP_Pos (0U)
13767#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
13768#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
13769
13770/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
13771#define ETH_DMACHTBAR_HTBAP_Pos (0U)
13772#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
13773#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
13774
13775/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
13776#define ETH_DMACHRBAR_HRBAP_Pos (0U)
13777#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
13778#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
13779
13780/******************************************************************************/
13781/* */
13782/* USB_OTG */
13783/* */
13784/******************************************************************************/
13785/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
13786#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
13787#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
13788#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
13789#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
13790#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
13791#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
13792#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
13793#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
13794#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
13795#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
13796#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
13797#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
13798#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
13799#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
13800#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
13801#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
13802#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
13803#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
13804#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
13805#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
13806#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
13807#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
13808#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
13809#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
13810#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
13811#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
13812#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
13813#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
13814#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
13815#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk
13817/******************** Bit definition forUSB_OTG_HCFG register ********************/
13818
13819#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
13820#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
13821#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
13822#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
13823#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
13824#define USB_OTG_HCFG_FSLSS_Pos (2U)
13825#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
13826#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
13828/******************** Bit definition for USB_OTG_DCFG register ********************/
13829
13830#define USB_OTG_DCFG_DSPD_Pos (0U)
13831#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
13832#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
13833#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
13834#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
13835#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
13836#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
13837#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
13839#define USB_OTG_DCFG_DAD_Pos (4U)
13840#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
13841#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
13842#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
13843#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
13844#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
13845#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
13846#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
13847#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
13848#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
13850#define USB_OTG_DCFG_PFIVL_Pos (11U)
13851#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
13852#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
13853#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
13854#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
13856#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
13857#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
13858#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
13860#define USB_OTG_DCFG_ERRATIM_Pos (15U)
13861#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
13862#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
13864#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
13865#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13866#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
13867#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13868#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13870/******************** Bit definition for USB_OTG_PCGCR register ********************/
13871#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
13872#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
13873#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
13874#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
13875#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
13876#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
13877#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
13878#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
13879#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
13881/******************** Bit definition for USB_OTG_GOTGINT register ********************/
13882#define USB_OTG_GOTGINT_SEDET_Pos (2U)
13883#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
13884#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
13885#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
13886#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
13887#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
13888#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
13889#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
13890#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
13891#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
13892#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
13893#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
13894#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
13895#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
13896#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
13897#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
13898#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
13899#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
13901/******************** Bit definition for USB_OTG_DCTL register ********************/
13902#define USB_OTG_DCTL_RWUSIG_Pos (0U)
13903#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
13904#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
13905#define USB_OTG_DCTL_SDIS_Pos (1U)
13906#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
13907#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
13908#define USB_OTG_DCTL_GINSTS_Pos (2U)
13909#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
13910#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
13911#define USB_OTG_DCTL_GONSTS_Pos (3U)
13912#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
13913#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
13915#define USB_OTG_DCTL_TCTL_Pos (4U)
13916#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
13917#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
13918#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
13919#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
13920#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
13921#define USB_OTG_DCTL_SGINAK_Pos (7U)
13922#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
13923#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
13924#define USB_OTG_DCTL_CGINAK_Pos (8U)
13925#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
13926#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
13927#define USB_OTG_DCTL_SGONAK_Pos (9U)
13928#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
13929#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
13930#define USB_OTG_DCTL_CGONAK_Pos (10U)
13931#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
13932#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
13933#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
13934#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
13935#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
13937/******************** Bit definition for USB_OTG_HFIR register ********************/
13938#define USB_OTG_HFIR_FRIVL_Pos (0U)
13939#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
13940#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
13942/******************** Bit definition for USB_OTG_HFNUM register ********************/
13943#define USB_OTG_HFNUM_FRNUM_Pos (0U)
13944#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
13945#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
13946#define USB_OTG_HFNUM_FTREM_Pos (16U)
13947#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
13948#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
13950/******************** Bit definition for USB_OTG_DSTS register ********************/
13951#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
13952#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
13953#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
13955#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
13956#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
13957#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
13958#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
13959#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
13960#define USB_OTG_DSTS_EERR_Pos (3U)
13961#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
13962#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
13963#define USB_OTG_DSTS_FNSOF_Pos (8U)
13964#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
13965#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
13967/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
13968#define USB_OTG_GAHBCFG_GINT_Pos (0U)
13969#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
13970#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
13971#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
13972#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13973#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
13974#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13975#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13976#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13977#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13978#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13979#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
13980#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
13981#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
13982#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
13983#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
13984#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
13985#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
13986#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
13987#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
13989/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
13990
13991#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
13992#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13993#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
13994#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13995#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13996#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13997#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
13998#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
13999#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
14000#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
14001#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
14002#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
14003#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
14004#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
14005#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
14006#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
14007#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
14008#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
14009#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
14010#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
14011#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
14012#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
14013#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
14014#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
14015#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
14016#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
14017#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
14018#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
14019#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
14020#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
14021#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
14022#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
14023#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
14024#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
14025#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
14026#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
14027#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
14028#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
14029#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
14030#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
14031#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
14032#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
14033#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
14034#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
14035#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
14036#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
14037#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
14038#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
14039#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
14040#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
14041#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
14042#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
14043#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
14044#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
14045#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
14046#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
14047#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
14048#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
14049#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
14050#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
14051#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
14053/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
14054#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
14055#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
14056#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
14057#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
14058#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
14059#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
14060#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
14061#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
14062#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
14063#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
14064#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
14065#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
14066#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
14067#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
14068#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
14071#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
14072#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14073#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
14074#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14075#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14076#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14077#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14078#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
14079#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
14080#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
14081#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
14082#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
14083#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
14084#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
14086/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
14087#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
14088#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
14089#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
14090#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
14091#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
14092#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
14093#define USB_OTG_DIEPMSK_TOM_Pos (3U)
14094#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
14095#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
14096#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
14097#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
14098#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
14099#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
14100#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
14101#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
14102#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
14103#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
14104#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
14105#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
14106#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
14107#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
14108#define USB_OTG_DIEPMSK_BIM_Pos (9U)
14109#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
14110#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
14112/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
14113#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
14114#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
14115#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
14116#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
14117#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14118#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
14119#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14120#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14121#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14122#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14123#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14124#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14125#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14126#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14128#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
14129#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14130#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
14131#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14132#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14133#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14134#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14135#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14136#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14137#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14138#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14140/******************** Bit definition for USB_OTG_HAINT register ********************/
14141#define USB_OTG_HAINT_HAINT_Pos (0U)
14142#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
14143#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
14145/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
14146#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
14147#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
14148#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
14149#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
14150#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
14151#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
14152#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
14153#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
14154#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
14155#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
14156#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
14157#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
14158#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
14159#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
14160#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
14161#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
14162#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
14163#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
14164#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
14165#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
14166#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
14167#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
14168#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
14169#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
14170#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
14171#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
14172#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
14173#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
14174#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
14175#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
14176#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
14177#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
14178#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
14179#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
14180#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
14181#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
14182/******************** Bit definition for USB_OTG_GINTSTS register ********************/
14183#define USB_OTG_GINTSTS_CMOD_Pos (0U)
14184#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
14185#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
14186#define USB_OTG_GINTSTS_MMIS_Pos (1U)
14187#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
14188#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
14189#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
14190#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
14191#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
14192#define USB_OTG_GINTSTS_SOF_Pos (3U)
14193#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
14194#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
14195#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
14196#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
14197#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
14198#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
14199#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
14200#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
14201#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
14202#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
14203#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
14204#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
14205#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
14206#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
14207#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
14208#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
14209#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
14210#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
14211#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
14212#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
14213#define USB_OTG_GINTSTS_USBRST_Pos (12U)
14214#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
14215#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
14216#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
14217#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
14218#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
14219#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
14220#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
14221#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
14222#define USB_OTG_GINTSTS_EOPF_Pos (15U)
14223#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
14224#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
14225#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
14226#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
14227#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
14228#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
14229#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
14230#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
14231#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
14232#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
14233#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
14234#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
14235#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
14236#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
14237#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
14238#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
14239#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
14240#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
14241#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
14242#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
14243#define USB_OTG_GINTSTS_HCINT_Pos (25U)
14244#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
14245#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
14246#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
14247#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
14248#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
14249#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
14250#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
14251#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
14252#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
14253#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
14254#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
14255#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
14256#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
14257#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
14258#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
14259#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
14260#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
14262/******************** Bit definition for USB_OTG_GINTMSK register ********************/
14263#define USB_OTG_GINTMSK_MMISM_Pos (1U)
14264#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
14265#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
14266#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
14267#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
14268#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
14269#define USB_OTG_GINTMSK_SOFM_Pos (3U)
14270#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
14271#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
14272#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
14273#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
14274#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
14275#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
14276#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
14277#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
14278#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
14279#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
14280#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
14281#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
14282#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
14283#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
14284#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
14285#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
14286#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
14287#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
14288#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
14289#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
14290#define USB_OTG_GINTMSK_USBRST_Pos (12U)
14291#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
14292#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
14293#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
14294#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
14295#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
14296#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
14297#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
14298#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
14299#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
14300#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
14301#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
14302#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
14303#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
14304#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
14305#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
14306#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
14307#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
14308#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
14309#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
14310#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
14311#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
14312#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
14313#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
14314#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
14315#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
14316#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
14317#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
14318#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
14319#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
14320#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
14321#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
14322#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
14323#define USB_OTG_GINTMSK_HCIM_Pos (25U)
14324#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
14325#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
14326#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
14327#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
14328#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
14329#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
14330#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
14331#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
14332#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
14333#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
14334#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
14335#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
14336#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
14337#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
14338#define USB_OTG_GINTMSK_WUIM_Pos (31U)
14339#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
14340#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
14342/******************** Bit definition for USB_OTG_DAINT register ********************/
14343#define USB_OTG_DAINT_IEPINT_Pos (0U)
14344#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
14345#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
14346#define USB_OTG_DAINT_OEPINT_Pos (16U)
14347#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
14348#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
14350/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
14351#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
14352#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
14353#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
14355/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
14356#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
14357#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
14358#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
14359#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
14360#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
14361#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
14362#define USB_OTG_GRXSTSP_DPID_Pos (15U)
14363#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
14364#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
14365#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
14366#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
14367#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
14369/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
14370#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
14371#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
14372#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
14373#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
14374#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
14375#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
14377/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
14378#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
14379#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
14380#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
14382/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
14383#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
14384#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
14385#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
14387/******************** Bit definition for OTG register ********************/
14388#define USB_OTG_NPTXFSA_Pos (0U)
14389#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
14390#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
14391#define USB_OTG_NPTXFD_Pos (16U)
14392#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
14393#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
14394#define USB_OTG_TX0FSA_Pos (0U)
14395#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
14396#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
14397#define USB_OTG_TX0FD_Pos (16U)
14398#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
14399#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
14401/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
14402#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
14403#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
14404#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
14406/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
14407#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
14408#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
14409#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
14411#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
14412#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14413#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
14414#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14415#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14416#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14417#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14418#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14419#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14420#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14421#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14423#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
14424#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14425#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
14426#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14427#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14428#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14429#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14430#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14431#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14432#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14434/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
14435#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
14436#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
14437#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
14438#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
14439#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
14440#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
14442#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
14443#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14444#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
14445#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14446#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14447#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14448#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14449#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14450#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14451#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14452#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14453#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14454#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
14455#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
14456#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
14458#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
14459#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14460#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
14461#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14462#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14463#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14464#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14465#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14466#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14467#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14468#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14469#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14470#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
14471#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
14472#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
14474/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
14475#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
14476#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
14477#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
14479/******************** Bit definition for USB_OTG_DEACHINT register ********************/
14480#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
14481#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
14482#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
14483#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
14484#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
14485#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
14487/******************** Bit definition for USB_OTG_GCCFG register ********************/
14488#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
14489#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
14490#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
14491#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
14492#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
14493#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk
14494#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
14495#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
14496#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk
14497#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
14498#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
14499#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk
14500#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
14501#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
14502#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk
14503#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
14504#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
14505#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk
14507/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
14508#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
14509#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
14510#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
14511#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
14512#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
14513#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
14515/******************** Bit definition for USB_OTG_CID register ********************/
14516#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
14517#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
14518#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
14520/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
14521#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
14522#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
14523#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
14524#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
14525#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
14526#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
14527#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
14528#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
14529#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
14530#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
14531#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
14532#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
14533#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
14534#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
14535#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
14536#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
14537#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
14538#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
14539#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
14540#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
14541#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
14542#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
14543#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
14544#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
14545#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
14546#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
14547#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
14549/******************** Bit definition for USB_OTG_HPRT register ********************/
14550#define USB_OTG_HPRT_PCSTS_Pos (0U)
14551#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
14552#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
14553#define USB_OTG_HPRT_PCDET_Pos (1U)
14554#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
14555#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
14556#define USB_OTG_HPRT_PENA_Pos (2U)
14557#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
14558#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
14559#define USB_OTG_HPRT_PENCHNG_Pos (3U)
14560#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
14561#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
14562#define USB_OTG_HPRT_POCA_Pos (4U)
14563#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
14564#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
14565#define USB_OTG_HPRT_POCCHNG_Pos (5U)
14566#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
14567#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
14568#define USB_OTG_HPRT_PRES_Pos (6U)
14569#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
14570#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
14571#define USB_OTG_HPRT_PSUSP_Pos (7U)
14572#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
14573#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
14574#define USB_OTG_HPRT_PRST_Pos (8U)
14575#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
14576#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
14578#define USB_OTG_HPRT_PLSTS_Pos (10U)
14579#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
14580#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
14581#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
14582#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
14583#define USB_OTG_HPRT_PPWR_Pos (12U)
14584#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
14585#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
14587#define USB_OTG_HPRT_PTCTL_Pos (13U)
14588#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
14589#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
14590#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
14591#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
14592#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
14593#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
14595#define USB_OTG_HPRT_PSPD_Pos (17U)
14596#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
14597#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
14598#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
14599#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
14601/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
14602#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
14603#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
14604#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
14605#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
14606#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
14607#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
14608#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
14609#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
14610#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
14611#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
14612#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
14613#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
14614#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
14615#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
14616#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
14617#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
14618#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
14619#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
14620#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
14621#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
14622#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
14623#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
14624#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
14625#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
14626#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
14627#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
14628#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
14629#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
14630#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
14631#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
14632#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
14633#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
14634#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
14636/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
14637#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
14638#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
14639#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
14640#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
14641#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
14642#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
14644/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
14645#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
14646#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
14647#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
14648#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
14649#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
14650#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
14651#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
14652#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
14653#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
14654#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
14655#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
14656#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
14658#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
14659#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14660#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
14661#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14662#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14663#define USB_OTG_DIEPCTL_STALL_Pos (21U)
14664#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
14665#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
14667#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
14668#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14669#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
14670#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14671#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14672#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14673#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14674#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
14675#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
14676#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
14677#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
14678#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
14679#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
14680#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
14681#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
14682#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
14683#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
14684#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
14685#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
14686#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
14687#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
14688#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
14689#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
14690#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
14691#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
14693/******************** Bit definition for USB_OTG_HCCHAR register ********************/
14694#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
14695#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
14696#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
14698#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
14699#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
14700#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
14701#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
14702#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
14703#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
14704#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
14705#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
14706#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
14707#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
14708#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
14709#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
14710#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
14712#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
14713#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
14714#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
14715#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
14716#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
14718#define USB_OTG_HCCHAR_MC_Pos (20U)
14719#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
14720#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
14721#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
14722#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
14724#define USB_OTG_HCCHAR_DAD_Pos (22U)
14725#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
14726#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
14727#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
14728#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
14729#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
14730#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
14731#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
14732#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
14733#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
14734#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
14735#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
14736#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
14737#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
14738#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
14739#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
14740#define USB_OTG_HCCHAR_CHENA_Pos (31U)
14741#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
14742#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
14744/******************** Bit definition for USB_OTG_HCSPLT register ********************/
14745
14746#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
14747#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
14748#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
14749#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14750#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14751#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14752#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14753#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14754#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14755#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14757#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
14758#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
14759#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
14760#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14761#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14762#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14763#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14764#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14765#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14766#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14768#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
14769#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14770#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
14771#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14772#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14773#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
14774#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
14775#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
14776#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
14777#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
14778#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
14780/******************** Bit definition for USB_OTG_HCINT register ********************/
14781#define USB_OTG_HCINT_XFRC_Pos (0U)
14782#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
14783#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
14784#define USB_OTG_HCINT_CHH_Pos (1U)
14785#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
14786#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
14787#define USB_OTG_HCINT_AHBERR_Pos (2U)
14788#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
14789#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
14790#define USB_OTG_HCINT_STALL_Pos (3U)
14791#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
14792#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
14793#define USB_OTG_HCINT_NAK_Pos (4U)
14794#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
14795#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
14796#define USB_OTG_HCINT_ACK_Pos (5U)
14797#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
14798#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
14799#define USB_OTG_HCINT_NYET_Pos (6U)
14800#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
14801#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
14802#define USB_OTG_HCINT_TXERR_Pos (7U)
14803#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
14804#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
14805#define USB_OTG_HCINT_BBERR_Pos (8U)
14806#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
14807#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
14808#define USB_OTG_HCINT_FRMOR_Pos (9U)
14809#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
14810#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
14811#define USB_OTG_HCINT_DTERR_Pos (10U)
14812#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
14813#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
14815/******************** Bit definition for USB_OTG_DIEPINT register ********************/
14816#define USB_OTG_DIEPINT_XFRC_Pos (0U)
14817#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
14818#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
14819#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
14820#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
14821#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
14822#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
14823#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
14824#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
14825#define USB_OTG_DIEPINT_TOC_Pos (3U)
14826#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
14827#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
14828#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
14829#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
14830#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
14831#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
14832#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
14833#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
14834#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
14835#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
14836#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
14837#define USB_OTG_DIEPINT_TXFE_Pos (7U)
14838#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
14839#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
14840#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
14841#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
14842#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
14843#define USB_OTG_DIEPINT_BNA_Pos (9U)
14844#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
14845#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
14846#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
14847#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
14848#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
14849#define USB_OTG_DIEPINT_BERR_Pos (12U)
14850#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
14851#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
14852#define USB_OTG_DIEPINT_NAK_Pos (13U)
14853#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
14854#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
14856/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
14857#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
14858#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
14859#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
14860#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
14861#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
14862#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
14863#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
14864#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
14865#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
14866#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
14867#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
14868#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
14869#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
14870#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
14871#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
14872#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
14873#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
14874#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
14875#define USB_OTG_HCINTMSK_NYET_Pos (6U)
14876#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
14877#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
14878#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
14879#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
14880#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
14881#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
14882#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
14883#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
14884#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
14885#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
14886#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
14887#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
14888#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
14889#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
14891/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
14892
14893#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
14894#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
14895#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
14896#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
14897#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
14898#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
14899#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
14900#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
14901#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
14902/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
14903#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
14904#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
14905#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
14906#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
14907#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
14908#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
14909#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
14910#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
14911#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
14912#define USB_OTG_HCTSIZ_DPID_Pos (29U)
14913#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
14914#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
14915#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
14916#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
14918/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
14919#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
14920#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
14921#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
14923/******************** Bit definition for USB_OTG_HCDMA register ********************/
14924#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
14925#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
14926#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
14928/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
14929#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
14930#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
14931#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
14933/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
14934#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
14935#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
14936#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
14937#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
14938#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
14939#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
14941/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
14942
14943#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
14944#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
14945#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
14946#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
14947#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
14948#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
14949#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
14950#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
14951#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
14952#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
14953#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
14954#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
14955#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
14956#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
14957#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
14958#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
14959#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14960#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
14961#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14962#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14963#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
14964#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
14965#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
14966#define USB_OTG_DOEPCTL_STALL_Pos (21U)
14967#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
14968#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
14969#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
14970#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
14971#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
14972#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
14973#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
14974#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
14975#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
14976#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
14977#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
14978#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
14979#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
14980#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
14982/******************** Bit definition for USB_OTG_DOEPINT register ********************/
14983#define USB_OTG_DOEPINT_XFRC_Pos (0U)
14984#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
14985#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
14986#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
14987#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
14988#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
14989#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
14990#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
14991#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
14992#define USB_OTG_DOEPINT_STUP_Pos (3U)
14993#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
14994#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
14995#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
14996#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
14997#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
14998#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
14999#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
15000#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
15001#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
15002#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
15003#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
15004#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
15005#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
15006#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
15007#define USB_OTG_DOEPINT_NAK_Pos (13U)
15008#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
15009#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
15010#define USB_OTG_DOEPINT_NYET_Pos (14U)
15011#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
15012#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
15013#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
15014#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
15015#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
15016/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
15017
15018#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
15019#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
15020#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
15021#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
15022#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
15023#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
15025#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
15026#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15027#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
15028#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15029#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15031/******************** Bit definition for PCGCCTL register ********************/
15032#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
15033#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
15034#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
15035#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
15036#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
15037#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
15038#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
15039#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
15040#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
15042/* Legacy define */
15043/******************** Bit definition for OTG register ********************/
15044#define USB_OTG_CHNUM_Pos (0U)
15045#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
15046#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
15047#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
15048#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
15049#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
15050#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
15051#define USB_OTG_BCNT_Pos (4U)
15052#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
15053#define USB_OTG_BCNT USB_OTG_BCNT_Msk
15055#define USB_OTG_DPID_Pos (15U)
15056#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
15057#define USB_OTG_DPID USB_OTG_DPID_Msk
15058#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
15059#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
15061#define USB_OTG_PKTSTS_Pos (17U)
15062#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
15063#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
15064#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
15065#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
15066#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
15067#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
15069#define USB_OTG_EPNUM_Pos (0U)
15070#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
15071#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
15072#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
15073#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
15074#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
15075#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
15077#define USB_OTG_FRMNUM_Pos (21U)
15078#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
15079#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
15080#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
15081#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
15082#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
15083#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
15096/******************************* ADC Instances ********************************/
15097#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
15098 ((INSTANCE) == ADC2) || \
15099 ((INSTANCE) == ADC3))
15100
15101#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
15102
15103#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
15104
15105/******************************* CAN Instances ********************************/
15106#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
15107 ((INSTANCE) == CAN2))
15108/******************************* CRC Instances ********************************/
15109#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
15110
15111/******************************* DAC Instances ********************************/
15112#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
15113
15114/******************************* DCMI Instances *******************************/
15115#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
15116
15117/******************************** DMA Instances *******************************/
15118#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
15119 ((INSTANCE) == DMA1_Stream1) || \
15120 ((INSTANCE) == DMA1_Stream2) || \
15121 ((INSTANCE) == DMA1_Stream3) || \
15122 ((INSTANCE) == DMA1_Stream4) || \
15123 ((INSTANCE) == DMA1_Stream5) || \
15124 ((INSTANCE) == DMA1_Stream6) || \
15125 ((INSTANCE) == DMA1_Stream7) || \
15126 ((INSTANCE) == DMA2_Stream0) || \
15127 ((INSTANCE) == DMA2_Stream1) || \
15128 ((INSTANCE) == DMA2_Stream2) || \
15129 ((INSTANCE) == DMA2_Stream3) || \
15130 ((INSTANCE) == DMA2_Stream4) || \
15131 ((INSTANCE) == DMA2_Stream5) || \
15132 ((INSTANCE) == DMA2_Stream6) || \
15133 ((INSTANCE) == DMA2_Stream7))
15134
15135/******************************* GPIO Instances *******************************/
15136#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
15137 ((INSTANCE) == GPIOB) || \
15138 ((INSTANCE) == GPIOC) || \
15139 ((INSTANCE) == GPIOD) || \
15140 ((INSTANCE) == GPIOE) || \
15141 ((INSTANCE) == GPIOF) || \
15142 ((INSTANCE) == GPIOG) || \
15143 ((INSTANCE) == GPIOH) || \
15144 ((INSTANCE) == GPIOI))
15145
15146/******************************** I2C Instances *******************************/
15147#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15148 ((INSTANCE) == I2C2) || \
15149 ((INSTANCE) == I2C3))
15150
15151/******************************* SMBUS Instances ******************************/
15152#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
15153
15154/******************************** I2S Instances *******************************/
15155
15156#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
15157 ((INSTANCE) == SPI3))
15158
15159/*************************** I2S Extended Instances ***************************/
15160#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
15161 ((INSTANCE) == I2S3ext))
15162/* Legacy Defines */
15163#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
15164
15165/******************************* RNG Instances ********************************/
15166#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
15167
15168/****************************** RTC Instances *********************************/
15169#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
15170
15171
15172/******************************** SPI Instances *******************************/
15173#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15174 ((INSTANCE) == SPI2) || \
15175 ((INSTANCE) == SPI3))
15176
15177
15178/****************** TIM Instances : All supported instances *******************/
15179#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15180 ((INSTANCE) == TIM2) || \
15181 ((INSTANCE) == TIM3) || \
15182 ((INSTANCE) == TIM4) || \
15183 ((INSTANCE) == TIM5) || \
15184 ((INSTANCE) == TIM6) || \
15185 ((INSTANCE) == TIM7) || \
15186 ((INSTANCE) == TIM8) || \
15187 ((INSTANCE) == TIM9) || \
15188 ((INSTANCE) == TIM10)|| \
15189 ((INSTANCE) == TIM11)|| \
15190 ((INSTANCE) == TIM12)|| \
15191 ((INSTANCE) == TIM13)|| \
15192 ((INSTANCE) == TIM14))
15193
15194/************* TIM Instances : at least 1 capture/compare channel *************/
15195#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15196 ((INSTANCE) == TIM2) || \
15197 ((INSTANCE) == TIM3) || \
15198 ((INSTANCE) == TIM4) || \
15199 ((INSTANCE) == TIM5) || \
15200 ((INSTANCE) == TIM8) || \
15201 ((INSTANCE) == TIM9) || \
15202 ((INSTANCE) == TIM10) || \
15203 ((INSTANCE) == TIM11) || \
15204 ((INSTANCE) == TIM12) || \
15205 ((INSTANCE) == TIM13) || \
15206 ((INSTANCE) == TIM14))
15207
15208/************ TIM Instances : at least 2 capture/compare channels *************/
15209#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15210 ((INSTANCE) == TIM2) || \
15211 ((INSTANCE) == TIM3) || \
15212 ((INSTANCE) == TIM4) || \
15213 ((INSTANCE) == TIM5) || \
15214 ((INSTANCE) == TIM8) || \
15215 ((INSTANCE) == TIM9) || \
15216 ((INSTANCE) == TIM12))
15217
15218/************ TIM Instances : at least 3 capture/compare channels *************/
15219#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15220 ((INSTANCE) == TIM2) || \
15221 ((INSTANCE) == TIM3) || \
15222 ((INSTANCE) == TIM4) || \
15223 ((INSTANCE) == TIM5) || \
15224 ((INSTANCE) == TIM8))
15225
15226/************ TIM Instances : at least 4 capture/compare channels *************/
15227#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15228 ((INSTANCE) == TIM2) || \
15229 ((INSTANCE) == TIM3) || \
15230 ((INSTANCE) == TIM4) || \
15231 ((INSTANCE) == TIM5) || \
15232 ((INSTANCE) == TIM8))
15233
15234/******************** TIM Instances : Advanced-control timers *****************/
15235#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15236 ((INSTANCE) == TIM8))
15237
15238/******************* TIM Instances : Timer input XOR function *****************/
15239#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15240 ((INSTANCE) == TIM2) || \
15241 ((INSTANCE) == TIM3) || \
15242 ((INSTANCE) == TIM4) || \
15243 ((INSTANCE) == TIM5) || \
15244 ((INSTANCE) == TIM8))
15245
15246/****************** TIM Instances : DMA requests generation (UDE) *************/
15247#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15248 ((INSTANCE) == TIM2) || \
15249 ((INSTANCE) == TIM3) || \
15250 ((INSTANCE) == TIM4) || \
15251 ((INSTANCE) == TIM5) || \
15252 ((INSTANCE) == TIM6) || \
15253 ((INSTANCE) == TIM7) || \
15254 ((INSTANCE) == TIM8))
15255
15256/************ TIM Instances : DMA requests generation (CCxDE) *****************/
15257#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15258 ((INSTANCE) == TIM2) || \
15259 ((INSTANCE) == TIM3) || \
15260 ((INSTANCE) == TIM4) || \
15261 ((INSTANCE) == TIM5) || \
15262 ((INSTANCE) == TIM8))
15263
15264/************ TIM Instances : DMA requests generation (COMDE) *****************/
15265#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15266 ((INSTANCE) == TIM2) || \
15267 ((INSTANCE) == TIM3) || \
15268 ((INSTANCE) == TIM4) || \
15269 ((INSTANCE) == TIM5) || \
15270 ((INSTANCE) == TIM8))
15271
15272/******************** TIM Instances : DMA burst feature ***********************/
15273#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15274 ((INSTANCE) == TIM2) || \
15275 ((INSTANCE) == TIM3) || \
15276 ((INSTANCE) == TIM4) || \
15277 ((INSTANCE) == TIM5) || \
15278 ((INSTANCE) == TIM8))
15279
15280/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
15281#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15282 ((INSTANCE) == TIM2) || \
15283 ((INSTANCE) == TIM3) || \
15284 ((INSTANCE) == TIM4) || \
15285 ((INSTANCE) == TIM5) || \
15286 ((INSTANCE) == TIM6) || \
15287 ((INSTANCE) == TIM7) || \
15288 ((INSTANCE) == TIM8))
15289
15290/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15291#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15292 ((INSTANCE) == TIM2) || \
15293 ((INSTANCE) == TIM3) || \
15294 ((INSTANCE) == TIM4) || \
15295 ((INSTANCE) == TIM5) || \
15296 ((INSTANCE) == TIM8) || \
15297 ((INSTANCE) == TIM9) || \
15298 ((INSTANCE) == TIM12))
15299/********************** TIM Instances : 32 bit Counter ************************/
15300#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
15301 ((INSTANCE) == TIM5))
15302
15303/***************** TIM Instances : external trigger input available ************/
15304#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15305 ((INSTANCE) == TIM2) || \
15306 ((INSTANCE) == TIM3) || \
15307 ((INSTANCE) == TIM4) || \
15308 ((INSTANCE) == TIM5) || \
15309 ((INSTANCE) == TIM8))
15310
15311/****************** TIM Instances : remapping capability **********************/
15312#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
15313 ((INSTANCE) == TIM5) || \
15314 ((INSTANCE) == TIM11))
15315
15316/******************* TIM Instances : output(s) available **********************/
15317#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15318 ((((INSTANCE) == TIM1) && \
15319 (((CHANNEL) == TIM_CHANNEL_1) || \
15320 ((CHANNEL) == TIM_CHANNEL_2) || \
15321 ((CHANNEL) == TIM_CHANNEL_3) || \
15322 ((CHANNEL) == TIM_CHANNEL_4))) \
15323 || \
15324 (((INSTANCE) == TIM2) && \
15325 (((CHANNEL) == TIM_CHANNEL_1) || \
15326 ((CHANNEL) == TIM_CHANNEL_2) || \
15327 ((CHANNEL) == TIM_CHANNEL_3) || \
15328 ((CHANNEL) == TIM_CHANNEL_4))) \
15329 || \
15330 (((INSTANCE) == TIM3) && \
15331 (((CHANNEL) == TIM_CHANNEL_1) || \
15332 ((CHANNEL) == TIM_CHANNEL_2) || \
15333 ((CHANNEL) == TIM_CHANNEL_3) || \
15334 ((CHANNEL) == TIM_CHANNEL_4))) \
15335 || \
15336 (((INSTANCE) == TIM4) && \
15337 (((CHANNEL) == TIM_CHANNEL_1) || \
15338 ((CHANNEL) == TIM_CHANNEL_2) || \
15339 ((CHANNEL) == TIM_CHANNEL_3) || \
15340 ((CHANNEL) == TIM_CHANNEL_4))) \
15341 || \
15342 (((INSTANCE) == TIM5) && \
15343 (((CHANNEL) == TIM_CHANNEL_1) || \
15344 ((CHANNEL) == TIM_CHANNEL_2) || \
15345 ((CHANNEL) == TIM_CHANNEL_3) || \
15346 ((CHANNEL) == TIM_CHANNEL_4))) \
15347 || \
15348 (((INSTANCE) == TIM8) && \
15349 (((CHANNEL) == TIM_CHANNEL_1) || \
15350 ((CHANNEL) == TIM_CHANNEL_2) || \
15351 ((CHANNEL) == TIM_CHANNEL_3) || \
15352 ((CHANNEL) == TIM_CHANNEL_4))) \
15353 || \
15354 (((INSTANCE) == TIM9) && \
15355 (((CHANNEL) == TIM_CHANNEL_1) || \
15356 ((CHANNEL) == TIM_CHANNEL_2))) \
15357 || \
15358 (((INSTANCE) == TIM10) && \
15359 (((CHANNEL) == TIM_CHANNEL_1))) \
15360 || \
15361 (((INSTANCE) == TIM11) && \
15362 (((CHANNEL) == TIM_CHANNEL_1))) \
15363 || \
15364 (((INSTANCE) == TIM12) && \
15365 (((CHANNEL) == TIM_CHANNEL_1) || \
15366 ((CHANNEL) == TIM_CHANNEL_2))) \
15367 || \
15368 (((INSTANCE) == TIM13) && \
15369 (((CHANNEL) == TIM_CHANNEL_1))) \
15370 || \
15371 (((INSTANCE) == TIM14) && \
15372 (((CHANNEL) == TIM_CHANNEL_1))))
15373
15374/************ TIM Instances : complementary output(s) available ***************/
15375#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15376 ((((INSTANCE) == TIM1) && \
15377 (((CHANNEL) == TIM_CHANNEL_1) || \
15378 ((CHANNEL) == TIM_CHANNEL_2) || \
15379 ((CHANNEL) == TIM_CHANNEL_3))) \
15380 || \
15381 (((INSTANCE) == TIM8) && \
15382 (((CHANNEL) == TIM_CHANNEL_1) || \
15383 ((CHANNEL) == TIM_CHANNEL_2) || \
15384 ((CHANNEL) == TIM_CHANNEL_3))))
15385
15386/****************** TIM Instances : supporting counting mode selection ********/
15387#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15388 ((INSTANCE) == TIM2) || \
15389 ((INSTANCE) == TIM3) || \
15390 ((INSTANCE) == TIM4) || \
15391 ((INSTANCE) == TIM5) || \
15392 ((INSTANCE) == TIM8))
15393
15394/****************** TIM Instances : supporting clock division *****************/
15395#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15396 ((INSTANCE) == TIM2) || \
15397 ((INSTANCE) == TIM3) || \
15398 ((INSTANCE) == TIM4) || \
15399 ((INSTANCE) == TIM5) || \
15400 ((INSTANCE) == TIM8) || \
15401 ((INSTANCE) == TIM9) || \
15402 ((INSTANCE) == TIM10)|| \
15403 ((INSTANCE) == TIM11)|| \
15404 ((INSTANCE) == TIM12)|| \
15405 ((INSTANCE) == TIM13)|| \
15406 ((INSTANCE) == TIM14))
15407
15408/****************** TIM Instances : supporting commutation event generation ***/
15409#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
15410 ((INSTANCE) == TIM8))
15411
15412
15413/****************** TIM Instances : supporting OCxREF clear *******************/
15414#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15415 ((INSTANCE) == TIM2) || \
15416 ((INSTANCE) == TIM3) || \
15417 ((INSTANCE) == TIM4) || \
15418 ((INSTANCE) == TIM5) || \
15419 ((INSTANCE) == TIM8))
15420
15421/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15422#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15423 ((INSTANCE) == TIM2) || \
15424 ((INSTANCE) == TIM3) || \
15425 ((INSTANCE) == TIM4) || \
15426 ((INSTANCE) == TIM5) || \
15427 ((INSTANCE) == TIM8) || \
15428 ((INSTANCE) == TIM9) || \
15429 ((INSTANCE) == TIM12))
15430
15431/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15432#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15433 ((INSTANCE) == TIM2) || \
15434 ((INSTANCE) == TIM3) || \
15435 ((INSTANCE) == TIM4) || \
15436 ((INSTANCE) == TIM5) || \
15437 ((INSTANCE) == TIM8))
15438
15439/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
15440#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15441 ((INSTANCE) == TIM2) || \
15442 ((INSTANCE) == TIM3) || \
15443 ((INSTANCE) == TIM4) || \
15444 ((INSTANCE) == TIM5) || \
15445 ((INSTANCE) == TIM8) || \
15446 ((INSTANCE) == TIM9) || \
15447 ((INSTANCE) == TIM12))
15448
15449/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
15450#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15451 ((INSTANCE) == TIM2) || \
15452 ((INSTANCE) == TIM3) || \
15453 ((INSTANCE) == TIM4) || \
15454 ((INSTANCE) == TIM5) || \
15455 ((INSTANCE) == TIM8) || \
15456 ((INSTANCE) == TIM9) || \
15457 ((INSTANCE) == TIM12))
15458
15459/****************** TIM Instances : supporting repetition counter *************/
15460#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15461 ((INSTANCE) == TIM8))
15462
15463/****************** TIM Instances : supporting encoder interface **************/
15464#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15465 ((INSTANCE) == TIM2) || \
15466 ((INSTANCE) == TIM3) || \
15467 ((INSTANCE) == TIM4) || \
15468 ((INSTANCE) == TIM5) || \
15469 ((INSTANCE) == TIM8) || \
15470 ((INSTANCE) == TIM9) || \
15471 ((INSTANCE) == TIM12))
15472/****************** TIM Instances : supporting Hall sensor interface **********/
15473#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15474 ((INSTANCE) == TIM2) || \
15475 ((INSTANCE) == TIM3) || \
15476 ((INSTANCE) == TIM4) || \
15477 ((INSTANCE) == TIM5) || \
15478 ((INSTANCE) == TIM8))
15479/****************** TIM Instances : supporting the break function *************/
15480#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15481 ((INSTANCE) == TIM8))
15482
15483/******************** USART Instances : Synchronous mode **********************/
15484#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15485 ((INSTANCE) == USART2) || \
15486 ((INSTANCE) == USART3) || \
15487 ((INSTANCE) == USART6))
15488
15489/******************** UART Instances : Half-Duplex mode **********************/
15490#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15491 ((INSTANCE) == USART2) || \
15492 ((INSTANCE) == USART3) || \
15493 ((INSTANCE) == UART4) || \
15494 ((INSTANCE) == UART5) || \
15495 ((INSTANCE) == USART6))
15496
15497/* Legacy defines */
15498#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15499
15500/****************** UART Instances : Hardware Flow control ********************/
15501#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15502 ((INSTANCE) == USART2) || \
15503 ((INSTANCE) == USART3) || \
15504 ((INSTANCE) == USART6))
15505/******************** UART Instances : LIN mode **********************/
15506#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15507
15508/********************* UART Instances : Smart card mode ***********************/
15509#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15510 ((INSTANCE) == USART2) || \
15511 ((INSTANCE) == USART3) || \
15512 ((INSTANCE) == USART6))
15513
15514/*********************** UART Instances : IRDA mode ***************************/
15515#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15516 ((INSTANCE) == USART2) || \
15517 ((INSTANCE) == USART3) || \
15518 ((INSTANCE) == UART4) || \
15519 ((INSTANCE) == UART5) || \
15520 ((INSTANCE) == USART6))
15521
15522
15523/*********************** PCD Instances ****************************************/
15524#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15525 ((INSTANCE) == USB_OTG_HS))
15526
15527/*********************** HCD Instances ****************************************/
15528#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15529 ((INSTANCE) == USB_OTG_HS))
15530
15531/****************************** SDIO Instances ********************************/
15532#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15533
15534/****************************** IWDG Instances ********************************/
15535#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
15536
15537/****************************** WWDG Instances ********************************/
15538#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15539
15540/****************************** USB Exported Constants ************************/
15541#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
15542#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
15543#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
15544#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
15545
15546/*
15547 * @brief Specific devices reset values definitions
15548 */
15549#define RCC_PLLCFGR_RST_VALUE 0x24003010U
15550#define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
15551
15552#define RCC_MAX_FREQUENCY 168000000U
15553#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
15554#define RCC_MAX_FREQUENCY_SCALE2 144000000U
15555#define RCC_PLLVCO_OUTPUT_MIN 100000000U
15556#define RCC_PLLVCO_INPUT_MIN 950000U
15557#define RCC_PLLVCO_INPUT_MAX 2100000U
15558#define RCC_PLLVCO_OUTPUT_MAX 432000000U
15560#define RCC_PLLN_MIN_VALUE 50U
15561#define RCC_PLLN_MAX_VALUE 432U
15562
15563#define FLASH_SCALE1_LATENCY1_FREQ 30000000U
15564#define FLASH_SCALE1_LATENCY2_FREQ 60000000U
15565#define FLASH_SCALE1_LATENCY3_FREQ 90000000U
15566#define FLASH_SCALE1_LATENCY4_FREQ 120000000U
15567#define FLASH_SCALE1_LATENCY5_FREQ 150000000U
15569#define FLASH_SCALE2_LATENCY1_FREQ 30000000U
15570#define FLASH_SCALE2_LATENCY2_FREQ 60000000U
15571#define FLASH_SCALE2_LATENCY3_FREQ 90000000U
15572#define FLASH_SCALE2_LATENCY4_FREQ 12000000U
15574#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
15575#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
15576#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
15577#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
15578/******************************************************************************/
15579/* For a painless codes migration between the STM32F4xx device product */
15580/* lines, the aliases defined below are put in place to overcome the */
15581/* differences in the interrupt handlers and IRQn definitions. */
15582/* No need to update developed interrupt code when moving across */
15583/* product lines within the same STM32F4 Family */
15584/******************************************************************************/
15585/* Aliases for __IRQn */
15586#define FMC_IRQn FSMC_IRQn
15587
15588/* Aliases for __IRQHandler */
15589#define FMC_IRQHandler FSMC_IRQHandler
15590
15603#ifdef __cplusplus
15604}
15605#endif /* __cplusplus */
15606
15607#endif /* __STM32F407xx_H */
__IO
#define __IO
Definition core_cm3.h:170
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
PMC
#define PMC
Definition MK60D10.h:8809
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f407xx.h:66
PendSV_IRQn
@ PendSV_IRQn
Definition stm32f407xx.h:74
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition stm32f407xx.h:139
EXTI2_IRQn
@ EXTI2_IRQn
Definition stm32f407xx.h:85
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition stm32f407xx.h:90
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition stm32f407xx.h:99
SDIO_IRQn
@ SDIO_IRQn
Definition stm32f407xx.h:126
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition stm32f407xx.h:80
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition stm32f407xx.h:152
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition stm32f407xx.h:133
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition stm32f407xx.h:146
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition stm32f407xx.h:109
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition stm32f407xx.h:110
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition stm32f407xx.h:69
TIM4_IRQn
@ TIM4_IRQn
Definition stm32f407xx.h:107
TIM2_IRQn
@ TIM2_IRQn
Definition stm32f407xx.h:105
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition stm32f407xx.h:147
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition stm32f407xx.h:120
USART2_IRQn
@ USART2_IRQn
Definition stm32f407xx.h:115
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition stm32f407xx.h:136
SVCall_IRQn
@ SVCall_IRQn
Definition stm32f407xx.h:72
ADC_IRQn
@ ADC_IRQn
Definition stm32f407xx.h:95
SPI3_IRQn
@ SPI3_IRQn
Definition stm32f407xx.h:128
SPI2_IRQn
@ SPI2_IRQn
Definition stm32f407xx.h:113
TIM7_IRQn
@ TIM7_IRQn
Definition stm32f407xx.h:132
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition stm32f407xx.h:143
RCC_IRQn
@ RCC_IRQn
Definition stm32f407xx.h:82
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition stm32f407xx.h:131
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition stm32f407xx.h:151
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition stm32f407xx.h:111
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition stm32f407xx.h:123
UsageFault_IRQn
@ UsageFault_IRQn
Definition stm32f407xx.h:71
SysTick_IRQn
@ SysTick_IRQn
Definition stm32f407xx.h:75
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition stm32f407xx.h:150
FSMC_IRQn
@ FSMC_IRQn
Definition stm32f407xx.h:125
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition stm32f407xx.h:149
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition stm32f407xx.h:141
BusFault_IRQn
@ BusFault_IRQn
Definition stm32f407xx.h:70
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition stm32f407xx.h:73
RNG_IRQn
@ RNG_IRQn
Definition stm32f407xx.h:156
FLASH_IRQn
@ FLASH_IRQn
Definition stm32f407xx.h:81
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition stm32f407xx.h:145
WWDG_IRQn
@ WWDG_IRQn
Definition stm32f407xx.h:77
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition stm32f407xx.h:108
TIM3_IRQn
@ TIM3_IRQn
Definition stm32f407xx.h:106
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition stm32f407xx.h:134
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition stm32f407xx.h:96
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition stm32f407xx.h:153
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition stm32f407xx.h:88
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition stm32f407xx.h:117
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f407xx.h:102
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition stm32f407xx.h:100
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition stm32f407xx.h:89
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition stm32f407xx.h:144
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition stm32f407xx.h:119
FPU_IRQn
@ FPU_IRQn
Definition stm32f407xx.h:157
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition stm32f407xx.h:121
USART6_IRQn
@ USART6_IRQn
Definition stm32f407xx.h:148
SPI1_IRQn
@ SPI1_IRQn
Definition stm32f407xx.h:112
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition stm32f407xx.h:154
PVD_IRQn
@ PVD_IRQn
Definition stm32f407xx.h:78
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f407xx.h:103
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition stm32f407xx.h:101
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition stm32f407xx.h:142
EXTI0_IRQn
@ EXTI0_IRQn
Definition stm32f407xx.h:83
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition stm32f407xx.h:97
EXTI4_IRQn
@ EXTI4_IRQn
Definition stm32f407xx.h:87
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition stm32f407xx.h:135
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f407xx.h:79
UART5_IRQn
@ UART5_IRQn
Definition stm32f407xx.h:130
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition stm32f407xx.h:93
DCMI_IRQn
@ DCMI_IRQn
Definition stm32f407xx.h:155
ETH_IRQn
@ ETH_IRQn
Definition stm32f407xx.h:138
USART1_IRQn
@ USART1_IRQn
Definition stm32f407xx.h:114
EXTI3_IRQn
@ EXTI3_IRQn
Definition stm32f407xx.h:86
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition stm32f407xx.h:68
UART4_IRQn
@ UART4_IRQn
Definition stm32f407xx.h:129
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition stm32f407xx.h:122
EXTI1_IRQn
@ EXTI1_IRQn
Definition stm32f407xx.h:84
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition stm32f407xx.h:137
TIM5_IRQn
@ TIM5_IRQn
Definition stm32f407xx.h:127
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition stm32f407xx.h:124
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f407xx.h:92
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition stm32f407xx.h:94
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition stm32f407xx.h:104
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition stm32f407xx.h:140
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition stm32f407xx.h:98
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition stm32f407xx.h:91
USART3_IRQn
@ USART3_IRQn
Definition stm32f407xx.h:116
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition stm32f407xx.h:118
ADC_Common_TypeDef
Definition stm32f107xc.h:187
ADC_TypeDef
Analog to Digital Converter
Definition stm32f107xc.h:163
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition stm32f107xc.h:267
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition stm32f107xc.h:279
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition stm32f107xc.h:255
CAN_TypeDef
Controller Area Network.
Definition stm32f107xc.h:289
CRC_TypeDef
CRC calculation unit.
Definition stm32f107xc.h:319
DAC_TypeDef
Digital to Analog Converter.
Definition stm32f107xc.h:332
DBGMCU_TypeDef
Debug MCU.
Definition stm32f107xc.h:353
DCMI_TypeDef
DCMI.
Definition stm32f207xx.h:325
DMA_Stream_TypeDef
DMA Controller.
Definition stm32f207xx.h:344
DMA_TypeDef
Definition stm32f107xc.h:371
ETH_TypeDef
Ethernet MAC.
Definition stm32f107xc.h:383
EXTI_TypeDef
External Interrupt/Event Controller.
Definition stm32f107xc.h:455
FLASH_TypeDef
FLASH Registers.
Definition stm32f107xc.h:469
FLASH_TypeDef::OPTCR1
__IO uint32_t OPTCR1
Definition stm32f407xx.h:464
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition stm32f207xx.h:480
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition stm32f207xx.h:471
FSMC_Bank2_3_TypeDef
Flexible Static Memory Controller Bank2.
Definition stm32f207xx.h:489
FSMC_Bank4_TypeDef
Flexible Static Memory Controller Bank4.
Definition stm32f207xx.h:511
GPIO_TypeDef
General Purpose I/O.
Definition stm32f107xc.h:502
I2C_TypeDef
Inter Integrated Circuit Interface.
Definition stm32f107xc.h:529
IWDG_TypeDef
Independent WATCHDOG.
Definition stm32f107xc.h:546
PWR_TypeDef
Power Control.
Definition stm32f107xc.h:558
RCC_TypeDef
Reset and Clock Control.
Definition stm32f107xc.h:568
RNG_TypeDef
RNG.
Definition stm32f207xx.h:782
RTC_TypeDef
Real-Time Clock.
Definition stm32f107xc.h:590
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition stm32f407xx.h:650
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition stm32f407xx.h:654
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition stm32f407xx.h:647
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition stm32f407xx.h:653
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition stm32f407xx.h:651
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition stm32f407xx.h:646
SDIO_TypeDef
SD host Interface.
Definition stm32f207xx.h:682
SPI_TypeDef
Serial Peripheral Interface.
Definition stm32f107xc.h:608
SYSCFG_TypeDef
System configuration controller.
Definition stm32f207xx.h:542
TIM_TypeDef
TIM Timers.
Definition stm32f107xc.h:624
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32f107xc.h:654
USB_OTG_DeviceTypeDef
__device_Registers
Definition stm32f107xc.h:696
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition stm32f107xc.h:670
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition stm32f107xc.h:770
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition stm32f107xc.h:755
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition stm32f107xc.h:724
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition stm32f107xc.h:740
WWDG_TypeDef
Window WATCHDOG.
Definition stm32f107xc.h:785
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.