mikroSDK Reference Manual
stm32f479xx.h
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1
33#ifndef __STM32F479xx_H
34#define __STM32F479xx_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
65typedef enum
66{
67/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68 NonMaskableInt_IRQn = -14,
69 MemoryManagement_IRQn = -12,
70 BusFault_IRQn = -11,
71 UsageFault_IRQn = -10,
72 SVCall_IRQn = -5,
73 DebugMonitor_IRQn = -4,
74 PendSV_IRQn = -2,
75 SysTick_IRQn = -1,
76/****** STM32 specific Interrupt Numbers **********************************************************************/
77 WWDG_IRQn = 0,
78 PVD_IRQn = 1,
79 TAMP_STAMP_IRQn = 2,
80 RTC_WKUP_IRQn = 3,
81 FLASH_IRQn = 4,
82 RCC_IRQn = 5,
83 EXTI0_IRQn = 6,
84 EXTI1_IRQn = 7,
85 EXTI2_IRQn = 8,
86 EXTI3_IRQn = 9,
87 EXTI4_IRQn = 10,
88 DMA1_Stream0_IRQn = 11,
89 DMA1_Stream1_IRQn = 12,
90 DMA1_Stream2_IRQn = 13,
91 DMA1_Stream3_IRQn = 14,
92 DMA1_Stream4_IRQn = 15,
93 DMA1_Stream5_IRQn = 16,
94 DMA1_Stream6_IRQn = 17,
95 ADC_IRQn = 18,
96 CAN1_TX_IRQn = 19,
97 CAN1_RX0_IRQn = 20,
98 CAN1_RX1_IRQn = 21,
99 CAN1_SCE_IRQn = 22,
100 EXTI9_5_IRQn = 23,
101 TIM1_BRK_TIM9_IRQn = 24,
102 TIM1_UP_TIM10_IRQn = 25,
103 TIM1_TRG_COM_TIM11_IRQn = 26,
104 TIM1_CC_IRQn = 27,
105 TIM2_IRQn = 28,
106 TIM3_IRQn = 29,
107 TIM4_IRQn = 30,
108 I2C1_EV_IRQn = 31,
109 I2C1_ER_IRQn = 32,
110 I2C2_EV_IRQn = 33,
111 I2C2_ER_IRQn = 34,
112 SPI1_IRQn = 35,
113 SPI2_IRQn = 36,
114 USART1_IRQn = 37,
115 USART2_IRQn = 38,
116 USART3_IRQn = 39,
117 EXTI15_10_IRQn = 40,
118 RTC_Alarm_IRQn = 41,
119 OTG_FS_WKUP_IRQn = 42,
120 TIM8_BRK_TIM12_IRQn = 43,
121 TIM8_UP_TIM13_IRQn = 44,
122 TIM8_TRG_COM_TIM14_IRQn = 45,
123 TIM8_CC_IRQn = 46,
124 DMA1_Stream7_IRQn = 47,
125 FMC_IRQn = 48,
126 SDIO_IRQn = 49,
127 TIM5_IRQn = 50,
128 SPI3_IRQn = 51,
129 UART4_IRQn = 52,
130 UART5_IRQn = 53,
131 TIM6_DAC_IRQn = 54,
132 TIM7_IRQn = 55,
133 DMA2_Stream0_IRQn = 56,
134 DMA2_Stream1_IRQn = 57,
135 DMA2_Stream2_IRQn = 58,
136 DMA2_Stream3_IRQn = 59,
137 DMA2_Stream4_IRQn = 60,
138 ETH_IRQn = 61,
139 ETH_WKUP_IRQn = 62,
140 CAN2_TX_IRQn = 63,
141 CAN2_RX0_IRQn = 64,
142 CAN2_RX1_IRQn = 65,
143 CAN2_SCE_IRQn = 66,
144 OTG_FS_IRQn = 67,
145 DMA2_Stream5_IRQn = 68,
146 DMA2_Stream6_IRQn = 69,
147 DMA2_Stream7_IRQn = 70,
148 USART6_IRQn = 71,
149 I2C3_EV_IRQn = 72,
150 I2C3_ER_IRQn = 73,
151 OTG_HS_EP1_OUT_IRQn = 74,
152 OTG_HS_EP1_IN_IRQn = 75,
153 OTG_HS_WKUP_IRQn = 76,
154 OTG_HS_IRQn = 77,
155 DCMI_IRQn = 78,
156 CRYP_IRQn = 79,
157 HASH_RNG_IRQn = 80,
158 FPU_IRQn = 81,
159 UART7_IRQn = 82,
160 UART8_IRQn = 83,
161 SPI4_IRQn = 84,
162 SPI5_IRQn = 85,
163 SPI6_IRQn = 86,
164 SAI1_IRQn = 87,
165 LTDC_IRQn = 88,
166 LTDC_ER_IRQn = 89,
167 DMA2D_IRQn = 90,
168 QUADSPI_IRQn = 91,
169 DSI_IRQn = 92
170} IRQn_Type;
171
176#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
177#include "system_stm32f4xx.h"
178#include <stdint.h>
179
188typedef struct
189{
190 __IO uint32_t SR;
191 __IO uint32_t CR1;
192 __IO uint32_t CR2;
193 __IO uint32_t SMPR1;
194 __IO uint32_t SMPR2;
195 __IO uint32_t JOFR1;
196 __IO uint32_t JOFR2;
197 __IO uint32_t JOFR3;
198 __IO uint32_t JOFR4;
199 __IO uint32_t HTR;
200 __IO uint32_t LTR;
201 __IO uint32_t SQR1;
202 __IO uint32_t SQR2;
203 __IO uint32_t SQR3;
204 __IO uint32_t JSQR;
205 __IO uint32_t JDR1;
206 __IO uint32_t JDR2;
207 __IO uint32_t JDR3;
208 __IO uint32_t JDR4;
209 __IO uint32_t DR;
210} ADC_TypeDef;
211
212typedef struct
213{
214 __IO uint32_t CSR;
215 __IO uint32_t CCR;
216 __IO uint32_t CDR;
218} ADC_Common_TypeDef;
219
220
225typedef struct
226{
227 __IO uint32_t TIR;
228 __IO uint32_t TDTR;
229 __IO uint32_t TDLR;
230 __IO uint32_t TDHR;
231} CAN_TxMailBox_TypeDef;
232
237typedef struct
238{
239 __IO uint32_t RIR;
240 __IO uint32_t RDTR;
241 __IO uint32_t RDLR;
242 __IO uint32_t RDHR;
243} CAN_FIFOMailBox_TypeDef;
244
249typedef struct
250{
251 __IO uint32_t FR1;
252 __IO uint32_t FR2;
253} CAN_FilterRegister_TypeDef;
254
259typedef struct
260{
261 __IO uint32_t MCR;
262 __IO uint32_t MSR;
263 __IO uint32_t TSR;
264 __IO uint32_t RF0R;
265 __IO uint32_t RF1R;
266 __IO uint32_t IER;
267 __IO uint32_t ESR;
268 __IO uint32_t BTR;
269 uint32_t RESERVED0[88];
270 CAN_TxMailBox_TypeDef sTxMailBox[3];
271 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
272 uint32_t RESERVED1[12];
273 __IO uint32_t FMR;
274 __IO uint32_t FM1R;
275 uint32_t RESERVED2;
276 __IO uint32_t FS1R;
277 uint32_t RESERVED3;
278 __IO uint32_t FFA1R;
279 uint32_t RESERVED4;
280 __IO uint32_t FA1R;
281 uint32_t RESERVED5[8];
282 CAN_FilterRegister_TypeDef sFilterRegister[28];
283} CAN_TypeDef;
284
289typedef struct
290{
291 __IO uint32_t DR;
292 __IO uint8_t IDR;
293 uint8_t RESERVED0;
294 uint16_t RESERVED1;
295 __IO uint32_t CR;
296} CRC_TypeDef;
297
302typedef struct
303{
304 __IO uint32_t CR;
305 __IO uint32_t SWTRIGR;
306 __IO uint32_t DHR12R1;
307 __IO uint32_t DHR12L1;
308 __IO uint32_t DHR8R1;
309 __IO uint32_t DHR12R2;
310 __IO uint32_t DHR12L2;
311 __IO uint32_t DHR8R2;
312 __IO uint32_t DHR12RD;
313 __IO uint32_t DHR12LD;
314 __IO uint32_t DHR8RD;
315 __IO uint32_t DOR1;
316 __IO uint32_t DOR2;
317 __IO uint32_t SR;
318} DAC_TypeDef;
319
324typedef struct
325{
326 __IO uint32_t IDCODE;
327 __IO uint32_t CR;
328 __IO uint32_t APB1FZ;
329 __IO uint32_t APB2FZ;
330}DBGMCU_TypeDef;
331
336typedef struct
337{
338 __IO uint32_t CR;
339 __IO uint32_t SR;
340 __IO uint32_t RISR;
341 __IO uint32_t IER;
342 __IO uint32_t MISR;
343 __IO uint32_t ICR;
344 __IO uint32_t ESCR;
345 __IO uint32_t ESUR;
346 __IO uint32_t CWSTRTR;
347 __IO uint32_t CWSIZER;
348 __IO uint32_t DR;
349} DCMI_TypeDef;
350
355typedef struct
356{
357 __IO uint32_t CR;
358 __IO uint32_t NDTR;
359 __IO uint32_t PAR;
360 __IO uint32_t M0AR;
361 __IO uint32_t M1AR;
362 __IO uint32_t FCR;
363} DMA_Stream_TypeDef;
364
365typedef struct
366{
367 __IO uint32_t LISR;
368 __IO uint32_t HISR;
369 __IO uint32_t LIFCR;
370 __IO uint32_t HIFCR;
371} DMA_TypeDef;
372
377typedef struct
378{
379 __IO uint32_t CR;
380 __IO uint32_t ISR;
381 __IO uint32_t IFCR;
382 __IO uint32_t FGMAR;
383 __IO uint32_t FGOR;
384 __IO uint32_t BGMAR;
385 __IO uint32_t BGOR;
386 __IO uint32_t FGPFCCR;
387 __IO uint32_t FGCOLR;
388 __IO uint32_t BGPFCCR;
389 __IO uint32_t BGCOLR;
390 __IO uint32_t FGCMAR;
391 __IO uint32_t BGCMAR;
392 __IO uint32_t OPFCCR;
393 __IO uint32_t OCOLR;
394 __IO uint32_t OMAR;
395 __IO uint32_t OOR;
396 __IO uint32_t NLR;
397 __IO uint32_t LWR;
398 __IO uint32_t AMTCR;
399 uint32_t RESERVED[236];
400 __IO uint32_t FGCLUT[256];
401 __IO uint32_t BGCLUT[256];
402} DMA2D_TypeDef;
403
408typedef struct
409{
410 __IO uint32_t VR;
411 __IO uint32_t CR;
412 __IO uint32_t CCR;
413 __IO uint32_t LVCIDR;
414 __IO uint32_t LCOLCR;
415 __IO uint32_t LPCR;
416 __IO uint32_t LPMCR;
417 uint32_t RESERVED0[4];
418 __IO uint32_t PCR;
419 __IO uint32_t GVCIDR;
420 __IO uint32_t MCR;
421 __IO uint32_t VMCR;
422 __IO uint32_t VPCR;
423 __IO uint32_t VCCR;
424 __IO uint32_t VNPCR;
425 __IO uint32_t VHSACR;
426 __IO uint32_t VHBPCR;
427 __IO uint32_t VLCR;
428 __IO uint32_t VVSACR;
429 __IO uint32_t VVBPCR;
430 __IO uint32_t VVFPCR;
431 __IO uint32_t VVACR;
432 __IO uint32_t LCCR;
433 __IO uint32_t CMCR;
434 __IO uint32_t GHCR;
435 __IO uint32_t GPDR;
436 __IO uint32_t GPSR;
437 __IO uint32_t TCCR[6];
438 __IO uint32_t TDCR;
439 __IO uint32_t CLCR;
440 __IO uint32_t CLTCR;
441 __IO uint32_t DLTCR;
442 __IO uint32_t PCTLR;
443 __IO uint32_t PCONFR;
444 __IO uint32_t PUCR;
445 __IO uint32_t PTTCR;
446 __IO uint32_t PSR;
447 uint32_t RESERVED1[2];
448 __IO uint32_t ISR[2];
449 __IO uint32_t IER[2];
450 uint32_t RESERVED2[3];
451 __IO uint32_t FIR[2];
452 uint32_t RESERVED3[8];
453 __IO uint32_t VSCR;
454 uint32_t RESERVED4[2];
455 __IO uint32_t LCVCIDR;
456 __IO uint32_t LCCCR;
457 uint32_t RESERVED5;
458 __IO uint32_t LPMCCR;
459 uint32_t RESERVED6[7];
460 __IO uint32_t VMCCR;
461 __IO uint32_t VPCCR;
462 __IO uint32_t VCCCR;
463 __IO uint32_t VNPCCR;
464 __IO uint32_t VHSACCR;
465 __IO uint32_t VHBPCCR;
466 __IO uint32_t VLCCR;
467 __IO uint32_t VVSACCR;
468 __IO uint32_t VVBPCCR;
469 __IO uint32_t VVFPCCR;
470 __IO uint32_t VVACCR;
471 uint32_t RESERVED7[11];
472 __IO uint32_t TDCCR;
473 uint32_t RESERVED8[155];
474 __IO uint32_t WCFGR;
475 __IO uint32_t WCR;
476 __IO uint32_t WIER;
477 __IO uint32_t WISR;
478 __IO uint32_t WIFCR;
479 uint32_t RESERVED9;
480 __IO uint32_t WPCR[5];
481 uint32_t RESERVED10;
482 __IO uint32_t WRPCR;
483} DSI_TypeDef;
484
489typedef struct
490{
491 __IO uint32_t MACCR;
492 __IO uint32_t MACFFR;
493 __IO uint32_t MACHTHR;
494 __IO uint32_t MACHTLR;
495 __IO uint32_t MACMIIAR;
496 __IO uint32_t MACMIIDR;
497 __IO uint32_t MACFCR;
498 __IO uint32_t MACVLANTR; /* 8 */
499 uint32_t RESERVED0[2];
500 __IO uint32_t MACRWUFFR; /* 11 */
501 __IO uint32_t MACPMTCSR;
502 uint32_t RESERVED1;
503 __IO uint32_t MACDBGR;
504 __IO uint32_t MACSR; /* 15 */
505 __IO uint32_t MACIMR;
506 __IO uint32_t MACA0HR;
507 __IO uint32_t MACA0LR;
508 __IO uint32_t MACA1HR;
509 __IO uint32_t MACA1LR;
510 __IO uint32_t MACA2HR;
511 __IO uint32_t MACA2LR;
512 __IO uint32_t MACA3HR;
513 __IO uint32_t MACA3LR; /* 24 */
514 uint32_t RESERVED2[40];
515 __IO uint32_t MMCCR; /* 65 */
516 __IO uint32_t MMCRIR;
517 __IO uint32_t MMCTIR;
518 __IO uint32_t MMCRIMR;
519 __IO uint32_t MMCTIMR; /* 69 */
520 uint32_t RESERVED3[14];
521 __IO uint32_t MMCTGFSCCR; /* 84 */
522 __IO uint32_t MMCTGFMSCCR;
523 uint32_t RESERVED4[5];
524 __IO uint32_t MMCTGFCR;
525 uint32_t RESERVED5[10];
526 __IO uint32_t MMCRFCECR;
527 __IO uint32_t MMCRFAECR;
528 uint32_t RESERVED6[10];
529 __IO uint32_t MMCRGUFCR;
530 uint32_t RESERVED7[334];
531 __IO uint32_t PTPTSCR;
532 __IO uint32_t PTPSSIR;
533 __IO uint32_t PTPTSHR;
534 __IO uint32_t PTPTSLR;
535 __IO uint32_t PTPTSHUR;
536 __IO uint32_t PTPTSLUR;
537 __IO uint32_t PTPTSAR;
538 __IO uint32_t PTPTTHR;
539 __IO uint32_t PTPTTLR;
540 __IO uint32_t RESERVED8;
541 __IO uint32_t PTPTSSR;
542 uint32_t RESERVED9[565];
543 __IO uint32_t DMABMR;
544 __IO uint32_t DMATPDR;
545 __IO uint32_t DMARPDR;
546 __IO uint32_t DMARDLAR;
547 __IO uint32_t DMATDLAR;
548 __IO uint32_t DMASR;
549 __IO uint32_t DMAOMR;
550 __IO uint32_t DMAIER;
551 __IO uint32_t DMAMFBOCR;
552 __IO uint32_t DMARSWTR;
553 uint32_t RESERVED10[8];
554 __IO uint32_t DMACHTDR;
555 __IO uint32_t DMACHRDR;
556 __IO uint32_t DMACHTBAR;
557 __IO uint32_t DMACHRBAR;
558} ETH_TypeDef;
559
564typedef struct
565{
566 __IO uint32_t IMR;
567 __IO uint32_t EMR;
568 __IO uint32_t RTSR;
569 __IO uint32_t FTSR;
570 __IO uint32_t SWIER;
571 __IO uint32_t PR;
572} EXTI_TypeDef;
573
578typedef struct
579{
580 __IO uint32_t ACR;
581 __IO uint32_t KEYR;
582 __IO uint32_t OPTKEYR;
583 __IO uint32_t SR;
584 __IO uint32_t CR;
585 __IO uint32_t OPTCR;
586 __IO uint32_t OPTCR1;
587} FLASH_TypeDef;
588
593typedef struct
594{
595 __IO uint32_t BTCR[8];
596} FMC_Bank1_TypeDef;
597
602typedef struct
603{
604 __IO uint32_t BWTR[7];
605} FMC_Bank1E_TypeDef;
606
611typedef struct
612{
613 __IO uint32_t PCR;
614 __IO uint32_t SR;
615 __IO uint32_t PMEM;
616 __IO uint32_t PATT;
617 uint32_t RESERVED;
618 __IO uint32_t ECCR;
619} FMC_Bank3_TypeDef;
620
625typedef struct
626{
627 __IO uint32_t SDCR[2];
628 __IO uint32_t SDTR[2];
629 __IO uint32_t SDCMR;
630 __IO uint32_t SDRTR;
631 __IO uint32_t SDSR;
632} FMC_Bank5_6_TypeDef;
633
638typedef struct
639{
640 __IO uint32_t MODER;
641 __IO uint32_t OTYPER;
642 __IO uint32_t OSPEEDR;
643 __IO uint32_t PUPDR;
644 __IO uint32_t IDR;
645 __IO uint32_t ODR;
646 __IO uint32_t BSRR;
647 __IO uint32_t LCKR;
648 __IO uint32_t AFR[2];
649} GPIO_TypeDef;
650
655typedef struct
656{
657 __IO uint32_t MEMRMP;
658 __IO uint32_t PMC;
659 __IO uint32_t EXTICR[4];
660 uint32_t RESERVED[2];
661 __IO uint32_t CMPCR;
662} SYSCFG_TypeDef;
663
668typedef struct
669{
670 __IO uint32_t CR1;
671 __IO uint32_t CR2;
672 __IO uint32_t OAR1;
673 __IO uint32_t OAR2;
674 __IO uint32_t DR;
675 __IO uint32_t SR1;
676 __IO uint32_t SR2;
677 __IO uint32_t CCR;
678 __IO uint32_t TRISE;
679 __IO uint32_t FLTR;
680} I2C_TypeDef;
681
686typedef struct
687{
688 __IO uint32_t KR;
689 __IO uint32_t PR;
690 __IO uint32_t RLR;
691 __IO uint32_t SR;
692} IWDG_TypeDef;
693
698typedef struct
699{
700 uint32_t RESERVED0[2];
701 __IO uint32_t SSCR;
702 __IO uint32_t BPCR;
703 __IO uint32_t AWCR;
704 __IO uint32_t TWCR;
705 __IO uint32_t GCR;
706 uint32_t RESERVED1[2];
707 __IO uint32_t SRCR;
708 uint32_t RESERVED2[1];
709 __IO uint32_t BCCR;
710 uint32_t RESERVED3[1];
711 __IO uint32_t IER;
712 __IO uint32_t ISR;
713 __IO uint32_t ICR;
714 __IO uint32_t LIPCR;
715 __IO uint32_t CPSR;
716 __IO uint32_t CDSR;
717} LTDC_TypeDef;
718
723typedef struct
724{
725 __IO uint32_t CR;
726 __IO uint32_t WHPCR;
727 __IO uint32_t WVPCR;
728 __IO uint32_t CKCR;
729 __IO uint32_t PFCR;
730 __IO uint32_t CACR;
731 __IO uint32_t DCCR;
732 __IO uint32_t BFCR;
733 uint32_t RESERVED0[2];
734 __IO uint32_t CFBAR;
735 __IO uint32_t CFBLR;
736 __IO uint32_t CFBLNR;
737 uint32_t RESERVED1[3];
738 __IO uint32_t CLUTWR;
739} LTDC_Layer_TypeDef;
740
745typedef struct
746{
747 __IO uint32_t CR;
748 __IO uint32_t CSR;
749} PWR_TypeDef;
750
755typedef struct
756{
757 __IO uint32_t CR;
758 __IO uint32_t PLLCFGR;
759 __IO uint32_t CFGR;
760 __IO uint32_t CIR;
761 __IO uint32_t AHB1RSTR;
762 __IO uint32_t AHB2RSTR;
763 __IO uint32_t AHB3RSTR;
764 uint32_t RESERVED0;
765 __IO uint32_t APB1RSTR;
766 __IO uint32_t APB2RSTR;
767 uint32_t RESERVED1[2];
768 __IO uint32_t AHB1ENR;
769 __IO uint32_t AHB2ENR;
770 __IO uint32_t AHB3ENR;
771 uint32_t RESERVED2;
772 __IO uint32_t APB1ENR;
773 __IO uint32_t APB2ENR;
774 uint32_t RESERVED3[2];
775 __IO uint32_t AHB1LPENR;
776 __IO uint32_t AHB2LPENR;
777 __IO uint32_t AHB3LPENR;
778 uint32_t RESERVED4;
779 __IO uint32_t APB1LPENR;
780 __IO uint32_t APB2LPENR;
781 uint32_t RESERVED5[2];
782 __IO uint32_t BDCR;
783 __IO uint32_t CSR;
784 uint32_t RESERVED6[2];
785 __IO uint32_t SSCGR;
786 __IO uint32_t PLLI2SCFGR;
787 __IO uint32_t PLLSAICFGR;
788 __IO uint32_t DCKCFGR;
789} RCC_TypeDef;
790
795typedef struct
796{
797 __IO uint32_t TR;
798 __IO uint32_t DR;
799 __IO uint32_t CR;
800 __IO uint32_t ISR;
801 __IO uint32_t PRER;
802 __IO uint32_t WUTR;
803 __IO uint32_t CALIBR;
804 __IO uint32_t ALRMAR;
805 __IO uint32_t ALRMBR;
806 __IO uint32_t WPR;
807 __IO uint32_t SSR;
808 __IO uint32_t SHIFTR;
809 __IO uint32_t TSTR;
810 __IO uint32_t TSDR;
811 __IO uint32_t TSSSR;
812 __IO uint32_t CALR;
813 __IO uint32_t TAFCR;
814 __IO uint32_t ALRMASSR;
815 __IO uint32_t ALRMBSSR;
816 uint32_t RESERVED7;
817 __IO uint32_t BKP0R;
818 __IO uint32_t BKP1R;
819 __IO uint32_t BKP2R;
820 __IO uint32_t BKP3R;
821 __IO uint32_t BKP4R;
822 __IO uint32_t BKP5R;
823 __IO uint32_t BKP6R;
824 __IO uint32_t BKP7R;
825 __IO uint32_t BKP8R;
826 __IO uint32_t BKP9R;
827 __IO uint32_t BKP10R;
828 __IO uint32_t BKP11R;
829 __IO uint32_t BKP12R;
830 __IO uint32_t BKP13R;
831 __IO uint32_t BKP14R;
832 __IO uint32_t BKP15R;
833 __IO uint32_t BKP16R;
834 __IO uint32_t BKP17R;
835 __IO uint32_t BKP18R;
836 __IO uint32_t BKP19R;
837} RTC_TypeDef;
838
843typedef struct
844{
845 __IO uint32_t GCR;
846} SAI_TypeDef;
847
848typedef struct
849{
850 __IO uint32_t CR1;
851 __IO uint32_t CR2;
852 __IO uint32_t FRCR;
853 __IO uint32_t SLOTR;
854 __IO uint32_t IMR;
855 __IO uint32_t SR;
856 __IO uint32_t CLRFR;
857 __IO uint32_t DR;
858} SAI_Block_TypeDef;
859
864typedef struct
865{
866 __IO uint32_t POWER;
867 __IO uint32_t CLKCR;
868 __IO uint32_t ARG;
869 __IO uint32_t CMD;
870 __IO const uint32_t RESPCMD;
871 __IO const uint32_t RESP1;
872 __IO const uint32_t RESP2;
873 __IO const uint32_t RESP3;
874 __IO const uint32_t RESP4;
875 __IO uint32_t DTIMER;
876 __IO uint32_t DLEN;
877 __IO uint32_t DCTRL;
878 __IO const uint32_t DCOUNT;
879 __IO const uint32_t STA;
880 __IO uint32_t ICR;
881 __IO uint32_t MASK;
882 uint32_t RESERVED0[2];
883 __IO const uint32_t FIFOCNT;
884 uint32_t RESERVED1[13];
885 __IO uint32_t FIFO;
886} SDIO_TypeDef;
887
892typedef struct
893{
894 __IO uint32_t CR1;
895 __IO uint32_t CR2;
896 __IO uint32_t SR;
897 __IO uint32_t DR;
898 __IO uint32_t CRCPR;
899 __IO uint32_t RXCRCR;
900 __IO uint32_t TXCRCR;
901 __IO uint32_t I2SCFGR;
902 __IO uint32_t I2SPR;
903} SPI_TypeDef;
904
909typedef struct
910{
911 __IO uint32_t CR;
912 __IO uint32_t DCR;
913 __IO uint32_t SR;
914 __IO uint32_t FCR;
915 __IO uint32_t DLR;
916 __IO uint32_t CCR;
917 __IO uint32_t AR;
918 __IO uint32_t ABR;
919 __IO uint32_t DR;
920 __IO uint32_t PSMKR;
921 __IO uint32_t PSMAR;
922 __IO uint32_t PIR;
923 __IO uint32_t LPTR;
924} QUADSPI_TypeDef;
925
930typedef struct
931{
932 __IO uint32_t CR1;
933 __IO uint32_t CR2;
934 __IO uint32_t SMCR;
935 __IO uint32_t DIER;
936 __IO uint32_t SR;
937 __IO uint32_t EGR;
938 __IO uint32_t CCMR1;
939 __IO uint32_t CCMR2;
940 __IO uint32_t CCER;
941 __IO uint32_t CNT;
942 __IO uint32_t PSC;
943 __IO uint32_t ARR;
944 __IO uint32_t RCR;
945 __IO uint32_t CCR1;
946 __IO uint32_t CCR2;
947 __IO uint32_t CCR3;
948 __IO uint32_t CCR4;
949 __IO uint32_t BDTR;
950 __IO uint32_t DCR;
951 __IO uint32_t DMAR;
952 __IO uint32_t OR;
953} TIM_TypeDef;
954
959typedef struct
960{
961 __IO uint32_t SR;
962 __IO uint32_t DR;
963 __IO uint32_t BRR;
964 __IO uint32_t CR1;
965 __IO uint32_t CR2;
966 __IO uint32_t CR3;
967 __IO uint32_t GTPR;
968} USART_TypeDef;
969
974typedef struct
975{
976 __IO uint32_t CR;
977 __IO uint32_t CFR;
978 __IO uint32_t SR;
979} WWDG_TypeDef;
980
985typedef struct
986{
987 __IO uint32_t CR;
988 __IO uint32_t SR;
989 __IO uint32_t DIN;
990 __IO uint32_t DOUT;
991 __IO uint32_t DMACR;
992 __IO uint32_t IMSCR;
993 __IO uint32_t RISR;
994 __IO uint32_t MISR;
995 __IO uint32_t K0LR;
996 __IO uint32_t K0RR;
997 __IO uint32_t K1LR;
998 __IO uint32_t K1RR;
999 __IO uint32_t K2LR;
1000 __IO uint32_t K2RR;
1001 __IO uint32_t K3LR;
1002 __IO uint32_t K3RR;
1003 __IO uint32_t IV0LR;
1004 __IO uint32_t IV0RR;
1005 __IO uint32_t IV1LR;
1006 __IO uint32_t IV1RR;
1007 __IO uint32_t CSGCMCCM0R;
1008 __IO uint32_t CSGCMCCM1R;
1009 __IO uint32_t CSGCMCCM2R;
1010 __IO uint32_t CSGCMCCM3R;
1011 __IO uint32_t CSGCMCCM4R;
1012 __IO uint32_t CSGCMCCM5R;
1013 __IO uint32_t CSGCMCCM6R;
1014 __IO uint32_t CSGCMCCM7R;
1015 __IO uint32_t CSGCM0R;
1016 __IO uint32_t CSGCM1R;
1017 __IO uint32_t CSGCM2R;
1018 __IO uint32_t CSGCM3R;
1019 __IO uint32_t CSGCM4R;
1020 __IO uint32_t CSGCM5R;
1021 __IO uint32_t CSGCM6R;
1022 __IO uint32_t CSGCM7R;
1023} CRYP_TypeDef;
1024
1029typedef struct
1030{
1031 __IO uint32_t CR;
1032 __IO uint32_t DIN;
1033 __IO uint32_t STR;
1034 __IO uint32_t HR[5];
1035 __IO uint32_t IMR;
1036 __IO uint32_t SR;
1037 uint32_t RESERVED[52];
1038 __IO uint32_t CSR[54];
1039} HASH_TypeDef;
1040
1045typedef struct
1046{
1047 __IO uint32_t HR[8];
1048} HASH_DIGEST_TypeDef;
1049
1054typedef struct
1055{
1056 __IO uint32_t CR;
1057 __IO uint32_t SR;
1058 __IO uint32_t DR;
1059} RNG_TypeDef;
1060
1064typedef struct
1065{
1066 __IO uint32_t GOTGCTL;
1067 __IO uint32_t GOTGINT;
1068 __IO uint32_t GAHBCFG;
1069 __IO uint32_t GUSBCFG;
1070 __IO uint32_t GRSTCTL;
1071 __IO uint32_t GINTSTS;
1072 __IO uint32_t GINTMSK;
1073 __IO uint32_t GRXSTSR;
1074 __IO uint32_t GRXSTSP;
1075 __IO uint32_t GRXFSIZ;
1076 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1077 __IO uint32_t HNPTXSTS;
1078 uint32_t Reserved30[2];
1079 __IO uint32_t GCCFG;
1080 __IO uint32_t CID;
1081 uint32_t Reserved5[3];
1082 __IO uint32_t GHWCFG3;
1083 uint32_t Reserved6;
1084 __IO uint32_t GLPMCFG;
1085 uint32_t Reserved;
1086 __IO uint32_t GDFIFOCFG;
1087 uint32_t Reserved43[40];
1088 __IO uint32_t HPTXFSIZ;
1089 __IO uint32_t DIEPTXF[0x0F];
1090} USB_OTG_GlobalTypeDef;
1091
1095typedef struct
1096{
1097 __IO uint32_t DCFG;
1098 __IO uint32_t DCTL;
1099 __IO uint32_t DSTS;
1100 uint32_t Reserved0C;
1101 __IO uint32_t DIEPMSK;
1102 __IO uint32_t DOEPMSK;
1103 __IO uint32_t DAINT;
1104 __IO uint32_t DAINTMSK;
1105 uint32_t Reserved20;
1106 uint32_t Reserved9;
1107 __IO uint32_t DVBUSDIS;
1108 __IO uint32_t DVBUSPULSE;
1109 __IO uint32_t DTHRCTL;
1110 __IO uint32_t DIEPEMPMSK;
1111 __IO uint32_t DEACHINT;
1112 __IO uint32_t DEACHMSK;
1113 uint32_t Reserved40;
1114 __IO uint32_t DINEP1MSK;
1115 uint32_t Reserved44[15];
1116 __IO uint32_t DOUTEP1MSK;
1117} USB_OTG_DeviceTypeDef;
1118
1122typedef struct
1123{
1124 __IO uint32_t DIEPCTL;
1125 uint32_t Reserved04;
1126 __IO uint32_t DIEPINT;
1127 uint32_t Reserved0C;
1128 __IO uint32_t DIEPTSIZ;
1129 __IO uint32_t DIEPDMA;
1130 __IO uint32_t DTXFSTS;
1131 uint32_t Reserved18;
1132} USB_OTG_INEndpointTypeDef;
1133
1137typedef struct
1138{
1139 __IO uint32_t DOEPCTL;
1140 uint32_t Reserved04;
1141 __IO uint32_t DOEPINT;
1142 uint32_t Reserved0C;
1143 __IO uint32_t DOEPTSIZ;
1144 __IO uint32_t DOEPDMA;
1145 uint32_t Reserved18[2];
1146} USB_OTG_OUTEndpointTypeDef;
1147
1151typedef struct
1152{
1153 __IO uint32_t HCFG;
1154 __IO uint32_t HFIR;
1155 __IO uint32_t HFNUM;
1156 uint32_t Reserved40C;
1157 __IO uint32_t HPTXSTS;
1158 __IO uint32_t HAINT;
1159 __IO uint32_t HAINTMSK;
1160} USB_OTG_HostTypeDef;
1161
1165typedef struct
1166{
1167 __IO uint32_t HCCHAR;
1168 __IO uint32_t HCSPLT;
1169 __IO uint32_t HCINT;
1170 __IO uint32_t HCINTMSK;
1171 __IO uint32_t HCTSIZ;
1172 __IO uint32_t HCDMA;
1173 uint32_t Reserved[2];
1174} USB_OTG_HostChannelTypeDef;
1175
1183#define FLASH_BASE 0x08000000UL
1184#define CCMDATARAM_BASE 0x10000000UL
1185#define SRAM1_BASE 0x20000000UL
1186#define SRAM2_BASE 0x20028000UL
1187#define SRAM3_BASE 0x20030000UL
1188#define PERIPH_BASE 0x40000000UL
1189#define BKPSRAM_BASE 0x40024000UL
1190#define FMC_R_BASE 0xA0000000UL
1191#define QSPI_R_BASE 0xA0001000UL
1192#define SRAM1_BB_BASE 0x22000000UL
1193#define SRAM2_BB_BASE 0x22500000UL
1194#define SRAM3_BB_BASE 0x22600000UL
1195#define PERIPH_BB_BASE 0x42000000UL
1196#define BKPSRAM_BB_BASE 0x42480000UL
1197#define FLASH_END 0x081FFFFFUL
1198#define FLASH_OTP_BASE 0x1FFF7800UL
1199#define FLASH_OTP_END 0x1FFF7A0FUL
1200#define CCMDATARAM_END 0x1000FFFFUL
1202/* Legacy defines */
1203#define SRAM_BASE SRAM1_BASE
1204#define SRAM_BB_BASE SRAM1_BB_BASE
1205
1207#define APB1PERIPH_BASE PERIPH_BASE
1208#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1209#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1210#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
1211
1213#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1214#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1215#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1216#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1217#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1218#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1219#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
1220#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
1221#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
1222#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1223#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1224#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1225#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
1226#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1227#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1228#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
1229#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1230#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1231#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1232#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1233#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1234#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1235#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
1236#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1237#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1238#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1239#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1240#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
1241#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
1242
1244#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
1245#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
1246#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
1247#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
1248#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
1249#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
1250#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
1251#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
1252/* Legacy define */
1253#define ADC_BASE ADC123_COMMON_BASE
1254#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
1255#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1256#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
1257#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
1258#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
1259#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
1260#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
1261#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
1262#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
1263#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
1264#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
1265#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
1266#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
1267#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
1268#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
1269#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
1270#define DSI_BASE (APB2PERIPH_BASE + 0x6C00UL)
1271
1273#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
1274#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1275#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1276#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1277#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1278#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1279#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1280#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1281#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
1282#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
1283#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
1284#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1285#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1286#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1287#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1288#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1289#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1290#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1291#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1292#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1293#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1294#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1295#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1296#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1297#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1298#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1299#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1300#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1301#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1302#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1303#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1304#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1305#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
1306#define ETH_MAC_BASE (ETH_BASE)
1307#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
1308#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
1309#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
1310#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
1311
1313#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1314#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000UL)
1315#define HASH_BASE (AHB2PERIPH_BASE + 0x60400UL)
1316#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710UL)
1317#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1318
1320#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1321#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1322#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1323#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
1324
1325
1327#define DBGMCU_BASE 0xE0042000UL
1329#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1330#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1331
1332#define USB_OTG_GLOBAL_BASE 0x000UL
1333#define USB_OTG_DEVICE_BASE 0x800UL
1334#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
1335#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
1336#define USB_OTG_EP_REG_SIZE 0x20UL
1337#define USB_OTG_HOST_BASE 0x400UL
1338#define USB_OTG_HOST_PORT_BASE 0x440UL
1339#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
1340#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
1341#define USB_OTG_PCGCCTL_BASE 0xE00UL
1342#define USB_OTG_FIFO_BASE 0x1000UL
1343#define USB_OTG_FIFO_SIZE 0x1000UL
1344
1345#define UID_BASE 0x1FFF7A10UL
1346#define FLASHSIZE_BASE 0x1FFF7A22UL
1347#define PACKAGE_BASE 0x1FFF7BF0UL
1355#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1356#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1357#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1358#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1359#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1360#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1361#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1362#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1363#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1364#define RTC ((RTC_TypeDef *) RTC_BASE)
1365#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1366#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1367#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1368#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1369#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1370#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1371#define USART2 ((USART_TypeDef *) USART2_BASE)
1372#define USART3 ((USART_TypeDef *) USART3_BASE)
1373#define UART4 ((USART_TypeDef *) UART4_BASE)
1374#define UART5 ((USART_TypeDef *) UART5_BASE)
1375#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1376#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1377#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1378#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1379#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1380#define PWR ((PWR_TypeDef *) PWR_BASE)
1381#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1382#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1383#define UART7 ((USART_TypeDef *) UART7_BASE)
1384#define UART8 ((USART_TypeDef *) UART8_BASE)
1385#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1386#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1387#define USART1 ((USART_TypeDef *) USART1_BASE)
1388#define USART6 ((USART_TypeDef *) USART6_BASE)
1389#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1390#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1391#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1392#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1393/* Legacy define */
1394#define ADC ADC123_COMMON
1395#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1396#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1397#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1398#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1399#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1400#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1401#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1402#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1403#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1404#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1405#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1406#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1407#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1408#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1409#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1410#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1411#define DSI ((DSI_TypeDef *)DSI_BASE)
1412#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1413#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1414#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1415#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1416#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1417#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1418#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1419#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1420#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1421#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1422#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1423#define CRC ((CRC_TypeDef *) CRC_BASE)
1424#define RCC ((RCC_TypeDef *) RCC_BASE)
1425#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1426#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1427#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1428#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1429#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1430#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1431#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1432#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1433#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1434#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1435#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1436#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1437#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1438#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1439#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1440#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1441#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1442#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1443#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1444#define ETH ((ETH_TypeDef *) ETH_BASE)
1445#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1446#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1447#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1448#define HASH ((HASH_TypeDef *) HASH_BASE)
1449#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1450#define RNG ((RNG_TypeDef *) RNG_BASE)
1451#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1452#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1453#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1454#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1455#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1456#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1457#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1458#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1459
1471#define LSI_STARTUP_TIME 40U
1480/******************************************************************************/
1481/* Peripheral Registers_Bits_Definition */
1482/******************************************************************************/
1483
1484/******************************************************************************/
1485/* */
1486/* Analog to Digital Converter */
1487/* */
1488/******************************************************************************/
1489/*
1490 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1491 */
1492#define ADC_MULTIMODE_SUPPORT
1494/******************** Bit definition for ADC_SR register ********************/
1495#define ADC_SR_AWD_Pos (0U)
1496#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1497#define ADC_SR_AWD ADC_SR_AWD_Msk
1498#define ADC_SR_EOC_Pos (1U)
1499#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1500#define ADC_SR_EOC ADC_SR_EOC_Msk
1501#define ADC_SR_JEOC_Pos (2U)
1502#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1503#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1504#define ADC_SR_JSTRT_Pos (3U)
1505#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1506#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1507#define ADC_SR_STRT_Pos (4U)
1508#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1509#define ADC_SR_STRT ADC_SR_STRT_Msk
1510#define ADC_SR_OVR_Pos (5U)
1511#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1512#define ADC_SR_OVR ADC_SR_OVR_Msk
1514/******************* Bit definition for ADC_CR1 register ********************/
1515#define ADC_CR1_AWDCH_Pos (0U)
1516#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1517#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1518#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1519#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1520#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1521#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1522#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1523#define ADC_CR1_EOCIE_Pos (5U)
1524#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1525#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1526#define ADC_CR1_AWDIE_Pos (6U)
1527#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1528#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1529#define ADC_CR1_JEOCIE_Pos (7U)
1530#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1531#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1532#define ADC_CR1_SCAN_Pos (8U)
1533#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1534#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1535#define ADC_CR1_AWDSGL_Pos (9U)
1536#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1537#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1538#define ADC_CR1_JAUTO_Pos (10U)
1539#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1540#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1541#define ADC_CR1_DISCEN_Pos (11U)
1542#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1543#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1544#define ADC_CR1_JDISCEN_Pos (12U)
1545#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1546#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1547#define ADC_CR1_DISCNUM_Pos (13U)
1548#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1549#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1550#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1551#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1552#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1553#define ADC_CR1_JAWDEN_Pos (22U)
1554#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1555#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1556#define ADC_CR1_AWDEN_Pos (23U)
1557#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1558#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1559#define ADC_CR1_RES_Pos (24U)
1560#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1561#define ADC_CR1_RES ADC_CR1_RES_Msk
1562#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1563#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1564#define ADC_CR1_OVRIE_Pos (26U)
1565#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1566#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1568/******************* Bit definition for ADC_CR2 register ********************/
1569#define ADC_CR2_ADON_Pos (0U)
1570#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1571#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1572#define ADC_CR2_CONT_Pos (1U)
1573#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1574#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1575#define ADC_CR2_DMA_Pos (8U)
1576#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1577#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1578#define ADC_CR2_DDS_Pos (9U)
1579#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1580#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1581#define ADC_CR2_EOCS_Pos (10U)
1582#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1583#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1584#define ADC_CR2_ALIGN_Pos (11U)
1585#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1586#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1587#define ADC_CR2_JEXTSEL_Pos (16U)
1588#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1589#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1590#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1591#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1592#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1593#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1594#define ADC_CR2_JEXTEN_Pos (20U)
1595#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1596#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1597#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1598#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1599#define ADC_CR2_JSWSTART_Pos (22U)
1600#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1601#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1602#define ADC_CR2_EXTSEL_Pos (24U)
1603#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1604#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1605#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1606#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1607#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1608#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1609#define ADC_CR2_EXTEN_Pos (28U)
1610#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1611#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1612#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1613#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1614#define ADC_CR2_SWSTART_Pos (30U)
1615#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1616#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1618/****************** Bit definition for ADC_SMPR1 register *******************/
1619#define ADC_SMPR1_SMP10_Pos (0U)
1620#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1621#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1622#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1623#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1624#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1625#define ADC_SMPR1_SMP11_Pos (3U)
1626#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1627#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1628#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1629#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1630#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1631#define ADC_SMPR1_SMP12_Pos (6U)
1632#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1633#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1634#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1635#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1636#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1637#define ADC_SMPR1_SMP13_Pos (9U)
1638#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1639#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1640#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1641#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1642#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1643#define ADC_SMPR1_SMP14_Pos (12U)
1644#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1645#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1646#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1647#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1648#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1649#define ADC_SMPR1_SMP15_Pos (15U)
1650#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1651#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1652#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1653#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1654#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1655#define ADC_SMPR1_SMP16_Pos (18U)
1656#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1657#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1658#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1659#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1660#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1661#define ADC_SMPR1_SMP17_Pos (21U)
1662#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1663#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1664#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1665#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1666#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1667#define ADC_SMPR1_SMP18_Pos (24U)
1668#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1669#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1670#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1671#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1672#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1674/****************** Bit definition for ADC_SMPR2 register *******************/
1675#define ADC_SMPR2_SMP0_Pos (0U)
1676#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1677#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1678#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1679#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1680#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1681#define ADC_SMPR2_SMP1_Pos (3U)
1682#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1683#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1684#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1685#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1686#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1687#define ADC_SMPR2_SMP2_Pos (6U)
1688#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1689#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1690#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1691#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1692#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1693#define ADC_SMPR2_SMP3_Pos (9U)
1694#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1695#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1696#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1697#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1698#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1699#define ADC_SMPR2_SMP4_Pos (12U)
1700#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1701#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1702#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1703#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1704#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1705#define ADC_SMPR2_SMP5_Pos (15U)
1706#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1707#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1708#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1709#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1710#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1711#define ADC_SMPR2_SMP6_Pos (18U)
1712#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1713#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1714#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1715#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1716#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1717#define ADC_SMPR2_SMP7_Pos (21U)
1718#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1719#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1720#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1721#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1722#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1723#define ADC_SMPR2_SMP8_Pos (24U)
1724#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1725#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1726#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1727#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1728#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1729#define ADC_SMPR2_SMP9_Pos (27U)
1730#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1731#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1732#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1733#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1734#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1736/****************** Bit definition for ADC_JOFR1 register *******************/
1737#define ADC_JOFR1_JOFFSET1_Pos (0U)
1738#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1739#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1741/****************** Bit definition for ADC_JOFR2 register *******************/
1742#define ADC_JOFR2_JOFFSET2_Pos (0U)
1743#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1744#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1746/****************** Bit definition for ADC_JOFR3 register *******************/
1747#define ADC_JOFR3_JOFFSET3_Pos (0U)
1748#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1749#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1751/****************** Bit definition for ADC_JOFR4 register *******************/
1752#define ADC_JOFR4_JOFFSET4_Pos (0U)
1753#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1754#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1756/******************* Bit definition for ADC_HTR register ********************/
1757#define ADC_HTR_HT_Pos (0U)
1758#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1759#define ADC_HTR_HT ADC_HTR_HT_Msk
1761/******************* Bit definition for ADC_LTR register ********************/
1762#define ADC_LTR_LT_Pos (0U)
1763#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1764#define ADC_LTR_LT ADC_LTR_LT_Msk
1766/******************* Bit definition for ADC_SQR1 register *******************/
1767#define ADC_SQR1_SQ13_Pos (0U)
1768#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1769#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1770#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1771#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1772#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1773#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1774#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1775#define ADC_SQR1_SQ14_Pos (5U)
1776#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1777#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1778#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1779#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1780#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1781#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1782#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1783#define ADC_SQR1_SQ15_Pos (10U)
1784#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1785#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1786#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1787#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1788#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1789#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1790#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1791#define ADC_SQR1_SQ16_Pos (15U)
1792#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1793#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1794#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1795#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1796#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1797#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1798#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1799#define ADC_SQR1_L_Pos (20U)
1800#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1801#define ADC_SQR1_L ADC_SQR1_L_Msk
1802#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1803#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1804#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1805#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1807/******************* Bit definition for ADC_SQR2 register *******************/
1808#define ADC_SQR2_SQ7_Pos (0U)
1809#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1810#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1811#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1812#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1813#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1814#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1815#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1816#define ADC_SQR2_SQ8_Pos (5U)
1817#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1818#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1819#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1820#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1821#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1822#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1823#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1824#define ADC_SQR2_SQ9_Pos (10U)
1825#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1826#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1827#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1828#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1829#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1830#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1831#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1832#define ADC_SQR2_SQ10_Pos (15U)
1833#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1834#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1835#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1836#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1837#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1838#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1839#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1840#define ADC_SQR2_SQ11_Pos (20U)
1841#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1842#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1843#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1844#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1845#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1846#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1847#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1848#define ADC_SQR2_SQ12_Pos (25U)
1849#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1850#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1851#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1852#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1853#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1854#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1855#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1857/******************* Bit definition for ADC_SQR3 register *******************/
1858#define ADC_SQR3_SQ1_Pos (0U)
1859#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1860#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1861#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1862#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1863#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1864#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1865#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1866#define ADC_SQR3_SQ2_Pos (5U)
1867#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1868#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1869#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1870#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1871#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1872#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1873#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1874#define ADC_SQR3_SQ3_Pos (10U)
1875#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1876#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1877#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1878#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1879#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1880#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1881#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1882#define ADC_SQR3_SQ4_Pos (15U)
1883#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1884#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1885#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1886#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1887#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1888#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1889#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1890#define ADC_SQR3_SQ5_Pos (20U)
1891#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1892#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1893#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1894#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1895#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1896#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1897#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1898#define ADC_SQR3_SQ6_Pos (25U)
1899#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1900#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1901#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1902#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1903#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1904#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1905#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1907/******************* Bit definition for ADC_JSQR register *******************/
1908#define ADC_JSQR_JSQ1_Pos (0U)
1909#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1910#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1911#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1912#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1913#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1914#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1915#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1916#define ADC_JSQR_JSQ2_Pos (5U)
1917#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1918#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1919#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1920#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1921#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1922#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1923#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1924#define ADC_JSQR_JSQ3_Pos (10U)
1925#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1926#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1927#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1928#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1929#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1930#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1931#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1932#define ADC_JSQR_JSQ4_Pos (15U)
1933#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1934#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1935#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1936#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1937#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1938#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1939#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1940#define ADC_JSQR_JL_Pos (20U)
1941#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1942#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1943#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1944#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1946/******************* Bit definition for ADC_JDR1 register *******************/
1947#define ADC_JDR1_JDATA_Pos (0U)
1948#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1949#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1951/******************* Bit definition for ADC_JDR2 register *******************/
1952#define ADC_JDR2_JDATA_Pos (0U)
1953#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1954#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1956/******************* Bit definition for ADC_JDR3 register *******************/
1957#define ADC_JDR3_JDATA_Pos (0U)
1958#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1959#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1961/******************* Bit definition for ADC_JDR4 register *******************/
1962#define ADC_JDR4_JDATA_Pos (0U)
1963#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1964#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1966/******************** Bit definition for ADC_DR register ********************/
1967#define ADC_DR_DATA_Pos (0U)
1968#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1969#define ADC_DR_DATA ADC_DR_DATA_Msk
1970#define ADC_DR_ADC2DATA_Pos (16U)
1971#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1972#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1974/******************* Bit definition for ADC_CSR register ********************/
1975#define ADC_CSR_AWD1_Pos (0U)
1976#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1977#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1978#define ADC_CSR_EOC1_Pos (1U)
1979#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1980#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1981#define ADC_CSR_JEOC1_Pos (2U)
1982#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1983#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1984#define ADC_CSR_JSTRT1_Pos (3U)
1985#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1986#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1987#define ADC_CSR_STRT1_Pos (4U)
1988#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1989#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1990#define ADC_CSR_OVR1_Pos (5U)
1991#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1992#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1993#define ADC_CSR_AWD2_Pos (8U)
1994#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1995#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1996#define ADC_CSR_EOC2_Pos (9U)
1997#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1998#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1999#define ADC_CSR_JEOC2_Pos (10U)
2000#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
2001#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
2002#define ADC_CSR_JSTRT2_Pos (11U)
2003#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
2004#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
2005#define ADC_CSR_STRT2_Pos (12U)
2006#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
2007#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
2008#define ADC_CSR_OVR2_Pos (13U)
2009#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
2010#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
2011#define ADC_CSR_AWD3_Pos (16U)
2012#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
2013#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
2014#define ADC_CSR_EOC3_Pos (17U)
2015#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
2016#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
2017#define ADC_CSR_JEOC3_Pos (18U)
2018#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
2019#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
2020#define ADC_CSR_JSTRT3_Pos (19U)
2021#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
2022#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
2023#define ADC_CSR_STRT3_Pos (20U)
2024#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
2025#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
2026#define ADC_CSR_OVR3_Pos (21U)
2027#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
2028#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
2030/* Legacy defines */
2031#define ADC_CSR_DOVR1 ADC_CSR_OVR1
2032#define ADC_CSR_DOVR2 ADC_CSR_OVR2
2033#define ADC_CSR_DOVR3 ADC_CSR_OVR3
2034
2035/******************* Bit definition for ADC_CCR register ********************/
2036#define ADC_CCR_MULTI_Pos (0U)
2037#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
2038#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
2039#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
2040#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
2041#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
2042#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
2043#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
2044#define ADC_CCR_DELAY_Pos (8U)
2045#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
2046#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
2047#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
2048#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
2049#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
2050#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
2051#define ADC_CCR_DDS_Pos (13U)
2052#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
2053#define ADC_CCR_DDS ADC_CCR_DDS_Msk
2054#define ADC_CCR_DMA_Pos (14U)
2055#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
2056#define ADC_CCR_DMA ADC_CCR_DMA_Msk
2057#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
2058#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
2059#define ADC_CCR_ADCPRE_Pos (16U)
2060#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
2061#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
2062#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
2063#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
2064#define ADC_CCR_VBATE_Pos (22U)
2065#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
2066#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
2067#define ADC_CCR_TSVREFE_Pos (23U)
2068#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
2069#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
2071/******************* Bit definition for ADC_CDR register ********************/
2072#define ADC_CDR_DATA1_Pos (0U)
2073#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
2074#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
2075#define ADC_CDR_DATA2_Pos (16U)
2076#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
2077#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
2079/* Legacy defines */
2080#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
2081#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
2082
2083/******************************************************************************/
2084/* */
2085/* Controller Area Network */
2086/* */
2087/******************************************************************************/
2089/******************* Bit definition for CAN_MCR register ********************/
2090#define CAN_MCR_INRQ_Pos (0U)
2091#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
2092#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
2093#define CAN_MCR_SLEEP_Pos (1U)
2094#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
2095#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
2096#define CAN_MCR_TXFP_Pos (2U)
2097#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
2098#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
2099#define CAN_MCR_RFLM_Pos (3U)
2100#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
2101#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
2102#define CAN_MCR_NART_Pos (4U)
2103#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
2104#define CAN_MCR_NART CAN_MCR_NART_Msk
2105#define CAN_MCR_AWUM_Pos (5U)
2106#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
2107#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
2108#define CAN_MCR_ABOM_Pos (6U)
2109#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
2110#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
2111#define CAN_MCR_TTCM_Pos (7U)
2112#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
2113#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
2114#define CAN_MCR_RESET_Pos (15U)
2115#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
2116#define CAN_MCR_RESET CAN_MCR_RESET_Msk
2117#define CAN_MCR_DBF_Pos (16U)
2118#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
2119#define CAN_MCR_DBF CAN_MCR_DBF_Msk
2120/******************* Bit definition for CAN_MSR register ********************/
2121#define CAN_MSR_INAK_Pos (0U)
2122#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
2123#define CAN_MSR_INAK CAN_MSR_INAK_Msk
2124#define CAN_MSR_SLAK_Pos (1U)
2125#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
2126#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
2127#define CAN_MSR_ERRI_Pos (2U)
2128#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
2129#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
2130#define CAN_MSR_WKUI_Pos (3U)
2131#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
2132#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
2133#define CAN_MSR_SLAKI_Pos (4U)
2134#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
2135#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
2136#define CAN_MSR_TXM_Pos (8U)
2137#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
2138#define CAN_MSR_TXM CAN_MSR_TXM_Msk
2139#define CAN_MSR_RXM_Pos (9U)
2140#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
2141#define CAN_MSR_RXM CAN_MSR_RXM_Msk
2142#define CAN_MSR_SAMP_Pos (10U)
2143#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
2144#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
2145#define CAN_MSR_RX_Pos (11U)
2146#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
2147#define CAN_MSR_RX CAN_MSR_RX_Msk
2149/******************* Bit definition for CAN_TSR register ********************/
2150#define CAN_TSR_RQCP0_Pos (0U)
2151#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
2152#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
2153#define CAN_TSR_TXOK0_Pos (1U)
2154#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
2155#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
2156#define CAN_TSR_ALST0_Pos (2U)
2157#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
2158#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
2159#define CAN_TSR_TERR0_Pos (3U)
2160#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
2161#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
2162#define CAN_TSR_ABRQ0_Pos (7U)
2163#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
2164#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
2165#define CAN_TSR_RQCP1_Pos (8U)
2166#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2167#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2168#define CAN_TSR_TXOK1_Pos (9U)
2169#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2170#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2171#define CAN_TSR_ALST1_Pos (10U)
2172#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2173#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2174#define CAN_TSR_TERR1_Pos (11U)
2175#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2176#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2177#define CAN_TSR_ABRQ1_Pos (15U)
2178#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2179#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2180#define CAN_TSR_RQCP2_Pos (16U)
2181#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2182#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2183#define CAN_TSR_TXOK2_Pos (17U)
2184#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2185#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2186#define CAN_TSR_ALST2_Pos (18U)
2187#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2188#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2189#define CAN_TSR_TERR2_Pos (19U)
2190#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2191#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2192#define CAN_TSR_ABRQ2_Pos (23U)
2193#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2194#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2195#define CAN_TSR_CODE_Pos (24U)
2196#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2197#define CAN_TSR_CODE CAN_TSR_CODE_Msk
2199#define CAN_TSR_TME_Pos (26U)
2200#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2201#define CAN_TSR_TME CAN_TSR_TME_Msk
2202#define CAN_TSR_TME0_Pos (26U)
2203#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2204#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2205#define CAN_TSR_TME1_Pos (27U)
2206#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2207#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2208#define CAN_TSR_TME2_Pos (28U)
2209#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2210#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2212#define CAN_TSR_LOW_Pos (29U)
2213#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2214#define CAN_TSR_LOW CAN_TSR_LOW_Msk
2215#define CAN_TSR_LOW0_Pos (29U)
2216#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2217#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2218#define CAN_TSR_LOW1_Pos (30U)
2219#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2220#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2221#define CAN_TSR_LOW2_Pos (31U)
2222#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2223#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2225/******************* Bit definition for CAN_RF0R register *******************/
2226#define CAN_RF0R_FMP0_Pos (0U)
2227#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2228#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2229#define CAN_RF0R_FULL0_Pos (3U)
2230#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2231#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2232#define CAN_RF0R_FOVR0_Pos (4U)
2233#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2234#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2235#define CAN_RF0R_RFOM0_Pos (5U)
2236#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2237#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2239/******************* Bit definition for CAN_RF1R register *******************/
2240#define CAN_RF1R_FMP1_Pos (0U)
2241#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2242#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2243#define CAN_RF1R_FULL1_Pos (3U)
2244#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2245#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2246#define CAN_RF1R_FOVR1_Pos (4U)
2247#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2248#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2249#define CAN_RF1R_RFOM1_Pos (5U)
2250#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2251#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2253/******************** Bit definition for CAN_IER register *******************/
2254#define CAN_IER_TMEIE_Pos (0U)
2255#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2256#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2257#define CAN_IER_FMPIE0_Pos (1U)
2258#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2259#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2260#define CAN_IER_FFIE0_Pos (2U)
2261#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2262#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2263#define CAN_IER_FOVIE0_Pos (3U)
2264#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2265#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2266#define CAN_IER_FMPIE1_Pos (4U)
2267#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2268#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2269#define CAN_IER_FFIE1_Pos (5U)
2270#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2271#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2272#define CAN_IER_FOVIE1_Pos (6U)
2273#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2274#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2275#define CAN_IER_EWGIE_Pos (8U)
2276#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2277#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2278#define CAN_IER_EPVIE_Pos (9U)
2279#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2280#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2281#define CAN_IER_BOFIE_Pos (10U)
2282#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2283#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2284#define CAN_IER_LECIE_Pos (11U)
2285#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2286#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2287#define CAN_IER_ERRIE_Pos (15U)
2288#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2289#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2290#define CAN_IER_WKUIE_Pos (16U)
2291#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2292#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2293#define CAN_IER_SLKIE_Pos (17U)
2294#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2295#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2296#define CAN_IER_EWGIE_Pos (8U)
2297
2298/******************** Bit definition for CAN_ESR register *******************/
2299#define CAN_ESR_EWGF_Pos (0U)
2300#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2301#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2302#define CAN_ESR_EPVF_Pos (1U)
2303#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2304#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2305#define CAN_ESR_BOFF_Pos (2U)
2306#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2307#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2309#define CAN_ESR_LEC_Pos (4U)
2310#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2311#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2312#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2313#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2314#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2316#define CAN_ESR_TEC_Pos (16U)
2317#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2318#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2319#define CAN_ESR_REC_Pos (24U)
2320#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2321#define CAN_ESR_REC CAN_ESR_REC_Msk
2323/******************* Bit definition for CAN_BTR register ********************/
2324#define CAN_BTR_BRP_Pos (0U)
2325#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2326#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2327#define CAN_BTR_TS1_Pos (16U)
2328#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2329#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2330#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2331#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2332#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2333#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2334#define CAN_BTR_TS2_Pos (20U)
2335#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2336#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2337#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2338#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2339#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2340#define CAN_BTR_SJW_Pos (24U)
2341#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2342#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2343#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2344#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2345#define CAN_BTR_LBKM_Pos (30U)
2346#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2347#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2348#define CAN_BTR_SILM_Pos (31U)
2349#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2350#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2354/****************** Bit definition for CAN_TI0R register ********************/
2355#define CAN_TI0R_TXRQ_Pos (0U)
2356#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2357#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2358#define CAN_TI0R_RTR_Pos (1U)
2359#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2360#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2361#define CAN_TI0R_IDE_Pos (2U)
2362#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2363#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2364#define CAN_TI0R_EXID_Pos (3U)
2365#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2366#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2367#define CAN_TI0R_STID_Pos (21U)
2368#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2369#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2371/****************** Bit definition for CAN_TDT0R register *******************/
2372#define CAN_TDT0R_DLC_Pos (0U)
2373#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2374#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2375#define CAN_TDT0R_TGT_Pos (8U)
2376#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2377#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2378#define CAN_TDT0R_TIME_Pos (16U)
2379#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2380#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2382/****************** Bit definition for CAN_TDL0R register *******************/
2383#define CAN_TDL0R_DATA0_Pos (0U)
2384#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2385#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2386#define CAN_TDL0R_DATA1_Pos (8U)
2387#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2388#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2389#define CAN_TDL0R_DATA2_Pos (16U)
2390#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2391#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2392#define CAN_TDL0R_DATA3_Pos (24U)
2393#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2394#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2396/****************** Bit definition for CAN_TDH0R register *******************/
2397#define CAN_TDH0R_DATA4_Pos (0U)
2398#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2399#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2400#define CAN_TDH0R_DATA5_Pos (8U)
2401#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2402#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2403#define CAN_TDH0R_DATA6_Pos (16U)
2404#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2405#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2406#define CAN_TDH0R_DATA7_Pos (24U)
2407#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2408#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2410/******************* Bit definition for CAN_TI1R register *******************/
2411#define CAN_TI1R_TXRQ_Pos (0U)
2412#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2413#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2414#define CAN_TI1R_RTR_Pos (1U)
2415#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2416#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2417#define CAN_TI1R_IDE_Pos (2U)
2418#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2419#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2420#define CAN_TI1R_EXID_Pos (3U)
2421#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2422#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2423#define CAN_TI1R_STID_Pos (21U)
2424#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2425#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2427/******************* Bit definition for CAN_TDT1R register ******************/
2428#define CAN_TDT1R_DLC_Pos (0U)
2429#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2430#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2431#define CAN_TDT1R_TGT_Pos (8U)
2432#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2433#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2434#define CAN_TDT1R_TIME_Pos (16U)
2435#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2436#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2438/******************* Bit definition for CAN_TDL1R register ******************/
2439#define CAN_TDL1R_DATA0_Pos (0U)
2440#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2441#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2442#define CAN_TDL1R_DATA1_Pos (8U)
2443#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2444#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2445#define CAN_TDL1R_DATA2_Pos (16U)
2446#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2447#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2448#define CAN_TDL1R_DATA3_Pos (24U)
2449#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2450#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2452/******************* Bit definition for CAN_TDH1R register ******************/
2453#define CAN_TDH1R_DATA4_Pos (0U)
2454#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2455#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2456#define CAN_TDH1R_DATA5_Pos (8U)
2457#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2458#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2459#define CAN_TDH1R_DATA6_Pos (16U)
2460#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2461#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2462#define CAN_TDH1R_DATA7_Pos (24U)
2463#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2464#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2466/******************* Bit definition for CAN_TI2R register *******************/
2467#define CAN_TI2R_TXRQ_Pos (0U)
2468#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2469#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2470#define CAN_TI2R_RTR_Pos (1U)
2471#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2472#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2473#define CAN_TI2R_IDE_Pos (2U)
2474#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2475#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2476#define CAN_TI2R_EXID_Pos (3U)
2477#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2478#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2479#define CAN_TI2R_STID_Pos (21U)
2480#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2481#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2483/******************* Bit definition for CAN_TDT2R register ******************/
2484#define CAN_TDT2R_DLC_Pos (0U)
2485#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2486#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2487#define CAN_TDT2R_TGT_Pos (8U)
2488#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2489#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2490#define CAN_TDT2R_TIME_Pos (16U)
2491#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2492#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2494/******************* Bit definition for CAN_TDL2R register ******************/
2495#define CAN_TDL2R_DATA0_Pos (0U)
2496#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2497#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2498#define CAN_TDL2R_DATA1_Pos (8U)
2499#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2500#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2501#define CAN_TDL2R_DATA2_Pos (16U)
2502#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2503#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2504#define CAN_TDL2R_DATA3_Pos (24U)
2505#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2506#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2508/******************* Bit definition for CAN_TDH2R register ******************/
2509#define CAN_TDH2R_DATA4_Pos (0U)
2510#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2511#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2512#define CAN_TDH2R_DATA5_Pos (8U)
2513#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2514#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2515#define CAN_TDH2R_DATA6_Pos (16U)
2516#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2517#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2518#define CAN_TDH2R_DATA7_Pos (24U)
2519#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2520#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2522/******************* Bit definition for CAN_RI0R register *******************/
2523#define CAN_RI0R_RTR_Pos (1U)
2524#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2525#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2526#define CAN_RI0R_IDE_Pos (2U)
2527#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2528#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2529#define CAN_RI0R_EXID_Pos (3U)
2530#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2531#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2532#define CAN_RI0R_STID_Pos (21U)
2533#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2534#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2536/******************* Bit definition for CAN_RDT0R register ******************/
2537#define CAN_RDT0R_DLC_Pos (0U)
2538#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2539#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2540#define CAN_RDT0R_FMI_Pos (8U)
2541#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2542#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2543#define CAN_RDT0R_TIME_Pos (16U)
2544#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2545#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2547/******************* Bit definition for CAN_RDL0R register ******************/
2548#define CAN_RDL0R_DATA0_Pos (0U)
2549#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2550#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2551#define CAN_RDL0R_DATA1_Pos (8U)
2552#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2553#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2554#define CAN_RDL0R_DATA2_Pos (16U)
2555#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2556#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2557#define CAN_RDL0R_DATA3_Pos (24U)
2558#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2559#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2561/******************* Bit definition for CAN_RDH0R register ******************/
2562#define CAN_RDH0R_DATA4_Pos (0U)
2563#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2564#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2565#define CAN_RDH0R_DATA5_Pos (8U)
2566#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2567#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2568#define CAN_RDH0R_DATA6_Pos (16U)
2569#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2570#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2571#define CAN_RDH0R_DATA7_Pos (24U)
2572#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2573#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2575/******************* Bit definition for CAN_RI1R register *******************/
2576#define CAN_RI1R_RTR_Pos (1U)
2577#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2578#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2579#define CAN_RI1R_IDE_Pos (2U)
2580#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2581#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2582#define CAN_RI1R_EXID_Pos (3U)
2583#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2584#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2585#define CAN_RI1R_STID_Pos (21U)
2586#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2587#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2589/******************* Bit definition for CAN_RDT1R register ******************/
2590#define CAN_RDT1R_DLC_Pos (0U)
2591#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2592#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2593#define CAN_RDT1R_FMI_Pos (8U)
2594#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2595#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2596#define CAN_RDT1R_TIME_Pos (16U)
2597#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2598#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2600/******************* Bit definition for CAN_RDL1R register ******************/
2601#define CAN_RDL1R_DATA0_Pos (0U)
2602#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2603#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2604#define CAN_RDL1R_DATA1_Pos (8U)
2605#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2606#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2607#define CAN_RDL1R_DATA2_Pos (16U)
2608#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2609#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2610#define CAN_RDL1R_DATA3_Pos (24U)
2611#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2612#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2614/******************* Bit definition for CAN_RDH1R register ******************/
2615#define CAN_RDH1R_DATA4_Pos (0U)
2616#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2617#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2618#define CAN_RDH1R_DATA5_Pos (8U)
2619#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2620#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2621#define CAN_RDH1R_DATA6_Pos (16U)
2622#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2623#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2624#define CAN_RDH1R_DATA7_Pos (24U)
2625#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2626#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2629/******************* Bit definition for CAN_FMR register ********************/
2630#define CAN_FMR_FINIT_Pos (0U)
2631#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2632#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2633#define CAN_FMR_CAN2SB_Pos (8U)
2634#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2635#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2637/******************* Bit definition for CAN_FM1R register *******************/
2638#define CAN_FM1R_FBM_Pos (0U)
2639#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2640#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2641#define CAN_FM1R_FBM0_Pos (0U)
2642#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2643#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2644#define CAN_FM1R_FBM1_Pos (1U)
2645#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2646#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2647#define CAN_FM1R_FBM2_Pos (2U)
2648#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2649#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2650#define CAN_FM1R_FBM3_Pos (3U)
2651#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2652#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2653#define CAN_FM1R_FBM4_Pos (4U)
2654#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2655#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2656#define CAN_FM1R_FBM5_Pos (5U)
2657#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2658#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2659#define CAN_FM1R_FBM6_Pos (6U)
2660#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2661#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2662#define CAN_FM1R_FBM7_Pos (7U)
2663#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2664#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2665#define CAN_FM1R_FBM8_Pos (8U)
2666#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2667#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2668#define CAN_FM1R_FBM9_Pos (9U)
2669#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2670#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2671#define CAN_FM1R_FBM10_Pos (10U)
2672#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2673#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2674#define CAN_FM1R_FBM11_Pos (11U)
2675#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2676#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2677#define CAN_FM1R_FBM12_Pos (12U)
2678#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2679#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2680#define CAN_FM1R_FBM13_Pos (13U)
2681#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2682#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2683#define CAN_FM1R_FBM14_Pos (14U)
2684#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2685#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2686#define CAN_FM1R_FBM15_Pos (15U)
2687#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2688#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2689#define CAN_FM1R_FBM16_Pos (16U)
2690#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2691#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2692#define CAN_FM1R_FBM17_Pos (17U)
2693#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2694#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2695#define CAN_FM1R_FBM18_Pos (18U)
2696#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2697#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2698#define CAN_FM1R_FBM19_Pos (19U)
2699#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2700#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2701#define CAN_FM1R_FBM20_Pos (20U)
2702#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2703#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2704#define CAN_FM1R_FBM21_Pos (21U)
2705#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2706#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2707#define CAN_FM1R_FBM22_Pos (22U)
2708#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2709#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2710#define CAN_FM1R_FBM23_Pos (23U)
2711#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2712#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2713#define CAN_FM1R_FBM24_Pos (24U)
2714#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2715#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2716#define CAN_FM1R_FBM25_Pos (25U)
2717#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2718#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2719#define CAN_FM1R_FBM26_Pos (26U)
2720#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2721#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2722#define CAN_FM1R_FBM27_Pos (27U)
2723#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2724#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2726/******************* Bit definition for CAN_FS1R register *******************/
2727#define CAN_FS1R_FSC_Pos (0U)
2728#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2729#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2730#define CAN_FS1R_FSC0_Pos (0U)
2731#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2732#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2733#define CAN_FS1R_FSC1_Pos (1U)
2734#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2735#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2736#define CAN_FS1R_FSC2_Pos (2U)
2737#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2738#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2739#define CAN_FS1R_FSC3_Pos (3U)
2740#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2741#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2742#define CAN_FS1R_FSC4_Pos (4U)
2743#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2744#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2745#define CAN_FS1R_FSC5_Pos (5U)
2746#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2747#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2748#define CAN_FS1R_FSC6_Pos (6U)
2749#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2750#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2751#define CAN_FS1R_FSC7_Pos (7U)
2752#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2753#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2754#define CAN_FS1R_FSC8_Pos (8U)
2755#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2756#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2757#define CAN_FS1R_FSC9_Pos (9U)
2758#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2759#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2760#define CAN_FS1R_FSC10_Pos (10U)
2761#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2762#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2763#define CAN_FS1R_FSC11_Pos (11U)
2764#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2765#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2766#define CAN_FS1R_FSC12_Pos (12U)
2767#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2768#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2769#define CAN_FS1R_FSC13_Pos (13U)
2770#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2771#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2772#define CAN_FS1R_FSC14_Pos (14U)
2773#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2774#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2775#define CAN_FS1R_FSC15_Pos (15U)
2776#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2777#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2778#define CAN_FS1R_FSC16_Pos (16U)
2779#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2780#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2781#define CAN_FS1R_FSC17_Pos (17U)
2782#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2783#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2784#define CAN_FS1R_FSC18_Pos (18U)
2785#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2786#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2787#define CAN_FS1R_FSC19_Pos (19U)
2788#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2789#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2790#define CAN_FS1R_FSC20_Pos (20U)
2791#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2792#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2793#define CAN_FS1R_FSC21_Pos (21U)
2794#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2795#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2796#define CAN_FS1R_FSC22_Pos (22U)
2797#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2798#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2799#define CAN_FS1R_FSC23_Pos (23U)
2800#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2801#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2802#define CAN_FS1R_FSC24_Pos (24U)
2803#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2804#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2805#define CAN_FS1R_FSC25_Pos (25U)
2806#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2807#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2808#define CAN_FS1R_FSC26_Pos (26U)
2809#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2810#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2811#define CAN_FS1R_FSC27_Pos (27U)
2812#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2813#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2815/****************** Bit definition for CAN_FFA1R register *******************/
2816#define CAN_FFA1R_FFA_Pos (0U)
2817#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2818#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2819#define CAN_FFA1R_FFA0_Pos (0U)
2820#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2821#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2822#define CAN_FFA1R_FFA1_Pos (1U)
2823#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2824#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2825#define CAN_FFA1R_FFA2_Pos (2U)
2826#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2827#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2828#define CAN_FFA1R_FFA3_Pos (3U)
2829#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2830#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2831#define CAN_FFA1R_FFA4_Pos (4U)
2832#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2833#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2834#define CAN_FFA1R_FFA5_Pos (5U)
2835#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2836#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2837#define CAN_FFA1R_FFA6_Pos (6U)
2838#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2839#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2840#define CAN_FFA1R_FFA7_Pos (7U)
2841#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2842#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2843#define CAN_FFA1R_FFA8_Pos (8U)
2844#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2845#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2846#define CAN_FFA1R_FFA9_Pos (9U)
2847#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2848#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2849#define CAN_FFA1R_FFA10_Pos (10U)
2850#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2851#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2852#define CAN_FFA1R_FFA11_Pos (11U)
2853#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2854#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2855#define CAN_FFA1R_FFA12_Pos (12U)
2856#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2857#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2858#define CAN_FFA1R_FFA13_Pos (13U)
2859#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2860#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2861#define CAN_FFA1R_FFA14_Pos (14U)
2862#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2863#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2864#define CAN_FFA1R_FFA15_Pos (15U)
2865#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2866#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2867#define CAN_FFA1R_FFA16_Pos (16U)
2868#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2869#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2870#define CAN_FFA1R_FFA17_Pos (17U)
2871#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2872#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2873#define CAN_FFA1R_FFA18_Pos (18U)
2874#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2875#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2876#define CAN_FFA1R_FFA19_Pos (19U)
2877#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2878#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2879#define CAN_FFA1R_FFA20_Pos (20U)
2880#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2881#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2882#define CAN_FFA1R_FFA21_Pos (21U)
2883#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2884#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2885#define CAN_FFA1R_FFA22_Pos (22U)
2886#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2887#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2888#define CAN_FFA1R_FFA23_Pos (23U)
2889#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2890#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2891#define CAN_FFA1R_FFA24_Pos (24U)
2892#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2893#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2894#define CAN_FFA1R_FFA25_Pos (25U)
2895#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2896#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2897#define CAN_FFA1R_FFA26_Pos (26U)
2898#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2899#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2900#define CAN_FFA1R_FFA27_Pos (27U)
2901#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2902#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2904/******************* Bit definition for CAN_FA1R register *******************/
2905#define CAN_FA1R_FACT_Pos (0U)
2906#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2907#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2908#define CAN_FA1R_FACT0_Pos (0U)
2909#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2910#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2911#define CAN_FA1R_FACT1_Pos (1U)
2912#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2913#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2914#define CAN_FA1R_FACT2_Pos (2U)
2915#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2916#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2917#define CAN_FA1R_FACT3_Pos (3U)
2918#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2919#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2920#define CAN_FA1R_FACT4_Pos (4U)
2921#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2922#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2923#define CAN_FA1R_FACT5_Pos (5U)
2924#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2925#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2926#define CAN_FA1R_FACT6_Pos (6U)
2927#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2928#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2929#define CAN_FA1R_FACT7_Pos (7U)
2930#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2931#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2932#define CAN_FA1R_FACT8_Pos (8U)
2933#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2934#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2935#define CAN_FA1R_FACT9_Pos (9U)
2936#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2937#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2938#define CAN_FA1R_FACT10_Pos (10U)
2939#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2940#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2941#define CAN_FA1R_FACT11_Pos (11U)
2942#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2943#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2944#define CAN_FA1R_FACT12_Pos (12U)
2945#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2946#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2947#define CAN_FA1R_FACT13_Pos (13U)
2948#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2949#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2950#define CAN_FA1R_FACT14_Pos (14U)
2951#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2952#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2953#define CAN_FA1R_FACT15_Pos (15U)
2954#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2955#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2956#define CAN_FA1R_FACT16_Pos (16U)
2957#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2958#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2959#define CAN_FA1R_FACT17_Pos (17U)
2960#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2961#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2962#define CAN_FA1R_FACT18_Pos (18U)
2963#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2964#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2965#define CAN_FA1R_FACT19_Pos (19U)
2966#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2967#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2968#define CAN_FA1R_FACT20_Pos (20U)
2969#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2970#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2971#define CAN_FA1R_FACT21_Pos (21U)
2972#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2973#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2974#define CAN_FA1R_FACT22_Pos (22U)
2975#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2976#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2977#define CAN_FA1R_FACT23_Pos (23U)
2978#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2979#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2980#define CAN_FA1R_FACT24_Pos (24U)
2981#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2982#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2983#define CAN_FA1R_FACT25_Pos (25U)
2984#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2985#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2986#define CAN_FA1R_FACT26_Pos (26U)
2987#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2988#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2989#define CAN_FA1R_FACT27_Pos (27U)
2990#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2991#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2994/******************* Bit definition for CAN_F0R1 register *******************/
2995#define CAN_F0R1_FB0_Pos (0U)
2996#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2997#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2998#define CAN_F0R1_FB1_Pos (1U)
2999#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
3000#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
3001#define CAN_F0R1_FB2_Pos (2U)
3002#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
3003#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
3004#define CAN_F0R1_FB3_Pos (3U)
3005#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
3006#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
3007#define CAN_F0R1_FB4_Pos (4U)
3008#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
3009#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
3010#define CAN_F0R1_FB5_Pos (5U)
3011#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
3012#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
3013#define CAN_F0R1_FB6_Pos (6U)
3014#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
3015#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
3016#define CAN_F0R1_FB7_Pos (7U)
3017#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
3018#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
3019#define CAN_F0R1_FB8_Pos (8U)
3020#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
3021#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
3022#define CAN_F0R1_FB9_Pos (9U)
3023#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
3024#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
3025#define CAN_F0R1_FB10_Pos (10U)
3026#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
3027#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
3028#define CAN_F0R1_FB11_Pos (11U)
3029#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
3030#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
3031#define CAN_F0R1_FB12_Pos (12U)
3032#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
3033#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
3034#define CAN_F0R1_FB13_Pos (13U)
3035#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
3036#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
3037#define CAN_F0R1_FB14_Pos (14U)
3038#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
3039#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
3040#define CAN_F0R1_FB15_Pos (15U)
3041#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
3042#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
3043#define CAN_F0R1_FB16_Pos (16U)
3044#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
3045#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
3046#define CAN_F0R1_FB17_Pos (17U)
3047#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
3048#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
3049#define CAN_F0R1_FB18_Pos (18U)
3050#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
3051#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
3052#define CAN_F0R1_FB19_Pos (19U)
3053#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
3054#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
3055#define CAN_F0R1_FB20_Pos (20U)
3056#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
3057#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
3058#define CAN_F0R1_FB21_Pos (21U)
3059#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
3060#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
3061#define CAN_F0R1_FB22_Pos (22U)
3062#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
3063#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
3064#define CAN_F0R1_FB23_Pos (23U)
3065#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
3066#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
3067#define CAN_F0R1_FB24_Pos (24U)
3068#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
3069#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
3070#define CAN_F0R1_FB25_Pos (25U)
3071#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
3072#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
3073#define CAN_F0R1_FB26_Pos (26U)
3074#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
3075#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
3076#define CAN_F0R1_FB27_Pos (27U)
3077#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
3078#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
3079#define CAN_F0R1_FB28_Pos (28U)
3080#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
3081#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
3082#define CAN_F0R1_FB29_Pos (29U)
3083#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
3084#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
3085#define CAN_F0R1_FB30_Pos (30U)
3086#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
3087#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
3088#define CAN_F0R1_FB31_Pos (31U)
3089#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
3090#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
3092/******************* Bit definition for CAN_F1R1 register *******************/
3093#define CAN_F1R1_FB0_Pos (0U)
3094#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
3095#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
3096#define CAN_F1R1_FB1_Pos (1U)
3097#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
3098#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
3099#define CAN_F1R1_FB2_Pos (2U)
3100#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
3101#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
3102#define CAN_F1R1_FB3_Pos (3U)
3103#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
3104#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
3105#define CAN_F1R1_FB4_Pos (4U)
3106#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
3107#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
3108#define CAN_F1R1_FB5_Pos (5U)
3109#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
3110#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
3111#define CAN_F1R1_FB6_Pos (6U)
3112#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
3113#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
3114#define CAN_F1R1_FB7_Pos (7U)
3115#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
3116#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
3117#define CAN_F1R1_FB8_Pos (8U)
3118#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
3119#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
3120#define CAN_F1R1_FB9_Pos (9U)
3121#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
3122#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
3123#define CAN_F1R1_FB10_Pos (10U)
3124#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
3125#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
3126#define CAN_F1R1_FB11_Pos (11U)
3127#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
3128#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
3129#define CAN_F1R1_FB12_Pos (12U)
3130#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
3131#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
3132#define CAN_F1R1_FB13_Pos (13U)
3133#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
3134#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
3135#define CAN_F1R1_FB14_Pos (14U)
3136#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
3137#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
3138#define CAN_F1R1_FB15_Pos (15U)
3139#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
3140#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
3141#define CAN_F1R1_FB16_Pos (16U)
3142#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
3143#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
3144#define CAN_F1R1_FB17_Pos (17U)
3145#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
3146#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
3147#define CAN_F1R1_FB18_Pos (18U)
3148#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
3149#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
3150#define CAN_F1R1_FB19_Pos (19U)
3151#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
3152#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
3153#define CAN_F1R1_FB20_Pos (20U)
3154#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
3155#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
3156#define CAN_F1R1_FB21_Pos (21U)
3157#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
3158#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
3159#define CAN_F1R1_FB22_Pos (22U)
3160#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
3161#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
3162#define CAN_F1R1_FB23_Pos (23U)
3163#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
3164#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
3165#define CAN_F1R1_FB24_Pos (24U)
3166#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
3167#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
3168#define CAN_F1R1_FB25_Pos (25U)
3169#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
3170#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
3171#define CAN_F1R1_FB26_Pos (26U)
3172#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
3173#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
3174#define CAN_F1R1_FB27_Pos (27U)
3175#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3176#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3177#define CAN_F1R1_FB28_Pos (28U)
3178#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3179#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3180#define CAN_F1R1_FB29_Pos (29U)
3181#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3182#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3183#define CAN_F1R1_FB30_Pos (30U)
3184#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3185#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3186#define CAN_F1R1_FB31_Pos (31U)
3187#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3188#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3190/******************* Bit definition for CAN_F2R1 register *******************/
3191#define CAN_F2R1_FB0_Pos (0U)
3192#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
3193#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
3194#define CAN_F2R1_FB1_Pos (1U)
3195#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
3196#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
3197#define CAN_F2R1_FB2_Pos (2U)
3198#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
3199#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
3200#define CAN_F2R1_FB3_Pos (3U)
3201#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
3202#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
3203#define CAN_F2R1_FB4_Pos (4U)
3204#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
3205#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
3206#define CAN_F2R1_FB5_Pos (5U)
3207#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
3208#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
3209#define CAN_F2R1_FB6_Pos (6U)
3210#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
3211#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
3212#define CAN_F2R1_FB7_Pos (7U)
3213#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
3214#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
3215#define CAN_F2R1_FB8_Pos (8U)
3216#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
3217#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
3218#define CAN_F2R1_FB9_Pos (9U)
3219#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
3220#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
3221#define CAN_F2R1_FB10_Pos (10U)
3222#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
3223#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
3224#define CAN_F2R1_FB11_Pos (11U)
3225#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
3226#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
3227#define CAN_F2R1_FB12_Pos (12U)
3228#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
3229#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
3230#define CAN_F2R1_FB13_Pos (13U)
3231#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
3232#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
3233#define CAN_F2R1_FB14_Pos (14U)
3234#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
3235#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
3236#define CAN_F2R1_FB15_Pos (15U)
3237#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
3238#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
3239#define CAN_F2R1_FB16_Pos (16U)
3240#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
3241#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
3242#define CAN_F2R1_FB17_Pos (17U)
3243#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
3244#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
3245#define CAN_F2R1_FB18_Pos (18U)
3246#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
3247#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
3248#define CAN_F2R1_FB19_Pos (19U)
3249#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
3250#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
3251#define CAN_F2R1_FB20_Pos (20U)
3252#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
3253#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
3254#define CAN_F2R1_FB21_Pos (21U)
3255#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
3256#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
3257#define CAN_F2R1_FB22_Pos (22U)
3258#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
3259#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
3260#define CAN_F2R1_FB23_Pos (23U)
3261#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
3262#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
3263#define CAN_F2R1_FB24_Pos (24U)
3264#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
3265#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
3266#define CAN_F2R1_FB25_Pos (25U)
3267#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
3268#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
3269#define CAN_F2R1_FB26_Pos (26U)
3270#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
3271#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
3272#define CAN_F2R1_FB27_Pos (27U)
3273#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
3274#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3275#define CAN_F2R1_FB28_Pos (28U)
3276#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3277#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3278#define CAN_F2R1_FB29_Pos (29U)
3279#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3280#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3281#define CAN_F2R1_FB30_Pos (30U)
3282#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3283#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3284#define CAN_F2R1_FB31_Pos (31U)
3285#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3286#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3288/******************* Bit definition for CAN_F3R1 register *******************/
3289#define CAN_F3R1_FB0_Pos (0U)
3290#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3291#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3292#define CAN_F3R1_FB1_Pos (1U)
3293#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3294#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3295#define CAN_F3R1_FB2_Pos (2U)
3296#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3297#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3298#define CAN_F3R1_FB3_Pos (3U)
3299#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3300#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3301#define CAN_F3R1_FB4_Pos (4U)
3302#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3303#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3304#define CAN_F3R1_FB5_Pos (5U)
3305#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3306#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3307#define CAN_F3R1_FB6_Pos (6U)
3308#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3309#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3310#define CAN_F3R1_FB7_Pos (7U)
3311#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3312#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3313#define CAN_F3R1_FB8_Pos (8U)
3314#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3315#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3316#define CAN_F3R1_FB9_Pos (9U)
3317#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3318#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3319#define CAN_F3R1_FB10_Pos (10U)
3320#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3321#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3322#define CAN_F3R1_FB11_Pos (11U)
3323#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3324#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3325#define CAN_F3R1_FB12_Pos (12U)
3326#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3327#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3328#define CAN_F3R1_FB13_Pos (13U)
3329#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3330#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3331#define CAN_F3R1_FB14_Pos (14U)
3332#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3333#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3334#define CAN_F3R1_FB15_Pos (15U)
3335#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3336#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3337#define CAN_F3R1_FB16_Pos (16U)
3338#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3339#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3340#define CAN_F3R1_FB17_Pos (17U)
3341#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3342#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3343#define CAN_F3R1_FB18_Pos (18U)
3344#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3345#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3346#define CAN_F3R1_FB19_Pos (19U)
3347#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3348#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3349#define CAN_F3R1_FB20_Pos (20U)
3350#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3351#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3352#define CAN_F3R1_FB21_Pos (21U)
3353#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3354#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3355#define CAN_F3R1_FB22_Pos (22U)
3356#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3357#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3358#define CAN_F3R1_FB23_Pos (23U)
3359#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3360#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3361#define CAN_F3R1_FB24_Pos (24U)
3362#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3363#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3364#define CAN_F3R1_FB25_Pos (25U)
3365#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3366#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3367#define CAN_F3R1_FB26_Pos (26U)
3368#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3369#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3370#define CAN_F3R1_FB27_Pos (27U)
3371#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3372#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3373#define CAN_F3R1_FB28_Pos (28U)
3374#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3375#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3376#define CAN_F3R1_FB29_Pos (29U)
3377#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3378#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3379#define CAN_F3R1_FB30_Pos (30U)
3380#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3381#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3382#define CAN_F3R1_FB31_Pos (31U)
3383#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3384#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3386/******************* Bit definition for CAN_F4R1 register *******************/
3387#define CAN_F4R1_FB0_Pos (0U)
3388#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3389#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3390#define CAN_F4R1_FB1_Pos (1U)
3391#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3392#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3393#define CAN_F4R1_FB2_Pos (2U)
3394#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3395#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3396#define CAN_F4R1_FB3_Pos (3U)
3397#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3398#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3399#define CAN_F4R1_FB4_Pos (4U)
3400#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3401#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3402#define CAN_F4R1_FB5_Pos (5U)
3403#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3404#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3405#define CAN_F4R1_FB6_Pos (6U)
3406#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3407#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3408#define CAN_F4R1_FB7_Pos (7U)
3409#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3410#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3411#define CAN_F4R1_FB8_Pos (8U)
3412#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3413#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3414#define CAN_F4R1_FB9_Pos (9U)
3415#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3416#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3417#define CAN_F4R1_FB10_Pos (10U)
3418#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3419#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3420#define CAN_F4R1_FB11_Pos (11U)
3421#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3422#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3423#define CAN_F4R1_FB12_Pos (12U)
3424#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3425#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3426#define CAN_F4R1_FB13_Pos (13U)
3427#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3428#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3429#define CAN_F4R1_FB14_Pos (14U)
3430#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3431#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3432#define CAN_F4R1_FB15_Pos (15U)
3433#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3434#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3435#define CAN_F4R1_FB16_Pos (16U)
3436#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3437#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3438#define CAN_F4R1_FB17_Pos (17U)
3439#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3440#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3441#define CAN_F4R1_FB18_Pos (18U)
3442#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3443#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3444#define CAN_F4R1_FB19_Pos (19U)
3445#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3446#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3447#define CAN_F4R1_FB20_Pos (20U)
3448#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3449#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3450#define CAN_F4R1_FB21_Pos (21U)
3451#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3452#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3453#define CAN_F4R1_FB22_Pos (22U)
3454#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3455#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3456#define CAN_F4R1_FB23_Pos (23U)
3457#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3458#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3459#define CAN_F4R1_FB24_Pos (24U)
3460#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3461#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3462#define CAN_F4R1_FB25_Pos (25U)
3463#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3464#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3465#define CAN_F4R1_FB26_Pos (26U)
3466#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3467#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3468#define CAN_F4R1_FB27_Pos (27U)
3469#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3470#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3471#define CAN_F4R1_FB28_Pos (28U)
3472#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3473#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3474#define CAN_F4R1_FB29_Pos (29U)
3475#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3476#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3477#define CAN_F4R1_FB30_Pos (30U)
3478#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3479#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3480#define CAN_F4R1_FB31_Pos (31U)
3481#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3482#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3484/******************* Bit definition for CAN_F5R1 register *******************/
3485#define CAN_F5R1_FB0_Pos (0U)
3486#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3487#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3488#define CAN_F5R1_FB1_Pos (1U)
3489#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3490#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3491#define CAN_F5R1_FB2_Pos (2U)
3492#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3493#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3494#define CAN_F5R1_FB3_Pos (3U)
3495#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3496#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3497#define CAN_F5R1_FB4_Pos (4U)
3498#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3499#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3500#define CAN_F5R1_FB5_Pos (5U)
3501#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3502#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3503#define CAN_F5R1_FB6_Pos (6U)
3504#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3505#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3506#define CAN_F5R1_FB7_Pos (7U)
3507#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3508#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3509#define CAN_F5R1_FB8_Pos (8U)
3510#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3511#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3512#define CAN_F5R1_FB9_Pos (9U)
3513#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3514#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3515#define CAN_F5R1_FB10_Pos (10U)
3516#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3517#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3518#define CAN_F5R1_FB11_Pos (11U)
3519#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3520#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3521#define CAN_F5R1_FB12_Pos (12U)
3522#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3523#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3524#define CAN_F5R1_FB13_Pos (13U)
3525#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3526#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3527#define CAN_F5R1_FB14_Pos (14U)
3528#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3529#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3530#define CAN_F5R1_FB15_Pos (15U)
3531#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3532#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3533#define CAN_F5R1_FB16_Pos (16U)
3534#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3535#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3536#define CAN_F5R1_FB17_Pos (17U)
3537#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3538#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3539#define CAN_F5R1_FB18_Pos (18U)
3540#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3541#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3542#define CAN_F5R1_FB19_Pos (19U)
3543#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3544#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3545#define CAN_F5R1_FB20_Pos (20U)
3546#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3547#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3548#define CAN_F5R1_FB21_Pos (21U)
3549#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3550#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3551#define CAN_F5R1_FB22_Pos (22U)
3552#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3553#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3554#define CAN_F5R1_FB23_Pos (23U)
3555#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3556#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3557#define CAN_F5R1_FB24_Pos (24U)
3558#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3559#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3560#define CAN_F5R1_FB25_Pos (25U)
3561#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3562#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3563#define CAN_F5R1_FB26_Pos (26U)
3564#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3565#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3566#define CAN_F5R1_FB27_Pos (27U)
3567#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3568#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3569#define CAN_F5R1_FB28_Pos (28U)
3570#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3571#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3572#define CAN_F5R1_FB29_Pos (29U)
3573#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3574#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3575#define CAN_F5R1_FB30_Pos (30U)
3576#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3577#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3578#define CAN_F5R1_FB31_Pos (31U)
3579#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3580#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3582/******************* Bit definition for CAN_F6R1 register *******************/
3583#define CAN_F6R1_FB0_Pos (0U)
3584#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3585#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3586#define CAN_F6R1_FB1_Pos (1U)
3587#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3588#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3589#define CAN_F6R1_FB2_Pos (2U)
3590#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3591#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3592#define CAN_F6R1_FB3_Pos (3U)
3593#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3594#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3595#define CAN_F6R1_FB4_Pos (4U)
3596#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3597#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3598#define CAN_F6R1_FB5_Pos (5U)
3599#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3600#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3601#define CAN_F6R1_FB6_Pos (6U)
3602#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3603#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3604#define CAN_F6R1_FB7_Pos (7U)
3605#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3606#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3607#define CAN_F6R1_FB8_Pos (8U)
3608#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3609#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3610#define CAN_F6R1_FB9_Pos (9U)
3611#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3612#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3613#define CAN_F6R1_FB10_Pos (10U)
3614#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3615#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3616#define CAN_F6R1_FB11_Pos (11U)
3617#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3618#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3619#define CAN_F6R1_FB12_Pos (12U)
3620#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3621#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3622#define CAN_F6R1_FB13_Pos (13U)
3623#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3624#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3625#define CAN_F6R1_FB14_Pos (14U)
3626#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3627#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3628#define CAN_F6R1_FB15_Pos (15U)
3629#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3630#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3631#define CAN_F6R1_FB16_Pos (16U)
3632#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3633#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3634#define CAN_F6R1_FB17_Pos (17U)
3635#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3636#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3637#define CAN_F6R1_FB18_Pos (18U)
3638#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3639#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3640#define CAN_F6R1_FB19_Pos (19U)
3641#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3642#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3643#define CAN_F6R1_FB20_Pos (20U)
3644#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3645#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3646#define CAN_F6R1_FB21_Pos (21U)
3647#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3648#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3649#define CAN_F6R1_FB22_Pos (22U)
3650#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3651#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3652#define CAN_F6R1_FB23_Pos (23U)
3653#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3654#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3655#define CAN_F6R1_FB24_Pos (24U)
3656#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3657#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3658#define CAN_F6R1_FB25_Pos (25U)
3659#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3660#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3661#define CAN_F6R1_FB26_Pos (26U)
3662#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3663#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3664#define CAN_F6R1_FB27_Pos (27U)
3665#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3666#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3667#define CAN_F6R1_FB28_Pos (28U)
3668#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3669#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3670#define CAN_F6R1_FB29_Pos (29U)
3671#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3672#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3673#define CAN_F6R1_FB30_Pos (30U)
3674#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3675#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3676#define CAN_F6R1_FB31_Pos (31U)
3677#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3678#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3680/******************* Bit definition for CAN_F7R1 register *******************/
3681#define CAN_F7R1_FB0_Pos (0U)
3682#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3683#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3684#define CAN_F7R1_FB1_Pos (1U)
3685#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3686#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3687#define CAN_F7R1_FB2_Pos (2U)
3688#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3689#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3690#define CAN_F7R1_FB3_Pos (3U)
3691#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3692#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3693#define CAN_F7R1_FB4_Pos (4U)
3694#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3695#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3696#define CAN_F7R1_FB5_Pos (5U)
3697#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3698#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3699#define CAN_F7R1_FB6_Pos (6U)
3700#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3701#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3702#define CAN_F7R1_FB7_Pos (7U)
3703#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3704#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3705#define CAN_F7R1_FB8_Pos (8U)
3706#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3707#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3708#define CAN_F7R1_FB9_Pos (9U)
3709#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3710#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3711#define CAN_F7R1_FB10_Pos (10U)
3712#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3713#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3714#define CAN_F7R1_FB11_Pos (11U)
3715#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3716#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3717#define CAN_F7R1_FB12_Pos (12U)
3718#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3719#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3720#define CAN_F7R1_FB13_Pos (13U)
3721#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3722#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3723#define CAN_F7R1_FB14_Pos (14U)
3724#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3725#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3726#define CAN_F7R1_FB15_Pos (15U)
3727#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3728#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3729#define CAN_F7R1_FB16_Pos (16U)
3730#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3731#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3732#define CAN_F7R1_FB17_Pos (17U)
3733#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3734#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3735#define CAN_F7R1_FB18_Pos (18U)
3736#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3737#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3738#define CAN_F7R1_FB19_Pos (19U)
3739#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3740#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3741#define CAN_F7R1_FB20_Pos (20U)
3742#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3743#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3744#define CAN_F7R1_FB21_Pos (21U)
3745#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3746#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3747#define CAN_F7R1_FB22_Pos (22U)
3748#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3749#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3750#define CAN_F7R1_FB23_Pos (23U)
3751#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3752#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3753#define CAN_F7R1_FB24_Pos (24U)
3754#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3755#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3756#define CAN_F7R1_FB25_Pos (25U)
3757#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3758#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3759#define CAN_F7R1_FB26_Pos (26U)
3760#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3761#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3762#define CAN_F7R1_FB27_Pos (27U)
3763#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3764#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3765#define CAN_F7R1_FB28_Pos (28U)
3766#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3767#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3768#define CAN_F7R1_FB29_Pos (29U)
3769#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3770#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3771#define CAN_F7R1_FB30_Pos (30U)
3772#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3773#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3774#define CAN_F7R1_FB31_Pos (31U)
3775#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3776#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3778/******************* Bit definition for CAN_F8R1 register *******************/
3779#define CAN_F8R1_FB0_Pos (0U)
3780#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3781#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3782#define CAN_F8R1_FB1_Pos (1U)
3783#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3784#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3785#define CAN_F8R1_FB2_Pos (2U)
3786#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3787#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3788#define CAN_F8R1_FB3_Pos (3U)
3789#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3790#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3791#define CAN_F8R1_FB4_Pos (4U)
3792#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3793#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3794#define CAN_F8R1_FB5_Pos (5U)
3795#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3796#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3797#define CAN_F8R1_FB6_Pos (6U)
3798#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3799#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3800#define CAN_F8R1_FB7_Pos (7U)
3801#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3802#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3803#define CAN_F8R1_FB8_Pos (8U)
3804#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3805#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3806#define CAN_F8R1_FB9_Pos (9U)
3807#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3808#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3809#define CAN_F8R1_FB10_Pos (10U)
3810#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3811#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3812#define CAN_F8R1_FB11_Pos (11U)
3813#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3814#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3815#define CAN_F8R1_FB12_Pos (12U)
3816#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3817#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3818#define CAN_F8R1_FB13_Pos (13U)
3819#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3820#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3821#define CAN_F8R1_FB14_Pos (14U)
3822#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3823#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3824#define CAN_F8R1_FB15_Pos (15U)
3825#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3826#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3827#define CAN_F8R1_FB16_Pos (16U)
3828#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3829#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3830#define CAN_F8R1_FB17_Pos (17U)
3831#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3832#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3833#define CAN_F8R1_FB18_Pos (18U)
3834#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3835#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3836#define CAN_F8R1_FB19_Pos (19U)
3837#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3838#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3839#define CAN_F8R1_FB20_Pos (20U)
3840#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3841#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3842#define CAN_F8R1_FB21_Pos (21U)
3843#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3844#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3845#define CAN_F8R1_FB22_Pos (22U)
3846#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3847#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3848#define CAN_F8R1_FB23_Pos (23U)
3849#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3850#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3851#define CAN_F8R1_FB24_Pos (24U)
3852#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3853#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3854#define CAN_F8R1_FB25_Pos (25U)
3855#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3856#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3857#define CAN_F8R1_FB26_Pos (26U)
3858#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3859#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3860#define CAN_F8R1_FB27_Pos (27U)
3861#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3862#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3863#define CAN_F8R1_FB28_Pos (28U)
3864#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3865#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3866#define CAN_F8R1_FB29_Pos (29U)
3867#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3868#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3869#define CAN_F8R1_FB30_Pos (30U)
3870#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3871#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3872#define CAN_F8R1_FB31_Pos (31U)
3873#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3874#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3876/******************* Bit definition for CAN_F9R1 register *******************/
3877#define CAN_F9R1_FB0_Pos (0U)
3878#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3879#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3880#define CAN_F9R1_FB1_Pos (1U)
3881#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3882#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3883#define CAN_F9R1_FB2_Pos (2U)
3884#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3885#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3886#define CAN_F9R1_FB3_Pos (3U)
3887#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3888#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3889#define CAN_F9R1_FB4_Pos (4U)
3890#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3891#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3892#define CAN_F9R1_FB5_Pos (5U)
3893#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3894#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3895#define CAN_F9R1_FB6_Pos (6U)
3896#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3897#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3898#define CAN_F9R1_FB7_Pos (7U)
3899#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3900#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3901#define CAN_F9R1_FB8_Pos (8U)
3902#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3903#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3904#define CAN_F9R1_FB9_Pos (9U)
3905#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3906#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3907#define CAN_F9R1_FB10_Pos (10U)
3908#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3909#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3910#define CAN_F9R1_FB11_Pos (11U)
3911#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3912#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3913#define CAN_F9R1_FB12_Pos (12U)
3914#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3915#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3916#define CAN_F9R1_FB13_Pos (13U)
3917#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3918#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3919#define CAN_F9R1_FB14_Pos (14U)
3920#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3921#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3922#define CAN_F9R1_FB15_Pos (15U)
3923#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3924#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3925#define CAN_F9R1_FB16_Pos (16U)
3926#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3927#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3928#define CAN_F9R1_FB17_Pos (17U)
3929#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3930#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3931#define CAN_F9R1_FB18_Pos (18U)
3932#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3933#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3934#define CAN_F9R1_FB19_Pos (19U)
3935#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3936#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3937#define CAN_F9R1_FB20_Pos (20U)
3938#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3939#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3940#define CAN_F9R1_FB21_Pos (21U)
3941#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3942#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3943#define CAN_F9R1_FB22_Pos (22U)
3944#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3945#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3946#define CAN_F9R1_FB23_Pos (23U)
3947#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3948#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3949#define CAN_F9R1_FB24_Pos (24U)
3950#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3951#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3952#define CAN_F9R1_FB25_Pos (25U)
3953#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3954#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3955#define CAN_F9R1_FB26_Pos (26U)
3956#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3957#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3958#define CAN_F9R1_FB27_Pos (27U)
3959#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3960#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3961#define CAN_F9R1_FB28_Pos (28U)
3962#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3963#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3964#define CAN_F9R1_FB29_Pos (29U)
3965#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3966#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3967#define CAN_F9R1_FB30_Pos (30U)
3968#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3969#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3970#define CAN_F9R1_FB31_Pos (31U)
3971#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3972#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3974/******************* Bit definition for CAN_F10R1 register ******************/
3975#define CAN_F10R1_FB0_Pos (0U)
3976#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3977#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3978#define CAN_F10R1_FB1_Pos (1U)
3979#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3980#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3981#define CAN_F10R1_FB2_Pos (2U)
3982#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3983#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3984#define CAN_F10R1_FB3_Pos (3U)
3985#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3986#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3987#define CAN_F10R1_FB4_Pos (4U)
3988#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3989#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3990#define CAN_F10R1_FB5_Pos (5U)
3991#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3992#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3993#define CAN_F10R1_FB6_Pos (6U)
3994#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3995#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3996#define CAN_F10R1_FB7_Pos (7U)
3997#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3998#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3999#define CAN_F10R1_FB8_Pos (8U)
4000#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
4001#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
4002#define CAN_F10R1_FB9_Pos (9U)
4003#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
4004#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
4005#define CAN_F10R1_FB10_Pos (10U)
4006#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
4007#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
4008#define CAN_F10R1_FB11_Pos (11U)
4009#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
4010#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
4011#define CAN_F10R1_FB12_Pos (12U)
4012#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
4013#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
4014#define CAN_F10R1_FB13_Pos (13U)
4015#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
4016#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
4017#define CAN_F10R1_FB14_Pos (14U)
4018#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
4019#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
4020#define CAN_F10R1_FB15_Pos (15U)
4021#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
4022#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
4023#define CAN_F10R1_FB16_Pos (16U)
4024#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
4025#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
4026#define CAN_F10R1_FB17_Pos (17U)
4027#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
4028#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
4029#define CAN_F10R1_FB18_Pos (18U)
4030#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
4031#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
4032#define CAN_F10R1_FB19_Pos (19U)
4033#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
4034#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
4035#define CAN_F10R1_FB20_Pos (20U)
4036#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
4037#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
4038#define CAN_F10R1_FB21_Pos (21U)
4039#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
4040#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
4041#define CAN_F10R1_FB22_Pos (22U)
4042#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
4043#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
4044#define CAN_F10R1_FB23_Pos (23U)
4045#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
4046#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
4047#define CAN_F10R1_FB24_Pos (24U)
4048#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
4049#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
4050#define CAN_F10R1_FB25_Pos (25U)
4051#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
4052#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
4053#define CAN_F10R1_FB26_Pos (26U)
4054#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
4055#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
4056#define CAN_F10R1_FB27_Pos (27U)
4057#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
4058#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
4059#define CAN_F10R1_FB28_Pos (28U)
4060#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
4061#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
4062#define CAN_F10R1_FB29_Pos (29U)
4063#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
4064#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
4065#define CAN_F10R1_FB30_Pos (30U)
4066#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
4067#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
4068#define CAN_F10R1_FB31_Pos (31U)
4069#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
4070#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
4072/******************* Bit definition for CAN_F11R1 register ******************/
4073#define CAN_F11R1_FB0_Pos (0U)
4074#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
4075#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
4076#define CAN_F11R1_FB1_Pos (1U)
4077#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
4078#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
4079#define CAN_F11R1_FB2_Pos (2U)
4080#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
4081#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
4082#define CAN_F11R1_FB3_Pos (3U)
4083#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
4084#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
4085#define CAN_F11R1_FB4_Pos (4U)
4086#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
4087#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
4088#define CAN_F11R1_FB5_Pos (5U)
4089#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
4090#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
4091#define CAN_F11R1_FB6_Pos (6U)
4092#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
4093#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
4094#define CAN_F11R1_FB7_Pos (7U)
4095#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
4096#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
4097#define CAN_F11R1_FB8_Pos (8U)
4098#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
4099#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
4100#define CAN_F11R1_FB9_Pos (9U)
4101#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
4102#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
4103#define CAN_F11R1_FB10_Pos (10U)
4104#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
4105#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
4106#define CAN_F11R1_FB11_Pos (11U)
4107#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
4108#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
4109#define CAN_F11R1_FB12_Pos (12U)
4110#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
4111#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
4112#define CAN_F11R1_FB13_Pos (13U)
4113#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
4114#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
4115#define CAN_F11R1_FB14_Pos (14U)
4116#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
4117#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
4118#define CAN_F11R1_FB15_Pos (15U)
4119#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
4120#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
4121#define CAN_F11R1_FB16_Pos (16U)
4122#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
4123#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
4124#define CAN_F11R1_FB17_Pos (17U)
4125#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
4126#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
4127#define CAN_F11R1_FB18_Pos (18U)
4128#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
4129#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
4130#define CAN_F11R1_FB19_Pos (19U)
4131#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
4132#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
4133#define CAN_F11R1_FB20_Pos (20U)
4134#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
4135#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
4136#define CAN_F11R1_FB21_Pos (21U)
4137#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
4138#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
4139#define CAN_F11R1_FB22_Pos (22U)
4140#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
4141#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
4142#define CAN_F11R1_FB23_Pos (23U)
4143#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
4144#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
4145#define CAN_F11R1_FB24_Pos (24U)
4146#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
4147#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
4148#define CAN_F11R1_FB25_Pos (25U)
4149#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
4150#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
4151#define CAN_F11R1_FB26_Pos (26U)
4152#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
4153#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
4154#define CAN_F11R1_FB27_Pos (27U)
4155#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
4156#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
4157#define CAN_F11R1_FB28_Pos (28U)
4158#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
4159#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
4160#define CAN_F11R1_FB29_Pos (29U)
4161#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
4162#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
4163#define CAN_F11R1_FB30_Pos (30U)
4164#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
4165#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
4166#define CAN_F11R1_FB31_Pos (31U)
4167#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
4168#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
4170/******************* Bit definition for CAN_F12R1 register ******************/
4171#define CAN_F12R1_FB0_Pos (0U)
4172#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
4173#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
4174#define CAN_F12R1_FB1_Pos (1U)
4175#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4176#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4177#define CAN_F12R1_FB2_Pos (2U)
4178#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4179#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4180#define CAN_F12R1_FB3_Pos (3U)
4181#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4182#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4183#define CAN_F12R1_FB4_Pos (4U)
4184#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4185#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4186#define CAN_F12R1_FB5_Pos (5U)
4187#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4188#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4189#define CAN_F12R1_FB6_Pos (6U)
4190#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4191#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
4192#define CAN_F12R1_FB7_Pos (7U)
4193#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
4194#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
4195#define CAN_F12R1_FB8_Pos (8U)
4196#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
4197#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
4198#define CAN_F12R1_FB9_Pos (9U)
4199#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
4200#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
4201#define CAN_F12R1_FB10_Pos (10U)
4202#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
4203#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
4204#define CAN_F12R1_FB11_Pos (11U)
4205#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
4206#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
4207#define CAN_F12R1_FB12_Pos (12U)
4208#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
4209#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
4210#define CAN_F12R1_FB13_Pos (13U)
4211#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
4212#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
4213#define CAN_F12R1_FB14_Pos (14U)
4214#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
4215#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
4216#define CAN_F12R1_FB15_Pos (15U)
4217#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
4218#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
4219#define CAN_F12R1_FB16_Pos (16U)
4220#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
4221#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
4222#define CAN_F12R1_FB17_Pos (17U)
4223#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
4224#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
4225#define CAN_F12R1_FB18_Pos (18U)
4226#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
4227#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
4228#define CAN_F12R1_FB19_Pos (19U)
4229#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
4230#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
4231#define CAN_F12R1_FB20_Pos (20U)
4232#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
4233#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
4234#define CAN_F12R1_FB21_Pos (21U)
4235#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
4236#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
4237#define CAN_F12R1_FB22_Pos (22U)
4238#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
4239#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
4240#define CAN_F12R1_FB23_Pos (23U)
4241#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
4242#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
4243#define CAN_F12R1_FB24_Pos (24U)
4244#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
4245#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
4246#define CAN_F12R1_FB25_Pos (25U)
4247#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
4248#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
4249#define CAN_F12R1_FB26_Pos (26U)
4250#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
4251#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
4252#define CAN_F12R1_FB27_Pos (27U)
4253#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
4254#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
4255#define CAN_F12R1_FB28_Pos (28U)
4256#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
4257#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
4258#define CAN_F12R1_FB29_Pos (29U)
4259#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
4260#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
4261#define CAN_F12R1_FB30_Pos (30U)
4262#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
4263#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
4264#define CAN_F12R1_FB31_Pos (31U)
4265#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
4266#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
4268/******************* Bit definition for CAN_F13R1 register ******************/
4269#define CAN_F13R1_FB0_Pos (0U)
4270#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
4271#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
4272#define CAN_F13R1_FB1_Pos (1U)
4273#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
4274#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4275#define CAN_F13R1_FB2_Pos (2U)
4276#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4277#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4278#define CAN_F13R1_FB3_Pos (3U)
4279#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4280#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4281#define CAN_F13R1_FB4_Pos (4U)
4282#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4283#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4284#define CAN_F13R1_FB5_Pos (5U)
4285#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4286#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4287#define CAN_F13R1_FB6_Pos (6U)
4288#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4289#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4290#define CAN_F13R1_FB7_Pos (7U)
4291#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4292#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4293#define CAN_F13R1_FB8_Pos (8U)
4294#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4295#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4296#define CAN_F13R1_FB9_Pos (9U)
4297#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4298#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4299#define CAN_F13R1_FB10_Pos (10U)
4300#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4301#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4302#define CAN_F13R1_FB11_Pos (11U)
4303#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4304#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4305#define CAN_F13R1_FB12_Pos (12U)
4306#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4307#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4308#define CAN_F13R1_FB13_Pos (13U)
4309#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4310#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4311#define CAN_F13R1_FB14_Pos (14U)
4312#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4313#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4314#define CAN_F13R1_FB15_Pos (15U)
4315#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4316#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4317#define CAN_F13R1_FB16_Pos (16U)
4318#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4319#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4320#define CAN_F13R1_FB17_Pos (17U)
4321#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4322#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4323#define CAN_F13R1_FB18_Pos (18U)
4324#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4325#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4326#define CAN_F13R1_FB19_Pos (19U)
4327#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4328#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4329#define CAN_F13R1_FB20_Pos (20U)
4330#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4331#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4332#define CAN_F13R1_FB21_Pos (21U)
4333#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4334#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4335#define CAN_F13R1_FB22_Pos (22U)
4336#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4337#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4338#define CAN_F13R1_FB23_Pos (23U)
4339#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4340#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4341#define CAN_F13R1_FB24_Pos (24U)
4342#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4343#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4344#define CAN_F13R1_FB25_Pos (25U)
4345#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4346#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4347#define CAN_F13R1_FB26_Pos (26U)
4348#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4349#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4350#define CAN_F13R1_FB27_Pos (27U)
4351#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4352#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4353#define CAN_F13R1_FB28_Pos (28U)
4354#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4355#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4356#define CAN_F13R1_FB29_Pos (29U)
4357#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4358#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4359#define CAN_F13R1_FB30_Pos (30U)
4360#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4361#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4362#define CAN_F13R1_FB31_Pos (31U)
4363#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4364#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4366/******************* Bit definition for CAN_F0R2 register *******************/
4367#define CAN_F0R2_FB0_Pos (0U)
4368#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4369#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4370#define CAN_F0R2_FB1_Pos (1U)
4371#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4372#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4373#define CAN_F0R2_FB2_Pos (2U)
4374#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4375#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4376#define CAN_F0R2_FB3_Pos (3U)
4377#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4378#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4379#define CAN_F0R2_FB4_Pos (4U)
4380#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4381#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4382#define CAN_F0R2_FB5_Pos (5U)
4383#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4384#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4385#define CAN_F0R2_FB6_Pos (6U)
4386#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4387#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4388#define CAN_F0R2_FB7_Pos (7U)
4389#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4390#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4391#define CAN_F0R2_FB8_Pos (8U)
4392#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4393#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4394#define CAN_F0R2_FB9_Pos (9U)
4395#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4396#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4397#define CAN_F0R2_FB10_Pos (10U)
4398#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4399#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4400#define CAN_F0R2_FB11_Pos (11U)
4401#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4402#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4403#define CAN_F0R2_FB12_Pos (12U)
4404#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4405#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4406#define CAN_F0R2_FB13_Pos (13U)
4407#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4408#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4409#define CAN_F0R2_FB14_Pos (14U)
4410#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4411#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4412#define CAN_F0R2_FB15_Pos (15U)
4413#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4414#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4415#define CAN_F0R2_FB16_Pos (16U)
4416#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4417#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4418#define CAN_F0R2_FB17_Pos (17U)
4419#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4420#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4421#define CAN_F0R2_FB18_Pos (18U)
4422#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4423#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4424#define CAN_F0R2_FB19_Pos (19U)
4425#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4426#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4427#define CAN_F0R2_FB20_Pos (20U)
4428#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4429#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4430#define CAN_F0R2_FB21_Pos (21U)
4431#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4432#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4433#define CAN_F0R2_FB22_Pos (22U)
4434#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4435#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4436#define CAN_F0R2_FB23_Pos (23U)
4437#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4438#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4439#define CAN_F0R2_FB24_Pos (24U)
4440#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4441#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4442#define CAN_F0R2_FB25_Pos (25U)
4443#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4444#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4445#define CAN_F0R2_FB26_Pos (26U)
4446#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4447#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4448#define CAN_F0R2_FB27_Pos (27U)
4449#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4450#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4451#define CAN_F0R2_FB28_Pos (28U)
4452#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4453#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4454#define CAN_F0R2_FB29_Pos (29U)
4455#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4456#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4457#define CAN_F0R2_FB30_Pos (30U)
4458#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4459#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4460#define CAN_F0R2_FB31_Pos (31U)
4461#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4462#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4464/******************* Bit definition for CAN_F1R2 register *******************/
4465#define CAN_F1R2_FB0_Pos (0U)
4466#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4467#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4468#define CAN_F1R2_FB1_Pos (1U)
4469#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4470#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4471#define CAN_F1R2_FB2_Pos (2U)
4472#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4473#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4474#define CAN_F1R2_FB3_Pos (3U)
4475#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4476#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4477#define CAN_F1R2_FB4_Pos (4U)
4478#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4479#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4480#define CAN_F1R2_FB5_Pos (5U)
4481#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4482#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4483#define CAN_F1R2_FB6_Pos (6U)
4484#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4485#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4486#define CAN_F1R2_FB7_Pos (7U)
4487#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4488#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4489#define CAN_F1R2_FB8_Pos (8U)
4490#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4491#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4492#define CAN_F1R2_FB9_Pos (9U)
4493#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4494#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4495#define CAN_F1R2_FB10_Pos (10U)
4496#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4497#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4498#define CAN_F1R2_FB11_Pos (11U)
4499#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4500#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4501#define CAN_F1R2_FB12_Pos (12U)
4502#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4503#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4504#define CAN_F1R2_FB13_Pos (13U)
4505#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4506#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4507#define CAN_F1R2_FB14_Pos (14U)
4508#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4509#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4510#define CAN_F1R2_FB15_Pos (15U)
4511#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4512#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4513#define CAN_F1R2_FB16_Pos (16U)
4514#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4515#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4516#define CAN_F1R2_FB17_Pos (17U)
4517#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4518#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4519#define CAN_F1R2_FB18_Pos (18U)
4520#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4521#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4522#define CAN_F1R2_FB19_Pos (19U)
4523#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4524#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4525#define CAN_F1R2_FB20_Pos (20U)
4526#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4527#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4528#define CAN_F1R2_FB21_Pos (21U)
4529#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4530#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4531#define CAN_F1R2_FB22_Pos (22U)
4532#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4533#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4534#define CAN_F1R2_FB23_Pos (23U)
4535#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4536#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4537#define CAN_F1R2_FB24_Pos (24U)
4538#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4539#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4540#define CAN_F1R2_FB25_Pos (25U)
4541#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4542#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4543#define CAN_F1R2_FB26_Pos (26U)
4544#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4545#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4546#define CAN_F1R2_FB27_Pos (27U)
4547#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4548#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4549#define CAN_F1R2_FB28_Pos (28U)
4550#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4551#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4552#define CAN_F1R2_FB29_Pos (29U)
4553#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4554#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4555#define CAN_F1R2_FB30_Pos (30U)
4556#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4557#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4558#define CAN_F1R2_FB31_Pos (31U)
4559#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4560#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4562/******************* Bit definition for CAN_F2R2 register *******************/
4563#define CAN_F2R2_FB0_Pos (0U)
4564#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4565#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4566#define CAN_F2R2_FB1_Pos (1U)
4567#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4568#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4569#define CAN_F2R2_FB2_Pos (2U)
4570#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4571#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4572#define CAN_F2R2_FB3_Pos (3U)
4573#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4574#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4575#define CAN_F2R2_FB4_Pos (4U)
4576#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4577#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4578#define CAN_F2R2_FB5_Pos (5U)
4579#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4580#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4581#define CAN_F2R2_FB6_Pos (6U)
4582#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4583#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4584#define CAN_F2R2_FB7_Pos (7U)
4585#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4586#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4587#define CAN_F2R2_FB8_Pos (8U)
4588#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4589#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4590#define CAN_F2R2_FB9_Pos (9U)
4591#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4592#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4593#define CAN_F2R2_FB10_Pos (10U)
4594#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4595#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4596#define CAN_F2R2_FB11_Pos (11U)
4597#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4598#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4599#define CAN_F2R2_FB12_Pos (12U)
4600#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4601#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4602#define CAN_F2R2_FB13_Pos (13U)
4603#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4604#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4605#define CAN_F2R2_FB14_Pos (14U)
4606#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4607#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4608#define CAN_F2R2_FB15_Pos (15U)
4609#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4610#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4611#define CAN_F2R2_FB16_Pos (16U)
4612#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4613#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4614#define CAN_F2R2_FB17_Pos (17U)
4615#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4616#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4617#define CAN_F2R2_FB18_Pos (18U)
4618#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4619#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4620#define CAN_F2R2_FB19_Pos (19U)
4621#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4622#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4623#define CAN_F2R2_FB20_Pos (20U)
4624#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4625#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4626#define CAN_F2R2_FB21_Pos (21U)
4627#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4628#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4629#define CAN_F2R2_FB22_Pos (22U)
4630#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4631#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4632#define CAN_F2R2_FB23_Pos (23U)
4633#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4634#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4635#define CAN_F2R2_FB24_Pos (24U)
4636#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4637#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4638#define CAN_F2R2_FB25_Pos (25U)
4639#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4640#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4641#define CAN_F2R2_FB26_Pos (26U)
4642#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4643#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4644#define CAN_F2R2_FB27_Pos (27U)
4645#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4646#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4647#define CAN_F2R2_FB28_Pos (28U)
4648#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4649#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4650#define CAN_F2R2_FB29_Pos (29U)
4651#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4652#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4653#define CAN_F2R2_FB30_Pos (30U)
4654#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4655#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4656#define CAN_F2R2_FB31_Pos (31U)
4657#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4658#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4660/******************* Bit definition for CAN_F3R2 register *******************/
4661#define CAN_F3R2_FB0_Pos (0U)
4662#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4663#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4664#define CAN_F3R2_FB1_Pos (1U)
4665#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4666#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4667#define CAN_F3R2_FB2_Pos (2U)
4668#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4669#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4670#define CAN_F3R2_FB3_Pos (3U)
4671#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4672#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4673#define CAN_F3R2_FB4_Pos (4U)
4674#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4675#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4676#define CAN_F3R2_FB5_Pos (5U)
4677#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4678#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4679#define CAN_F3R2_FB6_Pos (6U)
4680#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4681#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4682#define CAN_F3R2_FB7_Pos (7U)
4683#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4684#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4685#define CAN_F3R2_FB8_Pos (8U)
4686#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4687#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4688#define CAN_F3R2_FB9_Pos (9U)
4689#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4690#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4691#define CAN_F3R2_FB10_Pos (10U)
4692#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4693#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4694#define CAN_F3R2_FB11_Pos (11U)
4695#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4696#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4697#define CAN_F3R2_FB12_Pos (12U)
4698#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4699#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4700#define CAN_F3R2_FB13_Pos (13U)
4701#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4702#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4703#define CAN_F3R2_FB14_Pos (14U)
4704#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4705#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4706#define CAN_F3R2_FB15_Pos (15U)
4707#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4708#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4709#define CAN_F3R2_FB16_Pos (16U)
4710#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4711#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4712#define CAN_F3R2_FB17_Pos (17U)
4713#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4714#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4715#define CAN_F3R2_FB18_Pos (18U)
4716#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4717#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4718#define CAN_F3R2_FB19_Pos (19U)
4719#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4720#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4721#define CAN_F3R2_FB20_Pos (20U)
4722#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4723#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4724#define CAN_F3R2_FB21_Pos (21U)
4725#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4726#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4727#define CAN_F3R2_FB22_Pos (22U)
4728#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4729#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4730#define CAN_F3R2_FB23_Pos (23U)
4731#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4732#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4733#define CAN_F3R2_FB24_Pos (24U)
4734#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4735#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4736#define CAN_F3R2_FB25_Pos (25U)
4737#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4738#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4739#define CAN_F3R2_FB26_Pos (26U)
4740#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4741#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4742#define CAN_F3R2_FB27_Pos (27U)
4743#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4744#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4745#define CAN_F3R2_FB28_Pos (28U)
4746#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4747#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4748#define CAN_F3R2_FB29_Pos (29U)
4749#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4750#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4751#define CAN_F3R2_FB30_Pos (30U)
4752#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4753#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4754#define CAN_F3R2_FB31_Pos (31U)
4755#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4756#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4758/******************* Bit definition for CAN_F4R2 register *******************/
4759#define CAN_F4R2_FB0_Pos (0U)
4760#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4761#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4762#define CAN_F4R2_FB1_Pos (1U)
4763#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4764#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4765#define CAN_F4R2_FB2_Pos (2U)
4766#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4767#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4768#define CAN_F4R2_FB3_Pos (3U)
4769#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4770#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4771#define CAN_F4R2_FB4_Pos (4U)
4772#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4773#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4774#define CAN_F4R2_FB5_Pos (5U)
4775#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4776#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4777#define CAN_F4R2_FB6_Pos (6U)
4778#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4779#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4780#define CAN_F4R2_FB7_Pos (7U)
4781#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4782#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4783#define CAN_F4R2_FB8_Pos (8U)
4784#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4785#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4786#define CAN_F4R2_FB9_Pos (9U)
4787#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4788#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4789#define CAN_F4R2_FB10_Pos (10U)
4790#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4791#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4792#define CAN_F4R2_FB11_Pos (11U)
4793#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4794#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4795#define CAN_F4R2_FB12_Pos (12U)
4796#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4797#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4798#define CAN_F4R2_FB13_Pos (13U)
4799#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4800#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4801#define CAN_F4R2_FB14_Pos (14U)
4802#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4803#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4804#define CAN_F4R2_FB15_Pos (15U)
4805#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4806#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4807#define CAN_F4R2_FB16_Pos (16U)
4808#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4809#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4810#define CAN_F4R2_FB17_Pos (17U)
4811#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4812#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4813#define CAN_F4R2_FB18_Pos (18U)
4814#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4815#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4816#define CAN_F4R2_FB19_Pos (19U)
4817#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4818#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4819#define CAN_F4R2_FB20_Pos (20U)
4820#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4821#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4822#define CAN_F4R2_FB21_Pos (21U)
4823#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4824#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4825#define CAN_F4R2_FB22_Pos (22U)
4826#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4827#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4828#define CAN_F4R2_FB23_Pos (23U)
4829#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4830#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4831#define CAN_F4R2_FB24_Pos (24U)
4832#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4833#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4834#define CAN_F4R2_FB25_Pos (25U)
4835#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4836#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4837#define CAN_F4R2_FB26_Pos (26U)
4838#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4839#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4840#define CAN_F4R2_FB27_Pos (27U)
4841#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4842#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4843#define CAN_F4R2_FB28_Pos (28U)
4844#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4845#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4846#define CAN_F4R2_FB29_Pos (29U)
4847#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4848#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4849#define CAN_F4R2_FB30_Pos (30U)
4850#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4851#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4852#define CAN_F4R2_FB31_Pos (31U)
4853#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4854#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4856/******************* Bit definition for CAN_F5R2 register *******************/
4857#define CAN_F5R2_FB0_Pos (0U)
4858#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4859#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4860#define CAN_F5R2_FB1_Pos (1U)
4861#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4862#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4863#define CAN_F5R2_FB2_Pos (2U)
4864#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4865#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4866#define CAN_F5R2_FB3_Pos (3U)
4867#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4868#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4869#define CAN_F5R2_FB4_Pos (4U)
4870#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4871#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4872#define CAN_F5R2_FB5_Pos (5U)
4873#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4874#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4875#define CAN_F5R2_FB6_Pos (6U)
4876#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4877#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4878#define CAN_F5R2_FB7_Pos (7U)
4879#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4880#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4881#define CAN_F5R2_FB8_Pos (8U)
4882#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4883#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4884#define CAN_F5R2_FB9_Pos (9U)
4885#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4886#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4887#define CAN_F5R2_FB10_Pos (10U)
4888#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4889#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4890#define CAN_F5R2_FB11_Pos (11U)
4891#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4892#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4893#define CAN_F5R2_FB12_Pos (12U)
4894#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4895#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4896#define CAN_F5R2_FB13_Pos (13U)
4897#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4898#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4899#define CAN_F5R2_FB14_Pos (14U)
4900#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4901#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4902#define CAN_F5R2_FB15_Pos (15U)
4903#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4904#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4905#define CAN_F5R2_FB16_Pos (16U)
4906#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4907#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4908#define CAN_F5R2_FB17_Pos (17U)
4909#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4910#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4911#define CAN_F5R2_FB18_Pos (18U)
4912#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4913#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4914#define CAN_F5R2_FB19_Pos (19U)
4915#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4916#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4917#define CAN_F5R2_FB20_Pos (20U)
4918#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4919#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4920#define CAN_F5R2_FB21_Pos (21U)
4921#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4922#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4923#define CAN_F5R2_FB22_Pos (22U)
4924#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4925#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4926#define CAN_F5R2_FB23_Pos (23U)
4927#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4928#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4929#define CAN_F5R2_FB24_Pos (24U)
4930#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4931#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4932#define CAN_F5R2_FB25_Pos (25U)
4933#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4934#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4935#define CAN_F5R2_FB26_Pos (26U)
4936#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4937#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4938#define CAN_F5R2_FB27_Pos (27U)
4939#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4940#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4941#define CAN_F5R2_FB28_Pos (28U)
4942#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4943#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4944#define CAN_F5R2_FB29_Pos (29U)
4945#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4946#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4947#define CAN_F5R2_FB30_Pos (30U)
4948#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4949#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4950#define CAN_F5R2_FB31_Pos (31U)
4951#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4952#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4954/******************* Bit definition for CAN_F6R2 register *******************/
4955#define CAN_F6R2_FB0_Pos (0U)
4956#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4957#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4958#define CAN_F6R2_FB1_Pos (1U)
4959#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4960#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4961#define CAN_F6R2_FB2_Pos (2U)
4962#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4963#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4964#define CAN_F6R2_FB3_Pos (3U)
4965#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4966#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4967#define CAN_F6R2_FB4_Pos (4U)
4968#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4969#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4970#define CAN_F6R2_FB5_Pos (5U)
4971#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4972#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4973#define CAN_F6R2_FB6_Pos (6U)
4974#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4975#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4976#define CAN_F6R2_FB7_Pos (7U)
4977#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4978#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4979#define CAN_F6R2_FB8_Pos (8U)
4980#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4981#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4982#define CAN_F6R2_FB9_Pos (9U)
4983#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4984#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4985#define CAN_F6R2_FB10_Pos (10U)
4986#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4987#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4988#define CAN_F6R2_FB11_Pos (11U)
4989#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4990#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4991#define CAN_F6R2_FB12_Pos (12U)
4992#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4993#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4994#define CAN_F6R2_FB13_Pos (13U)
4995#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4996#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4997#define CAN_F6R2_FB14_Pos (14U)
4998#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4999#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
5000#define CAN_F6R2_FB15_Pos (15U)
5001#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
5002#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
5003#define CAN_F6R2_FB16_Pos (16U)
5004#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
5005#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
5006#define CAN_F6R2_FB17_Pos (17U)
5007#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
5008#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
5009#define CAN_F6R2_FB18_Pos (18U)
5010#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
5011#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
5012#define CAN_F6R2_FB19_Pos (19U)
5013#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
5014#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
5015#define CAN_F6R2_FB20_Pos (20U)
5016#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
5017#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
5018#define CAN_F6R2_FB21_Pos (21U)
5019#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
5020#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
5021#define CAN_F6R2_FB22_Pos (22U)
5022#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
5023#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
5024#define CAN_F6R2_FB23_Pos (23U)
5025#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
5026#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
5027#define CAN_F6R2_FB24_Pos (24U)
5028#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
5029#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
5030#define CAN_F6R2_FB25_Pos (25U)
5031#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
5032#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
5033#define CAN_F6R2_FB26_Pos (26U)
5034#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
5035#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
5036#define CAN_F6R2_FB27_Pos (27U)
5037#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
5038#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
5039#define CAN_F6R2_FB28_Pos (28U)
5040#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
5041#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
5042#define CAN_F6R2_FB29_Pos (29U)
5043#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
5044#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
5045#define CAN_F6R2_FB30_Pos (30U)
5046#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
5047#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
5048#define CAN_F6R2_FB31_Pos (31U)
5049#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
5050#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
5052/******************* Bit definition for CAN_F7R2 register *******************/
5053#define CAN_F7R2_FB0_Pos (0U)
5054#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
5055#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
5056#define CAN_F7R2_FB1_Pos (1U)
5057#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
5058#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
5059#define CAN_F7R2_FB2_Pos (2U)
5060#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
5061#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
5062#define CAN_F7R2_FB3_Pos (3U)
5063#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
5064#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
5065#define CAN_F7R2_FB4_Pos (4U)
5066#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
5067#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
5068#define CAN_F7R2_FB5_Pos (5U)
5069#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
5070#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
5071#define CAN_F7R2_FB6_Pos (6U)
5072#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
5073#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
5074#define CAN_F7R2_FB7_Pos (7U)
5075#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
5076#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
5077#define CAN_F7R2_FB8_Pos (8U)
5078#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
5079#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
5080#define CAN_F7R2_FB9_Pos (9U)
5081#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
5082#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
5083#define CAN_F7R2_FB10_Pos (10U)
5084#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
5085#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
5086#define CAN_F7R2_FB11_Pos (11U)
5087#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
5088#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
5089#define CAN_F7R2_FB12_Pos (12U)
5090#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
5091#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
5092#define CAN_F7R2_FB13_Pos (13U)
5093#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
5094#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
5095#define CAN_F7R2_FB14_Pos (14U)
5096#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
5097#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
5098#define CAN_F7R2_FB15_Pos (15U)
5099#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
5100#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
5101#define CAN_F7R2_FB16_Pos (16U)
5102#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
5103#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
5104#define CAN_F7R2_FB17_Pos (17U)
5105#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
5106#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
5107#define CAN_F7R2_FB18_Pos (18U)
5108#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
5109#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
5110#define CAN_F7R2_FB19_Pos (19U)
5111#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
5112#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
5113#define CAN_F7R2_FB20_Pos (20U)
5114#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
5115#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
5116#define CAN_F7R2_FB21_Pos (21U)
5117#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
5118#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
5119#define CAN_F7R2_FB22_Pos (22U)
5120#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
5121#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
5122#define CAN_F7R2_FB23_Pos (23U)
5123#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
5124#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
5125#define CAN_F7R2_FB24_Pos (24U)
5126#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
5127#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
5128#define CAN_F7R2_FB25_Pos (25U)
5129#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
5130#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
5131#define CAN_F7R2_FB26_Pos (26U)
5132#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
5133#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
5134#define CAN_F7R2_FB27_Pos (27U)
5135#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
5136#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
5137#define CAN_F7R2_FB28_Pos (28U)
5138#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
5139#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
5140#define CAN_F7R2_FB29_Pos (29U)
5141#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
5142#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
5143#define CAN_F7R2_FB30_Pos (30U)
5144#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
5145#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
5146#define CAN_F7R2_FB31_Pos (31U)
5147#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
5148#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
5150/******************* Bit definition for CAN_F8R2 register *******************/
5151#define CAN_F8R2_FB0_Pos (0U)
5152#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
5153#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
5154#define CAN_F8R2_FB1_Pos (1U)
5155#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
5156#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
5157#define CAN_F8R2_FB2_Pos (2U)
5158#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
5159#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
5160#define CAN_F8R2_FB3_Pos (3U)
5161#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
5162#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
5163#define CAN_F8R2_FB4_Pos (4U)
5164#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
5165#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
5166#define CAN_F8R2_FB5_Pos (5U)
5167#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
5168#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
5169#define CAN_F8R2_FB6_Pos (6U)
5170#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
5171#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
5172#define CAN_F8R2_FB7_Pos (7U)
5173#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
5174#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
5175#define CAN_F8R2_FB8_Pos (8U)
5176#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5177#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5178#define CAN_F8R2_FB9_Pos (9U)
5179#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5180#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5181#define CAN_F8R2_FB10_Pos (10U)
5182#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5183#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5184#define CAN_F8R2_FB11_Pos (11U)
5185#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5186#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5187#define CAN_F8R2_FB12_Pos (12U)
5188#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5189#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5190#define CAN_F8R2_FB13_Pos (13U)
5191#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
5192#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
5193#define CAN_F8R2_FB14_Pos (14U)
5194#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
5195#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
5196#define CAN_F8R2_FB15_Pos (15U)
5197#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
5198#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
5199#define CAN_F8R2_FB16_Pos (16U)
5200#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
5201#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
5202#define CAN_F8R2_FB17_Pos (17U)
5203#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
5204#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
5205#define CAN_F8R2_FB18_Pos (18U)
5206#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
5207#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
5208#define CAN_F8R2_FB19_Pos (19U)
5209#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
5210#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
5211#define CAN_F8R2_FB20_Pos (20U)
5212#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
5213#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
5214#define CAN_F8R2_FB21_Pos (21U)
5215#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
5216#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
5217#define CAN_F8R2_FB22_Pos (22U)
5218#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
5219#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
5220#define CAN_F8R2_FB23_Pos (23U)
5221#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
5222#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
5223#define CAN_F8R2_FB24_Pos (24U)
5224#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
5225#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
5226#define CAN_F8R2_FB25_Pos (25U)
5227#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
5228#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
5229#define CAN_F8R2_FB26_Pos (26U)
5230#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
5231#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
5232#define CAN_F8R2_FB27_Pos (27U)
5233#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
5234#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
5235#define CAN_F8R2_FB28_Pos (28U)
5236#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
5237#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
5238#define CAN_F8R2_FB29_Pos (29U)
5239#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
5240#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
5241#define CAN_F8R2_FB30_Pos (30U)
5242#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
5243#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
5244#define CAN_F8R2_FB31_Pos (31U)
5245#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
5246#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
5248/******************* Bit definition for CAN_F9R2 register *******************/
5249#define CAN_F9R2_FB0_Pos (0U)
5250#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
5251#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
5252#define CAN_F9R2_FB1_Pos (1U)
5253#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
5254#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
5255#define CAN_F9R2_FB2_Pos (2U)
5256#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
5257#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
5258#define CAN_F9R2_FB3_Pos (3U)
5259#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
5260#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
5261#define CAN_F9R2_FB4_Pos (4U)
5262#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
5263#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
5264#define CAN_F9R2_FB5_Pos (5U)
5265#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
5266#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
5267#define CAN_F9R2_FB6_Pos (6U)
5268#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
5269#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
5270#define CAN_F9R2_FB7_Pos (7U)
5271#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
5272#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
5273#define CAN_F9R2_FB8_Pos (8U)
5274#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5275#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5276#define CAN_F9R2_FB9_Pos (9U)
5277#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5278#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5279#define CAN_F9R2_FB10_Pos (10U)
5280#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5281#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5282#define CAN_F9R2_FB11_Pos (11U)
5283#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5284#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5285#define CAN_F9R2_FB12_Pos (12U)
5286#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5287#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5288#define CAN_F9R2_FB13_Pos (13U)
5289#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5290#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5291#define CAN_F9R2_FB14_Pos (14U)
5292#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5293#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5294#define CAN_F9R2_FB15_Pos (15U)
5295#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5296#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5297#define CAN_F9R2_FB16_Pos (16U)
5298#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5299#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5300#define CAN_F9R2_FB17_Pos (17U)
5301#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5302#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5303#define CAN_F9R2_FB18_Pos (18U)
5304#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5305#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5306#define CAN_F9R2_FB19_Pos (19U)
5307#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5308#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5309#define CAN_F9R2_FB20_Pos (20U)
5310#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5311#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5312#define CAN_F9R2_FB21_Pos (21U)
5313#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5314#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5315#define CAN_F9R2_FB22_Pos (22U)
5316#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5317#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5318#define CAN_F9R2_FB23_Pos (23U)
5319#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5320#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5321#define CAN_F9R2_FB24_Pos (24U)
5322#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5323#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5324#define CAN_F9R2_FB25_Pos (25U)
5325#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5326#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5327#define CAN_F9R2_FB26_Pos (26U)
5328#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5329#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5330#define CAN_F9R2_FB27_Pos (27U)
5331#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5332#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5333#define CAN_F9R2_FB28_Pos (28U)
5334#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5335#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5336#define CAN_F9R2_FB29_Pos (29U)
5337#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5338#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5339#define CAN_F9R2_FB30_Pos (30U)
5340#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5341#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5342#define CAN_F9R2_FB31_Pos (31U)
5343#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5344#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5346/******************* Bit definition for CAN_F10R2 register ******************/
5347#define CAN_F10R2_FB0_Pos (0U)
5348#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5349#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5350#define CAN_F10R2_FB1_Pos (1U)
5351#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5352#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5353#define CAN_F10R2_FB2_Pos (2U)
5354#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5355#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5356#define CAN_F10R2_FB3_Pos (3U)
5357#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5358#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5359#define CAN_F10R2_FB4_Pos (4U)
5360#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5361#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5362#define CAN_F10R2_FB5_Pos (5U)
5363#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5364#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5365#define CAN_F10R2_FB6_Pos (6U)
5366#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5367#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5368#define CAN_F10R2_FB7_Pos (7U)
5369#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5370#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5371#define CAN_F10R2_FB8_Pos (8U)
5372#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5373#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5374#define CAN_F10R2_FB9_Pos (9U)
5375#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5376#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5377#define CAN_F10R2_FB10_Pos (10U)
5378#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5379#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5380#define CAN_F10R2_FB11_Pos (11U)
5381#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5382#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5383#define CAN_F10R2_FB12_Pos (12U)
5384#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5385#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5386#define CAN_F10R2_FB13_Pos (13U)
5387#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5388#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5389#define CAN_F10R2_FB14_Pos (14U)
5390#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5391#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5392#define CAN_F10R2_FB15_Pos (15U)
5393#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5394#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5395#define CAN_F10R2_FB16_Pos (16U)
5396#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5397#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5398#define CAN_F10R2_FB17_Pos (17U)
5399#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5400#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5401#define CAN_F10R2_FB18_Pos (18U)
5402#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5403#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5404#define CAN_F10R2_FB19_Pos (19U)
5405#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5406#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5407#define CAN_F10R2_FB20_Pos (20U)
5408#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5409#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5410#define CAN_F10R2_FB21_Pos (21U)
5411#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5412#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5413#define CAN_F10R2_FB22_Pos (22U)
5414#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5415#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5416#define CAN_F10R2_FB23_Pos (23U)
5417#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5418#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5419#define CAN_F10R2_FB24_Pos (24U)
5420#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5421#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5422#define CAN_F10R2_FB25_Pos (25U)
5423#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5424#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5425#define CAN_F10R2_FB26_Pos (26U)
5426#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5427#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5428#define CAN_F10R2_FB27_Pos (27U)
5429#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5430#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5431#define CAN_F10R2_FB28_Pos (28U)
5432#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5433#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5434#define CAN_F10R2_FB29_Pos (29U)
5435#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5436#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5437#define CAN_F10R2_FB30_Pos (30U)
5438#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5439#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5440#define CAN_F10R2_FB31_Pos (31U)
5441#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5442#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5444/******************* Bit definition for CAN_F11R2 register ******************/
5445#define CAN_F11R2_FB0_Pos (0U)
5446#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5447#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5448#define CAN_F11R2_FB1_Pos (1U)
5449#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5450#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5451#define CAN_F11R2_FB2_Pos (2U)
5452#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5453#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5454#define CAN_F11R2_FB3_Pos (3U)
5455#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5456#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5457#define CAN_F11R2_FB4_Pos (4U)
5458#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5459#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5460#define CAN_F11R2_FB5_Pos (5U)
5461#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5462#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5463#define CAN_F11R2_FB6_Pos (6U)
5464#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5465#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5466#define CAN_F11R2_FB7_Pos (7U)
5467#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5468#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5469#define CAN_F11R2_FB8_Pos (8U)
5470#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5471#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5472#define CAN_F11R2_FB9_Pos (9U)
5473#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5474#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5475#define CAN_F11R2_FB10_Pos (10U)
5476#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5477#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5478#define CAN_F11R2_FB11_Pos (11U)
5479#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5480#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5481#define CAN_F11R2_FB12_Pos (12U)
5482#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5483#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5484#define CAN_F11R2_FB13_Pos (13U)
5485#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5486#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5487#define CAN_F11R2_FB14_Pos (14U)
5488#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5489#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5490#define CAN_F11R2_FB15_Pos (15U)
5491#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5492#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5493#define CAN_F11R2_FB16_Pos (16U)
5494#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5495#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5496#define CAN_F11R2_FB17_Pos (17U)
5497#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5498#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5499#define CAN_F11R2_FB18_Pos (18U)
5500#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5501#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5502#define CAN_F11R2_FB19_Pos (19U)
5503#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5504#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5505#define CAN_F11R2_FB20_Pos (20U)
5506#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5507#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5508#define CAN_F11R2_FB21_Pos (21U)
5509#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5510#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5511#define CAN_F11R2_FB22_Pos (22U)
5512#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5513#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5514#define CAN_F11R2_FB23_Pos (23U)
5515#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5516#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5517#define CAN_F11R2_FB24_Pos (24U)
5518#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5519#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5520#define CAN_F11R2_FB25_Pos (25U)
5521#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5522#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5523#define CAN_F11R2_FB26_Pos (26U)
5524#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5525#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5526#define CAN_F11R2_FB27_Pos (27U)
5527#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5528#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5529#define CAN_F11R2_FB28_Pos (28U)
5530#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5531#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5532#define CAN_F11R2_FB29_Pos (29U)
5533#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5534#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5535#define CAN_F11R2_FB30_Pos (30U)
5536#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5537#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5538#define CAN_F11R2_FB31_Pos (31U)
5539#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5540#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5542/******************* Bit definition for CAN_F12R2 register ******************/
5543#define CAN_F12R2_FB0_Pos (0U)
5544#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5545#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5546#define CAN_F12R2_FB1_Pos (1U)
5547#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5548#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5549#define CAN_F12R2_FB2_Pos (2U)
5550#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5551#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5552#define CAN_F12R2_FB3_Pos (3U)
5553#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5554#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5555#define CAN_F12R2_FB4_Pos (4U)
5556#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5557#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5558#define CAN_F12R2_FB5_Pos (5U)
5559#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5560#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5561#define CAN_F12R2_FB6_Pos (6U)
5562#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5563#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5564#define CAN_F12R2_FB7_Pos (7U)
5565#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5566#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5567#define CAN_F12R2_FB8_Pos (8U)
5568#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5569#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5570#define CAN_F12R2_FB9_Pos (9U)
5571#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5572#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5573#define CAN_F12R2_FB10_Pos (10U)
5574#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5575#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5576#define CAN_F12R2_FB11_Pos (11U)
5577#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5578#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5579#define CAN_F12R2_FB12_Pos (12U)
5580#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5581#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5582#define CAN_F12R2_FB13_Pos (13U)
5583#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5584#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5585#define CAN_F12R2_FB14_Pos (14U)
5586#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5587#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5588#define CAN_F12R2_FB15_Pos (15U)
5589#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5590#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5591#define CAN_F12R2_FB16_Pos (16U)
5592#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5593#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5594#define CAN_F12R2_FB17_Pos (17U)
5595#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5596#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5597#define CAN_F12R2_FB18_Pos (18U)
5598#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5599#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5600#define CAN_F12R2_FB19_Pos (19U)
5601#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5602#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5603#define CAN_F12R2_FB20_Pos (20U)
5604#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5605#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5606#define CAN_F12R2_FB21_Pos (21U)
5607#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5608#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5609#define CAN_F12R2_FB22_Pos (22U)
5610#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5611#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5612#define CAN_F12R2_FB23_Pos (23U)
5613#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5614#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5615#define CAN_F12R2_FB24_Pos (24U)
5616#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5617#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5618#define CAN_F12R2_FB25_Pos (25U)
5619#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5620#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5621#define CAN_F12R2_FB26_Pos (26U)
5622#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5623#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5624#define CAN_F12R2_FB27_Pos (27U)
5625#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5626#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5627#define CAN_F12R2_FB28_Pos (28U)
5628#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5629#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5630#define CAN_F12R2_FB29_Pos (29U)
5631#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5632#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5633#define CAN_F12R2_FB30_Pos (30U)
5634#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5635#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5636#define CAN_F12R2_FB31_Pos (31U)
5637#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5638#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5640/******************* Bit definition for CAN_F13R2 register ******************/
5641#define CAN_F13R2_FB0_Pos (0U)
5642#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5643#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5644#define CAN_F13R2_FB1_Pos (1U)
5645#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5646#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5647#define CAN_F13R2_FB2_Pos (2U)
5648#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5649#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5650#define CAN_F13R2_FB3_Pos (3U)
5651#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5652#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5653#define CAN_F13R2_FB4_Pos (4U)
5654#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5655#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5656#define CAN_F13R2_FB5_Pos (5U)
5657#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5658#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5659#define CAN_F13R2_FB6_Pos (6U)
5660#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5661#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5662#define CAN_F13R2_FB7_Pos (7U)
5663#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5664#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5665#define CAN_F13R2_FB8_Pos (8U)
5666#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5667#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5668#define CAN_F13R2_FB9_Pos (9U)
5669#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5670#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5671#define CAN_F13R2_FB10_Pos (10U)
5672#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5673#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5674#define CAN_F13R2_FB11_Pos (11U)
5675#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5676#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5677#define CAN_F13R2_FB12_Pos (12U)
5678#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5679#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5680#define CAN_F13R2_FB13_Pos (13U)
5681#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5682#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5683#define CAN_F13R2_FB14_Pos (14U)
5684#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5685#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5686#define CAN_F13R2_FB15_Pos (15U)
5687#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5688#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5689#define CAN_F13R2_FB16_Pos (16U)
5690#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5691#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5692#define CAN_F13R2_FB17_Pos (17U)
5693#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5694#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5695#define CAN_F13R2_FB18_Pos (18U)
5696#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5697#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5698#define CAN_F13R2_FB19_Pos (19U)
5699#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5700#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5701#define CAN_F13R2_FB20_Pos (20U)
5702#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5703#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5704#define CAN_F13R2_FB21_Pos (21U)
5705#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5706#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5707#define CAN_F13R2_FB22_Pos (22U)
5708#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5709#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5710#define CAN_F13R2_FB23_Pos (23U)
5711#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5712#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5713#define CAN_F13R2_FB24_Pos (24U)
5714#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5715#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5716#define CAN_F13R2_FB25_Pos (25U)
5717#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5718#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5719#define CAN_F13R2_FB26_Pos (26U)
5720#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5721#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5722#define CAN_F13R2_FB27_Pos (27U)
5723#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5724#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5725#define CAN_F13R2_FB28_Pos (28U)
5726#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5727#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5728#define CAN_F13R2_FB29_Pos (29U)
5729#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5730#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5731#define CAN_F13R2_FB30_Pos (30U)
5732#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5733#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5734#define CAN_F13R2_FB31_Pos (31U)
5735#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5736#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5738/******************************************************************************/
5739/* */
5740/* CRC calculation unit */
5741/* */
5742/******************************************************************************/
5743/******************* Bit definition for CRC_DR register *********************/
5744#define CRC_DR_DR_Pos (0U)
5745#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5746#define CRC_DR_DR CRC_DR_DR_Msk
5749/******************* Bit definition for CRC_IDR register ********************/
5750#define CRC_IDR_IDR_Pos (0U)
5751#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5752#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5755/******************** Bit definition for CRC_CR register ********************/
5756#define CRC_CR_RESET_Pos (0U)
5757#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5758#define CRC_CR_RESET CRC_CR_RESET_Msk
5760/******************************************************************************/
5761/* */
5762/* Crypto Processor */
5763/* */
5764/******************************************************************************/
5765/******************* Bits definition for CRYP_CR register ********************/
5766#define CRYP_CR_ALGODIR_Pos (2U)
5767#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos)
5768#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
5769
5770#define CRYP_CR_ALGOMODE_Pos (3U)
5771#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos)
5772#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
5773#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos)
5774#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos)
5775#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos)
5776#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
5777#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
5778#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos)
5779#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
5780#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
5781#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos)
5782#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
5783#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
5784#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos)
5785#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
5786#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
5787#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)
5788#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
5789#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
5790#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)
5791#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
5792#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
5793#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)
5794#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
5795#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
5796#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)
5797#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
5798#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
5799#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)
5800#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
5801#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
5802#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos)
5803#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
5804
5805#define CRYP_CR_DATATYPE_Pos (6U)
5806#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos)
5807#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
5808#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos)
5809#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos)
5810#define CRYP_CR_KEYSIZE_Pos (8U)
5811#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos)
5812#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
5813#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos)
5814#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos)
5815#define CRYP_CR_FFLUSH_Pos (14U)
5816#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos)
5817#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
5818#define CRYP_CR_CRYPEN_Pos (15U)
5819#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos)
5820#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
5821
5822#define CRYP_CR_GCM_CCMPH_Pos (16U)
5823#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos)
5824#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
5825#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos)
5826#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos)
5827#define CRYP_CR_ALGOMODE_3 0x00080000U
5828
5829/****************** Bits definition for CRYP_SR register *********************/
5830#define CRYP_SR_IFEM_Pos (0U)
5831#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos)
5832#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
5833#define CRYP_SR_IFNF_Pos (1U)
5834#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos)
5835#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
5836#define CRYP_SR_OFNE_Pos (2U)
5837#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos)
5838#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
5839#define CRYP_SR_OFFU_Pos (3U)
5840#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos)
5841#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
5842#define CRYP_SR_BUSY_Pos (4U)
5843#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos)
5844#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
5845/****************** Bits definition for CRYP_DMACR register ******************/
5846#define CRYP_DMACR_DIEN_Pos (0U)
5847#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos)
5848#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
5849#define CRYP_DMACR_DOEN_Pos (1U)
5850#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos)
5851#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
5852/***************** Bits definition for CRYP_IMSCR register ******************/
5853#define CRYP_IMSCR_INIM_Pos (0U)
5854#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos)
5855#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
5856#define CRYP_IMSCR_OUTIM_Pos (1U)
5857#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos)
5858#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
5859/****************** Bits definition for CRYP_RISR register *******************/
5860#define CRYP_RISR_OUTRIS_Pos (0U)
5861#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos)
5862#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
5863#define CRYP_RISR_INRIS_Pos (1U)
5864#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos)
5865#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
5866/****************** Bits definition for CRYP_MISR register *******************/
5867#define CRYP_MISR_INMIS_Pos (0U)
5868#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos)
5869#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
5870#define CRYP_MISR_OUTMIS_Pos (1U)
5871#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos)
5872#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
5873
5874/******************************************************************************/
5875/* */
5876/* Digital to Analog Converter */
5877/* */
5878/******************************************************************************/
5879/*
5880 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5881 */
5882#define DAC_CHANNEL2_SUPPORT
5883/******************** Bit definition for DAC_CR register ********************/
5884#define DAC_CR_EN1_Pos (0U)
5885#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5886#define DAC_CR_EN1 DAC_CR_EN1_Msk
5887#define DAC_CR_BOFF1_Pos (1U)
5888#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5889#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5890#define DAC_CR_TEN1_Pos (2U)
5891#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5892#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5894#define DAC_CR_TSEL1_Pos (3U)
5895#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5896#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5897#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5898#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5899#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5901#define DAC_CR_WAVE1_Pos (6U)
5902#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5903#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5904#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5905#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5907#define DAC_CR_MAMP1_Pos (8U)
5908#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5909#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5910#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5911#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5912#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5913#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5915#define DAC_CR_DMAEN1_Pos (12U)
5916#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5917#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5918#define DAC_CR_DMAUDRIE1_Pos (13U)
5919#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5920#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5921#define DAC_CR_EN2_Pos (16U)
5922#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5923#define DAC_CR_EN2 DAC_CR_EN2_Msk
5924#define DAC_CR_BOFF2_Pos (17U)
5925#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5926#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5927#define DAC_CR_TEN2_Pos (18U)
5928#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5929#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5931#define DAC_CR_TSEL2_Pos (19U)
5932#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5933#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5934#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5935#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5936#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5938#define DAC_CR_WAVE2_Pos (22U)
5939#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5940#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5941#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5942#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5944#define DAC_CR_MAMP2_Pos (24U)
5945#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5946#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5947#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5948#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5949#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5950#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5952#define DAC_CR_DMAEN2_Pos (28U)
5953#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5954#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5955#define DAC_CR_DMAUDRIE2_Pos (29U)
5956#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5957#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5959/***************** Bit definition for DAC_SWTRIGR register ******************/
5960#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5961#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5962#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5963#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5964#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5965#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5967/***************** Bit definition for DAC_DHR12R1 register ******************/
5968#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5969#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5970#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5972/***************** Bit definition for DAC_DHR12L1 register ******************/
5973#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5974#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5975#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5977/****************** Bit definition for DAC_DHR8R1 register ******************/
5978#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5979#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5980#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5982/***************** Bit definition for DAC_DHR12R2 register ******************/
5983#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5984#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5985#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5987/***************** Bit definition for DAC_DHR12L2 register ******************/
5988#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5989#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5990#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5992/****************** Bit definition for DAC_DHR8R2 register ******************/
5993#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5994#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5995#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5997/***************** Bit definition for DAC_DHR12RD register ******************/
5998#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5999#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
6000#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
6001#define DAC_DHR12RD_DACC2DHR_Pos (16U)
6002#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
6003#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
6005/***************** Bit definition for DAC_DHR12LD register ******************/
6006#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6007#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
6008#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
6009#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6010#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
6011#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
6013/****************** Bit definition for DAC_DHR8RD register ******************/
6014#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6015#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
6016#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
6017#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6018#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
6019#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
6021/******************* Bit definition for DAC_DOR1 register *******************/
6022#define DAC_DOR1_DACC1DOR_Pos (0U)
6023#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
6024#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
6026/******************* Bit definition for DAC_DOR2 register *******************/
6027#define DAC_DOR2_DACC2DOR_Pos (0U)
6028#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6029#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6031/******************** Bit definition for DAC_SR register ********************/
6032#define DAC_SR_DMAUDR1_Pos (13U)
6033#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6034#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6035#define DAC_SR_DMAUDR2_Pos (29U)
6036#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6037#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6039/******************************************************************************/
6040/* */
6041/* DCMI */
6042/* */
6043/******************************************************************************/
6044/******************** Bits definition for DCMI_CR register ******************/
6045#define DCMI_CR_CAPTURE_Pos (0U)
6046#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
6047#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6048#define DCMI_CR_CM_Pos (1U)
6049#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
6050#define DCMI_CR_CM DCMI_CR_CM_Msk
6051#define DCMI_CR_CROP_Pos (2U)
6052#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
6053#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6054#define DCMI_CR_JPEG_Pos (3U)
6055#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
6056#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6057#define DCMI_CR_ESS_Pos (4U)
6058#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
6059#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6060#define DCMI_CR_PCKPOL_Pos (5U)
6061#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
6062#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6063#define DCMI_CR_HSPOL_Pos (6U)
6064#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
6065#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6066#define DCMI_CR_VSPOL_Pos (7U)
6067#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
6068#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6069#define DCMI_CR_FCRC_0 0x00000100U
6070#define DCMI_CR_FCRC_1 0x00000200U
6071#define DCMI_CR_EDM_0 0x00000400U
6072#define DCMI_CR_EDM_1 0x00000800U
6073#define DCMI_CR_OUTEN_Pos (13U)
6074#define DCMI_CR_OUTEN_Msk (0x1UL << DCMI_CR_OUTEN_Pos)
6075#define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
6076#define DCMI_CR_ENABLE_Pos (14U)
6077#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
6078#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6079#define DCMI_CR_BSM_0 0x00010000U
6080#define DCMI_CR_BSM_1 0x00020000U
6081#define DCMI_CR_OEBS_Pos (18U)
6082#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
6083#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6084#define DCMI_CR_LSM_Pos (19U)
6085#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
6086#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6087#define DCMI_CR_OELS_Pos (20U)
6088#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
6089#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6090
6091/******************** Bits definition for DCMI_SR register ******************/
6092#define DCMI_SR_HSYNC_Pos (0U)
6093#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
6094#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6095#define DCMI_SR_VSYNC_Pos (1U)
6096#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
6097#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6098#define DCMI_SR_FNE_Pos (2U)
6099#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
6100#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6101
6102/******************** Bits definition for DCMI_RIS register *****************/
6103#define DCMI_RIS_FRAME_RIS_Pos (0U)
6104#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
6105#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6106#define DCMI_RIS_OVR_RIS_Pos (1U)
6107#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
6108#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6109#define DCMI_RIS_ERR_RIS_Pos (2U)
6110#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
6111#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6112#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6113#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
6114#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6115#define DCMI_RIS_LINE_RIS_Pos (4U)
6116#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
6117#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6118/* Legacy defines */
6119#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
6120#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
6121#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
6122#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
6123#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
6124#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
6125
6126/******************** Bits definition for DCMI_IER register *****************/
6127#define DCMI_IER_FRAME_IE_Pos (0U)
6128#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
6129#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6130#define DCMI_IER_OVR_IE_Pos (1U)
6131#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
6132#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6133#define DCMI_IER_ERR_IE_Pos (2U)
6134#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
6135#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6136#define DCMI_IER_VSYNC_IE_Pos (3U)
6137#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
6138#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6139#define DCMI_IER_LINE_IE_Pos (4U)
6140#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
6141#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6142/* Legacy defines */
6143#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
6144
6145/******************** Bits definition for DCMI_MIS register *****************/
6146#define DCMI_MIS_FRAME_MIS_Pos (0U)
6147#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
6148#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6149#define DCMI_MIS_OVR_MIS_Pos (1U)
6150#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
6151#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6152#define DCMI_MIS_ERR_MIS_Pos (2U)
6153#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
6154#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6155#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6156#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
6157#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6158#define DCMI_MIS_LINE_MIS_Pos (4U)
6159#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
6160#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6161
6162/* Legacy defines */
6163#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
6164#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
6165#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
6166#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
6167#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
6168
6169/******************** Bits definition for DCMI_ICR register *****************/
6170#define DCMI_ICR_FRAME_ISC_Pos (0U)
6171#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
6172#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6173#define DCMI_ICR_OVR_ISC_Pos (1U)
6174#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
6175#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6176#define DCMI_ICR_ERR_ISC_Pos (2U)
6177#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
6178#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6179#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6180#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
6181#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6182#define DCMI_ICR_LINE_ISC_Pos (4U)
6183#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
6184#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6185
6186/* Legacy defines */
6187#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
6188
6189/******************** Bits definition for DCMI_ESCR register ******************/
6190#define DCMI_ESCR_FSC_Pos (0U)
6191#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6192#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6193#define DCMI_ESCR_LSC_Pos (8U)
6194#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6195#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6196#define DCMI_ESCR_LEC_Pos (16U)
6197#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6198#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6199#define DCMI_ESCR_FEC_Pos (24U)
6200#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6201#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6202
6203/******************** Bits definition for DCMI_ESUR register ******************/
6204#define DCMI_ESUR_FSU_Pos (0U)
6205#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6206#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6207#define DCMI_ESUR_LSU_Pos (8U)
6208#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6209#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6210#define DCMI_ESUR_LEU_Pos (16U)
6211#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6212#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6213#define DCMI_ESUR_FEU_Pos (24U)
6214#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6215#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6216
6217/******************** Bits definition for DCMI_CWSTRT register ******************/
6218#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6219#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6220#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6221#define DCMI_CWSTRT_VST_Pos (16U)
6222#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6223#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6224
6225/******************** Bits definition for DCMI_CWSIZE register ******************/
6226#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6227#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6228#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6229#define DCMI_CWSIZE_VLINE_Pos (16U)
6230#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6231#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6232
6233/******************** Bits definition for DCMI_DR register *********************/
6234#define DCMI_DR_BYTE0_Pos (0U)
6235#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6236#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6237#define DCMI_DR_BYTE1_Pos (8U)
6238#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6239#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6240#define DCMI_DR_BYTE2_Pos (16U)
6241#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6242#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6243#define DCMI_DR_BYTE3_Pos (24U)
6244#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6245#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6246
6247/******************************************************************************/
6248/* */
6249/* DMA Controller */
6250/* */
6251/******************************************************************************/
6252/******************** Bits definition for DMA_SxCR register *****************/
6253#define DMA_SxCR_CHSEL_Pos (25U)
6254#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
6255#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6256#define DMA_SxCR_CHSEL_0 0x02000000U
6257#define DMA_SxCR_CHSEL_1 0x04000000U
6258#define DMA_SxCR_CHSEL_2 0x08000000U
6259#define DMA_SxCR_MBURST_Pos (23U)
6260#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
6261#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6262#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
6263#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
6264#define DMA_SxCR_PBURST_Pos (21U)
6265#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
6266#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6267#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
6268#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
6269#define DMA_SxCR_CT_Pos (19U)
6270#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
6271#define DMA_SxCR_CT DMA_SxCR_CT_Msk
6272#define DMA_SxCR_DBM_Pos (18U)
6273#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
6274#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6275#define DMA_SxCR_PL_Pos (16U)
6276#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
6277#define DMA_SxCR_PL DMA_SxCR_PL_Msk
6278#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
6279#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
6280#define DMA_SxCR_PINCOS_Pos (15U)
6281#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
6282#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6283#define DMA_SxCR_MSIZE_Pos (13U)
6284#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
6285#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6286#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
6287#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
6288#define DMA_SxCR_PSIZE_Pos (11U)
6289#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
6290#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6291#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
6292#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
6293#define DMA_SxCR_MINC_Pos (10U)
6294#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
6295#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6296#define DMA_SxCR_PINC_Pos (9U)
6297#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
6298#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6299#define DMA_SxCR_CIRC_Pos (8U)
6300#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
6301#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6302#define DMA_SxCR_DIR_Pos (6U)
6303#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
6304#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6305#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
6306#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
6307#define DMA_SxCR_PFCTRL_Pos (5U)
6308#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
6309#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6310#define DMA_SxCR_TCIE_Pos (4U)
6311#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
6312#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6313#define DMA_SxCR_HTIE_Pos (3U)
6314#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
6315#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6316#define DMA_SxCR_TEIE_Pos (2U)
6317#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
6318#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6319#define DMA_SxCR_DMEIE_Pos (1U)
6320#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
6321#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6322#define DMA_SxCR_EN_Pos (0U)
6323#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6324#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6325
6326/* Legacy defines */
6327#define DMA_SxCR_ACK_Pos (20U)
6328#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
6329#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6330
6331/******************** Bits definition for DMA_SxCNDTR register **************/
6332#define DMA_SxNDT_Pos (0U)
6333#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6334#define DMA_SxNDT DMA_SxNDT_Msk
6335#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6336#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6337#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6338#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6339#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6340#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6341#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6342#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6343#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6344#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6345#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6346#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6347#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6348#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6349#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6350#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6352/******************** Bits definition for DMA_SxFCR register ****************/
6353#define DMA_SxFCR_FEIE_Pos (7U)
6354#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6355#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6356#define DMA_SxFCR_FS_Pos (3U)
6357#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6358#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6359#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6360#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6361#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6362#define DMA_SxFCR_DMDIS_Pos (2U)
6363#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6364#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6365#define DMA_SxFCR_FTH_Pos (0U)
6366#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6367#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6368#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6369#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6371/******************** Bits definition for DMA_LISR register *****************/
6372#define DMA_LISR_TCIF3_Pos (27U)
6373#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6374#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6375#define DMA_LISR_HTIF3_Pos (26U)
6376#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6377#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6378#define DMA_LISR_TEIF3_Pos (25U)
6379#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6380#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6381#define DMA_LISR_DMEIF3_Pos (24U)
6382#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6383#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6384#define DMA_LISR_FEIF3_Pos (22U)
6385#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
6386#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6387#define DMA_LISR_TCIF2_Pos (21U)
6388#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
6389#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6390#define DMA_LISR_HTIF2_Pos (20U)
6391#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
6392#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6393#define DMA_LISR_TEIF2_Pos (19U)
6394#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
6395#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6396#define DMA_LISR_DMEIF2_Pos (18U)
6397#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
6398#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6399#define DMA_LISR_FEIF2_Pos (16U)
6400#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
6401#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6402#define DMA_LISR_TCIF1_Pos (11U)
6403#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
6404#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6405#define DMA_LISR_HTIF1_Pos (10U)
6406#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
6407#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6408#define DMA_LISR_TEIF1_Pos (9U)
6409#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
6410#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6411#define DMA_LISR_DMEIF1_Pos (8U)
6412#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
6413#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6414#define DMA_LISR_FEIF1_Pos (6U)
6415#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
6416#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6417#define DMA_LISR_TCIF0_Pos (5U)
6418#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
6419#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6420#define DMA_LISR_HTIF0_Pos (4U)
6421#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
6422#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6423#define DMA_LISR_TEIF0_Pos (3U)
6424#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
6425#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6426#define DMA_LISR_DMEIF0_Pos (2U)
6427#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
6428#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6429#define DMA_LISR_FEIF0_Pos (0U)
6430#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
6431#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6432
6433/******************** Bits definition for DMA_HISR register *****************/
6434#define DMA_HISR_TCIF7_Pos (27U)
6435#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
6436#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6437#define DMA_HISR_HTIF7_Pos (26U)
6438#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
6439#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6440#define DMA_HISR_TEIF7_Pos (25U)
6441#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6442#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6443#define DMA_HISR_DMEIF7_Pos (24U)
6444#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6445#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6446#define DMA_HISR_FEIF7_Pos (22U)
6447#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6448#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6449#define DMA_HISR_TCIF6_Pos (21U)
6450#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6451#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6452#define DMA_HISR_HTIF6_Pos (20U)
6453#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6454#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6455#define DMA_HISR_TEIF6_Pos (19U)
6456#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6457#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6458#define DMA_HISR_DMEIF6_Pos (18U)
6459#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6460#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6461#define DMA_HISR_FEIF6_Pos (16U)
6462#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6463#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6464#define DMA_HISR_TCIF5_Pos (11U)
6465#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6466#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6467#define DMA_HISR_HTIF5_Pos (10U)
6468#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6469#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6470#define DMA_HISR_TEIF5_Pos (9U)
6471#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6472#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6473#define DMA_HISR_DMEIF5_Pos (8U)
6474#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6475#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6476#define DMA_HISR_FEIF5_Pos (6U)
6477#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6478#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6479#define DMA_HISR_TCIF4_Pos (5U)
6480#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6481#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6482#define DMA_HISR_HTIF4_Pos (4U)
6483#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6484#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6485#define DMA_HISR_TEIF4_Pos (3U)
6486#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6487#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6488#define DMA_HISR_DMEIF4_Pos (2U)
6489#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6490#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6491#define DMA_HISR_FEIF4_Pos (0U)
6492#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6493#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6494
6495/******************** Bits definition for DMA_LIFCR register ****************/
6496#define DMA_LIFCR_CTCIF3_Pos (27U)
6497#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6498#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6499#define DMA_LIFCR_CHTIF3_Pos (26U)
6500#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6501#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6502#define DMA_LIFCR_CTEIF3_Pos (25U)
6503#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6504#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6505#define DMA_LIFCR_CDMEIF3_Pos (24U)
6506#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6507#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6508#define DMA_LIFCR_CFEIF3_Pos (22U)
6509#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6510#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6511#define DMA_LIFCR_CTCIF2_Pos (21U)
6512#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6513#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6514#define DMA_LIFCR_CHTIF2_Pos (20U)
6515#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6516#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6517#define DMA_LIFCR_CTEIF2_Pos (19U)
6518#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6519#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6520#define DMA_LIFCR_CDMEIF2_Pos (18U)
6521#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6522#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6523#define DMA_LIFCR_CFEIF2_Pos (16U)
6524#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6525#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6526#define DMA_LIFCR_CTCIF1_Pos (11U)
6527#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6528#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6529#define DMA_LIFCR_CHTIF1_Pos (10U)
6530#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6531#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6532#define DMA_LIFCR_CTEIF1_Pos (9U)
6533#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6534#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6535#define DMA_LIFCR_CDMEIF1_Pos (8U)
6536#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6537#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6538#define DMA_LIFCR_CFEIF1_Pos (6U)
6539#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6540#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6541#define DMA_LIFCR_CTCIF0_Pos (5U)
6542#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6543#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6544#define DMA_LIFCR_CHTIF0_Pos (4U)
6545#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6546#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6547#define DMA_LIFCR_CTEIF0_Pos (3U)
6548#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6549#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6550#define DMA_LIFCR_CDMEIF0_Pos (2U)
6551#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6552#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6553#define DMA_LIFCR_CFEIF0_Pos (0U)
6554#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6555#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6556
6557/******************** Bits definition for DMA_HIFCR register ****************/
6558#define DMA_HIFCR_CTCIF7_Pos (27U)
6559#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6560#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6561#define DMA_HIFCR_CHTIF7_Pos (26U)
6562#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6563#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6564#define DMA_HIFCR_CTEIF7_Pos (25U)
6565#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6566#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6567#define DMA_HIFCR_CDMEIF7_Pos (24U)
6568#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6569#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6570#define DMA_HIFCR_CFEIF7_Pos (22U)
6571#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6572#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6573#define DMA_HIFCR_CTCIF6_Pos (21U)
6574#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6575#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6576#define DMA_HIFCR_CHTIF6_Pos (20U)
6577#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6578#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6579#define DMA_HIFCR_CTEIF6_Pos (19U)
6580#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6581#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6582#define DMA_HIFCR_CDMEIF6_Pos (18U)
6583#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6584#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6585#define DMA_HIFCR_CFEIF6_Pos (16U)
6586#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6587#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6588#define DMA_HIFCR_CTCIF5_Pos (11U)
6589#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6590#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6591#define DMA_HIFCR_CHTIF5_Pos (10U)
6592#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6593#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6594#define DMA_HIFCR_CTEIF5_Pos (9U)
6595#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6596#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6597#define DMA_HIFCR_CDMEIF5_Pos (8U)
6598#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6599#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6600#define DMA_HIFCR_CFEIF5_Pos (6U)
6601#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6602#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6603#define DMA_HIFCR_CTCIF4_Pos (5U)
6604#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6605#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6606#define DMA_HIFCR_CHTIF4_Pos (4U)
6607#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6608#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6609#define DMA_HIFCR_CTEIF4_Pos (3U)
6610#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6611#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6612#define DMA_HIFCR_CDMEIF4_Pos (2U)
6613#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6614#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6615#define DMA_HIFCR_CFEIF4_Pos (0U)
6616#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6617#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6618
6619/****************** Bit definition for DMA_SxPAR register ********************/
6620#define DMA_SxPAR_PA_Pos (0U)
6621#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6622#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6624/****************** Bit definition for DMA_SxM0AR register ********************/
6625#define DMA_SxM0AR_M0A_Pos (0U)
6626#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6627#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6629/****************** Bit definition for DMA_SxM1AR register ********************/
6630#define DMA_SxM1AR_M1A_Pos (0U)
6631#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6632#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6635/******************************************************************************/
6636/* */
6637/* AHB Master DMA2D Controller (DMA2D) */
6638/* */
6639/******************************************************************************/
6640
6641/******************** Bit definition for DMA2D_CR register ******************/
6642
6643#define DMA2D_CR_START_Pos (0U)
6644#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
6645#define DMA2D_CR_START DMA2D_CR_START_Msk
6646#define DMA2D_CR_SUSP_Pos (1U)
6647#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
6648#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
6649#define DMA2D_CR_ABORT_Pos (2U)
6650#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
6651#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
6652#define DMA2D_CR_TEIE_Pos (8U)
6653#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
6654#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
6655#define DMA2D_CR_TCIE_Pos (9U)
6656#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
6657#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
6658#define DMA2D_CR_TWIE_Pos (10U)
6659#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
6660#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
6661#define DMA2D_CR_CAEIE_Pos (11U)
6662#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
6663#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
6664#define DMA2D_CR_CTCIE_Pos (12U)
6665#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
6666#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
6667#define DMA2D_CR_CEIE_Pos (13U)
6668#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
6669#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
6670#define DMA2D_CR_MODE_Pos (16U)
6671#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos)
6672#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
6673#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
6674#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
6676/******************** Bit definition for DMA2D_ISR register *****************/
6677
6678#define DMA2D_ISR_TEIF_Pos (0U)
6679#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
6680#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
6681#define DMA2D_ISR_TCIF_Pos (1U)
6682#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
6683#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
6684#define DMA2D_ISR_TWIF_Pos (2U)
6685#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
6686#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
6687#define DMA2D_ISR_CAEIF_Pos (3U)
6688#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
6689#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
6690#define DMA2D_ISR_CTCIF_Pos (4U)
6691#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
6692#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
6693#define DMA2D_ISR_CEIF_Pos (5U)
6694#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
6695#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
6697/******************** Bit definition for DMA2D_IFCR register ****************/
6698
6699#define DMA2D_IFCR_CTEIF_Pos (0U)
6700#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
6701#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
6702#define DMA2D_IFCR_CTCIF_Pos (1U)
6703#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
6704#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
6705#define DMA2D_IFCR_CTWIF_Pos (2U)
6706#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
6707#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
6708#define DMA2D_IFCR_CAECIF_Pos (3U)
6709#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
6710#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
6711#define DMA2D_IFCR_CCTCIF_Pos (4U)
6712#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
6713#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
6714#define DMA2D_IFCR_CCEIF_Pos (5U)
6715#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
6716#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
6718/* Legacy defines */
6719#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
6720#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
6721#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
6722#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
6723#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
6724#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
6726/******************** Bit definition for DMA2D_FGMAR register ***************/
6727
6728#define DMA2D_FGMAR_MA_Pos (0U)
6729#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
6730#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
6732/******************** Bit definition for DMA2D_FGOR register ****************/
6733
6734#define DMA2D_FGOR_LO_Pos (0U)
6735#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos)
6736#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
6738/******************** Bit definition for DMA2D_BGMAR register ***************/
6739
6740#define DMA2D_BGMAR_MA_Pos (0U)
6741#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
6742#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
6744/******************** Bit definition for DMA2D_BGOR register ****************/
6745
6746#define DMA2D_BGOR_LO_Pos (0U)
6747#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos)
6748#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
6750/******************** Bit definition for DMA2D_FGPFCCR register *************/
6751
6752#define DMA2D_FGPFCCR_CM_Pos (0U)
6753#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
6754#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
6755#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
6756#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
6757#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
6758#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
6759#define DMA2D_FGPFCCR_CCM_Pos (4U)
6760#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
6761#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
6762#define DMA2D_FGPFCCR_START_Pos (5U)
6763#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
6764#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
6765#define DMA2D_FGPFCCR_CS_Pos (8U)
6766#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
6767#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
6768#define DMA2D_FGPFCCR_AM_Pos (16U)
6769#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
6770#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
6771#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
6772#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
6773#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6774#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
6775#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
6777/******************** Bit definition for DMA2D_FGCOLR register **************/
6778
6779#define DMA2D_FGCOLR_BLUE_Pos (0U)
6780#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
6781#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
6782#define DMA2D_FGCOLR_GREEN_Pos (8U)
6783#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
6784#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
6785#define DMA2D_FGCOLR_RED_Pos (16U)
6786#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
6787#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
6789/******************** Bit definition for DMA2D_BGPFCCR register *************/
6790
6791#define DMA2D_BGPFCCR_CM_Pos (0U)
6792#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
6793#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
6794#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
6795#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
6796#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
6797#define DMA2D_BGPFCCR_CM_3 0x00000008U
6798#define DMA2D_BGPFCCR_CCM_Pos (4U)
6799#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
6800#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
6801#define DMA2D_BGPFCCR_START_Pos (5U)
6802#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
6803#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
6804#define DMA2D_BGPFCCR_CS_Pos (8U)
6805#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
6806#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
6807#define DMA2D_BGPFCCR_AM_Pos (16U)
6808#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
6809#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
6810#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
6811#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
6812#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6813#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
6814#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
6816/******************** Bit definition for DMA2D_BGCOLR register **************/
6817
6818#define DMA2D_BGCOLR_BLUE_Pos (0U)
6819#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
6820#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
6821#define DMA2D_BGCOLR_GREEN_Pos (8U)
6822#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
6823#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
6824#define DMA2D_BGCOLR_RED_Pos (16U)
6825#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
6826#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
6828/******************** Bit definition for DMA2D_FGCMAR register **************/
6829
6830#define DMA2D_FGCMAR_MA_Pos (0U)
6831#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
6832#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
6834/******************** Bit definition for DMA2D_BGCMAR register **************/
6835
6836#define DMA2D_BGCMAR_MA_Pos (0U)
6837#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
6838#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
6840/******************** Bit definition for DMA2D_OPFCCR register **************/
6841
6842#define DMA2D_OPFCCR_CM_Pos (0U)
6843#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
6844#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
6845#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
6846#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
6847#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
6849/******************** Bit definition for DMA2D_OCOLR register ***************/
6850
6853#define DMA2D_OCOLR_BLUE_1 0x000000FFU
6854#define DMA2D_OCOLR_GREEN_1 0x0000FF00U
6855#define DMA2D_OCOLR_RED_1 0x00FF0000U
6856#define DMA2D_OCOLR_ALPHA_1 0xFF000000U
6859#define DMA2D_OCOLR_BLUE_2 0x0000001FU
6860#define DMA2D_OCOLR_GREEN_2 0x000007E0U
6861#define DMA2D_OCOLR_RED_2 0x0000F800U
6864#define DMA2D_OCOLR_BLUE_3 0x0000001FU
6865#define DMA2D_OCOLR_GREEN_3 0x000003E0U
6866#define DMA2D_OCOLR_RED_3 0x00007C00U
6867#define DMA2D_OCOLR_ALPHA_3 0x00008000U
6870#define DMA2D_OCOLR_BLUE_4 0x0000000FU
6871#define DMA2D_OCOLR_GREEN_4 0x000000F0U
6872#define DMA2D_OCOLR_RED_4 0x00000F00U
6873#define DMA2D_OCOLR_ALPHA_4 0x0000F000U
6875/******************** Bit definition for DMA2D_OMAR register ****************/
6876
6877#define DMA2D_OMAR_MA_Pos (0U)
6878#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
6879#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
6881/******************** Bit definition for DMA2D_OOR register *****************/
6882
6883#define DMA2D_OOR_LO_Pos (0U)
6884#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos)
6885#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
6887/******************** Bit definition for DMA2D_NLR register *****************/
6888
6889#define DMA2D_NLR_NL_Pos (0U)
6890#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
6891#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
6892#define DMA2D_NLR_PL_Pos (16U)
6893#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
6894#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
6896/******************** Bit definition for DMA2D_LWR register *****************/
6897
6898#define DMA2D_LWR_LW_Pos (0U)
6899#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
6900#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
6902/******************** Bit definition for DMA2D_AMTCR register ***************/
6903
6904#define DMA2D_AMTCR_EN_Pos (0U)
6905#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
6906#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
6907#define DMA2D_AMTCR_DT_Pos (8U)
6908#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
6909#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
6911/******************** Bit definition for DMA2D_FGCLUT register **************/
6912
6913/******************** Bit definition for DMA2D_BGCLUT register **************/
6914
6915
6916/******************************************************************************/
6917/* */
6918/* Display Serial Interface (DSI) */
6919/* */
6920/******************************************************************************/
6921/******************* Bit definition for DSI_VR register *****************/
6922#define DSI_VR_Pos (1U)
6923#define DSI_VR_Msk (0x18999815UL << DSI_VR_Pos)
6924#define DSI_VR DSI_VR_Msk
6926/******************* Bit definition for DSI_CR register *****************/
6927#define DSI_CR_EN_Pos (0U)
6928#define DSI_CR_EN_Msk (0x1UL << DSI_CR_EN_Pos)
6929#define DSI_CR_EN DSI_CR_EN_Msk
6931/******************* Bit definition for DSI_CCR register ****************/
6932#define DSI_CCR_TXECKDIV_Pos (0U)
6933#define DSI_CCR_TXECKDIV_Msk (0xFFUL << DSI_CCR_TXECKDIV_Pos)
6934#define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk
6935#define DSI_CCR_TXECKDIV0_Pos (0U)
6936#define DSI_CCR_TXECKDIV0_Msk (0x1UL << DSI_CCR_TXECKDIV0_Pos)
6937#define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
6938#define DSI_CCR_TXECKDIV1_Pos (1U)
6939#define DSI_CCR_TXECKDIV1_Msk (0x1UL << DSI_CCR_TXECKDIV1_Pos)
6940#define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
6941#define DSI_CCR_TXECKDIV2_Pos (2U)
6942#define DSI_CCR_TXECKDIV2_Msk (0x1UL << DSI_CCR_TXECKDIV2_Pos)
6943#define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
6944#define DSI_CCR_TXECKDIV3_Pos (3U)
6945#define DSI_CCR_TXECKDIV3_Msk (0x1UL << DSI_CCR_TXECKDIV3_Pos)
6946#define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
6947#define DSI_CCR_TXECKDIV4_Pos (4U)
6948#define DSI_CCR_TXECKDIV4_Msk (0x1UL << DSI_CCR_TXECKDIV4_Pos)
6949#define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
6950#define DSI_CCR_TXECKDIV5_Pos (5U)
6951#define DSI_CCR_TXECKDIV5_Msk (0x1UL << DSI_CCR_TXECKDIV5_Pos)
6952#define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
6953#define DSI_CCR_TXECKDIV6_Pos (6U)
6954#define DSI_CCR_TXECKDIV6_Msk (0x1UL << DSI_CCR_TXECKDIV6_Pos)
6955#define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
6956#define DSI_CCR_TXECKDIV7_Pos (7U)
6957#define DSI_CCR_TXECKDIV7_Msk (0x1UL << DSI_CCR_TXECKDIV7_Pos)
6958#define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
6959
6960#define DSI_CCR_TOCKDIV_Pos (8U)
6961#define DSI_CCR_TOCKDIV_Msk (0xFFUL << DSI_CCR_TOCKDIV_Pos)
6962#define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk
6963#define DSI_CCR_TOCKDIV0_Pos (8U)
6964#define DSI_CCR_TOCKDIV0_Msk (0x1UL << DSI_CCR_TOCKDIV0_Pos)
6965#define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
6966#define DSI_CCR_TOCKDIV1_Pos (9U)
6967#define DSI_CCR_TOCKDIV1_Msk (0x1UL << DSI_CCR_TOCKDIV1_Pos)
6968#define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
6969#define DSI_CCR_TOCKDIV2_Pos (10U)
6970#define DSI_CCR_TOCKDIV2_Msk (0x1UL << DSI_CCR_TOCKDIV2_Pos)
6971#define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
6972#define DSI_CCR_TOCKDIV3_Pos (11U)
6973#define DSI_CCR_TOCKDIV3_Msk (0x1UL << DSI_CCR_TOCKDIV3_Pos)
6974#define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
6975#define DSI_CCR_TOCKDIV4_Pos (12U)
6976#define DSI_CCR_TOCKDIV4_Msk (0x1UL << DSI_CCR_TOCKDIV4_Pos)
6977#define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
6978#define DSI_CCR_TOCKDIV5_Pos (13U)
6979#define DSI_CCR_TOCKDIV5_Msk (0x1UL << DSI_CCR_TOCKDIV5_Pos)
6980#define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
6981#define DSI_CCR_TOCKDIV6_Pos (14U)
6982#define DSI_CCR_TOCKDIV6_Msk (0x1UL << DSI_CCR_TOCKDIV6_Pos)
6983#define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
6984#define DSI_CCR_TOCKDIV7_Pos (15U)
6985#define DSI_CCR_TOCKDIV7_Msk (0x1UL << DSI_CCR_TOCKDIV7_Pos)
6986#define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
6987
6988/******************* Bit definition for DSI_LVCIDR register *************/
6989#define DSI_LVCIDR_VCID_Pos (0U)
6990#define DSI_LVCIDR_VCID_Msk (0x3UL << DSI_LVCIDR_VCID_Pos)
6991#define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk
6992#define DSI_LVCIDR_VCID0_Pos (0U)
6993#define DSI_LVCIDR_VCID0_Msk (0x1UL << DSI_LVCIDR_VCID0_Pos)
6994#define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
6995#define DSI_LVCIDR_VCID1_Pos (1U)
6996#define DSI_LVCIDR_VCID1_Msk (0x1UL << DSI_LVCIDR_VCID1_Pos)
6997#define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
6998
6999/******************* Bit definition for DSI_LCOLCR register *************/
7000#define DSI_LCOLCR_COLC_Pos (0U)
7001#define DSI_LCOLCR_COLC_Msk (0xFUL << DSI_LCOLCR_COLC_Pos)
7002#define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk
7003#define DSI_LCOLCR_COLC0_Pos (0U)
7004#define DSI_LCOLCR_COLC0_Msk (0x1UL << DSI_LCOLCR_COLC0_Pos)
7005#define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
7006#define DSI_LCOLCR_COLC1_Pos (5U)
7007#define DSI_LCOLCR_COLC1_Msk (0x1UL << DSI_LCOLCR_COLC1_Pos)
7008#define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
7009#define DSI_LCOLCR_COLC2_Pos (6U)
7010#define DSI_LCOLCR_COLC2_Msk (0x1UL << DSI_LCOLCR_COLC2_Pos)
7011#define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
7012#define DSI_LCOLCR_COLC3_Pos (7U)
7013#define DSI_LCOLCR_COLC3_Msk (0x1UL << DSI_LCOLCR_COLC3_Pos)
7014#define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
7015
7016#define DSI_LCOLCR_LPE_Pos (8U)
7017#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos)
7018#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk
7020/******************* Bit definition for DSI_LPCR register ***************/
7021#define DSI_LPCR_DEP_Pos (0U)
7022#define DSI_LPCR_DEP_Msk (0x1UL << DSI_LPCR_DEP_Pos)
7023#define DSI_LPCR_DEP DSI_LPCR_DEP_Msk
7024#define DSI_LPCR_VSP_Pos (1U)
7025#define DSI_LPCR_VSP_Msk (0x1UL << DSI_LPCR_VSP_Pos)
7026#define DSI_LPCR_VSP DSI_LPCR_VSP_Msk
7027#define DSI_LPCR_HSP_Pos (2U)
7028#define DSI_LPCR_HSP_Msk (0x1UL << DSI_LPCR_HSP_Pos)
7029#define DSI_LPCR_HSP DSI_LPCR_HSP_Msk
7031/******************* Bit definition for DSI_LPMCR register **************/
7032#define DSI_LPMCR_VLPSIZE_Pos (0U)
7033#define DSI_LPMCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCR_VLPSIZE_Pos)
7034#define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk
7035#define DSI_LPMCR_VLPSIZE0_Pos (0U)
7036#define DSI_LPMCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCR_VLPSIZE0_Pos)
7037#define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
7038#define DSI_LPMCR_VLPSIZE1_Pos (1U)
7039#define DSI_LPMCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCR_VLPSIZE1_Pos)
7040#define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
7041#define DSI_LPMCR_VLPSIZE2_Pos (2U)
7042#define DSI_LPMCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCR_VLPSIZE2_Pos)
7043#define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
7044#define DSI_LPMCR_VLPSIZE3_Pos (3U)
7045#define DSI_LPMCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCR_VLPSIZE3_Pos)
7046#define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
7047#define DSI_LPMCR_VLPSIZE4_Pos (4U)
7048#define DSI_LPMCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCR_VLPSIZE4_Pos)
7049#define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
7050#define DSI_LPMCR_VLPSIZE5_Pos (5U)
7051#define DSI_LPMCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCR_VLPSIZE5_Pos)
7052#define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
7053#define DSI_LPMCR_VLPSIZE6_Pos (6U)
7054#define DSI_LPMCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCR_VLPSIZE6_Pos)
7055#define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
7056#define DSI_LPMCR_VLPSIZE7_Pos (7U)
7057#define DSI_LPMCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCR_VLPSIZE7_Pos)
7058#define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
7059
7060#define DSI_LPMCR_LPSIZE_Pos (16U)
7061#define DSI_LPMCR_LPSIZE_Msk (0xFFUL << DSI_LPMCR_LPSIZE_Pos)
7062#define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk
7063#define DSI_LPMCR_LPSIZE0_Pos (16U)
7064#define DSI_LPMCR_LPSIZE0_Msk (0x1UL << DSI_LPMCR_LPSIZE0_Pos)
7065#define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
7066#define DSI_LPMCR_LPSIZE1_Pos (17U)
7067#define DSI_LPMCR_LPSIZE1_Msk (0x1UL << DSI_LPMCR_LPSIZE1_Pos)
7068#define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
7069#define DSI_LPMCR_LPSIZE2_Pos (18U)
7070#define DSI_LPMCR_LPSIZE2_Msk (0x1UL << DSI_LPMCR_LPSIZE2_Pos)
7071#define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
7072#define DSI_LPMCR_LPSIZE3_Pos (19U)
7073#define DSI_LPMCR_LPSIZE3_Msk (0x1UL << DSI_LPMCR_LPSIZE3_Pos)
7074#define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
7075#define DSI_LPMCR_LPSIZE4_Pos (20U)
7076#define DSI_LPMCR_LPSIZE4_Msk (0x1UL << DSI_LPMCR_LPSIZE4_Pos)
7077#define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
7078#define DSI_LPMCR_LPSIZE5_Pos (21U)
7079#define DSI_LPMCR_LPSIZE5_Msk (0x1UL << DSI_LPMCR_LPSIZE5_Pos)
7080#define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
7081#define DSI_LPMCR_LPSIZE6_Pos (22U)
7082#define DSI_LPMCR_LPSIZE6_Msk (0x1UL << DSI_LPMCR_LPSIZE6_Pos)
7083#define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
7084#define DSI_LPMCR_LPSIZE7_Pos (23U)
7085#define DSI_LPMCR_LPSIZE7_Msk (0x1UL << DSI_LPMCR_LPSIZE7_Pos)
7086#define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
7087
7088/******************* Bit definition for DSI_PCR register ****************/
7089#define DSI_PCR_ETTXE_Pos (0U)
7090#define DSI_PCR_ETTXE_Msk (0x1UL << DSI_PCR_ETTXE_Pos)
7091#define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk
7092#define DSI_PCR_ETRXE_Pos (1U)
7093#define DSI_PCR_ETRXE_Msk (0x1UL << DSI_PCR_ETRXE_Pos)
7094#define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk
7095#define DSI_PCR_BTAE_Pos (2U)
7096#define DSI_PCR_BTAE_Msk (0x1UL << DSI_PCR_BTAE_Pos)
7097#define DSI_PCR_BTAE DSI_PCR_BTAE_Msk
7098#define DSI_PCR_ECCRXE_Pos (3U)
7099#define DSI_PCR_ECCRXE_Msk (0x1UL << DSI_PCR_ECCRXE_Pos)
7100#define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk
7101#define DSI_PCR_CRCRXE_Pos (4U)
7102#define DSI_PCR_CRCRXE_Msk (0x1UL << DSI_PCR_CRCRXE_Pos)
7103#define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk
7105/******************* Bit definition for DSI_GVCIDR register *************/
7106#define DSI_GVCIDR_VCID_Pos (0U)
7107#define DSI_GVCIDR_VCID_Msk (0x3UL << DSI_GVCIDR_VCID_Pos)
7108#define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk
7109#define DSI_GVCIDR_VCID0_Pos (0U)
7110#define DSI_GVCIDR_VCID0_Msk (0x1UL << DSI_GVCIDR_VCID0_Pos)
7111#define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
7112#define DSI_GVCIDR_VCID1_Pos (1U)
7113#define DSI_GVCIDR_VCID1_Msk (0x1UL << DSI_GVCIDR_VCID1_Pos)
7114#define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
7115
7116/******************* Bit definition for DSI_MCR register ****************/
7117#define DSI_MCR_CMDM_Pos (0U)
7118#define DSI_MCR_CMDM_Msk (0x1UL << DSI_MCR_CMDM_Pos)
7119#define DSI_MCR_CMDM DSI_MCR_CMDM_Msk
7121/******************* Bit definition for DSI_VMCR register ***************/
7122#define DSI_VMCR_VMT_Pos (0U)
7123#define DSI_VMCR_VMT_Msk (0x3UL << DSI_VMCR_VMT_Pos)
7124#define DSI_VMCR_VMT DSI_VMCR_VMT_Msk
7125#define DSI_VMCR_VMT0_Pos (0U)
7126#define DSI_VMCR_VMT0_Msk (0x1UL << DSI_VMCR_VMT0_Pos)
7127#define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
7128#define DSI_VMCR_VMT1_Pos (1U)
7129#define DSI_VMCR_VMT1_Msk (0x1UL << DSI_VMCR_VMT1_Pos)
7130#define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
7131
7132#define DSI_VMCR_LPVSAE_Pos (8U)
7133#define DSI_VMCR_LPVSAE_Msk (0x1UL << DSI_VMCR_LPVSAE_Pos)
7134#define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk
7135#define DSI_VMCR_LPVBPE_Pos (9U)
7136#define DSI_VMCR_LPVBPE_Msk (0x1UL << DSI_VMCR_LPVBPE_Pos)
7137#define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk
7138#define DSI_VMCR_LPVFPE_Pos (10U)
7139#define DSI_VMCR_LPVFPE_Msk (0x1UL << DSI_VMCR_LPVFPE_Pos)
7140#define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk
7141#define DSI_VMCR_LPVAE_Pos (11U)
7142#define DSI_VMCR_LPVAE_Msk (0x1UL << DSI_VMCR_LPVAE_Pos)
7143#define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk
7144#define DSI_VMCR_LPHBPE_Pos (12U)
7145#define DSI_VMCR_LPHBPE_Msk (0x1UL << DSI_VMCR_LPHBPE_Pos)
7146#define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk
7147#define DSI_VMCR_LPHFPE_Pos (13U)
7148#define DSI_VMCR_LPHFPE_Msk (0x1UL << DSI_VMCR_LPHFPE_Pos)
7149#define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk
7150#define DSI_VMCR_FBTAAE_Pos (14U)
7151#define DSI_VMCR_FBTAAE_Msk (0x1UL << DSI_VMCR_FBTAAE_Pos)
7152#define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk
7153#define DSI_VMCR_LPCE_Pos (15U)
7154#define DSI_VMCR_LPCE_Msk (0x1UL << DSI_VMCR_LPCE_Pos)
7155#define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk
7156#define DSI_VMCR_PGE_Pos (16U)
7157#define DSI_VMCR_PGE_Msk (0x1UL << DSI_VMCR_PGE_Pos)
7158#define DSI_VMCR_PGE DSI_VMCR_PGE_Msk
7159#define DSI_VMCR_PGM_Pos (20U)
7160#define DSI_VMCR_PGM_Msk (0x1UL << DSI_VMCR_PGM_Pos)
7161#define DSI_VMCR_PGM DSI_VMCR_PGM_Msk
7162#define DSI_VMCR_PGO_Pos (24U)
7163#define DSI_VMCR_PGO_Msk (0x1UL << DSI_VMCR_PGO_Pos)
7164#define DSI_VMCR_PGO DSI_VMCR_PGO_Msk
7166/******************* Bit definition for DSI_VPCR register ***************/
7167#define DSI_VPCR_VPSIZE_Pos (0U)
7168#define DSI_VPCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCR_VPSIZE_Pos)
7169#define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk
7170#define DSI_VPCR_VPSIZE0_Pos (0U)
7171#define DSI_VPCR_VPSIZE0_Msk (0x1UL << DSI_VPCR_VPSIZE0_Pos)
7172#define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
7173#define DSI_VPCR_VPSIZE1_Pos (1U)
7174#define DSI_VPCR_VPSIZE1_Msk (0x1UL << DSI_VPCR_VPSIZE1_Pos)
7175#define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
7176#define DSI_VPCR_VPSIZE2_Pos (2U)
7177#define DSI_VPCR_VPSIZE2_Msk (0x1UL << DSI_VPCR_VPSIZE2_Pos)
7178#define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
7179#define DSI_VPCR_VPSIZE3_Pos (3U)
7180#define DSI_VPCR_VPSIZE3_Msk (0x1UL << DSI_VPCR_VPSIZE3_Pos)
7181#define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
7182#define DSI_VPCR_VPSIZE4_Pos (4U)
7183#define DSI_VPCR_VPSIZE4_Msk (0x1UL << DSI_VPCR_VPSIZE4_Pos)
7184#define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
7185#define DSI_VPCR_VPSIZE5_Pos (5U)
7186#define DSI_VPCR_VPSIZE5_Msk (0x1UL << DSI_VPCR_VPSIZE5_Pos)
7187#define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
7188#define DSI_VPCR_VPSIZE6_Pos (6U)
7189#define DSI_VPCR_VPSIZE6_Msk (0x1UL << DSI_VPCR_VPSIZE6_Pos)
7190#define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
7191#define DSI_VPCR_VPSIZE7_Pos (7U)
7192#define DSI_VPCR_VPSIZE7_Msk (0x1UL << DSI_VPCR_VPSIZE7_Pos)
7193#define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
7194#define DSI_VPCR_VPSIZE8_Pos (8U)
7195#define DSI_VPCR_VPSIZE8_Msk (0x1UL << DSI_VPCR_VPSIZE8_Pos)
7196#define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
7197#define DSI_VPCR_VPSIZE9_Pos (9U)
7198#define DSI_VPCR_VPSIZE9_Msk (0x1UL << DSI_VPCR_VPSIZE9_Pos)
7199#define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
7200#define DSI_VPCR_VPSIZE10_Pos (10U)
7201#define DSI_VPCR_VPSIZE10_Msk (0x1UL << DSI_VPCR_VPSIZE10_Pos)
7202#define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
7203#define DSI_VPCR_VPSIZE11_Pos (11U)
7204#define DSI_VPCR_VPSIZE11_Msk (0x1UL << DSI_VPCR_VPSIZE11_Pos)
7205#define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
7206#define DSI_VPCR_VPSIZE12_Pos (12U)
7207#define DSI_VPCR_VPSIZE12_Msk (0x1UL << DSI_VPCR_VPSIZE12_Pos)
7208#define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
7209#define DSI_VPCR_VPSIZE13_Pos (13U)
7210#define DSI_VPCR_VPSIZE13_Msk (0x1UL << DSI_VPCR_VPSIZE13_Pos)
7211#define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
7212
7213/******************* Bit definition for DSI_VCCR register ***************/
7214#define DSI_VCCR_NUMC_Pos (0U)
7215#define DSI_VCCR_NUMC_Msk (0x1FFFUL << DSI_VCCR_NUMC_Pos)
7216#define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk
7217#define DSI_VCCR_NUMC0_Pos (0U)
7218#define DSI_VCCR_NUMC0_Msk (0x1UL << DSI_VCCR_NUMC0_Pos)
7219#define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
7220#define DSI_VCCR_NUMC1_Pos (1U)
7221#define DSI_VCCR_NUMC1_Msk (0x1UL << DSI_VCCR_NUMC1_Pos)
7222#define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
7223#define DSI_VCCR_NUMC2_Pos (2U)
7224#define DSI_VCCR_NUMC2_Msk (0x1UL << DSI_VCCR_NUMC2_Pos)
7225#define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
7226#define DSI_VCCR_NUMC3_Pos (3U)
7227#define DSI_VCCR_NUMC3_Msk (0x1UL << DSI_VCCR_NUMC3_Pos)
7228#define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
7229#define DSI_VCCR_NUMC4_Pos (4U)
7230#define DSI_VCCR_NUMC4_Msk (0x1UL << DSI_VCCR_NUMC4_Pos)
7231#define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
7232#define DSI_VCCR_NUMC5_Pos (5U)
7233#define DSI_VCCR_NUMC5_Msk (0x1UL << DSI_VCCR_NUMC5_Pos)
7234#define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
7235#define DSI_VCCR_NUMC6_Pos (6U)
7236#define DSI_VCCR_NUMC6_Msk (0x1UL << DSI_VCCR_NUMC6_Pos)
7237#define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
7238#define DSI_VCCR_NUMC7_Pos (7U)
7239#define DSI_VCCR_NUMC7_Msk (0x1UL << DSI_VCCR_NUMC7_Pos)
7240#define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
7241#define DSI_VCCR_NUMC8_Pos (8U)
7242#define DSI_VCCR_NUMC8_Msk (0x1UL << DSI_VCCR_NUMC8_Pos)
7243#define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
7244#define DSI_VCCR_NUMC9_Pos (9U)
7245#define DSI_VCCR_NUMC9_Msk (0x1UL << DSI_VCCR_NUMC9_Pos)
7246#define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
7247#define DSI_VCCR_NUMC10_Pos (10U)
7248#define DSI_VCCR_NUMC10_Msk (0x1UL << DSI_VCCR_NUMC10_Pos)
7249#define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
7250#define DSI_VCCR_NUMC11_Pos (11U)
7251#define DSI_VCCR_NUMC11_Msk (0x1UL << DSI_VCCR_NUMC11_Pos)
7252#define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
7253#define DSI_VCCR_NUMC12_Pos (12U)
7254#define DSI_VCCR_NUMC12_Msk (0x1UL << DSI_VCCR_NUMC12_Pos)
7255#define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
7256
7257/******************* Bit definition for DSI_VNPCR register **************/
7258#define DSI_VNPCR_NPSIZE_Pos (0U)
7259#define DSI_VNPCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos)
7260#define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk
7261#define DSI_VNPCR_NPSIZE0_Pos (0U)
7262#define DSI_VNPCR_NPSIZE0_Msk (0x1UL << DSI_VNPCR_NPSIZE0_Pos)
7263#define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
7264#define DSI_VNPCR_NPSIZE1_Pos (1U)
7265#define DSI_VNPCR_NPSIZE1_Msk (0x1UL << DSI_VNPCR_NPSIZE1_Pos)
7266#define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
7267#define DSI_VNPCR_NPSIZE2_Pos (2U)
7268#define DSI_VNPCR_NPSIZE2_Msk (0x1UL << DSI_VNPCR_NPSIZE2_Pos)
7269#define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
7270#define DSI_VNPCR_NPSIZE3_Pos (3U)
7271#define DSI_VNPCR_NPSIZE3_Msk (0x1UL << DSI_VNPCR_NPSIZE3_Pos)
7272#define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
7273#define DSI_VNPCR_NPSIZE4_Pos (4U)
7274#define DSI_VNPCR_NPSIZE4_Msk (0x1UL << DSI_VNPCR_NPSIZE4_Pos)
7275#define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
7276#define DSI_VNPCR_NPSIZE5_Pos (5U)
7277#define DSI_VNPCR_NPSIZE5_Msk (0x1UL << DSI_VNPCR_NPSIZE5_Pos)
7278#define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
7279#define DSI_VNPCR_NPSIZE6_Pos (6U)
7280#define DSI_VNPCR_NPSIZE6_Msk (0x1UL << DSI_VNPCR_NPSIZE6_Pos)
7281#define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
7282#define DSI_VNPCR_NPSIZE7_Pos (7U)
7283#define DSI_VNPCR_NPSIZE7_Msk (0x1UL << DSI_VNPCR_NPSIZE7_Pos)
7284#define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
7285#define DSI_VNPCR_NPSIZE8_Pos (8U)
7286#define DSI_VNPCR_NPSIZE8_Msk (0x1UL << DSI_VNPCR_NPSIZE8_Pos)
7287#define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
7288#define DSI_VNPCR_NPSIZE9_Pos (9U)
7289#define DSI_VNPCR_NPSIZE9_Msk (0x1UL << DSI_VNPCR_NPSIZE9_Pos)
7290#define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
7291#define DSI_VNPCR_NPSIZE10_Pos (10U)
7292#define DSI_VNPCR_NPSIZE10_Msk (0x1UL << DSI_VNPCR_NPSIZE10_Pos)
7293#define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
7294#define DSI_VNPCR_NPSIZE11_Pos (11U)
7295#define DSI_VNPCR_NPSIZE11_Msk (0x1UL << DSI_VNPCR_NPSIZE11_Pos)
7296#define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
7297#define DSI_VNPCR_NPSIZE12_Pos (12U)
7298#define DSI_VNPCR_NPSIZE12_Msk (0x1UL << DSI_VNPCR_NPSIZE12_Pos)
7299#define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
7300
7301/******************* Bit definition for DSI_VHSACR register *************/
7302#define DSI_VHSACR_HSA_Pos (0U)
7303#define DSI_VHSACR_HSA_Msk (0xFFFUL << DSI_VHSACR_HSA_Pos)
7304#define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk
7305#define DSI_VHSACR_HSA0_Pos (0U)
7306#define DSI_VHSACR_HSA0_Msk (0x1UL << DSI_VHSACR_HSA0_Pos)
7307#define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
7308#define DSI_VHSACR_HSA1_Pos (1U)
7309#define DSI_VHSACR_HSA1_Msk (0x1UL << DSI_VHSACR_HSA1_Pos)
7310#define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
7311#define DSI_VHSACR_HSA2_Pos (2U)
7312#define DSI_VHSACR_HSA2_Msk (0x1UL << DSI_VHSACR_HSA2_Pos)
7313#define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
7314#define DSI_VHSACR_HSA3_Pos (3U)
7315#define DSI_VHSACR_HSA3_Msk (0x1UL << DSI_VHSACR_HSA3_Pos)
7316#define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
7317#define DSI_VHSACR_HSA4_Pos (4U)
7318#define DSI_VHSACR_HSA4_Msk (0x1UL << DSI_VHSACR_HSA4_Pos)
7319#define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
7320#define DSI_VHSACR_HSA5_Pos (5U)
7321#define DSI_VHSACR_HSA5_Msk (0x1UL << DSI_VHSACR_HSA5_Pos)
7322#define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
7323#define DSI_VHSACR_HSA6_Pos (6U)
7324#define DSI_VHSACR_HSA6_Msk (0x1UL << DSI_VHSACR_HSA6_Pos)
7325#define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
7326#define DSI_VHSACR_HSA7_Pos (7U)
7327#define DSI_VHSACR_HSA7_Msk (0x1UL << DSI_VHSACR_HSA7_Pos)
7328#define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
7329#define DSI_VHSACR_HSA8_Pos (8U)
7330#define DSI_VHSACR_HSA8_Msk (0x1UL << DSI_VHSACR_HSA8_Pos)
7331#define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
7332#define DSI_VHSACR_HSA9_Pos (9U)
7333#define DSI_VHSACR_HSA9_Msk (0x1UL << DSI_VHSACR_HSA9_Pos)
7334#define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
7335#define DSI_VHSACR_HSA10_Pos (10U)
7336#define DSI_VHSACR_HSA10_Msk (0x1UL << DSI_VHSACR_HSA10_Pos)
7337#define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
7338#define DSI_VHSACR_HSA11_Pos (11U)
7339#define DSI_VHSACR_HSA11_Msk (0x1UL << DSI_VHSACR_HSA11_Pos)
7340#define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
7341
7342/******************* Bit definition for DSI_VHBPCR register *************/
7343#define DSI_VHBPCR_HBP_Pos (0U)
7344#define DSI_VHBPCR_HBP_Msk (0xFFFUL << DSI_VHBPCR_HBP_Pos)
7345#define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk
7346#define DSI_VHBPCR_HBP0_Pos (0U)
7347#define DSI_VHBPCR_HBP0_Msk (0x1UL << DSI_VHBPCR_HBP0_Pos)
7348#define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
7349#define DSI_VHBPCR_HBP1_Pos (1U)
7350#define DSI_VHBPCR_HBP1_Msk (0x1UL << DSI_VHBPCR_HBP1_Pos)
7351#define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
7352#define DSI_VHBPCR_HBP2_Pos (2U)
7353#define DSI_VHBPCR_HBP2_Msk (0x1UL << DSI_VHBPCR_HBP2_Pos)
7354#define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
7355#define DSI_VHBPCR_HBP3_Pos (3U)
7356#define DSI_VHBPCR_HBP3_Msk (0x1UL << DSI_VHBPCR_HBP3_Pos)
7357#define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
7358#define DSI_VHBPCR_HBP4_Pos (4U)
7359#define DSI_VHBPCR_HBP4_Msk (0x1UL << DSI_VHBPCR_HBP4_Pos)
7360#define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
7361#define DSI_VHBPCR_HBP5_Pos (5U)
7362#define DSI_VHBPCR_HBP5_Msk (0x1UL << DSI_VHBPCR_HBP5_Pos)
7363#define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
7364#define DSI_VHBPCR_HBP6_Pos (6U)
7365#define DSI_VHBPCR_HBP6_Msk (0x1UL << DSI_VHBPCR_HBP6_Pos)
7366#define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
7367#define DSI_VHBPCR_HBP7_Pos (7U)
7368#define DSI_VHBPCR_HBP7_Msk (0x1UL << DSI_VHBPCR_HBP7_Pos)
7369#define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
7370#define DSI_VHBPCR_HBP8_Pos (8U)
7371#define DSI_VHBPCR_HBP8_Msk (0x1UL << DSI_VHBPCR_HBP8_Pos)
7372#define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
7373#define DSI_VHBPCR_HBP9_Pos (9U)
7374#define DSI_VHBPCR_HBP9_Msk (0x1UL << DSI_VHBPCR_HBP9_Pos)
7375#define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
7376#define DSI_VHBPCR_HBP10_Pos (10U)
7377#define DSI_VHBPCR_HBP10_Msk (0x1UL << DSI_VHBPCR_HBP10_Pos)
7378#define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
7379#define DSI_VHBPCR_HBP11_Pos (11U)
7380#define DSI_VHBPCR_HBP11_Msk (0x1UL << DSI_VHBPCR_HBP11_Pos)
7381#define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
7382
7383/******************* Bit definition for DSI_VLCR register ***************/
7384#define DSI_VLCR_HLINE_Pos (0U)
7385#define DSI_VLCR_HLINE_Msk (0x7FFFUL << DSI_VLCR_HLINE_Pos)
7386#define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk
7387#define DSI_VLCR_HLINE0_Pos (0U)
7388#define DSI_VLCR_HLINE0_Msk (0x1UL << DSI_VLCR_HLINE0_Pos)
7389#define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
7390#define DSI_VLCR_HLINE1_Pos (1U)
7391#define DSI_VLCR_HLINE1_Msk (0x1UL << DSI_VLCR_HLINE1_Pos)
7392#define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
7393#define DSI_VLCR_HLINE2_Pos (2U)
7394#define DSI_VLCR_HLINE2_Msk (0x1UL << DSI_VLCR_HLINE2_Pos)
7395#define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
7396#define DSI_VLCR_HLINE3_Pos (3U)
7397#define DSI_VLCR_HLINE3_Msk (0x1UL << DSI_VLCR_HLINE3_Pos)
7398#define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
7399#define DSI_VLCR_HLINE4_Pos (4U)
7400#define DSI_VLCR_HLINE4_Msk (0x1UL << DSI_VLCR_HLINE4_Pos)
7401#define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
7402#define DSI_VLCR_HLINE5_Pos (5U)
7403#define DSI_VLCR_HLINE5_Msk (0x1UL << DSI_VLCR_HLINE5_Pos)
7404#define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
7405#define DSI_VLCR_HLINE6_Pos (6U)
7406#define DSI_VLCR_HLINE6_Msk (0x1UL << DSI_VLCR_HLINE6_Pos)
7407#define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
7408#define DSI_VLCR_HLINE7_Pos (7U)
7409#define DSI_VLCR_HLINE7_Msk (0x1UL << DSI_VLCR_HLINE7_Pos)
7410#define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
7411#define DSI_VLCR_HLINE8_Pos (8U)
7412#define DSI_VLCR_HLINE8_Msk (0x1UL << DSI_VLCR_HLINE8_Pos)
7413#define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
7414#define DSI_VLCR_HLINE9_Pos (9U)
7415#define DSI_VLCR_HLINE9_Msk (0x1UL << DSI_VLCR_HLINE9_Pos)
7416#define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
7417#define DSI_VLCR_HLINE10_Pos (10U)
7418#define DSI_VLCR_HLINE10_Msk (0x1UL << DSI_VLCR_HLINE10_Pos)
7419#define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
7420#define DSI_VLCR_HLINE11_Pos (11U)
7421#define DSI_VLCR_HLINE11_Msk (0x1UL << DSI_VLCR_HLINE11_Pos)
7422#define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
7423#define DSI_VLCR_HLINE12_Pos (12U)
7424#define DSI_VLCR_HLINE12_Msk (0x1UL << DSI_VLCR_HLINE12_Pos)
7425#define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
7426#define DSI_VLCR_HLINE13_Pos (13U)
7427#define DSI_VLCR_HLINE13_Msk (0x1UL << DSI_VLCR_HLINE13_Pos)
7428#define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
7429#define DSI_VLCR_HLINE14_Pos (14U)
7430#define DSI_VLCR_HLINE14_Msk (0x1UL << DSI_VLCR_HLINE14_Pos)
7431#define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
7432
7433/******************* Bit definition for DSI_VVSACR register *************/
7434#define DSI_VVSACR_VSA_Pos (0U)
7435#define DSI_VVSACR_VSA_Msk (0x3FFUL << DSI_VVSACR_VSA_Pos)
7436#define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk
7437#define DSI_VVSACR_VSA0_Pos (0U)
7438#define DSI_VVSACR_VSA0_Msk (0x1UL << DSI_VVSACR_VSA0_Pos)
7439#define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
7440#define DSI_VVSACR_VSA1_Pos (1U)
7441#define DSI_VVSACR_VSA1_Msk (0x1UL << DSI_VVSACR_VSA1_Pos)
7442#define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
7443#define DSI_VVSACR_VSA2_Pos (2U)
7444#define DSI_VVSACR_VSA2_Msk (0x1UL << DSI_VVSACR_VSA2_Pos)
7445#define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
7446#define DSI_VVSACR_VSA3_Pos (3U)
7447#define DSI_VVSACR_VSA3_Msk (0x1UL << DSI_VVSACR_VSA3_Pos)
7448#define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
7449#define DSI_VVSACR_VSA4_Pos (4U)
7450#define DSI_VVSACR_VSA4_Msk (0x1UL << DSI_VVSACR_VSA4_Pos)
7451#define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
7452#define DSI_VVSACR_VSA5_Pos (5U)
7453#define DSI_VVSACR_VSA5_Msk (0x1UL << DSI_VVSACR_VSA5_Pos)
7454#define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
7455#define DSI_VVSACR_VSA6_Pos (6U)
7456#define DSI_VVSACR_VSA6_Msk (0x1UL << DSI_VVSACR_VSA6_Pos)
7457#define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
7458#define DSI_VVSACR_VSA7_Pos (7U)
7459#define DSI_VVSACR_VSA7_Msk (0x1UL << DSI_VVSACR_VSA7_Pos)
7460#define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
7461#define DSI_VVSACR_VSA8_Pos (8U)
7462#define DSI_VVSACR_VSA8_Msk (0x1UL << DSI_VVSACR_VSA8_Pos)
7463#define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
7464#define DSI_VVSACR_VSA9_Pos (9U)
7465#define DSI_VVSACR_VSA9_Msk (0x1UL << DSI_VVSACR_VSA9_Pos)
7466#define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
7467
7468/******************* Bit definition for DSI_VVBPCR register *************/
7469#define DSI_VVBPCR_VBP_Pos (0U)
7470#define DSI_VVBPCR_VBP_Msk (0x3FFUL << DSI_VVBPCR_VBP_Pos)
7471#define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk
7472#define DSI_VVBPCR_VBP0_Pos (0U)
7473#define DSI_VVBPCR_VBP0_Msk (0x1UL << DSI_VVBPCR_VBP0_Pos)
7474#define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
7475#define DSI_VVBPCR_VBP1_Pos (1U)
7476#define DSI_VVBPCR_VBP1_Msk (0x1UL << DSI_VVBPCR_VBP1_Pos)
7477#define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
7478#define DSI_VVBPCR_VBP2_Pos (2U)
7479#define DSI_VVBPCR_VBP2_Msk (0x1UL << DSI_VVBPCR_VBP2_Pos)
7480#define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
7481#define DSI_VVBPCR_VBP3_Pos (3U)
7482#define DSI_VVBPCR_VBP3_Msk (0x1UL << DSI_VVBPCR_VBP3_Pos)
7483#define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
7484#define DSI_VVBPCR_VBP4_Pos (4U)
7485#define DSI_VVBPCR_VBP4_Msk (0x1UL << DSI_VVBPCR_VBP4_Pos)
7486#define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
7487#define DSI_VVBPCR_VBP5_Pos (5U)
7488#define DSI_VVBPCR_VBP5_Msk (0x1UL << DSI_VVBPCR_VBP5_Pos)
7489#define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
7490#define DSI_VVBPCR_VBP6_Pos (6U)
7491#define DSI_VVBPCR_VBP6_Msk (0x1UL << DSI_VVBPCR_VBP6_Pos)
7492#define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
7493#define DSI_VVBPCR_VBP7_Pos (7U)
7494#define DSI_VVBPCR_VBP7_Msk (0x1UL << DSI_VVBPCR_VBP7_Pos)
7495#define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
7496#define DSI_VVBPCR_VBP8_Pos (8U)
7497#define DSI_VVBPCR_VBP8_Msk (0x1UL << DSI_VVBPCR_VBP8_Pos)
7498#define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
7499#define DSI_VVBPCR_VBP9_Pos (9U)
7500#define DSI_VVBPCR_VBP9_Msk (0x1UL << DSI_VVBPCR_VBP9_Pos)
7501#define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
7502
7503/******************* Bit definition for DSI_VVFPCR register *************/
7504#define DSI_VVFPCR_VFP_Pos (0U)
7505#define DSI_VVFPCR_VFP_Msk (0x3FFUL << DSI_VVFPCR_VFP_Pos)
7506#define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk
7507#define DSI_VVFPCR_VFP0_Pos (0U)
7508#define DSI_VVFPCR_VFP0_Msk (0x1UL << DSI_VVFPCR_VFP0_Pos)
7509#define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
7510#define DSI_VVFPCR_VFP1_Pos (1U)
7511#define DSI_VVFPCR_VFP1_Msk (0x1UL << DSI_VVFPCR_VFP1_Pos)
7512#define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
7513#define DSI_VVFPCR_VFP2_Pos (2U)
7514#define DSI_VVFPCR_VFP2_Msk (0x1UL << DSI_VVFPCR_VFP2_Pos)
7515#define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
7516#define DSI_VVFPCR_VFP3_Pos (3U)
7517#define DSI_VVFPCR_VFP3_Msk (0x1UL << DSI_VVFPCR_VFP3_Pos)
7518#define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
7519#define DSI_VVFPCR_VFP4_Pos (4U)
7520#define DSI_VVFPCR_VFP4_Msk (0x1UL << DSI_VVFPCR_VFP4_Pos)
7521#define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
7522#define DSI_VVFPCR_VFP5_Pos (5U)
7523#define DSI_VVFPCR_VFP5_Msk (0x1UL << DSI_VVFPCR_VFP5_Pos)
7524#define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
7525#define DSI_VVFPCR_VFP6_Pos (6U)
7526#define DSI_VVFPCR_VFP6_Msk (0x1UL << DSI_VVFPCR_VFP6_Pos)
7527#define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
7528#define DSI_VVFPCR_VFP7_Pos (7U)
7529#define DSI_VVFPCR_VFP7_Msk (0x1UL << DSI_VVFPCR_VFP7_Pos)
7530#define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
7531#define DSI_VVFPCR_VFP8_Pos (8U)
7532#define DSI_VVFPCR_VFP8_Msk (0x1UL << DSI_VVFPCR_VFP8_Pos)
7533#define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
7534#define DSI_VVFPCR_VFP9_Pos (9U)
7535#define DSI_VVFPCR_VFP9_Msk (0x1UL << DSI_VVFPCR_VFP9_Pos)
7536#define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
7537
7538/******************* Bit definition for DSI_VVACR register **************/
7539#define DSI_VVACR_VA_Pos (0U)
7540#define DSI_VVACR_VA_Msk (0x3FFFUL << DSI_VVACR_VA_Pos)
7541#define DSI_VVACR_VA DSI_VVACR_VA_Msk
7542#define DSI_VVACR_VA0_Pos (0U)
7543#define DSI_VVACR_VA0_Msk (0x1UL << DSI_VVACR_VA0_Pos)
7544#define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
7545#define DSI_VVACR_VA1_Pos (1U)
7546#define DSI_VVACR_VA1_Msk (0x1UL << DSI_VVACR_VA1_Pos)
7547#define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
7548#define DSI_VVACR_VA2_Pos (2U)
7549#define DSI_VVACR_VA2_Msk (0x1UL << DSI_VVACR_VA2_Pos)
7550#define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
7551#define DSI_VVACR_VA3_Pos (3U)
7552#define DSI_VVACR_VA3_Msk (0x1UL << DSI_VVACR_VA3_Pos)
7553#define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
7554#define DSI_VVACR_VA4_Pos (4U)
7555#define DSI_VVACR_VA4_Msk (0x1UL << DSI_VVACR_VA4_Pos)
7556#define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
7557#define DSI_VVACR_VA5_Pos (5U)
7558#define DSI_VVACR_VA5_Msk (0x1UL << DSI_VVACR_VA5_Pos)
7559#define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
7560#define DSI_VVACR_VA6_Pos (6U)
7561#define DSI_VVACR_VA6_Msk (0x1UL << DSI_VVACR_VA6_Pos)
7562#define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
7563#define DSI_VVACR_VA7_Pos (7U)
7564#define DSI_VVACR_VA7_Msk (0x1UL << DSI_VVACR_VA7_Pos)
7565#define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
7566#define DSI_VVACR_VA8_Pos (8U)
7567#define DSI_VVACR_VA8_Msk (0x1UL << DSI_VVACR_VA8_Pos)
7568#define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
7569#define DSI_VVACR_VA9_Pos (9U)
7570#define DSI_VVACR_VA9_Msk (0x1UL << DSI_VVACR_VA9_Pos)
7571#define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
7572#define DSI_VVACR_VA10_Pos (10U)
7573#define DSI_VVACR_VA10_Msk (0x1UL << DSI_VVACR_VA10_Pos)
7574#define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
7575#define DSI_VVACR_VA11_Pos (11U)
7576#define DSI_VVACR_VA11_Msk (0x1UL << DSI_VVACR_VA11_Pos)
7577#define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
7578#define DSI_VVACR_VA12_Pos (12U)
7579#define DSI_VVACR_VA12_Msk (0x1UL << DSI_VVACR_VA12_Pos)
7580#define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
7581#define DSI_VVACR_VA13_Pos (13U)
7582#define DSI_VVACR_VA13_Msk (0x1UL << DSI_VVACR_VA13_Pos)
7583#define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
7584
7585/******************* Bit definition for DSI_LCCR register ***************/
7586#define DSI_LCCR_CMDSIZE_Pos (0U)
7587#define DSI_LCCR_CMDSIZE_Msk (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos)
7588#define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk
7589#define DSI_LCCR_CMDSIZE0_Pos (0U)
7590#define DSI_LCCR_CMDSIZE0_Msk (0x1UL << DSI_LCCR_CMDSIZE0_Pos)
7591#define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
7592#define DSI_LCCR_CMDSIZE1_Pos (1U)
7593#define DSI_LCCR_CMDSIZE1_Msk (0x1UL << DSI_LCCR_CMDSIZE1_Pos)
7594#define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
7595#define DSI_LCCR_CMDSIZE2_Pos (2U)
7596#define DSI_LCCR_CMDSIZE2_Msk (0x1UL << DSI_LCCR_CMDSIZE2_Pos)
7597#define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
7598#define DSI_LCCR_CMDSIZE3_Pos (3U)
7599#define DSI_LCCR_CMDSIZE3_Msk (0x1UL << DSI_LCCR_CMDSIZE3_Pos)
7600#define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
7601#define DSI_LCCR_CMDSIZE4_Pos (4U)
7602#define DSI_LCCR_CMDSIZE4_Msk (0x1UL << DSI_LCCR_CMDSIZE4_Pos)
7603#define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
7604#define DSI_LCCR_CMDSIZE5_Pos (5U)
7605#define DSI_LCCR_CMDSIZE5_Msk (0x1UL << DSI_LCCR_CMDSIZE5_Pos)
7606#define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
7607#define DSI_LCCR_CMDSIZE6_Pos (6U)
7608#define DSI_LCCR_CMDSIZE6_Msk (0x1UL << DSI_LCCR_CMDSIZE6_Pos)
7609#define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
7610#define DSI_LCCR_CMDSIZE7_Pos (7U)
7611#define DSI_LCCR_CMDSIZE7_Msk (0x1UL << DSI_LCCR_CMDSIZE7_Pos)
7612#define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
7613#define DSI_LCCR_CMDSIZE8_Pos (8U)
7614#define DSI_LCCR_CMDSIZE8_Msk (0x1UL << DSI_LCCR_CMDSIZE8_Pos)
7615#define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
7616#define DSI_LCCR_CMDSIZE9_Pos (9U)
7617#define DSI_LCCR_CMDSIZE9_Msk (0x1UL << DSI_LCCR_CMDSIZE9_Pos)
7618#define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
7619#define DSI_LCCR_CMDSIZE10_Pos (10U)
7620#define DSI_LCCR_CMDSIZE10_Msk (0x1UL << DSI_LCCR_CMDSIZE10_Pos)
7621#define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
7622#define DSI_LCCR_CMDSIZE11_Pos (11U)
7623#define DSI_LCCR_CMDSIZE11_Msk (0x1UL << DSI_LCCR_CMDSIZE11_Pos)
7624#define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
7625#define DSI_LCCR_CMDSIZE12_Pos (12U)
7626#define DSI_LCCR_CMDSIZE12_Msk (0x1UL << DSI_LCCR_CMDSIZE12_Pos)
7627#define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
7628#define DSI_LCCR_CMDSIZE13_Pos (13U)
7629#define DSI_LCCR_CMDSIZE13_Msk (0x1UL << DSI_LCCR_CMDSIZE13_Pos)
7630#define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
7631#define DSI_LCCR_CMDSIZE14_Pos (14U)
7632#define DSI_LCCR_CMDSIZE14_Msk (0x1UL << DSI_LCCR_CMDSIZE14_Pos)
7633#define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
7634#define DSI_LCCR_CMDSIZE15_Pos (15U)
7635#define DSI_LCCR_CMDSIZE15_Msk (0x1UL << DSI_LCCR_CMDSIZE15_Pos)
7636#define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
7637
7638/******************* Bit definition for DSI_CMCR register ***************/
7639#define DSI_CMCR_TEARE_Pos (0U)
7640#define DSI_CMCR_TEARE_Msk (0x1UL << DSI_CMCR_TEARE_Pos)
7641#define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk
7642#define DSI_CMCR_ARE_Pos (1U)
7643#define DSI_CMCR_ARE_Msk (0x1UL << DSI_CMCR_ARE_Pos)
7644#define DSI_CMCR_ARE DSI_CMCR_ARE_Msk
7645#define DSI_CMCR_GSW0TX_Pos (8U)
7646#define DSI_CMCR_GSW0TX_Msk (0x1UL << DSI_CMCR_GSW0TX_Pos)
7647#define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk
7648#define DSI_CMCR_GSW1TX_Pos (9U)
7649#define DSI_CMCR_GSW1TX_Msk (0x1UL << DSI_CMCR_GSW1TX_Pos)
7650#define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk
7651#define DSI_CMCR_GSW2TX_Pos (10U)
7652#define DSI_CMCR_GSW2TX_Msk (0x1UL << DSI_CMCR_GSW2TX_Pos)
7653#define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk
7654#define DSI_CMCR_GSR0TX_Pos (11U)
7655#define DSI_CMCR_GSR0TX_Msk (0x1UL << DSI_CMCR_GSR0TX_Pos)
7656#define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk
7657#define DSI_CMCR_GSR1TX_Pos (12U)
7658#define DSI_CMCR_GSR1TX_Msk (0x1UL << DSI_CMCR_GSR1TX_Pos)
7659#define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk
7660#define DSI_CMCR_GSR2TX_Pos (13U)
7661#define DSI_CMCR_GSR2TX_Msk (0x1UL << DSI_CMCR_GSR2TX_Pos)
7662#define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk
7663#define DSI_CMCR_GLWTX_Pos (14U)
7664#define DSI_CMCR_GLWTX_Msk (0x1UL << DSI_CMCR_GLWTX_Pos)
7665#define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk
7666#define DSI_CMCR_DSW0TX_Pos (16U)
7667#define DSI_CMCR_DSW0TX_Msk (0x1UL << DSI_CMCR_DSW0TX_Pos)
7668#define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk
7669#define DSI_CMCR_DSW1TX_Pos (17U)
7670#define DSI_CMCR_DSW1TX_Msk (0x1UL << DSI_CMCR_DSW1TX_Pos)
7671#define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk
7672#define DSI_CMCR_DSR0TX_Pos (18U)
7673#define DSI_CMCR_DSR0TX_Msk (0x1UL << DSI_CMCR_DSR0TX_Pos)
7674#define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk
7675#define DSI_CMCR_DLWTX_Pos (19U)
7676#define DSI_CMCR_DLWTX_Msk (0x1UL << DSI_CMCR_DLWTX_Pos)
7677#define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk
7678#define DSI_CMCR_MRDPS_Pos (24U)
7679#define DSI_CMCR_MRDPS_Msk (0x1UL << DSI_CMCR_MRDPS_Pos)
7680#define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk
7682/******************* Bit definition for DSI_GHCR register ***************/
7683#define DSI_GHCR_DT_Pos (0U)
7684#define DSI_GHCR_DT_Msk (0x3FUL << DSI_GHCR_DT_Pos)
7685#define DSI_GHCR_DT DSI_GHCR_DT_Msk
7686#define DSI_GHCR_DT0_Pos (0U)
7687#define DSI_GHCR_DT0_Msk (0x1UL << DSI_GHCR_DT0_Pos)
7688#define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
7689#define DSI_GHCR_DT1_Pos (1U)
7690#define DSI_GHCR_DT1_Msk (0x1UL << DSI_GHCR_DT1_Pos)
7691#define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
7692#define DSI_GHCR_DT2_Pos (2U)
7693#define DSI_GHCR_DT2_Msk (0x1UL << DSI_GHCR_DT2_Pos)
7694#define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
7695#define DSI_GHCR_DT3_Pos (3U)
7696#define DSI_GHCR_DT3_Msk (0x1UL << DSI_GHCR_DT3_Pos)
7697#define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
7698#define DSI_GHCR_DT4_Pos (4U)
7699#define DSI_GHCR_DT4_Msk (0x1UL << DSI_GHCR_DT4_Pos)
7700#define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
7701#define DSI_GHCR_DT5_Pos (5U)
7702#define DSI_GHCR_DT5_Msk (0x1UL << DSI_GHCR_DT5_Pos)
7703#define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
7704
7705#define DSI_GHCR_VCID_Pos (6U)
7706#define DSI_GHCR_VCID_Msk (0x3UL << DSI_GHCR_VCID_Pos)
7707#define DSI_GHCR_VCID DSI_GHCR_VCID_Msk
7708#define DSI_GHCR_VCID0_Pos (6U)
7709#define DSI_GHCR_VCID0_Msk (0x1UL << DSI_GHCR_VCID0_Pos)
7710#define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
7711#define DSI_GHCR_VCID1_Pos (7U)
7712#define DSI_GHCR_VCID1_Msk (0x1UL << DSI_GHCR_VCID1_Pos)
7713#define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
7714
7715#define DSI_GHCR_WCLSB_Pos (8U)
7716#define DSI_GHCR_WCLSB_Msk (0xFFUL << DSI_GHCR_WCLSB_Pos)
7717#define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk
7718#define DSI_GHCR_WCLSB0_Pos (8U)
7719#define DSI_GHCR_WCLSB0_Msk (0x1UL << DSI_GHCR_WCLSB0_Pos)
7720#define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
7721#define DSI_GHCR_WCLSB1_Pos (9U)
7722#define DSI_GHCR_WCLSB1_Msk (0x1UL << DSI_GHCR_WCLSB1_Pos)
7723#define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
7724#define DSI_GHCR_WCLSB2_Pos (10U)
7725#define DSI_GHCR_WCLSB2_Msk (0x1UL << DSI_GHCR_WCLSB2_Pos)
7726#define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
7727#define DSI_GHCR_WCLSB3_Pos (11U)
7728#define DSI_GHCR_WCLSB3_Msk (0x1UL << DSI_GHCR_WCLSB3_Pos)
7729#define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
7730#define DSI_GHCR_WCLSB4_Pos (12U)
7731#define DSI_GHCR_WCLSB4_Msk (0x1UL << DSI_GHCR_WCLSB4_Pos)
7732#define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
7733#define DSI_GHCR_WCLSB5_Pos (13U)
7734#define DSI_GHCR_WCLSB5_Msk (0x1UL << DSI_GHCR_WCLSB5_Pos)
7735#define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
7736#define DSI_GHCR_WCLSB6_Pos (14U)
7737#define DSI_GHCR_WCLSB6_Msk (0x1UL << DSI_GHCR_WCLSB6_Pos)
7738#define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
7739#define DSI_GHCR_WCLSB7_Pos (15U)
7740#define DSI_GHCR_WCLSB7_Msk (0x1UL << DSI_GHCR_WCLSB7_Pos)
7741#define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
7742
7743#define DSI_GHCR_WCMSB_Pos (16U)
7744#define DSI_GHCR_WCMSB_Msk (0xFFUL << DSI_GHCR_WCMSB_Pos)
7745#define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk
7746#define DSI_GHCR_WCMSB0_Pos (16U)
7747#define DSI_GHCR_WCMSB0_Msk (0x1UL << DSI_GHCR_WCMSB0_Pos)
7748#define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
7749#define DSI_GHCR_WCMSB1_Pos (17U)
7750#define DSI_GHCR_WCMSB1_Msk (0x1UL << DSI_GHCR_WCMSB1_Pos)
7751#define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
7752#define DSI_GHCR_WCMSB2_Pos (18U)
7753#define DSI_GHCR_WCMSB2_Msk (0x1UL << DSI_GHCR_WCMSB2_Pos)
7754#define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
7755#define DSI_GHCR_WCMSB3_Pos (19U)
7756#define DSI_GHCR_WCMSB3_Msk (0x1UL << DSI_GHCR_WCMSB3_Pos)
7757#define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
7758#define DSI_GHCR_WCMSB4_Pos (20U)
7759#define DSI_GHCR_WCMSB4_Msk (0x1UL << DSI_GHCR_WCMSB4_Pos)
7760#define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
7761#define DSI_GHCR_WCMSB5_Pos (21U)
7762#define DSI_GHCR_WCMSB5_Msk (0x1UL << DSI_GHCR_WCMSB5_Pos)
7763#define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
7764#define DSI_GHCR_WCMSB6_Pos (22U)
7765#define DSI_GHCR_WCMSB6_Msk (0x1UL << DSI_GHCR_WCMSB6_Pos)
7766#define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
7767#define DSI_GHCR_WCMSB7_Pos (23U)
7768#define DSI_GHCR_WCMSB7_Msk (0x1UL << DSI_GHCR_WCMSB7_Pos)
7769#define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
7770
7771/******************* Bit definition for DSI_GPDR register ***************/
7772#define DSI_GPDR_DATA1_Pos (0U)
7773#define DSI_GPDR_DATA1_Msk (0xFFUL << DSI_GPDR_DATA1_Pos)
7774#define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk
7775#define DSI_GPDR_DATA1_0 (0x01UL << DSI_GPDR_DATA1_Pos)
7776#define DSI_GPDR_DATA1_1 (0x02UL << DSI_GPDR_DATA1_Pos)
7777#define DSI_GPDR_DATA1_2 (0x04UL << DSI_GPDR_DATA1_Pos)
7778#define DSI_GPDR_DATA1_3 (0x08UL << DSI_GPDR_DATA1_Pos)
7779#define DSI_GPDR_DATA1_4 (0x10UL << DSI_GPDR_DATA1_Pos)
7780#define DSI_GPDR_DATA1_5 (0x20UL << DSI_GPDR_DATA1_Pos)
7781#define DSI_GPDR_DATA1_6 (0x40UL << DSI_GPDR_DATA1_Pos)
7782#define DSI_GPDR_DATA1_7 (0x80UL << DSI_GPDR_DATA1_Pos)
7784#define DSI_GPDR_DATA2_Pos (8U)
7785#define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos)
7786#define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk
7787#define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos)
7788#define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos)
7789#define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos)
7790#define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos)
7791#define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos)
7792#define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos)
7793#define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos)
7794#define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos)
7796#define DSI_GPDR_DATA3_Pos (16U)
7797#define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos)
7798#define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk
7799#define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos)
7800#define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos)
7801#define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos)
7802#define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos)
7803#define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos)
7804#define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos)
7805#define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos)
7806#define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos)
7808#define DSI_GPDR_DATA4_Pos (24U)
7809#define DSI_GPDR_DATA4_Msk (0xFFUL << DSI_GPDR_DATA4_Pos)
7810#define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk
7811#define DSI_GPDR_DATA4_0 (0x01UL << DSI_GPDR_DATA4_Pos)
7812#define DSI_GPDR_DATA4_1 (0x02UL << DSI_GPDR_DATA4_Pos)
7813#define DSI_GPDR_DATA4_2 (0x04UL << DSI_GPDR_DATA4_Pos)
7814#define DSI_GPDR_DATA4_3 (0x08UL << DSI_GPDR_DATA4_Pos)
7815#define DSI_GPDR_DATA4_4 (0x10UL << DSI_GPDR_DATA4_Pos)
7816#define DSI_GPDR_DATA4_5 (0x20UL << DSI_GPDR_DATA4_Pos)
7817#define DSI_GPDR_DATA4_6 (0x40UL << DSI_GPDR_DATA4_Pos)
7818#define DSI_GPDR_DATA4_7 (0x80UL << DSI_GPDR_DATA4_Pos)
7820/******************* Bit definition for DSI_GPSR register ***************/
7821#define DSI_GPSR_CMDFE_Pos (0U)
7822#define DSI_GPSR_CMDFE_Msk (0x1UL << DSI_GPSR_CMDFE_Pos)
7823#define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk
7824#define DSI_GPSR_CMDFF_Pos (1U)
7825#define DSI_GPSR_CMDFF_Msk (0x1UL << DSI_GPSR_CMDFF_Pos)
7826#define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk
7827#define DSI_GPSR_PWRFE_Pos (2U)
7828#define DSI_GPSR_PWRFE_Msk (0x1UL << DSI_GPSR_PWRFE_Pos)
7829#define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk
7830#define DSI_GPSR_PWRFF_Pos (3U)
7831#define DSI_GPSR_PWRFF_Msk (0x1UL << DSI_GPSR_PWRFF_Pos)
7832#define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk
7833#define DSI_GPSR_PRDFE_Pos (4U)
7834#define DSI_GPSR_PRDFE_Msk (0x1UL << DSI_GPSR_PRDFE_Pos)
7835#define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk
7836#define DSI_GPSR_PRDFF_Pos (5U)
7837#define DSI_GPSR_PRDFF_Msk (0x1UL << DSI_GPSR_PRDFF_Pos)
7838#define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk
7839#define DSI_GPSR_RCB_Pos (6U)
7840#define DSI_GPSR_RCB_Msk (0x1UL << DSI_GPSR_RCB_Pos)
7841#define DSI_GPSR_RCB DSI_GPSR_RCB_Msk
7843/******************* Bit definition for DSI_TCCR0 register **************/
7844#define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
7845#define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos)
7846#define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk
7847#define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
7848#define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos)
7849#define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
7850#define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
7851#define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos)
7852#define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
7853#define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
7854#define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos)
7855#define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
7856#define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
7857#define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos)
7858#define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
7859#define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
7860#define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos)
7861#define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
7862#define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
7863#define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos)
7864#define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
7865#define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
7866#define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos)
7867#define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
7868#define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
7869#define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos)
7870#define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
7871#define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
7872#define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos)
7873#define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
7874#define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
7875#define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos)
7876#define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
7877#define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
7878#define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos)
7879#define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
7880#define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
7881#define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos)
7882#define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
7883#define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
7884#define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos)
7885#define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
7886#define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
7887#define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos)
7888#define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
7889#define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
7890#define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos)
7891#define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
7892#define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
7893#define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos)
7894#define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
7895
7896#define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
7897#define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos)
7898#define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk
7899#define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
7900#define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos)
7901#define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
7902#define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
7903#define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos)
7904#define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
7905#define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
7906#define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos)
7907#define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
7908#define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
7909#define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos)
7910#define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
7911#define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
7912#define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos)
7913#define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
7914#define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
7915#define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos)
7916#define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
7917#define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
7918#define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos)
7919#define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
7920#define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
7921#define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos)
7922#define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
7923#define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
7924#define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos)
7925#define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
7926#define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
7927#define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos)
7928#define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
7929#define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
7930#define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos)
7931#define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
7932#define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
7933#define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos)
7934#define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
7935#define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
7936#define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos)
7937#define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
7938#define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
7939#define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos)
7940#define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
7941#define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
7942#define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos)
7943#define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
7944#define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
7945#define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos)
7946#define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
7947
7948/******************* Bit definition for DSI_TCCR1 register **************/
7949#define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
7950#define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos)
7951#define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk
7952#define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
7953#define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos)
7954#define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
7955#define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
7956#define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos)
7957#define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
7958#define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
7959#define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos)
7960#define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
7961#define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
7962#define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos)
7963#define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
7964#define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
7965#define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos)
7966#define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
7967#define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
7968#define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos)
7969#define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
7970#define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
7971#define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos)
7972#define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
7973#define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
7974#define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos)
7975#define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
7976#define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
7977#define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos)
7978#define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
7979#define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
7980#define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos)
7981#define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
7982#define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
7983#define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos)
7984#define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
7985#define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
7986#define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos)
7987#define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
7988#define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
7989#define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos)
7990#define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
7991#define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
7992#define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos)
7993#define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
7994#define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
7995#define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos)
7996#define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
7997#define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
7998#define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos)
7999#define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
8000
8001/******************* Bit definition for DSI_TCCR2 register **************/
8002#define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
8003#define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos)
8004#define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk
8005#define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
8006#define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos)
8007#define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
8008#define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
8009#define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos)
8010#define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
8011#define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
8012#define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos)
8013#define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
8014#define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
8015#define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos)
8016#define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
8017#define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
8018#define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos)
8019#define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
8020#define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
8021#define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos)
8022#define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
8023#define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
8024#define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos)
8025#define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
8026#define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
8027#define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos)
8028#define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
8029#define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
8030#define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos)
8031#define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
8032#define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
8033#define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos)
8034#define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
8035#define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
8036#define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos)
8037#define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
8038#define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
8039#define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos)
8040#define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
8041#define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
8042#define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos)
8043#define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
8044#define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
8045#define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos)
8046#define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
8047#define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
8048#define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos)
8049#define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
8050#define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
8051#define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos)
8052#define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
8053
8054/******************* Bit definition for DSI_TCCR3 register **************/
8055#define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
8056#define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos)
8057#define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk
8058#define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
8059#define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos)
8060#define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
8061#define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
8062#define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos)
8063#define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
8064#define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
8065#define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos)
8066#define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
8067#define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
8068#define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos)
8069#define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
8070#define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
8071#define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos)
8072#define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
8073#define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
8074#define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos)
8075#define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
8076#define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
8077#define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos)
8078#define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
8079#define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
8080#define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos)
8081#define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
8082#define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
8083#define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos)
8084#define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
8085#define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
8086#define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos)
8087#define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
8088#define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
8089#define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos)
8090#define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
8091#define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
8092#define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos)
8093#define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
8094#define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
8095#define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos)
8096#define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
8097#define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
8098#define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos)
8099#define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
8100#define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
8101#define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos)
8102#define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
8103#define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
8104#define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos)
8105#define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
8106
8107#define DSI_TCCR3_PM_Pos (24U)
8108#define DSI_TCCR3_PM_Msk (0x1UL << DSI_TCCR3_PM_Pos)
8109#define DSI_TCCR3_PM DSI_TCCR3_PM_Msk
8111/******************* Bit definition for DSI_TCCR4 register **************/
8112#define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
8113#define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos)
8114#define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk
8115#define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
8116#define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos)
8117#define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
8118#define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
8119#define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos)
8120#define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
8121#define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
8122#define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos)
8123#define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
8124#define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
8125#define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos)
8126#define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
8127#define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
8128#define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos)
8129#define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
8130#define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
8131#define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos)
8132#define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
8133#define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
8134#define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos)
8135#define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
8136#define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
8137#define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos)
8138#define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
8139#define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
8140#define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos)
8141#define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
8142#define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
8143#define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos)
8144#define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
8145#define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
8146#define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos)
8147#define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
8148#define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
8149#define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos)
8150#define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
8151#define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
8152#define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos)
8153#define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
8154#define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
8155#define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos)
8156#define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
8157#define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
8158#define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos)
8159#define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
8160#define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
8161#define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos)
8162#define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
8163
8164/******************* Bit definition for DSI_TCCR5 register **************/
8165#define DSI_TCCR5_BTA_TOCNT_Pos (0U)
8166#define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos)
8167#define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk
8168#define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
8169#define DSI_TCCR5_BTA_TOCNT0_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos)
8170#define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
8171#define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
8172#define DSI_TCCR5_BTA_TOCNT1_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos)
8173#define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
8174#define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
8175#define DSI_TCCR5_BTA_TOCNT2_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos)
8176#define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
8177#define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
8178#define DSI_TCCR5_BTA_TOCNT3_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos)
8179#define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
8180#define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
8181#define DSI_TCCR5_BTA_TOCNT4_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos)
8182#define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
8183#define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
8184#define DSI_TCCR5_BTA_TOCNT5_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos)
8185#define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
8186#define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
8187#define DSI_TCCR5_BTA_TOCNT6_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos)
8188#define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
8189#define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
8190#define DSI_TCCR5_BTA_TOCNT7_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos)
8191#define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
8192#define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
8193#define DSI_TCCR5_BTA_TOCNT8_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos)
8194#define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
8195#define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
8196#define DSI_TCCR5_BTA_TOCNT9_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos)
8197#define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
8198#define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
8199#define DSI_TCCR5_BTA_TOCNT10_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos)
8200#define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
8201#define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
8202#define DSI_TCCR5_BTA_TOCNT11_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos)
8203#define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
8204#define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
8205#define DSI_TCCR5_BTA_TOCNT12_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos)
8206#define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
8207#define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
8208#define DSI_TCCR5_BTA_TOCNT13_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos)
8209#define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
8210#define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
8211#define DSI_TCCR5_BTA_TOCNT14_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos)
8212#define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
8213#define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
8214#define DSI_TCCR5_BTA_TOCNT15_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos)
8215#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
8216
8217/******************* Bit definition for DSI_TDCR register ***************/
8218#define DSI_TDCR_3DM 0x00000003U
8219#define DSI_TDCR_3DM0 0x00000001U
8220#define DSI_TDCR_3DM1 0x00000002U
8221
8222#define DSI_TDCR_3DF 0x0000000CU
8223#define DSI_TDCR_3DF0 0x00000004U
8224#define DSI_TDCR_3DF1 0x00000008U
8225
8226#define DSI_TDCR_SVS_Pos (4U)
8227#define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos)
8228#define DSI_TDCR_SVS DSI_TDCR_SVS_Msk
8229#define DSI_TDCR_RF_Pos (5U)
8230#define DSI_TDCR_RF_Msk (0x1UL << DSI_TDCR_RF_Pos)
8231#define DSI_TDCR_RF DSI_TDCR_RF_Msk
8232#define DSI_TDCR_S3DC_Pos (16U)
8233#define DSI_TDCR_S3DC_Msk (0x1UL << DSI_TDCR_S3DC_Pos)
8234#define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk
8236/******************* Bit definition for DSI_CLCR register ***************/
8237#define DSI_CLCR_DPCC_Pos (0U)
8238#define DSI_CLCR_DPCC_Msk (0x1UL << DSI_CLCR_DPCC_Pos)
8239#define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk
8240#define DSI_CLCR_ACR_Pos (1U)
8241#define DSI_CLCR_ACR_Msk (0x1UL << DSI_CLCR_ACR_Pos)
8242#define DSI_CLCR_ACR DSI_CLCR_ACR_Msk
8244/******************* Bit definition for DSI_CLTCR register **************/
8245#define DSI_CLTCR_LP2HS_TIME_Pos (0U)
8246#define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos)
8247#define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk
8248#define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
8249#define DSI_CLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos)
8250#define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
8251#define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
8252#define DSI_CLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos)
8253#define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
8254#define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
8255#define DSI_CLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos)
8256#define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
8257#define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
8258#define DSI_CLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos)
8259#define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
8260#define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
8261#define DSI_CLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos)
8262#define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
8263#define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
8264#define DSI_CLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos)
8265#define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
8266#define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
8267#define DSI_CLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos)
8268#define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
8269#define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
8270#define DSI_CLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos)
8271#define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
8272#define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
8273#define DSI_CLTCR_LP2HS_TIME8_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos)
8274#define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
8275#define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
8276#define DSI_CLTCR_LP2HS_TIME9_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos)
8277#define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
8278
8279#define DSI_CLTCR_HS2LP_TIME_Pos (16U)
8280#define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos)
8281#define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk
8282#define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
8283#define DSI_CLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos)
8284#define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
8285#define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
8286#define DSI_CLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos)
8287#define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
8288#define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
8289#define DSI_CLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos)
8290#define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
8291#define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
8292#define DSI_CLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos)
8293#define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
8294#define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
8295#define DSI_CLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos)
8296#define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
8297#define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
8298#define DSI_CLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos)
8299#define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
8300#define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
8301#define DSI_CLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos)
8302#define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
8303#define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
8304#define DSI_CLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos)
8305#define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
8306#define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
8307#define DSI_CLTCR_HS2LP_TIME8_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos)
8308#define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
8309#define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
8310#define DSI_CLTCR_HS2LP_TIME9_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos)
8311#define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
8312
8313/******************* Bit definition for DSI_DLTCR register **************/
8314#define DSI_DLTCR_MRD_TIME_Pos (0U)
8315#define DSI_DLTCR_MRD_TIME_Msk (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos)
8316#define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk
8317#define DSI_DLTCR_MRD_TIME0_Pos (0U)
8318#define DSI_DLTCR_MRD_TIME0_Msk (0x1UL << DSI_DLTCR_MRD_TIME0_Pos)
8319#define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
8320#define DSI_DLTCR_MRD_TIME1_Pos (1U)
8321#define DSI_DLTCR_MRD_TIME1_Msk (0x1UL << DSI_DLTCR_MRD_TIME1_Pos)
8322#define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
8323#define DSI_DLTCR_MRD_TIME2_Pos (2U)
8324#define DSI_DLTCR_MRD_TIME2_Msk (0x1UL << DSI_DLTCR_MRD_TIME2_Pos)
8325#define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
8326#define DSI_DLTCR_MRD_TIME3_Pos (3U)
8327#define DSI_DLTCR_MRD_TIME3_Msk (0x1UL << DSI_DLTCR_MRD_TIME3_Pos)
8328#define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
8329#define DSI_DLTCR_MRD_TIME4_Pos (4U)
8330#define DSI_DLTCR_MRD_TIME4_Msk (0x1UL << DSI_DLTCR_MRD_TIME4_Pos)
8331#define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
8332#define DSI_DLTCR_MRD_TIME5_Pos (5U)
8333#define DSI_DLTCR_MRD_TIME5_Msk (0x1UL << DSI_DLTCR_MRD_TIME5_Pos)
8334#define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
8335#define DSI_DLTCR_MRD_TIME6_Pos (6U)
8336#define DSI_DLTCR_MRD_TIME6_Msk (0x1UL << DSI_DLTCR_MRD_TIME6_Pos)
8337#define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
8338#define DSI_DLTCR_MRD_TIME7_Pos (7U)
8339#define DSI_DLTCR_MRD_TIME7_Msk (0x1UL << DSI_DLTCR_MRD_TIME7_Pos)
8340#define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
8341#define DSI_DLTCR_MRD_TIME8_Pos (8U)
8342#define DSI_DLTCR_MRD_TIME8_Msk (0x1UL << DSI_DLTCR_MRD_TIME8_Pos)
8343#define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
8344#define DSI_DLTCR_MRD_TIME9_Pos (9U)
8345#define DSI_DLTCR_MRD_TIME9_Msk (0x1UL << DSI_DLTCR_MRD_TIME9_Pos)
8346#define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
8347#define DSI_DLTCR_MRD_TIME10_Pos (10U)
8348#define DSI_DLTCR_MRD_TIME10_Msk (0x1UL << DSI_DLTCR_MRD_TIME10_Pos)
8349#define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
8350#define DSI_DLTCR_MRD_TIME11_Pos (11U)
8351#define DSI_DLTCR_MRD_TIME11_Msk (0x1UL << DSI_DLTCR_MRD_TIME11_Pos)
8352#define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
8353#define DSI_DLTCR_MRD_TIME12_Pos (12U)
8354#define DSI_DLTCR_MRD_TIME12_Msk (0x1UL << DSI_DLTCR_MRD_TIME12_Pos)
8355#define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
8356#define DSI_DLTCR_MRD_TIME13_Pos (13U)
8357#define DSI_DLTCR_MRD_TIME13_Msk (0x1UL << DSI_DLTCR_MRD_TIME13_Pos)
8358#define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
8359#define DSI_DLTCR_MRD_TIME14_Pos (14U)
8360#define DSI_DLTCR_MRD_TIME14_Msk (0x1UL << DSI_DLTCR_MRD_TIME14_Pos)
8361#define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
8362
8363#define DSI_DLTCR_LP2HS_TIME_Pos (16U)
8364#define DSI_DLTCR_LP2HS_TIME_Msk (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos)
8365#define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk
8366#define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
8367#define DSI_DLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos)
8368#define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
8369#define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
8370#define DSI_DLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos)
8371#define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
8372#define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
8373#define DSI_DLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos)
8374#define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
8375#define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
8376#define DSI_DLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos)
8377#define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
8378#define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
8379#define DSI_DLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos)
8380#define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
8381#define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
8382#define DSI_DLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos)
8383#define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
8384#define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
8385#define DSI_DLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos)
8386#define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
8387#define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
8388#define DSI_DLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos)
8389#define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
8390
8391#define DSI_DLTCR_HS2LP_TIME_Pos (24U)
8392#define DSI_DLTCR_HS2LP_TIME_Msk (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos)
8393#define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk
8394#define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
8395#define DSI_DLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos)
8396#define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
8397#define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
8398#define DSI_DLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos)
8399#define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
8400#define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
8401#define DSI_DLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos)
8402#define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
8403#define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
8404#define DSI_DLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos)
8405#define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
8406#define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
8407#define DSI_DLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos)
8408#define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
8409#define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
8410#define DSI_DLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos)
8411#define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
8412#define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
8413#define DSI_DLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos)
8414#define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
8415#define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
8416#define DSI_DLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos)
8417#define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
8418
8419/******************* Bit definition for DSI_PCTLR register **************/
8420#define DSI_PCTLR_DEN_Pos (1U)
8421#define DSI_PCTLR_DEN_Msk (0x1UL << DSI_PCTLR_DEN_Pos)
8422#define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk
8423#define DSI_PCTLR_CKE_Pos (2U)
8424#define DSI_PCTLR_CKE_Msk (0x1UL << DSI_PCTLR_CKE_Pos)
8425#define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk
8427/******************* Bit definition for DSI_PCONFR register *************/
8428#define DSI_PCONFR_NL_Pos (0U)
8429#define DSI_PCONFR_NL_Msk (0x3UL << DSI_PCONFR_NL_Pos)
8430#define DSI_PCONFR_NL DSI_PCONFR_NL_Msk
8431#define DSI_PCONFR_NL0_Pos (0U)
8432#define DSI_PCONFR_NL0_Msk (0x1UL << DSI_PCONFR_NL0_Pos)
8433#define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
8434#define DSI_PCONFR_NL1_Pos (1U)
8435#define DSI_PCONFR_NL1_Msk (0x1UL << DSI_PCONFR_NL1_Pos)
8436#define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
8437
8438#define DSI_PCONFR_SW_TIME_Pos (8U)
8439#define DSI_PCONFR_SW_TIME_Msk (0xFFUL << DSI_PCONFR_SW_TIME_Pos)
8440#define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk
8441#define DSI_PCONFR_SW_TIME0_Pos (8U)
8442#define DSI_PCONFR_SW_TIME0_Msk (0x1UL << DSI_PCONFR_SW_TIME0_Pos)
8443#define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
8444#define DSI_PCONFR_SW_TIME1_Pos (9U)
8445#define DSI_PCONFR_SW_TIME1_Msk (0x1UL << DSI_PCONFR_SW_TIME1_Pos)
8446#define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
8447#define DSI_PCONFR_SW_TIME2_Pos (10U)
8448#define DSI_PCONFR_SW_TIME2_Msk (0x1UL << DSI_PCONFR_SW_TIME2_Pos)
8449#define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
8450#define DSI_PCONFR_SW_TIME3_Pos (11U)
8451#define DSI_PCONFR_SW_TIME3_Msk (0x1UL << DSI_PCONFR_SW_TIME3_Pos)
8452#define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
8453#define DSI_PCONFR_SW_TIME4_Pos (12U)
8454#define DSI_PCONFR_SW_TIME4_Msk (0x1UL << DSI_PCONFR_SW_TIME4_Pos)
8455#define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
8456#define DSI_PCONFR_SW_TIME5_Pos (13U)
8457#define DSI_PCONFR_SW_TIME5_Msk (0x1UL << DSI_PCONFR_SW_TIME5_Pos)
8458#define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
8459#define DSI_PCONFR_SW_TIME6_Pos (14U)
8460#define DSI_PCONFR_SW_TIME6_Msk (0x1UL << DSI_PCONFR_SW_TIME6_Pos)
8461#define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
8462#define DSI_PCONFR_SW_TIME7_Pos (15U)
8463#define DSI_PCONFR_SW_TIME7_Msk (0x1UL << DSI_PCONFR_SW_TIME7_Pos)
8464#define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
8465
8466/******************* Bit definition for DSI_PUCR register ***************/
8467#define DSI_PUCR_URCL_Pos (0U)
8468#define DSI_PUCR_URCL_Msk (0x1UL << DSI_PUCR_URCL_Pos)
8469#define DSI_PUCR_URCL DSI_PUCR_URCL_Msk
8470#define DSI_PUCR_UECL_Pos (1U)
8471#define DSI_PUCR_UECL_Msk (0x1UL << DSI_PUCR_UECL_Pos)
8472#define DSI_PUCR_UECL DSI_PUCR_UECL_Msk
8473#define DSI_PUCR_URDL_Pos (2U)
8474#define DSI_PUCR_URDL_Msk (0x1UL << DSI_PUCR_URDL_Pos)
8475#define DSI_PUCR_URDL DSI_PUCR_URDL_Msk
8476#define DSI_PUCR_UEDL_Pos (3U)
8477#define DSI_PUCR_UEDL_Msk (0x1UL << DSI_PUCR_UEDL_Pos)
8478#define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk
8480/******************* Bit definition for DSI_PTTCR register **************/
8481#define DSI_PTTCR_TX_TRIG_Pos (0U)
8482#define DSI_PTTCR_TX_TRIG_Msk (0xFUL << DSI_PTTCR_TX_TRIG_Pos)
8483#define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk
8484#define DSI_PTTCR_TX_TRIG0_Pos (0U)
8485#define DSI_PTTCR_TX_TRIG0_Msk (0x1UL << DSI_PTTCR_TX_TRIG0_Pos)
8486#define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
8487#define DSI_PTTCR_TX_TRIG1_Pos (1U)
8488#define DSI_PTTCR_TX_TRIG1_Msk (0x1UL << DSI_PTTCR_TX_TRIG1_Pos)
8489#define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
8490#define DSI_PTTCR_TX_TRIG2_Pos (2U)
8491#define DSI_PTTCR_TX_TRIG2_Msk (0x1UL << DSI_PTTCR_TX_TRIG2_Pos)
8492#define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
8493#define DSI_PTTCR_TX_TRIG3_Pos (3U)
8494#define DSI_PTTCR_TX_TRIG3_Msk (0x1UL << DSI_PTTCR_TX_TRIG3_Pos)
8495#define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
8496
8497/******************* Bit definition for DSI_PSR register ****************/
8498#define DSI_PSR_PD_Pos (1U)
8499#define DSI_PSR_PD_Msk (0x1UL << DSI_PSR_PD_Pos)
8500#define DSI_PSR_PD DSI_PSR_PD_Msk
8501#define DSI_PSR_PSSC_Pos (2U)
8502#define DSI_PSR_PSSC_Msk (0x1UL << DSI_PSR_PSSC_Pos)
8503#define DSI_PSR_PSSC DSI_PSR_PSSC_Msk
8504#define DSI_PSR_UANC_Pos (3U)
8505#define DSI_PSR_UANC_Msk (0x1UL << DSI_PSR_UANC_Pos)
8506#define DSI_PSR_UANC DSI_PSR_UANC_Msk
8507#define DSI_PSR_PSS0_Pos (4U)
8508#define DSI_PSR_PSS0_Msk (0x1UL << DSI_PSR_PSS0_Pos)
8509#define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk
8510#define DSI_PSR_UAN0_Pos (5U)
8511#define DSI_PSR_UAN0_Msk (0x1UL << DSI_PSR_UAN0_Pos)
8512#define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk
8513#define DSI_PSR_RUE0_Pos (6U)
8514#define DSI_PSR_RUE0_Msk (0x1UL << DSI_PSR_RUE0_Pos)
8515#define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk
8516#define DSI_PSR_PSS1_Pos (7U)
8517#define DSI_PSR_PSS1_Msk (0x1UL << DSI_PSR_PSS1_Pos)
8518#define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk
8519#define DSI_PSR_UAN1_Pos (8U)
8520#define DSI_PSR_UAN1_Msk (0x1UL << DSI_PSR_UAN1_Pos)
8521#define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk
8523/******************* Bit definition for DSI_ISR0 register ***************/
8524#define DSI_ISR0_AE0_Pos (0U)
8525#define DSI_ISR0_AE0_Msk (0x1UL << DSI_ISR0_AE0_Pos)
8526#define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk
8527#define DSI_ISR0_AE1_Pos (1U)
8528#define DSI_ISR0_AE1_Msk (0x1UL << DSI_ISR0_AE1_Pos)
8529#define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk
8530#define DSI_ISR0_AE2_Pos (2U)
8531#define DSI_ISR0_AE2_Msk (0x1UL << DSI_ISR0_AE2_Pos)
8532#define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk
8533#define DSI_ISR0_AE3_Pos (3U)
8534#define DSI_ISR0_AE3_Msk (0x1UL << DSI_ISR0_AE3_Pos)
8535#define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk
8536#define DSI_ISR0_AE4_Pos (4U)
8537#define DSI_ISR0_AE4_Msk (0x1UL << DSI_ISR0_AE4_Pos)
8538#define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk
8539#define DSI_ISR0_AE5_Pos (5U)
8540#define DSI_ISR0_AE5_Msk (0x1UL << DSI_ISR0_AE5_Pos)
8541#define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk
8542#define DSI_ISR0_AE6_Pos (6U)
8543#define DSI_ISR0_AE6_Msk (0x1UL << DSI_ISR0_AE6_Pos)
8544#define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk
8545#define DSI_ISR0_AE7_Pos (7U)
8546#define DSI_ISR0_AE7_Msk (0x1UL << DSI_ISR0_AE7_Pos)
8547#define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk
8548#define DSI_ISR0_AE8_Pos (8U)
8549#define DSI_ISR0_AE8_Msk (0x1UL << DSI_ISR0_AE8_Pos)
8550#define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk
8551#define DSI_ISR0_AE9_Pos (9U)
8552#define DSI_ISR0_AE9_Msk (0x1UL << DSI_ISR0_AE9_Pos)
8553#define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk
8554#define DSI_ISR0_AE10_Pos (10U)
8555#define DSI_ISR0_AE10_Msk (0x1UL << DSI_ISR0_AE10_Pos)
8556#define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk
8557#define DSI_ISR0_AE11_Pos (11U)
8558#define DSI_ISR0_AE11_Msk (0x1UL << DSI_ISR0_AE11_Pos)
8559#define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk
8560#define DSI_ISR0_AE12_Pos (12U)
8561#define DSI_ISR0_AE12_Msk (0x1UL << DSI_ISR0_AE12_Pos)
8562#define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk
8563#define DSI_ISR0_AE13_Pos (13U)
8564#define DSI_ISR0_AE13_Msk (0x1UL << DSI_ISR0_AE13_Pos)
8565#define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk
8566#define DSI_ISR0_AE14_Pos (14U)
8567#define DSI_ISR0_AE14_Msk (0x1UL << DSI_ISR0_AE14_Pos)
8568#define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk
8569#define DSI_ISR0_AE15_Pos (15U)
8570#define DSI_ISR0_AE15_Msk (0x1UL << DSI_ISR0_AE15_Pos)
8571#define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk
8572#define DSI_ISR0_PE0_Pos (16U)
8573#define DSI_ISR0_PE0_Msk (0x1UL << DSI_ISR0_PE0_Pos)
8574#define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk
8575#define DSI_ISR0_PE1_Pos (17U)
8576#define DSI_ISR0_PE1_Msk (0x1UL << DSI_ISR0_PE1_Pos)
8577#define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk
8578#define DSI_ISR0_PE2_Pos (18U)
8579#define DSI_ISR0_PE2_Msk (0x1UL << DSI_ISR0_PE2_Pos)
8580#define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk
8581#define DSI_ISR0_PE3_Pos (19U)
8582#define DSI_ISR0_PE3_Msk (0x1UL << DSI_ISR0_PE3_Pos)
8583#define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk
8584#define DSI_ISR0_PE4_Pos (20U)
8585#define DSI_ISR0_PE4_Msk (0x1UL << DSI_ISR0_PE4_Pos)
8586#define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk
8588/******************* Bit definition for DSI_ISR1 register ***************/
8589#define DSI_ISR1_TOHSTX_Pos (0U)
8590#define DSI_ISR1_TOHSTX_Msk (0x1UL << DSI_ISR1_TOHSTX_Pos)
8591#define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk
8592#define DSI_ISR1_TOLPRX_Pos (1U)
8593#define DSI_ISR1_TOLPRX_Msk (0x1UL << DSI_ISR1_TOLPRX_Pos)
8594#define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk
8595#define DSI_ISR1_ECCSE_Pos (2U)
8596#define DSI_ISR1_ECCSE_Msk (0x1UL << DSI_ISR1_ECCSE_Pos)
8597#define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk
8598#define DSI_ISR1_ECCME_Pos (3U)
8599#define DSI_ISR1_ECCME_Msk (0x1UL << DSI_ISR1_ECCME_Pos)
8600#define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk
8601#define DSI_ISR1_CRCE_Pos (4U)
8602#define DSI_ISR1_CRCE_Msk (0x1UL << DSI_ISR1_CRCE_Pos)
8603#define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk
8604#define DSI_ISR1_PSE_Pos (5U)
8605#define DSI_ISR1_PSE_Msk (0x1UL << DSI_ISR1_PSE_Pos)
8606#define DSI_ISR1_PSE DSI_ISR1_PSE_Msk
8607#define DSI_ISR1_EOTPE_Pos (6U)
8608#define DSI_ISR1_EOTPE_Msk (0x1UL << DSI_ISR1_EOTPE_Pos)
8609#define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk
8610#define DSI_ISR1_LPWRE_Pos (7U)
8611#define DSI_ISR1_LPWRE_Msk (0x1UL << DSI_ISR1_LPWRE_Pos)
8612#define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk
8613#define DSI_ISR1_GCWRE_Pos (8U)
8614#define DSI_ISR1_GCWRE_Msk (0x1UL << DSI_ISR1_GCWRE_Pos)
8615#define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk
8616#define DSI_ISR1_GPWRE_Pos (9U)
8617#define DSI_ISR1_GPWRE_Msk (0x1UL << DSI_ISR1_GPWRE_Pos)
8618#define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk
8619#define DSI_ISR1_GPTXE_Pos (10U)
8620#define DSI_ISR1_GPTXE_Msk (0x1UL << DSI_ISR1_GPTXE_Pos)
8621#define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk
8622#define DSI_ISR1_GPRDE_Pos (11U)
8623#define DSI_ISR1_GPRDE_Msk (0x1UL << DSI_ISR1_GPRDE_Pos)
8624#define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk
8625#define DSI_ISR1_GPRXE_Pos (12U)
8626#define DSI_ISR1_GPRXE_Msk (0x1UL << DSI_ISR1_GPRXE_Pos)
8627#define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk
8629/******************* Bit definition for DSI_IER0 register ***************/
8630#define DSI_IER0_AE0IE_Pos (0U)
8631#define DSI_IER0_AE0IE_Msk (0x1UL << DSI_IER0_AE0IE_Pos)
8632#define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk
8633#define DSI_IER0_AE1IE_Pos (1U)
8634#define DSI_IER0_AE1IE_Msk (0x1UL << DSI_IER0_AE1IE_Pos)
8635#define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk
8636#define DSI_IER0_AE2IE_Pos (2U)
8637#define DSI_IER0_AE2IE_Msk (0x1UL << DSI_IER0_AE2IE_Pos)
8638#define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk
8639#define DSI_IER0_AE3IE_Pos (3U)
8640#define DSI_IER0_AE3IE_Msk (0x1UL << DSI_IER0_AE3IE_Pos)
8641#define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk
8642#define DSI_IER0_AE4IE_Pos (4U)
8643#define DSI_IER0_AE4IE_Msk (0x1UL << DSI_IER0_AE4IE_Pos)
8644#define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk
8645#define DSI_IER0_AE5IE_Pos (5U)
8646#define DSI_IER0_AE5IE_Msk (0x1UL << DSI_IER0_AE5IE_Pos)
8647#define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk
8648#define DSI_IER0_AE6IE_Pos (6U)
8649#define DSI_IER0_AE6IE_Msk (0x1UL << DSI_IER0_AE6IE_Pos)
8650#define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk
8651#define DSI_IER0_AE7IE_Pos (7U)
8652#define DSI_IER0_AE7IE_Msk (0x1UL << DSI_IER0_AE7IE_Pos)
8653#define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk
8654#define DSI_IER0_AE8IE_Pos (8U)
8655#define DSI_IER0_AE8IE_Msk (0x1UL << DSI_IER0_AE8IE_Pos)
8656#define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk
8657#define DSI_IER0_AE9IE_Pos (9U)
8658#define DSI_IER0_AE9IE_Msk (0x1UL << DSI_IER0_AE9IE_Pos)
8659#define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk
8660#define DSI_IER0_AE10IE_Pos (10U)
8661#define DSI_IER0_AE10IE_Msk (0x1UL << DSI_IER0_AE10IE_Pos)
8662#define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk
8663#define DSI_IER0_AE11IE_Pos (11U)
8664#define DSI_IER0_AE11IE_Msk (0x1UL << DSI_IER0_AE11IE_Pos)
8665#define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk
8666#define DSI_IER0_AE12IE_Pos (12U)
8667#define DSI_IER0_AE12IE_Msk (0x1UL << DSI_IER0_AE12IE_Pos)
8668#define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk
8669#define DSI_IER0_AE13IE_Pos (13U)
8670#define DSI_IER0_AE13IE_Msk (0x1UL << DSI_IER0_AE13IE_Pos)
8671#define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk
8672#define DSI_IER0_AE14IE_Pos (14U)
8673#define DSI_IER0_AE14IE_Msk (0x1UL << DSI_IER0_AE14IE_Pos)
8674#define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk
8675#define DSI_IER0_AE15IE_Pos (15U)
8676#define DSI_IER0_AE15IE_Msk (0x1UL << DSI_IER0_AE15IE_Pos)
8677#define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk
8678#define DSI_IER0_PE0IE_Pos (16U)
8679#define DSI_IER0_PE0IE_Msk (0x1UL << DSI_IER0_PE0IE_Pos)
8680#define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk
8681#define DSI_IER0_PE1IE_Pos (17U)
8682#define DSI_IER0_PE1IE_Msk (0x1UL << DSI_IER0_PE1IE_Pos)
8683#define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk
8684#define DSI_IER0_PE2IE_Pos (18U)
8685#define DSI_IER0_PE2IE_Msk (0x1UL << DSI_IER0_PE2IE_Pos)
8686#define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk
8687#define DSI_IER0_PE3IE_Pos (19U)
8688#define DSI_IER0_PE3IE_Msk (0x1UL << DSI_IER0_PE3IE_Pos)
8689#define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk
8690#define DSI_IER0_PE4IE_Pos (20U)
8691#define DSI_IER0_PE4IE_Msk (0x1UL << DSI_IER0_PE4IE_Pos)
8692#define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk
8694/******************* Bit definition for DSI_IER1 register ***************/
8695#define DSI_IER1_TOHSTXIE_Pos (0U)
8696#define DSI_IER1_TOHSTXIE_Msk (0x1UL << DSI_IER1_TOHSTXIE_Pos)
8697#define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk
8698#define DSI_IER1_TOLPRXIE_Pos (1U)
8699#define DSI_IER1_TOLPRXIE_Msk (0x1UL << DSI_IER1_TOLPRXIE_Pos)
8700#define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk
8701#define DSI_IER1_ECCSEIE_Pos (2U)
8702#define DSI_IER1_ECCSEIE_Msk (0x1UL << DSI_IER1_ECCSEIE_Pos)
8703#define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk
8704#define DSI_IER1_ECCMEIE_Pos (3U)
8705#define DSI_IER1_ECCMEIE_Msk (0x1UL << DSI_IER1_ECCMEIE_Pos)
8706#define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk
8707#define DSI_IER1_CRCEIE_Pos (4U)
8708#define DSI_IER1_CRCEIE_Msk (0x1UL << DSI_IER1_CRCEIE_Pos)
8709#define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk
8710#define DSI_IER1_PSEIE_Pos (5U)
8711#define DSI_IER1_PSEIE_Msk (0x1UL << DSI_IER1_PSEIE_Pos)
8712#define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk
8713#define DSI_IER1_EOTPEIE_Pos (6U)
8714#define DSI_IER1_EOTPEIE_Msk (0x1UL << DSI_IER1_EOTPEIE_Pos)
8715#define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk
8716#define DSI_IER1_LPWREIE_Pos (7U)
8717#define DSI_IER1_LPWREIE_Msk (0x1UL << DSI_IER1_LPWREIE_Pos)
8718#define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk
8719#define DSI_IER1_GCWREIE_Pos (8U)
8720#define DSI_IER1_GCWREIE_Msk (0x1UL << DSI_IER1_GCWREIE_Pos)
8721#define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk
8722#define DSI_IER1_GPWREIE_Pos (9U)
8723#define DSI_IER1_GPWREIE_Msk (0x1UL << DSI_IER1_GPWREIE_Pos)
8724#define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk
8725#define DSI_IER1_GPTXEIE_Pos (10U)
8726#define DSI_IER1_GPTXEIE_Msk (0x1UL << DSI_IER1_GPTXEIE_Pos)
8727#define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk
8728#define DSI_IER1_GPRDEIE_Pos (11U)
8729#define DSI_IER1_GPRDEIE_Msk (0x1UL << DSI_IER1_GPRDEIE_Pos)
8730#define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk
8731#define DSI_IER1_GPRXEIE_Pos (12U)
8732#define DSI_IER1_GPRXEIE_Msk (0x1UL << DSI_IER1_GPRXEIE_Pos)
8733#define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk
8735/******************* Bit definition for DSI_FIR0 register ***************/
8736#define DSI_FIR0_FAE0_Pos (0U)
8737#define DSI_FIR0_FAE0_Msk (0x1UL << DSI_FIR0_FAE0_Pos)
8738#define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk
8739#define DSI_FIR0_FAE1_Pos (1U)
8740#define DSI_FIR0_FAE1_Msk (0x1UL << DSI_FIR0_FAE1_Pos)
8741#define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk
8742#define DSI_FIR0_FAE2_Pos (2U)
8743#define DSI_FIR0_FAE2_Msk (0x1UL << DSI_FIR0_FAE2_Pos)
8744#define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk
8745#define DSI_FIR0_FAE3_Pos (3U)
8746#define DSI_FIR0_FAE3_Msk (0x1UL << DSI_FIR0_FAE3_Pos)
8747#define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk
8748#define DSI_FIR0_FAE4_Pos (4U)
8749#define DSI_FIR0_FAE4_Msk (0x1UL << DSI_FIR0_FAE4_Pos)
8750#define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk
8751#define DSI_FIR0_FAE5_Pos (5U)
8752#define DSI_FIR0_FAE5_Msk (0x1UL << DSI_FIR0_FAE5_Pos)
8753#define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk
8754#define DSI_FIR0_FAE6_Pos (6U)
8755#define DSI_FIR0_FAE6_Msk (0x1UL << DSI_FIR0_FAE6_Pos)
8756#define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk
8757#define DSI_FIR0_FAE7_Pos (7U)
8758#define DSI_FIR0_FAE7_Msk (0x1UL << DSI_FIR0_FAE7_Pos)
8759#define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk
8760#define DSI_FIR0_FAE8_Pos (8U)
8761#define DSI_FIR0_FAE8_Msk (0x1UL << DSI_FIR0_FAE8_Pos)
8762#define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk
8763#define DSI_FIR0_FAE9_Pos (9U)
8764#define DSI_FIR0_FAE9_Msk (0x1UL << DSI_FIR0_FAE9_Pos)
8765#define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk
8766#define DSI_FIR0_FAE10_Pos (10U)
8767#define DSI_FIR0_FAE10_Msk (0x1UL << DSI_FIR0_FAE10_Pos)
8768#define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk
8769#define DSI_FIR0_FAE11_Pos (11U)
8770#define DSI_FIR0_FAE11_Msk (0x1UL << DSI_FIR0_FAE11_Pos)
8771#define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk
8772#define DSI_FIR0_FAE12_Pos (12U)
8773#define DSI_FIR0_FAE12_Msk (0x1UL << DSI_FIR0_FAE12_Pos)
8774#define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk
8775#define DSI_FIR0_FAE13_Pos (13U)
8776#define DSI_FIR0_FAE13_Msk (0x1UL << DSI_FIR0_FAE13_Pos)
8777#define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk
8778#define DSI_FIR0_FAE14_Pos (14U)
8779#define DSI_FIR0_FAE14_Msk (0x1UL << DSI_FIR0_FAE14_Pos)
8780#define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk
8781#define DSI_FIR0_FAE15_Pos (15U)
8782#define DSI_FIR0_FAE15_Msk (0x1UL << DSI_FIR0_FAE15_Pos)
8783#define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk
8784#define DSI_FIR0_FPE0_Pos (16U)
8785#define DSI_FIR0_FPE0_Msk (0x1UL << DSI_FIR0_FPE0_Pos)
8786#define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk
8787#define DSI_FIR0_FPE1_Pos (17U)
8788#define DSI_FIR0_FPE1_Msk (0x1UL << DSI_FIR0_FPE1_Pos)
8789#define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk
8790#define DSI_FIR0_FPE2_Pos (18U)
8791#define DSI_FIR0_FPE2_Msk (0x1UL << DSI_FIR0_FPE2_Pos)
8792#define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk
8793#define DSI_FIR0_FPE3_Pos (19U)
8794#define DSI_FIR0_FPE3_Msk (0x1UL << DSI_FIR0_FPE3_Pos)
8795#define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk
8796#define DSI_FIR0_FPE4_Pos (20U)
8797#define DSI_FIR0_FPE4_Msk (0x1UL << DSI_FIR0_FPE4_Pos)
8798#define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk
8800/******************* Bit definition for DSI_FIR1 register ***************/
8801#define DSI_FIR1_FTOHSTX_Pos (0U)
8802#define DSI_FIR1_FTOHSTX_Msk (0x1UL << DSI_FIR1_FTOHSTX_Pos)
8803#define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk
8804#define DSI_FIR1_FTOLPRX_Pos (1U)
8805#define DSI_FIR1_FTOLPRX_Msk (0x1UL << DSI_FIR1_FTOLPRX_Pos)
8806#define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk
8807#define DSI_FIR1_FECCSE_Pos (2U)
8808#define DSI_FIR1_FECCSE_Msk (0x1UL << DSI_FIR1_FECCSE_Pos)
8809#define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk
8810#define DSI_FIR1_FECCME_Pos (3U)
8811#define DSI_FIR1_FECCME_Msk (0x1UL << DSI_FIR1_FECCME_Pos)
8812#define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk
8813#define DSI_FIR1_FCRCE_Pos (4U)
8814#define DSI_FIR1_FCRCE_Msk (0x1UL << DSI_FIR1_FCRCE_Pos)
8815#define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk
8816#define DSI_FIR1_FPSE_Pos (5U)
8817#define DSI_FIR1_FPSE_Msk (0x1UL << DSI_FIR1_FPSE_Pos)
8818#define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk
8819#define DSI_FIR1_FEOTPE_Pos (6U)
8820#define DSI_FIR1_FEOTPE_Msk (0x1UL << DSI_FIR1_FEOTPE_Pos)
8821#define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk
8822#define DSI_FIR1_FLPWRE_Pos (7U)
8823#define DSI_FIR1_FLPWRE_Msk (0x1UL << DSI_FIR1_FLPWRE_Pos)
8824#define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk
8825#define DSI_FIR1_FGCWRE_Pos (8U)
8826#define DSI_FIR1_FGCWRE_Msk (0x1UL << DSI_FIR1_FGCWRE_Pos)
8827#define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk
8828#define DSI_FIR1_FGPWRE_Pos (9U)
8829#define DSI_FIR1_FGPWRE_Msk (0x1UL << DSI_FIR1_FGPWRE_Pos)
8830#define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk
8831#define DSI_FIR1_FGPTXE_Pos (10U)
8832#define DSI_FIR1_FGPTXE_Msk (0x1UL << DSI_FIR1_FGPTXE_Pos)
8833#define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk
8834#define DSI_FIR1_FGPRDE_Pos (11U)
8835#define DSI_FIR1_FGPRDE_Msk (0x1UL << DSI_FIR1_FGPRDE_Pos)
8836#define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk
8837#define DSI_FIR1_FGPRXE_Pos (12U)
8838#define DSI_FIR1_FGPRXE_Msk (0x1UL << DSI_FIR1_FGPRXE_Pos)
8839#define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk
8841/******************* Bit definition for DSI_VSCR register ***************/
8842#define DSI_VSCR_EN_Pos (0U)
8843#define DSI_VSCR_EN_Msk (0x1UL << DSI_VSCR_EN_Pos)
8844#define DSI_VSCR_EN DSI_VSCR_EN_Msk
8845#define DSI_VSCR_UR_Pos (8U)
8846#define DSI_VSCR_UR_Msk (0x1UL << DSI_VSCR_UR_Pos)
8847#define DSI_VSCR_UR DSI_VSCR_UR_Msk
8849/******************* Bit definition for DSI_LCVCIDR register ************/
8850#define DSI_LCVCIDR_VCID_Pos (0U)
8851#define DSI_LCVCIDR_VCID_Msk (0x3UL << DSI_LCVCIDR_VCID_Pos)
8852#define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk
8853#define DSI_LCVCIDR_VCID0_Pos (0U)
8854#define DSI_LCVCIDR_VCID0_Msk (0x1UL << DSI_LCVCIDR_VCID0_Pos)
8855#define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
8856#define DSI_LCVCIDR_VCID1_Pos (1U)
8857#define DSI_LCVCIDR_VCID1_Msk (0x1UL << DSI_LCVCIDR_VCID1_Pos)
8858#define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
8859
8860/******************* Bit definition for DSI_LCCCR register **************/
8861#define DSI_LCCCR_COLC_Pos (0U)
8862#define DSI_LCCCR_COLC_Msk (0xFUL << DSI_LCCCR_COLC_Pos)
8863#define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk
8864#define DSI_LCCCR_COLC0_Pos (0U)
8865#define DSI_LCCCR_COLC0_Msk (0x1UL << DSI_LCCCR_COLC0_Pos)
8866#define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
8867#define DSI_LCCCR_COLC1_Pos (1U)
8868#define DSI_LCCCR_COLC1_Msk (0x1UL << DSI_LCCCR_COLC1_Pos)
8869#define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
8870#define DSI_LCCCR_COLC2_Pos (2U)
8871#define DSI_LCCCR_COLC2_Msk (0x1UL << DSI_LCCCR_COLC2_Pos)
8872#define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
8873#define DSI_LCCCR_COLC3_Pos (3U)
8874#define DSI_LCCCR_COLC3_Msk (0x1UL << DSI_LCCCR_COLC3_Pos)
8875#define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
8876
8877#define DSI_LCCCR_LPE_Pos (8U)
8878#define DSI_LCCCR_LPE_Msk (0x1UL << DSI_LCCCR_LPE_Pos)
8879#define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk
8881/******************* Bit definition for DSI_LPMCCR register *************/
8882#define DSI_LPMCCR_VLPSIZE_Pos (0U)
8883#define DSI_LPMCCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos)
8884#define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk
8885#define DSI_LPMCCR_VLPSIZE0_Pos (0U)
8886#define DSI_LPMCCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos)
8887#define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
8888#define DSI_LPMCCR_VLPSIZE1_Pos (1U)
8889#define DSI_LPMCCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos)
8890#define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
8891#define DSI_LPMCCR_VLPSIZE2_Pos (2U)
8892#define DSI_LPMCCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos)
8893#define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
8894#define DSI_LPMCCR_VLPSIZE3_Pos (3U)
8895#define DSI_LPMCCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos)
8896#define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
8897#define DSI_LPMCCR_VLPSIZE4_Pos (4U)
8898#define DSI_LPMCCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos)
8899#define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
8900#define DSI_LPMCCR_VLPSIZE5_Pos (5U)
8901#define DSI_LPMCCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos)
8902#define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
8903#define DSI_LPMCCR_VLPSIZE6_Pos (6U)
8904#define DSI_LPMCCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos)
8905#define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
8906#define DSI_LPMCCR_VLPSIZE7_Pos (7U)
8907#define DSI_LPMCCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos)
8908#define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
8909
8910#define DSI_LPMCCR_LPSIZE_Pos (16U)
8911#define DSI_LPMCCR_LPSIZE_Msk (0xFFUL << DSI_LPMCCR_LPSIZE_Pos)
8912#define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk
8913#define DSI_LPMCCR_LPSIZE0_Pos (16U)
8914#define DSI_LPMCCR_LPSIZE0_Msk (0x1UL << DSI_LPMCCR_LPSIZE0_Pos)
8915#define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
8916#define DSI_LPMCCR_LPSIZE1_Pos (17U)
8917#define DSI_LPMCCR_LPSIZE1_Msk (0x1UL << DSI_LPMCCR_LPSIZE1_Pos)
8918#define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
8919#define DSI_LPMCCR_LPSIZE2_Pos (18U)
8920#define DSI_LPMCCR_LPSIZE2_Msk (0x1UL << DSI_LPMCCR_LPSIZE2_Pos)
8921#define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
8922#define DSI_LPMCCR_LPSIZE3_Pos (19U)
8923#define DSI_LPMCCR_LPSIZE3_Msk (0x1UL << DSI_LPMCCR_LPSIZE3_Pos)
8924#define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
8925#define DSI_LPMCCR_LPSIZE4_Pos (20U)
8926#define DSI_LPMCCR_LPSIZE4_Msk (0x1UL << DSI_LPMCCR_LPSIZE4_Pos)
8927#define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
8928#define DSI_LPMCCR_LPSIZE5_Pos (21U)
8929#define DSI_LPMCCR_LPSIZE5_Msk (0x1UL << DSI_LPMCCR_LPSIZE5_Pos)
8930#define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
8931#define DSI_LPMCCR_LPSIZE6_Pos (22U)
8932#define DSI_LPMCCR_LPSIZE6_Msk (0x1UL << DSI_LPMCCR_LPSIZE6_Pos)
8933#define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
8934#define DSI_LPMCCR_LPSIZE7_Pos (23U)
8935#define DSI_LPMCCR_LPSIZE7_Msk (0x1UL << DSI_LPMCCR_LPSIZE7_Pos)
8936#define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
8937
8938/******************* Bit definition for DSI_VMCCR register **************/
8939#define DSI_VMCCR_VMT_Pos (0U)
8940#define DSI_VMCCR_VMT_Msk (0x3UL << DSI_VMCCR_VMT_Pos)
8941#define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk
8942#define DSI_VMCCR_VMT0_Pos (0U)
8943#define DSI_VMCCR_VMT0_Msk (0x1UL << DSI_VMCCR_VMT0_Pos)
8944#define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
8945#define DSI_VMCCR_VMT1_Pos (1U)
8946#define DSI_VMCCR_VMT1_Msk (0x1UL << DSI_VMCCR_VMT1_Pos)
8947#define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
8948
8949#define DSI_VMCCR_LPVSAE_Pos (8U)
8950#define DSI_VMCCR_LPVSAE_Msk (0x1UL << DSI_VMCCR_LPVSAE_Pos)
8951#define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk
8952#define DSI_VMCCR_LPVBPE_Pos (9U)
8953#define DSI_VMCCR_LPVBPE_Msk (0x1UL << DSI_VMCCR_LPVBPE_Pos)
8954#define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk
8955#define DSI_VMCCR_LPVFPE_Pos (10U)
8956#define DSI_VMCCR_LPVFPE_Msk (0x1UL << DSI_VMCCR_LPVFPE_Pos)
8957#define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk
8958#define DSI_VMCCR_LPVAE_Pos (11U)
8959#define DSI_VMCCR_LPVAE_Msk (0x1UL << DSI_VMCCR_LPVAE_Pos)
8960#define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk
8961#define DSI_VMCCR_LPHBPE_Pos (12U)
8962#define DSI_VMCCR_LPHBPE_Msk (0x1UL << DSI_VMCCR_LPHBPE_Pos)
8963#define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk
8964#define DSI_VMCCR_LPHFE_Pos (13U)
8965#define DSI_VMCCR_LPHFE_Msk (0x1UL << DSI_VMCCR_LPHFE_Pos)
8966#define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk
8967#define DSI_VMCCR_FBTAAE_Pos (14U)
8968#define DSI_VMCCR_FBTAAE_Msk (0x1UL << DSI_VMCCR_FBTAAE_Pos)
8969#define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk
8970#define DSI_VMCCR_LPCE_Pos (15U)
8971#define DSI_VMCCR_LPCE_Msk (0x1UL << DSI_VMCCR_LPCE_Pos)
8972#define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk
8974/******************* Bit definition for DSI_VPCCR register **************/
8975#define DSI_VPCCR_VPSIZE_Pos (0U)
8976#define DSI_VPCCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos)
8977#define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk
8978#define DSI_VPCCR_VPSIZE0_Pos (0U)
8979#define DSI_VPCCR_VPSIZE0_Msk (0x1UL << DSI_VPCCR_VPSIZE0_Pos)
8980#define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
8981#define DSI_VPCCR_VPSIZE1_Pos (1U)
8982#define DSI_VPCCR_VPSIZE1_Msk (0x1UL << DSI_VPCCR_VPSIZE1_Pos)
8983#define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
8984#define DSI_VPCCR_VPSIZE2_Pos (2U)
8985#define DSI_VPCCR_VPSIZE2_Msk (0x1UL << DSI_VPCCR_VPSIZE2_Pos)
8986#define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
8987#define DSI_VPCCR_VPSIZE3_Pos (3U)
8988#define DSI_VPCCR_VPSIZE3_Msk (0x1UL << DSI_VPCCR_VPSIZE3_Pos)
8989#define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
8990#define DSI_VPCCR_VPSIZE4_Pos (4U)
8991#define DSI_VPCCR_VPSIZE4_Msk (0x1UL << DSI_VPCCR_VPSIZE4_Pos)
8992#define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
8993#define DSI_VPCCR_VPSIZE5_Pos (5U)
8994#define DSI_VPCCR_VPSIZE5_Msk (0x1UL << DSI_VPCCR_VPSIZE5_Pos)
8995#define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
8996#define DSI_VPCCR_VPSIZE6_Pos (6U)
8997#define DSI_VPCCR_VPSIZE6_Msk (0x1UL << DSI_VPCCR_VPSIZE6_Pos)
8998#define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
8999#define DSI_VPCCR_VPSIZE7_Pos (7U)
9000#define DSI_VPCCR_VPSIZE7_Msk (0x1UL << DSI_VPCCR_VPSIZE7_Pos)
9001#define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
9002#define DSI_VPCCR_VPSIZE8_Pos (8U)
9003#define DSI_VPCCR_VPSIZE8_Msk (0x1UL << DSI_VPCCR_VPSIZE8_Pos)
9004#define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
9005#define DSI_VPCCR_VPSIZE9_Pos (9U)
9006#define DSI_VPCCR_VPSIZE9_Msk (0x1UL << DSI_VPCCR_VPSIZE9_Pos)
9007#define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
9008#define DSI_VPCCR_VPSIZE10_Pos (10U)
9009#define DSI_VPCCR_VPSIZE10_Msk (0x1UL << DSI_VPCCR_VPSIZE10_Pos)
9010#define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
9011#define DSI_VPCCR_VPSIZE11_Pos (11U)
9012#define DSI_VPCCR_VPSIZE11_Msk (0x1UL << DSI_VPCCR_VPSIZE11_Pos)
9013#define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
9014#define DSI_VPCCR_VPSIZE12_Pos (12U)
9015#define DSI_VPCCR_VPSIZE12_Msk (0x1UL << DSI_VPCCR_VPSIZE12_Pos)
9016#define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
9017#define DSI_VPCCR_VPSIZE13_Pos (13U)
9018#define DSI_VPCCR_VPSIZE13_Msk (0x1UL << DSI_VPCCR_VPSIZE13_Pos)
9019#define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
9020
9021/******************* Bit definition for DSI_VCCCR register **************/
9022#define DSI_VCCCR_NUMC_Pos (0U)
9023#define DSI_VCCCR_NUMC_Msk (0x1FFFUL << DSI_VCCCR_NUMC_Pos)
9024#define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk
9025#define DSI_VCCCR_NUMC0_Pos (0U)
9026#define DSI_VCCCR_NUMC0_Msk (0x1UL << DSI_VCCCR_NUMC0_Pos)
9027#define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
9028#define DSI_VCCCR_NUMC1_Pos (1U)
9029#define DSI_VCCCR_NUMC1_Msk (0x1UL << DSI_VCCCR_NUMC1_Pos)
9030#define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
9031#define DSI_VCCCR_NUMC2_Pos (2U)
9032#define DSI_VCCCR_NUMC2_Msk (0x1UL << DSI_VCCCR_NUMC2_Pos)
9033#define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
9034#define DSI_VCCCR_NUMC3_Pos (3U)
9035#define DSI_VCCCR_NUMC3_Msk (0x1UL << DSI_VCCCR_NUMC3_Pos)
9036#define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
9037#define DSI_VCCCR_NUMC4_Pos (4U)
9038#define DSI_VCCCR_NUMC4_Msk (0x1UL << DSI_VCCCR_NUMC4_Pos)
9039#define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
9040#define DSI_VCCCR_NUMC5_Pos (5U)
9041#define DSI_VCCCR_NUMC5_Msk (0x1UL << DSI_VCCCR_NUMC5_Pos)
9042#define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
9043#define DSI_VCCCR_NUMC6_Pos (6U)
9044#define DSI_VCCCR_NUMC6_Msk (0x1UL << DSI_VCCCR_NUMC6_Pos)
9045#define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
9046#define DSI_VCCCR_NUMC7_Pos (7U)
9047#define DSI_VCCCR_NUMC7_Msk (0x1UL << DSI_VCCCR_NUMC7_Pos)
9048#define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
9049#define DSI_VCCCR_NUMC8_Pos (8U)
9050#define DSI_VCCCR_NUMC8_Msk (0x1UL << DSI_VCCCR_NUMC8_Pos)
9051#define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
9052#define DSI_VCCCR_NUMC9_Pos (9U)
9053#define DSI_VCCCR_NUMC9_Msk (0x1UL << DSI_VCCCR_NUMC9_Pos)
9054#define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
9055#define DSI_VCCCR_NUMC10_Pos (10U)
9056#define DSI_VCCCR_NUMC10_Msk (0x1UL << DSI_VCCCR_NUMC10_Pos)
9057#define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
9058#define DSI_VCCCR_NUMC11_Pos (11U)
9059#define DSI_VCCCR_NUMC11_Msk (0x1UL << DSI_VCCCR_NUMC11_Pos)
9060#define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
9061#define DSI_VCCCR_NUMC12_Pos (12U)
9062#define DSI_VCCCR_NUMC12_Msk (0x1UL << DSI_VCCCR_NUMC12_Pos)
9063#define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
9064
9065/******************* Bit definition for DSI_VNPCCR register *************/
9066#define DSI_VNPCCR_NPSIZE_Pos (0U)
9067#define DSI_VNPCCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos)
9068#define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk
9069#define DSI_VNPCCR_NPSIZE0_Pos (0U)
9070#define DSI_VNPCCR_NPSIZE0_Msk (0x1UL << DSI_VNPCCR_NPSIZE0_Pos)
9071#define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
9072#define DSI_VNPCCR_NPSIZE1_Pos (1U)
9073#define DSI_VNPCCR_NPSIZE1_Msk (0x1UL << DSI_VNPCCR_NPSIZE1_Pos)
9074#define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
9075#define DSI_VNPCCR_NPSIZE2_Pos (2U)
9076#define DSI_VNPCCR_NPSIZE2_Msk (0x1UL << DSI_VNPCCR_NPSIZE2_Pos)
9077#define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
9078#define DSI_VNPCCR_NPSIZE3_Pos (3U)
9079#define DSI_VNPCCR_NPSIZE3_Msk (0x1UL << DSI_VNPCCR_NPSIZE3_Pos)
9080#define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
9081#define DSI_VNPCCR_NPSIZE4_Pos (4U)
9082#define DSI_VNPCCR_NPSIZE4_Msk (0x1UL << DSI_VNPCCR_NPSIZE4_Pos)
9083#define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
9084#define DSI_VNPCCR_NPSIZE5_Pos (5U)
9085#define DSI_VNPCCR_NPSIZE5_Msk (0x1UL << DSI_VNPCCR_NPSIZE5_Pos)
9086#define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
9087#define DSI_VNPCCR_NPSIZE6_Pos (6U)
9088#define DSI_VNPCCR_NPSIZE6_Msk (0x1UL << DSI_VNPCCR_NPSIZE6_Pos)
9089#define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
9090#define DSI_VNPCCR_NPSIZE7_Pos (7U)
9091#define DSI_VNPCCR_NPSIZE7_Msk (0x1UL << DSI_VNPCCR_NPSIZE7_Pos)
9092#define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
9093#define DSI_VNPCCR_NPSIZE8_Pos (8U)
9094#define DSI_VNPCCR_NPSIZE8_Msk (0x1UL << DSI_VNPCCR_NPSIZE8_Pos)
9095#define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
9096#define DSI_VNPCCR_NPSIZE9_Pos (9U)
9097#define DSI_VNPCCR_NPSIZE9_Msk (0x1UL << DSI_VNPCCR_NPSIZE9_Pos)
9098#define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
9099#define DSI_VNPCCR_NPSIZE10_Pos (10U)
9100#define DSI_VNPCCR_NPSIZE10_Msk (0x1UL << DSI_VNPCCR_NPSIZE10_Pos)
9101#define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
9102#define DSI_VNPCCR_NPSIZE11_Pos (11U)
9103#define DSI_VNPCCR_NPSIZE11_Msk (0x1UL << DSI_VNPCCR_NPSIZE11_Pos)
9104#define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
9105#define DSI_VNPCCR_NPSIZE12_Pos (12U)
9106#define DSI_VNPCCR_NPSIZE12_Msk (0x1UL << DSI_VNPCCR_NPSIZE12_Pos)
9107#define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
9108
9109/******************* Bit definition for DSI_VHSACCR register ************/
9110#define DSI_VHSACCR_HSA_Pos (0U)
9111#define DSI_VHSACCR_HSA_Msk (0xFFFUL << DSI_VHSACCR_HSA_Pos)
9112#define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk
9113#define DSI_VHSACCR_HSA0_Pos (0U)
9114#define DSI_VHSACCR_HSA0_Msk (0x1UL << DSI_VHSACCR_HSA0_Pos)
9115#define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
9116#define DSI_VHSACCR_HSA1_Pos (1U)
9117#define DSI_VHSACCR_HSA1_Msk (0x1UL << DSI_VHSACCR_HSA1_Pos)
9118#define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
9119#define DSI_VHSACCR_HSA2_Pos (2U)
9120#define DSI_VHSACCR_HSA2_Msk (0x1UL << DSI_VHSACCR_HSA2_Pos)
9121#define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
9122#define DSI_VHSACCR_HSA3_Pos (3U)
9123#define DSI_VHSACCR_HSA3_Msk (0x1UL << DSI_VHSACCR_HSA3_Pos)
9124#define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
9125#define DSI_VHSACCR_HSA4_Pos (4U)
9126#define DSI_VHSACCR_HSA4_Msk (0x1UL << DSI_VHSACCR_HSA4_Pos)
9127#define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
9128#define DSI_VHSACCR_HSA5_Pos (5U)
9129#define DSI_VHSACCR_HSA5_Msk (0x1UL << DSI_VHSACCR_HSA5_Pos)
9130#define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
9131#define DSI_VHSACCR_HSA6_Pos (6U)
9132#define DSI_VHSACCR_HSA6_Msk (0x1UL << DSI_VHSACCR_HSA6_Pos)
9133#define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
9134#define DSI_VHSACCR_HSA7_Pos (7U)
9135#define DSI_VHSACCR_HSA7_Msk (0x1UL << DSI_VHSACCR_HSA7_Pos)
9136#define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
9137#define DSI_VHSACCR_HSA8_Pos (8U)
9138#define DSI_VHSACCR_HSA8_Msk (0x1UL << DSI_VHSACCR_HSA8_Pos)
9139#define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
9140#define DSI_VHSACCR_HSA9_Pos (9U)
9141#define DSI_VHSACCR_HSA9_Msk (0x1UL << DSI_VHSACCR_HSA9_Pos)
9142#define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
9143#define DSI_VHSACCR_HSA10_Pos (10U)
9144#define DSI_VHSACCR_HSA10_Msk (0x1UL << DSI_VHSACCR_HSA10_Pos)
9145#define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
9146#define DSI_VHSACCR_HSA11_Pos (11U)
9147#define DSI_VHSACCR_HSA11_Msk (0x1UL << DSI_VHSACCR_HSA11_Pos)
9148#define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
9149
9150/******************* Bit definition for DSI_VHBPCCR register ************/
9151#define DSI_VHBPCCR_HBP_Pos (0U)
9152#define DSI_VHBPCCR_HBP_Msk (0xFFFUL << DSI_VHBPCCR_HBP_Pos)
9153#define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk
9154#define DSI_VHBPCCR_HBP0_Pos (0U)
9155#define DSI_VHBPCCR_HBP0_Msk (0x1UL << DSI_VHBPCCR_HBP0_Pos)
9156#define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
9157#define DSI_VHBPCCR_HBP1_Pos (1U)
9158#define DSI_VHBPCCR_HBP1_Msk (0x1UL << DSI_VHBPCCR_HBP1_Pos)
9159#define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
9160#define DSI_VHBPCCR_HBP2_Pos (2U)
9161#define DSI_VHBPCCR_HBP2_Msk (0x1UL << DSI_VHBPCCR_HBP2_Pos)
9162#define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
9163#define DSI_VHBPCCR_HBP3_Pos (3U)
9164#define DSI_VHBPCCR_HBP3_Msk (0x1UL << DSI_VHBPCCR_HBP3_Pos)
9165#define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
9166#define DSI_VHBPCCR_HBP4_Pos (4U)
9167#define DSI_VHBPCCR_HBP4_Msk (0x1UL << DSI_VHBPCCR_HBP4_Pos)
9168#define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
9169#define DSI_VHBPCCR_HBP5_Pos (5U)
9170#define DSI_VHBPCCR_HBP5_Msk (0x1UL << DSI_VHBPCCR_HBP5_Pos)
9171#define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
9172#define DSI_VHBPCCR_HBP6_Pos (6U)
9173#define DSI_VHBPCCR_HBP6_Msk (0x1UL << DSI_VHBPCCR_HBP6_Pos)
9174#define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
9175#define DSI_VHBPCCR_HBP7_Pos (7U)
9176#define DSI_VHBPCCR_HBP7_Msk (0x1UL << DSI_VHBPCCR_HBP7_Pos)
9177#define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
9178#define DSI_VHBPCCR_HBP8_Pos (8U)
9179#define DSI_VHBPCCR_HBP8_Msk (0x1UL << DSI_VHBPCCR_HBP8_Pos)
9180#define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
9181#define DSI_VHBPCCR_HBP9_Pos (9U)
9182#define DSI_VHBPCCR_HBP9_Msk (0x1UL << DSI_VHBPCCR_HBP9_Pos)
9183#define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
9184#define DSI_VHBPCCR_HBP10_Pos (10U)
9185#define DSI_VHBPCCR_HBP10_Msk (0x1UL << DSI_VHBPCCR_HBP10_Pos)
9186#define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
9187#define DSI_VHBPCCR_HBP11_Pos (11U)
9188#define DSI_VHBPCCR_HBP11_Msk (0x1UL << DSI_VHBPCCR_HBP11_Pos)
9189#define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
9190
9191/******************* Bit definition for DSI_VLCCR register **************/
9192#define DSI_VLCCR_HLINE_Pos (0U)
9193#define DSI_VLCCR_HLINE_Msk (0x7FFFUL << DSI_VLCCR_HLINE_Pos)
9194#define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk
9195#define DSI_VLCCR_HLINE0_Pos (0U)
9196#define DSI_VLCCR_HLINE0_Msk (0x1UL << DSI_VLCCR_HLINE0_Pos)
9197#define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
9198#define DSI_VLCCR_HLINE1_Pos (1U)
9199#define DSI_VLCCR_HLINE1_Msk (0x1UL << DSI_VLCCR_HLINE1_Pos)
9200#define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
9201#define DSI_VLCCR_HLINE2_Pos (2U)
9202#define DSI_VLCCR_HLINE2_Msk (0x1UL << DSI_VLCCR_HLINE2_Pos)
9203#define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
9204#define DSI_VLCCR_HLINE3_Pos (3U)
9205#define DSI_VLCCR_HLINE3_Msk (0x1UL << DSI_VLCCR_HLINE3_Pos)
9206#define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
9207#define DSI_VLCCR_HLINE4_Pos (4U)
9208#define DSI_VLCCR_HLINE4_Msk (0x1UL << DSI_VLCCR_HLINE4_Pos)
9209#define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
9210#define DSI_VLCCR_HLINE5_Pos (5U)
9211#define DSI_VLCCR_HLINE5_Msk (0x1UL << DSI_VLCCR_HLINE5_Pos)
9212#define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
9213#define DSI_VLCCR_HLINE6_Pos (6U)
9214#define DSI_VLCCR_HLINE6_Msk (0x1UL << DSI_VLCCR_HLINE6_Pos)
9215#define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
9216#define DSI_VLCCR_HLINE7_Pos (7U)
9217#define DSI_VLCCR_HLINE7_Msk (0x1UL << DSI_VLCCR_HLINE7_Pos)
9218#define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
9219#define DSI_VLCCR_HLINE8_Pos (8U)
9220#define DSI_VLCCR_HLINE8_Msk (0x1UL << DSI_VLCCR_HLINE8_Pos)
9221#define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
9222#define DSI_VLCCR_HLINE9_Pos (9U)
9223#define DSI_VLCCR_HLINE9_Msk (0x1UL << DSI_VLCCR_HLINE9_Pos)
9224#define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
9225#define DSI_VLCCR_HLINE10_Pos (10U)
9226#define DSI_VLCCR_HLINE10_Msk (0x1UL << DSI_VLCCR_HLINE10_Pos)
9227#define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
9228#define DSI_VLCCR_HLINE11_Pos (11U)
9229#define DSI_VLCCR_HLINE11_Msk (0x1UL << DSI_VLCCR_HLINE11_Pos)
9230#define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
9231#define DSI_VLCCR_HLINE12_Pos (12U)
9232#define DSI_VLCCR_HLINE12_Msk (0x1UL << DSI_VLCCR_HLINE12_Pos)
9233#define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
9234#define DSI_VLCCR_HLINE13_Pos (13U)
9235#define DSI_VLCCR_HLINE13_Msk (0x1UL << DSI_VLCCR_HLINE13_Pos)
9236#define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
9237#define DSI_VLCCR_HLINE14_Pos (14U)
9238#define DSI_VLCCR_HLINE14_Msk (0x1UL << DSI_VLCCR_HLINE14_Pos)
9239#define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
9240
9241/******************* Bit definition for DSI_VVSACCR register ***************/
9242#define DSI_VVSACCR_VSA_Pos (0U)
9243#define DSI_VVSACCR_VSA_Msk (0x3FFUL << DSI_VVSACCR_VSA_Pos)
9244#define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk
9245#define DSI_VVSACCR_VSA0_Pos (0U)
9246#define DSI_VVSACCR_VSA0_Msk (0x1UL << DSI_VVSACCR_VSA0_Pos)
9247#define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
9248#define DSI_VVSACCR_VSA1_Pos (1U)
9249#define DSI_VVSACCR_VSA1_Msk (0x1UL << DSI_VVSACCR_VSA1_Pos)
9250#define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
9251#define DSI_VVSACCR_VSA2_Pos (2U)
9252#define DSI_VVSACCR_VSA2_Msk (0x1UL << DSI_VVSACCR_VSA2_Pos)
9253#define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
9254#define DSI_VVSACCR_VSA3_Pos (3U)
9255#define DSI_VVSACCR_VSA3_Msk (0x1UL << DSI_VVSACCR_VSA3_Pos)
9256#define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
9257#define DSI_VVSACCR_VSA4_Pos (4U)
9258#define DSI_VVSACCR_VSA4_Msk (0x1UL << DSI_VVSACCR_VSA4_Pos)
9259#define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
9260#define DSI_VVSACCR_VSA5_Pos (5U)
9261#define DSI_VVSACCR_VSA5_Msk (0x1UL << DSI_VVSACCR_VSA5_Pos)
9262#define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
9263#define DSI_VVSACCR_VSA6_Pos (6U)
9264#define DSI_VVSACCR_VSA6_Msk (0x1UL << DSI_VVSACCR_VSA6_Pos)
9265#define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
9266#define DSI_VVSACCR_VSA7_Pos (7U)
9267#define DSI_VVSACCR_VSA7_Msk (0x1UL << DSI_VVSACCR_VSA7_Pos)
9268#define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
9269#define DSI_VVSACCR_VSA8_Pos (8U)
9270#define DSI_VVSACCR_VSA8_Msk (0x1UL << DSI_VVSACCR_VSA8_Pos)
9271#define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
9272#define DSI_VVSACCR_VSA9_Pos (9U)
9273#define DSI_VVSACCR_VSA9_Msk (0x1UL << DSI_VVSACCR_VSA9_Pos)
9274#define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
9275
9276/******************* Bit definition for DSI_VVBPCCR register ************/
9277#define DSI_VVBPCCR_VBP_Pos (0U)
9278#define DSI_VVBPCCR_VBP_Msk (0x3FFUL << DSI_VVBPCCR_VBP_Pos)
9279#define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk
9280#define DSI_VVBPCCR_VBP0_Pos (0U)
9281#define DSI_VVBPCCR_VBP0_Msk (0x1UL << DSI_VVBPCCR_VBP0_Pos)
9282#define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
9283#define DSI_VVBPCCR_VBP1_Pos (1U)
9284#define DSI_VVBPCCR_VBP1_Msk (0x1UL << DSI_VVBPCCR_VBP1_Pos)
9285#define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
9286#define DSI_VVBPCCR_VBP2_Pos (2U)
9287#define DSI_VVBPCCR_VBP2_Msk (0x1UL << DSI_VVBPCCR_VBP2_Pos)
9288#define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
9289#define DSI_VVBPCCR_VBP3_Pos (3U)
9290#define DSI_VVBPCCR_VBP3_Msk (0x1UL << DSI_VVBPCCR_VBP3_Pos)
9291#define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
9292#define DSI_VVBPCCR_VBP4_Pos (4U)
9293#define DSI_VVBPCCR_VBP4_Msk (0x1UL << DSI_VVBPCCR_VBP4_Pos)
9294#define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
9295#define DSI_VVBPCCR_VBP5_Pos (5U)
9296#define DSI_VVBPCCR_VBP5_Msk (0x1UL << DSI_VVBPCCR_VBP5_Pos)
9297#define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
9298#define DSI_VVBPCCR_VBP6_Pos (6U)
9299#define DSI_VVBPCCR_VBP6_Msk (0x1UL << DSI_VVBPCCR_VBP6_Pos)
9300#define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
9301#define DSI_VVBPCCR_VBP7_Pos (7U)
9302#define DSI_VVBPCCR_VBP7_Msk (0x1UL << DSI_VVBPCCR_VBP7_Pos)
9303#define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
9304#define DSI_VVBPCCR_VBP8_Pos (8U)
9305#define DSI_VVBPCCR_VBP8_Msk (0x1UL << DSI_VVBPCCR_VBP8_Pos)
9306#define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
9307#define DSI_VVBPCCR_VBP9_Pos (9U)
9308#define DSI_VVBPCCR_VBP9_Msk (0x1UL << DSI_VVBPCCR_VBP9_Pos)
9309#define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
9310
9311/******************* Bit definition for DSI_VVFPCCR register ************/
9312#define DSI_VVFPCCR_VFP_Pos (0U)
9313#define DSI_VVFPCCR_VFP_Msk (0x3FFUL << DSI_VVFPCCR_VFP_Pos)
9314#define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk
9315#define DSI_VVFPCCR_VFP0_Pos (0U)
9316#define DSI_VVFPCCR_VFP0_Msk (0x1UL << DSI_VVFPCCR_VFP0_Pos)
9317#define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
9318#define DSI_VVFPCCR_VFP1_Pos (1U)
9319#define DSI_VVFPCCR_VFP1_Msk (0x1UL << DSI_VVFPCCR_VFP1_Pos)
9320#define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
9321#define DSI_VVFPCCR_VFP2_Pos (2U)
9322#define DSI_VVFPCCR_VFP2_Msk (0x1UL << DSI_VVFPCCR_VFP2_Pos)
9323#define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
9324#define DSI_VVFPCCR_VFP3_Pos (3U)
9325#define DSI_VVFPCCR_VFP3_Msk (0x1UL << DSI_VVFPCCR_VFP3_Pos)
9326#define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
9327#define DSI_VVFPCCR_VFP4_Pos (4U)
9328#define DSI_VVFPCCR_VFP4_Msk (0x1UL << DSI_VVFPCCR_VFP4_Pos)
9329#define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
9330#define DSI_VVFPCCR_VFP5_Pos (5U)
9331#define DSI_VVFPCCR_VFP5_Msk (0x1UL << DSI_VVFPCCR_VFP5_Pos)
9332#define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
9333#define DSI_VVFPCCR_VFP6_Pos (6U)
9334#define DSI_VVFPCCR_VFP6_Msk (0x1UL << DSI_VVFPCCR_VFP6_Pos)
9335#define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
9336#define DSI_VVFPCCR_VFP7_Pos (7U)
9337#define DSI_VVFPCCR_VFP7_Msk (0x1UL << DSI_VVFPCCR_VFP7_Pos)
9338#define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
9339#define DSI_VVFPCCR_VFP8_Pos (8U)
9340#define DSI_VVFPCCR_VFP8_Msk (0x1UL << DSI_VVFPCCR_VFP8_Pos)
9341#define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
9342#define DSI_VVFPCCR_VFP9_Pos (9U)
9343#define DSI_VVFPCCR_VFP9_Msk (0x1UL << DSI_VVFPCCR_VFP9_Pos)
9344#define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
9345
9346/******************* Bit definition for DSI_VVACCR register *************/
9347#define DSI_VVACCR_VA_Pos (0U)
9348#define DSI_VVACCR_VA_Msk (0x3FFFUL << DSI_VVACCR_VA_Pos)
9349#define DSI_VVACCR_VA DSI_VVACCR_VA_Msk
9350#define DSI_VVACCR_VA0_Pos (0U)
9351#define DSI_VVACCR_VA0_Msk (0x1UL << DSI_VVACCR_VA0_Pos)
9352#define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
9353#define DSI_VVACCR_VA1_Pos (1U)
9354#define DSI_VVACCR_VA1_Msk (0x1UL << DSI_VVACCR_VA1_Pos)
9355#define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
9356#define DSI_VVACCR_VA2_Pos (2U)
9357#define DSI_VVACCR_VA2_Msk (0x1UL << DSI_VVACCR_VA2_Pos)
9358#define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
9359#define DSI_VVACCR_VA3_Pos (3U)
9360#define DSI_VVACCR_VA3_Msk (0x1UL << DSI_VVACCR_VA3_Pos)
9361#define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
9362#define DSI_VVACCR_VA4_Pos (4U)
9363#define DSI_VVACCR_VA4_Msk (0x1UL << DSI_VVACCR_VA4_Pos)
9364#define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
9365#define DSI_VVACCR_VA5_Pos (5U)
9366#define DSI_VVACCR_VA5_Msk (0x1UL << DSI_VVACCR_VA5_Pos)
9367#define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
9368#define DSI_VVACCR_VA6_Pos (6U)
9369#define DSI_VVACCR_VA6_Msk (0x1UL << DSI_VVACCR_VA6_Pos)
9370#define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
9371#define DSI_VVACCR_VA7_Pos (7U)
9372#define DSI_VVACCR_VA7_Msk (0x1UL << DSI_VVACCR_VA7_Pos)
9373#define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
9374#define DSI_VVACCR_VA8_Pos (8U)
9375#define DSI_VVACCR_VA8_Msk (0x1UL << DSI_VVACCR_VA8_Pos)
9376#define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
9377#define DSI_VVACCR_VA9_Pos (9U)
9378#define DSI_VVACCR_VA9_Msk (0x1UL << DSI_VVACCR_VA9_Pos)
9379#define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
9380#define DSI_VVACCR_VA10_Pos (10U)
9381#define DSI_VVACCR_VA10_Msk (0x1UL << DSI_VVACCR_VA10_Pos)
9382#define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
9383#define DSI_VVACCR_VA11_Pos (11U)
9384#define DSI_VVACCR_VA11_Msk (0x1UL << DSI_VVACCR_VA11_Pos)
9385#define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
9386#define DSI_VVACCR_VA12_Pos (12U)
9387#define DSI_VVACCR_VA12_Msk (0x1UL << DSI_VVACCR_VA12_Pos)
9388#define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
9389#define DSI_VVACCR_VA13_Pos (13U)
9390#define DSI_VVACCR_VA13_Msk (0x1UL << DSI_VVACCR_VA13_Pos)
9391#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
9392
9393/******************* Bit definition for DSI_TDCCR register **************/
9394#define DSI_TDCCR_3DM 0x00000003U
9395#define DSI_TDCCR_3DM0 0x00000001U
9396#define DSI_TDCCR_3DM1 0x00000002U
9397
9398#define DSI_TDCCR_3DF 0x0000000CU
9399#define DSI_TDCCR_3DF0 0x00000004U
9400#define DSI_TDCCR_3DF1 0x00000008U
9401
9402#define DSI_TDCCR_SVS_Pos (4U)
9403#define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos)
9404#define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk
9405#define DSI_TDCCR_RF_Pos (5U)
9406#define DSI_TDCCR_RF_Msk (0x1UL << DSI_TDCCR_RF_Pos)
9407#define DSI_TDCCR_RF DSI_TDCCR_RF_Msk
9408#define DSI_TDCCR_S3DC_Pos (16U)
9409#define DSI_TDCCR_S3DC_Msk (0x1UL << DSI_TDCCR_S3DC_Pos)
9410#define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk
9412/******************* Bit definition for DSI_WCFGR register ***************/
9413#define DSI_WCFGR_DSIM_Pos (0U)
9414#define DSI_WCFGR_DSIM_Msk (0x1UL << DSI_WCFGR_DSIM_Pos)
9415#define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk
9416#define DSI_WCFGR_COLMUX_Pos (1U)
9417#define DSI_WCFGR_COLMUX_Msk (0x7UL << DSI_WCFGR_COLMUX_Pos)
9418#define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk
9419#define DSI_WCFGR_COLMUX0_Pos (1U)
9420#define DSI_WCFGR_COLMUX0_Msk (0x1UL << DSI_WCFGR_COLMUX0_Pos)
9421#define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
9422#define DSI_WCFGR_COLMUX1_Pos (2U)
9423#define DSI_WCFGR_COLMUX1_Msk (0x1UL << DSI_WCFGR_COLMUX1_Pos)
9424#define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
9425#define DSI_WCFGR_COLMUX2_Pos (3U)
9426#define DSI_WCFGR_COLMUX2_Msk (0x1UL << DSI_WCFGR_COLMUX2_Pos)
9427#define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
9428
9429#define DSI_WCFGR_TESRC_Pos (4U)
9430#define DSI_WCFGR_TESRC_Msk (0x1UL << DSI_WCFGR_TESRC_Pos)
9431#define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk
9432#define DSI_WCFGR_TEPOL_Pos (5U)
9433#define DSI_WCFGR_TEPOL_Msk (0x1UL << DSI_WCFGR_TEPOL_Pos)
9434#define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk
9435#define DSI_WCFGR_AR_Pos (6U)
9436#define DSI_WCFGR_AR_Msk (0x1UL << DSI_WCFGR_AR_Pos)
9437#define DSI_WCFGR_AR DSI_WCFGR_AR_Msk
9438#define DSI_WCFGR_VSPOL_Pos (7U)
9439#define DSI_WCFGR_VSPOL_Msk (0x1UL << DSI_WCFGR_VSPOL_Pos)
9440#define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk
9442/******************* Bit definition for DSI_WCR register *****************/
9443#define DSI_WCR_COLM_Pos (0U)
9444#define DSI_WCR_COLM_Msk (0x1UL << DSI_WCR_COLM_Pos)
9445#define DSI_WCR_COLM DSI_WCR_COLM_Msk
9446#define DSI_WCR_SHTDN_Pos (1U)
9447#define DSI_WCR_SHTDN_Msk (0x1UL << DSI_WCR_SHTDN_Pos)
9448#define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk
9449#define DSI_WCR_LTDCEN_Pos (2U)
9450#define DSI_WCR_LTDCEN_Msk (0x1UL << DSI_WCR_LTDCEN_Pos)
9451#define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk
9452#define DSI_WCR_DSIEN_Pos (3U)
9453#define DSI_WCR_DSIEN_Msk (0x1UL << DSI_WCR_DSIEN_Pos)
9454#define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk
9456/******************* Bit definition for DSI_WIER register ****************/
9457#define DSI_WIER_TEIE_Pos (0U)
9458#define DSI_WIER_TEIE_Msk (0x1UL << DSI_WIER_TEIE_Pos)
9459#define DSI_WIER_TEIE DSI_WIER_TEIE_Msk
9460#define DSI_WIER_ERIE_Pos (1U)
9461#define DSI_WIER_ERIE_Msk (0x1UL << DSI_WIER_ERIE_Pos)
9462#define DSI_WIER_ERIE DSI_WIER_ERIE_Msk
9463#define DSI_WIER_PLLLIE_Pos (9U)
9464#define DSI_WIER_PLLLIE_Msk (0x1UL << DSI_WIER_PLLLIE_Pos)
9465#define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk
9466#define DSI_WIER_PLLUIE_Pos (10U)
9467#define DSI_WIER_PLLUIE_Msk (0x1UL << DSI_WIER_PLLUIE_Pos)
9468#define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk
9469#define DSI_WIER_RRIE_Pos (13U)
9470#define DSI_WIER_RRIE_Msk (0x1UL << DSI_WIER_RRIE_Pos)
9471#define DSI_WIER_RRIE DSI_WIER_RRIE_Msk
9473/******************* Bit definition for DSI_WISR register ****************/
9474#define DSI_WISR_TEIF_Pos (0U)
9475#define DSI_WISR_TEIF_Msk (0x1UL << DSI_WISR_TEIF_Pos)
9476#define DSI_WISR_TEIF DSI_WISR_TEIF_Msk
9477#define DSI_WISR_ERIF_Pos (1U)
9478#define DSI_WISR_ERIF_Msk (0x1UL << DSI_WISR_ERIF_Pos)
9479#define DSI_WISR_ERIF DSI_WISR_ERIF_Msk
9480#define DSI_WISR_BUSY_Pos (2U)
9481#define DSI_WISR_BUSY_Msk (0x1UL << DSI_WISR_BUSY_Pos)
9482#define DSI_WISR_BUSY DSI_WISR_BUSY_Msk
9483#define DSI_WISR_PLLLS_Pos (8U)
9484#define DSI_WISR_PLLLS_Msk (0x1UL << DSI_WISR_PLLLS_Pos)
9485#define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk
9486#define DSI_WISR_PLLLIF_Pos (9U)
9487#define DSI_WISR_PLLLIF_Msk (0x1UL << DSI_WISR_PLLLIF_Pos)
9488#define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk
9489#define DSI_WISR_PLLUIF_Pos (10U)
9490#define DSI_WISR_PLLUIF_Msk (0x1UL << DSI_WISR_PLLUIF_Pos)
9491#define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk
9492#define DSI_WISR_RRS_Pos (12U)
9493#define DSI_WISR_RRS_Msk (0x1UL << DSI_WISR_RRS_Pos)
9494#define DSI_WISR_RRS DSI_WISR_RRS_Msk
9495#define DSI_WISR_RRIF_Pos (13U)
9496#define DSI_WISR_RRIF_Msk (0x1UL << DSI_WISR_RRIF_Pos)
9497#define DSI_WISR_RRIF DSI_WISR_RRIF_Msk
9499/******************* Bit definition for DSI_WIFCR register ***************/
9500#define DSI_WIFCR_CTEIF_Pos (0U)
9501#define DSI_WIFCR_CTEIF_Msk (0x1UL << DSI_WIFCR_CTEIF_Pos)
9502#define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk
9503#define DSI_WIFCR_CERIF_Pos (1U)
9504#define DSI_WIFCR_CERIF_Msk (0x1UL << DSI_WIFCR_CERIF_Pos)
9505#define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk
9506#define DSI_WIFCR_CPLLLIF_Pos (9U)
9507#define DSI_WIFCR_CPLLLIF_Msk (0x1UL << DSI_WIFCR_CPLLLIF_Pos)
9508#define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk
9509#define DSI_WIFCR_CPLLUIF_Pos (10U)
9510#define DSI_WIFCR_CPLLUIF_Msk (0x1UL << DSI_WIFCR_CPLLUIF_Pos)
9511#define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk
9512#define DSI_WIFCR_CRRIF_Pos (13U)
9513#define DSI_WIFCR_CRRIF_Msk (0x1UL << DSI_WIFCR_CRRIF_Pos)
9514#define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk
9516/******************* Bit definition for DSI_WPCR0 register ***************/
9517#define DSI_WPCR0_UIX4_Pos (0U)
9518#define DSI_WPCR0_UIX4_Msk (0x3FUL << DSI_WPCR0_UIX4_Pos)
9519#define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk
9520#define DSI_WPCR0_UIX4_0 (0x01UL << DSI_WPCR0_UIX4_Pos)
9521#define DSI_WPCR0_UIX4_1 (0x02UL << DSI_WPCR0_UIX4_Pos)
9522#define DSI_WPCR0_UIX4_2 (0x04UL << DSI_WPCR0_UIX4_Pos)
9523#define DSI_WPCR0_UIX4_3 (0x08UL << DSI_WPCR0_UIX4_Pos)
9524#define DSI_WPCR0_UIX4_4 (0x10UL << DSI_WPCR0_UIX4_Pos)
9525#define DSI_WPCR0_UIX4_5 (0x20UL << DSI_WPCR0_UIX4_Pos)
9527#define DSI_WPCR0_SWCL_Pos (6U)
9528#define DSI_WPCR0_SWCL_Msk (0x1UL << DSI_WPCR0_SWCL_Pos)
9529#define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk
9530#define DSI_WPCR0_SWDL0_Pos (7U)
9531#define DSI_WPCR0_SWDL0_Msk (0x1UL << DSI_WPCR0_SWDL0_Pos)
9532#define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk
9533#define DSI_WPCR0_SWDL1_Pos (8U)
9534#define DSI_WPCR0_SWDL1_Msk (0x1UL << DSI_WPCR0_SWDL1_Pos)
9535#define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk
9536#define DSI_WPCR0_HSICL_Pos (9U)
9537#define DSI_WPCR0_HSICL_Msk (0x1UL << DSI_WPCR0_HSICL_Pos)
9538#define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk
9539#define DSI_WPCR0_HSIDL0_Pos (10U)
9540#define DSI_WPCR0_HSIDL0_Msk (0x1UL << DSI_WPCR0_HSIDL0_Pos)
9541#define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk
9542#define DSI_WPCR0_HSIDL1_Pos (11U)
9543#define DSI_WPCR0_HSIDL1_Msk (0x1UL << DSI_WPCR0_HSIDL1_Pos)
9544#define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk
9545#define DSI_WPCR0_FTXSMCL_Pos (12U)
9546#define DSI_WPCR0_FTXSMCL_Msk (0x1UL << DSI_WPCR0_FTXSMCL_Pos)
9547#define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk
9548#define DSI_WPCR0_FTXSMDL_Pos (13U)
9549#define DSI_WPCR0_FTXSMDL_Msk (0x1UL << DSI_WPCR0_FTXSMDL_Pos)
9550#define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk
9551#define DSI_WPCR0_CDOFFDL_Pos (14U)
9552#define DSI_WPCR0_CDOFFDL_Msk (0x1UL << DSI_WPCR0_CDOFFDL_Pos)
9553#define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk
9554#define DSI_WPCR0_TDDL_Pos (16U)
9555#define DSI_WPCR0_TDDL_Msk (0x1UL << DSI_WPCR0_TDDL_Pos)
9556#define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk
9557#define DSI_WPCR0_PDEN_Pos (18U)
9558#define DSI_WPCR0_PDEN_Msk (0x1UL << DSI_WPCR0_PDEN_Pos)
9559#define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk
9560#define DSI_WPCR0_TCLKPREPEN_Pos (19U)
9561#define DSI_WPCR0_TCLKPREPEN_Msk (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos)
9562#define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk
9563#define DSI_WPCR0_TCLKZEROEN_Pos (20U)
9564#define DSI_WPCR0_TCLKZEROEN_Msk (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos)
9565#define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk
9566#define DSI_WPCR0_THSPREPEN_Pos (21U)
9567#define DSI_WPCR0_THSPREPEN_Msk (0x1UL << DSI_WPCR0_THSPREPEN_Pos)
9568#define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk
9569#define DSI_WPCR0_THSTRAILEN_Pos (22U)
9570#define DSI_WPCR0_THSTRAILEN_Msk (0x1UL << DSI_WPCR0_THSTRAILEN_Pos)
9571#define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk
9572#define DSI_WPCR0_THSZEROEN_Pos (23U)
9573#define DSI_WPCR0_THSZEROEN_Msk (0x1UL << DSI_WPCR0_THSZEROEN_Pos)
9574#define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk
9575#define DSI_WPCR0_TLPXDEN_Pos (24U)
9576#define DSI_WPCR0_TLPXDEN_Msk (0x1UL << DSI_WPCR0_TLPXDEN_Pos)
9577#define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk
9578#define DSI_WPCR0_THSEXITEN_Pos (25U)
9579#define DSI_WPCR0_THSEXITEN_Msk (0x1UL << DSI_WPCR0_THSEXITEN_Pos)
9580#define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk
9581#define DSI_WPCR0_TLPXCEN_Pos (26U)
9582#define DSI_WPCR0_TLPXCEN_Msk (0x1UL << DSI_WPCR0_TLPXCEN_Pos)
9583#define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk
9584#define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
9585#define DSI_WPCR0_TCLKPOSTEN_Msk (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos)
9586#define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk
9588/******************* Bit definition for DSI_WPCR1 register ***************/
9589#define DSI_WPCR1_HSTXDCL_Pos (0U)
9590#define DSI_WPCR1_HSTXDCL_Msk (0x3UL << DSI_WPCR1_HSTXDCL_Pos)
9591#define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk
9592#define DSI_WPCR1_HSTXDCL0_Pos (0U)
9593#define DSI_WPCR1_HSTXDCL0_Msk (0x1UL << DSI_WPCR1_HSTXDCL0_Pos)
9594#define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
9595#define DSI_WPCR1_HSTXDCL1_Pos (1U)
9596#define DSI_WPCR1_HSTXDCL1_Msk (0x1UL << DSI_WPCR1_HSTXDCL1_Pos)
9597#define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
9598
9599#define DSI_WPCR1_HSTXDDL_Pos (2U)
9600#define DSI_WPCR1_HSTXDDL_Msk (0x3UL << DSI_WPCR1_HSTXDDL_Pos)
9601#define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk
9602#define DSI_WPCR1_HSTXDDL0_Pos (2U)
9603#define DSI_WPCR1_HSTXDDL0_Msk (0x1UL << DSI_WPCR1_HSTXDDL0_Pos)
9604#define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
9605#define DSI_WPCR1_HSTXDDL1_Pos (3U)
9606#define DSI_WPCR1_HSTXDDL1_Msk (0x1UL << DSI_WPCR1_HSTXDDL1_Pos)
9607#define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
9608
9609#define DSI_WPCR1_LPSRCCL_Pos (6U)
9610#define DSI_WPCR1_LPSRCCL_Msk (0x3UL << DSI_WPCR1_LPSRCCL_Pos)
9611#define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk
9612#define DSI_WPCR1_LPSRCCL0_Pos (6U)
9613#define DSI_WPCR1_LPSRCCL0_Msk (0x1UL << DSI_WPCR1_LPSRCCL0_Pos)
9614#define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
9615#define DSI_WPCR1_LPSRCCL1_Pos (7U)
9616#define DSI_WPCR1_LPSRCCL1_Msk (0x1UL << DSI_WPCR1_LPSRCCL1_Pos)
9617#define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
9618
9619#define DSI_WPCR1_LPSRCDL_Pos (8U)
9620#define DSI_WPCR1_LPSRCDL_Msk (0x3UL << DSI_WPCR1_LPSRCDL_Pos)
9621#define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk
9622#define DSI_WPCR1_LPSRCDL0_Pos (8U)
9623#define DSI_WPCR1_LPSRCDL0_Msk (0x1UL << DSI_WPCR1_LPSRCDL0_Pos)
9624#define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
9625#define DSI_WPCR1_LPSRCDL1_Pos (9U)
9626#define DSI_WPCR1_LPSRCDL1_Msk (0x1UL << DSI_WPCR1_LPSRCDL1_Pos)
9627#define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
9628
9629#define DSI_WPCR1_SDDC_Pos (12U)
9630#define DSI_WPCR1_SDDC_Msk (0x1UL << DSI_WPCR1_SDDC_Pos)
9631#define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk
9633#define DSI_WPCR1_LPRXVCDL_Pos (14U)
9634#define DSI_WPCR1_LPRXVCDL_Msk (0x3UL << DSI_WPCR1_LPRXVCDL_Pos)
9635#define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk
9636#define DSI_WPCR1_LPRXVCDL0_Pos (14U)
9637#define DSI_WPCR1_LPRXVCDL0_Msk (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos)
9638#define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
9639#define DSI_WPCR1_LPRXVCDL1_Pos (15U)
9640#define DSI_WPCR1_LPRXVCDL1_Msk (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos)
9641#define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
9642
9643#define DSI_WPCR1_HSTXSRCCL_Pos (16U)
9644#define DSI_WPCR1_HSTXSRCCL_Msk (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos)
9645#define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk
9646#define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
9647#define DSI_WPCR1_HSTXSRCCL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos)
9648#define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
9649#define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
9650#define DSI_WPCR1_HSTXSRCCL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos)
9651#define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
9652
9653#define DSI_WPCR1_HSTXSRCDL_Pos (18U)
9654#define DSI_WPCR1_HSTXSRCDL_Msk (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos)
9655#define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk
9656#define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
9657#define DSI_WPCR1_HSTXSRCDL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos)
9658#define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
9659#define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
9660#define DSI_WPCR1_HSTXSRCDL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos)
9661#define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
9662
9663#define DSI_WPCR1_FLPRXLPM_Pos (22U)
9664#define DSI_WPCR1_FLPRXLPM_Msk (0x1UL << DSI_WPCR1_FLPRXLPM_Pos)
9665#define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk
9667#define DSI_WPCR1_LPRXFT_Pos (25U)
9668#define DSI_WPCR1_LPRXFT_Msk (0x3UL << DSI_WPCR1_LPRXFT_Pos)
9669#define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk
9670#define DSI_WPCR1_LPRXFT0_Pos (25U)
9671#define DSI_WPCR1_LPRXFT0_Msk (0x1UL << DSI_WPCR1_LPRXFT0_Pos)
9672#define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
9673#define DSI_WPCR1_LPRXFT1_Pos (26U)
9674#define DSI_WPCR1_LPRXFT1_Msk (0x1UL << DSI_WPCR1_LPRXFT1_Pos)
9675#define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
9676
9677/******************* Bit definition for DSI_WPCR2 register ***************/
9678#define DSI_WPCR2_TCLKPREP_Pos (0U)
9679#define DSI_WPCR2_TCLKPREP_Msk (0xFFUL << DSI_WPCR2_TCLKPREP_Pos)
9680#define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk
9681#define DSI_WPCR2_TCLKPREP0_Pos (0U)
9682#define DSI_WPCR2_TCLKPREP0_Msk (0x1UL << DSI_WPCR2_TCLKPREP0_Pos)
9683#define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
9684#define DSI_WPCR2_TCLKPREP1_Pos (1U)
9685#define DSI_WPCR2_TCLKPREP1_Msk (0x1UL << DSI_WPCR2_TCLKPREP1_Pos)
9686#define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
9687#define DSI_WPCR2_TCLKPREP2_Pos (2U)
9688#define DSI_WPCR2_TCLKPREP2_Msk (0x1UL << DSI_WPCR2_TCLKPREP2_Pos)
9689#define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
9690#define DSI_WPCR2_TCLKPREP3_Pos (3U)
9691#define DSI_WPCR2_TCLKPREP3_Msk (0x1UL << DSI_WPCR2_TCLKPREP3_Pos)
9692#define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
9693#define DSI_WPCR2_TCLKPREP4_Pos (4U)
9694#define DSI_WPCR2_TCLKPREP4_Msk (0x1UL << DSI_WPCR2_TCLKPREP4_Pos)
9695#define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
9696#define DSI_WPCR2_TCLKPREP5_Pos (5U)
9697#define DSI_WPCR2_TCLKPREP5_Msk (0x1UL << DSI_WPCR2_TCLKPREP5_Pos)
9698#define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
9699#define DSI_WPCR2_TCLKPREP6_Pos (6U)
9700#define DSI_WPCR2_TCLKPREP6_Msk (0x1UL << DSI_WPCR2_TCLKPREP6_Pos)
9701#define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
9702#define DSI_WPCR2_TCLKPREP7_Pos (7U)
9703#define DSI_WPCR2_TCLKPREP7_Msk (0x1UL << DSI_WPCR2_TCLKPREP7_Pos)
9704#define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
9705
9706#define DSI_WPCR2_TCLKZERO_Pos (8U)
9707#define DSI_WPCR2_TCLKZERO_Msk (0xFFUL << DSI_WPCR2_TCLKZERO_Pos)
9708#define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk
9709#define DSI_WPCR2_TCLKZERO0_Pos (8U)
9710#define DSI_WPCR2_TCLKZERO0_Msk (0x1UL << DSI_WPCR2_TCLKZERO0_Pos)
9711#define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
9712#define DSI_WPCR2_TCLKZERO1_Pos (9U)
9713#define DSI_WPCR2_TCLKZERO1_Msk (0x1UL << DSI_WPCR2_TCLKZERO1_Pos)
9714#define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
9715#define DSI_WPCR2_TCLKZERO2_Pos (10U)
9716#define DSI_WPCR2_TCLKZERO2_Msk (0x1UL << DSI_WPCR2_TCLKZERO2_Pos)
9717#define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
9718#define DSI_WPCR2_TCLKZERO3_Pos (11U)
9719#define DSI_WPCR2_TCLKZERO3_Msk (0x1UL << DSI_WPCR2_TCLKZERO3_Pos)
9720#define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
9721#define DSI_WPCR2_TCLKZERO4_Pos (12U)
9722#define DSI_WPCR2_TCLKZERO4_Msk (0x1UL << DSI_WPCR2_TCLKZERO4_Pos)
9723#define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
9724#define DSI_WPCR2_TCLKZERO5_Pos (13U)
9725#define DSI_WPCR2_TCLKZERO5_Msk (0x1UL << DSI_WPCR2_TCLKZERO5_Pos)
9726#define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
9727#define DSI_WPCR2_TCLKZERO6_Pos (14U)
9728#define DSI_WPCR2_TCLKZERO6_Msk (0x1UL << DSI_WPCR2_TCLKZERO6_Pos)
9729#define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
9730#define DSI_WPCR2_TCLKZERO7_Pos (15U)
9731#define DSI_WPCR2_TCLKZERO7_Msk (0x1UL << DSI_WPCR2_TCLKZERO7_Pos)
9732#define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
9733
9734#define DSI_WPCR2_THSPREP_Pos (16U)
9735#define DSI_WPCR2_THSPREP_Msk (0xFFUL << DSI_WPCR2_THSPREP_Pos)
9736#define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk
9737#define DSI_WPCR2_THSPREP0_Pos (16U)
9738#define DSI_WPCR2_THSPREP0_Msk (0x1UL << DSI_WPCR2_THSPREP0_Pos)
9739#define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
9740#define DSI_WPCR2_THSPREP1_Pos (17U)
9741#define DSI_WPCR2_THSPREP1_Msk (0x1UL << DSI_WPCR2_THSPREP1_Pos)
9742#define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
9743#define DSI_WPCR2_THSPREP2_Pos (18U)
9744#define DSI_WPCR2_THSPREP2_Msk (0x1UL << DSI_WPCR2_THSPREP2_Pos)
9745#define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
9746#define DSI_WPCR2_THSPREP3_Pos (19U)
9747#define DSI_WPCR2_THSPREP3_Msk (0x1UL << DSI_WPCR2_THSPREP3_Pos)
9748#define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
9749#define DSI_WPCR2_THSPREP4_Pos (20U)
9750#define DSI_WPCR2_THSPREP4_Msk (0x1UL << DSI_WPCR2_THSPREP4_Pos)
9751#define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
9752#define DSI_WPCR2_THSPREP5_Pos (21U)
9753#define DSI_WPCR2_THSPREP5_Msk (0x1UL << DSI_WPCR2_THSPREP5_Pos)
9754#define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
9755#define DSI_WPCR2_THSPREP6_Pos (22U)
9756#define DSI_WPCR2_THSPREP6_Msk (0x1UL << DSI_WPCR2_THSPREP6_Pos)
9757#define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
9758#define DSI_WPCR2_THSPREP7_Pos (23U)
9759#define DSI_WPCR2_THSPREP7_Msk (0x1UL << DSI_WPCR2_THSPREP7_Pos)
9760#define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
9761
9762#define DSI_WPCR2_THSTRAIL_Pos (24U)
9763#define DSI_WPCR2_THSTRAIL_Msk (0xFFUL << DSI_WPCR2_THSTRAIL_Pos)
9764#define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk
9765#define DSI_WPCR2_THSTRAIL0_Pos (24U)
9766#define DSI_WPCR2_THSTRAIL0_Msk (0x1UL << DSI_WPCR2_THSTRAIL0_Pos)
9767#define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
9768#define DSI_WPCR2_THSTRAIL1_Pos (25U)
9769#define DSI_WPCR2_THSTRAIL1_Msk (0x1UL << DSI_WPCR2_THSTRAIL1_Pos)
9770#define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
9771#define DSI_WPCR2_THSTRAIL2_Pos (26U)
9772#define DSI_WPCR2_THSTRAIL2_Msk (0x1UL << DSI_WPCR2_THSTRAIL2_Pos)
9773#define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
9774#define DSI_WPCR2_THSTRAIL3_Pos (27U)
9775#define DSI_WPCR2_THSTRAIL3_Msk (0x1UL << DSI_WPCR2_THSTRAIL3_Pos)
9776#define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
9777#define DSI_WPCR2_THSTRAIL4_Pos (28U)
9778#define DSI_WPCR2_THSTRAIL4_Msk (0x1UL << DSI_WPCR2_THSTRAIL4_Pos)
9779#define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
9780#define DSI_WPCR2_THSTRAIL5_Pos (29U)
9781#define DSI_WPCR2_THSTRAIL5_Msk (0x1UL << DSI_WPCR2_THSTRAIL5_Pos)
9782#define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
9783#define DSI_WPCR2_THSTRAIL6_Pos (30U)
9784#define DSI_WPCR2_THSTRAIL6_Msk (0x1UL << DSI_WPCR2_THSTRAIL6_Pos)
9785#define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
9786#define DSI_WPCR2_THSTRAIL7_Pos (31U)
9787#define DSI_WPCR2_THSTRAIL7_Msk (0x1UL << DSI_WPCR2_THSTRAIL7_Pos)
9788#define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
9789
9790/******************* Bit definition for DSI_WPCR3 register ***************/
9791#define DSI_WPCR3_THSZERO_Pos (0U)
9792#define DSI_WPCR3_THSZERO_Msk (0xFFUL << DSI_WPCR3_THSZERO_Pos)
9793#define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk
9794#define DSI_WPCR3_THSZERO0_Pos (0U)
9795#define DSI_WPCR3_THSZERO0_Msk (0x1UL << DSI_WPCR3_THSZERO0_Pos)
9796#define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
9797#define DSI_WPCR3_THSZERO1_Pos (1U)
9798#define DSI_WPCR3_THSZERO1_Msk (0x1UL << DSI_WPCR3_THSZERO1_Pos)
9799#define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
9800#define DSI_WPCR3_THSZERO2_Pos (2U)
9801#define DSI_WPCR3_THSZERO2_Msk (0x1UL << DSI_WPCR3_THSZERO2_Pos)
9802#define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
9803#define DSI_WPCR3_THSZERO3_Pos (3U)
9804#define DSI_WPCR3_THSZERO3_Msk (0x1UL << DSI_WPCR3_THSZERO3_Pos)
9805#define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
9806#define DSI_WPCR3_THSZERO4_Pos (4U)
9807#define DSI_WPCR3_THSZERO4_Msk (0x1UL << DSI_WPCR3_THSZERO4_Pos)
9808#define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
9809#define DSI_WPCR3_THSZERO5_Pos (5U)
9810#define DSI_WPCR3_THSZERO5_Msk (0x1UL << DSI_WPCR3_THSZERO5_Pos)
9811#define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
9812#define DSI_WPCR3_THSZERO6_Pos (6U)
9813#define DSI_WPCR3_THSZERO6_Msk (0x1UL << DSI_WPCR3_THSZERO6_Pos)
9814#define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
9815#define DSI_WPCR3_THSZERO7_Pos (7U)
9816#define DSI_WPCR3_THSZERO7_Msk (0x1UL << DSI_WPCR3_THSZERO7_Pos)
9817#define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
9818
9819#define DSI_WPCR3_TLPXD_Pos (8U)
9820#define DSI_WPCR3_TLPXD_Msk (0xFFUL << DSI_WPCR3_TLPXD_Pos)
9821#define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk
9822#define DSI_WPCR3_TLPXD0_Pos (8U)
9823#define DSI_WPCR3_TLPXD0_Msk (0x1UL << DSI_WPCR3_TLPXD0_Pos)
9824#define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
9825#define DSI_WPCR3_TLPXD1_Pos (9U)
9826#define DSI_WPCR3_TLPXD1_Msk (0x1UL << DSI_WPCR3_TLPXD1_Pos)
9827#define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
9828#define DSI_WPCR3_TLPXD2_Pos (10U)
9829#define DSI_WPCR3_TLPXD2_Msk (0x1UL << DSI_WPCR3_TLPXD2_Pos)
9830#define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
9831#define DSI_WPCR3_TLPXD3_Pos (11U)
9832#define DSI_WPCR3_TLPXD3_Msk (0x1UL << DSI_WPCR3_TLPXD3_Pos)
9833#define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
9834#define DSI_WPCR3_TLPXD4_Pos (12U)
9835#define DSI_WPCR3_TLPXD4_Msk (0x1UL << DSI_WPCR3_TLPXD4_Pos)
9836#define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
9837#define DSI_WPCR3_TLPXD5_Pos (13U)
9838#define DSI_WPCR3_TLPXD5_Msk (0x1UL << DSI_WPCR3_TLPXD5_Pos)
9839#define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
9840#define DSI_WPCR3_TLPXD6_Pos (14U)
9841#define DSI_WPCR3_TLPXD6_Msk (0x1UL << DSI_WPCR3_TLPXD6_Pos)
9842#define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
9843#define DSI_WPCR3_TLPXD7_Pos (15U)
9844#define DSI_WPCR3_TLPXD7_Msk (0x1UL << DSI_WPCR3_TLPXD7_Pos)
9845#define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
9846
9847#define DSI_WPCR3_THSEXIT_Pos (16U)
9848#define DSI_WPCR3_THSEXIT_Msk (0xFFUL << DSI_WPCR3_THSEXIT_Pos)
9849#define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk
9850#define DSI_WPCR3_THSEXIT0_Pos (16U)
9851#define DSI_WPCR3_THSEXIT0_Msk (0x1UL << DSI_WPCR3_THSEXIT0_Pos)
9852#define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
9853#define DSI_WPCR3_THSEXIT1_Pos (17U)
9854#define DSI_WPCR3_THSEXIT1_Msk (0x1UL << DSI_WPCR3_THSEXIT1_Pos)
9855#define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
9856#define DSI_WPCR3_THSEXIT2_Pos (18U)
9857#define DSI_WPCR3_THSEXIT2_Msk (0x1UL << DSI_WPCR3_THSEXIT2_Pos)
9858#define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
9859#define DSI_WPCR3_THSEXIT3_Pos (19U)
9860#define DSI_WPCR3_THSEXIT3_Msk (0x1UL << DSI_WPCR3_THSEXIT3_Pos)
9861#define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
9862#define DSI_WPCR3_THSEXIT4_Pos (20U)
9863#define DSI_WPCR3_THSEXIT4_Msk (0x1UL << DSI_WPCR3_THSEXIT4_Pos)
9864#define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
9865#define DSI_WPCR3_THSEXIT5_Pos (21U)
9866#define DSI_WPCR3_THSEXIT5_Msk (0x1UL << DSI_WPCR3_THSEXIT5_Pos)
9867#define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
9868#define DSI_WPCR3_THSEXIT6_Pos (22U)
9869#define DSI_WPCR3_THSEXIT6_Msk (0x1UL << DSI_WPCR3_THSEXIT6_Pos)
9870#define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
9871#define DSI_WPCR3_THSEXIT7_Pos (23U)
9872#define DSI_WPCR3_THSEXIT7_Msk (0x1UL << DSI_WPCR3_THSEXIT7_Pos)
9873#define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
9874
9875#define DSI_WPCR3_TLPXC_Pos (24U)
9876#define DSI_WPCR3_TLPXC_Msk (0xFFUL << DSI_WPCR3_TLPXC_Pos)
9877#define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk
9878#define DSI_WPCR3_TLPXC0_Pos (24U)
9879#define DSI_WPCR3_TLPXC0_Msk (0x1UL << DSI_WPCR3_TLPXC0_Pos)
9880#define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
9881#define DSI_WPCR3_TLPXC1_Pos (25U)
9882#define DSI_WPCR3_TLPXC1_Msk (0x1UL << DSI_WPCR3_TLPXC1_Pos)
9883#define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
9884#define DSI_WPCR3_TLPXC2_Pos (26U)
9885#define DSI_WPCR3_TLPXC2_Msk (0x1UL << DSI_WPCR3_TLPXC2_Pos)
9886#define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
9887#define DSI_WPCR3_TLPXC3_Pos (27U)
9888#define DSI_WPCR3_TLPXC3_Msk (0x1UL << DSI_WPCR3_TLPXC3_Pos)
9889#define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
9890#define DSI_WPCR3_TLPXC4_Pos (28U)
9891#define DSI_WPCR3_TLPXC4_Msk (0x1UL << DSI_WPCR3_TLPXC4_Pos)
9892#define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
9893#define DSI_WPCR3_TLPXC5_Pos (29U)
9894#define DSI_WPCR3_TLPXC5_Msk (0x1UL << DSI_WPCR3_TLPXC5_Pos)
9895#define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
9896#define DSI_WPCR3_TLPXC6_Pos (30U)
9897#define DSI_WPCR3_TLPXC6_Msk (0x1UL << DSI_WPCR3_TLPXC6_Pos)
9898#define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
9899#define DSI_WPCR3_TLPXC7_Pos (31U)
9900#define DSI_WPCR3_TLPXC7_Msk (0x1UL << DSI_WPCR3_TLPXC7_Pos)
9901#define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
9902
9903/******************* Bit definition for DSI_WPCR4 register ***************/
9904#define DSI_WPCR4_TCLKPOST_Pos (0U)
9905#define DSI_WPCR4_TCLKPOST_Msk (0xFFUL << DSI_WPCR4_TCLKPOST_Pos)
9906#define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk
9907#define DSI_WPCR4_TCLKPOST0_Pos (0U)
9908#define DSI_WPCR4_TCLKPOST0_Msk (0x1UL << DSI_WPCR4_TCLKPOST0_Pos)
9909#define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
9910#define DSI_WPCR4_TCLKPOST1_Pos (1U)
9911#define DSI_WPCR4_TCLKPOST1_Msk (0x1UL << DSI_WPCR4_TCLKPOST1_Pos)
9912#define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
9913#define DSI_WPCR4_TCLKPOST2_Pos (2U)
9914#define DSI_WPCR4_TCLKPOST2_Msk (0x1UL << DSI_WPCR4_TCLKPOST2_Pos)
9915#define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
9916#define DSI_WPCR4_TCLKPOST3_Pos (3U)
9917#define DSI_WPCR4_TCLKPOST3_Msk (0x1UL << DSI_WPCR4_TCLKPOST3_Pos)
9918#define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
9919#define DSI_WPCR4_TCLKPOST4_Pos (4U)
9920#define DSI_WPCR4_TCLKPOST4_Msk (0x1UL << DSI_WPCR4_TCLKPOST4_Pos)
9921#define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
9922#define DSI_WPCR4_TCLKPOST5_Pos (5U)
9923#define DSI_WPCR4_TCLKPOST5_Msk (0x1UL << DSI_WPCR4_TCLKPOST5_Pos)
9924#define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
9925#define DSI_WPCR4_TCLKPOST6_Pos (6U)
9926#define DSI_WPCR4_TCLKPOST6_Msk (0x1UL << DSI_WPCR4_TCLKPOST6_Pos)
9927#define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
9928#define DSI_WPCR4_TCLKPOST7_Pos (7U)
9929#define DSI_WPCR4_TCLKPOST7_Msk (0x1UL << DSI_WPCR4_TCLKPOST7_Pos)
9930#define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
9931
9932/******************* Bit definition for DSI_WRPCR register ***************/
9933#define DSI_WRPCR_PLLEN_Pos (0U)
9934#define DSI_WRPCR_PLLEN_Msk (0x1UL << DSI_WRPCR_PLLEN_Pos)
9935#define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk
9936#define DSI_WRPCR_PLL_NDIV_Pos (2U)
9937#define DSI_WRPCR_PLL_NDIV_Msk (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos)
9938#define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk
9939#define DSI_WRPCR_PLL_NDIV0_Pos (2U)
9940#define DSI_WRPCR_PLL_NDIV0_Msk (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos)
9941#define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
9942#define DSI_WRPCR_PLL_NDIV1_Pos (3U)
9943#define DSI_WRPCR_PLL_NDIV1_Msk (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos)
9944#define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
9945#define DSI_WRPCR_PLL_NDIV2_Pos (4U)
9946#define DSI_WRPCR_PLL_NDIV2_Msk (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos)
9947#define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
9948#define DSI_WRPCR_PLL_NDIV3_Pos (5U)
9949#define DSI_WRPCR_PLL_NDIV3_Msk (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos)
9950#define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
9951#define DSI_WRPCR_PLL_NDIV4_Pos (6U)
9952#define DSI_WRPCR_PLL_NDIV4_Msk (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos)
9953#define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
9954#define DSI_WRPCR_PLL_NDIV5_Pos (7U)
9955#define DSI_WRPCR_PLL_NDIV5_Msk (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos)
9956#define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
9957#define DSI_WRPCR_PLL_NDIV6_Pos (8U)
9958#define DSI_WRPCR_PLL_NDIV6_Msk (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos)
9959#define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
9960
9961#define DSI_WRPCR_PLL_IDF_Pos (11U)
9962#define DSI_WRPCR_PLL_IDF_Msk (0xFUL << DSI_WRPCR_PLL_IDF_Pos)
9963#define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk
9964#define DSI_WRPCR_PLL_IDF0_Pos (11U)
9965#define DSI_WRPCR_PLL_IDF0_Msk (0x1UL << DSI_WRPCR_PLL_IDF0_Pos)
9966#define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
9967#define DSI_WRPCR_PLL_IDF1_Pos (12U)
9968#define DSI_WRPCR_PLL_IDF1_Msk (0x1UL << DSI_WRPCR_PLL_IDF1_Pos)
9969#define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
9970#define DSI_WRPCR_PLL_IDF2_Pos (13U)
9971#define DSI_WRPCR_PLL_IDF2_Msk (0x1UL << DSI_WRPCR_PLL_IDF2_Pos)
9972#define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
9973#define DSI_WRPCR_PLL_IDF3_Pos (14U)
9974#define DSI_WRPCR_PLL_IDF3_Msk (0x1UL << DSI_WRPCR_PLL_IDF3_Pos)
9975#define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
9976
9977#define DSI_WRPCR_PLL_ODF_Pos (16U)
9978#define DSI_WRPCR_PLL_ODF_Msk (0x3UL << DSI_WRPCR_PLL_ODF_Pos)
9979#define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk
9980#define DSI_WRPCR_PLL_ODF0_Pos (16U)
9981#define DSI_WRPCR_PLL_ODF0_Msk (0x1UL << DSI_WRPCR_PLL_ODF0_Pos)
9982#define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
9983#define DSI_WRPCR_PLL_ODF1_Pos (17U)
9984#define DSI_WRPCR_PLL_ODF1_Msk (0x1UL << DSI_WRPCR_PLL_ODF1_Pos)
9985#define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
9986
9987#define DSI_WRPCR_REGEN_Pos (24U)
9988#define DSI_WRPCR_REGEN_Msk (0x1UL << DSI_WRPCR_REGEN_Pos)
9989#define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk
9991/******************************************************************************/
9992/* */
9993/* External Interrupt/Event Controller */
9994/* */
9995/******************************************************************************/
9996/******************* Bit definition for EXTI_IMR register *******************/
9997#define EXTI_IMR_MR0_Pos (0U)
9998#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
9999#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
10000#define EXTI_IMR_MR1_Pos (1U)
10001#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
10002#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
10003#define EXTI_IMR_MR2_Pos (2U)
10004#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
10005#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
10006#define EXTI_IMR_MR3_Pos (3U)
10007#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
10008#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
10009#define EXTI_IMR_MR4_Pos (4U)
10010#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
10011#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
10012#define EXTI_IMR_MR5_Pos (5U)
10013#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
10014#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
10015#define EXTI_IMR_MR6_Pos (6U)
10016#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
10017#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
10018#define EXTI_IMR_MR7_Pos (7U)
10019#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
10020#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
10021#define EXTI_IMR_MR8_Pos (8U)
10022#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
10023#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
10024#define EXTI_IMR_MR9_Pos (9U)
10025#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
10026#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
10027#define EXTI_IMR_MR10_Pos (10U)
10028#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
10029#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
10030#define EXTI_IMR_MR11_Pos (11U)
10031#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
10032#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
10033#define EXTI_IMR_MR12_Pos (12U)
10034#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
10035#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
10036#define EXTI_IMR_MR13_Pos (13U)
10037#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
10038#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
10039#define EXTI_IMR_MR14_Pos (14U)
10040#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
10041#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
10042#define EXTI_IMR_MR15_Pos (15U)
10043#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
10044#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
10045#define EXTI_IMR_MR16_Pos (16U)
10046#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
10047#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
10048#define EXTI_IMR_MR17_Pos (17U)
10049#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
10050#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
10051#define EXTI_IMR_MR18_Pos (18U)
10052#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
10053#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
10054#define EXTI_IMR_MR19_Pos (19U)
10055#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
10056#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
10057#define EXTI_IMR_MR20_Pos (20U)
10058#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
10059#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
10060#define EXTI_IMR_MR21_Pos (21U)
10061#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
10062#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
10063#define EXTI_IMR_MR22_Pos (22U)
10064#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
10065#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
10067/* Reference Defines */
10068#define EXTI_IMR_IM0 EXTI_IMR_MR0
10069#define EXTI_IMR_IM1 EXTI_IMR_MR1
10070#define EXTI_IMR_IM2 EXTI_IMR_MR2
10071#define EXTI_IMR_IM3 EXTI_IMR_MR3
10072#define EXTI_IMR_IM4 EXTI_IMR_MR4
10073#define EXTI_IMR_IM5 EXTI_IMR_MR5
10074#define EXTI_IMR_IM6 EXTI_IMR_MR6
10075#define EXTI_IMR_IM7 EXTI_IMR_MR7
10076#define EXTI_IMR_IM8 EXTI_IMR_MR8
10077#define EXTI_IMR_IM9 EXTI_IMR_MR9
10078#define EXTI_IMR_IM10 EXTI_IMR_MR10
10079#define EXTI_IMR_IM11 EXTI_IMR_MR11
10080#define EXTI_IMR_IM12 EXTI_IMR_MR12
10081#define EXTI_IMR_IM13 EXTI_IMR_MR13
10082#define EXTI_IMR_IM14 EXTI_IMR_MR14
10083#define EXTI_IMR_IM15 EXTI_IMR_MR15
10084#define EXTI_IMR_IM16 EXTI_IMR_MR16
10085#define EXTI_IMR_IM17 EXTI_IMR_MR17
10086#define EXTI_IMR_IM18 EXTI_IMR_MR18
10087#define EXTI_IMR_IM19 EXTI_IMR_MR19
10088#define EXTI_IMR_IM20 EXTI_IMR_MR20
10089#define EXTI_IMR_IM21 EXTI_IMR_MR21
10090#define EXTI_IMR_IM22 EXTI_IMR_MR22
10091#define EXTI_IMR_IM_Pos (0U)
10092#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
10093#define EXTI_IMR_IM EXTI_IMR_IM_Msk
10095/******************* Bit definition for EXTI_EMR register *******************/
10096#define EXTI_EMR_MR0_Pos (0U)
10097#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
10098#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
10099#define EXTI_EMR_MR1_Pos (1U)
10100#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
10101#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
10102#define EXTI_EMR_MR2_Pos (2U)
10103#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
10104#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
10105#define EXTI_EMR_MR3_Pos (3U)
10106#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
10107#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
10108#define EXTI_EMR_MR4_Pos (4U)
10109#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
10110#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
10111#define EXTI_EMR_MR5_Pos (5U)
10112#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
10113#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
10114#define EXTI_EMR_MR6_Pos (6U)
10115#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
10116#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
10117#define EXTI_EMR_MR7_Pos (7U)
10118#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
10119#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
10120#define EXTI_EMR_MR8_Pos (8U)
10121#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
10122#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
10123#define EXTI_EMR_MR9_Pos (9U)
10124#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
10125#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
10126#define EXTI_EMR_MR10_Pos (10U)
10127#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
10128#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
10129#define EXTI_EMR_MR11_Pos (11U)
10130#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
10131#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
10132#define EXTI_EMR_MR12_Pos (12U)
10133#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
10134#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
10135#define EXTI_EMR_MR13_Pos (13U)
10136#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
10137#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
10138#define EXTI_EMR_MR14_Pos (14U)
10139#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
10140#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
10141#define EXTI_EMR_MR15_Pos (15U)
10142#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
10143#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
10144#define EXTI_EMR_MR16_Pos (16U)
10145#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
10146#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
10147#define EXTI_EMR_MR17_Pos (17U)
10148#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
10149#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
10150#define EXTI_EMR_MR18_Pos (18U)
10151#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
10152#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
10153#define EXTI_EMR_MR19_Pos (19U)
10154#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
10155#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
10156#define EXTI_EMR_MR20_Pos (20U)
10157#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
10158#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
10159#define EXTI_EMR_MR21_Pos (21U)
10160#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
10161#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
10162#define EXTI_EMR_MR22_Pos (22U)
10163#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
10164#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
10166/* Reference Defines */
10167#define EXTI_EMR_EM0 EXTI_EMR_MR0
10168#define EXTI_EMR_EM1 EXTI_EMR_MR1
10169#define EXTI_EMR_EM2 EXTI_EMR_MR2
10170#define EXTI_EMR_EM3 EXTI_EMR_MR3
10171#define EXTI_EMR_EM4 EXTI_EMR_MR4
10172#define EXTI_EMR_EM5 EXTI_EMR_MR5
10173#define EXTI_EMR_EM6 EXTI_EMR_MR6
10174#define EXTI_EMR_EM7 EXTI_EMR_MR7
10175#define EXTI_EMR_EM8 EXTI_EMR_MR8
10176#define EXTI_EMR_EM9 EXTI_EMR_MR9
10177#define EXTI_EMR_EM10 EXTI_EMR_MR10
10178#define EXTI_EMR_EM11 EXTI_EMR_MR11
10179#define EXTI_EMR_EM12 EXTI_EMR_MR12
10180#define EXTI_EMR_EM13 EXTI_EMR_MR13
10181#define EXTI_EMR_EM14 EXTI_EMR_MR14
10182#define EXTI_EMR_EM15 EXTI_EMR_MR15
10183#define EXTI_EMR_EM16 EXTI_EMR_MR16
10184#define EXTI_EMR_EM17 EXTI_EMR_MR17
10185#define EXTI_EMR_EM18 EXTI_EMR_MR18
10186#define EXTI_EMR_EM19 EXTI_EMR_MR19
10187#define EXTI_EMR_EM20 EXTI_EMR_MR20
10188#define EXTI_EMR_EM21 EXTI_EMR_MR21
10189#define EXTI_EMR_EM22 EXTI_EMR_MR22
10190
10191/****************** Bit definition for EXTI_RTSR register *******************/
10192#define EXTI_RTSR_TR0_Pos (0U)
10193#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
10194#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
10195#define EXTI_RTSR_TR1_Pos (1U)
10196#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
10197#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
10198#define EXTI_RTSR_TR2_Pos (2U)
10199#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
10200#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
10201#define EXTI_RTSR_TR3_Pos (3U)
10202#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
10203#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
10204#define EXTI_RTSR_TR4_Pos (4U)
10205#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
10206#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
10207#define EXTI_RTSR_TR5_Pos (5U)
10208#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
10209#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
10210#define EXTI_RTSR_TR6_Pos (6U)
10211#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
10212#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
10213#define EXTI_RTSR_TR7_Pos (7U)
10214#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
10215#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
10216#define EXTI_RTSR_TR8_Pos (8U)
10217#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
10218#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
10219#define EXTI_RTSR_TR9_Pos (9U)
10220#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
10221#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
10222#define EXTI_RTSR_TR10_Pos (10U)
10223#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
10224#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
10225#define EXTI_RTSR_TR11_Pos (11U)
10226#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
10227#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
10228#define EXTI_RTSR_TR12_Pos (12U)
10229#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
10230#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
10231#define EXTI_RTSR_TR13_Pos (13U)
10232#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
10233#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
10234#define EXTI_RTSR_TR14_Pos (14U)
10235#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
10236#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
10237#define EXTI_RTSR_TR15_Pos (15U)
10238#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
10239#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
10240#define EXTI_RTSR_TR16_Pos (16U)
10241#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
10242#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
10243#define EXTI_RTSR_TR17_Pos (17U)
10244#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
10245#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
10246#define EXTI_RTSR_TR18_Pos (18U)
10247#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
10248#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
10249#define EXTI_RTSR_TR19_Pos (19U)
10250#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
10251#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
10252#define EXTI_RTSR_TR20_Pos (20U)
10253#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
10254#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
10255#define EXTI_RTSR_TR21_Pos (21U)
10256#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
10257#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
10258#define EXTI_RTSR_TR22_Pos (22U)
10259#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
10260#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
10262/****************** Bit definition for EXTI_FTSR register *******************/
10263#define EXTI_FTSR_TR0_Pos (0U)
10264#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
10265#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
10266#define EXTI_FTSR_TR1_Pos (1U)
10267#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
10268#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
10269#define EXTI_FTSR_TR2_Pos (2U)
10270#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
10271#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
10272#define EXTI_FTSR_TR3_Pos (3U)
10273#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
10274#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
10275#define EXTI_FTSR_TR4_Pos (4U)
10276#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
10277#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
10278#define EXTI_FTSR_TR5_Pos (5U)
10279#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
10280#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
10281#define EXTI_FTSR_TR6_Pos (6U)
10282#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
10283#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
10284#define EXTI_FTSR_TR7_Pos (7U)
10285#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
10286#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
10287#define EXTI_FTSR_TR8_Pos (8U)
10288#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
10289#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
10290#define EXTI_FTSR_TR9_Pos (9U)
10291#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
10292#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
10293#define EXTI_FTSR_TR10_Pos (10U)
10294#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
10295#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
10296#define EXTI_FTSR_TR11_Pos (11U)
10297#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
10298#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
10299#define EXTI_FTSR_TR12_Pos (12U)
10300#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
10301#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
10302#define EXTI_FTSR_TR13_Pos (13U)
10303#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
10304#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
10305#define EXTI_FTSR_TR14_Pos (14U)
10306#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
10307#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
10308#define EXTI_FTSR_TR15_Pos (15U)
10309#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
10310#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
10311#define EXTI_FTSR_TR16_Pos (16U)
10312#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
10313#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
10314#define EXTI_FTSR_TR17_Pos (17U)
10315#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
10316#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
10317#define EXTI_FTSR_TR18_Pos (18U)
10318#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
10319#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
10320#define EXTI_FTSR_TR19_Pos (19U)
10321#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
10322#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
10323#define EXTI_FTSR_TR20_Pos (20U)
10324#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
10325#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
10326#define EXTI_FTSR_TR21_Pos (21U)
10327#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
10328#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
10329#define EXTI_FTSR_TR22_Pos (22U)
10330#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
10331#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
10333/****************** Bit definition for EXTI_SWIER register ******************/
10334#define EXTI_SWIER_SWIER0_Pos (0U)
10335#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
10336#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
10337#define EXTI_SWIER_SWIER1_Pos (1U)
10338#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
10339#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
10340#define EXTI_SWIER_SWIER2_Pos (2U)
10341#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
10342#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
10343#define EXTI_SWIER_SWIER3_Pos (3U)
10344#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
10345#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
10346#define EXTI_SWIER_SWIER4_Pos (4U)
10347#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
10348#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
10349#define EXTI_SWIER_SWIER5_Pos (5U)
10350#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
10351#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
10352#define EXTI_SWIER_SWIER6_Pos (6U)
10353#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
10354#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
10355#define EXTI_SWIER_SWIER7_Pos (7U)
10356#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
10357#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
10358#define EXTI_SWIER_SWIER8_Pos (8U)
10359#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
10360#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
10361#define EXTI_SWIER_SWIER9_Pos (9U)
10362#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
10363#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
10364#define EXTI_SWIER_SWIER10_Pos (10U)
10365#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
10366#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
10367#define EXTI_SWIER_SWIER11_Pos (11U)
10368#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
10369#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
10370#define EXTI_SWIER_SWIER12_Pos (12U)
10371#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
10372#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
10373#define EXTI_SWIER_SWIER13_Pos (13U)
10374#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
10375#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
10376#define EXTI_SWIER_SWIER14_Pos (14U)
10377#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
10378#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
10379#define EXTI_SWIER_SWIER15_Pos (15U)
10380#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
10381#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
10382#define EXTI_SWIER_SWIER16_Pos (16U)
10383#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
10384#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
10385#define EXTI_SWIER_SWIER17_Pos (17U)
10386#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
10387#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
10388#define EXTI_SWIER_SWIER18_Pos (18U)
10389#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
10390#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
10391#define EXTI_SWIER_SWIER19_Pos (19U)
10392#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
10393#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
10394#define EXTI_SWIER_SWIER20_Pos (20U)
10395#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
10396#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
10397#define EXTI_SWIER_SWIER21_Pos (21U)
10398#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
10399#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
10400#define EXTI_SWIER_SWIER22_Pos (22U)
10401#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
10402#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
10404/******************* Bit definition for EXTI_PR register ********************/
10405#define EXTI_PR_PR0_Pos (0U)
10406#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
10407#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
10408#define EXTI_PR_PR1_Pos (1U)
10409#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
10410#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
10411#define EXTI_PR_PR2_Pos (2U)
10412#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
10413#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
10414#define EXTI_PR_PR3_Pos (3U)
10415#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
10416#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
10417#define EXTI_PR_PR4_Pos (4U)
10418#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
10419#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
10420#define EXTI_PR_PR5_Pos (5U)
10421#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
10422#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
10423#define EXTI_PR_PR6_Pos (6U)
10424#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
10425#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
10426#define EXTI_PR_PR7_Pos (7U)
10427#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
10428#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
10429#define EXTI_PR_PR8_Pos (8U)
10430#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
10431#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
10432#define EXTI_PR_PR9_Pos (9U)
10433#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
10434#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
10435#define EXTI_PR_PR10_Pos (10U)
10436#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
10437#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
10438#define EXTI_PR_PR11_Pos (11U)
10439#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
10440#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
10441#define EXTI_PR_PR12_Pos (12U)
10442#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
10443#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
10444#define EXTI_PR_PR13_Pos (13U)
10445#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
10446#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
10447#define EXTI_PR_PR14_Pos (14U)
10448#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
10449#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
10450#define EXTI_PR_PR15_Pos (15U)
10451#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
10452#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
10453#define EXTI_PR_PR16_Pos (16U)
10454#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
10455#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
10456#define EXTI_PR_PR17_Pos (17U)
10457#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
10458#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
10459#define EXTI_PR_PR18_Pos (18U)
10460#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
10461#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
10462#define EXTI_PR_PR19_Pos (19U)
10463#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
10464#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
10465#define EXTI_PR_PR20_Pos (20U)
10466#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
10467#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
10468#define EXTI_PR_PR21_Pos (21U)
10469#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
10470#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
10471#define EXTI_PR_PR22_Pos (22U)
10472#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
10473#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
10475/******************************************************************************/
10476/* */
10477/* FLASH */
10478/* */
10479/******************************************************************************/
10480/******************* Bits definition for FLASH_ACR register *****************/
10481#define FLASH_ACR_LATENCY_Pos (0U)
10482#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
10483#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
10484#define FLASH_ACR_LATENCY_0WS 0x00000000U
10485#define FLASH_ACR_LATENCY_1WS 0x00000001U
10486#define FLASH_ACR_LATENCY_2WS 0x00000002U
10487#define FLASH_ACR_LATENCY_3WS 0x00000003U
10488#define FLASH_ACR_LATENCY_4WS 0x00000004U
10489#define FLASH_ACR_LATENCY_5WS 0x00000005U
10490#define FLASH_ACR_LATENCY_6WS 0x00000006U
10491#define FLASH_ACR_LATENCY_7WS 0x00000007U
10492
10493#define FLASH_ACR_LATENCY_8WS 0x00000008U
10494#define FLASH_ACR_LATENCY_9WS 0x00000009U
10495#define FLASH_ACR_LATENCY_10WS 0x0000000AU
10496#define FLASH_ACR_LATENCY_11WS 0x0000000BU
10497#define FLASH_ACR_LATENCY_12WS 0x0000000CU
10498#define FLASH_ACR_LATENCY_13WS 0x0000000DU
10499#define FLASH_ACR_LATENCY_14WS 0x0000000EU
10500#define FLASH_ACR_LATENCY_15WS 0x0000000FU
10501
10502#define FLASH_ACR_PRFTEN_Pos (8U)
10503#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
10504#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
10505#define FLASH_ACR_ICEN_Pos (9U)
10506#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
10507#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
10508#define FLASH_ACR_DCEN_Pos (10U)
10509#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
10510#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
10511#define FLASH_ACR_ICRST_Pos (11U)
10512#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
10513#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
10514#define FLASH_ACR_DCRST_Pos (12U)
10515#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
10516#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
10517#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
10518#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
10519#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
10520#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
10521#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
10522#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
10523
10524/******************* Bits definition for FLASH_SR register ******************/
10525#define FLASH_SR_EOP_Pos (0U)
10526#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
10527#define FLASH_SR_EOP FLASH_SR_EOP_Msk
10528#define FLASH_SR_SOP_Pos (1U)
10529#define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos)
10530#define FLASH_SR_SOP FLASH_SR_SOP_Msk
10531#define FLASH_SR_WRPERR_Pos (4U)
10532#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
10533#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
10534#define FLASH_SR_PGAERR_Pos (5U)
10535#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
10536#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
10537#define FLASH_SR_PGPERR_Pos (6U)
10538#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
10539#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
10540#define FLASH_SR_PGSERR_Pos (7U)
10541#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
10542#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
10543#define FLASH_SR_RDERR_Pos (8U)
10544#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
10545#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
10546#define FLASH_SR_BSY_Pos (16U)
10547#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
10548#define FLASH_SR_BSY FLASH_SR_BSY_Msk
10549
10550/******************* Bits definition for FLASH_CR register ******************/
10551#define FLASH_CR_PG_Pos (0U)
10552#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
10553#define FLASH_CR_PG FLASH_CR_PG_Msk
10554#define FLASH_CR_SER_Pos (1U)
10555#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
10556#define FLASH_CR_SER FLASH_CR_SER_Msk
10557#define FLASH_CR_MER_Pos (2U)
10558#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
10559#define FLASH_CR_MER FLASH_CR_MER_Msk
10560#define FLASH_CR_MER1 FLASH_CR_MER
10561#define FLASH_CR_SNB_Pos (3U)
10562#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
10563#define FLASH_CR_SNB FLASH_CR_SNB_Msk
10564#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
10565#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
10566#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
10567#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
10568#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
10569#define FLASH_CR_PSIZE_Pos (8U)
10570#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
10571#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
10572#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
10573#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
10574#define FLASH_CR_MER2_Pos (15U)
10575#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos)
10576#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
10577#define FLASH_CR_STRT_Pos (16U)
10578#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
10579#define FLASH_CR_STRT FLASH_CR_STRT_Msk
10580#define FLASH_CR_EOPIE_Pos (24U)
10581#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
10582#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
10583#define FLASH_CR_ERRIE_Pos (25U)
10584#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
10585#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
10586#define FLASH_CR_LOCK_Pos (31U)
10587#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
10588#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
10589
10590/******************* Bits definition for FLASH_OPTCR register ***************/
10591#define FLASH_OPTCR_OPTLOCK_Pos (0U)
10592#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
10593#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
10594#define FLASH_OPTCR_OPTSTRT_Pos (1U)
10595#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
10596#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
10597
10598#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
10599#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
10600#define FLASH_OPTCR_BOR_LEV_Pos (2U)
10601#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
10602#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
10603#define FLASH_OPTCR_BFB2_Pos (4U)
10604#define FLASH_OPTCR_BFB2_Msk (0x1UL << FLASH_OPTCR_BFB2_Pos)
10605#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
10606#define FLASH_OPTCR_WDG_SW_Pos (5U)
10607#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
10608#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
10609#define FLASH_OPTCR_nRST_STOP_Pos (6U)
10610#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
10611#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
10612#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
10613#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
10614#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
10615#define FLASH_OPTCR_RDP_Pos (8U)
10616#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
10617#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
10618#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
10619#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
10620#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
10621#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
10622#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
10623#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
10624#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
10625#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
10626#define FLASH_OPTCR_nWRP_Pos (16U)
10627#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
10628#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
10629#define FLASH_OPTCR_nWRP_0 0x00010000U
10630#define FLASH_OPTCR_nWRP_1 0x00020000U
10631#define FLASH_OPTCR_nWRP_2 0x00040000U
10632#define FLASH_OPTCR_nWRP_3 0x00080000U
10633#define FLASH_OPTCR_nWRP_4 0x00100000U
10634#define FLASH_OPTCR_nWRP_5 0x00200000U
10635#define FLASH_OPTCR_nWRP_6 0x00400000U
10636#define FLASH_OPTCR_nWRP_7 0x00800000U
10637#define FLASH_OPTCR_nWRP_8 0x01000000U
10638#define FLASH_OPTCR_nWRP_9 0x02000000U
10639#define FLASH_OPTCR_nWRP_10 0x04000000U
10640#define FLASH_OPTCR_nWRP_11 0x08000000U
10641#define FLASH_OPTCR_DB1M_Pos (30U)
10642#define FLASH_OPTCR_DB1M_Msk (0x1UL << FLASH_OPTCR_DB1M_Pos)
10643#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
10644#define FLASH_OPTCR_SPRMOD_Pos (31U)
10645#define FLASH_OPTCR_SPRMOD_Msk (0x1UL << FLASH_OPTCR_SPRMOD_Pos)
10646#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
10647
10648/****************** Bits definition for FLASH_OPTCR1 register ***************/
10649#define FLASH_OPTCR1_nWRP_Pos (16U)
10650#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
10651#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
10652#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
10653#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
10654#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
10655#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
10656#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
10657#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
10658#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
10659#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
10660#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
10661#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
10662#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
10663#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
10665/******************************************************************************/
10666/* */
10667/* Flexible Memory Controller */
10668/* */
10669/******************************************************************************/
10670/****************** Bit definition for FMC_BCR1 register *******************/
10671#define FMC_BCR1_MBKEN_Pos (0U)
10672#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)
10673#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk
10674#define FMC_BCR1_MUXEN_Pos (1U)
10675#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)
10676#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk
10678#define FMC_BCR1_MTYP_Pos (2U)
10679#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)
10680#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk
10681#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)
10682#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)
10684#define FMC_BCR1_MWID_Pos (4U)
10685#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)
10686#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk
10687#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)
10688#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)
10690#define FMC_BCR1_FACCEN_Pos (6U)
10691#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)
10692#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk
10693#define FMC_BCR1_BURSTEN_Pos (8U)
10694#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)
10695#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk
10696#define FMC_BCR1_WAITPOL_Pos (9U)
10697#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)
10698#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk
10699#define FMC_BCR1_WAITCFG_Pos (11U)
10700#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)
10701#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk
10702#define FMC_BCR1_WREN_Pos (12U)
10703#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)
10704#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk
10705#define FMC_BCR1_WAITEN_Pos (13U)
10706#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)
10707#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk
10708#define FMC_BCR1_EXTMOD_Pos (14U)
10709#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)
10710#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk
10711#define FMC_BCR1_ASYNCWAIT_Pos (15U)
10712#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)
10713#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk
10714#define FMC_BCR1_CPSIZE_Pos (16U)
10715#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos)
10716#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk
10717#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos)
10718#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos)
10719#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos)
10720#define FMC_BCR1_CBURSTRW_Pos (19U)
10721#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)
10722#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk
10723#define FMC_BCR1_CCLKEN_Pos (20U)
10724#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
10725#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
10726#define FMC_BCR1_WFDIS_Pos (21U)
10727#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
10728#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
10730/****************** Bit definition for FMC_BCR2 register *******************/
10731#define FMC_BCR2_MBKEN_Pos (0U)
10732#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)
10733#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk
10734#define FMC_BCR2_MUXEN_Pos (1U)
10735#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)
10736#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk
10738#define FMC_BCR2_MTYP_Pos (2U)
10739#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)
10740#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk
10741#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)
10742#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)
10744#define FMC_BCR2_MWID_Pos (4U)
10745#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)
10746#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk
10747#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)
10748#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)
10750#define FMC_BCR2_FACCEN_Pos (6U)
10751#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)
10752#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk
10753#define FMC_BCR2_BURSTEN_Pos (8U)
10754#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)
10755#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk
10756#define FMC_BCR2_WAITPOL_Pos (9U)
10757#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)
10758#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk
10759#define FMC_BCR2_WAITCFG_Pos (11U)
10760#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)
10761#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk
10762#define FMC_BCR2_WREN_Pos (12U)
10763#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)
10764#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk
10765#define FMC_BCR2_WAITEN_Pos (13U)
10766#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)
10767#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk
10768#define FMC_BCR2_EXTMOD_Pos (14U)
10769#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)
10770#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk
10771#define FMC_BCR2_ASYNCWAIT_Pos (15U)
10772#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)
10773#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk
10774#define FMC_BCR2_CBURSTRW_Pos (19U)
10775#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)
10776#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk
10778/****************** Bit definition for FMC_BCR3 register *******************/
10779#define FMC_BCR3_MBKEN_Pos (0U)
10780#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)
10781#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk
10782#define FMC_BCR3_MUXEN_Pos (1U)
10783#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)
10784#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk
10786#define FMC_BCR3_MTYP_Pos (2U)
10787#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)
10788#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk
10789#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)
10790#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)
10792#define FMC_BCR3_MWID_Pos (4U)
10793#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)
10794#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk
10795#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)
10796#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)
10798#define FMC_BCR3_FACCEN_Pos (6U)
10799#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)
10800#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk
10801#define FMC_BCR3_BURSTEN_Pos (8U)
10802#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)
10803#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk
10804#define FMC_BCR3_WAITPOL_Pos (9U)
10805#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)
10806#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk
10807#define FMC_BCR3_WAITCFG_Pos (11U)
10808#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)
10809#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk
10810#define FMC_BCR3_WREN_Pos (12U)
10811#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)
10812#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk
10813#define FMC_BCR3_WAITEN_Pos (13U)
10814#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)
10815#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk
10816#define FMC_BCR3_EXTMOD_Pos (14U)
10817#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)
10818#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk
10819#define FMC_BCR3_ASYNCWAIT_Pos (15U)
10820#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)
10821#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk
10822#define FMC_BCR3_CBURSTRW_Pos (19U)
10823#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)
10824#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk
10826/****************** Bit definition for FMC_BCR4 register *******************/
10827#define FMC_BCR4_MBKEN_Pos (0U)
10828#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)
10829#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk
10830#define FMC_BCR4_MUXEN_Pos (1U)
10831#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)
10832#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk
10834#define FMC_BCR4_MTYP_Pos (2U)
10835#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)
10836#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk
10837#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)
10838#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)
10840#define FMC_BCR4_MWID_Pos (4U)
10841#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)
10842#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk
10843#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)
10844#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)
10846#define FMC_BCR4_FACCEN_Pos (6U)
10847#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)
10848#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk
10849#define FMC_BCR4_BURSTEN_Pos (8U)
10850#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)
10851#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk
10852#define FMC_BCR4_WAITPOL_Pos (9U)
10853#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)
10854#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk
10855#define FMC_BCR4_WAITCFG_Pos (11U)
10856#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)
10857#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk
10858#define FMC_BCR4_WREN_Pos (12U)
10859#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)
10860#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk
10861#define FMC_BCR4_WAITEN_Pos (13U)
10862#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)
10863#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk
10864#define FMC_BCR4_EXTMOD_Pos (14U)
10865#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)
10866#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk
10867#define FMC_BCR4_ASYNCWAIT_Pos (15U)
10868#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)
10869#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk
10870#define FMC_BCR4_CBURSTRW_Pos (19U)
10871#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)
10872#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk
10874/****************** Bit definition for FMC_BTR1 register ******************/
10875#define FMC_BTR1_ADDSET_Pos (0U)
10876#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)
10877#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk
10878#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)
10879#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)
10880#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)
10881#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)
10883#define FMC_BTR1_ADDHLD_Pos (4U)
10884#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)
10885#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk
10886#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)
10887#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)
10888#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)
10889#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)
10891#define FMC_BTR1_DATAST_Pos (8U)
10892#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)
10893#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk
10894#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)
10895#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)
10896#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)
10897#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)
10898#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)
10899#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)
10900#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)
10901#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)
10903#define FMC_BTR1_BUSTURN_Pos (16U)
10904#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)
10905#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk
10906#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)
10907#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)
10908#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)
10909#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)
10911#define FMC_BTR1_CLKDIV_Pos (20U)
10912#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)
10913#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk
10914#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)
10915#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)
10916#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)
10917#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)
10919#define FMC_BTR1_DATLAT_Pos (24U)
10920#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)
10921#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk
10922#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)
10923#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)
10924#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)
10925#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)
10927#define FMC_BTR1_ACCMOD_Pos (28U)
10928#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)
10929#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk
10930#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)
10931#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)
10933/****************** Bit definition for FMC_BTR2 register *******************/
10934#define FMC_BTR2_ADDSET_Pos (0U)
10935#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)
10936#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk
10937#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)
10938#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)
10939#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)
10940#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)
10942#define FMC_BTR2_ADDHLD_Pos (4U)
10943#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)
10944#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk
10945#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)
10946#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)
10947#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)
10948#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)
10950#define FMC_BTR2_DATAST_Pos (8U)
10951#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)
10952#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk
10953#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)
10954#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)
10955#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)
10956#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)
10957#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)
10958#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)
10959#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)
10960#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)
10962#define FMC_BTR2_BUSTURN_Pos (16U)
10963#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)
10964#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk
10965#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)
10966#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)
10967#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)
10968#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)
10970#define FMC_BTR2_CLKDIV_Pos (20U)
10971#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)
10972#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk
10973#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)
10974#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)
10975#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)
10976#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)
10978#define FMC_BTR2_DATLAT_Pos (24U)
10979#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)
10980#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk
10981#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)
10982#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)
10983#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)
10984#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)
10986#define FMC_BTR2_ACCMOD_Pos (28U)
10987#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)
10988#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk
10989#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)
10990#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)
10992/******************* Bit definition for FMC_BTR3 register *******************/
10993#define FMC_BTR3_ADDSET_Pos (0U)
10994#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)
10995#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk
10996#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)
10997#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)
10998#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)
10999#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)
11001#define FMC_BTR3_ADDHLD_Pos (4U)
11002#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)
11003#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk
11004#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)
11005#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)
11006#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)
11007#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)
11009#define FMC_BTR3_DATAST_Pos (8U)
11010#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)
11011#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk
11012#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)
11013#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)
11014#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)
11015#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)
11016#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)
11017#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)
11018#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)
11019#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)
11021#define FMC_BTR3_BUSTURN_Pos (16U)
11022#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)
11023#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk
11024#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)
11025#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)
11026#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)
11027#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)
11029#define FMC_BTR3_CLKDIV_Pos (20U)
11030#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)
11031#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk
11032#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)
11033#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)
11034#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)
11035#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)
11037#define FMC_BTR3_DATLAT_Pos (24U)
11038#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)
11039#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk
11040#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)
11041#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)
11042#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)
11043#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)
11045#define FMC_BTR3_ACCMOD_Pos (28U)
11046#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)
11047#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk
11048#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)
11049#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)
11051/****************** Bit definition for FMC_BTR4 register *******************/
11052#define FMC_BTR4_ADDSET_Pos (0U)
11053#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)
11054#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk
11055#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)
11056#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)
11057#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)
11058#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)
11060#define FMC_BTR4_ADDHLD_Pos (4U)
11061#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)
11062#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk
11063#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)
11064#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)
11065#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)
11066#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)
11068#define FMC_BTR4_DATAST_Pos (8U)
11069#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)
11070#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk
11071#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)
11072#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)
11073#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)
11074#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)
11075#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)
11076#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)
11077#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)
11078#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)
11080#define FMC_BTR4_BUSTURN_Pos (16U)
11081#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)
11082#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk
11083#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)
11084#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)
11085#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)
11086#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)
11088#define FMC_BTR4_CLKDIV_Pos (20U)
11089#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)
11090#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk
11091#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)
11092#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)
11093#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)
11094#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)
11096#define FMC_BTR4_DATLAT_Pos (24U)
11097#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)
11098#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk
11099#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)
11100#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)
11101#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)
11102#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)
11104#define FMC_BTR4_ACCMOD_Pos (28U)
11105#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)
11106#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk
11107#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)
11108#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)
11110/****************** Bit definition for FMC_BWTR1 register ******************/
11111#define FMC_BWTR1_ADDSET_Pos (0U)
11112#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)
11113#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk
11114#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)
11115#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)
11116#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)
11117#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)
11119#define FMC_BWTR1_ADDHLD_Pos (4U)
11120#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)
11121#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk
11122#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)
11123#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)
11124#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)
11125#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)
11127#define FMC_BWTR1_DATAST_Pos (8U)
11128#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)
11129#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk
11130#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)
11131#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)
11132#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)
11133#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)
11134#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)
11135#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)
11136#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)
11137#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)
11139#define FMC_BWTR1_BUSTURN_Pos (16U)
11140#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos)
11141#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk
11142#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos)
11143#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos)
11144#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos)
11145#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos)
11147#define FMC_BWTR1_ACCMOD_Pos (28U)
11148#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)
11149#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk
11150#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)
11151#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)
11153/****************** Bit definition for FMC_BWTR2 register ******************/
11154#define FMC_BWTR2_ADDSET_Pos (0U)
11155#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)
11156#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk
11157#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)
11158#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)
11159#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)
11160#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)
11162#define FMC_BWTR2_ADDHLD_Pos (4U)
11163#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)
11164#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk
11165#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)
11166#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)
11167#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)
11168#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)
11170#define FMC_BWTR2_DATAST_Pos (8U)
11171#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)
11172#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk
11173#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)
11174#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)
11175#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)
11176#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)
11177#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)
11178#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)
11179#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)
11180#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)
11182#define FMC_BWTR2_BUSTURN_Pos (16U)
11183#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos)
11184#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk
11185#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos)
11186#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos)
11187#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos)
11188#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos)
11190#define FMC_BWTR2_ACCMOD_Pos (28U)
11191#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)
11192#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk
11193#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)
11194#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)
11196/****************** Bit definition for FMC_BWTR3 register ******************/
11197#define FMC_BWTR3_ADDSET_Pos (0U)
11198#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)
11199#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk
11200#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)
11201#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)
11202#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)
11203#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)
11205#define FMC_BWTR3_ADDHLD_Pos (4U)
11206#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)
11207#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk
11208#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)
11209#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)
11210#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)
11211#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)
11213#define FMC_BWTR3_DATAST_Pos (8U)
11214#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)
11215#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk
11216#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)
11217#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)
11218#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)
11219#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)
11220#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)
11221#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)
11222#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)
11223#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)
11225#define FMC_BWTR3_BUSTURN_Pos (16U)
11226#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos)
11227#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk
11228#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos)
11229#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos)
11230#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos)
11231#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos)
11233#define FMC_BWTR3_ACCMOD_Pos (28U)
11234#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)
11235#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk
11236#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)
11237#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)
11239/****************** Bit definition for FMC_BWTR4 register ******************/
11240#define FMC_BWTR4_ADDSET_Pos (0U)
11241#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)
11242#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk
11243#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)
11244#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)
11245#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)
11246#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)
11248#define FMC_BWTR4_ADDHLD_Pos (4U)
11249#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)
11250#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk
11251#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)
11252#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)
11253#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)
11254#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)
11256#define FMC_BWTR4_DATAST_Pos (8U)
11257#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)
11258#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk
11259#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)
11260#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)
11261#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)
11262#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)
11263#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)
11264#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)
11265#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)
11266#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)
11268#define FMC_BWTR4_BUSTURN_Pos (16U)
11269#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos)
11270#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk
11271#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos)
11272#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos)
11273#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos)
11274#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos)
11276#define FMC_BWTR4_ACCMOD_Pos (28U)
11277#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)
11278#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk
11279#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)
11280#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)
11282/****************** Bit definition for FMC_PCR register *******************/
11283#define FMC_PCR_PWAITEN_Pos (1U)
11284#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
11285#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
11286#define FMC_PCR_PBKEN_Pos (2U)
11287#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
11288#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
11289#define FMC_PCR_PTYP_Pos (3U)
11290#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
11291#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
11293#define FMC_PCR_PWID_Pos (4U)
11294#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
11295#define FMC_PCR_PWID FMC_PCR_PWID_Msk
11296#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
11297#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
11299#define FMC_PCR_ECCEN_Pos (6U)
11300#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
11301#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
11303#define FMC_PCR_TCLR_Pos (9U)
11304#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
11305#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
11306#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
11307#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
11308#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
11309#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
11311#define FMC_PCR_TAR_Pos (13U)
11312#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
11313#define FMC_PCR_TAR FMC_PCR_TAR_Msk
11314#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
11315#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
11316#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
11317#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
11319#define FMC_PCR_ECCPS_Pos (17U)
11320#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
11321#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
11322#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
11323#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
11324#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
11326/******************* Bit definition for FMC_SR register *******************/
11327#define FMC_SR_IRS_Pos (0U)
11328#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
11329#define FMC_SR_IRS FMC_SR_IRS_Msk
11330#define FMC_SR_ILS_Pos (1U)
11331#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
11332#define FMC_SR_ILS FMC_SR_ILS_Msk
11333#define FMC_SR_IFS_Pos (2U)
11334#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
11335#define FMC_SR_IFS FMC_SR_IFS_Msk
11336#define FMC_SR_IREN_Pos (3U)
11337#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
11338#define FMC_SR_IREN FMC_SR_IREN_Msk
11339#define FMC_SR_ILEN_Pos (4U)
11340#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
11341#define FMC_SR_ILEN FMC_SR_ILEN_Msk
11342#define FMC_SR_IFEN_Pos (5U)
11343#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
11344#define FMC_SR_IFEN FMC_SR_IFEN_Msk
11345#define FMC_SR_FEMPT_Pos (6U)
11346#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
11347#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
11349/****************** Bit definition for FMC_PMEM register ******************/
11350#define FMC_PMEM_MEMSET2_Pos (0U)
11351#define FMC_PMEM_MEMSET2_Msk (0xFFUL << FMC_PMEM_MEMSET2_Pos)
11352#define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk
11353#define FMC_PMEM_MEMSET2_0 (0x01UL << FMC_PMEM_MEMSET2_Pos)
11354#define FMC_PMEM_MEMSET2_1 (0x02UL << FMC_PMEM_MEMSET2_Pos)
11355#define FMC_PMEM_MEMSET2_2 (0x04UL << FMC_PMEM_MEMSET2_Pos)
11356#define FMC_PMEM_MEMSET2_3 (0x08UL << FMC_PMEM_MEMSET2_Pos)
11357#define FMC_PMEM_MEMSET2_4 (0x10UL << FMC_PMEM_MEMSET2_Pos)
11358#define FMC_PMEM_MEMSET2_5 (0x20UL << FMC_PMEM_MEMSET2_Pos)
11359#define FMC_PMEM_MEMSET2_6 (0x40UL << FMC_PMEM_MEMSET2_Pos)
11360#define FMC_PMEM_MEMSET2_7 (0x80UL << FMC_PMEM_MEMSET2_Pos)
11362#define FMC_PMEM_MEMWAIT2_Pos (8U)
11363#define FMC_PMEM_MEMWAIT2_Msk (0xFFUL << FMC_PMEM_MEMWAIT2_Pos)
11364#define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk
11365#define FMC_PMEM_MEMWAIT2_0 (0x01UL << FMC_PMEM_MEMWAIT2_Pos)
11366#define FMC_PMEM_MEMWAIT2_1 (0x02UL << FMC_PMEM_MEMWAIT2_Pos)
11367#define FMC_PMEM_MEMWAIT2_2 (0x04UL << FMC_PMEM_MEMWAIT2_Pos)
11368#define FMC_PMEM_MEMWAIT2_3 (0x08UL << FMC_PMEM_MEMWAIT2_Pos)
11369#define FMC_PMEM_MEMWAIT2_4 (0x10UL << FMC_PMEM_MEMWAIT2_Pos)
11370#define FMC_PMEM_MEMWAIT2_5 (0x20UL << FMC_PMEM_MEMWAIT2_Pos)
11371#define FMC_PMEM_MEMWAIT2_6 (0x40UL << FMC_PMEM_MEMWAIT2_Pos)
11372#define FMC_PMEM_MEMWAIT2_7 (0x80UL << FMC_PMEM_MEMWAIT2_Pos)
11374#define FMC_PMEM_MEMHOLD2_Pos (16U)
11375#define FMC_PMEM_MEMHOLD2_Msk (0xFFUL << FMC_PMEM_MEMHOLD2_Pos)
11376#define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk
11377#define FMC_PMEM_MEMHOLD2_0 (0x01UL << FMC_PMEM_MEMHOLD2_Pos)
11378#define FMC_PMEM_MEMHOLD2_1 (0x02UL << FMC_PMEM_MEMHOLD2_Pos)
11379#define FMC_PMEM_MEMHOLD2_2 (0x04UL << FMC_PMEM_MEMHOLD2_Pos)
11380#define FMC_PMEM_MEMHOLD2_3 (0x08UL << FMC_PMEM_MEMHOLD2_Pos)
11381#define FMC_PMEM_MEMHOLD2_4 (0x10UL << FMC_PMEM_MEMHOLD2_Pos)
11382#define FMC_PMEM_MEMHOLD2_5 (0x20UL << FMC_PMEM_MEMHOLD2_Pos)
11383#define FMC_PMEM_MEMHOLD2_6 (0x40UL << FMC_PMEM_MEMHOLD2_Pos)
11384#define FMC_PMEM_MEMHOLD2_7 (0x80UL << FMC_PMEM_MEMHOLD2_Pos)
11386#define FMC_PMEM_MEMHIZ2_Pos (24U)
11387#define FMC_PMEM_MEMHIZ2_Msk (0xFFUL << FMC_PMEM_MEMHIZ2_Pos)
11388#define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk
11389#define FMC_PMEM_MEMHIZ2_0 (0x01UL << FMC_PMEM_MEMHIZ2_Pos)
11390#define FMC_PMEM_MEMHIZ2_1 (0x02UL << FMC_PMEM_MEMHIZ2_Pos)
11391#define FMC_PMEM_MEMHIZ2_2 (0x04UL << FMC_PMEM_MEMHIZ2_Pos)
11392#define FMC_PMEM_MEMHIZ2_3 (0x08UL << FMC_PMEM_MEMHIZ2_Pos)
11393#define FMC_PMEM_MEMHIZ2_4 (0x10UL << FMC_PMEM_MEMHIZ2_Pos)
11394#define FMC_PMEM_MEMHIZ2_5 (0x20UL << FMC_PMEM_MEMHIZ2_Pos)
11395#define FMC_PMEM_MEMHIZ2_6 (0x40UL << FMC_PMEM_MEMHIZ2_Pos)
11396#define FMC_PMEM_MEMHIZ2_7 (0x80UL << FMC_PMEM_MEMHIZ2_Pos)
11398/****************** Bit definition for FMC_PATT register ******************/
11399#define FMC_PATT_ATTSET2_Pos (0U)
11400#define FMC_PATT_ATTSET2_Msk (0xFFUL << FMC_PATT_ATTSET2_Pos)
11401#define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk
11402#define FMC_PATT_ATTSET2_0 (0x01UL << FMC_PATT_ATTSET2_Pos)
11403#define FMC_PATT_ATTSET2_1 (0x02UL << FMC_PATT_ATTSET2_Pos)
11404#define FMC_PATT_ATTSET2_2 (0x04UL << FMC_PATT_ATTSET2_Pos)
11405#define FMC_PATT_ATTSET2_3 (0x08UL << FMC_PATT_ATTSET2_Pos)
11406#define FMC_PATT_ATTSET2_4 (0x10UL << FMC_PATT_ATTSET2_Pos)
11407#define FMC_PATT_ATTSET2_5 (0x20UL << FMC_PATT_ATTSET2_Pos)
11408#define FMC_PATT_ATTSET2_6 (0x40UL << FMC_PATT_ATTSET2_Pos)
11409#define FMC_PATT_ATTSET2_7 (0x80UL << FMC_PATT_ATTSET2_Pos)
11411#define FMC_PATT_ATTWAIT2_Pos (8U)
11412#define FMC_PATT_ATTWAIT2_Msk (0xFFUL << FMC_PATT_ATTWAIT2_Pos)
11413#define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk
11414#define FMC_PATT_ATTWAIT2_0 (0x01UL << FMC_PATT_ATTWAIT2_Pos)
11415#define FMC_PATT_ATTWAIT2_1 (0x02UL << FMC_PATT_ATTWAIT2_Pos)
11416#define FMC_PATT_ATTWAIT2_2 (0x04UL << FMC_PATT_ATTWAIT2_Pos)
11417#define FMC_PATT_ATTWAIT2_3 (0x08UL << FMC_PATT_ATTWAIT2_Pos)
11418#define FMC_PATT_ATTWAIT2_4 (0x10UL << FMC_PATT_ATTWAIT2_Pos)
11419#define FMC_PATT_ATTWAIT2_5 (0x20UL << FMC_PATT_ATTWAIT2_Pos)
11420#define FMC_PATT_ATTWAIT2_6 (0x40UL << FMC_PATT_ATTWAIT2_Pos)
11421#define FMC_PATT_ATTWAIT2_7 (0x80UL << FMC_PATT_ATTWAIT2_Pos)
11423#define FMC_PATT_ATTHOLD2_Pos (16U)
11424#define FMC_PATT_ATTHOLD2_Msk (0xFFUL << FMC_PATT_ATTHOLD2_Pos)
11425#define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk
11426#define FMC_PATT_ATTHOLD2_0 (0x01UL << FMC_PATT_ATTHOLD2_Pos)
11427#define FMC_PATT_ATTHOLD2_1 (0x02UL << FMC_PATT_ATTHOLD2_Pos)
11428#define FMC_PATT_ATTHOLD2_2 (0x04UL << FMC_PATT_ATTHOLD2_Pos)
11429#define FMC_PATT_ATTHOLD2_3 (0x08UL << FMC_PATT_ATTHOLD2_Pos)
11430#define FMC_PATT_ATTHOLD2_4 (0x10UL << FMC_PATT_ATTHOLD2_Pos)
11431#define FMC_PATT_ATTHOLD2_5 (0x20UL << FMC_PATT_ATTHOLD2_Pos)
11432#define FMC_PATT_ATTHOLD2_6 (0x40UL << FMC_PATT_ATTHOLD2_Pos)
11433#define FMC_PATT_ATTHOLD2_7 (0x80UL << FMC_PATT_ATTHOLD2_Pos)
11435#define FMC_PATT_ATTHIZ2_Pos (24U)
11436#define FMC_PATT_ATTHIZ2_Msk (0xFFUL << FMC_PATT_ATTHIZ2_Pos)
11437#define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk
11438#define FMC_PATT_ATTHIZ2_0 (0x01UL << FMC_PATT_ATTHIZ2_Pos)
11439#define FMC_PATT_ATTHIZ2_1 (0x02UL << FMC_PATT_ATTHIZ2_Pos)
11440#define FMC_PATT_ATTHIZ2_2 (0x04UL << FMC_PATT_ATTHIZ2_Pos)
11441#define FMC_PATT_ATTHIZ2_3 (0x08UL << FMC_PATT_ATTHIZ2_Pos)
11442#define FMC_PATT_ATTHIZ2_4 (0x10UL << FMC_PATT_ATTHIZ2_Pos)
11443#define FMC_PATT_ATTHIZ2_5 (0x20UL << FMC_PATT_ATTHIZ2_Pos)
11444#define FMC_PATT_ATTHIZ2_6 (0x40UL << FMC_PATT_ATTHIZ2_Pos)
11445#define FMC_PATT_ATTHIZ2_7 (0x80UL << FMC_PATT_ATTHIZ2_Pos)
11447/****************** Bit definition for FMC_ECCR register ******************/
11448#define FMC_ECCR_ECC2_Pos (0U)
11449#define FMC_ECCR_ECC2_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC2_Pos)
11450#define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk
11452/****************** Bit definition for FMC_SDCR1 register ******************/
11453#define FMC_SDCR1_NC_Pos (0U)
11454#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos)
11455#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk
11456#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos)
11457#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos)
11459#define FMC_SDCR1_NR_Pos (2U)
11460#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos)
11461#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk
11462#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos)
11463#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos)
11465#define FMC_SDCR1_MWID_Pos (4U)
11466#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos)
11467#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk
11468#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos)
11469#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos)
11471#define FMC_SDCR1_NB_Pos (6U)
11472#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos)
11473#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk
11475#define FMC_SDCR1_CAS_Pos (7U)
11476#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos)
11477#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk
11478#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos)
11479#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos)
11481#define FMC_SDCR1_WP_Pos (9U)
11482#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos)
11483#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk
11485#define FMC_SDCR1_SDCLK_Pos (10U)
11486#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos)
11487#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk
11488#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos)
11489#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos)
11491#define FMC_SDCR1_RBURST_Pos (12U)
11492#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos)
11493#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk
11495#define FMC_SDCR1_RPIPE_Pos (13U)
11496#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos)
11497#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk
11498#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos)
11499#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos)
11501/****************** Bit definition for FMC_SDCR2 register ******************/
11502#define FMC_SDCR2_NC_Pos (0U)
11503#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos)
11504#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk
11505#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos)
11506#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos)
11508#define FMC_SDCR2_NR_Pos (2U)
11509#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos)
11510#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk
11511#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos)
11512#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos)
11514#define FMC_SDCR2_MWID_Pos (4U)
11515#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos)
11516#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk
11517#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos)
11518#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos)
11520#define FMC_SDCR2_NB_Pos (6U)
11521#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos)
11522#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk
11524#define FMC_SDCR2_CAS_Pos (7U)
11525#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos)
11526#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk
11527#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos)
11528#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos)
11530#define FMC_SDCR2_WP_Pos (9U)
11531#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos)
11532#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk
11534#define FMC_SDCR2_SDCLK_Pos (10U)
11535#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos)
11536#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk
11537#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos)
11538#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos)
11540#define FMC_SDCR2_RBURST_Pos (12U)
11541#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos)
11542#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk
11544#define FMC_SDCR2_RPIPE_Pos (13U)
11545#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos)
11546#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk
11547#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos)
11548#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos)
11550/****************** Bit definition for FMC_SDTR1 register ******************/
11551#define FMC_SDTR1_TMRD_Pos (0U)
11552#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos)
11553#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk
11554#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos)
11555#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos)
11556#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos)
11557#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos)
11559#define FMC_SDTR1_TXSR_Pos (4U)
11560#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos)
11561#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk
11562#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos)
11563#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos)
11564#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos)
11565#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos)
11567#define FMC_SDTR1_TRAS_Pos (8U)
11568#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos)
11569#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk
11570#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos)
11571#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos)
11572#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos)
11573#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos)
11575#define FMC_SDTR1_TRC_Pos (12U)
11576#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos)
11577#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk
11578#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos)
11579#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos)
11580#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos)
11582#define FMC_SDTR1_TWR_Pos (16U)
11583#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos)
11584#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk
11585#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos)
11586#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos)
11587#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos)
11589#define FMC_SDTR1_TRP_Pos (20U)
11590#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos)
11591#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk
11592#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos)
11593#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos)
11594#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos)
11596#define FMC_SDTR1_TRCD_Pos (24U)
11597#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos)
11598#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk
11599#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos)
11600#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos)
11601#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos)
11603/****************** Bit definition for FMC_SDTR2 register ******************/
11604#define FMC_SDTR2_TMRD_Pos (0U)
11605#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos)
11606#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk
11607#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos)
11608#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos)
11609#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos)
11610#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos)
11612#define FMC_SDTR2_TXSR_Pos (4U)
11613#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos)
11614#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk
11615#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos)
11616#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos)
11617#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos)
11618#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos)
11620#define FMC_SDTR2_TRAS_Pos (8U)
11621#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos)
11622#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk
11623#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos)
11624#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos)
11625#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos)
11626#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos)
11628#define FMC_SDTR2_TRC_Pos (12U)
11629#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos)
11630#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk
11631#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos)
11632#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos)
11633#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos)
11635#define FMC_SDTR2_TWR_Pos (16U)
11636#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos)
11637#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk
11638#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos)
11639#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos)
11640#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos)
11642#define FMC_SDTR2_TRP_Pos (20U)
11643#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos)
11644#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk
11645#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos)
11646#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos)
11647#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos)
11649#define FMC_SDTR2_TRCD_Pos (24U)
11650#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos)
11651#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk
11652#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos)
11653#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos)
11654#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos)
11656/****************** Bit definition for FMC_SDCMR register ******************/
11657#define FMC_SDCMR_MODE_Pos (0U)
11658#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
11659#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
11660#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
11661#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
11662#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos)
11664#define FMC_SDCMR_CTB2_Pos (3U)
11665#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
11666#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
11668#define FMC_SDCMR_CTB1_Pos (4U)
11669#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
11670#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
11672#define FMC_SDCMR_NRFS_Pos (5U)
11673#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
11674#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
11675#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
11676#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
11677#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
11678#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
11680#define FMC_SDCMR_MRD_Pos (9U)
11681#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
11682#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
11684/****************** Bit definition for FMC_SDRTR register ******************/
11685#define FMC_SDRTR_CRE_Pos (0U)
11686#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
11687#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
11689#define FMC_SDRTR_COUNT_Pos (1U)
11690#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
11691#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
11693#define FMC_SDRTR_REIE_Pos (14U)
11694#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
11695#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
11697/****************** Bit definition for FMC_SDSR register ******************/
11698#define FMC_SDSR_RE_Pos (0U)
11699#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
11700#define FMC_SDSR_RE FMC_SDSR_RE_Msk
11702#define FMC_SDSR_MODES1_Pos (1U)
11703#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
11704#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
11705#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
11706#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
11708#define FMC_SDSR_MODES2_Pos (3U)
11709#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
11710#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
11711#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
11712#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
11713#define FMC_SDSR_BUSY_Pos (5U)
11714#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos)
11715#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk
11717/******************************************************************************/
11718/* */
11719/* General Purpose I/O */
11720/* */
11721/******************************************************************************/
11722/****************** Bits definition for GPIO_MODER register *****************/
11723#define GPIO_MODER_MODER0_Pos (0U)
11724#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
11725#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
11726#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
11727#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
11728#define GPIO_MODER_MODER1_Pos (2U)
11729#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
11730#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
11731#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
11732#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
11733#define GPIO_MODER_MODER2_Pos (4U)
11734#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
11735#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
11736#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
11737#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
11738#define GPIO_MODER_MODER3_Pos (6U)
11739#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
11740#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
11741#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
11742#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
11743#define GPIO_MODER_MODER4_Pos (8U)
11744#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
11745#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
11746#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
11747#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
11748#define GPIO_MODER_MODER5_Pos (10U)
11749#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
11750#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
11751#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
11752#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
11753#define GPIO_MODER_MODER6_Pos (12U)
11754#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
11755#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
11756#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
11757#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
11758#define GPIO_MODER_MODER7_Pos (14U)
11759#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
11760#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
11761#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
11762#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
11763#define GPIO_MODER_MODER8_Pos (16U)
11764#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
11765#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
11766#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
11767#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
11768#define GPIO_MODER_MODER9_Pos (18U)
11769#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
11770#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
11771#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
11772#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
11773#define GPIO_MODER_MODER10_Pos (20U)
11774#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
11775#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
11776#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
11777#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
11778#define GPIO_MODER_MODER11_Pos (22U)
11779#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
11780#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
11781#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
11782#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
11783#define GPIO_MODER_MODER12_Pos (24U)
11784#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
11785#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
11786#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
11787#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
11788#define GPIO_MODER_MODER13_Pos (26U)
11789#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
11790#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
11791#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
11792#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
11793#define GPIO_MODER_MODER14_Pos (28U)
11794#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
11795#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
11796#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
11797#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
11798#define GPIO_MODER_MODER15_Pos (30U)
11799#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
11800#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
11801#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
11802#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
11804/* Legacy defines */
11805#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
11806#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
11807#define GPIO_MODER_MODE0 GPIO_MODER_MODER0
11808#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
11809#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
11810#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
11811#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
11812#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
11813#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
11814#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
11815#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
11816#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
11817#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
11818#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
11819#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
11820#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
11821#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
11822#define GPIO_MODER_MODE3 GPIO_MODER_MODER3
11823#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
11824#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
11825#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
11826#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
11827#define GPIO_MODER_MODE4 GPIO_MODER_MODER4
11828#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
11829#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
11830#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
11831#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
11832#define GPIO_MODER_MODE5 GPIO_MODER_MODER5
11833#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
11834#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
11835#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
11836#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
11837#define GPIO_MODER_MODE6 GPIO_MODER_MODER6
11838#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
11839#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
11840#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
11841#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
11842#define GPIO_MODER_MODE7 GPIO_MODER_MODER7
11843#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
11844#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
11845#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
11846#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
11847#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
11848#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
11849#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
11850#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
11851#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
11852#define GPIO_MODER_MODE9 GPIO_MODER_MODER9
11853#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
11854#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
11855#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
11856#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
11857#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
11858#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
11859#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
11860#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
11861#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
11862#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
11863#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
11864#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
11865#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
11866#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
11867#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
11868#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
11869#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
11870#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
11871#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
11872#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
11873#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
11874#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
11875#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
11876#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
11877#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
11878#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
11879#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
11880#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
11881#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
11882#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
11883#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
11884#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
11885
11886/****************** Bits definition for GPIO_OTYPER register ****************/
11887#define GPIO_OTYPER_OT0_Pos (0U)
11888#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
11889#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
11890#define GPIO_OTYPER_OT1_Pos (1U)
11891#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
11892#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
11893#define GPIO_OTYPER_OT2_Pos (2U)
11894#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
11895#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
11896#define GPIO_OTYPER_OT3_Pos (3U)
11897#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
11898#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
11899#define GPIO_OTYPER_OT4_Pos (4U)
11900#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
11901#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
11902#define GPIO_OTYPER_OT5_Pos (5U)
11903#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
11904#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
11905#define GPIO_OTYPER_OT6_Pos (6U)
11906#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
11907#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
11908#define GPIO_OTYPER_OT7_Pos (7U)
11909#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
11910#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
11911#define GPIO_OTYPER_OT8_Pos (8U)
11912#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
11913#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
11914#define GPIO_OTYPER_OT9_Pos (9U)
11915#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
11916#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
11917#define GPIO_OTYPER_OT10_Pos (10U)
11918#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
11919#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
11920#define GPIO_OTYPER_OT11_Pos (11U)
11921#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
11922#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
11923#define GPIO_OTYPER_OT12_Pos (12U)
11924#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
11925#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
11926#define GPIO_OTYPER_OT13_Pos (13U)
11927#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
11928#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
11929#define GPIO_OTYPER_OT14_Pos (14U)
11930#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
11931#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
11932#define GPIO_OTYPER_OT15_Pos (15U)
11933#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
11934#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
11935
11936/* Legacy defines */
11937#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
11938#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
11939#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
11940#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
11941#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
11942#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
11943#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
11944#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
11945#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
11946#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
11947#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
11948#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
11949#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
11950#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
11951#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
11952#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
11953
11954/****************** Bits definition for GPIO_OSPEEDR register ***************/
11955#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
11956#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
11957#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
11958#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
11959#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
11960#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
11961#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
11962#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
11963#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
11964#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
11965#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
11966#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
11967#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
11968#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
11969#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
11970#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
11971#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
11972#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
11973#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
11974#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
11975#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
11976#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
11977#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
11978#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
11979#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
11980#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
11981#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
11982#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
11983#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
11984#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
11985#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
11986#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
11987#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
11988#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
11989#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
11990#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
11991#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
11992#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
11993#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
11994#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
11995#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
11996#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
11997#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
11998#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
11999#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
12000#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
12001#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
12002#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
12003#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
12004#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
12005#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
12006#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
12007#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
12008#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
12009#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
12010#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
12011#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
12012#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
12013#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
12014#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
12015#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
12016#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
12017#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
12018#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
12019#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
12020#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
12021#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
12022#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
12023#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
12024#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
12025#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
12026#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
12027#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
12028#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
12029#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
12030#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
12031#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
12032#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
12033#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
12034#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
12036/* Legacy defines */
12037#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
12038#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
12039#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
12040#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
12041#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
12042#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
12043#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
12044#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
12045#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
12046#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
12047#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
12048#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
12049#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
12050#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
12051#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
12052#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
12053#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
12054#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
12055#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
12056#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
12057#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
12058#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
12059#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
12060#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
12061#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
12062#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
12063#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
12064#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
12065#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
12066#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
12067#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
12068#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
12069#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
12070#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
12071#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
12072#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
12073#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
12074#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
12075#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
12076#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
12077#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
12078#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
12079#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
12080#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
12081#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
12082#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
12083#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
12084#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
12085
12086/****************** Bits definition for GPIO_PUPDR register *****************/
12087#define GPIO_PUPDR_PUPD0_Pos (0U)
12088#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
12089#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
12090#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
12091#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
12092#define GPIO_PUPDR_PUPD1_Pos (2U)
12093#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
12094#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
12095#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
12096#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
12097#define GPIO_PUPDR_PUPD2_Pos (4U)
12098#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
12099#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
12100#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
12101#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
12102#define GPIO_PUPDR_PUPD3_Pos (6U)
12103#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
12104#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
12105#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
12106#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
12107#define GPIO_PUPDR_PUPD4_Pos (8U)
12108#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
12109#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
12110#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
12111#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
12112#define GPIO_PUPDR_PUPD5_Pos (10U)
12113#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
12114#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
12115#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
12116#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
12117#define GPIO_PUPDR_PUPD6_Pos (12U)
12118#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
12119#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
12120#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
12121#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
12122#define GPIO_PUPDR_PUPD7_Pos (14U)
12123#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
12124#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
12125#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
12126#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
12127#define GPIO_PUPDR_PUPD8_Pos (16U)
12128#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
12129#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
12130#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
12131#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
12132#define GPIO_PUPDR_PUPD9_Pos (18U)
12133#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
12134#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
12135#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
12136#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
12137#define GPIO_PUPDR_PUPD10_Pos (20U)
12138#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
12139#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
12140#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
12141#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
12142#define GPIO_PUPDR_PUPD11_Pos (22U)
12143#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
12144#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
12145#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
12146#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
12147#define GPIO_PUPDR_PUPD12_Pos (24U)
12148#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
12149#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
12150#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
12151#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
12152#define GPIO_PUPDR_PUPD13_Pos (26U)
12153#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
12154#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
12155#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
12156#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
12157#define GPIO_PUPDR_PUPD14_Pos (28U)
12158#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
12159#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
12160#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
12161#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
12162#define GPIO_PUPDR_PUPD15_Pos (30U)
12163#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
12164#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
12165#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
12166#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
12168/* Legacy defines */
12169#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
12170#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
12171#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
12172#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
12173#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
12174#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
12175#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
12176#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
12177#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
12178#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
12179#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
12180#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
12181#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
12182#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
12183#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
12184#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
12185#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
12186#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
12187#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
12188#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
12189#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
12190#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
12191#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
12192#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
12193#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
12194#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
12195#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
12196#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
12197#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
12198#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
12199#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
12200#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
12201#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
12202#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
12203#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
12204#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
12205#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
12206#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
12207#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
12208#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
12209#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
12210#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
12211#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
12212#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
12213#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
12214#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
12215#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
12216#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
12217
12218/****************** Bits definition for GPIO_IDR register *******************/
12219#define GPIO_IDR_ID0_Pos (0U)
12220#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
12221#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
12222#define GPIO_IDR_ID1_Pos (1U)
12223#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
12224#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
12225#define GPIO_IDR_ID2_Pos (2U)
12226#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
12227#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
12228#define GPIO_IDR_ID3_Pos (3U)
12229#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
12230#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
12231#define GPIO_IDR_ID4_Pos (4U)
12232#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
12233#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
12234#define GPIO_IDR_ID5_Pos (5U)
12235#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
12236#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
12237#define GPIO_IDR_ID6_Pos (6U)
12238#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
12239#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
12240#define GPIO_IDR_ID7_Pos (7U)
12241#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
12242#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
12243#define GPIO_IDR_ID8_Pos (8U)
12244#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
12245#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
12246#define GPIO_IDR_ID9_Pos (9U)
12247#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
12248#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
12249#define GPIO_IDR_ID10_Pos (10U)
12250#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
12251#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
12252#define GPIO_IDR_ID11_Pos (11U)
12253#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
12254#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
12255#define GPIO_IDR_ID12_Pos (12U)
12256#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
12257#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
12258#define GPIO_IDR_ID13_Pos (13U)
12259#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
12260#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
12261#define GPIO_IDR_ID14_Pos (14U)
12262#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
12263#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
12264#define GPIO_IDR_ID15_Pos (15U)
12265#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
12266#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
12267
12268/* Legacy defines */
12269#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
12270#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
12271#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
12272#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
12273#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
12274#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
12275#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
12276#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
12277#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
12278#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
12279#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
12280#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
12281#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
12282#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
12283#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
12284#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
12285
12286/****************** Bits definition for GPIO_ODR register *******************/
12287#define GPIO_ODR_OD0_Pos (0U)
12288#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
12289#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
12290#define GPIO_ODR_OD1_Pos (1U)
12291#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
12292#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
12293#define GPIO_ODR_OD2_Pos (2U)
12294#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
12295#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
12296#define GPIO_ODR_OD3_Pos (3U)
12297#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
12298#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
12299#define GPIO_ODR_OD4_Pos (4U)
12300#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
12301#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
12302#define GPIO_ODR_OD5_Pos (5U)
12303#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
12304#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
12305#define GPIO_ODR_OD6_Pos (6U)
12306#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
12307#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
12308#define GPIO_ODR_OD7_Pos (7U)
12309#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
12310#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
12311#define GPIO_ODR_OD8_Pos (8U)
12312#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
12313#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
12314#define GPIO_ODR_OD9_Pos (9U)
12315#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
12316#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
12317#define GPIO_ODR_OD10_Pos (10U)
12318#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
12319#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
12320#define GPIO_ODR_OD11_Pos (11U)
12321#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
12322#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
12323#define GPIO_ODR_OD12_Pos (12U)
12324#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
12325#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
12326#define GPIO_ODR_OD13_Pos (13U)
12327#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
12328#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
12329#define GPIO_ODR_OD14_Pos (14U)
12330#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
12331#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
12332#define GPIO_ODR_OD15_Pos (15U)
12333#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
12334#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
12335/* Legacy defines */
12336#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
12337#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
12338#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
12339#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
12340#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
12341#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
12342#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
12343#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
12344#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
12345#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
12346#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
12347#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
12348#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
12349#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
12350#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
12351#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
12352
12353/****************** Bits definition for GPIO_BSRR register ******************/
12354#define GPIO_BSRR_BS0_Pos (0U)
12355#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
12356#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
12357#define GPIO_BSRR_BS1_Pos (1U)
12358#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
12359#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
12360#define GPIO_BSRR_BS2_Pos (2U)
12361#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
12362#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
12363#define GPIO_BSRR_BS3_Pos (3U)
12364#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
12365#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
12366#define GPIO_BSRR_BS4_Pos (4U)
12367#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
12368#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
12369#define GPIO_BSRR_BS5_Pos (5U)
12370#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
12371#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
12372#define GPIO_BSRR_BS6_Pos (6U)
12373#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
12374#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
12375#define GPIO_BSRR_BS7_Pos (7U)
12376#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
12377#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
12378#define GPIO_BSRR_BS8_Pos (8U)
12379#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
12380#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
12381#define GPIO_BSRR_BS9_Pos (9U)
12382#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
12383#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
12384#define GPIO_BSRR_BS10_Pos (10U)
12385#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
12386#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
12387#define GPIO_BSRR_BS11_Pos (11U)
12388#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
12389#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
12390#define GPIO_BSRR_BS12_Pos (12U)
12391#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
12392#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
12393#define GPIO_BSRR_BS13_Pos (13U)
12394#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
12395#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
12396#define GPIO_BSRR_BS14_Pos (14U)
12397#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
12398#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
12399#define GPIO_BSRR_BS15_Pos (15U)
12400#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
12401#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
12402#define GPIO_BSRR_BR0_Pos (16U)
12403#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
12404#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
12405#define GPIO_BSRR_BR1_Pos (17U)
12406#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
12407#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
12408#define GPIO_BSRR_BR2_Pos (18U)
12409#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
12410#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
12411#define GPIO_BSRR_BR3_Pos (19U)
12412#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
12413#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
12414#define GPIO_BSRR_BR4_Pos (20U)
12415#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
12416#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
12417#define GPIO_BSRR_BR5_Pos (21U)
12418#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
12419#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
12420#define GPIO_BSRR_BR6_Pos (22U)
12421#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
12422#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
12423#define GPIO_BSRR_BR7_Pos (23U)
12424#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
12425#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
12426#define GPIO_BSRR_BR8_Pos (24U)
12427#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
12428#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
12429#define GPIO_BSRR_BR9_Pos (25U)
12430#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
12431#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
12432#define GPIO_BSRR_BR10_Pos (26U)
12433#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
12434#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
12435#define GPIO_BSRR_BR11_Pos (27U)
12436#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
12437#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
12438#define GPIO_BSRR_BR12_Pos (28U)
12439#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
12440#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
12441#define GPIO_BSRR_BR13_Pos (29U)
12442#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
12443#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
12444#define GPIO_BSRR_BR14_Pos (30U)
12445#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
12446#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
12447#define GPIO_BSRR_BR15_Pos (31U)
12448#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
12449#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
12450
12451/* Legacy defines */
12452#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
12453#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
12454#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
12455#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
12456#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
12457#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
12458#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
12459#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
12460#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
12461#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
12462#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
12463#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
12464#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
12465#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
12466#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
12467#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
12468#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
12469#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
12470#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
12471#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
12472#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
12473#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
12474#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
12475#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
12476#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
12477#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
12478#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
12479#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
12480#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
12481#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
12482#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
12483#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
12484#define GPIO_BRR_BR0 GPIO_BSRR_BR0
12485#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
12486#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
12487#define GPIO_BRR_BR1 GPIO_BSRR_BR1
12488#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
12489#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
12490#define GPIO_BRR_BR2 GPIO_BSRR_BR2
12491#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
12492#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
12493#define GPIO_BRR_BR3 GPIO_BSRR_BR3
12494#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
12495#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
12496#define GPIO_BRR_BR4 GPIO_BSRR_BR4
12497#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
12498#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
12499#define GPIO_BRR_BR5 GPIO_BSRR_BR5
12500#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
12501#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
12502#define GPIO_BRR_BR6 GPIO_BSRR_BR6
12503#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
12504#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
12505#define GPIO_BRR_BR7 GPIO_BSRR_BR7
12506#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
12507#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
12508#define GPIO_BRR_BR8 GPIO_BSRR_BR8
12509#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
12510#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
12511#define GPIO_BRR_BR9 GPIO_BSRR_BR9
12512#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
12513#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
12514#define GPIO_BRR_BR10 GPIO_BSRR_BR10
12515#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
12516#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
12517#define GPIO_BRR_BR11 GPIO_BSRR_BR11
12518#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
12519#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
12520#define GPIO_BRR_BR12 GPIO_BSRR_BR12
12521#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
12522#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
12523#define GPIO_BRR_BR13 GPIO_BSRR_BR13
12524#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
12525#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
12526#define GPIO_BRR_BR14 GPIO_BSRR_BR14
12527#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
12528#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
12529#define GPIO_BRR_BR15 GPIO_BSRR_BR15
12530#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
12531#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
12532/****************** Bit definition for GPIO_LCKR register *********************/
12533#define GPIO_LCKR_LCK0_Pos (0U)
12534#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
12535#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
12536#define GPIO_LCKR_LCK1_Pos (1U)
12537#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
12538#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
12539#define GPIO_LCKR_LCK2_Pos (2U)
12540#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
12541#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
12542#define GPIO_LCKR_LCK3_Pos (3U)
12543#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
12544#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
12545#define GPIO_LCKR_LCK4_Pos (4U)
12546#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
12547#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
12548#define GPIO_LCKR_LCK5_Pos (5U)
12549#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
12550#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
12551#define GPIO_LCKR_LCK6_Pos (6U)
12552#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
12553#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
12554#define GPIO_LCKR_LCK7_Pos (7U)
12555#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
12556#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
12557#define GPIO_LCKR_LCK8_Pos (8U)
12558#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
12559#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
12560#define GPIO_LCKR_LCK9_Pos (9U)
12561#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
12562#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
12563#define GPIO_LCKR_LCK10_Pos (10U)
12564#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
12565#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
12566#define GPIO_LCKR_LCK11_Pos (11U)
12567#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
12568#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
12569#define GPIO_LCKR_LCK12_Pos (12U)
12570#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
12571#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
12572#define GPIO_LCKR_LCK13_Pos (13U)
12573#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
12574#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
12575#define GPIO_LCKR_LCK14_Pos (14U)
12576#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
12577#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
12578#define GPIO_LCKR_LCK15_Pos (15U)
12579#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
12580#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
12581#define GPIO_LCKR_LCKK_Pos (16U)
12582#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
12583#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
12584/****************** Bit definition for GPIO_AFRL register *********************/
12585#define GPIO_AFRL_AFSEL0_Pos (0U)
12586#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
12587#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
12588#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
12589#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
12590#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
12591#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
12592#define GPIO_AFRL_AFSEL1_Pos (4U)
12593#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
12594#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
12595#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
12596#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
12597#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
12598#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
12599#define GPIO_AFRL_AFSEL2_Pos (8U)
12600#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
12601#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
12602#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
12603#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
12604#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
12605#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
12606#define GPIO_AFRL_AFSEL3_Pos (12U)
12607#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
12608#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
12609#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
12610#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
12611#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
12612#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
12613#define GPIO_AFRL_AFSEL4_Pos (16U)
12614#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
12615#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
12616#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
12617#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
12618#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
12619#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
12620#define GPIO_AFRL_AFSEL5_Pos (20U)
12621#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
12622#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
12623#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
12624#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
12625#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
12626#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
12627#define GPIO_AFRL_AFSEL6_Pos (24U)
12628#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
12629#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
12630#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
12631#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
12632#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
12633#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
12634#define GPIO_AFRL_AFSEL7_Pos (28U)
12635#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
12636#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
12637#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
12638#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
12639#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
12640#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
12642/* Legacy defines */
12643#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
12644#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
12645#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
12646#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
12647#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
12648#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
12649#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
12650#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
12651#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
12652#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
12653#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
12654#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
12655#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
12656#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
12657#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
12658#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
12659#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
12660#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
12661#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
12662#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
12663#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
12664#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
12665#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
12666#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
12667#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
12668#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
12669#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
12670#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
12671#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
12672#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
12673#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
12674#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
12675#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
12676#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
12677#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
12678#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
12679#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
12680#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
12681#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
12682#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
12683
12684/****************** Bit definition for GPIO_AFRH register *********************/
12685#define GPIO_AFRH_AFSEL8_Pos (0U)
12686#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
12687#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
12688#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
12689#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
12690#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
12691#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
12692#define GPIO_AFRH_AFSEL9_Pos (4U)
12693#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
12694#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
12695#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
12696#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
12697#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
12698#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
12699#define GPIO_AFRH_AFSEL10_Pos (8U)
12700#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
12701#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
12702#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
12703#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
12704#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
12705#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
12706#define GPIO_AFRH_AFSEL11_Pos (12U)
12707#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
12708#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
12709#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
12710#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
12711#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
12712#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
12713#define GPIO_AFRH_AFSEL12_Pos (16U)
12714#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
12715#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12716#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
12717#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
12718#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
12719#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
12720#define GPIO_AFRH_AFSEL13_Pos (20U)
12721#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
12722#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12723#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
12724#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
12725#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
12726#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
12727#define GPIO_AFRH_AFSEL14_Pos (24U)
12728#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
12729#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12730#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
12731#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
12732#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
12733#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
12734#define GPIO_AFRH_AFSEL15_Pos (28U)
12735#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
12736#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12737#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
12738#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
12739#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
12740#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
12742/* Legacy defines */
12743#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12744#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
12745#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
12746#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
12747#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
12748#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12749#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
12750#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
12751#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
12752#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
12753#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12754#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
12755#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
12756#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
12757#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
12758#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12759#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
12760#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
12761#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
12762#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
12763#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12764#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
12765#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
12766#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
12767#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
12768#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12769#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
12770#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
12771#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
12772#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
12773#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12774#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
12775#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
12776#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
12777#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
12778#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12779#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
12780#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
12781#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
12782#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
12783
12784
12785/******************************************************************************/
12786/* */
12787/* HASH */
12788/* */
12789/******************************************************************************/
12790/****************** Bits definition for HASH_CR register ********************/
12791#define HASH_CR_INIT_Pos (2U)
12792#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos)
12793#define HASH_CR_INIT HASH_CR_INIT_Msk
12794#define HASH_CR_DMAE_Pos (3U)
12795#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos)
12796#define HASH_CR_DMAE HASH_CR_DMAE_Msk
12797#define HASH_CR_DATATYPE_Pos (4U)
12798#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos)
12799#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
12800#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos)
12801#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos)
12802#define HASH_CR_MODE_Pos (6U)
12803#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos)
12804#define HASH_CR_MODE HASH_CR_MODE_Msk
12805#define HASH_CR_ALGO_Pos (7U)
12806#define HASH_CR_ALGO_Msk (0x801UL << HASH_CR_ALGO_Pos)
12807#define HASH_CR_ALGO HASH_CR_ALGO_Msk
12808#define HASH_CR_ALGO_0 (0x001UL << HASH_CR_ALGO_Pos)
12809#define HASH_CR_ALGO_1 (0x800UL << HASH_CR_ALGO_Pos)
12810#define HASH_CR_NBW_Pos (8U)
12811#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos)
12812#define HASH_CR_NBW HASH_CR_NBW_Msk
12813#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos)
12814#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos)
12815#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos)
12816#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos)
12817#define HASH_CR_DINNE_Pos (12U)
12818#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos)
12819#define HASH_CR_DINNE HASH_CR_DINNE_Msk
12820#define HASH_CR_MDMAT_Pos (13U)
12821#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos)
12822#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
12823#define HASH_CR_LKEY_Pos (16U)
12824#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos)
12825#define HASH_CR_LKEY HASH_CR_LKEY_Msk
12826
12827/****************** Bits definition for HASH_STR register *******************/
12828#define HASH_STR_NBLW_Pos (0U)
12829#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos)
12830#define HASH_STR_NBLW HASH_STR_NBLW_Msk
12831#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos)
12832#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos)
12833#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos)
12834#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos)
12835#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos)
12836#define HASH_STR_DCAL_Pos (8U)
12837#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos)
12838#define HASH_STR_DCAL HASH_STR_DCAL_Msk
12839/* Aliases for HASH_STR register */
12840#define HASH_STR_NBW HASH_STR_NBLW
12841#define HASH_STR_NBW_0 HASH_STR_NBLW_0
12842#define HASH_STR_NBW_1 HASH_STR_NBLW_1
12843#define HASH_STR_NBW_2 HASH_STR_NBLW_2
12844#define HASH_STR_NBW_3 HASH_STR_NBLW_3
12845#define HASH_STR_NBW_4 HASH_STR_NBLW_4
12846
12847/****************** Bits definition for HASH_IMR register *******************/
12848#define HASH_IMR_DINIE_Pos (0U)
12849#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos)
12850#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
12851#define HASH_IMR_DCIE_Pos (1U)
12852#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos)
12853#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
12854/* Aliases for HASH_IMR register */
12855#define HASH_IMR_DINIM HASH_IMR_DINIE
12856#define HASH_IMR_DCIM HASH_IMR_DCIE
12857
12858/****************** Bits definition for HASH_SR register ********************/
12859#define HASH_SR_DINIS_Pos (0U)
12860#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos)
12861#define HASH_SR_DINIS HASH_SR_DINIS_Msk
12862#define HASH_SR_DCIS_Pos (1U)
12863#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos)
12864#define HASH_SR_DCIS HASH_SR_DCIS_Msk
12865#define HASH_SR_DMAS_Pos (2U)
12866#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos)
12867#define HASH_SR_DMAS HASH_SR_DMAS_Msk
12868#define HASH_SR_BUSY_Pos (3U)
12869#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos)
12870#define HASH_SR_BUSY HASH_SR_BUSY_Msk
12871
12872/******************************************************************************/
12873/* */
12874/* Inter-integrated Circuit Interface */
12875/* */
12876/******************************************************************************/
12877/******************* Bit definition for I2C_CR1 register ********************/
12878#define I2C_CR1_PE_Pos (0U)
12879#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
12880#define I2C_CR1_PE I2C_CR1_PE_Msk
12881#define I2C_CR1_SMBUS_Pos (1U)
12882#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
12883#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
12884#define I2C_CR1_SMBTYPE_Pos (3U)
12885#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
12886#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
12887#define I2C_CR1_ENARP_Pos (4U)
12888#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
12889#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
12890#define I2C_CR1_ENPEC_Pos (5U)
12891#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
12892#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
12893#define I2C_CR1_ENGC_Pos (6U)
12894#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
12895#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
12896#define I2C_CR1_NOSTRETCH_Pos (7U)
12897#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
12898#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
12899#define I2C_CR1_START_Pos (8U)
12900#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
12901#define I2C_CR1_START I2C_CR1_START_Msk
12902#define I2C_CR1_STOP_Pos (9U)
12903#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
12904#define I2C_CR1_STOP I2C_CR1_STOP_Msk
12905#define I2C_CR1_ACK_Pos (10U)
12906#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
12907#define I2C_CR1_ACK I2C_CR1_ACK_Msk
12908#define I2C_CR1_POS_Pos (11U)
12909#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
12910#define I2C_CR1_POS I2C_CR1_POS_Msk
12911#define I2C_CR1_PEC_Pos (12U)
12912#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
12913#define I2C_CR1_PEC I2C_CR1_PEC_Msk
12914#define I2C_CR1_ALERT_Pos (13U)
12915#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
12916#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
12917#define I2C_CR1_SWRST_Pos (15U)
12918#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
12919#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
12921/******************* Bit definition for I2C_CR2 register ********************/
12922#define I2C_CR2_FREQ_Pos (0U)
12923#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
12924#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
12925#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
12926#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
12927#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
12928#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
12929#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
12930#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
12932#define I2C_CR2_ITERREN_Pos (8U)
12933#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
12934#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
12935#define I2C_CR2_ITEVTEN_Pos (9U)
12936#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
12937#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
12938#define I2C_CR2_ITBUFEN_Pos (10U)
12939#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
12940#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
12941#define I2C_CR2_DMAEN_Pos (11U)
12942#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
12943#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
12944#define I2C_CR2_LAST_Pos (12U)
12945#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
12946#define I2C_CR2_LAST I2C_CR2_LAST_Msk
12948/******************* Bit definition for I2C_OAR1 register *******************/
12949#define I2C_OAR1_ADD1_7 0x000000FEU
12950#define I2C_OAR1_ADD8_9 0x00000300U
12952#define I2C_OAR1_ADD0_Pos (0U)
12953#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
12954#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
12955#define I2C_OAR1_ADD1_Pos (1U)
12956#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
12957#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
12958#define I2C_OAR1_ADD2_Pos (2U)
12959#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
12960#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
12961#define I2C_OAR1_ADD3_Pos (3U)
12962#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
12963#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
12964#define I2C_OAR1_ADD4_Pos (4U)
12965#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
12966#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
12967#define I2C_OAR1_ADD5_Pos (5U)
12968#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
12969#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
12970#define I2C_OAR1_ADD6_Pos (6U)
12971#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
12972#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
12973#define I2C_OAR1_ADD7_Pos (7U)
12974#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
12975#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
12976#define I2C_OAR1_ADD8_Pos (8U)
12977#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
12978#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
12979#define I2C_OAR1_ADD9_Pos (9U)
12980#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
12981#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
12983#define I2C_OAR1_ADDMODE_Pos (15U)
12984#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
12985#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
12987/******************* Bit definition for I2C_OAR2 register *******************/
12988#define I2C_OAR2_ENDUAL_Pos (0U)
12989#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
12990#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
12991#define I2C_OAR2_ADD2_Pos (1U)
12992#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
12993#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
12995/******************** Bit definition for I2C_DR register ********************/
12996#define I2C_DR_DR_Pos (0U)
12997#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
12998#define I2C_DR_DR I2C_DR_DR_Msk
13000/******************* Bit definition for I2C_SR1 register ********************/
13001#define I2C_SR1_SB_Pos (0U)
13002#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
13003#define I2C_SR1_SB I2C_SR1_SB_Msk
13004#define I2C_SR1_ADDR_Pos (1U)
13005#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
13006#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
13007#define I2C_SR1_BTF_Pos (2U)
13008#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
13009#define I2C_SR1_BTF I2C_SR1_BTF_Msk
13010#define I2C_SR1_ADD10_Pos (3U)
13011#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
13012#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
13013#define I2C_SR1_STOPF_Pos (4U)
13014#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
13015#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
13016#define I2C_SR1_RXNE_Pos (6U)
13017#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
13018#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
13019#define I2C_SR1_TXE_Pos (7U)
13020#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
13021#define I2C_SR1_TXE I2C_SR1_TXE_Msk
13022#define I2C_SR1_BERR_Pos (8U)
13023#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
13024#define I2C_SR1_BERR I2C_SR1_BERR_Msk
13025#define I2C_SR1_ARLO_Pos (9U)
13026#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
13027#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
13028#define I2C_SR1_AF_Pos (10U)
13029#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
13030#define I2C_SR1_AF I2C_SR1_AF_Msk
13031#define I2C_SR1_OVR_Pos (11U)
13032#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
13033#define I2C_SR1_OVR I2C_SR1_OVR_Msk
13034#define I2C_SR1_PECERR_Pos (12U)
13035#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
13036#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
13037#define I2C_SR1_TIMEOUT_Pos (14U)
13038#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
13039#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
13040#define I2C_SR1_SMBALERT_Pos (15U)
13041#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
13042#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
13044/******************* Bit definition for I2C_SR2 register ********************/
13045#define I2C_SR2_MSL_Pos (0U)
13046#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
13047#define I2C_SR2_MSL I2C_SR2_MSL_Msk
13048#define I2C_SR2_BUSY_Pos (1U)
13049#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
13050#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
13051#define I2C_SR2_TRA_Pos (2U)
13052#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
13053#define I2C_SR2_TRA I2C_SR2_TRA_Msk
13054#define I2C_SR2_GENCALL_Pos (4U)
13055#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
13056#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
13057#define I2C_SR2_SMBDEFAULT_Pos (5U)
13058#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
13059#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
13060#define I2C_SR2_SMBHOST_Pos (6U)
13061#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
13062#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
13063#define I2C_SR2_DUALF_Pos (7U)
13064#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
13065#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
13066#define I2C_SR2_PEC_Pos (8U)
13067#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
13068#define I2C_SR2_PEC I2C_SR2_PEC_Msk
13070/******************* Bit definition for I2C_CCR register ********************/
13071#define I2C_CCR_CCR_Pos (0U)
13072#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
13073#define I2C_CCR_CCR I2C_CCR_CCR_Msk
13074#define I2C_CCR_DUTY_Pos (14U)
13075#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
13076#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
13077#define I2C_CCR_FS_Pos (15U)
13078#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
13079#define I2C_CCR_FS I2C_CCR_FS_Msk
13081/****************** Bit definition for I2C_TRISE register *******************/
13082#define I2C_TRISE_TRISE_Pos (0U)
13083#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
13084#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
13086/****************** Bit definition for I2C_FLTR register *******************/
13087#define I2C_FLTR_DNF_Pos (0U)
13088#define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos)
13089#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk
13090#define I2C_FLTR_ANOFF_Pos (4U)
13091#define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos)
13092#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk
13094/******************************************************************************/
13095/* */
13096/* Independent WATCHDOG */
13097/* */
13098/******************************************************************************/
13099/******************* Bit definition for IWDG_KR register ********************/
13100#define IWDG_KR_KEY_Pos (0U)
13101#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
13102#define IWDG_KR_KEY IWDG_KR_KEY_Msk
13104/******************* Bit definition for IWDG_PR register ********************/
13105#define IWDG_PR_PR_Pos (0U)
13106#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
13107#define IWDG_PR_PR IWDG_PR_PR_Msk
13108#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
13109#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
13110#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
13112/******************* Bit definition for IWDG_RLR register *******************/
13113#define IWDG_RLR_RL_Pos (0U)
13114#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
13115#define IWDG_RLR_RL IWDG_RLR_RL_Msk
13117/******************* Bit definition for IWDG_SR register ********************/
13118#define IWDG_SR_PVU_Pos (0U)
13119#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
13120#define IWDG_SR_PVU IWDG_SR_PVU_Msk
13121#define IWDG_SR_RVU_Pos (1U)
13122#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
13123#define IWDG_SR_RVU IWDG_SR_RVU_Msk
13126/******************************************************************************/
13127/* */
13128/* LCD-TFT Display Controller (LTDC) */
13129/* */
13130/******************************************************************************/
13131
13132/******************** Bit definition for LTDC_SSCR register *****************/
13133
13134#define LTDC_SSCR_VSH_Pos (0U)
13135#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
13136#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
13137#define LTDC_SSCR_HSW_Pos (16U)
13138#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
13139#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
13141/******************** Bit definition for LTDC_BPCR register *****************/
13142
13143#define LTDC_BPCR_AVBP_Pos (0U)
13144#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
13145#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
13146#define LTDC_BPCR_AHBP_Pos (16U)
13147#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
13148#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
13150/******************** Bit definition for LTDC_AWCR register *****************/
13151
13152#define LTDC_AWCR_AAH_Pos (0U)
13153#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
13154#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
13155#define LTDC_AWCR_AAW_Pos (16U)
13156#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
13157#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
13159/******************** Bit definition for LTDC_TWCR register *****************/
13160
13161#define LTDC_TWCR_TOTALH_Pos (0U)
13162#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
13163#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
13164#define LTDC_TWCR_TOTALW_Pos (16U)
13165#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
13166#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
13168/******************** Bit definition for LTDC_GCR register ******************/
13169
13170#define LTDC_GCR_LTDCEN_Pos (0U)
13171#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
13172#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
13173#define LTDC_GCR_DBW_Pos (4U)
13174#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
13175#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
13176#define LTDC_GCR_DGW_Pos (8U)
13177#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
13178#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
13179#define LTDC_GCR_DRW_Pos (12U)
13180#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
13181#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
13182#define LTDC_GCR_DEN_Pos (16U)
13183#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
13184#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
13185#define LTDC_GCR_PCPOL_Pos (28U)
13186#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
13187#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
13188#define LTDC_GCR_DEPOL_Pos (29U)
13189#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
13190#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
13191#define LTDC_GCR_VSPOL_Pos (30U)
13192#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
13193#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
13194#define LTDC_GCR_HSPOL_Pos (31U)
13195#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
13196#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
13198/* Legacy defines */
13199#define LTDC_GCR_DTEN LTDC_GCR_DEN
13200
13201/******************** Bit definition for LTDC_SRCR register *****************/
13202
13203#define LTDC_SRCR_IMR_Pos (0U)
13204#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
13205#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
13206#define LTDC_SRCR_VBR_Pos (1U)
13207#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
13208#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
13210/******************** Bit definition for LTDC_BCCR register *****************/
13211
13212#define LTDC_BCCR_BCBLUE_Pos (0U)
13213#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
13214#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
13215#define LTDC_BCCR_BCGREEN_Pos (8U)
13216#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
13217#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
13218#define LTDC_BCCR_BCRED_Pos (16U)
13219#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
13220#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
13222/******************** Bit definition for LTDC_IER register ******************/
13223
13224#define LTDC_IER_LIE_Pos (0U)
13225#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
13226#define LTDC_IER_LIE LTDC_IER_LIE_Msk
13227#define LTDC_IER_FUIE_Pos (1U)
13228#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
13229#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
13230#define LTDC_IER_TERRIE_Pos (2U)
13231#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
13232#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
13233#define LTDC_IER_RRIE_Pos (3U)
13234#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
13235#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
13237/******************** Bit definition for LTDC_ISR register ******************/
13238
13239#define LTDC_ISR_LIF_Pos (0U)
13240#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
13241#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
13242#define LTDC_ISR_FUIF_Pos (1U)
13243#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
13244#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
13245#define LTDC_ISR_TERRIF_Pos (2U)
13246#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
13247#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
13248#define LTDC_ISR_RRIF_Pos (3U)
13249#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
13250#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
13252/******************** Bit definition for LTDC_ICR register ******************/
13253
13254#define LTDC_ICR_CLIF_Pos (0U)
13255#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
13256#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
13257#define LTDC_ICR_CFUIF_Pos (1U)
13258#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
13259#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
13260#define LTDC_ICR_CTERRIF_Pos (2U)
13261#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
13262#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
13263#define LTDC_ICR_CRRIF_Pos (3U)
13264#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
13265#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
13267/******************** Bit definition for LTDC_LIPCR register ****************/
13268
13269#define LTDC_LIPCR_LIPOS_Pos (0U)
13270#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
13271#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
13273/******************** Bit definition for LTDC_CPSR register *****************/
13274
13275#define LTDC_CPSR_CYPOS_Pos (0U)
13276#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
13277#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
13278#define LTDC_CPSR_CXPOS_Pos (16U)
13279#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
13280#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
13282/******************** Bit definition for LTDC_CDSR register *****************/
13283
13284#define LTDC_CDSR_VDES_Pos (0U)
13285#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
13286#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
13287#define LTDC_CDSR_HDES_Pos (1U)
13288#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
13289#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
13290#define LTDC_CDSR_VSYNCS_Pos (2U)
13291#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
13292#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
13293#define LTDC_CDSR_HSYNCS_Pos (3U)
13294#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
13295#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
13297/******************** Bit definition for LTDC_LxCR register *****************/
13298
13299#define LTDC_LxCR_LEN_Pos (0U)
13300#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
13301#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
13302#define LTDC_LxCR_COLKEN_Pos (1U)
13303#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
13304#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
13305#define LTDC_LxCR_CLUTEN_Pos (4U)
13306#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
13307#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
13309/******************** Bit definition for LTDC_LxWHPCR register **************/
13310
13311#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
13312#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
13313#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
13314#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
13315#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
13316#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
13318/******************** Bit definition for LTDC_LxWVPCR register **************/
13319
13320#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
13321#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
13322#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
13323#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
13324#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
13325#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
13327/******************** Bit definition for LTDC_LxCKCR register ***************/
13328
13329#define LTDC_LxCKCR_CKBLUE_Pos (0U)
13330#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
13331#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
13332#define LTDC_LxCKCR_CKGREEN_Pos (8U)
13333#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
13334#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
13335#define LTDC_LxCKCR_CKRED_Pos (16U)
13336#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
13337#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
13339/******************** Bit definition for LTDC_LxPFCR register ***************/
13340
13341#define LTDC_LxPFCR_PF_Pos (0U)
13342#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
13343#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
13345/******************** Bit definition for LTDC_LxCACR register ***************/
13346
13347#define LTDC_LxCACR_CONSTA_Pos (0U)
13348#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
13349#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
13351/******************** Bit definition for LTDC_LxDCCR register ***************/
13352
13353#define LTDC_LxDCCR_DCBLUE_Pos (0U)
13354#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
13355#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
13356#define LTDC_LxDCCR_DCGREEN_Pos (8U)
13357#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
13358#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
13359#define LTDC_LxDCCR_DCRED_Pos (16U)
13360#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
13361#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
13362#define LTDC_LxDCCR_DCALPHA_Pos (24U)
13363#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
13364#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
13366/******************** Bit definition for LTDC_LxBFCR register ***************/
13367
13368#define LTDC_LxBFCR_BF2_Pos (0U)
13369#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
13370#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
13371#define LTDC_LxBFCR_BF1_Pos (8U)
13372#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
13373#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
13375/******************** Bit definition for LTDC_LxCFBAR register **************/
13376
13377#define LTDC_LxCFBAR_CFBADD_Pos (0U)
13378#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
13379#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
13381/******************** Bit definition for LTDC_LxCFBLR register **************/
13382
13383#define LTDC_LxCFBLR_CFBLL_Pos (0U)
13384#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
13385#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
13386#define LTDC_LxCFBLR_CFBP_Pos (16U)
13387#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
13388#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
13390/******************** Bit definition for LTDC_LxCFBLNR register *************/
13391
13392#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
13393#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
13394#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
13396/******************** Bit definition for LTDC_LxCLUTWR register *************/
13397
13398#define LTDC_LxCLUTWR_BLUE_Pos (0U)
13399#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
13400#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
13401#define LTDC_LxCLUTWR_GREEN_Pos (8U)
13402#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
13403#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
13404#define LTDC_LxCLUTWR_RED_Pos (16U)
13405#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
13406#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
13407#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
13408#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
13409#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
13412/******************************************************************************/
13413/* */
13414/* Power Control */
13415/* */
13416/******************************************************************************/
13417/******************** Bit definition for PWR_CR register ********************/
13418#define PWR_CR_LPDS_Pos (0U)
13419#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
13420#define PWR_CR_LPDS PWR_CR_LPDS_Msk
13421#define PWR_CR_PDDS_Pos (1U)
13422#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
13423#define PWR_CR_PDDS PWR_CR_PDDS_Msk
13424#define PWR_CR_CWUF_Pos (2U)
13425#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
13426#define PWR_CR_CWUF PWR_CR_CWUF_Msk
13427#define PWR_CR_CSBF_Pos (3U)
13428#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
13429#define PWR_CR_CSBF PWR_CR_CSBF_Msk
13430#define PWR_CR_PVDE_Pos (4U)
13431#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
13432#define PWR_CR_PVDE PWR_CR_PVDE_Msk
13434#define PWR_CR_PLS_Pos (5U)
13435#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
13436#define PWR_CR_PLS PWR_CR_PLS_Msk
13437#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
13438#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
13439#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
13442#define PWR_CR_PLS_LEV0 0x00000000U
13443#define PWR_CR_PLS_LEV1 0x00000020U
13444#define PWR_CR_PLS_LEV2 0x00000040U
13445#define PWR_CR_PLS_LEV3 0x00000060U
13446#define PWR_CR_PLS_LEV4 0x00000080U
13447#define PWR_CR_PLS_LEV5 0x000000A0U
13448#define PWR_CR_PLS_LEV6 0x000000C0U
13449#define PWR_CR_PLS_LEV7 0x000000E0U
13450#define PWR_CR_DBP_Pos (8U)
13451#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
13452#define PWR_CR_DBP PWR_CR_DBP_Msk
13453#define PWR_CR_FPDS_Pos (9U)
13454#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
13455#define PWR_CR_FPDS PWR_CR_FPDS_Msk
13456#define PWR_CR_LPLVDS_Pos (10U)
13457#define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos)
13458#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk
13459#define PWR_CR_MRLVDS_Pos (11U)
13460#define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos)
13461#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk
13462#define PWR_CR_ADCDC1_Pos (13U)
13463#define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos)
13464#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk
13465#define PWR_CR_VOS_Pos (14U)
13466#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)
13467#define PWR_CR_VOS PWR_CR_VOS_Msk
13468#define PWR_CR_VOS_0 0x00004000U
13469#define PWR_CR_VOS_1 0x00008000U
13470#define PWR_CR_ODEN_Pos (16U)
13471#define PWR_CR_ODEN_Msk (0x1UL << PWR_CR_ODEN_Pos)
13472#define PWR_CR_ODEN PWR_CR_ODEN_Msk
13473#define PWR_CR_ODSWEN_Pos (17U)
13474#define PWR_CR_ODSWEN_Msk (0x1UL << PWR_CR_ODSWEN_Pos)
13475#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk
13476#define PWR_CR_UDEN_Pos (18U)
13477#define PWR_CR_UDEN_Msk (0x3UL << PWR_CR_UDEN_Pos)
13478#define PWR_CR_UDEN PWR_CR_UDEN_Msk
13479#define PWR_CR_UDEN_0 (0x1UL << PWR_CR_UDEN_Pos)
13480#define PWR_CR_UDEN_1 (0x2UL << PWR_CR_UDEN_Pos)
13482/* Legacy define */
13483#define PWR_CR_PMODE PWR_CR_VOS
13484#define PWR_CR_LPUDS PWR_CR_LPLVDS
13485#define PWR_CR_MRUDS PWR_CR_MRLVDS
13487/******************* Bit definition for PWR_CSR register ********************/
13488#define PWR_CSR_WUF_Pos (0U)
13489#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
13490#define PWR_CSR_WUF PWR_CSR_WUF_Msk
13491#define PWR_CSR_SBF_Pos (1U)
13492#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
13493#define PWR_CSR_SBF PWR_CSR_SBF_Msk
13494#define PWR_CSR_PVDO_Pos (2U)
13495#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
13496#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
13497#define PWR_CSR_BRR_Pos (3U)
13498#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
13499#define PWR_CSR_BRR PWR_CSR_BRR_Msk
13500#define PWR_CSR_EWUP_Pos (8U)
13501#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
13502#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
13503#define PWR_CSR_BRE_Pos (9U)
13504#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
13505#define PWR_CSR_BRE PWR_CSR_BRE_Msk
13506#define PWR_CSR_VOSRDY_Pos (14U)
13507#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
13508#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
13509#define PWR_CSR_ODRDY_Pos (16U)
13510#define PWR_CSR_ODRDY_Msk (0x1UL << PWR_CSR_ODRDY_Pos)
13511#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk
13512#define PWR_CSR_ODSWRDY_Pos (17U)
13513#define PWR_CSR_ODSWRDY_Msk (0x1UL << PWR_CSR_ODSWRDY_Pos)
13514#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk
13515#define PWR_CSR_UDRDY_Pos (18U)
13516#define PWR_CSR_UDRDY_Msk (0x3UL << PWR_CSR_UDRDY_Pos)
13517#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk
13518/* Legacy define */
13519#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
13520
13521/* Legacy define */
13522#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
13523
13524/******************************************************************************/
13525/* */
13526/* QUADSPI */
13527/* */
13528/******************************************************************************/
13529/***************** Bit definition for QUADSPI_CR register *******************/
13530#define QUADSPI_CR_EN_Pos (0U)
13531#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
13532#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
13533#define QUADSPI_CR_ABORT_Pos (1U)
13534#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
13535#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
13536#define QUADSPI_CR_DMAEN_Pos (2U)
13537#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
13538#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
13539#define QUADSPI_CR_TCEN_Pos (3U)
13540#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
13541#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
13542#define QUADSPI_CR_SSHIFT_Pos (4U)
13543#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
13544#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
13545#define QUADSPI_CR_DFM_Pos (6U)
13546#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
13547#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
13548#define QUADSPI_CR_FSEL_Pos (7U)
13549#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
13550#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
13551#define QUADSPI_CR_FTHRES_Pos (8U)
13552#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
13553#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
13554#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos)
13555#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos)
13556#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos)
13557#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos)
13558#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
13559#define QUADSPI_CR_TEIE_Pos (16U)
13560#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
13561#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
13562#define QUADSPI_CR_TCIE_Pos (17U)
13563#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
13564#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
13565#define QUADSPI_CR_FTIE_Pos (18U)
13566#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
13567#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
13568#define QUADSPI_CR_SMIE_Pos (19U)
13569#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
13570#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
13571#define QUADSPI_CR_TOIE_Pos (20U)
13572#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
13573#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
13574#define QUADSPI_CR_APMS_Pos (22U)
13575#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
13576#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
13577#define QUADSPI_CR_PMM_Pos (23U)
13578#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
13579#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
13580#define QUADSPI_CR_PRESCALER_Pos (24U)
13581#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
13582#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
13583#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
13584#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
13585#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
13586#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
13587#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
13588#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
13589#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
13590#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
13592/***************** Bit definition for QUADSPI_DCR register ******************/
13593#define QUADSPI_DCR_CKMODE_Pos (0U)
13594#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
13595#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
13596#define QUADSPI_DCR_CSHT_Pos (8U)
13597#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
13598#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
13599#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
13600#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
13601#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
13602#define QUADSPI_DCR_FSIZE_Pos (16U)
13603#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
13604#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
13605#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
13606#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
13607#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
13608#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
13609#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
13611/****************** Bit definition for QUADSPI_SR register *******************/
13612#define QUADSPI_SR_TEF_Pos (0U)
13613#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
13614#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
13615#define QUADSPI_SR_TCF_Pos (1U)
13616#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
13617#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
13618#define QUADSPI_SR_FTF_Pos (2U)
13619#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
13620#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
13621#define QUADSPI_SR_SMF_Pos (3U)
13622#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
13623#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
13624#define QUADSPI_SR_TOF_Pos (4U)
13625#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
13626#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
13627#define QUADSPI_SR_BUSY_Pos (5U)
13628#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
13629#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
13630#define QUADSPI_SR_FLEVEL_Pos (8U)
13631#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
13632#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
13633#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
13634#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
13635#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
13636#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
13637#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
13638#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
13640/****************** Bit definition for QUADSPI_FCR register ******************/
13641#define QUADSPI_FCR_CTEF_Pos (0U)
13642#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
13643#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
13644#define QUADSPI_FCR_CTCF_Pos (1U)
13645#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
13646#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
13647#define QUADSPI_FCR_CSMF_Pos (3U)
13648#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
13649#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
13650#define QUADSPI_FCR_CTOF_Pos (4U)
13651#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
13652#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
13654/****************** Bit definition for QUADSPI_DLR register ******************/
13655#define QUADSPI_DLR_DL_Pos (0U)
13656#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
13657#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
13659/****************** Bit definition for QUADSPI_CCR register ******************/
13660#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
13661#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
13662#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
13663#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
13664#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
13665#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
13666#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
13667#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
13668#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
13669#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
13670#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
13671#define QUADSPI_CCR_IMODE_Pos (8U)
13672#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
13673#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
13674#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
13675#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
13676#define QUADSPI_CCR_ADMODE_Pos (10U)
13677#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
13678#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
13679#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
13680#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
13681#define QUADSPI_CCR_ADSIZE_Pos (12U)
13682#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
13683#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
13684#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
13685#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
13686#define QUADSPI_CCR_ABMODE_Pos (14U)
13687#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
13688#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
13689#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
13690#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
13691#define QUADSPI_CCR_ABSIZE_Pos (16U)
13692#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
13693#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
13694#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
13695#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
13696#define QUADSPI_CCR_DCYC_Pos (18U)
13697#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
13698#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
13699#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
13700#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
13701#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
13702#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
13703#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
13704#define QUADSPI_CCR_DMODE_Pos (24U)
13705#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
13706#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
13707#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
13708#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
13709#define QUADSPI_CCR_FMODE_Pos (26U)
13710#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
13711#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
13712#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
13713#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
13714#define QUADSPI_CCR_SIOO_Pos (28U)
13715#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
13716#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
13717#define QUADSPI_CCR_DHHC_Pos (30U)
13718#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
13719#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
13720#define QUADSPI_CCR_DDRM_Pos (31U)
13721#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
13722#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
13723/****************** Bit definition for QUADSPI_AR register *******************/
13724#define QUADSPI_AR_ADDRESS_Pos (0U)
13725#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
13726#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
13728/****************** Bit definition for QUADSPI_ABR register ******************/
13729#define QUADSPI_ABR_ALTERNATE_Pos (0U)
13730#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
13731#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
13733/****************** Bit definition for QUADSPI_DR register *******************/
13734#define QUADSPI_DR_DATA_Pos (0U)
13735#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
13736#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
13738/****************** Bit definition for QUADSPI_PSMKR register ****************/
13739#define QUADSPI_PSMKR_MASK_Pos (0U)
13740#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
13741#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
13743/****************** Bit definition for QUADSPI_PSMAR register ****************/
13744#define QUADSPI_PSMAR_MATCH_Pos (0U)
13745#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
13746#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
13748/****************** Bit definition for QUADSPI_PIR register *****************/
13749#define QUADSPI_PIR_INTERVAL_Pos (0U)
13750#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
13751#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
13753/****************** Bit definition for QUADSPI_LPTR register *****************/
13754#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
13755#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
13756#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
13758/******************************************************************************/
13759/* */
13760/* Reset and Clock Control */
13761/* */
13762/******************************************************************************/
13763/******************** Bit definition for RCC_CR register ********************/
13764#define RCC_CR_HSION_Pos (0U)
13765#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
13766#define RCC_CR_HSION RCC_CR_HSION_Msk
13767#define RCC_CR_HSIRDY_Pos (1U)
13768#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
13769#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
13770
13771#define RCC_CR_HSITRIM_Pos (3U)
13772#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
13773#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
13774#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
13775#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
13776#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
13777#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
13778#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
13780#define RCC_CR_HSICAL_Pos (8U)
13781#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
13782#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
13783#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
13784#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
13785#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
13786#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
13787#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
13788#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
13789#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
13790#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
13792#define RCC_CR_HSEON_Pos (16U)
13793#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
13794#define RCC_CR_HSEON RCC_CR_HSEON_Msk
13795#define RCC_CR_HSERDY_Pos (17U)
13796#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
13797#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
13798#define RCC_CR_HSEBYP_Pos (18U)
13799#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
13800#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
13801#define RCC_CR_CSSON_Pos (19U)
13802#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
13803#define RCC_CR_CSSON RCC_CR_CSSON_Msk
13804#define RCC_CR_PLLON_Pos (24U)
13805#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
13806#define RCC_CR_PLLON RCC_CR_PLLON_Msk
13807#define RCC_CR_PLLRDY_Pos (25U)
13808#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
13809#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
13810/*
13811 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
13812 */
13813#define RCC_PLLI2S_SUPPORT
13815#define RCC_CR_PLLI2SON_Pos (26U)
13816#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
13817#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
13818#define RCC_CR_PLLI2SRDY_Pos (27U)
13819#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
13820#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
13821/*
13822 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
13823 */
13824#define RCC_PLLSAI_SUPPORT
13826#define RCC_CR_PLLSAION_Pos (28U)
13827#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos)
13828#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
13829#define RCC_CR_PLLSAIRDY_Pos (29U)
13830#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos)
13831#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
13832
13833/******************** Bit definition for RCC_PLLCFGR register ***************/
13834#define RCC_PLLCFGR_PLLM_Pos (0U)
13835#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
13836#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
13837#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
13838#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
13839#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
13840#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
13841#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
13842#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
13844#define RCC_PLLCFGR_PLLN_Pos (6U)
13845#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
13846#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
13847#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
13848#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
13849#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
13850#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
13851#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
13852#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
13853#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
13854#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
13855#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
13857#define RCC_PLLCFGR_PLLP_Pos (16U)
13858#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
13859#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
13860#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
13861#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
13863#define RCC_PLLCFGR_PLLSRC_Pos (22U)
13864#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
13865#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
13866#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
13867#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
13868#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
13869#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
13870
13871#define RCC_PLLCFGR_PLLQ_Pos (24U)
13872#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
13873#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
13874#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
13875#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
13876#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
13877#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
13879#define RCC_PLLCFGR_PLLR_Pos (28U)
13880#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)
13881#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
13882#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
13883#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
13884#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)
13886/******************** Bit definition for RCC_CFGR register ******************/
13888#define RCC_CFGR_SW_Pos (0U)
13889#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
13890#define RCC_CFGR_SW RCC_CFGR_SW_Msk
13891#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
13892#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
13894#define RCC_CFGR_SW_HSI 0x00000000U
13895#define RCC_CFGR_SW_HSE 0x00000001U
13896#define RCC_CFGR_SW_PLL 0x00000002U
13899#define RCC_CFGR_SWS_Pos (2U)
13900#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
13901#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
13902#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
13903#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
13905#define RCC_CFGR_SWS_HSI 0x00000000U
13906#define RCC_CFGR_SWS_HSE 0x00000004U
13907#define RCC_CFGR_SWS_PLL 0x00000008U
13910#define RCC_CFGR_HPRE_Pos (4U)
13911#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
13912#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
13913#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
13914#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
13915#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
13916#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
13918#define RCC_CFGR_HPRE_DIV1 0x00000000U
13919#define RCC_CFGR_HPRE_DIV2 0x00000080U
13920#define RCC_CFGR_HPRE_DIV4 0x00000090U
13921#define RCC_CFGR_HPRE_DIV8 0x000000A0U
13922#define RCC_CFGR_HPRE_DIV16 0x000000B0U
13923#define RCC_CFGR_HPRE_DIV64 0x000000C0U
13924#define RCC_CFGR_HPRE_DIV128 0x000000D0U
13925#define RCC_CFGR_HPRE_DIV256 0x000000E0U
13926#define RCC_CFGR_HPRE_DIV512 0x000000F0U
13929#define RCC_CFGR_PPRE1_Pos (10U)
13930#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
13931#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
13932#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
13933#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
13934#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
13936#define RCC_CFGR_PPRE1_DIV1 0x00000000U
13937#define RCC_CFGR_PPRE1_DIV2 0x00001000U
13938#define RCC_CFGR_PPRE1_DIV4 0x00001400U
13939#define RCC_CFGR_PPRE1_DIV8 0x00001800U
13940#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
13943#define RCC_CFGR_PPRE2_Pos (13U)
13944#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
13945#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
13946#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
13947#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
13948#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
13950#define RCC_CFGR_PPRE2_DIV1 0x00000000U
13951#define RCC_CFGR_PPRE2_DIV2 0x00008000U
13952#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
13953#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
13954#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
13957#define RCC_CFGR_RTCPRE_Pos (16U)
13958#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
13959#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
13960#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
13961#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
13962#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
13963#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
13964#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
13967#define RCC_CFGR_MCO1_Pos (21U)
13968#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
13969#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
13970#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
13971#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
13973#define RCC_CFGR_I2SSRC_Pos (23U)
13974#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
13975#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
13976
13977#define RCC_CFGR_MCO1PRE_Pos (24U)
13978#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
13979#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
13980#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
13981#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
13982#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
13984#define RCC_CFGR_MCO2PRE_Pos (27U)
13985#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
13986#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
13987#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
13988#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
13989#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
13991#define RCC_CFGR_MCO2_Pos (30U)
13992#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
13993#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
13994#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
13995#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
13997/******************** Bit definition for RCC_CIR register *******************/
13998#define RCC_CIR_LSIRDYF_Pos (0U)
13999#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
14000#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
14001#define RCC_CIR_LSERDYF_Pos (1U)
14002#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
14003#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
14004#define RCC_CIR_HSIRDYF_Pos (2U)
14005#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
14006#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
14007#define RCC_CIR_HSERDYF_Pos (3U)
14008#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
14009#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
14010#define RCC_CIR_PLLRDYF_Pos (4U)
14011#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
14012#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
14013#define RCC_CIR_PLLI2SRDYF_Pos (5U)
14014#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
14015#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
14016
14017#define RCC_CIR_PLLSAIRDYF_Pos (6U)
14018#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)
14019#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
14020#define RCC_CIR_CSSF_Pos (7U)
14021#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
14022#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
14023#define RCC_CIR_LSIRDYIE_Pos (8U)
14024#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
14025#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
14026#define RCC_CIR_LSERDYIE_Pos (9U)
14027#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
14028#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
14029#define RCC_CIR_HSIRDYIE_Pos (10U)
14030#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
14031#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
14032#define RCC_CIR_HSERDYIE_Pos (11U)
14033#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
14034#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
14035#define RCC_CIR_PLLRDYIE_Pos (12U)
14036#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
14037#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
14038#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
14039#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
14040#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
14041
14042#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
14043#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)
14044#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
14045#define RCC_CIR_LSIRDYC_Pos (16U)
14046#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
14047#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
14048#define RCC_CIR_LSERDYC_Pos (17U)
14049#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
14050#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
14051#define RCC_CIR_HSIRDYC_Pos (18U)
14052#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
14053#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
14054#define RCC_CIR_HSERDYC_Pos (19U)
14055#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
14056#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
14057#define RCC_CIR_PLLRDYC_Pos (20U)
14058#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
14059#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
14060#define RCC_CIR_PLLI2SRDYC_Pos (21U)
14061#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
14062#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
14063#define RCC_CIR_PLLSAIRDYC_Pos (22U)
14064#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)
14065#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
14066
14067#define RCC_CIR_CSSC_Pos (23U)
14068#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
14069#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
14070
14071/******************** Bit definition for RCC_AHB1RSTR register **************/
14072#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
14073#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
14074#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
14075#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
14076#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
14077#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
14078#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
14079#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
14080#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
14081#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
14082#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
14083#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
14084#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
14085#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
14086#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
14087#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
14088#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
14089#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
14090#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
14091#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
14092#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
14093#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
14094#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
14095#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
14096#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
14097#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
14098#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
14099#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
14100#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos)
14101#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
14102#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
14103#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos)
14104#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
14105#define RCC_AHB1RSTR_CRCRST_Pos (12U)
14106#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
14107#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
14108#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
14109#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
14110#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
14111#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
14112#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
14113#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
14114#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
14115#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos)
14116#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
14117#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
14118#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
14119#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
14120#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
14121#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
14122#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
14123
14124/******************** Bit definition for RCC_AHB2RSTR register **************/
14125#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
14126#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
14127#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
14128#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
14129#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)
14130#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
14131#define RCC_AHB2RSTR_HASHRST_Pos (5U)
14132#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)
14133#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
14134 /* maintained for legacy purpose */
14135#define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
14136#define RCC_AHB2RSTR_RNGRST_Pos (6U)
14137#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
14138#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
14139#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
14140#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
14141#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
14142/******************** Bit definition for RCC_AHB3RSTR register **************/
14143#define RCC_AHB3RSTR_FMCRST_Pos (0U)
14144#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
14145#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
14146#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
14147#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
14148#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
14149
14150
14151/******************** Bit definition for RCC_APB1RSTR register **************/
14152#define RCC_APB1RSTR_TIM2RST_Pos (0U)
14153#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
14154#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
14155#define RCC_APB1RSTR_TIM3RST_Pos (1U)
14156#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
14157#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
14158#define RCC_APB1RSTR_TIM4RST_Pos (2U)
14159#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
14160#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
14161#define RCC_APB1RSTR_TIM5RST_Pos (3U)
14162#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
14163#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
14164#define RCC_APB1RSTR_TIM6RST_Pos (4U)
14165#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
14166#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
14167#define RCC_APB1RSTR_TIM7RST_Pos (5U)
14168#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
14169#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
14170#define RCC_APB1RSTR_TIM12RST_Pos (6U)
14171#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
14172#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
14173#define RCC_APB1RSTR_TIM13RST_Pos (7U)
14174#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
14175#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
14176#define RCC_APB1RSTR_TIM14RST_Pos (8U)
14177#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
14178#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
14179#define RCC_APB1RSTR_WWDGRST_Pos (11U)
14180#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
14181#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
14182#define RCC_APB1RSTR_SPI2RST_Pos (14U)
14183#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
14184#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
14185#define RCC_APB1RSTR_SPI3RST_Pos (15U)
14186#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
14187#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
14188#define RCC_APB1RSTR_USART2RST_Pos (17U)
14189#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
14190#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
14191#define RCC_APB1RSTR_USART3RST_Pos (18U)
14192#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
14193#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
14194#define RCC_APB1RSTR_UART4RST_Pos (19U)
14195#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
14196#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
14197#define RCC_APB1RSTR_UART5RST_Pos (20U)
14198#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
14199#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
14200#define RCC_APB1RSTR_I2C1RST_Pos (21U)
14201#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
14202#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
14203#define RCC_APB1RSTR_I2C2RST_Pos (22U)
14204#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
14205#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
14206#define RCC_APB1RSTR_I2C3RST_Pos (23U)
14207#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
14208#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
14209#define RCC_APB1RSTR_CAN1RST_Pos (25U)
14210#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
14211#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
14212#define RCC_APB1RSTR_CAN2RST_Pos (26U)
14213#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
14214#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
14215#define RCC_APB1RSTR_PWRRST_Pos (28U)
14216#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
14217#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
14218#define RCC_APB1RSTR_DACRST_Pos (29U)
14219#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
14220#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
14221#define RCC_APB1RSTR_UART7RST_Pos (30U)
14222#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos)
14223#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
14224#define RCC_APB1RSTR_UART8RST_Pos (31U)
14225#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos)
14226#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
14227
14228/******************** Bit definition for RCC_APB2RSTR register **************/
14229#define RCC_APB2RSTR_TIM1RST_Pos (0U)
14230#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
14231#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
14232#define RCC_APB2RSTR_TIM8RST_Pos (1U)
14233#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
14234#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
14235#define RCC_APB2RSTR_USART1RST_Pos (4U)
14236#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
14237#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
14238#define RCC_APB2RSTR_USART6RST_Pos (5U)
14239#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
14240#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
14241#define RCC_APB2RSTR_ADCRST_Pos (8U)
14242#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
14243#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
14244#define RCC_APB2RSTR_SDIORST_Pos (11U)
14245#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
14246#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
14247#define RCC_APB2RSTR_SPI1RST_Pos (12U)
14248#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
14249#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
14250#define RCC_APB2RSTR_SPI4RST_Pos (13U)
14251#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
14252#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
14253#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
14254#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
14255#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
14256#define RCC_APB2RSTR_TIM9RST_Pos (16U)
14257#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
14258#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
14259#define RCC_APB2RSTR_TIM10RST_Pos (17U)
14260#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
14261#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
14262#define RCC_APB2RSTR_TIM11RST_Pos (18U)
14263#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
14264#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
14265#define RCC_APB2RSTR_SPI5RST_Pos (20U)
14266#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
14267#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
14268#define RCC_APB2RSTR_SPI6RST_Pos (21U)
14269#define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)
14270#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
14271#define RCC_APB2RSTR_SAI1RST_Pos (22U)
14272#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
14273#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
14274#define RCC_APB2RSTR_LTDCRST_Pos (26U)
14275#define RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)
14276#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
14277#define RCC_APB2RSTR_DSIRST_Pos (27U)
14278#define RCC_APB2RSTR_DSIRST_Msk (0x1UL << RCC_APB2RSTR_DSIRST_Pos)
14279#define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk
14280
14281/* Old SPI1RST bit definition, maintained for legacy purpose */
14282#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
14283
14284/******************** Bit definition for RCC_AHB1ENR register ***************/
14285#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
14286#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
14287#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
14288#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
14289#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
14290#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
14291#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
14292#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
14293#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
14294#define RCC_AHB1ENR_GPIODEN_Pos (3U)
14295#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
14296#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
14297#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
14298#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
14299#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
14300#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
14301#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
14302#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
14303#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
14304#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
14305#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
14306#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
14307#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
14308#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
14309#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
14310#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
14311#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
14312#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
14313#define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)
14314#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
14315#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
14316#define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)
14317#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
14318#define RCC_AHB1ENR_CRCEN_Pos (12U)
14319#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
14320#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
14321#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
14322#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
14323#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
14324#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
14325#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
14326#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
14327#define RCC_AHB1ENR_DMA1EN_Pos (21U)
14328#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
14329#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
14330#define RCC_AHB1ENR_DMA2EN_Pos (22U)
14331#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
14332#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
14333#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
14334#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)
14335#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
14336#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
14337#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
14338#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
14339#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
14340#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
14341#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
14342#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
14343#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
14344#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
14345#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
14346#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
14347#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
14348#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
14349#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
14350#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
14351#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
14352#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
14353#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
14354/******************** Bit definition for RCC_AHB2ENR register ***************/
14355/*
14356 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14357 */
14358#define RCC_AHB2_SUPPORT
14360#define RCC_AHB2ENR_DCMIEN_Pos (0U)
14361#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
14362#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
14363#define RCC_AHB2ENR_CRYPEN_Pos (4U)
14364#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)
14365#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
14366#define RCC_AHB2ENR_HASHEN_Pos (5U)
14367#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos)
14368#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
14369#define RCC_AHB2ENR_RNGEN_Pos (6U)
14370#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
14371#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
14372#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
14373#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
14374#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
14375
14376/******************** Bit definition for RCC_AHB3ENR register ***************/
14377/*
14378 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14379 */
14380#define RCC_AHB3_SUPPORT
14382#define RCC_AHB3ENR_FMCEN_Pos (0U)
14383#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
14384#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
14385#define RCC_AHB3ENR_QSPIEN_Pos (1U)
14386#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
14387#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
14388
14389/******************** Bit definition for RCC_APB1ENR register ***************/
14390#define RCC_APB1ENR_TIM2EN_Pos (0U)
14391#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
14392#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
14393#define RCC_APB1ENR_TIM3EN_Pos (1U)
14394#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
14395#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
14396#define RCC_APB1ENR_TIM4EN_Pos (2U)
14397#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
14398#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
14399#define RCC_APB1ENR_TIM5EN_Pos (3U)
14400#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
14401#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
14402#define RCC_APB1ENR_TIM6EN_Pos (4U)
14403#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
14404#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
14405#define RCC_APB1ENR_TIM7EN_Pos (5U)
14406#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
14407#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
14408#define RCC_APB1ENR_TIM12EN_Pos (6U)
14409#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
14410#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
14411#define RCC_APB1ENR_TIM13EN_Pos (7U)
14412#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
14413#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
14414#define RCC_APB1ENR_TIM14EN_Pos (8U)
14415#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
14416#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
14417#define RCC_APB1ENR_WWDGEN_Pos (11U)
14418#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
14419#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
14420#define RCC_APB1ENR_SPI2EN_Pos (14U)
14421#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
14422#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
14423#define RCC_APB1ENR_SPI3EN_Pos (15U)
14424#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
14425#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
14426#define RCC_APB1ENR_USART2EN_Pos (17U)
14427#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
14428#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
14429#define RCC_APB1ENR_USART3EN_Pos (18U)
14430#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
14431#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
14432#define RCC_APB1ENR_UART4EN_Pos (19U)
14433#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
14434#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
14435#define RCC_APB1ENR_UART5EN_Pos (20U)
14436#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
14437#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
14438#define RCC_APB1ENR_I2C1EN_Pos (21U)
14439#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
14440#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
14441#define RCC_APB1ENR_I2C2EN_Pos (22U)
14442#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
14443#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
14444#define RCC_APB1ENR_I2C3EN_Pos (23U)
14445#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
14446#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
14447#define RCC_APB1ENR_CAN1EN_Pos (25U)
14448#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
14449#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
14450#define RCC_APB1ENR_CAN2EN_Pos (26U)
14451#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
14452#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
14453#define RCC_APB1ENR_PWREN_Pos (28U)
14454#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
14455#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
14456#define RCC_APB1ENR_DACEN_Pos (29U)
14457#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
14458#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
14459#define RCC_APB1ENR_UART7EN_Pos (30U)
14460#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos)
14461#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
14462#define RCC_APB1ENR_UART8EN_Pos (31U)
14463#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos)
14464#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
14465
14466/******************** Bit definition for RCC_APB2ENR register ***************/
14467#define RCC_APB2ENR_TIM1EN_Pos (0U)
14468#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
14469#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
14470#define RCC_APB2ENR_TIM8EN_Pos (1U)
14471#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
14472#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
14473#define RCC_APB2ENR_USART1EN_Pos (4U)
14474#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
14475#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
14476#define RCC_APB2ENR_USART6EN_Pos (5U)
14477#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
14478#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
14479#define RCC_APB2ENR_ADC1EN_Pos (8U)
14480#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
14481#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
14482#define RCC_APB2ENR_ADC2EN_Pos (9U)
14483#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
14484#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
14485#define RCC_APB2ENR_ADC3EN_Pos (10U)
14486#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
14487#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
14488#define RCC_APB2ENR_SDIOEN_Pos (11U)
14489#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
14490#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
14491#define RCC_APB2ENR_SPI1EN_Pos (12U)
14492#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
14493#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
14494#define RCC_APB2ENR_SPI4EN_Pos (13U)
14495#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
14496#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
14497#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
14498#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
14499#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
14500#define RCC_APB2ENR_TIM9EN_Pos (16U)
14501#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
14502#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
14503#define RCC_APB2ENR_TIM10EN_Pos (17U)
14504#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
14505#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
14506#define RCC_APB2ENR_TIM11EN_Pos (18U)
14507#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
14508#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
14509#define RCC_APB2ENR_SPI5EN_Pos (20U)
14510#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
14511#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
14512#define RCC_APB2ENR_SPI6EN_Pos (21U)
14513#define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos)
14514#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
14515#define RCC_APB2ENR_SAI1EN_Pos (22U)
14516#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
14517#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
14518#define RCC_APB2ENR_LTDCEN_Pos (26U)
14519#define RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos)
14520#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
14521#define RCC_APB2ENR_DSIEN_Pos (27U)
14522#define RCC_APB2ENR_DSIEN_Msk (0x1UL << RCC_APB2ENR_DSIEN_Pos)
14523#define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk
14524
14525/******************** Bit definition for RCC_AHB1LPENR register *************/
14526#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
14527#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
14528#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
14529#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
14530#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
14531#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
14532#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
14533#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
14534#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
14535#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
14536#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
14537#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
14538#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
14539#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
14540#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
14541#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
14542#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
14543#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
14544#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
14545#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
14546#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
14547#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
14548#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
14549#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
14550#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
14551#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
14552#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
14553#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
14554#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos)
14555#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
14556#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
14557#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos)
14558#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
14559#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
14560#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
14561#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
14562#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
14563#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
14564#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
14565#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
14566#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
14567#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
14568#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
14569#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
14570#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
14571#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
14572#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
14573#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
14574#define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
14575#define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM3LPEN_Pos)
14576#define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
14577#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
14578#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
14579#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
14580#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
14581#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
14582#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
14583#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
14584#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos)
14585#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
14586
14587#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
14588#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
14589#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
14590#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
14591#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
14592#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
14593#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
14594#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
14595#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
14596#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
14597#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
14598#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
14599#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
14600#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
14601#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
14602#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
14603#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
14604#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
14605
14606/******************** Bit definition for RCC_AHB2LPENR register *************/
14607#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
14608#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
14609#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
14610#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
14611#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos)
14612#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
14613#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
14614#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)
14615#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
14616#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
14617#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
14618#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
14619#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
14620#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
14621#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
14622
14623/******************** Bit definition for RCC_AHB3LPENR register *************/
14624#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
14625#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
14626#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
14627#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
14628#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
14629#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
14630
14631/******************** Bit definition for RCC_APB1LPENR register *************/
14632#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
14633#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
14634#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
14635#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
14636#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
14637#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
14638#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
14639#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
14640#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
14641#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
14642#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
14643#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
14644#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
14645#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
14646#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
14647#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
14648#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
14649#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
14650#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
14651#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
14652#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
14653#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
14654#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
14655#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
14656#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
14657#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
14658#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
14659#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
14660#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
14661#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
14662#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
14663#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
14664#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
14665#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
14666#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
14667#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
14668#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
14669#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
14670#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
14671#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
14672#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
14673#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
14674#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
14675#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
14676#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
14677#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
14678#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
14679#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
14680#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
14681#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
14682#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
14683#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
14684#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
14685#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
14686#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
14687#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
14688#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
14689#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
14690#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
14691#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
14692#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
14693#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
14694#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
14695#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
14696#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
14697#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
14698#define RCC_APB1LPENR_DACLPEN_Pos (29U)
14699#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
14700#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
14701#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
14702#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos)
14703#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
14704#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
14705#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos)
14706#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
14707
14708/******************** Bit definition for RCC_APB2LPENR register *************/
14709#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
14710#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
14711#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
14712#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
14713#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
14714#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
14715#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
14716#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
14717#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
14718#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
14719#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
14720#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
14721#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
14722#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
14723#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
14724#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
14725#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
14726#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
14727#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
14728#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
14729#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
14730#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
14731#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
14732#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
14733#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
14734#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
14735#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
14736#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
14737#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
14738#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
14739#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
14740#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
14741#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
14742#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
14743#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
14744#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
14745#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
14746#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
14747#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
14748#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
14749#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
14750#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
14751#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
14752#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
14753#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
14754#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
14755#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos)
14756#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
14757#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
14758#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
14759#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
14760#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
14761#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos)
14762#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
14763#define RCC_APB2LPENR_DSILPEN_Pos (27U)
14764#define RCC_APB2LPENR_DSILPEN_Msk (0x1UL << RCC_APB2LPENR_DSILPEN_Pos)
14765#define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk
14766
14767/******************** Bit definition for RCC_BDCR register ******************/
14768#define RCC_BDCR_LSEON_Pos (0U)
14769#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
14770#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
14771#define RCC_BDCR_LSERDY_Pos (1U)
14772#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
14773#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
14774#define RCC_BDCR_LSEBYP_Pos (2U)
14775#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
14776#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
14777#define RCC_BDCR_LSEMOD_Pos (3U)
14778#define RCC_BDCR_LSEMOD_Msk (0x1UL << RCC_BDCR_LSEMOD_Pos)
14779#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
14780
14781#define RCC_BDCR_RTCSEL_Pos (8U)
14782#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
14783#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
14784#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
14785#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
14787#define RCC_BDCR_RTCEN_Pos (15U)
14788#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
14789#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
14790#define RCC_BDCR_BDRST_Pos (16U)
14791#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
14792#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
14793
14794/******************** Bit definition for RCC_CSR register *******************/
14795#define RCC_CSR_LSION_Pos (0U)
14796#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
14797#define RCC_CSR_LSION RCC_CSR_LSION_Msk
14798#define RCC_CSR_LSIRDY_Pos (1U)
14799#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
14800#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
14801#define RCC_CSR_RMVF_Pos (24U)
14802#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
14803#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
14804#define RCC_CSR_BORRSTF_Pos (25U)
14805#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
14806#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
14807#define RCC_CSR_PINRSTF_Pos (26U)
14808#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
14809#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
14810#define RCC_CSR_PORRSTF_Pos (27U)
14811#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
14812#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
14813#define RCC_CSR_SFTRSTF_Pos (28U)
14814#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
14815#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
14816#define RCC_CSR_IWDGRSTF_Pos (29U)
14817#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
14818#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
14819#define RCC_CSR_WWDGRSTF_Pos (30U)
14820#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
14821#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
14822#define RCC_CSR_LPWRRSTF_Pos (31U)
14823#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
14824#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
14825/* Legacy defines */
14826#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
14827#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
14828
14829/******************** Bit definition for RCC_SSCGR register *****************/
14830#define RCC_SSCGR_MODPER_Pos (0U)
14831#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
14832#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
14833#define RCC_SSCGR_INCSTEP_Pos (13U)
14834#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
14835#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
14836#define RCC_SSCGR_SPREADSEL_Pos (30U)
14837#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
14838#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
14839#define RCC_SSCGR_SSCGEN_Pos (31U)
14840#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
14841#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
14842
14843/******************** Bit definition for RCC_PLLI2SCFGR register ************/
14844#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
14845#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14846#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
14847#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14848#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14849#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14850#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14851#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14852#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14853#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14854#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14855#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14857#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
14858#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
14859#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
14860#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
14861#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
14862#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
14863#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
14864#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
14865#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
14866#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
14867#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
14868#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
14869#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
14871/******************** Bit definition for RCC_PLLSAICFGR register ************/
14872#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
14873#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14874#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
14875#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14876#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14877#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14878#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14879#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14880#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14881#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14882#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14883#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14885#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
14886#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
14887#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
14888#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
14889#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
14891#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
14892#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
14893#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
14894#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
14895#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
14896#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
14897#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
14899#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
14900#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
14901#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
14902#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
14903#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
14904#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
14906/******************** Bit definition for RCC_DCKCFGR register ***************/
14907#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
14908#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14909#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
14910#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14911#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14912#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14913#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14914#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14916#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
14917#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14918#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
14919#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14920#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14921#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14922#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14923#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14924#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
14925#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
14926#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
14927#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
14928#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
14930#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
14931#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)
14932#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
14933#define RCC_DCKCFGR_SAI1ASRC_0 (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)
14934#define RCC_DCKCFGR_SAI1ASRC_1 (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)
14935#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
14936#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)
14937#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
14938#define RCC_DCKCFGR_SAI1BSRC_0 (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)
14939#define RCC_DCKCFGR_SAI1BSRC_1 (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)
14940#define RCC_DCKCFGR_TIMPRE_Pos (24U)
14941#define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)
14942#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
14943#define RCC_DCKCFGR_CK48MSEL_Pos (27U)
14944#define RCC_DCKCFGR_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR_CK48MSEL_Pos)
14945#define RCC_DCKCFGR_CK48MSEL RCC_DCKCFGR_CK48MSEL_Msk
14946#define RCC_DCKCFGR_SDIOSEL_Pos (28U)
14947#define RCC_DCKCFGR_SDIOSEL_Msk (0x1UL << RCC_DCKCFGR_SDIOSEL_Pos)
14948#define RCC_DCKCFGR_SDIOSEL RCC_DCKCFGR_SDIOSEL_Msk
14949#define RCC_DCKCFGR_DSISEL_Pos (29U)
14950#define RCC_DCKCFGR_DSISEL_Msk (0x1UL << RCC_DCKCFGR_DSISEL_Pos)
14951#define RCC_DCKCFGR_DSISEL RCC_DCKCFGR_DSISEL_Msk
14952
14953
14954/******************************************************************************/
14955/* */
14956/* RNG */
14957/* */
14958/******************************************************************************/
14959/******************** Bits definition for RNG_CR register *******************/
14960#define RNG_CR_RNGEN_Pos (2U)
14961#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
14962#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
14963#define RNG_CR_IE_Pos (3U)
14964#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
14965#define RNG_CR_IE RNG_CR_IE_Msk
14966
14967/******************** Bits definition for RNG_SR register *******************/
14968#define RNG_SR_DRDY_Pos (0U)
14969#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
14970#define RNG_SR_DRDY RNG_SR_DRDY_Msk
14971#define RNG_SR_CECS_Pos (1U)
14972#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
14973#define RNG_SR_CECS RNG_SR_CECS_Msk
14974#define RNG_SR_SECS_Pos (2U)
14975#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
14976#define RNG_SR_SECS RNG_SR_SECS_Msk
14977#define RNG_SR_CEIS_Pos (5U)
14978#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
14979#define RNG_SR_CEIS RNG_SR_CEIS_Msk
14980#define RNG_SR_SEIS_Pos (6U)
14981#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
14982#define RNG_SR_SEIS RNG_SR_SEIS_Msk
14983
14984/******************************************************************************/
14985/* */
14986/* Real-Time Clock (RTC) */
14987/* */
14988/******************************************************************************/
14989/*
14990 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14991 */
14992#define RTC_TAMPER2_SUPPORT
14993#define RTC_AF2_SUPPORT
14994/******************** Bits definition for RTC_TR register *******************/
14995#define RTC_TR_PM_Pos (22U)
14996#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
14997#define RTC_TR_PM RTC_TR_PM_Msk
14998#define RTC_TR_HT_Pos (20U)
14999#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
15000#define RTC_TR_HT RTC_TR_HT_Msk
15001#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
15002#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
15003#define RTC_TR_HU_Pos (16U)
15004#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
15005#define RTC_TR_HU RTC_TR_HU_Msk
15006#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
15007#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
15008#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
15009#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
15010#define RTC_TR_MNT_Pos (12U)
15011#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
15012#define RTC_TR_MNT RTC_TR_MNT_Msk
15013#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
15014#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
15015#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
15016#define RTC_TR_MNU_Pos (8U)
15017#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
15018#define RTC_TR_MNU RTC_TR_MNU_Msk
15019#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
15020#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
15021#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
15022#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
15023#define RTC_TR_ST_Pos (4U)
15024#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
15025#define RTC_TR_ST RTC_TR_ST_Msk
15026#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
15027#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
15028#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
15029#define RTC_TR_SU_Pos (0U)
15030#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
15031#define RTC_TR_SU RTC_TR_SU_Msk
15032#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
15033#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
15034#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
15035#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
15037/******************** Bits definition for RTC_DR register *******************/
15038#define RTC_DR_YT_Pos (20U)
15039#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
15040#define RTC_DR_YT RTC_DR_YT_Msk
15041#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
15042#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
15043#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
15044#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
15045#define RTC_DR_YU_Pos (16U)
15046#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
15047#define RTC_DR_YU RTC_DR_YU_Msk
15048#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
15049#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
15050#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
15051#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
15052#define RTC_DR_WDU_Pos (13U)
15053#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
15054#define RTC_DR_WDU RTC_DR_WDU_Msk
15055#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
15056#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
15057#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
15058#define RTC_DR_MT_Pos (12U)
15059#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
15060#define RTC_DR_MT RTC_DR_MT_Msk
15061#define RTC_DR_MU_Pos (8U)
15062#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
15063#define RTC_DR_MU RTC_DR_MU_Msk
15064#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
15065#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
15066#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
15067#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
15068#define RTC_DR_DT_Pos (4U)
15069#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
15070#define RTC_DR_DT RTC_DR_DT_Msk
15071#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
15072#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
15073#define RTC_DR_DU_Pos (0U)
15074#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
15075#define RTC_DR_DU RTC_DR_DU_Msk
15076#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
15077#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
15078#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
15079#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
15081/******************** Bits definition for RTC_CR register *******************/
15082#define RTC_CR_COE_Pos (23U)
15083#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
15084#define RTC_CR_COE RTC_CR_COE_Msk
15085#define RTC_CR_OSEL_Pos (21U)
15086#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
15087#define RTC_CR_OSEL RTC_CR_OSEL_Msk
15088#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
15089#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
15090#define RTC_CR_POL_Pos (20U)
15091#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
15092#define RTC_CR_POL RTC_CR_POL_Msk
15093#define RTC_CR_COSEL_Pos (19U)
15094#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
15095#define RTC_CR_COSEL RTC_CR_COSEL_Msk
15096#define RTC_CR_BKP_Pos (18U)
15097#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
15098#define RTC_CR_BKP RTC_CR_BKP_Msk
15099#define RTC_CR_SUB1H_Pos (17U)
15100#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
15101#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
15102#define RTC_CR_ADD1H_Pos (16U)
15103#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
15104#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
15105#define RTC_CR_TSIE_Pos (15U)
15106#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
15107#define RTC_CR_TSIE RTC_CR_TSIE_Msk
15108#define RTC_CR_WUTIE_Pos (14U)
15109#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
15110#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
15111#define RTC_CR_ALRBIE_Pos (13U)
15112#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
15113#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
15114#define RTC_CR_ALRAIE_Pos (12U)
15115#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
15116#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
15117#define RTC_CR_TSE_Pos (11U)
15118#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
15119#define RTC_CR_TSE RTC_CR_TSE_Msk
15120#define RTC_CR_WUTE_Pos (10U)
15121#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
15122#define RTC_CR_WUTE RTC_CR_WUTE_Msk
15123#define RTC_CR_ALRBE_Pos (9U)
15124#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
15125#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
15126#define RTC_CR_ALRAE_Pos (8U)
15127#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
15128#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
15129#define RTC_CR_DCE_Pos (7U)
15130#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
15131#define RTC_CR_DCE RTC_CR_DCE_Msk
15132#define RTC_CR_FMT_Pos (6U)
15133#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
15134#define RTC_CR_FMT RTC_CR_FMT_Msk
15135#define RTC_CR_BYPSHAD_Pos (5U)
15136#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
15137#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
15138#define RTC_CR_REFCKON_Pos (4U)
15139#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
15140#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
15141#define RTC_CR_TSEDGE_Pos (3U)
15142#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
15143#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
15144#define RTC_CR_WUCKSEL_Pos (0U)
15145#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
15146#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
15147#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
15148#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
15149#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
15151/* Legacy defines */
15152#define RTC_CR_BCK RTC_CR_BKP
15153
15154/******************** Bits definition for RTC_ISR register ******************/
15155#define RTC_ISR_RECALPF_Pos (16U)
15156#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
15157#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
15158#define RTC_ISR_TAMP1F_Pos (13U)
15159#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
15160#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
15161#define RTC_ISR_TAMP2F_Pos (14U)
15162#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
15163#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
15164#define RTC_ISR_TSOVF_Pos (12U)
15165#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
15166#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
15167#define RTC_ISR_TSF_Pos (11U)
15168#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
15169#define RTC_ISR_TSF RTC_ISR_TSF_Msk
15170#define RTC_ISR_WUTF_Pos (10U)
15171#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
15172#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
15173#define RTC_ISR_ALRBF_Pos (9U)
15174#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
15175#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
15176#define RTC_ISR_ALRAF_Pos (8U)
15177#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
15178#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
15179#define RTC_ISR_INIT_Pos (7U)
15180#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
15181#define RTC_ISR_INIT RTC_ISR_INIT_Msk
15182#define RTC_ISR_INITF_Pos (6U)
15183#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
15184#define RTC_ISR_INITF RTC_ISR_INITF_Msk
15185#define RTC_ISR_RSF_Pos (5U)
15186#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
15187#define RTC_ISR_RSF RTC_ISR_RSF_Msk
15188#define RTC_ISR_INITS_Pos (4U)
15189#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
15190#define RTC_ISR_INITS RTC_ISR_INITS_Msk
15191#define RTC_ISR_SHPF_Pos (3U)
15192#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
15193#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
15194#define RTC_ISR_WUTWF_Pos (2U)
15195#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
15196#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
15197#define RTC_ISR_ALRBWF_Pos (1U)
15198#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
15199#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
15200#define RTC_ISR_ALRAWF_Pos (0U)
15201#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
15202#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
15203
15204/******************** Bits definition for RTC_PRER register *****************/
15205#define RTC_PRER_PREDIV_A_Pos (16U)
15206#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
15207#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
15208#define RTC_PRER_PREDIV_S_Pos (0U)
15209#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
15210#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
15211
15212/******************** Bits definition for RTC_WUTR register *****************/
15213#define RTC_WUTR_WUT_Pos (0U)
15214#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
15215#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
15216
15217/******************** Bits definition for RTC_CALIBR register ***************/
15218#define RTC_CALIBR_DCS_Pos (7U)
15219#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
15220#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
15221#define RTC_CALIBR_DC_Pos (0U)
15222#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
15223#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
15224
15225/******************** Bits definition for RTC_ALRMAR register ***************/
15226#define RTC_ALRMAR_MSK4_Pos (31U)
15227#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
15228#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
15229#define RTC_ALRMAR_WDSEL_Pos (30U)
15230#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
15231#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
15232#define RTC_ALRMAR_DT_Pos (28U)
15233#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
15234#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
15235#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
15236#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
15237#define RTC_ALRMAR_DU_Pos (24U)
15238#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
15239#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
15240#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
15241#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
15242#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
15243#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
15244#define RTC_ALRMAR_MSK3_Pos (23U)
15245#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
15246#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
15247#define RTC_ALRMAR_PM_Pos (22U)
15248#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
15249#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
15250#define RTC_ALRMAR_HT_Pos (20U)
15251#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
15252#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
15253#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
15254#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
15255#define RTC_ALRMAR_HU_Pos (16U)
15256#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
15257#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
15258#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
15259#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
15260#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
15261#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
15262#define RTC_ALRMAR_MSK2_Pos (15U)
15263#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
15264#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
15265#define RTC_ALRMAR_MNT_Pos (12U)
15266#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
15267#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
15268#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
15269#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
15270#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
15271#define RTC_ALRMAR_MNU_Pos (8U)
15272#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
15273#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
15274#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
15275#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
15276#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
15277#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
15278#define RTC_ALRMAR_MSK1_Pos (7U)
15279#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
15280#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
15281#define RTC_ALRMAR_ST_Pos (4U)
15282#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
15283#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
15284#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
15285#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
15286#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
15287#define RTC_ALRMAR_SU_Pos (0U)
15288#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
15289#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
15290#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
15291#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
15292#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
15293#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
15295/******************** Bits definition for RTC_ALRMBR register ***************/
15296#define RTC_ALRMBR_MSK4_Pos (31U)
15297#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
15298#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
15299#define RTC_ALRMBR_WDSEL_Pos (30U)
15300#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
15301#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
15302#define RTC_ALRMBR_DT_Pos (28U)
15303#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
15304#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
15305#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
15306#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
15307#define RTC_ALRMBR_DU_Pos (24U)
15308#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
15309#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
15310#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
15311#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
15312#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
15313#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
15314#define RTC_ALRMBR_MSK3_Pos (23U)
15315#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
15316#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
15317#define RTC_ALRMBR_PM_Pos (22U)
15318#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
15319#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
15320#define RTC_ALRMBR_HT_Pos (20U)
15321#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
15322#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
15323#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
15324#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
15325#define RTC_ALRMBR_HU_Pos (16U)
15326#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
15327#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
15328#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
15329#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
15330#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
15331#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
15332#define RTC_ALRMBR_MSK2_Pos (15U)
15333#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
15334#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
15335#define RTC_ALRMBR_MNT_Pos (12U)
15336#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
15337#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
15338#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
15339#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
15340#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
15341#define RTC_ALRMBR_MNU_Pos (8U)
15342#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
15343#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
15344#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
15345#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
15346#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
15347#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
15348#define RTC_ALRMBR_MSK1_Pos (7U)
15349#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
15350#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
15351#define RTC_ALRMBR_ST_Pos (4U)
15352#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
15353#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
15354#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
15355#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
15356#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
15357#define RTC_ALRMBR_SU_Pos (0U)
15358#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
15359#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
15360#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
15361#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
15362#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
15363#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
15365/******************** Bits definition for RTC_WPR register ******************/
15366#define RTC_WPR_KEY_Pos (0U)
15367#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
15368#define RTC_WPR_KEY RTC_WPR_KEY_Msk
15369
15370/******************** Bits definition for RTC_SSR register ******************/
15371#define RTC_SSR_SS_Pos (0U)
15372#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
15373#define RTC_SSR_SS RTC_SSR_SS_Msk
15374
15375/******************** Bits definition for RTC_SHIFTR register ***************/
15376#define RTC_SHIFTR_SUBFS_Pos (0U)
15377#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
15378#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
15379#define RTC_SHIFTR_ADD1S_Pos (31U)
15380#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
15381#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
15382
15383/******************** Bits definition for RTC_TSTR register *****************/
15384#define RTC_TSTR_PM_Pos (22U)
15385#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
15386#define RTC_TSTR_PM RTC_TSTR_PM_Msk
15387#define RTC_TSTR_HT_Pos (20U)
15388#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
15389#define RTC_TSTR_HT RTC_TSTR_HT_Msk
15390#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
15391#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
15392#define RTC_TSTR_HU_Pos (16U)
15393#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
15394#define RTC_TSTR_HU RTC_TSTR_HU_Msk
15395#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
15396#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
15397#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
15398#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
15399#define RTC_TSTR_MNT_Pos (12U)
15400#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
15401#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
15402#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
15403#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
15404#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
15405#define RTC_TSTR_MNU_Pos (8U)
15406#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
15407#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
15408#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
15409#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
15410#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
15411#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
15412#define RTC_TSTR_ST_Pos (4U)
15413#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
15414#define RTC_TSTR_ST RTC_TSTR_ST_Msk
15415#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
15416#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
15417#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
15418#define RTC_TSTR_SU_Pos (0U)
15419#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
15420#define RTC_TSTR_SU RTC_TSTR_SU_Msk
15421#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
15422#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
15423#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
15424#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
15426/******************** Bits definition for RTC_TSDR register *****************/
15427#define RTC_TSDR_WDU_Pos (13U)
15428#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
15429#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
15430#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
15431#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
15432#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
15433#define RTC_TSDR_MT_Pos (12U)
15434#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
15435#define RTC_TSDR_MT RTC_TSDR_MT_Msk
15436#define RTC_TSDR_MU_Pos (8U)
15437#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
15438#define RTC_TSDR_MU RTC_TSDR_MU_Msk
15439#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
15440#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
15441#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
15442#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
15443#define RTC_TSDR_DT_Pos (4U)
15444#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
15445#define RTC_TSDR_DT RTC_TSDR_DT_Msk
15446#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
15447#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
15448#define RTC_TSDR_DU_Pos (0U)
15449#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
15450#define RTC_TSDR_DU RTC_TSDR_DU_Msk
15451#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
15452#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
15453#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
15454#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
15456/******************** Bits definition for RTC_TSSSR register ****************/
15457#define RTC_TSSSR_SS_Pos (0U)
15458#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
15459#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
15460
15461/******************** Bits definition for RTC_CAL register *****************/
15462#define RTC_CALR_CALP_Pos (15U)
15463#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
15464#define RTC_CALR_CALP RTC_CALR_CALP_Msk
15465#define RTC_CALR_CALW8_Pos (14U)
15466#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
15467#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
15468#define RTC_CALR_CALW16_Pos (13U)
15469#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
15470#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
15471#define RTC_CALR_CALM_Pos (0U)
15472#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
15473#define RTC_CALR_CALM RTC_CALR_CALM_Msk
15474#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
15475#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
15476#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
15477#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
15478#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
15479#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
15480#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
15481#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
15482#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
15484/******************** Bits definition for RTC_TAFCR register ****************/
15485#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
15486#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
15487#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
15488#define RTC_TAFCR_TSINSEL_Pos (17U)
15489#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
15490#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
15491#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
15492#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
15493#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
15494#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
15495#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
15496#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
15497#define RTC_TAFCR_TAMPPRCH_Pos (13U)
15498#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
15499#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
15500#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
15501#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
15502#define RTC_TAFCR_TAMPFLT_Pos (11U)
15503#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
15504#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
15505#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
15506#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
15507#define RTC_TAFCR_TAMPFREQ_Pos (8U)
15508#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
15509#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
15510#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
15511#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
15512#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
15513#define RTC_TAFCR_TAMPTS_Pos (7U)
15514#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
15515#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
15516#define RTC_TAFCR_TAMP2TRG_Pos (4U)
15517#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
15518#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
15519#define RTC_TAFCR_TAMP2E_Pos (3U)
15520#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
15521#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
15522#define RTC_TAFCR_TAMPIE_Pos (2U)
15523#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
15524#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
15525#define RTC_TAFCR_TAMP1TRG_Pos (1U)
15526#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
15527#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
15528#define RTC_TAFCR_TAMP1E_Pos (0U)
15529#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
15530#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
15531
15532/* Legacy defines */
15533#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
15534
15535/******************** Bits definition for RTC_ALRMASSR register *************/
15536#define RTC_ALRMASSR_MASKSS_Pos (24U)
15537#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
15538#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
15539#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
15540#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
15541#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
15542#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
15543#define RTC_ALRMASSR_SS_Pos (0U)
15544#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
15545#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
15546
15547/******************** Bits definition for RTC_ALRMBSSR register *************/
15548#define RTC_ALRMBSSR_MASKSS_Pos (24U)
15549#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
15550#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
15551#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
15552#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
15553#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
15554#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
15555#define RTC_ALRMBSSR_SS_Pos (0U)
15556#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
15557#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
15558
15559/******************** Bits definition for RTC_BKP0R register ****************/
15560#define RTC_BKP0R_Pos (0U)
15561#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
15562#define RTC_BKP0R RTC_BKP0R_Msk
15563
15564/******************** Bits definition for RTC_BKP1R register ****************/
15565#define RTC_BKP1R_Pos (0U)
15566#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
15567#define RTC_BKP1R RTC_BKP1R_Msk
15568
15569/******************** Bits definition for RTC_BKP2R register ****************/
15570#define RTC_BKP2R_Pos (0U)
15571#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
15572#define RTC_BKP2R RTC_BKP2R_Msk
15573
15574/******************** Bits definition for RTC_BKP3R register ****************/
15575#define RTC_BKP3R_Pos (0U)
15576#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
15577#define RTC_BKP3R RTC_BKP3R_Msk
15578
15579/******************** Bits definition for RTC_BKP4R register ****************/
15580#define RTC_BKP4R_Pos (0U)
15581#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
15582#define RTC_BKP4R RTC_BKP4R_Msk
15583
15584/******************** Bits definition for RTC_BKP5R register ****************/
15585#define RTC_BKP5R_Pos (0U)
15586#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
15587#define RTC_BKP5R RTC_BKP5R_Msk
15588
15589/******************** Bits definition for RTC_BKP6R register ****************/
15590#define RTC_BKP6R_Pos (0U)
15591#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
15592#define RTC_BKP6R RTC_BKP6R_Msk
15593
15594/******************** Bits definition for RTC_BKP7R register ****************/
15595#define RTC_BKP7R_Pos (0U)
15596#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
15597#define RTC_BKP7R RTC_BKP7R_Msk
15598
15599/******************** Bits definition for RTC_BKP8R register ****************/
15600#define RTC_BKP8R_Pos (0U)
15601#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
15602#define RTC_BKP8R RTC_BKP8R_Msk
15603
15604/******************** Bits definition for RTC_BKP9R register ****************/
15605#define RTC_BKP9R_Pos (0U)
15606#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
15607#define RTC_BKP9R RTC_BKP9R_Msk
15608
15609/******************** Bits definition for RTC_BKP10R register ***************/
15610#define RTC_BKP10R_Pos (0U)
15611#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
15612#define RTC_BKP10R RTC_BKP10R_Msk
15613
15614/******************** Bits definition for RTC_BKP11R register ***************/
15615#define RTC_BKP11R_Pos (0U)
15616#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
15617#define RTC_BKP11R RTC_BKP11R_Msk
15618
15619/******************** Bits definition for RTC_BKP12R register ***************/
15620#define RTC_BKP12R_Pos (0U)
15621#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
15622#define RTC_BKP12R RTC_BKP12R_Msk
15623
15624/******************** Bits definition for RTC_BKP13R register ***************/
15625#define RTC_BKP13R_Pos (0U)
15626#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
15627#define RTC_BKP13R RTC_BKP13R_Msk
15628
15629/******************** Bits definition for RTC_BKP14R register ***************/
15630#define RTC_BKP14R_Pos (0U)
15631#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
15632#define RTC_BKP14R RTC_BKP14R_Msk
15633
15634/******************** Bits definition for RTC_BKP15R register ***************/
15635#define RTC_BKP15R_Pos (0U)
15636#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
15637#define RTC_BKP15R RTC_BKP15R_Msk
15638
15639/******************** Bits definition for RTC_BKP16R register ***************/
15640#define RTC_BKP16R_Pos (0U)
15641#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
15642#define RTC_BKP16R RTC_BKP16R_Msk
15643
15644/******************** Bits definition for RTC_BKP17R register ***************/
15645#define RTC_BKP17R_Pos (0U)
15646#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
15647#define RTC_BKP17R RTC_BKP17R_Msk
15648
15649/******************** Bits definition for RTC_BKP18R register ***************/
15650#define RTC_BKP18R_Pos (0U)
15651#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
15652#define RTC_BKP18R RTC_BKP18R_Msk
15653
15654/******************** Bits definition for RTC_BKP19R register ***************/
15655#define RTC_BKP19R_Pos (0U)
15656#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
15657#define RTC_BKP19R RTC_BKP19R_Msk
15658
15659/******************** Number of backup registers ******************************/
15660#define RTC_BKP_NUMBER 0x000000014U
15661
15662/******************************************************************************/
15663/* */
15664/* Serial Audio Interface */
15665/* */
15666/******************************************************************************/
15667/******************** Bit definition for SAI_GCR register *******************/
15668#define SAI_GCR_SYNCIN_Pos (0U)
15669#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
15670#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
15671#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
15672#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
15674#define SAI_GCR_SYNCOUT_Pos (4U)
15675#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
15676#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
15677#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
15678#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
15680/******************* Bit definition for SAI_xCR1 register *******************/
15681#define SAI_xCR1_MODE_Pos (0U)
15682#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
15683#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
15684#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
15685#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
15687#define SAI_xCR1_PRTCFG_Pos (2U)
15688#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
15689#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
15690#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
15691#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
15693#define SAI_xCR1_DS_Pos (5U)
15694#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
15695#define SAI_xCR1_DS SAI_xCR1_DS_Msk
15696#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
15697#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
15698#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
15700#define SAI_xCR1_LSBFIRST_Pos (8U)
15701#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
15702#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
15703#define SAI_xCR1_CKSTR_Pos (9U)
15704#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
15705#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
15707#define SAI_xCR1_SYNCEN_Pos (10U)
15708#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
15709#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
15710#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
15711#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
15713#define SAI_xCR1_MONO_Pos (12U)
15714#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
15715#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
15716#define SAI_xCR1_OUTDRIV_Pos (13U)
15717#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
15718#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
15719#define SAI_xCR1_SAIEN_Pos (16U)
15720#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
15721#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
15722#define SAI_xCR1_DMAEN_Pos (17U)
15723#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
15724#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
15725#define SAI_xCR1_NODIV_Pos (19U)
15726#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
15727#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
15729#define SAI_xCR1_MCKDIV_Pos (20U)
15730#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
15731#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
15732#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
15733#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
15734#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
15735#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
15737/******************* Bit definition for SAI_xCR2 register *******************/
15738#define SAI_xCR2_FTH_Pos (0U)
15739#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
15740#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
15741#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
15742#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
15743#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
15745#define SAI_xCR2_FFLUSH_Pos (3U)
15746#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
15747#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
15748#define SAI_xCR2_TRIS_Pos (4U)
15749#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
15750#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
15751#define SAI_xCR2_MUTE_Pos (5U)
15752#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
15753#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
15754#define SAI_xCR2_MUTEVAL_Pos (6U)
15755#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
15756#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
15758#define SAI_xCR2_MUTECNT_Pos (7U)
15759#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
15760#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
15761#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
15762#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
15763#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
15764#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
15765#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
15766#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
15768#define SAI_xCR2_CPL_Pos (13U)
15769#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
15770#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
15772#define SAI_xCR2_COMP_Pos (14U)
15773#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
15774#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
15775#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
15776#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
15778/****************** Bit definition for SAI_xFRCR register *******************/
15779#define SAI_xFRCR_FRL_Pos (0U)
15780#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
15781#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
15782#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
15783#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
15784#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
15785#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
15786#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
15787#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
15788#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
15789#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
15791#define SAI_xFRCR_FSALL_Pos (8U)
15792#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
15793#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
15794#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
15795#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
15796#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
15797#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
15798#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
15799#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
15800#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
15802#define SAI_xFRCR_FSDEF_Pos (16U)
15803#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
15804#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
15805#define SAI_xFRCR_FSPOL_Pos (17U)
15806#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
15807#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
15808#define SAI_xFRCR_FSOFF_Pos (18U)
15809#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
15810#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
15811/* Legacy defines */
15812#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
15813
15814/****************** Bit definition for SAI_xSLOTR register *******************/
15815#define SAI_xSLOTR_FBOFF_Pos (0U)
15816#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
15817#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
15818#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
15819#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
15820#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
15821#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
15822#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
15824#define SAI_xSLOTR_SLOTSZ_Pos (6U)
15825#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
15826#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
15827#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
15828#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
15830#define SAI_xSLOTR_NBSLOT_Pos (8U)
15831#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
15832#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
15833#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
15834#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
15835#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
15836#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
15838#define SAI_xSLOTR_SLOTEN_Pos (16U)
15839#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
15840#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
15842/******************* Bit definition for SAI_xIMR register *******************/
15843#define SAI_xIMR_OVRUDRIE_Pos (0U)
15844#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
15845#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
15846#define SAI_xIMR_MUTEDETIE_Pos (1U)
15847#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
15848#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
15849#define SAI_xIMR_WCKCFGIE_Pos (2U)
15850#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
15851#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
15852#define SAI_xIMR_FREQIE_Pos (3U)
15853#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
15854#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
15855#define SAI_xIMR_CNRDYIE_Pos (4U)
15856#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
15857#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
15858#define SAI_xIMR_AFSDETIE_Pos (5U)
15859#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
15860#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
15861#define SAI_xIMR_LFSDETIE_Pos (6U)
15862#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
15863#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
15865/******************** Bit definition for SAI_xSR register *******************/
15866#define SAI_xSR_OVRUDR_Pos (0U)
15867#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
15868#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
15869#define SAI_xSR_MUTEDET_Pos (1U)
15870#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
15871#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
15872#define SAI_xSR_WCKCFG_Pos (2U)
15873#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
15874#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
15875#define SAI_xSR_FREQ_Pos (3U)
15876#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
15877#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
15878#define SAI_xSR_CNRDY_Pos (4U)
15879#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
15880#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
15881#define SAI_xSR_AFSDET_Pos (5U)
15882#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
15883#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
15884#define SAI_xSR_LFSDET_Pos (6U)
15885#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
15886#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
15888#define SAI_xSR_FLVL_Pos (16U)
15889#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
15890#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
15891#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
15892#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
15893#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
15895/****************** Bit definition for SAI_xCLRFR register ******************/
15896#define SAI_xCLRFR_COVRUDR_Pos (0U)
15897#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
15898#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
15899#define SAI_xCLRFR_CMUTEDET_Pos (1U)
15900#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
15901#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
15902#define SAI_xCLRFR_CWCKCFG_Pos (2U)
15903#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
15904#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
15905#define SAI_xCLRFR_CFREQ_Pos (3U)
15906#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
15907#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
15908#define SAI_xCLRFR_CCNRDY_Pos (4U)
15909#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
15910#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
15911#define SAI_xCLRFR_CAFSDET_Pos (5U)
15912#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
15913#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
15914#define SAI_xCLRFR_CLFSDET_Pos (6U)
15915#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
15916#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
15918/****************** Bit definition for SAI_xDR register ******************/
15919#define SAI_xDR_DATA_Pos (0U)
15920#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
15921#define SAI_xDR_DATA SAI_xDR_DATA_Msk
15922
15923
15924/******************************************************************************/
15925/* */
15926/* SD host Interface */
15927/* */
15928/******************************************************************************/
15929/****************** Bit definition for SDIO_POWER register ******************/
15930#define SDIO_POWER_PWRCTRL_Pos (0U)
15931#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
15932#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
15933#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
15934#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
15936/****************** Bit definition for SDIO_CLKCR register ******************/
15937#define SDIO_CLKCR_CLKDIV_Pos (0U)
15938#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
15939#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
15940#define SDIO_CLKCR_CLKEN_Pos (8U)
15941#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
15942#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
15943#define SDIO_CLKCR_PWRSAV_Pos (9U)
15944#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
15945#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
15946#define SDIO_CLKCR_BYPASS_Pos (10U)
15947#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
15948#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
15950#define SDIO_CLKCR_WIDBUS_Pos (11U)
15951#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
15952#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
15953#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
15954#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
15956#define SDIO_CLKCR_NEGEDGE_Pos (13U)
15957#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
15958#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
15959#define SDIO_CLKCR_HWFC_EN_Pos (14U)
15960#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
15961#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
15963/******************* Bit definition for SDIO_ARG register *******************/
15964#define SDIO_ARG_CMDARG_Pos (0U)
15965#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
15966#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
15968/******************* Bit definition for SDIO_CMD register *******************/
15969#define SDIO_CMD_CMDINDEX_Pos (0U)
15970#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
15971#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
15973#define SDIO_CMD_WAITRESP_Pos (6U)
15974#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
15975#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
15976#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
15977#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
15979#define SDIO_CMD_WAITINT_Pos (8U)
15980#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
15981#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
15982#define SDIO_CMD_WAITPEND_Pos (9U)
15983#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
15984#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
15985#define SDIO_CMD_CPSMEN_Pos (10U)
15986#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
15987#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
15988#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
15989#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
15990#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
15992/***************** Bit definition for SDIO_RESPCMD register *****************/
15993#define SDIO_RESPCMD_RESPCMD_Pos (0U)
15994#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
15995#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
15997/****************** Bit definition for SDIO_RESP0 register ******************/
15998#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
15999#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
16000#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
16002/****************** Bit definition for SDIO_RESP1 register ******************/
16003#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
16004#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
16005#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
16007/****************** Bit definition for SDIO_RESP2 register ******************/
16008#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
16009#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
16010#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
16012/****************** Bit definition for SDIO_RESP3 register ******************/
16013#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
16014#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
16015#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
16017/****************** Bit definition for SDIO_RESP4 register ******************/
16018#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
16019#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
16020#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
16022/****************** Bit definition for SDIO_DTIMER register *****************/
16023#define SDIO_DTIMER_DATATIME_Pos (0U)
16024#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
16025#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
16027/****************** Bit definition for SDIO_DLEN register *******************/
16028#define SDIO_DLEN_DATALENGTH_Pos (0U)
16029#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
16030#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
16032/****************** Bit definition for SDIO_DCTRL register ******************/
16033#define SDIO_DCTRL_DTEN_Pos (0U)
16034#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
16035#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
16036#define SDIO_DCTRL_DTDIR_Pos (1U)
16037#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
16038#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
16039#define SDIO_DCTRL_DTMODE_Pos (2U)
16040#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
16041#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
16042#define SDIO_DCTRL_DMAEN_Pos (3U)
16043#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
16044#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
16046#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
16047#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
16048#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
16049#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
16050#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
16051#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
16052#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
16054#define SDIO_DCTRL_RWSTART_Pos (8U)
16055#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
16056#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
16057#define SDIO_DCTRL_RWSTOP_Pos (9U)
16058#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
16059#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
16060#define SDIO_DCTRL_RWMOD_Pos (10U)
16061#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
16062#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
16063#define SDIO_DCTRL_SDIOEN_Pos (11U)
16064#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
16065#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
16067/****************** Bit definition for SDIO_DCOUNT register *****************/
16068#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
16069#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
16070#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
16072/****************** Bit definition for SDIO_STA register ********************/
16073#define SDIO_STA_CCRCFAIL_Pos (0U)
16074#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
16075#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
16076#define SDIO_STA_DCRCFAIL_Pos (1U)
16077#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
16078#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
16079#define SDIO_STA_CTIMEOUT_Pos (2U)
16080#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
16081#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
16082#define SDIO_STA_DTIMEOUT_Pos (3U)
16083#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
16084#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
16085#define SDIO_STA_TXUNDERR_Pos (4U)
16086#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
16087#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
16088#define SDIO_STA_RXOVERR_Pos (5U)
16089#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
16090#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
16091#define SDIO_STA_CMDREND_Pos (6U)
16092#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
16093#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
16094#define SDIO_STA_CMDSENT_Pos (7U)
16095#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
16096#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
16097#define SDIO_STA_DATAEND_Pos (8U)
16098#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
16099#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
16100#define SDIO_STA_DBCKEND_Pos (10U)
16101#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
16102#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
16103#define SDIO_STA_CMDACT_Pos (11U)
16104#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
16105#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
16106#define SDIO_STA_TXACT_Pos (12U)
16107#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
16108#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
16109#define SDIO_STA_RXACT_Pos (13U)
16110#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
16111#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
16112#define SDIO_STA_TXFIFOHE_Pos (14U)
16113#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
16114#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
16115#define SDIO_STA_RXFIFOHF_Pos (15U)
16116#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
16117#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
16118#define SDIO_STA_TXFIFOF_Pos (16U)
16119#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
16120#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
16121#define SDIO_STA_RXFIFOF_Pos (17U)
16122#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
16123#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
16124#define SDIO_STA_TXFIFOE_Pos (18U)
16125#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
16126#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
16127#define SDIO_STA_RXFIFOE_Pos (19U)
16128#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
16129#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
16130#define SDIO_STA_TXDAVL_Pos (20U)
16131#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
16132#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
16133#define SDIO_STA_RXDAVL_Pos (21U)
16134#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
16135#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
16136#define SDIO_STA_SDIOIT_Pos (22U)
16137#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
16138#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
16140/******************* Bit definition for SDIO_ICR register *******************/
16141#define SDIO_ICR_CCRCFAILC_Pos (0U)
16142#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
16143#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
16144#define SDIO_ICR_DCRCFAILC_Pos (1U)
16145#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
16146#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
16147#define SDIO_ICR_CTIMEOUTC_Pos (2U)
16148#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
16149#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
16150#define SDIO_ICR_DTIMEOUTC_Pos (3U)
16151#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
16152#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
16153#define SDIO_ICR_TXUNDERRC_Pos (4U)
16154#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
16155#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
16156#define SDIO_ICR_RXOVERRC_Pos (5U)
16157#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
16158#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
16159#define SDIO_ICR_CMDRENDC_Pos (6U)
16160#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
16161#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
16162#define SDIO_ICR_CMDSENTC_Pos (7U)
16163#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
16164#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
16165#define SDIO_ICR_DATAENDC_Pos (8U)
16166#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
16167#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
16168#define SDIO_ICR_DBCKENDC_Pos (10U)
16169#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
16170#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
16171#define SDIO_ICR_SDIOITC_Pos (22U)
16172#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
16173#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
16175/****************** Bit definition for SDIO_MASK register *******************/
16176#define SDIO_MASK_CCRCFAILIE_Pos (0U)
16177#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
16178#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
16179#define SDIO_MASK_DCRCFAILIE_Pos (1U)
16180#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
16181#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
16182#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
16183#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
16184#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
16185#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
16186#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
16187#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
16188#define SDIO_MASK_TXUNDERRIE_Pos (4U)
16189#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
16190#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
16191#define SDIO_MASK_RXOVERRIE_Pos (5U)
16192#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
16193#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
16194#define SDIO_MASK_CMDRENDIE_Pos (6U)
16195#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
16196#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
16197#define SDIO_MASK_CMDSENTIE_Pos (7U)
16198#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
16199#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
16200#define SDIO_MASK_DATAENDIE_Pos (8U)
16201#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
16202#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
16203#define SDIO_MASK_DBCKENDIE_Pos (10U)
16204#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
16205#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
16206#define SDIO_MASK_CMDACTIE_Pos (11U)
16207#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
16208#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
16209#define SDIO_MASK_TXACTIE_Pos (12U)
16210#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
16211#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
16212#define SDIO_MASK_RXACTIE_Pos (13U)
16213#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
16214#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
16215#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
16216#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
16217#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
16218#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
16219#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
16220#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
16221#define SDIO_MASK_TXFIFOFIE_Pos (16U)
16222#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
16223#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
16224#define SDIO_MASK_RXFIFOFIE_Pos (17U)
16225#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
16226#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
16227#define SDIO_MASK_TXFIFOEIE_Pos (18U)
16228#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
16229#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
16230#define SDIO_MASK_RXFIFOEIE_Pos (19U)
16231#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
16232#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
16233#define SDIO_MASK_TXDAVLIE_Pos (20U)
16234#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
16235#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
16236#define SDIO_MASK_RXDAVLIE_Pos (21U)
16237#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
16238#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
16239#define SDIO_MASK_SDIOITIE_Pos (22U)
16240#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
16241#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
16243/***************** Bit definition for SDIO_FIFOCNT register *****************/
16244#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
16245#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
16246#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
16248/****************** Bit definition for SDIO_FIFO register *******************/
16249#define SDIO_FIFO_FIFODATA_Pos (0U)
16250#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
16251#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
16253/******************************************************************************/
16254/* */
16255/* Serial Peripheral Interface */
16256/* */
16257/******************************************************************************/
16258#define SPI_I2S_FULLDUPLEX_SUPPORT
16260/******************* Bit definition for SPI_CR1 register ********************/
16261#define SPI_CR1_CPHA_Pos (0U)
16262#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
16263#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
16264#define SPI_CR1_CPOL_Pos (1U)
16265#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
16266#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
16267#define SPI_CR1_MSTR_Pos (2U)
16268#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
16269#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
16271#define SPI_CR1_BR_Pos (3U)
16272#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
16273#define SPI_CR1_BR SPI_CR1_BR_Msk
16274#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
16275#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
16276#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
16278#define SPI_CR1_SPE_Pos (6U)
16279#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
16280#define SPI_CR1_SPE SPI_CR1_SPE_Msk
16281#define SPI_CR1_LSBFIRST_Pos (7U)
16282#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
16283#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
16284#define SPI_CR1_SSI_Pos (8U)
16285#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
16286#define SPI_CR1_SSI SPI_CR1_SSI_Msk
16287#define SPI_CR1_SSM_Pos (9U)
16288#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
16289#define SPI_CR1_SSM SPI_CR1_SSM_Msk
16290#define SPI_CR1_RXONLY_Pos (10U)
16291#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
16292#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
16293#define SPI_CR1_DFF_Pos (11U)
16294#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
16295#define SPI_CR1_DFF SPI_CR1_DFF_Msk
16296#define SPI_CR1_CRCNEXT_Pos (12U)
16297#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
16298#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
16299#define SPI_CR1_CRCEN_Pos (13U)
16300#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
16301#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
16302#define SPI_CR1_BIDIOE_Pos (14U)
16303#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
16304#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
16305#define SPI_CR1_BIDIMODE_Pos (15U)
16306#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
16307#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
16309/******************* Bit definition for SPI_CR2 register ********************/
16310#define SPI_CR2_RXDMAEN_Pos (0U)
16311#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
16312#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
16313#define SPI_CR2_TXDMAEN_Pos (1U)
16314#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
16315#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
16316#define SPI_CR2_SSOE_Pos (2U)
16317#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
16318#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
16319#define SPI_CR2_FRF_Pos (4U)
16320#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
16321#define SPI_CR2_FRF SPI_CR2_FRF_Msk
16322#define SPI_CR2_ERRIE_Pos (5U)
16323#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
16324#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
16325#define SPI_CR2_RXNEIE_Pos (6U)
16326#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
16327#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
16328#define SPI_CR2_TXEIE_Pos (7U)
16329#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
16330#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
16332/******************** Bit definition for SPI_SR register ********************/
16333#define SPI_SR_RXNE_Pos (0U)
16334#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
16335#define SPI_SR_RXNE SPI_SR_RXNE_Msk
16336#define SPI_SR_TXE_Pos (1U)
16337#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
16338#define SPI_SR_TXE SPI_SR_TXE_Msk
16339#define SPI_SR_CHSIDE_Pos (2U)
16340#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
16341#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
16342#define SPI_SR_UDR_Pos (3U)
16343#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
16344#define SPI_SR_UDR SPI_SR_UDR_Msk
16345#define SPI_SR_CRCERR_Pos (4U)
16346#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
16347#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
16348#define SPI_SR_MODF_Pos (5U)
16349#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
16350#define SPI_SR_MODF SPI_SR_MODF_Msk
16351#define SPI_SR_OVR_Pos (6U)
16352#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
16353#define SPI_SR_OVR SPI_SR_OVR_Msk
16354#define SPI_SR_BSY_Pos (7U)
16355#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
16356#define SPI_SR_BSY SPI_SR_BSY_Msk
16357#define SPI_SR_FRE_Pos (8U)
16358#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
16359#define SPI_SR_FRE SPI_SR_FRE_Msk
16361/******************** Bit definition for SPI_DR register ********************/
16362#define SPI_DR_DR_Pos (0U)
16363#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
16364#define SPI_DR_DR SPI_DR_DR_Msk
16366/******************* Bit definition for SPI_CRCPR register ******************/
16367#define SPI_CRCPR_CRCPOLY_Pos (0U)
16368#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
16369#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
16371/****************** Bit definition for SPI_RXCRCR register ******************/
16372#define SPI_RXCRCR_RXCRC_Pos (0U)
16373#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
16374#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
16376/****************** Bit definition for SPI_TXCRCR register ******************/
16377#define SPI_TXCRCR_TXCRC_Pos (0U)
16378#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
16379#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
16381/****************** Bit definition for SPI_I2SCFGR register *****************/
16382#define SPI_I2SCFGR_CHLEN_Pos (0U)
16383#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
16384#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
16386#define SPI_I2SCFGR_DATLEN_Pos (1U)
16387#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
16388#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
16389#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
16390#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
16392#define SPI_I2SCFGR_CKPOL_Pos (3U)
16393#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
16394#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
16396#define SPI_I2SCFGR_I2SSTD_Pos (4U)
16397#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
16398#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
16399#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
16400#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
16402#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
16403#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
16404#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
16406#define SPI_I2SCFGR_I2SCFG_Pos (8U)
16407#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
16408#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
16409#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
16410#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
16412#define SPI_I2SCFGR_I2SE_Pos (10U)
16413#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
16414#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
16415#define SPI_I2SCFGR_I2SMOD_Pos (11U)
16416#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
16417#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
16418#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
16419#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
16420#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
16422/****************** Bit definition for SPI_I2SPR register *******************/
16423#define SPI_I2SPR_I2SDIV_Pos (0U)
16424#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
16425#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
16426#define SPI_I2SPR_ODD_Pos (8U)
16427#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
16428#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
16429#define SPI_I2SPR_MCKOE_Pos (9U)
16430#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
16431#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
16433/******************************************************************************/
16434/* */
16435/* SYSCFG */
16436/* */
16437/******************************************************************************/
16438/****************** Bit definition for SYSCFG_MEMRMP register ***************/
16439#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
16440#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
16441#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
16442#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
16443#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
16444#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
16445#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
16446#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos)
16447#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk
16448#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
16449#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
16450#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk
16451#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
16452/* Legacy Defines */
16453#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
16454/****************** Bit definition for SYSCFG_PMC register ******************/
16455#define SYSCFG_PMC_ADCxDC2_Pos (16U)
16456#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)
16457#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk
16458#define SYSCFG_PMC_ADC1DC2_Pos (16U)
16459#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
16460#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
16461#define SYSCFG_PMC_ADC2DC2_Pos (17U)
16462#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)
16463#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk
16464#define SYSCFG_PMC_ADC3DC2_Pos (18U)
16465#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)
16466#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk
16467#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
16468#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
16469#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
16471/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
16472#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
16473#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
16474#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
16475#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
16476#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
16477#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
16478#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
16479#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
16480#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
16481#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
16482#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
16483#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
16487#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
16488#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
16489#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
16490#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
16491#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
16492#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
16493#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
16494#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
16495#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
16496#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
16497#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
16502#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
16503#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
16504#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
16505#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
16506#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
16507#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
16508#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
16509#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
16510#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
16511#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
16512#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
16517#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
16518#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
16519#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
16520#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
16521#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
16522#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
16523#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
16524#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
16525#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
16526#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
16527#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
16532#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
16533#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
16534#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
16535#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
16536#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
16537#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
16538#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
16539#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
16540#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
16541#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
16542#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
16544/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
16545#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
16546#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
16547#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
16548#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
16549#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
16550#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
16551#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
16552#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
16553#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
16554#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
16555#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
16556#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
16561#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
16562#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
16563#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
16564#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
16565#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
16566#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
16567#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
16568#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
16569#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
16570#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
16571#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
16576#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
16577#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
16578#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
16579#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
16580#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
16581#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
16582#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
16583#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
16584#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
16585#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
16586#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
16591#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
16592#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
16593#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
16594#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
16595#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
16596#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
16597#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
16598#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
16599#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
16600#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
16601#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
16606#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
16607#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
16608#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
16609#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
16610#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
16611#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
16612#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
16613#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
16614#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
16615#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
16616#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
16618/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
16619#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
16620#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
16621#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
16622#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
16623#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
16624#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
16625#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
16626#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
16627#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
16628#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
16629#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
16630#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
16635#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
16636#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
16637#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
16638#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
16639#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
16640#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
16641#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
16642#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
16643#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
16644#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
16649#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
16650#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
16651#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
16652#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
16653#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
16654#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
16655#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
16656#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
16657#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
16658#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
16663#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
16664#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
16665#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
16666#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
16667#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
16668#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
16669#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
16670#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
16671#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
16672#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
16677#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
16678#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
16679#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
16680#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
16681#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
16682#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
16683#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
16684#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
16685#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
16686#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
16689/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
16690#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
16691#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
16692#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
16693#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
16694#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
16695#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
16696#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
16697#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
16698#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
16699#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
16700#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
16701#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
16706#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
16707#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
16708#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
16709#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
16710#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
16711#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
16712#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
16713#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
16714#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
16715#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
16720#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
16721#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
16722#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
16723#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
16724#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
16725#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
16726#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
16727#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
16728#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
16729#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
16734#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
16735#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
16736#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
16737#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
16738#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
16739#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
16740#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
16741#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
16742#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
16743#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
16748#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
16749#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
16750#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
16751#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
16752#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
16753#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
16754#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
16755#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
16756#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
16757#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
16759/****************** Bit definition for SYSCFG_CMPCR register ****************/
16760#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
16761#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
16762#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
16763#define SYSCFG_CMPCR_READY_Pos (8U)
16764#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
16765#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
16767/******************************************************************************/
16768/* */
16769/* TIM */
16770/* */
16771/******************************************************************************/
16772/******************* Bit definition for TIM_CR1 register ********************/
16773#define TIM_CR1_CEN_Pos (0U)
16774#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
16775#define TIM_CR1_CEN TIM_CR1_CEN_Msk
16776#define TIM_CR1_UDIS_Pos (1U)
16777#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
16778#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
16779#define TIM_CR1_URS_Pos (2U)
16780#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
16781#define TIM_CR1_URS TIM_CR1_URS_Msk
16782#define TIM_CR1_OPM_Pos (3U)
16783#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
16784#define TIM_CR1_OPM TIM_CR1_OPM_Msk
16785#define TIM_CR1_DIR_Pos (4U)
16786#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
16787#define TIM_CR1_DIR TIM_CR1_DIR_Msk
16789#define TIM_CR1_CMS_Pos (5U)
16790#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
16791#define TIM_CR1_CMS TIM_CR1_CMS_Msk
16792#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
16793#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
16795#define TIM_CR1_ARPE_Pos (7U)
16796#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
16797#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
16799#define TIM_CR1_CKD_Pos (8U)
16800#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
16801#define TIM_CR1_CKD TIM_CR1_CKD_Msk
16802#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
16803#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
16805/******************* Bit definition for TIM_CR2 register ********************/
16806#define TIM_CR2_CCPC_Pos (0U)
16807#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
16808#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
16809#define TIM_CR2_CCUS_Pos (2U)
16810#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
16811#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
16812#define TIM_CR2_CCDS_Pos (3U)
16813#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
16814#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
16816#define TIM_CR2_MMS_Pos (4U)
16817#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
16818#define TIM_CR2_MMS TIM_CR2_MMS_Msk
16819#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
16820#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
16821#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
16823#define TIM_CR2_TI1S_Pos (7U)
16824#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
16825#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
16826#define TIM_CR2_OIS1_Pos (8U)
16827#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
16828#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
16829#define TIM_CR2_OIS1N_Pos (9U)
16830#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
16831#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
16832#define TIM_CR2_OIS2_Pos (10U)
16833#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
16834#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
16835#define TIM_CR2_OIS2N_Pos (11U)
16836#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
16837#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
16838#define TIM_CR2_OIS3_Pos (12U)
16839#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
16840#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
16841#define TIM_CR2_OIS3N_Pos (13U)
16842#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
16843#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
16844#define TIM_CR2_OIS4_Pos (14U)
16845#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
16846#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
16848/******************* Bit definition for TIM_SMCR register *******************/
16849#define TIM_SMCR_SMS_Pos (0U)
16850#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
16851#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
16852#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
16853#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
16854#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
16856#define TIM_SMCR_TS_Pos (4U)
16857#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
16858#define TIM_SMCR_TS TIM_SMCR_TS_Msk
16859#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
16860#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
16861#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
16863#define TIM_SMCR_MSM_Pos (7U)
16864#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
16865#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
16867#define TIM_SMCR_ETF_Pos (8U)
16868#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
16869#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
16870#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
16871#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
16872#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
16873#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
16875#define TIM_SMCR_ETPS_Pos (12U)
16876#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
16877#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
16878#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
16879#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
16881#define TIM_SMCR_ECE_Pos (14U)
16882#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
16883#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
16884#define TIM_SMCR_ETP_Pos (15U)
16885#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
16886#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
16888/******************* Bit definition for TIM_DIER register *******************/
16889#define TIM_DIER_UIE_Pos (0U)
16890#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
16891#define TIM_DIER_UIE TIM_DIER_UIE_Msk
16892#define TIM_DIER_CC1IE_Pos (1U)
16893#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
16894#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
16895#define TIM_DIER_CC2IE_Pos (2U)
16896#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
16897#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
16898#define TIM_DIER_CC3IE_Pos (3U)
16899#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
16900#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
16901#define TIM_DIER_CC4IE_Pos (4U)
16902#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
16903#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
16904#define TIM_DIER_COMIE_Pos (5U)
16905#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
16906#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
16907#define TIM_DIER_TIE_Pos (6U)
16908#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
16909#define TIM_DIER_TIE TIM_DIER_TIE_Msk
16910#define TIM_DIER_BIE_Pos (7U)
16911#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
16912#define TIM_DIER_BIE TIM_DIER_BIE_Msk
16913#define TIM_DIER_UDE_Pos (8U)
16914#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
16915#define TIM_DIER_UDE TIM_DIER_UDE_Msk
16916#define TIM_DIER_CC1DE_Pos (9U)
16917#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
16918#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
16919#define TIM_DIER_CC2DE_Pos (10U)
16920#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
16921#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
16922#define TIM_DIER_CC3DE_Pos (11U)
16923#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
16924#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
16925#define TIM_DIER_CC4DE_Pos (12U)
16926#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
16927#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
16928#define TIM_DIER_COMDE_Pos (13U)
16929#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
16930#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
16931#define TIM_DIER_TDE_Pos (14U)
16932#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
16933#define TIM_DIER_TDE TIM_DIER_TDE_Msk
16935/******************** Bit definition for TIM_SR register ********************/
16936#define TIM_SR_UIF_Pos (0U)
16937#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
16938#define TIM_SR_UIF TIM_SR_UIF_Msk
16939#define TIM_SR_CC1IF_Pos (1U)
16940#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
16941#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
16942#define TIM_SR_CC2IF_Pos (2U)
16943#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
16944#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
16945#define TIM_SR_CC3IF_Pos (3U)
16946#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
16947#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
16948#define TIM_SR_CC4IF_Pos (4U)
16949#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
16950#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
16951#define TIM_SR_COMIF_Pos (5U)
16952#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
16953#define TIM_SR_COMIF TIM_SR_COMIF_Msk
16954#define TIM_SR_TIF_Pos (6U)
16955#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
16956#define TIM_SR_TIF TIM_SR_TIF_Msk
16957#define TIM_SR_BIF_Pos (7U)
16958#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
16959#define TIM_SR_BIF TIM_SR_BIF_Msk
16960#define TIM_SR_CC1OF_Pos (9U)
16961#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
16962#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
16963#define TIM_SR_CC2OF_Pos (10U)
16964#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
16965#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
16966#define TIM_SR_CC3OF_Pos (11U)
16967#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
16968#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
16969#define TIM_SR_CC4OF_Pos (12U)
16970#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
16971#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
16973/******************* Bit definition for TIM_EGR register ********************/
16974#define TIM_EGR_UG_Pos (0U)
16975#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
16976#define TIM_EGR_UG TIM_EGR_UG_Msk
16977#define TIM_EGR_CC1G_Pos (1U)
16978#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
16979#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
16980#define TIM_EGR_CC2G_Pos (2U)
16981#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
16982#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
16983#define TIM_EGR_CC3G_Pos (3U)
16984#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
16985#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
16986#define TIM_EGR_CC4G_Pos (4U)
16987#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
16988#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
16989#define TIM_EGR_COMG_Pos (5U)
16990#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
16991#define TIM_EGR_COMG TIM_EGR_COMG_Msk
16992#define TIM_EGR_TG_Pos (6U)
16993#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
16994#define TIM_EGR_TG TIM_EGR_TG_Msk
16995#define TIM_EGR_BG_Pos (7U)
16996#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
16997#define TIM_EGR_BG TIM_EGR_BG_Msk
16999/****************** Bit definition for TIM_CCMR1 register *******************/
17000#define TIM_CCMR1_CC1S_Pos (0U)
17001#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
17002#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
17003#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
17004#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
17006#define TIM_CCMR1_OC1FE_Pos (2U)
17007#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
17008#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
17009#define TIM_CCMR1_OC1PE_Pos (3U)
17010#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
17011#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
17013#define TIM_CCMR1_OC1M_Pos (4U)
17014#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
17015#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
17016#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
17017#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
17018#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
17020#define TIM_CCMR1_OC1CE_Pos (7U)
17021#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
17022#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
17024#define TIM_CCMR1_CC2S_Pos (8U)
17025#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
17026#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
17027#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
17028#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
17030#define TIM_CCMR1_OC2FE_Pos (10U)
17031#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
17032#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
17033#define TIM_CCMR1_OC2PE_Pos (11U)
17034#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
17035#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
17037#define TIM_CCMR1_OC2M_Pos (12U)
17038#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
17039#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
17040#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
17041#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
17042#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
17044#define TIM_CCMR1_OC2CE_Pos (15U)
17045#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
17046#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
17048/*----------------------------------------------------------------------------*/
17049
17050#define TIM_CCMR1_IC1PSC_Pos (2U)
17051#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
17052#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
17053#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
17054#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
17056#define TIM_CCMR1_IC1F_Pos (4U)
17057#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
17058#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
17059#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
17060#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
17061#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
17062#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
17064#define TIM_CCMR1_IC2PSC_Pos (10U)
17065#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
17066#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
17067#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
17068#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
17070#define TIM_CCMR1_IC2F_Pos (12U)
17071#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
17072#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
17073#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
17074#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
17075#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
17076#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
17078/****************** Bit definition for TIM_CCMR2 register *******************/
17079#define TIM_CCMR2_CC3S_Pos (0U)
17080#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
17081#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
17082#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
17083#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
17085#define TIM_CCMR2_OC3FE_Pos (2U)
17086#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
17087#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
17088#define TIM_CCMR2_OC3PE_Pos (3U)
17089#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
17090#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
17092#define TIM_CCMR2_OC3M_Pos (4U)
17093#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
17094#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
17095#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
17096#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
17097#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
17099#define TIM_CCMR2_OC3CE_Pos (7U)
17100#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
17101#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
17103#define TIM_CCMR2_CC4S_Pos (8U)
17104#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
17105#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
17106#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
17107#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
17109#define TIM_CCMR2_OC4FE_Pos (10U)
17110#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
17111#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
17112#define TIM_CCMR2_OC4PE_Pos (11U)
17113#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
17114#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
17116#define TIM_CCMR2_OC4M_Pos (12U)
17117#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
17118#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
17119#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
17120#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
17121#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
17123#define TIM_CCMR2_OC4CE_Pos (15U)
17124#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
17125#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
17127/*----------------------------------------------------------------------------*/
17128
17129#define TIM_CCMR2_IC3PSC_Pos (2U)
17130#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
17131#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
17132#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
17133#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
17135#define TIM_CCMR2_IC3F_Pos (4U)
17136#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
17137#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
17138#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
17139#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
17140#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
17141#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
17143#define TIM_CCMR2_IC4PSC_Pos (10U)
17144#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
17145#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
17146#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
17147#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
17149#define TIM_CCMR2_IC4F_Pos (12U)
17150#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
17151#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
17152#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
17153#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
17154#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
17155#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
17157/******************* Bit definition for TIM_CCER register *******************/
17158#define TIM_CCER_CC1E_Pos (0U)
17159#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
17160#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
17161#define TIM_CCER_CC1P_Pos (1U)
17162#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
17163#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
17164#define TIM_CCER_CC1NE_Pos (2U)
17165#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
17166#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
17167#define TIM_CCER_CC1NP_Pos (3U)
17168#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
17169#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
17170#define TIM_CCER_CC2E_Pos (4U)
17171#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
17172#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
17173#define TIM_CCER_CC2P_Pos (5U)
17174#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
17175#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
17176#define TIM_CCER_CC2NE_Pos (6U)
17177#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
17178#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
17179#define TIM_CCER_CC2NP_Pos (7U)
17180#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
17181#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
17182#define TIM_CCER_CC3E_Pos (8U)
17183#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
17184#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
17185#define TIM_CCER_CC3P_Pos (9U)
17186#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
17187#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
17188#define TIM_CCER_CC3NE_Pos (10U)
17189#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
17190#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
17191#define TIM_CCER_CC3NP_Pos (11U)
17192#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
17193#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
17194#define TIM_CCER_CC4E_Pos (12U)
17195#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
17196#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
17197#define TIM_CCER_CC4P_Pos (13U)
17198#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
17199#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
17200#define TIM_CCER_CC4NP_Pos (15U)
17201#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
17202#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
17204/******************* Bit definition for TIM_CNT register ********************/
17205#define TIM_CNT_CNT_Pos (0U)
17206#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
17207#define TIM_CNT_CNT TIM_CNT_CNT_Msk
17209/******************* Bit definition for TIM_PSC register ********************/
17210#define TIM_PSC_PSC_Pos (0U)
17211#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
17212#define TIM_PSC_PSC TIM_PSC_PSC_Msk
17214/******************* Bit definition for TIM_ARR register ********************/
17215#define TIM_ARR_ARR_Pos (0U)
17216#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
17217#define TIM_ARR_ARR TIM_ARR_ARR_Msk
17219/******************* Bit definition for TIM_RCR register ********************/
17220#define TIM_RCR_REP_Pos (0U)
17221#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
17222#define TIM_RCR_REP TIM_RCR_REP_Msk
17224/******************* Bit definition for TIM_CCR1 register *******************/
17225#define TIM_CCR1_CCR1_Pos (0U)
17226#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
17227#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
17229/******************* Bit definition for TIM_CCR2 register *******************/
17230#define TIM_CCR2_CCR2_Pos (0U)
17231#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
17232#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
17234/******************* Bit definition for TIM_CCR3 register *******************/
17235#define TIM_CCR3_CCR3_Pos (0U)
17236#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
17237#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
17239/******************* Bit definition for TIM_CCR4 register *******************/
17240#define TIM_CCR4_CCR4_Pos (0U)
17241#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
17242#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
17244/******************* Bit definition for TIM_BDTR register *******************/
17245#define TIM_BDTR_DTG_Pos (0U)
17246#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
17247#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
17248#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
17249#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
17250#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
17251#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
17252#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
17253#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
17254#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
17255#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
17257#define TIM_BDTR_LOCK_Pos (8U)
17258#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
17259#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
17260#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
17261#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
17263#define TIM_BDTR_OSSI_Pos (10U)
17264#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
17265#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
17266#define TIM_BDTR_OSSR_Pos (11U)
17267#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
17268#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
17269#define TIM_BDTR_BKE_Pos (12U)
17270#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
17271#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
17272#define TIM_BDTR_BKP_Pos (13U)
17273#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
17274#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
17275#define TIM_BDTR_AOE_Pos (14U)
17276#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
17277#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
17278#define TIM_BDTR_MOE_Pos (15U)
17279#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
17280#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
17282/******************* Bit definition for TIM_DCR register ********************/
17283#define TIM_DCR_DBA_Pos (0U)
17284#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
17285#define TIM_DCR_DBA TIM_DCR_DBA_Msk
17286#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
17287#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
17288#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
17289#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
17290#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
17292#define TIM_DCR_DBL_Pos (8U)
17293#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
17294#define TIM_DCR_DBL TIM_DCR_DBL_Msk
17295#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
17296#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
17297#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
17298#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
17299#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
17301/******************* Bit definition for TIM_DMAR register *******************/
17302#define TIM_DMAR_DMAB_Pos (0U)
17303#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
17304#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
17306/******************* Bit definition for TIM_OR register *********************/
17307#define TIM_OR_TI1_RMP_Pos (0U)
17308#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
17309#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
17310#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
17311#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
17313#define TIM_OR_TI4_RMP_Pos (6U)
17314#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
17315#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
17316#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
17317#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
17318#define TIM_OR_ITR1_RMP_Pos (10U)
17319#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
17320#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
17321#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
17322#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
17325/******************************************************************************/
17326/* */
17327/* Universal Synchronous Asynchronous Receiver Transmitter */
17328/* */
17329/******************************************************************************/
17330/******************* Bit definition for USART_SR register *******************/
17331#define USART_SR_PE_Pos (0U)
17332#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
17333#define USART_SR_PE USART_SR_PE_Msk
17334#define USART_SR_FE_Pos (1U)
17335#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
17336#define USART_SR_FE USART_SR_FE_Msk
17337#define USART_SR_NE_Pos (2U)
17338#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
17339#define USART_SR_NE USART_SR_NE_Msk
17340#define USART_SR_ORE_Pos (3U)
17341#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
17342#define USART_SR_ORE USART_SR_ORE_Msk
17343#define USART_SR_IDLE_Pos (4U)
17344#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
17345#define USART_SR_IDLE USART_SR_IDLE_Msk
17346#define USART_SR_RXNE_Pos (5U)
17347#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
17348#define USART_SR_RXNE USART_SR_RXNE_Msk
17349#define USART_SR_TC_Pos (6U)
17350#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
17351#define USART_SR_TC USART_SR_TC_Msk
17352#define USART_SR_TXE_Pos (7U)
17353#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
17354#define USART_SR_TXE USART_SR_TXE_Msk
17355#define USART_SR_LBD_Pos (8U)
17356#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
17357#define USART_SR_LBD USART_SR_LBD_Msk
17358#define USART_SR_CTS_Pos (9U)
17359#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
17360#define USART_SR_CTS USART_SR_CTS_Msk
17362/******************* Bit definition for USART_DR register *******************/
17363#define USART_DR_DR_Pos (0U)
17364#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
17365#define USART_DR_DR USART_DR_DR_Msk
17367/****************** Bit definition for USART_BRR register *******************/
17368#define USART_BRR_DIV_Fraction_Pos (0U)
17369#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
17370#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
17371#define USART_BRR_DIV_Mantissa_Pos (4U)
17372#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
17373#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
17375/****************** Bit definition for USART_CR1 register *******************/
17376#define USART_CR1_SBK_Pos (0U)
17377#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
17378#define USART_CR1_SBK USART_CR1_SBK_Msk
17379#define USART_CR1_RWU_Pos (1U)
17380#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
17381#define USART_CR1_RWU USART_CR1_RWU_Msk
17382#define USART_CR1_RE_Pos (2U)
17383#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
17384#define USART_CR1_RE USART_CR1_RE_Msk
17385#define USART_CR1_TE_Pos (3U)
17386#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
17387#define USART_CR1_TE USART_CR1_TE_Msk
17388#define USART_CR1_IDLEIE_Pos (4U)
17389#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
17390#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
17391#define USART_CR1_RXNEIE_Pos (5U)
17392#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
17393#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
17394#define USART_CR1_TCIE_Pos (6U)
17395#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
17396#define USART_CR1_TCIE USART_CR1_TCIE_Msk
17397#define USART_CR1_TXEIE_Pos (7U)
17398#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
17399#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
17400#define USART_CR1_PEIE_Pos (8U)
17401#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
17402#define USART_CR1_PEIE USART_CR1_PEIE_Msk
17403#define USART_CR1_PS_Pos (9U)
17404#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
17405#define USART_CR1_PS USART_CR1_PS_Msk
17406#define USART_CR1_PCE_Pos (10U)
17407#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
17408#define USART_CR1_PCE USART_CR1_PCE_Msk
17409#define USART_CR1_WAKE_Pos (11U)
17410#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
17411#define USART_CR1_WAKE USART_CR1_WAKE_Msk
17412#define USART_CR1_M_Pos (12U)
17413#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
17414#define USART_CR1_M USART_CR1_M_Msk
17415#define USART_CR1_UE_Pos (13U)
17416#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
17417#define USART_CR1_UE USART_CR1_UE_Msk
17418#define USART_CR1_OVER8_Pos (15U)
17419#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
17420#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
17422/****************** Bit definition for USART_CR2 register *******************/
17423#define USART_CR2_ADD_Pos (0U)
17424#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
17425#define USART_CR2_ADD USART_CR2_ADD_Msk
17426#define USART_CR2_LBDL_Pos (5U)
17427#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
17428#define USART_CR2_LBDL USART_CR2_LBDL_Msk
17429#define USART_CR2_LBDIE_Pos (6U)
17430#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
17431#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
17432#define USART_CR2_LBCL_Pos (8U)
17433#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
17434#define USART_CR2_LBCL USART_CR2_LBCL_Msk
17435#define USART_CR2_CPHA_Pos (9U)
17436#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
17437#define USART_CR2_CPHA USART_CR2_CPHA_Msk
17438#define USART_CR2_CPOL_Pos (10U)
17439#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
17440#define USART_CR2_CPOL USART_CR2_CPOL_Msk
17441#define USART_CR2_CLKEN_Pos (11U)
17442#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
17443#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
17445#define USART_CR2_STOP_Pos (12U)
17446#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
17447#define USART_CR2_STOP USART_CR2_STOP_Msk
17448#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
17449#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
17451#define USART_CR2_LINEN_Pos (14U)
17452#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
17453#define USART_CR2_LINEN USART_CR2_LINEN_Msk
17455/****************** Bit definition for USART_CR3 register *******************/
17456#define USART_CR3_EIE_Pos (0U)
17457#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
17458#define USART_CR3_EIE USART_CR3_EIE_Msk
17459#define USART_CR3_IREN_Pos (1U)
17460#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
17461#define USART_CR3_IREN USART_CR3_IREN_Msk
17462#define USART_CR3_IRLP_Pos (2U)
17463#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
17464#define USART_CR3_IRLP USART_CR3_IRLP_Msk
17465#define USART_CR3_HDSEL_Pos (3U)
17466#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
17467#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
17468#define USART_CR3_NACK_Pos (4U)
17469#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
17470#define USART_CR3_NACK USART_CR3_NACK_Msk
17471#define USART_CR3_SCEN_Pos (5U)
17472#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
17473#define USART_CR3_SCEN USART_CR3_SCEN_Msk
17474#define USART_CR3_DMAR_Pos (6U)
17475#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
17476#define USART_CR3_DMAR USART_CR3_DMAR_Msk
17477#define USART_CR3_DMAT_Pos (7U)
17478#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
17479#define USART_CR3_DMAT USART_CR3_DMAT_Msk
17480#define USART_CR3_RTSE_Pos (8U)
17481#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
17482#define USART_CR3_RTSE USART_CR3_RTSE_Msk
17483#define USART_CR3_CTSE_Pos (9U)
17484#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
17485#define USART_CR3_CTSE USART_CR3_CTSE_Msk
17486#define USART_CR3_CTSIE_Pos (10U)
17487#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
17488#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
17489#define USART_CR3_ONEBIT_Pos (11U)
17490#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
17491#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
17493/****************** Bit definition for USART_GTPR register ******************/
17494#define USART_GTPR_PSC_Pos (0U)
17495#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
17496#define USART_GTPR_PSC USART_GTPR_PSC_Msk
17497#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
17498#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
17499#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
17500#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
17501#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
17502#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
17503#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
17504#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
17506#define USART_GTPR_GT_Pos (8U)
17507#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
17508#define USART_GTPR_GT USART_GTPR_GT_Msk
17510/******************************************************************************/
17511/* */
17512/* Window WATCHDOG */
17513/* */
17514/******************************************************************************/
17515/******************* Bit definition for WWDG_CR register ********************/
17516#define WWDG_CR_T_Pos (0U)
17517#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
17518#define WWDG_CR_T WWDG_CR_T_Msk
17519#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
17520#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
17521#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
17522#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
17523#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
17524#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
17525#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
17526/* Legacy defines */
17527#define WWDG_CR_T0 WWDG_CR_T_0
17528#define WWDG_CR_T1 WWDG_CR_T_1
17529#define WWDG_CR_T2 WWDG_CR_T_2
17530#define WWDG_CR_T3 WWDG_CR_T_3
17531#define WWDG_CR_T4 WWDG_CR_T_4
17532#define WWDG_CR_T5 WWDG_CR_T_5
17533#define WWDG_CR_T6 WWDG_CR_T_6
17534
17535#define WWDG_CR_WDGA_Pos (7U)
17536#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
17537#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
17539/******************* Bit definition for WWDG_CFR register *******************/
17540#define WWDG_CFR_W_Pos (0U)
17541#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
17542#define WWDG_CFR_W WWDG_CFR_W_Msk
17543#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
17544#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
17545#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
17546#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
17547#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
17548#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
17549#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
17550/* Legacy defines */
17551#define WWDG_CFR_W0 WWDG_CFR_W_0
17552#define WWDG_CFR_W1 WWDG_CFR_W_1
17553#define WWDG_CFR_W2 WWDG_CFR_W_2
17554#define WWDG_CFR_W3 WWDG_CFR_W_3
17555#define WWDG_CFR_W4 WWDG_CFR_W_4
17556#define WWDG_CFR_W5 WWDG_CFR_W_5
17557#define WWDG_CFR_W6 WWDG_CFR_W_6
17558
17559#define WWDG_CFR_WDGTB_Pos (7U)
17560#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
17561#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
17562#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
17563#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
17564/* Legacy defines */
17565#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
17566#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
17567
17568#define WWDG_CFR_EWI_Pos (9U)
17569#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
17570#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
17572/******************* Bit definition for WWDG_SR register ********************/
17573#define WWDG_SR_EWIF_Pos (0U)
17574#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
17575#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
17578/******************************************************************************/
17579/* */
17580/* DBG */
17581/* */
17582/******************************************************************************/
17583/******************** Bit definition for DBGMCU_IDCODE register *************/
17584#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
17585#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
17586#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
17587#define DBGMCU_IDCODE_REV_ID_Pos (16U)
17588#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
17589#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
17590
17591/******************** Bit definition for DBGMCU_CR register *****************/
17592#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
17593#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
17594#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
17595#define DBGMCU_CR_DBG_STOP_Pos (1U)
17596#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
17597#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
17598#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
17599#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
17600#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
17601#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
17602#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
17603#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
17604
17605#define DBGMCU_CR_TRACE_MODE_Pos (6U)
17606#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
17607#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
17608#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
17609#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
17611/******************** Bit definition for DBGMCU_APB1_FZ register ************/
17612#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
17613#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
17614#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
17615#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
17616#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
17617#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
17618#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
17619#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
17620#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
17621#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
17622#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
17623#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
17624#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
17625#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
17626#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
17627#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
17628#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
17629#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
17630#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
17631#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
17632#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
17633#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
17634#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
17635#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
17636#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
17637#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
17638#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
17639#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
17640#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
17641#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
17642#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
17643#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
17644#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
17645#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
17646#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
17647#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
17648#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
17649#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
17650#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
17651#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
17652#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
17653#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
17654#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
17655#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
17656#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
17657#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
17658#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos)
17659#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
17660#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
17661#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
17662#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
17663#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
17664#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
17665#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
17666/* Old IWDGSTOP bit definition, maintained for legacy purpose */
17667#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
17668
17669/******************** Bit definition for DBGMCU_APB2_FZ register ************/
17670#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
17671#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
17672#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
17673#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
17674#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
17675#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
17676#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
17677#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
17678#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
17679#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
17680#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
17681#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
17682#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
17683#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
17684#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
17685
17686/******************************************************************************/
17687/* */
17688/* Ethernet MAC Registers bits definitions */
17689/* */
17690/******************************************************************************/
17691/* Bit definition for Ethernet MAC Control Register register */
17692#define ETH_MACCR_WD_Pos (23U)
17693#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
17694#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
17695#define ETH_MACCR_JD_Pos (22U)
17696#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
17697#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
17698#define ETH_MACCR_IFG_Pos (17U)
17699#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
17700#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
17701#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
17702#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
17703#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
17704#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
17705#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
17706#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
17707#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
17708#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
17709#define ETH_MACCR_CSD_Pos (16U)
17710#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
17711#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
17712#define ETH_MACCR_FES_Pos (14U)
17713#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
17714#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
17715#define ETH_MACCR_ROD_Pos (13U)
17716#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
17717#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
17718#define ETH_MACCR_LM_Pos (12U)
17719#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
17720#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
17721#define ETH_MACCR_DM_Pos (11U)
17722#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
17723#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
17724#define ETH_MACCR_IPCO_Pos (10U)
17725#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
17726#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
17727#define ETH_MACCR_RD_Pos (9U)
17728#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
17729#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
17730#define ETH_MACCR_APCS_Pos (7U)
17731#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
17732#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
17733#define ETH_MACCR_BL_Pos (5U)
17734#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
17735#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
17736 a transmission attempt during retries after a collision: 0 =< r <2^k */
17737#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
17738#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
17739#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
17740#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
17741#define ETH_MACCR_DC_Pos (4U)
17742#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
17743#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
17744#define ETH_MACCR_TE_Pos (3U)
17745#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
17746#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
17747#define ETH_MACCR_RE_Pos (2U)
17748#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
17749#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
17750
17751/* Bit definition for Ethernet MAC Frame Filter Register */
17752#define ETH_MACFFR_RA_Pos (31U)
17753#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
17754#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
17755#define ETH_MACFFR_HPF_Pos (10U)
17756#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
17757#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
17758#define ETH_MACFFR_SAF_Pos (9U)
17759#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
17760#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
17761#define ETH_MACFFR_SAIF_Pos (8U)
17762#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
17763#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
17764#define ETH_MACFFR_PCF_Pos (6U)
17765#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
17766#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
17767#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
17768#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
17769#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
17770#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
17771#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
17772#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
17773#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
17774#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
17775#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
17776#define ETH_MACFFR_BFD_Pos (5U)
17777#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
17778#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
17779#define ETH_MACFFR_PAM_Pos (4U)
17780#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
17781#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
17782#define ETH_MACFFR_DAIF_Pos (3U)
17783#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
17784#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
17785#define ETH_MACFFR_HM_Pos (2U)
17786#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
17787#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
17788#define ETH_MACFFR_HU_Pos (1U)
17789#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
17790#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
17791#define ETH_MACFFR_PM_Pos (0U)
17792#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
17793#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
17794
17795/* Bit definition for Ethernet MAC Hash Table High Register */
17796#define ETH_MACHTHR_HTH_Pos (0U)
17797#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
17798#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
17799
17800/* Bit definition for Ethernet MAC Hash Table Low Register */
17801#define ETH_MACHTLR_HTL_Pos (0U)
17802#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
17803#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
17804
17805/* Bit definition for Ethernet MAC MII Address Register */
17806#define ETH_MACMIIAR_PA_Pos (11U)
17807#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
17808#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
17809#define ETH_MACMIIAR_MR_Pos (6U)
17810#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
17811#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
17812#define ETH_MACMIIAR_CR_Pos (2U)
17813#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
17814#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
17815#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
17816#define ETH_MACMIIAR_CR_Div62_Pos (2U)
17817#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
17818#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
17819#define ETH_MACMIIAR_CR_Div16_Pos (3U)
17820#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
17821#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
17822#define ETH_MACMIIAR_CR_Div26_Pos (2U)
17823#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
17824#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
17825#define ETH_MACMIIAR_CR_Div102_Pos (4U)
17826#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
17827#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
17828#define ETH_MACMIIAR_MW_Pos (1U)
17829#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
17830#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
17831#define ETH_MACMIIAR_MB_Pos (0U)
17832#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
17833#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
17834
17835/* Bit definition for Ethernet MAC MII Data Register */
17836#define ETH_MACMIIDR_MD_Pos (0U)
17837#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
17838#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
17839
17840/* Bit definition for Ethernet MAC Flow Control Register */
17841#define ETH_MACFCR_PT_Pos (16U)
17842#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
17843#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
17844#define ETH_MACFCR_ZQPD_Pos (7U)
17845#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
17846#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
17847#define ETH_MACFCR_PLT_Pos (4U)
17848#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
17849#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
17850#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
17851#define ETH_MACFCR_PLT_Minus28_Pos (4U)
17852#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
17853#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
17854#define ETH_MACFCR_PLT_Minus144_Pos (5U)
17855#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
17856#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
17857#define ETH_MACFCR_PLT_Minus256_Pos (4U)
17858#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
17859#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
17860#define ETH_MACFCR_UPFD_Pos (3U)
17861#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
17862#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
17863#define ETH_MACFCR_RFCE_Pos (2U)
17864#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
17865#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
17866#define ETH_MACFCR_TFCE_Pos (1U)
17867#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
17868#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
17869#define ETH_MACFCR_FCBBPA_Pos (0U)
17870#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
17871#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
17872
17873/* Bit definition for Ethernet MAC VLAN Tag Register */
17874#define ETH_MACVLANTR_VLANTC_Pos (16U)
17875#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
17876#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
17877#define ETH_MACVLANTR_VLANTI_Pos (0U)
17878#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
17879#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
17880
17881/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
17882#define ETH_MACRWUFFR_D_Pos (0U)
17883#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
17884#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
17885/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
17886 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
17887/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
17888 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
17889 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
17890 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
17891 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
17892 RSVD - Filter1 Command - RSVD - Filter0 Command
17893 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
17894 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
17895 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
17896
17897/* Bit definition for Ethernet MAC PMT Control and Status Register */
17898#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
17899#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
17900#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
17901#define ETH_MACPMTCSR_GU_Pos (9U)
17902#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
17903#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
17904#define ETH_MACPMTCSR_WFR_Pos (6U)
17905#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
17906#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
17907#define ETH_MACPMTCSR_MPR_Pos (5U)
17908#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
17909#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
17910#define ETH_MACPMTCSR_WFE_Pos (2U)
17911#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
17912#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
17913#define ETH_MACPMTCSR_MPE_Pos (1U)
17914#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
17915#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
17916#define ETH_MACPMTCSR_PD_Pos (0U)
17917#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
17918#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
17919
17920/* Bit definition for Ethernet MAC debug Register */
17921#define ETH_MACDBGR_TFF_Pos (25U)
17922#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
17923#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
17924#define ETH_MACDBGR_TFNE_Pos (24U)
17925#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
17926#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
17927#define ETH_MACDBGR_TFWA_Pos (22U)
17928#define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)
17929#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
17930#define ETH_MACDBGR_TFRS_Pos (20U)
17931#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
17932#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
17933#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
17934#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
17935#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
17936#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
17937#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
17938#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
17939#define ETH_MACDBGR_TFRS_READ_Pos (20U)
17940#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
17941#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
17942#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
17943#define ETH_MACDBGR_MTP_Pos (19U)
17944#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
17945#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
17946#define ETH_MACDBGR_MTFCS_Pos (17U)
17947#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
17948#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
17949#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
17950#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
17951#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
17952#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
17953#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
17954#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
17955#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
17956#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
17957#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
17958#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
17959#define ETH_MACDBGR_MMTEA_Pos (16U)
17960#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
17961#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
17962#define ETH_MACDBGR_RFFL_Pos (8U)
17963#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
17964#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
17965#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
17966#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
17967#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
17968#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
17969#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
17970#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
17971#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
17972#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
17973#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
17974#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
17975#define ETH_MACDBGR_RFRCS_Pos (5U)
17976#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
17977#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
17978#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
17979#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
17980#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
17981#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
17982#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
17983#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
17984#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
17985#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
17986#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
17987#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
17988#define ETH_MACDBGR_RFWRA_Pos (4U)
17989#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
17990#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
17991#define ETH_MACDBGR_MSFRWCS_Pos (1U)
17992#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
17993#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
17994#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
17995#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
17996#define ETH_MACDBGR_MMRPEA_Pos (0U)
17997#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
17998#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
17999
18000/* Bit definition for Ethernet MAC Status Register */
18001#define ETH_MACSR_TSTS_Pos (9U)
18002#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
18003#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
18004#define ETH_MACSR_MMCTS_Pos (6U)
18005#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
18006#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
18007#define ETH_MACSR_MMMCRS_Pos (5U)
18008#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
18009#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
18010#define ETH_MACSR_MMCS_Pos (4U)
18011#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
18012#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
18013#define ETH_MACSR_PMTS_Pos (3U)
18014#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
18015#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
18016
18017/* Bit definition for Ethernet MAC Interrupt Mask Register */
18018#define ETH_MACIMR_TSTIM_Pos (9U)
18019#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
18020#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
18021#define ETH_MACIMR_PMTIM_Pos (3U)
18022#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
18023#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
18024
18025/* Bit definition for Ethernet MAC Address0 High Register */
18026#define ETH_MACA0HR_MACA0H_Pos (0U)
18027#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
18028#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
18029
18030/* Bit definition for Ethernet MAC Address0 Low Register */
18031#define ETH_MACA0LR_MACA0L_Pos (0U)
18032#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
18033#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
18034
18035/* Bit definition for Ethernet MAC Address1 High Register */
18036#define ETH_MACA1HR_AE_Pos (31U)
18037#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
18038#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
18039#define ETH_MACA1HR_SA_Pos (30U)
18040#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
18041#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
18042#define ETH_MACA1HR_MBC_Pos (24U)
18043#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
18044#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
18045#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
18046#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
18047#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
18048#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
18049#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
18050#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
18051#define ETH_MACA1HR_MACA1H_Pos (0U)
18052#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
18053#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
18054
18055/* Bit definition for Ethernet MAC Address1 Low Register */
18056#define ETH_MACA1LR_MACA1L_Pos (0U)
18057#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
18058#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
18059
18060/* Bit definition for Ethernet MAC Address2 High Register */
18061#define ETH_MACA2HR_AE_Pos (31U)
18062#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
18063#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
18064#define ETH_MACA2HR_SA_Pos (30U)
18065#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
18066#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
18067#define ETH_MACA2HR_MBC_Pos (24U)
18068#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
18069#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
18070#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
18071#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
18072#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
18073#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
18074#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
18075#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
18076#define ETH_MACA2HR_MACA2H_Pos (0U)
18077#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
18078#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
18079
18080/* Bit definition for Ethernet MAC Address2 Low Register */
18081#define ETH_MACA2LR_MACA2L_Pos (0U)
18082#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
18083#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
18084
18085/* Bit definition for Ethernet MAC Address3 High Register */
18086#define ETH_MACA3HR_AE_Pos (31U)
18087#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
18088#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
18089#define ETH_MACA3HR_SA_Pos (30U)
18090#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
18091#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
18092#define ETH_MACA3HR_MBC_Pos (24U)
18093#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
18094#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
18095#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
18096#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
18097#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
18098#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
18099#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
18100#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
18101#define ETH_MACA3HR_MACA3H_Pos (0U)
18102#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
18103#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
18104
18105/* Bit definition for Ethernet MAC Address3 Low Register */
18106#define ETH_MACA3LR_MACA3L_Pos (0U)
18107#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
18108#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
18109
18110/******************************************************************************/
18111/* Ethernet MMC Registers bits definition */
18112/******************************************************************************/
18113
18114/* Bit definition for Ethernet MMC Control Register */
18115#define ETH_MMCCR_MCFHP_Pos (5U)
18116#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
18117#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
18118#define ETH_MMCCR_MCP_Pos (4U)
18119#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
18120#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
18121#define ETH_MMCCR_MCF_Pos (3U)
18122#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
18123#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
18124#define ETH_MMCCR_ROR_Pos (2U)
18125#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
18126#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
18127#define ETH_MMCCR_CSR_Pos (1U)
18128#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
18129#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
18130#define ETH_MMCCR_CR_Pos (0U)
18131#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
18132#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
18133
18134/* Bit definition for Ethernet MMC Receive Interrupt Register */
18135#define ETH_MMCRIR_RGUFS_Pos (17U)
18136#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
18137#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
18138#define ETH_MMCRIR_RFAES_Pos (6U)
18139#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
18140#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
18141#define ETH_MMCRIR_RFCES_Pos (5U)
18142#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
18143#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
18144
18145/* Bit definition for Ethernet MMC Transmit Interrupt Register */
18146#define ETH_MMCTIR_TGFS_Pos (21U)
18147#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
18148#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
18149#define ETH_MMCTIR_TGFMSCS_Pos (15U)
18150#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
18151#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
18152#define ETH_MMCTIR_TGFSCS_Pos (14U)
18153#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
18154#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
18155
18156/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
18157#define ETH_MMCRIMR_RGUFM_Pos (17U)
18158#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
18159#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
18160#define ETH_MMCRIMR_RFAEM_Pos (6U)
18161#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
18162#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
18163#define ETH_MMCRIMR_RFCEM_Pos (5U)
18164#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
18165#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
18166
18167/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
18168#define ETH_MMCTIMR_TGFM_Pos (21U)
18169#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
18170#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
18171#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
18172#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
18173#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
18174#define ETH_MMCTIMR_TGFSCM_Pos (14U)
18175#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
18176#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
18177
18178/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
18179#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
18180#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
18181#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
18182
18183/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
18184#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
18185#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
18186#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
18187
18188/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
18189#define ETH_MMCTGFCR_TGFC_Pos (0U)
18190#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
18191#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
18192
18193/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
18194#define ETH_MMCRFCECR_RFCEC_Pos (0U)
18195#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
18196#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
18197
18198/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
18199#define ETH_MMCRFAECR_RFAEC_Pos (0U)
18200#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
18201#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
18202
18203/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
18204#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
18205#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
18206#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
18207
18208/******************************************************************************/
18209/* Ethernet PTP Registers bits definition */
18210/******************************************************************************/
18211
18212/* Bit definition for Ethernet PTP Time Stamp Control Register */
18213#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
18214#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)
18215#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
18216#define ETH_PTPTSCR_TSCNT_Pos (16U)
18217#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
18218#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
18219#define ETH_PTPTSCR_TSSMRME_Pos (15U)
18220#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)
18221#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
18222#define ETH_PTPTSCR_TSSEME_Pos (14U)
18223#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos)
18224#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
18225#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
18226#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)
18227#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
18228#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
18229#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)
18230#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
18231#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
18232#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)
18233#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
18234#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
18235#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)
18236#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
18237#define ETH_PTPTSCR_TSSSR_Pos (9U)
18238#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos)
18239#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
18240#define ETH_PTPTSCR_TSSARFE_Pos (8U)
18241#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)
18242#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
18243
18244#define ETH_PTPTSCR_TSARU_Pos (5U)
18245#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
18246#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
18247#define ETH_PTPTSCR_TSITE_Pos (4U)
18248#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
18249#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
18250#define ETH_PTPTSCR_TSSTU_Pos (3U)
18251#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
18252#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
18253#define ETH_PTPTSCR_TSSTI_Pos (2U)
18254#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
18255#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
18256#define ETH_PTPTSCR_TSFCU_Pos (1U)
18257#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
18258#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
18259#define ETH_PTPTSCR_TSE_Pos (0U)
18260#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
18261#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
18262
18263/* Bit definition for Ethernet PTP Sub-Second Increment Register */
18264#define ETH_PTPSSIR_STSSI_Pos (0U)
18265#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
18266#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
18267
18268/* Bit definition for Ethernet PTP Time Stamp High Register */
18269#define ETH_PTPTSHR_STS_Pos (0U)
18270#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
18271#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
18272
18273/* Bit definition for Ethernet PTP Time Stamp Low Register */
18274#define ETH_PTPTSLR_STPNS_Pos (31U)
18275#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
18276#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
18277#define ETH_PTPTSLR_STSS_Pos (0U)
18278#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
18279#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
18280
18281/* Bit definition for Ethernet PTP Time Stamp High Update Register */
18282#define ETH_PTPTSHUR_TSUS_Pos (0U)
18283#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
18284#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
18285
18286/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
18287#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
18288#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
18289#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
18290#define ETH_PTPTSLUR_TSUSS_Pos (0U)
18291#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
18292#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
18293
18294/* Bit definition for Ethernet PTP Time Stamp Addend Register */
18295#define ETH_PTPTSAR_TSA_Pos (0U)
18296#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
18297#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
18298
18299/* Bit definition for Ethernet PTP Target Time High Register */
18300#define ETH_PTPTTHR_TTSH_Pos (0U)
18301#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
18302#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
18303
18304/* Bit definition for Ethernet PTP Target Time Low Register */
18305#define ETH_PTPTTLR_TTSL_Pos (0U)
18306#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
18307#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
18308
18309/* Bit definition for Ethernet PTP Time Stamp Status Register */
18310#define ETH_PTPTSSR_TSTTR_Pos (5U)
18311#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
18312#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
18313#define ETH_PTPTSSR_TSSO_Pos (4U)
18314#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
18315#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
18316
18317/******************************************************************************/
18318/* Ethernet DMA Registers bits definition */
18319/******************************************************************************/
18320
18321/* Bit definition for Ethernet DMA Bus Mode Register */
18322#define ETH_DMABMR_MB_Pos (26U)
18323#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos)
18324#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
18325#define ETH_DMABMR_AAB_Pos (25U)
18326#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
18327#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
18328#define ETH_DMABMR_FPM_Pos (24U)
18329#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
18330#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
18331#define ETH_DMABMR_USP_Pos (23U)
18332#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
18333#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
18334#define ETH_DMABMR_RDP_Pos (17U)
18335#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
18336#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
18337#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
18338#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
18339#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18340#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18341#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18342#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18343#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18344#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18345#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18346#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18347#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
18348#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
18349#define ETH_DMABMR_FB_Pos (16U)
18350#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
18351#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
18352#define ETH_DMABMR_RTPR_Pos (14U)
18353#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
18354#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
18355#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
18356#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
18357#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
18358#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
18359#define ETH_DMABMR_PBL_Pos (8U)
18360#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
18361#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
18362#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
18363#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
18364#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18365#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18366#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18367#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18368#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18369#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18370#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18371#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18372#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
18373#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
18374#define ETH_DMABMR_EDE_Pos (7U)
18375#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
18376#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
18377#define ETH_DMABMR_DSL_Pos (2U)
18378#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
18379#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
18380#define ETH_DMABMR_DA_Pos (1U)
18381#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
18382#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
18383#define ETH_DMABMR_SR_Pos (0U)
18384#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
18385#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
18386
18387/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
18388#define ETH_DMATPDR_TPD_Pos (0U)
18389#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
18390#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
18391
18392/* Bit definition for Ethernet DMA Receive Poll Demand Register */
18393#define ETH_DMARPDR_RPD_Pos (0U)
18394#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
18395#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
18396
18397/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
18398#define ETH_DMARDLAR_SRL_Pos (0U)
18399#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
18400#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
18401
18402/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
18403#define ETH_DMATDLAR_STL_Pos (0U)
18404#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
18405#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
18406
18407/* Bit definition for Ethernet DMA Status Register */
18408#define ETH_DMASR_TSTS_Pos (29U)
18409#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
18410#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
18411#define ETH_DMASR_PMTS_Pos (28U)
18412#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
18413#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
18414#define ETH_DMASR_MMCS_Pos (27U)
18415#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
18416#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
18417#define ETH_DMASR_EBS_Pos (23U)
18418#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
18419#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
18420 /* combination with EBS[2:0] for GetFlagStatus function */
18421#define ETH_DMASR_EBS_DescAccess_Pos (25U)
18422#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
18423#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
18424#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
18425#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
18426#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
18427#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
18428#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
18429#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
18430#define ETH_DMASR_TPS_Pos (20U)
18431#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
18432#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
18433#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
18434#define ETH_DMASR_TPS_Fetching_Pos (20U)
18435#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
18436#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
18437#define ETH_DMASR_TPS_Waiting_Pos (21U)
18438#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
18439#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
18440#define ETH_DMASR_TPS_Reading_Pos (20U)
18441#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
18442#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
18443#define ETH_DMASR_TPS_Suspended_Pos (21U)
18444#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
18445#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
18446#define ETH_DMASR_TPS_Closing_Pos (20U)
18447#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
18448#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
18449#define ETH_DMASR_RPS_Pos (17U)
18450#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
18451#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
18452#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
18453#define ETH_DMASR_RPS_Fetching_Pos (17U)
18454#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
18455#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
18456#define ETH_DMASR_RPS_Waiting_Pos (17U)
18457#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
18458#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
18459#define ETH_DMASR_RPS_Suspended_Pos (19U)
18460#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
18461#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
18462#define ETH_DMASR_RPS_Closing_Pos (17U)
18463#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
18464#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
18465#define ETH_DMASR_RPS_Queuing_Pos (17U)
18466#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
18467#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
18468#define ETH_DMASR_NIS_Pos (16U)
18469#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
18470#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
18471#define ETH_DMASR_AIS_Pos (15U)
18472#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
18473#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
18474#define ETH_DMASR_ERS_Pos (14U)
18475#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
18476#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
18477#define ETH_DMASR_FBES_Pos (13U)
18478#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
18479#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
18480#define ETH_DMASR_ETS_Pos (10U)
18481#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
18482#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
18483#define ETH_DMASR_RWTS_Pos (9U)
18484#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
18485#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
18486#define ETH_DMASR_RPSS_Pos (8U)
18487#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
18488#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
18489#define ETH_DMASR_RBUS_Pos (7U)
18490#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
18491#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
18492#define ETH_DMASR_RS_Pos (6U)
18493#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
18494#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
18495#define ETH_DMASR_TUS_Pos (5U)
18496#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
18497#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
18498#define ETH_DMASR_ROS_Pos (4U)
18499#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
18500#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
18501#define ETH_DMASR_TJTS_Pos (3U)
18502#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
18503#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
18504#define ETH_DMASR_TBUS_Pos (2U)
18505#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
18506#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
18507#define ETH_DMASR_TPSS_Pos (1U)
18508#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
18509#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
18510#define ETH_DMASR_TS_Pos (0U)
18511#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
18512#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
18513
18514/* Bit definition for Ethernet DMA Operation Mode Register */
18515#define ETH_DMAOMR_DTCEFD_Pos (26U)
18516#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
18517#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
18518#define ETH_DMAOMR_RSF_Pos (25U)
18519#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
18520#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
18521#define ETH_DMAOMR_DFRF_Pos (24U)
18522#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
18523#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
18524#define ETH_DMAOMR_TSF_Pos (21U)
18525#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
18526#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
18527#define ETH_DMAOMR_FTF_Pos (20U)
18528#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
18529#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
18530#define ETH_DMAOMR_TTC_Pos (14U)
18531#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
18532#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
18533#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
18534#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
18535#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
18536#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
18537#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
18538#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
18539#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
18540#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
18541#define ETH_DMAOMR_ST_Pos (13U)
18542#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
18543#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
18544#define ETH_DMAOMR_FEF_Pos (7U)
18545#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
18546#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
18547#define ETH_DMAOMR_FUGF_Pos (6U)
18548#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
18549#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
18550#define ETH_DMAOMR_RTC_Pos (3U)
18551#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
18552#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
18553#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
18554#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
18555#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
18556#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
18557#define ETH_DMAOMR_OSF_Pos (2U)
18558#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
18559#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
18560#define ETH_DMAOMR_SR_Pos (1U)
18561#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
18562#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
18563
18564/* Bit definition for Ethernet DMA Interrupt Enable Register */
18565#define ETH_DMAIER_NISE_Pos (16U)
18566#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
18567#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
18568#define ETH_DMAIER_AISE_Pos (15U)
18569#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
18570#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
18571#define ETH_DMAIER_ERIE_Pos (14U)
18572#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
18573#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
18574#define ETH_DMAIER_FBEIE_Pos (13U)
18575#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
18576#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
18577#define ETH_DMAIER_ETIE_Pos (10U)
18578#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
18579#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
18580#define ETH_DMAIER_RWTIE_Pos (9U)
18581#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
18582#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
18583#define ETH_DMAIER_RPSIE_Pos (8U)
18584#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
18585#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
18586#define ETH_DMAIER_RBUIE_Pos (7U)
18587#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
18588#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
18589#define ETH_DMAIER_RIE_Pos (6U)
18590#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
18591#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
18592#define ETH_DMAIER_TUIE_Pos (5U)
18593#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
18594#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
18595#define ETH_DMAIER_ROIE_Pos (4U)
18596#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
18597#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
18598#define ETH_DMAIER_TJTIE_Pos (3U)
18599#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
18600#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
18601#define ETH_DMAIER_TBUIE_Pos (2U)
18602#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
18603#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
18604#define ETH_DMAIER_TPSIE_Pos (1U)
18605#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
18606#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
18607#define ETH_DMAIER_TIE_Pos (0U)
18608#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
18609#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
18610
18611/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
18612#define ETH_DMAMFBOCR_OFOC_Pos (28U)
18613#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
18614#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
18615#define ETH_DMAMFBOCR_MFA_Pos (17U)
18616#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
18617#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
18618#define ETH_DMAMFBOCR_OMFC_Pos (16U)
18619#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
18620#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
18621#define ETH_DMAMFBOCR_MFC_Pos (0U)
18622#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
18623#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
18624
18625/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
18626#define ETH_DMACHTDR_HTDAP_Pos (0U)
18627#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
18628#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
18629
18630/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
18631#define ETH_DMACHRDR_HRDAP_Pos (0U)
18632#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
18633#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
18634
18635/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
18636#define ETH_DMACHTBAR_HTBAP_Pos (0U)
18637#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
18638#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
18639
18640/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
18641#define ETH_DMACHRBAR_HRBAP_Pos (0U)
18642#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
18643#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
18644
18645/******************************************************************************/
18646/* */
18647/* USB_OTG */
18648/* */
18649/******************************************************************************/
18650/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
18651#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
18652#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
18653#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
18654#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
18655#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
18656#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
18657#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
18658#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
18659#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
18660#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
18661#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
18662#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
18663#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
18664#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
18665#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
18666#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
18667#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
18668#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
18669#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
18670#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
18671#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
18672#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
18673#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
18674#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
18675#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
18676#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
18677#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
18678#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
18679#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
18680#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
18681#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
18682#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
18683#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
18684#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
18685#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
18686#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
18687#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
18688#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
18689#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
18690#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
18691#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
18692#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
18693#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
18694#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
18695#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
18696#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
18697#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
18698#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
18699#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
18700#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
18701#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
18702#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
18703#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
18704#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
18706/******************** Bit definition forUSB_OTG_HCFG register ********************/
18707
18708#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
18709#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
18710#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
18711#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
18712#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
18713#define USB_OTG_HCFG_FSLSS_Pos (2U)
18714#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
18715#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
18717/******************** Bit definition for USB_OTG_DCFG register ********************/
18718
18719#define USB_OTG_DCFG_DSPD_Pos (0U)
18720#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
18721#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
18722#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
18723#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
18724#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
18725#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
18726#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
18728#define USB_OTG_DCFG_DAD_Pos (4U)
18729#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
18730#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
18731#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
18732#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
18733#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
18734#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
18735#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
18736#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
18737#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
18739#define USB_OTG_DCFG_PFIVL_Pos (11U)
18740#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
18741#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
18742#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
18743#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
18745#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
18746#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
18747#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
18749#define USB_OTG_DCFG_ERRATIM_Pos (15U)
18750#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
18751#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
18753#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
18754#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
18755#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
18756#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
18757#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
18759/******************** Bit definition for USB_OTG_PCGCR register ********************/
18760#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
18761#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
18762#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
18763#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
18764#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
18765#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
18766#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
18767#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
18768#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
18770/******************** Bit definition for USB_OTG_GOTGINT register ********************/
18771#define USB_OTG_GOTGINT_SEDET_Pos (2U)
18772#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
18773#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
18774#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
18775#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
18776#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
18777#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
18778#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
18779#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
18780#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
18781#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
18782#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
18783#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
18784#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
18785#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
18786#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
18787#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
18788#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
18789#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
18790#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos)
18791#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk
18793/******************** Bit definition for USB_OTG_DCTL register ********************/
18794#define USB_OTG_DCTL_RWUSIG_Pos (0U)
18795#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
18796#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
18797#define USB_OTG_DCTL_SDIS_Pos (1U)
18798#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
18799#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
18800#define USB_OTG_DCTL_GINSTS_Pos (2U)
18801#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
18802#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
18803#define USB_OTG_DCTL_GONSTS_Pos (3U)
18804#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
18805#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
18807#define USB_OTG_DCTL_TCTL_Pos (4U)
18808#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
18809#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
18810#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
18811#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
18812#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
18813#define USB_OTG_DCTL_SGINAK_Pos (7U)
18814#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
18815#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
18816#define USB_OTG_DCTL_CGINAK_Pos (8U)
18817#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
18818#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
18819#define USB_OTG_DCTL_SGONAK_Pos (9U)
18820#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
18821#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
18822#define USB_OTG_DCTL_CGONAK_Pos (10U)
18823#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
18824#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
18825#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
18826#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
18827#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
18829/******************** Bit definition for USB_OTG_HFIR register ********************/
18830#define USB_OTG_HFIR_FRIVL_Pos (0U)
18831#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
18832#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
18834/******************** Bit definition for USB_OTG_HFNUM register ********************/
18835#define USB_OTG_HFNUM_FRNUM_Pos (0U)
18836#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
18837#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
18838#define USB_OTG_HFNUM_FTREM_Pos (16U)
18839#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
18840#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
18842/******************** Bit definition for USB_OTG_DSTS register ********************/
18843#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
18844#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
18845#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
18847#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
18848#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
18849#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
18850#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
18851#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
18852#define USB_OTG_DSTS_EERR_Pos (3U)
18853#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
18854#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
18855#define USB_OTG_DSTS_FNSOF_Pos (8U)
18856#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
18857#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
18859/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
18860#define USB_OTG_GAHBCFG_GINT_Pos (0U)
18861#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
18862#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
18863#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
18864#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18865#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
18866#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18867#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18868#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18869#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18870#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18871#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
18872#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
18873#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
18874#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
18875#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
18876#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
18877#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
18878#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
18879#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
18881/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
18882
18883#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
18884#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18885#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
18886#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18887#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18888#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18889#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
18890#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
18891#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
18892#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
18893#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
18894#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
18895#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
18896#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
18897#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
18898#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
18899#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
18900#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
18901#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
18902#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
18903#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
18904#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
18905#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
18906#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
18907#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
18908#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
18909#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
18910#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
18911#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
18912#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
18913#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
18914#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
18915#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
18916#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
18917#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
18918#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
18919#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
18920#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
18921#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
18922#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
18923#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
18924#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
18925#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
18926#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
18927#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
18928#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
18929#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
18930#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
18931#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
18932#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
18933#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
18934#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
18935#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
18936#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
18937#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
18938#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
18939#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
18940#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
18941#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
18942#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
18943#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
18945/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
18946#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
18947#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
18948#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
18949#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
18950#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
18951#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
18952#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
18953#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
18954#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
18955#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
18956#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
18957#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
18958#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
18959#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
18960#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
18963#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
18964#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18965#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
18966#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18967#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18968#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18969#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18970#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18971#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
18972#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
18973#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
18974#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
18975#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
18976#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
18978/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
18979#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
18980#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
18981#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
18982#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
18983#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
18984#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
18985#define USB_OTG_DIEPMSK_TOM_Pos (3U)
18986#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
18987#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
18988#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
18989#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
18990#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
18991#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
18992#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
18993#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
18994#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
18995#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
18996#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
18997#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
18998#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
18999#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
19000#define USB_OTG_DIEPMSK_BIM_Pos (9U)
19001#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
19002#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
19004/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
19005#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
19006#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
19007#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
19008#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
19009#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
19010#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
19011#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
19012#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
19013#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
19014#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
19015#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
19016#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
19017#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
19018#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
19020#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
19021#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
19022#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
19023#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
19024#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
19025#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
19026#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
19027#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
19028#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
19029#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
19030#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
19032/******************** Bit definition for USB_OTG_HAINT register ********************/
19033#define USB_OTG_HAINT_HAINT_Pos (0U)
19034#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
19035#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
19037/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
19038#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
19039#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
19040#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
19041#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
19042#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
19043#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
19044#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
19045#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
19046#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
19047#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
19048#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
19049#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
19050#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
19051#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
19052#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
19053#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
19054#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
19055#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
19056#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
19057#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
19058#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
19059#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
19060#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
19061#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
19062#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
19063#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
19064#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
19065#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
19066#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
19067#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
19068#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
19069#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
19070#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
19071#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
19072#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
19073#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
19074/******************** Bit definition for USB_OTG_GINTSTS register ********************/
19075#define USB_OTG_GINTSTS_CMOD_Pos (0U)
19076#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
19077#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
19078#define USB_OTG_GINTSTS_MMIS_Pos (1U)
19079#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
19080#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
19081#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
19082#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
19083#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
19084#define USB_OTG_GINTSTS_SOF_Pos (3U)
19085#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
19086#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
19087#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
19088#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
19089#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
19090#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
19091#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
19092#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
19093#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
19094#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
19095#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
19096#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
19097#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
19098#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
19099#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
19100#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
19101#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
19102#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
19103#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
19104#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
19105#define USB_OTG_GINTSTS_USBRST_Pos (12U)
19106#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
19107#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
19108#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
19109#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
19110#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
19111#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
19112#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
19113#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
19114#define USB_OTG_GINTSTS_EOPF_Pos (15U)
19115#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
19116#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
19117#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
19118#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
19119#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
19120#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
19121#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
19122#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
19123#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
19124#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
19125#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
19126#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
19127#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
19128#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
19129#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
19130#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
19131#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
19132#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
19133#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
19134#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
19135#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
19136#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
19137#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
19138#define USB_OTG_GINTSTS_HCINT_Pos (25U)
19139#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
19140#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
19141#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
19142#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
19143#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
19144#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
19145#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
19146#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
19147#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
19148#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
19149#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
19150#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
19151#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
19152#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
19153#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
19154#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
19155#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
19156#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
19157#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
19158#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
19160/******************** Bit definition for USB_OTG_GINTMSK register ********************/
19161#define USB_OTG_GINTMSK_MMISM_Pos (1U)
19162#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
19163#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
19164#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
19165#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
19166#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
19167#define USB_OTG_GINTMSK_SOFM_Pos (3U)
19168#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
19169#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
19170#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
19171#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
19172#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
19173#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
19174#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
19175#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
19176#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
19177#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
19178#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
19179#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
19180#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
19181#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
19182#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
19183#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
19184#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
19185#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
19186#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
19187#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
19188#define USB_OTG_GINTMSK_USBRST_Pos (12U)
19189#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
19190#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
19191#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
19192#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
19193#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
19194#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
19195#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
19196#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
19197#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
19198#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
19199#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
19200#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
19201#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
19202#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
19203#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
19204#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
19205#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
19206#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
19207#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
19208#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
19209#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
19210#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
19211#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
19212#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
19213#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
19214#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
19215#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
19216#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
19217#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
19218#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
19219#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
19220#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
19221#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
19222#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
19223#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
19224#define USB_OTG_GINTMSK_HCIM_Pos (25U)
19225#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
19226#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
19227#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
19228#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
19229#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
19230#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
19231#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
19232#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
19233#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
19234#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
19235#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
19236#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
19237#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
19238#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
19239#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
19240#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
19241#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
19242#define USB_OTG_GINTMSK_WUIM_Pos (31U)
19243#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
19244#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
19246/******************** Bit definition for USB_OTG_DAINT register ********************/
19247#define USB_OTG_DAINT_IEPINT_Pos (0U)
19248#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
19249#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
19250#define USB_OTG_DAINT_OEPINT_Pos (16U)
19251#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
19252#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
19254/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
19255#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
19256#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
19257#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
19259/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
19260#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
19261#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
19262#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
19263#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
19264#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
19265#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
19266#define USB_OTG_GRXSTSP_DPID_Pos (15U)
19267#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
19268#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
19269#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
19270#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
19271#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
19273/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
19274#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
19275#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
19276#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
19277#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
19278#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
19279#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
19281/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
19282#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
19283#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
19284#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
19286/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
19287#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
19288#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
19289#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
19291/******************** Bit definition for OTG register ********************/
19292#define USB_OTG_NPTXFSA_Pos (0U)
19293#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
19294#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
19295#define USB_OTG_NPTXFD_Pos (16U)
19296#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
19297#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
19298#define USB_OTG_TX0FSA_Pos (0U)
19299#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
19300#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
19301#define USB_OTG_TX0FD_Pos (16U)
19302#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
19303#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
19305/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
19306#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
19307#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
19308#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
19310/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
19311#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
19312#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
19313#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
19315#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
19316#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19317#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
19318#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19319#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19320#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19321#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19322#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19323#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19324#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19325#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19327#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
19328#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19329#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
19330#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19331#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19332#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19333#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19334#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19335#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19336#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19338/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
19339#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
19340#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
19341#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
19342#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
19343#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
19344#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
19346#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
19347#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19348#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
19349#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19350#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19351#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19352#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19353#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19354#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19355#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19356#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19357#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19358#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
19359#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
19360#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
19362#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
19363#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19364#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
19365#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19366#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19367#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19368#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19369#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19370#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19371#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19372#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19373#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19374#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
19375#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
19376#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
19378/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
19379#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
19380#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
19381#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
19383/******************** Bit definition for USB_OTG_DEACHINT register ********************/
19384#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
19385#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
19386#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
19387#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
19388#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
19389#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
19391/******************** Bit definition for USB_OTG_GCCFG register ********************/
19392#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
19393#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
19394#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
19395#define USB_OTG_GCCFG_VBDEN_Pos (21U)
19396#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
19397#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
19399/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
19400#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
19401#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
19402#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
19403#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
19404#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
19405#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
19407/******************** Bit definition for USB_OTG_CID register ********************/
19408#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
19409#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
19410#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
19412/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
19413#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
19414#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
19415#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
19416#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
19417#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
19418#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
19419#define USB_OTG_GLPMCFG_BESL_Pos (2U)
19420#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
19421#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
19422#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
19423#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
19424#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
19425#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
19426#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
19427#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
19428#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
19429#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
19430#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
19431#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
19432#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
19433#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
19434#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
19435#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
19436#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
19437#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
19438#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
19439#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
19440#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
19441#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
19442#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
19443#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
19444#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
19445#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
19446#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
19447#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
19448#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
19449#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
19450#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
19451#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
19452#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
19453#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
19454#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
19455#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
19456#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
19457#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
19459/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
19460#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
19461#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
19462#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
19463#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
19464#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
19465#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
19466#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
19467#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
19468#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
19469#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
19470#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
19471#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
19472#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
19473#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
19474#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
19475#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
19476#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
19477#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
19478#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
19479#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
19480#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
19481#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
19482#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
19483#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
19484#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
19485#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
19486#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
19488/******************** Bit definition for USB_OTG_HPRT register ********************/
19489#define USB_OTG_HPRT_PCSTS_Pos (0U)
19490#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
19491#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
19492#define USB_OTG_HPRT_PCDET_Pos (1U)
19493#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
19494#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
19495#define USB_OTG_HPRT_PENA_Pos (2U)
19496#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
19497#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
19498#define USB_OTG_HPRT_PENCHNG_Pos (3U)
19499#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
19500#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
19501#define USB_OTG_HPRT_POCA_Pos (4U)
19502#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
19503#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
19504#define USB_OTG_HPRT_POCCHNG_Pos (5U)
19505#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
19506#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
19507#define USB_OTG_HPRT_PRES_Pos (6U)
19508#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
19509#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
19510#define USB_OTG_HPRT_PSUSP_Pos (7U)
19511#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
19512#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
19513#define USB_OTG_HPRT_PRST_Pos (8U)
19514#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
19515#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
19517#define USB_OTG_HPRT_PLSTS_Pos (10U)
19518#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
19519#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
19520#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
19521#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
19522#define USB_OTG_HPRT_PPWR_Pos (12U)
19523#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
19524#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
19526#define USB_OTG_HPRT_PTCTL_Pos (13U)
19527#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
19528#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
19529#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
19530#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
19531#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
19532#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
19534#define USB_OTG_HPRT_PSPD_Pos (17U)
19535#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
19536#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
19537#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
19538#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
19540/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
19541#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
19542#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
19543#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
19544#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
19545#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
19546#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
19547#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
19548#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
19549#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
19550#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
19551#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
19552#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
19553#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
19554#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
19555#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
19556#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
19557#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
19558#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
19559#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
19560#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
19561#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
19562#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
19563#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
19564#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
19565#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
19566#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
19567#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
19568#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
19569#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
19570#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
19571#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
19572#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
19573#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
19575/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
19576#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
19577#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
19578#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
19579#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
19580#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
19581#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
19583/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
19584#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
19585#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
19586#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
19587#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
19588#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
19589#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
19590#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
19591#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
19592#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
19593#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
19594#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
19595#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
19597#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
19598#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
19599#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
19600#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
19601#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
19602#define USB_OTG_DIEPCTL_STALL_Pos (21U)
19603#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
19604#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
19606#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
19607#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19608#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
19609#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19610#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19611#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19612#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19613#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
19614#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
19615#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
19616#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
19617#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
19618#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
19619#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
19620#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
19621#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
19622#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
19623#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
19624#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
19625#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
19626#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
19627#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
19628#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
19629#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
19630#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
19632/******************** Bit definition for USB_OTG_HCCHAR register ********************/
19633#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
19634#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
19635#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
19637#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
19638#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
19639#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
19640#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
19641#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
19642#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
19643#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
19644#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
19645#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
19646#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
19647#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
19648#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
19649#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
19651#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
19652#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
19653#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
19654#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
19655#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
19657#define USB_OTG_HCCHAR_MC_Pos (20U)
19658#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
19659#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
19660#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
19661#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
19663#define USB_OTG_HCCHAR_DAD_Pos (22U)
19664#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
19665#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
19666#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
19667#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
19668#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
19669#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
19670#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
19671#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
19672#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
19673#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
19674#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
19675#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
19676#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
19677#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
19678#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
19679#define USB_OTG_HCCHAR_CHENA_Pos (31U)
19680#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
19681#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
19683/******************** Bit definition for USB_OTG_HCSPLT register ********************/
19684
19685#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
19686#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
19687#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
19688#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19689#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19690#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19691#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19692#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19693#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19694#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19696#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
19697#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
19698#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
19699#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19700#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19701#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19702#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19703#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19704#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19705#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19707#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
19708#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
19709#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
19710#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
19711#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
19712#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
19713#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
19714#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
19715#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
19716#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
19717#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
19719/******************** Bit definition for USB_OTG_HCINT register ********************/
19720#define USB_OTG_HCINT_XFRC_Pos (0U)
19721#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
19722#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
19723#define USB_OTG_HCINT_CHH_Pos (1U)
19724#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
19725#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
19726#define USB_OTG_HCINT_AHBERR_Pos (2U)
19727#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
19728#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
19729#define USB_OTG_HCINT_STALL_Pos (3U)
19730#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
19731#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
19732#define USB_OTG_HCINT_NAK_Pos (4U)
19733#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
19734#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
19735#define USB_OTG_HCINT_ACK_Pos (5U)
19736#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
19737#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
19738#define USB_OTG_HCINT_NYET_Pos (6U)
19739#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
19740#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
19741#define USB_OTG_HCINT_TXERR_Pos (7U)
19742#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
19743#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
19744#define USB_OTG_HCINT_BBERR_Pos (8U)
19745#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
19746#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
19747#define USB_OTG_HCINT_FRMOR_Pos (9U)
19748#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
19749#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
19750#define USB_OTG_HCINT_DTERR_Pos (10U)
19751#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
19752#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
19754/******************** Bit definition for USB_OTG_DIEPINT register ********************/
19755#define USB_OTG_DIEPINT_XFRC_Pos (0U)
19756#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
19757#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
19758#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
19759#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
19760#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
19761#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
19762#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
19763#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
19764#define USB_OTG_DIEPINT_TOC_Pos (3U)
19765#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
19766#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
19767#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
19768#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
19769#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
19770#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
19771#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
19772#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
19773#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
19774#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
19775#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
19776#define USB_OTG_DIEPINT_TXFE_Pos (7U)
19777#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
19778#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
19779#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
19780#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
19781#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
19782#define USB_OTG_DIEPINT_BNA_Pos (9U)
19783#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
19784#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
19785#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
19786#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
19787#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
19788#define USB_OTG_DIEPINT_BERR_Pos (12U)
19789#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
19790#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
19791#define USB_OTG_DIEPINT_NAK_Pos (13U)
19792#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
19793#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
19795/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
19796#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
19797#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
19798#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
19799#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
19800#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
19801#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
19802#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
19803#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
19804#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
19805#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
19806#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
19807#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
19808#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
19809#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
19810#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
19811#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
19812#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
19813#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
19814#define USB_OTG_HCINTMSK_NYET_Pos (6U)
19815#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
19816#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
19817#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
19818#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
19819#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
19820#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
19821#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
19822#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
19823#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
19824#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
19825#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
19826#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
19827#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
19828#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
19830/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
19831
19832#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
19833#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
19834#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
19835#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
19836#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
19837#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
19838#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
19839#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
19840#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
19841/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
19842#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
19843#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
19844#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
19845#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
19846#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
19847#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
19848#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
19849#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
19850#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
19851#define USB_OTG_HCTSIZ_DPID_Pos (29U)
19852#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
19853#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
19854#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
19855#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
19857/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
19858#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
19859#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
19860#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
19862/******************** Bit definition for USB_OTG_HCDMA register ********************/
19863#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
19864#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
19865#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
19867/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
19868#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
19869#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
19870#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
19872/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
19873#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
19874#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
19875#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
19876#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
19877#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
19878#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
19880/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
19881
19882#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
19883#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
19884#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
19885#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
19886#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
19887#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
19888#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
19889#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
19890#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
19891#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
19892#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
19893#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
19894#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
19895#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
19896#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
19897#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
19898#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
19899#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
19900#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
19901#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
19902#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
19903#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
19904#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
19905#define USB_OTG_DOEPCTL_STALL_Pos (21U)
19906#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
19907#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
19908#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
19909#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
19910#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
19911#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
19912#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
19913#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
19914#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
19915#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
19916#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
19917#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
19918#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
19919#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
19921/******************** Bit definition for USB_OTG_DOEPINT register ********************/
19922#define USB_OTG_DOEPINT_XFRC_Pos (0U)
19923#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
19924#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
19925#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
19926#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
19927#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
19928#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
19929#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
19930#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
19931#define USB_OTG_DOEPINT_STUP_Pos (3U)
19932#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
19933#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
19934#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
19935#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
19936#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
19937#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
19938#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
19939#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
19940#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
19941#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
19942#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
19943#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
19944#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
19945#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
19946#define USB_OTG_DOEPINT_NAK_Pos (13U)
19947#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
19948#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
19949#define USB_OTG_DOEPINT_NYET_Pos (14U)
19950#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
19951#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
19952#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
19953#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
19954#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
19955/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
19956
19957#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
19958#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
19959#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
19960#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
19961#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
19962#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
19964#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
19965#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
19966#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
19967#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
19968#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
19970/******************** Bit definition for PCGCCTL register ********************/
19971#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
19972#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
19973#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
19974#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
19975#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
19976#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
19977#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
19978#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
19979#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
19981/* Legacy define */
19982/******************** Bit definition for OTG register ********************/
19983#define USB_OTG_CHNUM_Pos (0U)
19984#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
19985#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
19986#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
19987#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
19988#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
19989#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
19990#define USB_OTG_BCNT_Pos (4U)
19991#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
19992#define USB_OTG_BCNT USB_OTG_BCNT_Msk
19994#define USB_OTG_DPID_Pos (15U)
19995#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
19996#define USB_OTG_DPID USB_OTG_DPID_Msk
19997#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
19998#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
20000#define USB_OTG_PKTSTS_Pos (17U)
20001#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
20002#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
20003#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
20004#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
20005#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
20006#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
20008#define USB_OTG_EPNUM_Pos (0U)
20009#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
20010#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
20011#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
20012#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
20013#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
20014#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
20016#define USB_OTG_FRMNUM_Pos (21U)
20017#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
20018#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
20019#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
20020#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
20021#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
20022#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
20035/******************************* ADC Instances ********************************/
20036#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
20037 ((INSTANCE) == ADC2) || \
20038 ((INSTANCE) == ADC3))
20039
20040#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
20041
20042#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
20043
20044/******************************* CAN Instances ********************************/
20045#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
20046 ((INSTANCE) == CAN2))
20047/******************************* CRC Instances ********************************/
20048#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
20049
20050/******************************* DAC Instances ********************************/
20051#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
20052
20053/******************************* DCMI Instances *******************************/
20054#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
20055
20056/******************************* DMA2D Instances *******************************/
20057#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
20058
20059/******************************** DMA Instances *******************************/
20060#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
20061 ((INSTANCE) == DMA1_Stream1) || \
20062 ((INSTANCE) == DMA1_Stream2) || \
20063 ((INSTANCE) == DMA1_Stream3) || \
20064 ((INSTANCE) == DMA1_Stream4) || \
20065 ((INSTANCE) == DMA1_Stream5) || \
20066 ((INSTANCE) == DMA1_Stream6) || \
20067 ((INSTANCE) == DMA1_Stream7) || \
20068 ((INSTANCE) == DMA2_Stream0) || \
20069 ((INSTANCE) == DMA2_Stream1) || \
20070 ((INSTANCE) == DMA2_Stream2) || \
20071 ((INSTANCE) == DMA2_Stream3) || \
20072 ((INSTANCE) == DMA2_Stream4) || \
20073 ((INSTANCE) == DMA2_Stream5) || \
20074 ((INSTANCE) == DMA2_Stream6) || \
20075 ((INSTANCE) == DMA2_Stream7))
20076
20077/******************************* GPIO Instances *******************************/
20078#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
20079 ((INSTANCE) == GPIOB) || \
20080 ((INSTANCE) == GPIOC) || \
20081 ((INSTANCE) == GPIOD) || \
20082 ((INSTANCE) == GPIOE) || \
20083 ((INSTANCE) == GPIOF) || \
20084 ((INSTANCE) == GPIOG) || \
20085 ((INSTANCE) == GPIOH) || \
20086 ((INSTANCE) == GPIOI) || \
20087 ((INSTANCE) == GPIOJ) || \
20088 ((INSTANCE) == GPIOK))
20089
20090/******************************** I2C Instances *******************************/
20091#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
20092 ((INSTANCE) == I2C2) || \
20093 ((INSTANCE) == I2C3))
20094
20095/******************************* SMBUS Instances ******************************/
20096#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
20097
20098/******************************** I2S Instances *******************************/
20099
20100#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
20101 ((INSTANCE) == SPI3))
20102
20103/*************************** I2S Extended Instances ***************************/
20104#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
20105 ((INSTANCE) == I2S3ext))
20106/* Legacy Defines */
20107#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
20108
20109/****************************** LTDC Instances ********************************/
20110#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
20111/******************************* RNG Instances ********************************/
20112#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
20113
20114/****************************** RTC Instances *********************************/
20115#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
20116
20117/******************************* SAI Instances ********************************/
20118#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
20119 ((PERIPH) == SAI1_Block_B))
20120/* Legacy define */
20121
20122#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
20123
20124/******************************** SPI Instances *******************************/
20125#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
20126 ((INSTANCE) == SPI2) || \
20127 ((INSTANCE) == SPI3) || \
20128 ((INSTANCE) == SPI4) || \
20129 ((INSTANCE) == SPI5) || \
20130 ((INSTANCE) == SPI6))
20131
20132
20133/****************** TIM Instances : All supported instances *******************/
20134#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20135 ((INSTANCE) == TIM2) || \
20136 ((INSTANCE) == TIM3) || \
20137 ((INSTANCE) == TIM4) || \
20138 ((INSTANCE) == TIM5) || \
20139 ((INSTANCE) == TIM6) || \
20140 ((INSTANCE) == TIM7) || \
20141 ((INSTANCE) == TIM8) || \
20142 ((INSTANCE) == TIM9) || \
20143 ((INSTANCE) == TIM10)|| \
20144 ((INSTANCE) == TIM11)|| \
20145 ((INSTANCE) == TIM12)|| \
20146 ((INSTANCE) == TIM13)|| \
20147 ((INSTANCE) == TIM14))
20148
20149/************* TIM Instances : at least 1 capture/compare channel *************/
20150#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20151 ((INSTANCE) == TIM2) || \
20152 ((INSTANCE) == TIM3) || \
20153 ((INSTANCE) == TIM4) || \
20154 ((INSTANCE) == TIM5) || \
20155 ((INSTANCE) == TIM8) || \
20156 ((INSTANCE) == TIM9) || \
20157 ((INSTANCE) == TIM10) || \
20158 ((INSTANCE) == TIM11) || \
20159 ((INSTANCE) == TIM12) || \
20160 ((INSTANCE) == TIM13) || \
20161 ((INSTANCE) == TIM14))
20162
20163/************ TIM Instances : at least 2 capture/compare channels *************/
20164#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20165 ((INSTANCE) == TIM2) || \
20166 ((INSTANCE) == TIM3) || \
20167 ((INSTANCE) == TIM4) || \
20168 ((INSTANCE) == TIM5) || \
20169 ((INSTANCE) == TIM8) || \
20170 ((INSTANCE) == TIM9) || \
20171 ((INSTANCE) == TIM12))
20172
20173/************ TIM Instances : at least 3 capture/compare channels *************/
20174#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20175 ((INSTANCE) == TIM2) || \
20176 ((INSTANCE) == TIM3) || \
20177 ((INSTANCE) == TIM4) || \
20178 ((INSTANCE) == TIM5) || \
20179 ((INSTANCE) == TIM8))
20180
20181/************ TIM Instances : at least 4 capture/compare channels *************/
20182#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20183 ((INSTANCE) == TIM2) || \
20184 ((INSTANCE) == TIM3) || \
20185 ((INSTANCE) == TIM4) || \
20186 ((INSTANCE) == TIM5) || \
20187 ((INSTANCE) == TIM8))
20188
20189/******************** TIM Instances : Advanced-control timers *****************/
20190#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20191 ((INSTANCE) == TIM8))
20192
20193/******************* TIM Instances : Timer input XOR function *****************/
20194#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20195 ((INSTANCE) == TIM2) || \
20196 ((INSTANCE) == TIM3) || \
20197 ((INSTANCE) == TIM4) || \
20198 ((INSTANCE) == TIM5) || \
20199 ((INSTANCE) == TIM8))
20200
20201/****************** TIM Instances : DMA requests generation (UDE) *************/
20202#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20203 ((INSTANCE) == TIM2) || \
20204 ((INSTANCE) == TIM3) || \
20205 ((INSTANCE) == TIM4) || \
20206 ((INSTANCE) == TIM5) || \
20207 ((INSTANCE) == TIM6) || \
20208 ((INSTANCE) == TIM7) || \
20209 ((INSTANCE) == TIM8))
20210
20211/************ TIM Instances : DMA requests generation (CCxDE) *****************/
20212#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20213 ((INSTANCE) == TIM2) || \
20214 ((INSTANCE) == TIM3) || \
20215 ((INSTANCE) == TIM4) || \
20216 ((INSTANCE) == TIM5) || \
20217 ((INSTANCE) == TIM8))
20218
20219/************ TIM Instances : DMA requests generation (COMDE) *****************/
20220#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20221 ((INSTANCE) == TIM2) || \
20222 ((INSTANCE) == TIM3) || \
20223 ((INSTANCE) == TIM4) || \
20224 ((INSTANCE) == TIM5) || \
20225 ((INSTANCE) == TIM8))
20226
20227/******************** TIM Instances : DMA burst feature ***********************/
20228#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20229 ((INSTANCE) == TIM2) || \
20230 ((INSTANCE) == TIM3) || \
20231 ((INSTANCE) == TIM4) || \
20232 ((INSTANCE) == TIM5) || \
20233 ((INSTANCE) == TIM8))
20234
20235/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
20236#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20237 ((INSTANCE) == TIM2) || \
20238 ((INSTANCE) == TIM3) || \
20239 ((INSTANCE) == TIM4) || \
20240 ((INSTANCE) == TIM5) || \
20241 ((INSTANCE) == TIM6) || \
20242 ((INSTANCE) == TIM7) || \
20243 ((INSTANCE) == TIM8))
20244
20245/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
20246#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20247 ((INSTANCE) == TIM2) || \
20248 ((INSTANCE) == TIM3) || \
20249 ((INSTANCE) == TIM4) || \
20250 ((INSTANCE) == TIM5) || \
20251 ((INSTANCE) == TIM8) || \
20252 ((INSTANCE) == TIM9) || \
20253 ((INSTANCE) == TIM12))
20254/********************** TIM Instances : 32 bit Counter ************************/
20255#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
20256 ((INSTANCE) == TIM5))
20257
20258/***************** TIM Instances : external trigger input available ************/
20259#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20260 ((INSTANCE) == TIM2) || \
20261 ((INSTANCE) == TIM3) || \
20262 ((INSTANCE) == TIM4) || \
20263 ((INSTANCE) == TIM5) || \
20264 ((INSTANCE) == TIM8))
20265
20266/****************** TIM Instances : remapping capability **********************/
20267#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
20268 ((INSTANCE) == TIM5) || \
20269 ((INSTANCE) == TIM11))
20270
20271/******************* TIM Instances : output(s) available **********************/
20272#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
20273 ((((INSTANCE) == TIM1) && \
20274 (((CHANNEL) == TIM_CHANNEL_1) || \
20275 ((CHANNEL) == TIM_CHANNEL_2) || \
20276 ((CHANNEL) == TIM_CHANNEL_3) || \
20277 ((CHANNEL) == TIM_CHANNEL_4))) \
20278 || \
20279 (((INSTANCE) == TIM2) && \
20280 (((CHANNEL) == TIM_CHANNEL_1) || \
20281 ((CHANNEL) == TIM_CHANNEL_2) || \
20282 ((CHANNEL) == TIM_CHANNEL_3) || \
20283 ((CHANNEL) == TIM_CHANNEL_4))) \
20284 || \
20285 (((INSTANCE) == TIM3) && \
20286 (((CHANNEL) == TIM_CHANNEL_1) || \
20287 ((CHANNEL) == TIM_CHANNEL_2) || \
20288 ((CHANNEL) == TIM_CHANNEL_3) || \
20289 ((CHANNEL) == TIM_CHANNEL_4))) \
20290 || \
20291 (((INSTANCE) == TIM4) && \
20292 (((CHANNEL) == TIM_CHANNEL_1) || \
20293 ((CHANNEL) == TIM_CHANNEL_2) || \
20294 ((CHANNEL) == TIM_CHANNEL_3) || \
20295 ((CHANNEL) == TIM_CHANNEL_4))) \
20296 || \
20297 (((INSTANCE) == TIM5) && \
20298 (((CHANNEL) == TIM_CHANNEL_1) || \
20299 ((CHANNEL) == TIM_CHANNEL_2) || \
20300 ((CHANNEL) == TIM_CHANNEL_3) || \
20301 ((CHANNEL) == TIM_CHANNEL_4))) \
20302 || \
20303 (((INSTANCE) == TIM8) && \
20304 (((CHANNEL) == TIM_CHANNEL_1) || \
20305 ((CHANNEL) == TIM_CHANNEL_2) || \
20306 ((CHANNEL) == TIM_CHANNEL_3) || \
20307 ((CHANNEL) == TIM_CHANNEL_4))) \
20308 || \
20309 (((INSTANCE) == TIM9) && \
20310 (((CHANNEL) == TIM_CHANNEL_1) || \
20311 ((CHANNEL) == TIM_CHANNEL_2))) \
20312 || \
20313 (((INSTANCE) == TIM10) && \
20314 (((CHANNEL) == TIM_CHANNEL_1))) \
20315 || \
20316 (((INSTANCE) == TIM11) && \
20317 (((CHANNEL) == TIM_CHANNEL_1))) \
20318 || \
20319 (((INSTANCE) == TIM12) && \
20320 (((CHANNEL) == TIM_CHANNEL_1) || \
20321 ((CHANNEL) == TIM_CHANNEL_2))) \
20322 || \
20323 (((INSTANCE) == TIM13) && \
20324 (((CHANNEL) == TIM_CHANNEL_1))) \
20325 || \
20326 (((INSTANCE) == TIM14) && \
20327 (((CHANNEL) == TIM_CHANNEL_1))))
20328
20329/************ TIM Instances : complementary output(s) available ***************/
20330#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
20331 ((((INSTANCE) == TIM1) && \
20332 (((CHANNEL) == TIM_CHANNEL_1) || \
20333 ((CHANNEL) == TIM_CHANNEL_2) || \
20334 ((CHANNEL) == TIM_CHANNEL_3))) \
20335 || \
20336 (((INSTANCE) == TIM8) && \
20337 (((CHANNEL) == TIM_CHANNEL_1) || \
20338 ((CHANNEL) == TIM_CHANNEL_2) || \
20339 ((CHANNEL) == TIM_CHANNEL_3))))
20340
20341/****************** TIM Instances : supporting counting mode selection ********/
20342#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20343 ((INSTANCE) == TIM2) || \
20344 ((INSTANCE) == TIM3) || \
20345 ((INSTANCE) == TIM4) || \
20346 ((INSTANCE) == TIM5) || \
20347 ((INSTANCE) == TIM8))
20348
20349/****************** TIM Instances : supporting clock division *****************/
20350#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20351 ((INSTANCE) == TIM2) || \
20352 ((INSTANCE) == TIM3) || \
20353 ((INSTANCE) == TIM4) || \
20354 ((INSTANCE) == TIM5) || \
20355 ((INSTANCE) == TIM8) || \
20356 ((INSTANCE) == TIM9) || \
20357 ((INSTANCE) == TIM10)|| \
20358 ((INSTANCE) == TIM11)|| \
20359 ((INSTANCE) == TIM12)|| \
20360 ((INSTANCE) == TIM13)|| \
20361 ((INSTANCE) == TIM14))
20362
20363/****************** TIM Instances : supporting commutation event generation ***/
20364#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
20365 ((INSTANCE) == TIM8))
20366
20367
20368/****************** TIM Instances : supporting OCxREF clear *******************/
20369#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20370 ((INSTANCE) == TIM2) || \
20371 ((INSTANCE) == TIM3) || \
20372 ((INSTANCE) == TIM4) || \
20373 ((INSTANCE) == TIM5) || \
20374 ((INSTANCE) == TIM8))
20375
20376/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
20377#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20378 ((INSTANCE) == TIM2) || \
20379 ((INSTANCE) == TIM3) || \
20380 ((INSTANCE) == TIM4) || \
20381 ((INSTANCE) == TIM5) || \
20382 ((INSTANCE) == TIM8) || \
20383 ((INSTANCE) == TIM9) || \
20384 ((INSTANCE) == TIM12))
20385
20386/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
20387#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20388 ((INSTANCE) == TIM2) || \
20389 ((INSTANCE) == TIM3) || \
20390 ((INSTANCE) == TIM4) || \
20391 ((INSTANCE) == TIM5) || \
20392 ((INSTANCE) == TIM8))
20393
20394/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
20395#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20396 ((INSTANCE) == TIM2) || \
20397 ((INSTANCE) == TIM3) || \
20398 ((INSTANCE) == TIM4) || \
20399 ((INSTANCE) == TIM5) || \
20400 ((INSTANCE) == TIM8) || \
20401 ((INSTANCE) == TIM9) || \
20402 ((INSTANCE) == TIM12))
20403
20404/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
20405#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20406 ((INSTANCE) == TIM2) || \
20407 ((INSTANCE) == TIM3) || \
20408 ((INSTANCE) == TIM4) || \
20409 ((INSTANCE) == TIM5) || \
20410 ((INSTANCE) == TIM8) || \
20411 ((INSTANCE) == TIM9) || \
20412 ((INSTANCE) == TIM12))
20413
20414/****************** TIM Instances : supporting repetition counter *************/
20415#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20416 ((INSTANCE) == TIM8))
20417
20418/****************** TIM Instances : supporting encoder interface **************/
20419#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20420 ((INSTANCE) == TIM2) || \
20421 ((INSTANCE) == TIM3) || \
20422 ((INSTANCE) == TIM4) || \
20423 ((INSTANCE) == TIM5) || \
20424 ((INSTANCE) == TIM8) || \
20425 ((INSTANCE) == TIM9) || \
20426 ((INSTANCE) == TIM12))
20427/****************** TIM Instances : supporting Hall sensor interface **********/
20428#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20429 ((INSTANCE) == TIM2) || \
20430 ((INSTANCE) == TIM3) || \
20431 ((INSTANCE) == TIM4) || \
20432 ((INSTANCE) == TIM5) || \
20433 ((INSTANCE) == TIM8))
20434/****************** TIM Instances : supporting the break function *************/
20435#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20436 ((INSTANCE) == TIM8))
20437
20438/******************** USART Instances : Synchronous mode **********************/
20439#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20440 ((INSTANCE) == USART2) || \
20441 ((INSTANCE) == USART3) || \
20442 ((INSTANCE) == USART6))
20443
20444/******************** UART Instances : Half-Duplex mode **********************/
20445#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20446 ((INSTANCE) == USART2) || \
20447 ((INSTANCE) == USART3) || \
20448 ((INSTANCE) == UART4) || \
20449 ((INSTANCE) == UART5) || \
20450 ((INSTANCE) == USART6) || \
20451 ((INSTANCE) == UART7) || \
20452 ((INSTANCE) == UART8))
20453
20454/* Legacy defines */
20455#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
20456
20457/****************** UART Instances : Hardware Flow control ********************/
20458#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20459 ((INSTANCE) == USART2) || \
20460 ((INSTANCE) == USART3) || \
20461 ((INSTANCE) == USART6))
20462/******************** UART Instances : LIN mode **********************/
20463#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
20464
20465/********************* UART Instances : Smart card mode ***********************/
20466#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20467 ((INSTANCE) == USART2) || \
20468 ((INSTANCE) == USART3) || \
20469 ((INSTANCE) == USART6))
20470
20471/*********************** UART Instances : IRDA mode ***************************/
20472#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20473 ((INSTANCE) == USART2) || \
20474 ((INSTANCE) == USART3) || \
20475 ((INSTANCE) == UART4) || \
20476 ((INSTANCE) == UART5) || \
20477 ((INSTANCE) == USART6) || \
20478 ((INSTANCE) == UART7) || \
20479 ((INSTANCE) == UART8))
20480
20481/*********************** PCD Instances ****************************************/
20482#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20483 ((INSTANCE) == USB_OTG_HS))
20484
20485/*********************** HCD Instances ****************************************/
20486#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20487 ((INSTANCE) == USB_OTG_HS))
20488
20489/****************************** SDIO Instances ********************************/
20490#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
20491
20492/****************************** IWDG Instances ********************************/
20493#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
20494
20495/****************************** WWDG Instances ********************************/
20496#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
20497
20498
20499/****************************** QSPI Instances ********************************/
20500#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
20501/****************************** USB Exported Constants ************************/
20502#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
20503#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
20504#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
20505#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
20506#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
20507#define USB_OTG_HS_MAX_IN_ENDPOINTS 9U /* Including EP0 */
20508#define USB_OTG_HS_MAX_OUT_ENDPOINTS 9U /* Including EP0 */
20509#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
20510
20511/*
20512 * @brief Specific devices reset values definitions
20513 */
20514#define RCC_PLLCFGR_RST_VALUE 0x24003010U
20515#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
20516#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
20517
20518#define RCC_MAX_FREQUENCY 180000000U
20519#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
20520#define RCC_MAX_FREQUENCY_SCALE2 168000000U
20521#define RCC_MAX_FREQUENCY_SCALE3 120000000U
20522#define RCC_PLLVCO_OUTPUT_MIN 192000000U
20523#define RCC_PLLVCO_INPUT_MIN 950000U
20524#define RCC_PLLVCO_INPUT_MAX 2100000U
20525#define RCC_PLLVCO_OUTPUT_MAX 432000000U
20527#define RCC_PLLN_MIN_VALUE 50U
20528#define RCC_PLLN_MAX_VALUE 432U
20529
20530#define FLASH_SCALE1_LATENCY1_FREQ 30000000U
20531#define FLASH_SCALE1_LATENCY2_FREQ 60000000U
20532#define FLASH_SCALE1_LATENCY3_FREQ 90000000U
20533#define FLASH_SCALE1_LATENCY4_FREQ 120000000U
20534#define FLASH_SCALE1_LATENCY5_FREQ 150000000U
20536#define FLASH_SCALE2_LATENCY1_FREQ 30000000U
20537#define FLASH_SCALE2_LATENCY2_FREQ 60000000U
20538#define FLASH_SCALE2_LATENCY3_FREQ 90000000U
20539#define FLASH_SCALE2_LATENCY4_FREQ 12000000U
20540#define FLASH_SCALE2_LATENCY5_FREQ 150000000U
20542#define FLASH_SCALE3_LATENCY1_FREQ 30000000U
20543#define FLASH_SCALE3_LATENCY2_FREQ 60000000U
20544#define FLASH_SCALE3_LATENCY3_FREQ 90000000U
20546/******************************************************************************/
20547/* For a painless codes migration between the STM32F4xx device product */
20548/* lines, the aliases defined below are put in place to overcome the */
20549/* differences in the interrupt handlers and IRQn definitions. */
20550/* No need to update developed interrupt code when moving across */
20551/* product lines within the same STM32F4 Family */
20552/******************************************************************************/
20553/* Aliases for __IRQn */
20554#define FSMC_IRQn FMC_IRQn
20555
20556/* Aliases for __IRQHandler */
20557#define FSMC_IRQHandler FMC_IRQHandler
20558
20571#ifdef __cplusplus
20572}
20573#endif /* __cplusplus */
20574
20575#endif /* __STM32F479xx_H */
__IO
#define __IO
Definition core_cm3.h:170
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
PMC
#define PMC
Definition MK60D10.h:8809
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f479xx.h:66
PendSV_IRQn
@ PendSV_IRQn
Definition stm32f479xx.h:74
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition stm32f479xx.h:139
EXTI2_IRQn
@ EXTI2_IRQn
Definition stm32f479xx.h:85
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition stm32f479xx.h:90
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition stm32f479xx.h:99
SDIO_IRQn
@ SDIO_IRQn
Definition stm32f479xx.h:126
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition stm32f479xx.h:80
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition stm32f479xx.h:152
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition stm32f479xx.h:133
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition stm32f479xx.h:146
UART7_IRQn
@ UART7_IRQn
Definition stm32f479xx.h:159
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition stm32f479xx.h:109
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition stm32f479xx.h:110
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition stm32f479xx.h:69
SAI1_IRQn
@ SAI1_IRQn
Definition stm32f479xx.h:164
TIM4_IRQn
@ TIM4_IRQn
Definition stm32f479xx.h:107
TIM2_IRQn
@ TIM2_IRQn
Definition stm32f479xx.h:105
LTDC_ER_IRQn
@ LTDC_ER_IRQn
Definition stm32f479xx.h:166
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition stm32f479xx.h:147
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition stm32f479xx.h:120
USART2_IRQn
@ USART2_IRQn
Definition stm32f479xx.h:115
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition stm32f479xx.h:136
SVCall_IRQn
@ SVCall_IRQn
Definition stm32f479xx.h:72
ADC_IRQn
@ ADC_IRQn
Definition stm32f479xx.h:95
SPI3_IRQn
@ SPI3_IRQn
Definition stm32f479xx.h:128
SPI2_IRQn
@ SPI2_IRQn
Definition stm32f479xx.h:113
TIM7_IRQn
@ TIM7_IRQn
Definition stm32f479xx.h:132
UART8_IRQn
@ UART8_IRQn
Definition stm32f479xx.h:160
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition stm32f479xx.h:143
RCC_IRQn
@ RCC_IRQn
Definition stm32f479xx.h:82
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition stm32f479xx.h:131
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition stm32f479xx.h:151
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition stm32f479xx.h:111
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition stm32f479xx.h:168
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition stm32f479xx.h:123
UsageFault_IRQn
@ UsageFault_IRQn
Definition stm32f479xx.h:71
SysTick_IRQn
@ SysTick_IRQn
Definition stm32f479xx.h:75
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition stm32f479xx.h:150
CRYP_IRQn
@ CRYP_IRQn
Definition stm32f479xx.h:156
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition stm32f479xx.h:149
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition stm32f479xx.h:141
BusFault_IRQn
@ BusFault_IRQn
Definition stm32f479xx.h:70
HASH_RNG_IRQn
@ HASH_RNG_IRQn
Definition stm32f479xx.h:157
SPI5_IRQn
@ SPI5_IRQn
Definition stm32f479xx.h:162
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition stm32f479xx.h:73
FLASH_IRQn
@ FLASH_IRQn
Definition stm32f479xx.h:81
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition stm32f479xx.h:145
WWDG_IRQn
@ WWDG_IRQn
Definition stm32f479xx.h:77
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition stm32f479xx.h:108
TIM3_IRQn
@ TIM3_IRQn
Definition stm32f479xx.h:106
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition stm32f479xx.h:134
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition stm32f479xx.h:96
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition stm32f479xx.h:153
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition stm32f479xx.h:88
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition stm32f479xx.h:117
SPI4_IRQn
@ SPI4_IRQn
Definition stm32f479xx.h:161
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f479xx.h:102
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition stm32f479xx.h:100
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition stm32f479xx.h:89
SPI6_IRQn
@ SPI6_IRQn
Definition stm32f479xx.h:163
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition stm32f479xx.h:144
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition stm32f479xx.h:119
FPU_IRQn
@ FPU_IRQn
Definition stm32f479xx.h:158
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition stm32f479xx.h:121
USART6_IRQn
@ USART6_IRQn
Definition stm32f479xx.h:148
SPI1_IRQn
@ SPI1_IRQn
Definition stm32f479xx.h:112
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition stm32f479xx.h:154
PVD_IRQn
@ PVD_IRQn
Definition stm32f479xx.h:78
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f479xx.h:103
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition stm32f479xx.h:101
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition stm32f479xx.h:142
FMC_IRQn
@ FMC_IRQn
Definition stm32f479xx.h:125
EXTI0_IRQn
@ EXTI0_IRQn
Definition stm32f479xx.h:83
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition stm32f479xx.h:97
EXTI4_IRQn
@ EXTI4_IRQn
Definition stm32f479xx.h:87
DSI_IRQn
@ DSI_IRQn
Definition stm32f479xx.h:169
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition stm32f479xx.h:135
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f479xx.h:79
UART5_IRQn
@ UART5_IRQn
Definition stm32f479xx.h:130
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition stm32f479xx.h:93
DMA2D_IRQn
@ DMA2D_IRQn
Definition stm32f479xx.h:167
DCMI_IRQn
@ DCMI_IRQn
Definition stm32f479xx.h:155
ETH_IRQn
@ ETH_IRQn
Definition stm32f479xx.h:138
USART1_IRQn
@ USART1_IRQn
Definition stm32f479xx.h:114
EXTI3_IRQn
@ EXTI3_IRQn
Definition stm32f479xx.h:86
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition stm32f479xx.h:68
UART4_IRQn
@ UART4_IRQn
Definition stm32f479xx.h:129
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition stm32f479xx.h:122
EXTI1_IRQn
@ EXTI1_IRQn
Definition stm32f479xx.h:84
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition stm32f479xx.h:137
TIM5_IRQn
@ TIM5_IRQn
Definition stm32f479xx.h:127
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition stm32f479xx.h:124
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f479xx.h:92
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition stm32f479xx.h:94
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition stm32f479xx.h:104
LTDC_IRQn
@ LTDC_IRQn
Definition stm32f479xx.h:165
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition stm32f479xx.h:140
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition stm32f479xx.h:98
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition stm32f479xx.h:91
USART3_IRQn
@ USART3_IRQn
Definition stm32f479xx.h:116
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition stm32f479xx.h:118
ADC_Common_TypeDef
Definition stm32f107xc.h:187
ADC_TypeDef
Analog to Digital Converter
Definition stm32f107xc.h:163
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition stm32f107xc.h:267
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition stm32f107xc.h:279
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition stm32f107xc.h:255
CAN_TypeDef
Controller Area Network.
Definition stm32f107xc.h:289
CRC_TypeDef
CRC calculation unit.
Definition stm32f107xc.h:319
CRYP_TypeDef
Crypto Processor.
Definition stm32f217xx.h:784
DAC_TypeDef
Digital to Analog Converter.
Definition stm32f107xc.h:332
DBGMCU_TypeDef
Debug MCU.
Definition stm32f107xc.h:353
DCMI_TypeDef
DCMI.
Definition stm32f207xx.h:325
DMA2D_TypeDef
DMA2D Controller.
Definition stm32f427xx.h:373
DMA_Stream_TypeDef
DMA Controller.
Definition stm32f207xx.h:344
DMA_TypeDef
Definition stm32f107xc.h:371
DSI_TypeDef
DSI Controller.
Definition stm32f469xx.h:408
ETH_TypeDef
Ethernet MAC.
Definition stm32f107xc.h:383
EXTI_TypeDef
External Interrupt/Event Controller.
Definition stm32f107xc.h:455
FLASH_TypeDef
FLASH Registers.
Definition stm32f107xc.h:469
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition stm32f427xx.h:517
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition stm32f427xx.h:508
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition stm32f469xx.h:611
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition stm32f427xx.h:560
GPIO_TypeDef
General Purpose I/O.
Definition stm32f107xc.h:502
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition stm32f417xx.h:843
HASH_TypeDef
HASH.
Definition stm32f217xx.h:812
I2C_TypeDef
Inter Integrated Circuit Interface.
Definition stm32f107xc.h:529
IWDG_TypeDef
Independent WATCHDOG.
Definition stm32f107xc.h:546
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition stm32f429xx.h:660
LTDC_TypeDef
LCD-TFT Display Controller.
Definition stm32f429xx.h:635
PWR_TypeDef
Power Control.
Definition stm32f107xc.h:558
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition stm32f469xx.h:909
RCC_TypeDef
Reset and Clock Control.
Definition stm32f107xc.h:568
RNG_TypeDef
RNG.
Definition stm32f207xx.h:782
RTC_TypeDef
Real-Time Clock.
Definition stm32f107xc.h:590
SAI_Block_TypeDef
Definition stm32f427xx.h:737
SAI_TypeDef
Serial Audio Interface.
Definition stm32f427xx.h:732
SDIO_TypeDef
SD host Interface.
Definition stm32f207xx.h:682
SPI_TypeDef
Serial Peripheral Interface.
Definition stm32f107xc.h:608
SYSCFG_TypeDef
System configuration controller.
Definition stm32f207xx.h:542
TIM_TypeDef
TIM Timers.
Definition stm32f107xc.h:624
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32f107xc.h:654
USB_OTG_DeviceTypeDef
__device_Registers
Definition stm32f107xc.h:696
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition stm32f107xc.h:670
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition stm32f107xc.h:770
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition stm32f107xc.h:755
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition stm32f107xc.h:724
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition stm32f107xc.h:740
WWDG_TypeDef
Window WATCHDOG.
Definition stm32f107xc.h:785
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.