mikroSDK Reference Manual
stm32f745xx.h
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1
33#ifndef __STM32F745xx_H
34#define __STM32F745xx_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
48typedef enum
49{
50/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
51 NonMaskableInt_IRQn = -14,
52 MemoryManagement_IRQn = -12,
53 BusFault_IRQn = -11,
54 UsageFault_IRQn = -10,
55 SVCall_IRQn = -5,
56 DebugMonitor_IRQn = -4,
57 PendSV_IRQn = -2,
58 SysTick_IRQn = -1,
59/****** STM32 specific Interrupt Numbers **********************************************************************/
60 WWDG_IRQn = 0,
61 PVD_IRQn = 1,
62 TAMP_STAMP_IRQn = 2,
63 RTC_WKUP_IRQn = 3,
64 FLASH_IRQn = 4,
65 RCC_IRQn = 5,
66 EXTI0_IRQn = 6,
67 EXTI1_IRQn = 7,
68 EXTI2_IRQn = 8,
69 EXTI3_IRQn = 9,
70 EXTI4_IRQn = 10,
71 DMA1_Stream0_IRQn = 11,
72 DMA1_Stream1_IRQn = 12,
73 DMA1_Stream2_IRQn = 13,
74 DMA1_Stream3_IRQn = 14,
75 DMA1_Stream4_IRQn = 15,
76 DMA1_Stream5_IRQn = 16,
77 DMA1_Stream6_IRQn = 17,
78 ADC_IRQn = 18,
79 CAN1_TX_IRQn = 19,
80 CAN1_RX0_IRQn = 20,
81 CAN1_RX1_IRQn = 21,
82 CAN1_SCE_IRQn = 22,
83 EXTI9_5_IRQn = 23,
84 TIM1_BRK_TIM9_IRQn = 24,
85 TIM1_UP_TIM10_IRQn = 25,
86 TIM1_TRG_COM_TIM11_IRQn = 26,
87 TIM1_CC_IRQn = 27,
88 TIM2_IRQn = 28,
89 TIM3_IRQn = 29,
90 TIM4_IRQn = 30,
91 I2C1_EV_IRQn = 31,
92 I2C1_ER_IRQn = 32,
93 I2C2_EV_IRQn = 33,
94 I2C2_ER_IRQn = 34,
95 SPI1_IRQn = 35,
96 SPI2_IRQn = 36,
97 USART1_IRQn = 37,
98 USART2_IRQn = 38,
99 USART3_IRQn = 39,
100 EXTI15_10_IRQn = 40,
101 RTC_Alarm_IRQn = 41,
102 OTG_FS_WKUP_IRQn = 42,
103 TIM8_BRK_TIM12_IRQn = 43,
104 TIM8_UP_TIM13_IRQn = 44,
105 TIM8_TRG_COM_TIM14_IRQn = 45,
106 TIM8_CC_IRQn = 46,
107 DMA1_Stream7_IRQn = 47,
108 FMC_IRQn = 48,
109 SDMMC1_IRQn = 49,
110 TIM5_IRQn = 50,
111 SPI3_IRQn = 51,
112 UART4_IRQn = 52,
113 UART5_IRQn = 53,
114 TIM6_DAC_IRQn = 54,
115 TIM7_IRQn = 55,
116 DMA2_Stream0_IRQn = 56,
117 DMA2_Stream1_IRQn = 57,
118 DMA2_Stream2_IRQn = 58,
119 DMA2_Stream3_IRQn = 59,
120 DMA2_Stream4_IRQn = 60,
121 ETH_IRQn = 61,
122 ETH_WKUP_IRQn = 62,
123 CAN2_TX_IRQn = 63,
124 CAN2_RX0_IRQn = 64,
125 CAN2_RX1_IRQn = 65,
126 CAN2_SCE_IRQn = 66,
127 OTG_FS_IRQn = 67,
128 DMA2_Stream5_IRQn = 68,
129 DMA2_Stream6_IRQn = 69,
130 DMA2_Stream7_IRQn = 70,
131 USART6_IRQn = 71,
132 I2C3_EV_IRQn = 72,
133 I2C3_ER_IRQn = 73,
134 OTG_HS_EP1_OUT_IRQn = 74,
135 OTG_HS_EP1_IN_IRQn = 75,
136 OTG_HS_WKUP_IRQn = 76,
137 OTG_HS_IRQn = 77,
138 DCMI_IRQn = 78,
139 RNG_IRQn = 80,
140 FPU_IRQn = 81,
141 UART7_IRQn = 82,
142 UART8_IRQn = 83,
143 SPI4_IRQn = 84,
144 SPI5_IRQn = 85,
145 SPI6_IRQn = 86,
146 SAI1_IRQn = 87,
147 DMA2D_IRQn = 90,
148 SAI2_IRQn = 91,
149 QUADSPI_IRQn = 92,
150 LPTIM1_IRQn = 93,
151 CEC_IRQn = 94,
152 I2C4_EV_IRQn = 95,
153 I2C4_ER_IRQn = 96,
154 SPDIF_RX_IRQn = 97,
155} IRQn_Type;
156
164#define __CM7_REV 0x0001U
165#define __MPU_PRESENT 1U
166#define __NVIC_PRIO_BITS 4U
167#define __Vendor_SysTickConfig 0U
168#define __FPU_PRESENT 1U
169#define __ICACHE_PRESENT 1U
170#define __DCACHE_PRESENT 1U
171#include "core_cm7.h"
174#include "system_stm32f7xx.h"
175#include <stdint.h>
176
185typedef struct
186{
187 __IO uint32_t SR;
188 __IO uint32_t CR1;
189 __IO uint32_t CR2;
190 __IO uint32_t SMPR1;
191 __IO uint32_t SMPR2;
192 __IO uint32_t JOFR1;
193 __IO uint32_t JOFR2;
194 __IO uint32_t JOFR3;
195 __IO uint32_t JOFR4;
196 __IO uint32_t HTR;
197 __IO uint32_t LTR;
198 __IO uint32_t SQR1;
199 __IO uint32_t SQR2;
200 __IO uint32_t SQR3;
201 __IO uint32_t JSQR;
202 __IO uint32_t JDR1;
203 __IO uint32_t JDR2;
204 __IO uint32_t JDR3;
205 __IO uint32_t JDR4;
206 __IO uint32_t DR;
207} ADC_TypeDef;
208
209typedef struct
210{
211 __IO uint32_t CSR;
212 __IO uint32_t CCR;
213 __IO uint32_t CDR;
215} ADC_Common_TypeDef;
216
217
222typedef struct
223{
224 __IO uint32_t TIR;
225 __IO uint32_t TDTR;
226 __IO uint32_t TDLR;
227 __IO uint32_t TDHR;
228} CAN_TxMailBox_TypeDef;
229
234typedef struct
235{
236 __IO uint32_t RIR;
237 __IO uint32_t RDTR;
238 __IO uint32_t RDLR;
239 __IO uint32_t RDHR;
240} CAN_FIFOMailBox_TypeDef;
241
246typedef struct
247{
248 __IO uint32_t FR1;
249 __IO uint32_t FR2;
250} CAN_FilterRegister_TypeDef;
251
256typedef struct
257{
258 __IO uint32_t MCR;
259 __IO uint32_t MSR;
260 __IO uint32_t TSR;
261 __IO uint32_t RF0R;
262 __IO uint32_t RF1R;
263 __IO uint32_t IER;
264 __IO uint32_t ESR;
265 __IO uint32_t BTR;
266 uint32_t RESERVED0[88];
267 CAN_TxMailBox_TypeDef sTxMailBox[3];
268 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
269 uint32_t RESERVED1[12];
270 __IO uint32_t FMR;
271 __IO uint32_t FM1R;
272 uint32_t RESERVED2;
273 __IO uint32_t FS1R;
274 uint32_t RESERVED3;
275 __IO uint32_t FFA1R;
276 uint32_t RESERVED4;
277 __IO uint32_t FA1R;
278 uint32_t RESERVED5[8];
279 CAN_FilterRegister_TypeDef sFilterRegister[28];
280} CAN_TypeDef;
281
286typedef struct
287{
288 __IO uint32_t CR;
289 __IO uint32_t CFGR;
290 __IO uint32_t TXDR;
291 __IO uint32_t RXDR;
292 __IO uint32_t ISR;
293 __IO uint32_t IER;
294}CEC_TypeDef;
295
300typedef struct
301{
302 __IO uint32_t DR;
303 __IO uint8_t IDR;
304 uint8_t RESERVED0;
305 uint16_t RESERVED1;
306 __IO uint32_t CR;
307 uint32_t RESERVED2;
308 __IO uint32_t INIT;
309 __IO uint32_t POL;
310} CRC_TypeDef;
311
316typedef struct
317{
318 __IO uint32_t CR;
319 __IO uint32_t SWTRIGR;
320 __IO uint32_t DHR12R1;
321 __IO uint32_t DHR12L1;
322 __IO uint32_t DHR8R1;
323 __IO uint32_t DHR12R2;
324 __IO uint32_t DHR12L2;
325 __IO uint32_t DHR8R2;
326 __IO uint32_t DHR12RD;
327 __IO uint32_t DHR12LD;
328 __IO uint32_t DHR8RD;
329 __IO uint32_t DOR1;
330 __IO uint32_t DOR2;
331 __IO uint32_t SR;
332} DAC_TypeDef;
333
334
339typedef struct
340{
341 __IO uint32_t IDCODE;
342 __IO uint32_t CR;
343 __IO uint32_t APB1FZ;
344 __IO uint32_t APB2FZ;
345}DBGMCU_TypeDef;
346
351typedef struct
352{
353 __IO uint32_t CR;
354 __IO uint32_t SR;
355 __IO uint32_t RISR;
356 __IO uint32_t IER;
357 __IO uint32_t MISR;
358 __IO uint32_t ICR;
359 __IO uint32_t ESCR;
360 __IO uint32_t ESUR;
361 __IO uint32_t CWSTRTR;
362 __IO uint32_t CWSIZER;
363 __IO uint32_t DR;
364} DCMI_TypeDef;
365
370typedef struct
371{
372 __IO uint32_t CR;
373 __IO uint32_t NDTR;
374 __IO uint32_t PAR;
375 __IO uint32_t M0AR;
376 __IO uint32_t M1AR;
377 __IO uint32_t FCR;
378} DMA_Stream_TypeDef;
379
380typedef struct
381{
382 __IO uint32_t LISR;
383 __IO uint32_t HISR;
384 __IO uint32_t LIFCR;
385 __IO uint32_t HIFCR;
386} DMA_TypeDef;
387
392typedef struct
393{
394 __IO uint32_t CR;
395 __IO uint32_t ISR;
396 __IO uint32_t IFCR;
397 __IO uint32_t FGMAR;
398 __IO uint32_t FGOR;
399 __IO uint32_t BGMAR;
400 __IO uint32_t BGOR;
401 __IO uint32_t FGPFCCR;
402 __IO uint32_t FGCOLR;
403 __IO uint32_t BGPFCCR;
404 __IO uint32_t BGCOLR;
405 __IO uint32_t FGCMAR;
406 __IO uint32_t BGCMAR;
407 __IO uint32_t OPFCCR;
408 __IO uint32_t OCOLR;
409 __IO uint32_t OMAR;
410 __IO uint32_t OOR;
411 __IO uint32_t NLR;
412 __IO uint32_t LWR;
413 __IO uint32_t AMTCR;
414 uint32_t RESERVED[236];
415 __IO uint32_t FGCLUT[256];
416 __IO uint32_t BGCLUT[256];
417} DMA2D_TypeDef;
418
419
424typedef struct
425{
426 __IO uint32_t MACCR;
427 __IO uint32_t MACFFR;
428 __IO uint32_t MACHTHR;
429 __IO uint32_t MACHTLR;
430 __IO uint32_t MACMIIAR;
431 __IO uint32_t MACMIIDR;
432 __IO uint32_t MACFCR;
433 __IO uint32_t MACVLANTR; /* 8 */
434 uint32_t RESERVED0[2];
435 __IO uint32_t MACRWUFFR; /* 11 */
436 __IO uint32_t MACPMTCSR;
437 uint32_t RESERVED1;
438 __IO uint32_t MACDBGR;
439 __IO uint32_t MACSR; /* 15 */
440 __IO uint32_t MACIMR;
441 __IO uint32_t MACA0HR;
442 __IO uint32_t MACA0LR;
443 __IO uint32_t MACA1HR;
444 __IO uint32_t MACA1LR;
445 __IO uint32_t MACA2HR;
446 __IO uint32_t MACA2LR;
447 __IO uint32_t MACA3HR;
448 __IO uint32_t MACA3LR; /* 24 */
449 uint32_t RESERVED2[40];
450 __IO uint32_t MMCCR; /* 65 */
451 __IO uint32_t MMCRIR;
452 __IO uint32_t MMCTIR;
453 __IO uint32_t MMCRIMR;
454 __IO uint32_t MMCTIMR; /* 69 */
455 uint32_t RESERVED3[14];
456 __IO uint32_t MMCTGFSCCR; /* 84 */
457 __IO uint32_t MMCTGFMSCCR;
458 uint32_t RESERVED4[5];
459 __IO uint32_t MMCTGFCR;
460 uint32_t RESERVED5[10];
461 __IO uint32_t MMCRFCECR;
462 __IO uint32_t MMCRFAECR;
463 uint32_t RESERVED6[10];
464 __IO uint32_t MMCRGUFCR;
465 uint32_t RESERVED7[334];
466 __IO uint32_t PTPTSCR;
467 __IO uint32_t PTPSSIR;
468 __IO uint32_t PTPTSHR;
469 __IO uint32_t PTPTSLR;
470 __IO uint32_t PTPTSHUR;
471 __IO uint32_t PTPTSLUR;
472 __IO uint32_t PTPTSAR;
473 __IO uint32_t PTPTTHR;
474 __IO uint32_t PTPTTLR;
475 __IO uint32_t RESERVED8;
476 __IO uint32_t PTPTSSR;
477 __IO uint32_t PTPPPSCR;
478 uint32_t RESERVED9[564];
479 __IO uint32_t DMABMR;
480 __IO uint32_t DMATPDR;
481 __IO uint32_t DMARPDR;
482 __IO uint32_t DMARDLAR;
483 __IO uint32_t DMATDLAR;
484 __IO uint32_t DMASR;
485 __IO uint32_t DMAOMR;
486 __IO uint32_t DMAIER;
487 __IO uint32_t DMAMFBOCR;
488 __IO uint32_t DMARSWTR;
489 uint32_t RESERVED10[8];
490 __IO uint32_t DMACHTDR;
491 __IO uint32_t DMACHRDR;
492 __IO uint32_t DMACHTBAR;
493 __IO uint32_t DMACHRBAR;
494} ETH_TypeDef;
495
500typedef struct
501{
502 __IO uint32_t IMR;
503 __IO uint32_t EMR;
504 __IO uint32_t RTSR;
505 __IO uint32_t FTSR;
506 __IO uint32_t SWIER;
507 __IO uint32_t PR;
508} EXTI_TypeDef;
509
514typedef struct
515{
516 __IO uint32_t ACR;
517 __IO uint32_t KEYR;
518 __IO uint32_t OPTKEYR;
519 __IO uint32_t SR;
520 __IO uint32_t CR;
521 __IO uint32_t OPTCR;
522 __IO uint32_t OPTCR1;
523} FLASH_TypeDef;
524
525
526
531typedef struct
532{
533 __IO uint32_t BTCR[8];
534} FMC_Bank1_TypeDef;
535
540typedef struct
541{
542 __IO uint32_t BWTR[7];
543} FMC_Bank1E_TypeDef;
544
549typedef struct
550{
551 __IO uint32_t PCR;
552 __IO uint32_t SR;
553 __IO uint32_t PMEM;
554 __IO uint32_t PATT;
555 uint32_t RESERVED0;
556 __IO uint32_t ECCR;
557} FMC_Bank3_TypeDef;
558
563typedef struct
564{
565 __IO uint32_t SDCR[2];
566 __IO uint32_t SDTR[2];
567 __IO uint32_t SDCMR;
568 __IO uint32_t SDRTR;
569 __IO uint32_t SDSR;
570} FMC_Bank5_6_TypeDef;
571
572
577typedef struct
578{
579 __IO uint32_t MODER;
580 __IO uint32_t OTYPER;
581 __IO uint32_t OSPEEDR;
582 __IO uint32_t PUPDR;
583 __IO uint32_t IDR;
584 __IO uint32_t ODR;
585 __IO uint32_t BSRR;
586 __IO uint32_t LCKR;
587 __IO uint32_t AFR[2];
588} GPIO_TypeDef;
589
594typedef struct
595{
596 __IO uint32_t MEMRMP;
597 __IO uint32_t PMC;
598 __IO uint32_t EXTICR[4];
599 uint32_t RESERVED[2];
600 __IO uint32_t CMPCR;
601} SYSCFG_TypeDef;
602
607typedef struct
608{
609 __IO uint32_t CR1;
610 __IO uint32_t CR2;
611 __IO uint32_t OAR1;
612 __IO uint32_t OAR2;
613 __IO uint32_t TIMINGR;
614 __IO uint32_t TIMEOUTR;
615 __IO uint32_t ISR;
616 __IO uint32_t ICR;
617 __IO uint32_t PECR;
618 __IO uint32_t RXDR;
619 __IO uint32_t TXDR;
620} I2C_TypeDef;
621
626typedef struct
627{
628 __IO uint32_t KR;
629 __IO uint32_t PR;
630 __IO uint32_t RLR;
631 __IO uint32_t SR;
632 __IO uint32_t WINR;
633} IWDG_TypeDef;
634
635
636
641typedef struct
642{
643 __IO uint32_t CR1;
644 __IO uint32_t CSR1;
645 __IO uint32_t CR2;
646 __IO uint32_t CSR2;
647} PWR_TypeDef;
648
649
654typedef struct
655{
656 __IO uint32_t CR;
657 __IO uint32_t PLLCFGR;
658 __IO uint32_t CFGR;
659 __IO uint32_t CIR;
660 __IO uint32_t AHB1RSTR;
661 __IO uint32_t AHB2RSTR;
662 __IO uint32_t AHB3RSTR;
663 uint32_t RESERVED0;
664 __IO uint32_t APB1RSTR;
665 __IO uint32_t APB2RSTR;
666 uint32_t RESERVED1[2];
667 __IO uint32_t AHB1ENR;
668 __IO uint32_t AHB2ENR;
669 __IO uint32_t AHB3ENR;
670 uint32_t RESERVED2;
671 __IO uint32_t APB1ENR;
672 __IO uint32_t APB2ENR;
673 uint32_t RESERVED3[2];
674 __IO uint32_t AHB1LPENR;
675 __IO uint32_t AHB2LPENR;
676 __IO uint32_t AHB3LPENR;
677 uint32_t RESERVED4;
678 __IO uint32_t APB1LPENR;
679 __IO uint32_t APB2LPENR;
680 uint32_t RESERVED5[2];
681 __IO uint32_t BDCR;
682 __IO uint32_t CSR;
683 uint32_t RESERVED6[2];
684 __IO uint32_t SSCGR;
685 __IO uint32_t PLLI2SCFGR;
686 __IO uint32_t PLLSAICFGR;
687 __IO uint32_t DCKCFGR1;
688 __IO uint32_t DCKCFGR2;
690} RCC_TypeDef;
691
696typedef struct
697{
698 __IO uint32_t TR;
699 __IO uint32_t DR;
700 __IO uint32_t CR;
701 __IO uint32_t ISR;
702 __IO uint32_t PRER;
703 __IO uint32_t WUTR;
704 uint32_t reserved;
705 __IO uint32_t ALRMAR;
706 __IO uint32_t ALRMBR;
707 __IO uint32_t WPR;
708 __IO uint32_t SSR;
709 __IO uint32_t SHIFTR;
710 __IO uint32_t TSTR;
711 __IO uint32_t TSDR;
712 __IO uint32_t TSSSR;
713 __IO uint32_t CALR;
714 __IO uint32_t TAMPCR;
715 __IO uint32_t ALRMASSR;
716 __IO uint32_t ALRMBSSR;
717 __IO uint32_t OR;
718 __IO uint32_t BKP0R;
719 __IO uint32_t BKP1R;
720 __IO uint32_t BKP2R;
721 __IO uint32_t BKP3R;
722 __IO uint32_t BKP4R;
723 __IO uint32_t BKP5R;
724 __IO uint32_t BKP6R;
725 __IO uint32_t BKP7R;
726 __IO uint32_t BKP8R;
727 __IO uint32_t BKP9R;
728 __IO uint32_t BKP10R;
729 __IO uint32_t BKP11R;
730 __IO uint32_t BKP12R;
731 __IO uint32_t BKP13R;
732 __IO uint32_t BKP14R;
733 __IO uint32_t BKP15R;
734 __IO uint32_t BKP16R;
735 __IO uint32_t BKP17R;
736 __IO uint32_t BKP18R;
737 __IO uint32_t BKP19R;
738 __IO uint32_t BKP20R;
739 __IO uint32_t BKP21R;
740 __IO uint32_t BKP22R;
741 __IO uint32_t BKP23R;
742 __IO uint32_t BKP24R;
743 __IO uint32_t BKP25R;
744 __IO uint32_t BKP26R;
745 __IO uint32_t BKP27R;
746 __IO uint32_t BKP28R;
747 __IO uint32_t BKP29R;
748 __IO uint32_t BKP30R;
749 __IO uint32_t BKP31R;
750} RTC_TypeDef;
751
752
757typedef struct
758{
759 __IO uint32_t GCR;
760} SAI_TypeDef;
761
762typedef struct
763{
764 __IO uint32_t CR1;
765 __IO uint32_t CR2;
766 __IO uint32_t FRCR;
767 __IO uint32_t SLOTR;
768 __IO uint32_t IMR;
769 __IO uint32_t SR;
770 __IO uint32_t CLRFR;
771 __IO uint32_t DR;
772} SAI_Block_TypeDef;
773
778typedef struct
779{
780 __IO uint32_t CR;
781 __IO uint32_t IMR;
782 __IO uint32_t SR;
783 __IO uint32_t IFCR;
784 __IO uint32_t DR;
785 __IO uint32_t CSR;
786 __IO uint32_t DIR;
787} SPDIFRX_TypeDef;
788
793typedef struct
794{
795 __IO uint32_t POWER;
796 __IO uint32_t CLKCR;
797 __IO uint32_t ARG;
798 __IO uint32_t CMD;
799 __I uint32_t RESPCMD;
800 __I uint32_t RESP1;
801 __I uint32_t RESP2;
802 __I uint32_t RESP3;
803 __I uint32_t RESP4;
804 __IO uint32_t DTIMER;
805 __IO uint32_t DLEN;
806 __IO uint32_t DCTRL;
807 __I uint32_t DCOUNT;
808 __I uint32_t STA;
809 __IO uint32_t ICR;
810 __IO uint32_t MASK;
811 uint32_t RESERVED0[2];
812 __I uint32_t FIFOCNT;
813 uint32_t RESERVED1[13];
814 __IO uint32_t FIFO;
815} SDMMC_TypeDef;
816
821typedef struct
822{
823 __IO uint32_t CR1;
824 __IO uint32_t CR2;
825 __IO uint32_t SR;
826 __IO uint32_t DR;
827 __IO uint32_t CRCPR;
828 __IO uint32_t RXCRCR;
829 __IO uint32_t TXCRCR;
830 __IO uint32_t I2SCFGR;
831 __IO uint32_t I2SPR;
832} SPI_TypeDef;
833
838typedef struct
839{
840 __IO uint32_t CR;
841 __IO uint32_t DCR;
842 __IO uint32_t SR;
843 __IO uint32_t FCR;
844 __IO uint32_t DLR;
845 __IO uint32_t CCR;
846 __IO uint32_t AR;
847 __IO uint32_t ABR;
848 __IO uint32_t DR;
849 __IO uint32_t PSMKR;
850 __IO uint32_t PSMAR;
851 __IO uint32_t PIR;
852 __IO uint32_t LPTR;
853} QUADSPI_TypeDef;
854
859typedef struct
860{
861 __IO uint32_t CR1;
862 __IO uint32_t CR2;
863 __IO uint32_t SMCR;
864 __IO uint32_t DIER;
865 __IO uint32_t SR;
866 __IO uint32_t EGR;
867 __IO uint32_t CCMR1;
868 __IO uint32_t CCMR2;
869 __IO uint32_t CCER;
870 __IO uint32_t CNT;
871 __IO uint32_t PSC;
872 __IO uint32_t ARR;
873 __IO uint32_t RCR;
874 __IO uint32_t CCR1;
875 __IO uint32_t CCR2;
876 __IO uint32_t CCR3;
877 __IO uint32_t CCR4;
878 __IO uint32_t BDTR;
879 __IO uint32_t DCR;
880 __IO uint32_t DMAR;
881 __IO uint32_t OR;
882 __IO uint32_t CCMR3;
883 __IO uint32_t CCR5;
884 __IO uint32_t CCR6;
886} TIM_TypeDef;
887
891typedef struct
892{
893 __IO uint32_t ISR;
894 __IO uint32_t ICR;
895 __IO uint32_t IER;
896 __IO uint32_t CFGR;
897 __IO uint32_t CR;
898 __IO uint32_t CMP;
899 __IO uint32_t ARR;
900 __IO uint32_t CNT;
901} LPTIM_TypeDef;
902
903
908typedef struct
909{
910 __IO uint32_t CR1;
911 __IO uint32_t CR2;
912 __IO uint32_t CR3;
913 __IO uint32_t BRR;
914 __IO uint32_t GTPR;
915 __IO uint32_t RTOR;
916 __IO uint32_t RQR;
917 __IO uint32_t ISR;
918 __IO uint32_t ICR;
919 __IO uint32_t RDR;
920 __IO uint32_t TDR;
921} USART_TypeDef;
922
923
928typedef struct
929{
930 __IO uint32_t CR;
931 __IO uint32_t CFR;
932 __IO uint32_t SR;
933} WWDG_TypeDef;
934
935
940typedef struct
941{
942 __IO uint32_t CR;
943 __IO uint32_t SR;
944 __IO uint32_t DR;
945} RNG_TypeDef;
946
954typedef struct
955{
956 __IO uint32_t GOTGCTL;
957 __IO uint32_t GOTGINT;
958 __IO uint32_t GAHBCFG;
959 __IO uint32_t GUSBCFG;
960 __IO uint32_t GRSTCTL;
961 __IO uint32_t GINTSTS;
962 __IO uint32_t GINTMSK;
963 __IO uint32_t GRXSTSR;
964 __IO uint32_t GRXSTSP;
965 __IO uint32_t GRXFSIZ;
966 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
967 __IO uint32_t HNPTXSTS;
968 uint32_t Reserved30[2];
969 __IO uint32_t GCCFG;
970 __IO uint32_t CID;
971 uint32_t Reserved5[3];
972 __IO uint32_t GHWCFG3;
973 uint32_t Reserved6;
974 __IO uint32_t GLPMCFG;
975 uint32_t Reserved7;
976 __IO uint32_t GDFIFOCFG;
977 uint32_t Reserved43[40];
978 __IO uint32_t HPTXFSIZ;
979 __IO uint32_t DIEPTXF[0x0F];
980} USB_OTG_GlobalTypeDef;
981
982
986typedef struct
987{
988 __IO uint32_t DCFG;
989 __IO uint32_t DCTL;
990 __IO uint32_t DSTS;
991 uint32_t Reserved0C;
992 __IO uint32_t DIEPMSK;
993 __IO uint32_t DOEPMSK;
994 __IO uint32_t DAINT;
995 __IO uint32_t DAINTMSK;
996 uint32_t Reserved20;
997 uint32_t Reserved9;
998 __IO uint32_t DVBUSDIS;
999 __IO uint32_t DVBUSPULSE;
1000 __IO uint32_t DTHRCTL;
1001 __IO uint32_t DIEPEMPMSK;
1002 __IO uint32_t DEACHINT;
1003 __IO uint32_t DEACHMSK;
1004 uint32_t Reserved40;
1005 __IO uint32_t DINEP1MSK;
1006 uint32_t Reserved44[15];
1007 __IO uint32_t DOUTEP1MSK;
1008} USB_OTG_DeviceTypeDef;
1009
1010
1014typedef struct
1015{
1016 __IO uint32_t DIEPCTL;
1017 uint32_t Reserved04;
1018 __IO uint32_t DIEPINT;
1019 uint32_t Reserved0C;
1020 __IO uint32_t DIEPTSIZ;
1021 __IO uint32_t DIEPDMA;
1022 __IO uint32_t DTXFSTS;
1023 uint32_t Reserved18;
1024} USB_OTG_INEndpointTypeDef;
1025
1026
1030typedef struct
1031{
1032 __IO uint32_t DOEPCTL;
1033 uint32_t Reserved04;
1034 __IO uint32_t DOEPINT;
1035 uint32_t Reserved0C;
1036 __IO uint32_t DOEPTSIZ;
1037 __IO uint32_t DOEPDMA;
1038 uint32_t Reserved18[2];
1039} USB_OTG_OUTEndpointTypeDef;
1040
1041
1045typedef struct
1046{
1047 __IO uint32_t HCFG;
1048 __IO uint32_t HFIR;
1049 __IO uint32_t HFNUM;
1050 uint32_t Reserved40C;
1051 __IO uint32_t HPTXSTS;
1052 __IO uint32_t HAINT;
1053 __IO uint32_t HAINTMSK;
1054} USB_OTG_HostTypeDef;
1055
1059typedef struct
1060{
1061 __IO uint32_t HCCHAR;
1062 __IO uint32_t HCSPLT;
1063 __IO uint32_t HCINT;
1064 __IO uint32_t HCINTMSK;
1065 __IO uint32_t HCTSIZ;
1066 __IO uint32_t HCDMA;
1067 uint32_t Reserved[2];
1068} USB_OTG_HostChannelTypeDef;
1079#define RAMITCM_BASE 0x00000000UL
1080#define FLASHITCM_BASE 0x00200000UL
1081#define FLASHAXI_BASE 0x08000000UL
1082#define RAMDTCM_BASE 0x20000000UL
1083#define PERIPH_BASE 0x40000000UL
1084#define BKPSRAM_BASE 0x40024000UL
1085#define QSPI_BASE 0x90000000UL
1086#define FMC_R_BASE 0xA0000000UL
1087#define QSPI_R_BASE 0xA0001000UL
1088#define SRAM1_BASE 0x20010000UL
1089#define SRAM2_BASE 0x2004C000UL
1090#define FLASH_END 0x080FFFFFUL
1091#define FLASH_OTP_BASE 0x1FF0F000UL
1092#define FLASH_OTP_END 0x1FF0F41FUL
1094/* Legacy define */
1095#define FLASH_BASE FLASHAXI_BASE
1096
1098#define APB1PERIPH_BASE PERIPH_BASE
1099#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1100#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1101#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
1102
1104#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1105#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1106#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1107#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1108#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1109#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1110#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
1111#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
1112#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
1113#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
1114#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1115#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1116#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1117#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1118#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1119#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL)
1120#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1121#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1122#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1123#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1124#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1125#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1126#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
1127#define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL)
1128#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1129#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1130#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL)
1131#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1132#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1133#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
1134#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
1135
1137#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
1138#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
1139#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
1140#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
1141#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
1142#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
1143#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
1144#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)
1145#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)
1146#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1147#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
1148#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
1149#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
1150#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
1151#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
1152#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
1153#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
1154#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
1155#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
1156#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)
1157#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
1158#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
1159#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
1160#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
1162#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
1163#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1164#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1165#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1166#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1167#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1168#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1169#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1170#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
1171#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
1172#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
1173#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1174#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1175#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1176#define UID_BASE 0x1FF0F420UL
1177#define FLASHSIZE_BASE 0x1FF0F442UL
1178#define PACKAGE_BASE 0x1FF0F7E0UL
1179/* Legacy define */
1180#define PACKAGESIZE_BASE PACKAGE_BASE
1181
1182#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1183#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1184#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1185#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1186#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1187#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1188#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1189#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1190#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1191#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1192#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1193#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1194#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1195#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1196#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1197#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1198#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1199#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1200#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
1201#define ETH_MAC_BASE (ETH_BASE)
1202#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
1203#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
1204#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
1205#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
1207#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1208#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1210#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1211#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1212#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1213#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
1214
1215/* Debug MCU registers base address */
1216#define DBGMCU_BASE 0xE0042000UL
1217
1219#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1220#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1221
1222#define USB_OTG_GLOBAL_BASE 0x0000UL
1223#define USB_OTG_DEVICE_BASE 0x0800UL
1224#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL
1225#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL
1226#define USB_OTG_EP_REG_SIZE 0x0020UL
1227#define USB_OTG_HOST_BASE 0x0400UL
1228#define USB_OTG_HOST_PORT_BASE 0x0440UL
1229#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL
1230#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL
1231#define USB_OTG_PCGCCTL_BASE 0x0E00UL
1232#define USB_OTG_FIFO_BASE 0x1000UL
1233#define USB_OTG_FIFO_SIZE 0x1000UL
1234
1242#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1243#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1244#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1245#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1246#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1247#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1248#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1249#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1250#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1251#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1252#define RTC ((RTC_TypeDef *) RTC_BASE)
1253#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1254#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1255#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1256#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1257#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1258#define USART2 ((USART_TypeDef *) USART2_BASE)
1259#define USART3 ((USART_TypeDef *) USART3_BASE)
1260#define UART4 ((USART_TypeDef *) UART4_BASE)
1261#define UART5 ((USART_TypeDef *) UART5_BASE)
1262#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1263#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1264#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1265#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1266#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1267#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1268#define CEC ((CEC_TypeDef *) CEC_BASE)
1269#define PWR ((PWR_TypeDef *) PWR_BASE)
1270#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1271#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1272#define UART7 ((USART_TypeDef *) UART7_BASE)
1273#define UART8 ((USART_TypeDef *) UART8_BASE)
1274#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1275#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1276#define USART1 ((USART_TypeDef *) USART1_BASE)
1277#define USART6 ((USART_TypeDef *) USART6_BASE)
1278#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1279#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1280#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1281#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1282#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
1283#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1284#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1285#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1286#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1287#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1288#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1289#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1290#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1291#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1292#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1293#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1294#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1295#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1296#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1297#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1298#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1299#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1300#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1301#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1302#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1303#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1304#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1305#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1306#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1307#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1308#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1309#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1310#define CRC ((CRC_TypeDef *) CRC_BASE)
1311#define RCC ((RCC_TypeDef *) RCC_BASE)
1312#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1313#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1314#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1315#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1316#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1317#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1318#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1319#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1320#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1321#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1322#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1323#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1324#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1325#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1326#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1327#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1328#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1329#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1330#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1331#define ETH ((ETH_TypeDef *) ETH_BASE)
1332#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1333#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1334#define RNG ((RNG_TypeDef *) RNG_BASE)
1335#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1336#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1337#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1338#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1339#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1340#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1341#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1342#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1343
1355#define LSI_STARTUP_TIME 40U
1365/******************************************************************************/
1366/* Peripheral Registers_Bits_Definition */
1367/******************************************************************************/
1368
1369/******************************************************************************/
1370/* */
1371/* Analog to Digital Converter */
1372/* */
1373/******************************************************************************/
1374#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A))
1375#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF0F44C))
1376#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF0F44E))
1378/******************** Bit definition for ADC_SR register ********************/
1379#define ADC_SR_AWD_Pos (0U)
1380#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1381#define ADC_SR_AWD ADC_SR_AWD_Msk
1382#define ADC_SR_EOC_Pos (1U)
1383#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1384#define ADC_SR_EOC ADC_SR_EOC_Msk
1385#define ADC_SR_JEOC_Pos (2U)
1386#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1387#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1388#define ADC_SR_JSTRT_Pos (3U)
1389#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1390#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1391#define ADC_SR_STRT_Pos (4U)
1392#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1393#define ADC_SR_STRT ADC_SR_STRT_Msk
1394#define ADC_SR_OVR_Pos (5U)
1395#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1396#define ADC_SR_OVR ADC_SR_OVR_Msk
1398/******************* Bit definition for ADC_CR1 register ********************/
1399#define ADC_CR1_AWDCH_Pos (0U)
1400#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1401#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1402#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1403#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1404#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1405#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1406#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1407#define ADC_CR1_EOCIE_Pos (5U)
1408#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1409#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1410#define ADC_CR1_AWDIE_Pos (6U)
1411#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1412#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1413#define ADC_CR1_JEOCIE_Pos (7U)
1414#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1415#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1416#define ADC_CR1_SCAN_Pos (8U)
1417#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1418#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1419#define ADC_CR1_AWDSGL_Pos (9U)
1420#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1421#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1422#define ADC_CR1_JAUTO_Pos (10U)
1423#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1424#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1425#define ADC_CR1_DISCEN_Pos (11U)
1426#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1427#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1428#define ADC_CR1_JDISCEN_Pos (12U)
1429#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1430#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1431#define ADC_CR1_DISCNUM_Pos (13U)
1432#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1433#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1434#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1435#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1436#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1437#define ADC_CR1_JAWDEN_Pos (22U)
1438#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1439#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1440#define ADC_CR1_AWDEN_Pos (23U)
1441#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1442#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1443#define ADC_CR1_RES_Pos (24U)
1444#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1445#define ADC_CR1_RES ADC_CR1_RES_Msk
1446#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1447#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1448#define ADC_CR1_OVRIE_Pos (26U)
1449#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1450#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1452/******************* Bit definition for ADC_CR2 register ********************/
1453#define ADC_CR2_ADON_Pos (0U)
1454#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1455#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1456#define ADC_CR2_CONT_Pos (1U)
1457#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1458#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1459#define ADC_CR2_DMA_Pos (8U)
1460#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1461#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1462#define ADC_CR2_DDS_Pos (9U)
1463#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1464#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1465#define ADC_CR2_EOCS_Pos (10U)
1466#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1467#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1468#define ADC_CR2_ALIGN_Pos (11U)
1469#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1470#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1471#define ADC_CR2_JEXTSEL_Pos (16U)
1472#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1473#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1474#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1475#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1476#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1477#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1478#define ADC_CR2_JEXTEN_Pos (20U)
1479#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1480#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1481#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1482#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1483#define ADC_CR2_JSWSTART_Pos (22U)
1484#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1485#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1486#define ADC_CR2_EXTSEL_Pos (24U)
1487#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1488#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1489#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1490#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1491#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1492#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1493#define ADC_CR2_EXTEN_Pos (28U)
1494#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1495#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1496#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1497#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1498#define ADC_CR2_SWSTART_Pos (30U)
1499#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1500#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1502/****************** Bit definition for ADC_SMPR1 register *******************/
1503#define ADC_SMPR1_SMP10_Pos (0U)
1504#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1505#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1506#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1507#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1508#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1509#define ADC_SMPR1_SMP11_Pos (3U)
1510#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1511#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1512#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1513#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1514#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1515#define ADC_SMPR1_SMP12_Pos (6U)
1516#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1517#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1518#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1519#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1520#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1521#define ADC_SMPR1_SMP13_Pos (9U)
1522#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1523#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1524#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1525#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1526#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1527#define ADC_SMPR1_SMP14_Pos (12U)
1528#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1529#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1530#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1531#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1532#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1533#define ADC_SMPR1_SMP15_Pos (15U)
1534#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1535#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1536#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1537#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1538#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1539#define ADC_SMPR1_SMP16_Pos (18U)
1540#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1541#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1542#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1543#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1544#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1545#define ADC_SMPR1_SMP17_Pos (21U)
1546#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1547#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1548#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1549#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1550#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1551#define ADC_SMPR1_SMP18_Pos (24U)
1552#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1553#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1554#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1555#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1556#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1558/****************** Bit definition for ADC_SMPR2 register *******************/
1559#define ADC_SMPR2_SMP0_Pos (0U)
1560#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1561#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1562#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1563#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1564#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1565#define ADC_SMPR2_SMP1_Pos (3U)
1566#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1567#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1568#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1569#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1570#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1571#define ADC_SMPR2_SMP2_Pos (6U)
1572#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1573#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1574#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1575#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1576#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1577#define ADC_SMPR2_SMP3_Pos (9U)
1578#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1579#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1580#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1581#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1582#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1583#define ADC_SMPR2_SMP4_Pos (12U)
1584#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1585#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1586#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1587#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1588#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1589#define ADC_SMPR2_SMP5_Pos (15U)
1590#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1591#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1592#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1593#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1594#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1595#define ADC_SMPR2_SMP6_Pos (18U)
1596#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1597#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1598#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1599#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1600#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1601#define ADC_SMPR2_SMP7_Pos (21U)
1602#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1603#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1604#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1605#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1606#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1607#define ADC_SMPR2_SMP8_Pos (24U)
1608#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1609#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1610#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1611#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1612#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1613#define ADC_SMPR2_SMP9_Pos (27U)
1614#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1615#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1616#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1617#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1618#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1620/****************** Bit definition for ADC_JOFR1 register *******************/
1621#define ADC_JOFR1_JOFFSET1_Pos (0U)
1622#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1623#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1625/****************** Bit definition for ADC_JOFR2 register *******************/
1626#define ADC_JOFR2_JOFFSET2_Pos (0U)
1627#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1628#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1630/****************** Bit definition for ADC_JOFR3 register *******************/
1631#define ADC_JOFR3_JOFFSET3_Pos (0U)
1632#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1633#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1635/****************** Bit definition for ADC_JOFR4 register *******************/
1636#define ADC_JOFR4_JOFFSET4_Pos (0U)
1637#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1638#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1640/******************* Bit definition for ADC_HTR register ********************/
1641#define ADC_HTR_HT_Pos (0U)
1642#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1643#define ADC_HTR_HT ADC_HTR_HT_Msk
1645/******************* Bit definition for ADC_LTR register ********************/
1646#define ADC_LTR_LT_Pos (0U)
1647#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1648#define ADC_LTR_LT ADC_LTR_LT_Msk
1650/******************* Bit definition for ADC_SQR1 register *******************/
1651#define ADC_SQR1_SQ13_Pos (0U)
1652#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1653#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1654#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1655#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1656#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1657#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1658#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1659#define ADC_SQR1_SQ14_Pos (5U)
1660#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1661#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1662#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1663#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1664#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1665#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1666#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1667#define ADC_SQR1_SQ15_Pos (10U)
1668#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1669#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1670#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1671#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1672#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1673#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1674#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1675#define ADC_SQR1_SQ16_Pos (15U)
1676#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1677#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1678#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1679#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1680#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1681#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1682#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1683#define ADC_SQR1_L_Pos (20U)
1684#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1685#define ADC_SQR1_L ADC_SQR1_L_Msk
1686#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1687#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1688#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1689#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1691/******************* Bit definition for ADC_SQR2 register *******************/
1692#define ADC_SQR2_SQ7_Pos (0U)
1693#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1694#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1695#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1696#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1697#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1698#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1699#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1700#define ADC_SQR2_SQ8_Pos (5U)
1701#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1702#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1703#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1704#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1705#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1706#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1707#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1708#define ADC_SQR2_SQ9_Pos (10U)
1709#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1710#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1711#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1712#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1713#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1714#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1715#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1716#define ADC_SQR2_SQ10_Pos (15U)
1717#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1718#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1719#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1720#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1721#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1722#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1723#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1724#define ADC_SQR2_SQ11_Pos (20U)
1725#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1726#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1727#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1728#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1729#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1730#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1731#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1732#define ADC_SQR2_SQ12_Pos (25U)
1733#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1734#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1735#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1736#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1737#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1738#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1739#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1741/******************* Bit definition for ADC_SQR3 register *******************/
1742#define ADC_SQR3_SQ1_Pos (0U)
1743#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1744#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1745#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1746#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1747#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1748#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1749#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1750#define ADC_SQR3_SQ2_Pos (5U)
1751#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1752#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1753#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1754#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1755#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1756#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1757#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1758#define ADC_SQR3_SQ3_Pos (10U)
1759#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1760#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1761#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1762#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1763#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1764#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1765#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1766#define ADC_SQR3_SQ4_Pos (15U)
1767#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1768#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1769#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1770#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1771#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1772#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1773#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1774#define ADC_SQR3_SQ5_Pos (20U)
1775#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1776#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1777#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1778#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1779#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1780#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1781#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1782#define ADC_SQR3_SQ6_Pos (25U)
1783#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1784#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1785#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1786#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1787#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1788#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1789#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1791/******************* Bit definition for ADC_JSQR register *******************/
1792#define ADC_JSQR_JSQ1_Pos (0U)
1793#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1794#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1795#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1796#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1797#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1798#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1799#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1800#define ADC_JSQR_JSQ2_Pos (5U)
1801#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1802#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1803#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1804#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1805#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1806#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1807#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1808#define ADC_JSQR_JSQ3_Pos (10U)
1809#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1810#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1811#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1812#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1813#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1814#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1815#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1816#define ADC_JSQR_JSQ4_Pos (15U)
1817#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1818#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1819#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1820#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1821#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1822#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1823#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1824#define ADC_JSQR_JL_Pos (20U)
1825#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1826#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1827#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1828#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1830/******************* Bit definition for ADC_JDR1 register *******************/
1831#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU)
1833/******************* Bit definition for ADC_JDR2 register *******************/
1834#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU)
1836/******************* Bit definition for ADC_JDR3 register *******************/
1837#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU)
1839/******************* Bit definition for ADC_JDR4 register *******************/
1840#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU)
1842/******************** Bit definition for ADC_DR register ********************/
1843#define ADC_DR_DATA_Pos (0U)
1844#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1845#define ADC_DR_DATA ADC_DR_DATA_Msk
1846#define ADC_DR_ADC2DATA_Pos (16U)
1847#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1848#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1850/******************* Bit definition for ADC_CSR register ********************/
1851#define ADC_CSR_AWD1_Pos (0U)
1852#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1853#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1854#define ADC_CSR_EOC1_Pos (1U)
1855#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1856#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1857#define ADC_CSR_JEOC1_Pos (2U)
1858#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1859#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1860#define ADC_CSR_JSTRT1_Pos (3U)
1861#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1862#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1863#define ADC_CSR_STRT1_Pos (4U)
1864#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1865#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1866#define ADC_CSR_OVR1_Pos (5U)
1867#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1868#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1869#define ADC_CSR_AWD2_Pos (8U)
1870#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1871#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1872#define ADC_CSR_EOC2_Pos (9U)
1873#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1874#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1875#define ADC_CSR_JEOC2_Pos (10U)
1876#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1877#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
1878#define ADC_CSR_JSTRT2_Pos (11U)
1879#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
1880#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
1881#define ADC_CSR_STRT2_Pos (12U)
1882#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
1883#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
1884#define ADC_CSR_OVR2_Pos (13U)
1885#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
1886#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
1887#define ADC_CSR_AWD3_Pos (16U)
1888#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
1889#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
1890#define ADC_CSR_EOC3_Pos (17U)
1891#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
1892#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
1893#define ADC_CSR_JEOC3_Pos (18U)
1894#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
1895#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
1896#define ADC_CSR_JSTRT3_Pos (19U)
1897#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
1898#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
1899#define ADC_CSR_STRT3_Pos (20U)
1900#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
1901#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
1902#define ADC_CSR_OVR3_Pos (21U)
1903#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
1904#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
1906/* Legacy defines */
1907#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1908#define ADC_CSR_DOVR2 ADC_CSR_OVR2
1909#define ADC_CSR_DOVR3 ADC_CSR_OVR3
1910
1911
1912/******************* Bit definition for ADC_CCR register ********************/
1913#define ADC_CCR_MULTI_Pos (0U)
1914#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1915#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1916#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1917#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1918#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1919#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1920#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1921#define ADC_CCR_DELAY_Pos (8U)
1922#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1923#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1924#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1925#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1926#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1927#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1928#define ADC_CCR_DDS_Pos (13U)
1929#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1930#define ADC_CCR_DDS ADC_CCR_DDS_Msk
1931#define ADC_CCR_DMA_Pos (14U)
1932#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1933#define ADC_CCR_DMA ADC_CCR_DMA_Msk
1934#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1935#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1936#define ADC_CCR_ADCPRE_Pos (16U)
1937#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1938#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1939#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1940#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1941#define ADC_CCR_VBATE_Pos (22U)
1942#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1943#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1944#define ADC_CCR_TSVREFE_Pos (23U)
1945#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1946#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1948/******************* Bit definition for ADC_CDR register ********************/
1949#define ADC_CDR_DATA1_Pos (0U)
1950#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1951#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1952#define ADC_CDR_DATA2_Pos (16U)
1953#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1954#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1956/* Legacy defines */
1957#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1958#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1959
1960/******************************************************************************/
1961/* */
1962/* Controller Area Network */
1963/* */
1964/******************************************************************************/
1966/******************* Bit definition for CAN_MCR register ********************/
1967#define CAN_MCR_INRQ_Pos (0U)
1968#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1969#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1970#define CAN_MCR_SLEEP_Pos (1U)
1971#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1972#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1973#define CAN_MCR_TXFP_Pos (2U)
1974#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1975#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1976#define CAN_MCR_RFLM_Pos (3U)
1977#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1978#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1979#define CAN_MCR_NART_Pos (4U)
1980#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1981#define CAN_MCR_NART CAN_MCR_NART_Msk
1982#define CAN_MCR_AWUM_Pos (5U)
1983#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1984#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1985#define CAN_MCR_ABOM_Pos (6U)
1986#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1987#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1988#define CAN_MCR_TTCM_Pos (7U)
1989#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1990#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1991#define CAN_MCR_RESET_Pos (15U)
1992#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1993#define CAN_MCR_RESET CAN_MCR_RESET_Msk
1995/******************* Bit definition for CAN_MSR register ********************/
1996#define CAN_MSR_INAK_Pos (0U)
1997#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1998#define CAN_MSR_INAK CAN_MSR_INAK_Msk
1999#define CAN_MSR_SLAK_Pos (1U)
2000#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
2001#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
2002#define CAN_MSR_ERRI_Pos (2U)
2003#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
2004#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
2005#define CAN_MSR_WKUI_Pos (3U)
2006#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
2007#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
2008#define CAN_MSR_SLAKI_Pos (4U)
2009#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
2010#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
2011#define CAN_MSR_TXM_Pos (8U)
2012#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
2013#define CAN_MSR_TXM CAN_MSR_TXM_Msk
2014#define CAN_MSR_RXM_Pos (9U)
2015#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
2016#define CAN_MSR_RXM CAN_MSR_RXM_Msk
2017#define CAN_MSR_SAMP_Pos (10U)
2018#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
2019#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
2020#define CAN_MSR_RX_Pos (11U)
2021#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
2022#define CAN_MSR_RX CAN_MSR_RX_Msk
2024/******************* Bit definition for CAN_TSR register ********************/
2025#define CAN_TSR_RQCP0_Pos (0U)
2026#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
2027#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
2028#define CAN_TSR_TXOK0_Pos (1U)
2029#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
2030#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
2031#define CAN_TSR_ALST0_Pos (2U)
2032#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
2033#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
2034#define CAN_TSR_TERR0_Pos (3U)
2035#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
2036#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
2037#define CAN_TSR_ABRQ0_Pos (7U)
2038#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
2039#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
2040#define CAN_TSR_RQCP1_Pos (8U)
2041#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2042#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2043#define CAN_TSR_TXOK1_Pos (9U)
2044#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2045#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2046#define CAN_TSR_ALST1_Pos (10U)
2047#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2048#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2049#define CAN_TSR_TERR1_Pos (11U)
2050#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2051#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2052#define CAN_TSR_ABRQ1_Pos (15U)
2053#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2054#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2055#define CAN_TSR_RQCP2_Pos (16U)
2056#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2057#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2058#define CAN_TSR_TXOK2_Pos (17U)
2059#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2060#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2061#define CAN_TSR_ALST2_Pos (18U)
2062#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2063#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2064#define CAN_TSR_TERR2_Pos (19U)
2065#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2066#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2067#define CAN_TSR_ABRQ2_Pos (23U)
2068#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2069#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2070#define CAN_TSR_CODE_Pos (24U)
2071#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2072#define CAN_TSR_CODE CAN_TSR_CODE_Msk
2074#define CAN_TSR_TME_Pos (26U)
2075#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2076#define CAN_TSR_TME CAN_TSR_TME_Msk
2077#define CAN_TSR_TME0_Pos (26U)
2078#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2079#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2080#define CAN_TSR_TME1_Pos (27U)
2081#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2082#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2083#define CAN_TSR_TME2_Pos (28U)
2084#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2085#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2087#define CAN_TSR_LOW_Pos (29U)
2088#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2089#define CAN_TSR_LOW CAN_TSR_LOW_Msk
2090#define CAN_TSR_LOW0_Pos (29U)
2091#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2092#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2093#define CAN_TSR_LOW1_Pos (30U)
2094#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2095#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2096#define CAN_TSR_LOW2_Pos (31U)
2097#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2098#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2100/******************* Bit definition for CAN_RF0R register *******************/
2101#define CAN_RF0R_FMP0_Pos (0U)
2102#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2103#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2104#define CAN_RF0R_FULL0_Pos (3U)
2105#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2106#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2107#define CAN_RF0R_FOVR0_Pos (4U)
2108#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2109#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2110#define CAN_RF0R_RFOM0_Pos (5U)
2111#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2112#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2114/******************* Bit definition for CAN_RF1R register *******************/
2115#define CAN_RF1R_FMP1_Pos (0U)
2116#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2117#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2118#define CAN_RF1R_FULL1_Pos (3U)
2119#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2120#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2121#define CAN_RF1R_FOVR1_Pos (4U)
2122#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2123#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2124#define CAN_RF1R_RFOM1_Pos (5U)
2125#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2126#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2128/******************** Bit definition for CAN_IER register *******************/
2129#define CAN_IER_TMEIE_Pos (0U)
2130#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2131#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2132#define CAN_IER_FMPIE0_Pos (1U)
2133#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2134#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2135#define CAN_IER_FFIE0_Pos (2U)
2136#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2137#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2138#define CAN_IER_FOVIE0_Pos (3U)
2139#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2140#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2141#define CAN_IER_FMPIE1_Pos (4U)
2142#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2143#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2144#define CAN_IER_FFIE1_Pos (5U)
2145#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2146#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2147#define CAN_IER_FOVIE1_Pos (6U)
2148#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2149#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2150#define CAN_IER_EWGIE_Pos (8U)
2151#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2152#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2153#define CAN_IER_EPVIE_Pos (9U)
2154#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2155#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2156#define CAN_IER_BOFIE_Pos (10U)
2157#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2158#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2159#define CAN_IER_LECIE_Pos (11U)
2160#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2161#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2162#define CAN_IER_ERRIE_Pos (15U)
2163#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2164#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2165#define CAN_IER_WKUIE_Pos (16U)
2166#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2167#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2168#define CAN_IER_SLKIE_Pos (17U)
2169#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2170#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2172/******************** Bit definition for CAN_ESR register *******************/
2173#define CAN_ESR_EWGF_Pos (0U)
2174#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2175#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2176#define CAN_ESR_EPVF_Pos (1U)
2177#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2178#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2179#define CAN_ESR_BOFF_Pos (2U)
2180#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2181#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2183#define CAN_ESR_LEC_Pos (4U)
2184#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2185#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2186#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2187#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2188#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2190#define CAN_ESR_TEC_Pos (16U)
2191#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2192#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2193#define CAN_ESR_REC_Pos (24U)
2194#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2195#define CAN_ESR_REC CAN_ESR_REC_Msk
2197/******************* Bit definition for CAN_BTR register ********************/
2198#define CAN_BTR_BRP_Pos (0U)
2199#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2200#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2201#define CAN_BTR_TS1_Pos (16U)
2202#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2203#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2204#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2205#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2206#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2207#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2208#define CAN_BTR_TS2_Pos (20U)
2209#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2210#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2211#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2212#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2213#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2214#define CAN_BTR_SJW_Pos (24U)
2215#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2216#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2217#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2218#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2219#define CAN_BTR_LBKM_Pos (30U)
2220#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2221#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2222#define CAN_BTR_SILM_Pos (31U)
2223#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2224#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2227/****************** Bit definition for CAN_TI0R register ********************/
2228#define CAN_TI0R_TXRQ_Pos (0U)
2229#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2230#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2231#define CAN_TI0R_RTR_Pos (1U)
2232#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2233#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2234#define CAN_TI0R_IDE_Pos (2U)
2235#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2236#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2237#define CAN_TI0R_EXID_Pos (3U)
2238#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2239#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2240#define CAN_TI0R_STID_Pos (21U)
2241#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2242#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2244/****************** Bit definition for CAN_TDT0R register *******************/
2245#define CAN_TDT0R_DLC_Pos (0U)
2246#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2247#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2248#define CAN_TDT0R_TGT_Pos (8U)
2249#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2250#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2251#define CAN_TDT0R_TIME_Pos (16U)
2252#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2253#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2255/****************** Bit definition for CAN_TDL0R register *******************/
2256#define CAN_TDL0R_DATA0_Pos (0U)
2257#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2258#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2259#define CAN_TDL0R_DATA1_Pos (8U)
2260#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2261#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2262#define CAN_TDL0R_DATA2_Pos (16U)
2263#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2264#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2265#define CAN_TDL0R_DATA3_Pos (24U)
2266#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2267#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2269/****************** Bit definition for CAN_TDH0R register *******************/
2270#define CAN_TDH0R_DATA4_Pos (0U)
2271#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2272#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2273#define CAN_TDH0R_DATA5_Pos (8U)
2274#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2275#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2276#define CAN_TDH0R_DATA6_Pos (16U)
2277#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2278#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2279#define CAN_TDH0R_DATA7_Pos (24U)
2280#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2281#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2283/******************* Bit definition for CAN_TI1R register *******************/
2284#define CAN_TI1R_TXRQ_Pos (0U)
2285#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2286#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2287#define CAN_TI1R_RTR_Pos (1U)
2288#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2289#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2290#define CAN_TI1R_IDE_Pos (2U)
2291#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2292#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2293#define CAN_TI1R_EXID_Pos (3U)
2294#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2295#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2296#define CAN_TI1R_STID_Pos (21U)
2297#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2298#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2300/******************* Bit definition for CAN_TDT1R register ******************/
2301#define CAN_TDT1R_DLC_Pos (0U)
2302#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2303#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2304#define CAN_TDT1R_TGT_Pos (8U)
2305#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2306#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2307#define CAN_TDT1R_TIME_Pos (16U)
2308#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2309#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2311/******************* Bit definition for CAN_TDL1R register ******************/
2312#define CAN_TDL1R_DATA0_Pos (0U)
2313#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2314#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2315#define CAN_TDL1R_DATA1_Pos (8U)
2316#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2317#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2318#define CAN_TDL1R_DATA2_Pos (16U)
2319#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2320#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2321#define CAN_TDL1R_DATA3_Pos (24U)
2322#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2323#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2325/******************* Bit definition for CAN_TDH1R register ******************/
2326#define CAN_TDH1R_DATA4_Pos (0U)
2327#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2328#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2329#define CAN_TDH1R_DATA5_Pos (8U)
2330#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2331#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2332#define CAN_TDH1R_DATA6_Pos (16U)
2333#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2334#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2335#define CAN_TDH1R_DATA7_Pos (24U)
2336#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2337#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2339/******************* Bit definition for CAN_TI2R register *******************/
2340#define CAN_TI2R_TXRQ_Pos (0U)
2341#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2342#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2343#define CAN_TI2R_RTR_Pos (1U)
2344#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2345#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2346#define CAN_TI2R_IDE_Pos (2U)
2347#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2348#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2349#define CAN_TI2R_EXID_Pos (3U)
2350#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2351#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2352#define CAN_TI2R_STID_Pos (21U)
2353#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2354#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2356/******************* Bit definition for CAN_TDT2R register ******************/
2357#define CAN_TDT2R_DLC_Pos (0U)
2358#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2359#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2360#define CAN_TDT2R_TGT_Pos (8U)
2361#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2362#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2363#define CAN_TDT2R_TIME_Pos (16U)
2364#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2365#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2367/******************* Bit definition for CAN_TDL2R register ******************/
2368#define CAN_TDL2R_DATA0_Pos (0U)
2369#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2370#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2371#define CAN_TDL2R_DATA1_Pos (8U)
2372#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2373#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2374#define CAN_TDL2R_DATA2_Pos (16U)
2375#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2376#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2377#define CAN_TDL2R_DATA3_Pos (24U)
2378#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2379#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2381/******************* Bit definition for CAN_TDH2R register ******************/
2382#define CAN_TDH2R_DATA4_Pos (0U)
2383#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2384#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2385#define CAN_TDH2R_DATA5_Pos (8U)
2386#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2387#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2388#define CAN_TDH2R_DATA6_Pos (16U)
2389#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2390#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2391#define CAN_TDH2R_DATA7_Pos (24U)
2392#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2393#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2395/******************* Bit definition for CAN_RI0R register *******************/
2396#define CAN_RI0R_RTR_Pos (1U)
2397#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2398#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2399#define CAN_RI0R_IDE_Pos (2U)
2400#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2401#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2402#define CAN_RI0R_EXID_Pos (3U)
2403#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2404#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2405#define CAN_RI0R_STID_Pos (21U)
2406#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2407#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2409/******************* Bit definition for CAN_RDT0R register ******************/
2410#define CAN_RDT0R_DLC_Pos (0U)
2411#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2412#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2413#define CAN_RDT0R_FMI_Pos (8U)
2414#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2415#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2416#define CAN_RDT0R_TIME_Pos (16U)
2417#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2418#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2420/******************* Bit definition for CAN_RDL0R register ******************/
2421#define CAN_RDL0R_DATA0_Pos (0U)
2422#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2423#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2424#define CAN_RDL0R_DATA1_Pos (8U)
2425#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2426#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2427#define CAN_RDL0R_DATA2_Pos (16U)
2428#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2429#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2430#define CAN_RDL0R_DATA3_Pos (24U)
2431#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2432#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2434/******************* Bit definition for CAN_RDH0R register ******************/
2435#define CAN_RDH0R_DATA4_Pos (0U)
2436#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2437#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2438#define CAN_RDH0R_DATA5_Pos (8U)
2439#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2440#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2441#define CAN_RDH0R_DATA6_Pos (16U)
2442#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2443#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2444#define CAN_RDH0R_DATA7_Pos (24U)
2445#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2446#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2448/******************* Bit definition for CAN_RI1R register *******************/
2449#define CAN_RI1R_RTR_Pos (1U)
2450#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2451#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2452#define CAN_RI1R_IDE_Pos (2U)
2453#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2454#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2455#define CAN_RI1R_EXID_Pos (3U)
2456#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2457#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2458#define CAN_RI1R_STID_Pos (21U)
2459#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2460#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2462/******************* Bit definition for CAN_RDT1R register ******************/
2463#define CAN_RDT1R_DLC_Pos (0U)
2464#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2465#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2466#define CAN_RDT1R_FMI_Pos (8U)
2467#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2468#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2469#define CAN_RDT1R_TIME_Pos (16U)
2470#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2471#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2473/******************* Bit definition for CAN_RDL1R register ******************/
2474#define CAN_RDL1R_DATA0_Pos (0U)
2475#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2476#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2477#define CAN_RDL1R_DATA1_Pos (8U)
2478#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2479#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2480#define CAN_RDL1R_DATA2_Pos (16U)
2481#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2482#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2483#define CAN_RDL1R_DATA3_Pos (24U)
2484#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2485#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2487/******************* Bit definition for CAN_RDH1R register ******************/
2488#define CAN_RDH1R_DATA4_Pos (0U)
2489#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2490#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2491#define CAN_RDH1R_DATA5_Pos (8U)
2492#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2493#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2494#define CAN_RDH1R_DATA6_Pos (16U)
2495#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2496#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2497#define CAN_RDH1R_DATA7_Pos (24U)
2498#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2499#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2502/******************* Bit definition for CAN_FMR register ********************/
2503#define CAN_FMR_FINIT ((uint8_t)0x01U)
2504#define CAN_FMR_CAN2SB_Pos (8U)
2505#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2506#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2508/******************* Bit definition for CAN_FM1R register *******************/
2509#define CAN_FM1R_FBM_Pos (0U)
2510#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
2511#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2512#define CAN_FM1R_FBM0_Pos (0U)
2513#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2514#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2515#define CAN_FM1R_FBM1_Pos (1U)
2516#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2517#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2518#define CAN_FM1R_FBM2_Pos (2U)
2519#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2520#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2521#define CAN_FM1R_FBM3_Pos (3U)
2522#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2523#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2524#define CAN_FM1R_FBM4_Pos (4U)
2525#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2526#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2527#define CAN_FM1R_FBM5_Pos (5U)
2528#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2529#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2530#define CAN_FM1R_FBM6_Pos (6U)
2531#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2532#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2533#define CAN_FM1R_FBM7_Pos (7U)
2534#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2535#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2536#define CAN_FM1R_FBM8_Pos (8U)
2537#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2538#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2539#define CAN_FM1R_FBM9_Pos (9U)
2540#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2541#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2542#define CAN_FM1R_FBM10_Pos (10U)
2543#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2544#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2545#define CAN_FM1R_FBM11_Pos (11U)
2546#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2547#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2548#define CAN_FM1R_FBM12_Pos (12U)
2549#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2550#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2551#define CAN_FM1R_FBM13_Pos (13U)
2552#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2553#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2555/******************* Bit definition for CAN_FS1R register *******************/
2556#define CAN_FS1R_FSC_Pos (0U)
2557#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
2558#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2559#define CAN_FS1R_FSC0_Pos (0U)
2560#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2561#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2562#define CAN_FS1R_FSC1_Pos (1U)
2563#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2564#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2565#define CAN_FS1R_FSC2_Pos (2U)
2566#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2567#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2568#define CAN_FS1R_FSC3_Pos (3U)
2569#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2570#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2571#define CAN_FS1R_FSC4_Pos (4U)
2572#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2573#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2574#define CAN_FS1R_FSC5_Pos (5U)
2575#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2576#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2577#define CAN_FS1R_FSC6_Pos (6U)
2578#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2579#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2580#define CAN_FS1R_FSC7_Pos (7U)
2581#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2582#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2583#define CAN_FS1R_FSC8_Pos (8U)
2584#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2585#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2586#define CAN_FS1R_FSC9_Pos (9U)
2587#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2588#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2589#define CAN_FS1R_FSC10_Pos (10U)
2590#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2591#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2592#define CAN_FS1R_FSC11_Pos (11U)
2593#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2594#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2595#define CAN_FS1R_FSC12_Pos (12U)
2596#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2597#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2598#define CAN_FS1R_FSC13_Pos (13U)
2599#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2600#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2602/****************** Bit definition for CAN_FFA1R register *******************/
2603#define CAN_FFA1R_FFA_Pos (0U)
2604#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
2605#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2606#define CAN_FFA1R_FFA0_Pos (0U)
2607#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2608#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2609#define CAN_FFA1R_FFA1_Pos (1U)
2610#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2611#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2612#define CAN_FFA1R_FFA2_Pos (2U)
2613#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2614#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2615#define CAN_FFA1R_FFA3_Pos (3U)
2616#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2617#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2618#define CAN_FFA1R_FFA4_Pos (4U)
2619#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2620#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2621#define CAN_FFA1R_FFA5_Pos (5U)
2622#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2623#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2624#define CAN_FFA1R_FFA6_Pos (6U)
2625#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2626#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2627#define CAN_FFA1R_FFA7_Pos (7U)
2628#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2629#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2630#define CAN_FFA1R_FFA8_Pos (8U)
2631#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2632#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2633#define CAN_FFA1R_FFA9_Pos (9U)
2634#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2635#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2636#define CAN_FFA1R_FFA10_Pos (10U)
2637#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2638#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2639#define CAN_FFA1R_FFA11_Pos (11U)
2640#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2641#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2642#define CAN_FFA1R_FFA12_Pos (12U)
2643#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2644#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2645#define CAN_FFA1R_FFA13_Pos (13U)
2646#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2647#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2649/******************* Bit definition for CAN_FA1R register *******************/
2650#define CAN_FA1R_FACT_Pos (0U)
2651#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
2652#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2653#define CAN_FA1R_FACT0_Pos (0U)
2654#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2655#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2656#define CAN_FA1R_FACT1_Pos (1U)
2657#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2658#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2659#define CAN_FA1R_FACT2_Pos (2U)
2660#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2661#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2662#define CAN_FA1R_FACT3_Pos (3U)
2663#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2664#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2665#define CAN_FA1R_FACT4_Pos (4U)
2666#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2667#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2668#define CAN_FA1R_FACT5_Pos (5U)
2669#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2670#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2671#define CAN_FA1R_FACT6_Pos (6U)
2672#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2673#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2674#define CAN_FA1R_FACT7_Pos (7U)
2675#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2676#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2677#define CAN_FA1R_FACT8_Pos (8U)
2678#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2679#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2680#define CAN_FA1R_FACT9_Pos (9U)
2681#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2682#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2683#define CAN_FA1R_FACT10_Pos (10U)
2684#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2685#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2686#define CAN_FA1R_FACT11_Pos (11U)
2687#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2688#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2689#define CAN_FA1R_FACT12_Pos (12U)
2690#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2691#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2692#define CAN_FA1R_FACT13_Pos (13U)
2693#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2694#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2696/******************* Bit definition for CAN_F0R1 register *******************/
2697#define CAN_F0R1_FB0_Pos (0U)
2698#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2699#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2700#define CAN_F0R1_FB1_Pos (1U)
2701#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2702#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2703#define CAN_F0R1_FB2_Pos (2U)
2704#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2705#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2706#define CAN_F0R1_FB3_Pos (3U)
2707#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2708#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2709#define CAN_F0R1_FB4_Pos (4U)
2710#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2711#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2712#define CAN_F0R1_FB5_Pos (5U)
2713#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2714#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2715#define CAN_F0R1_FB6_Pos (6U)
2716#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2717#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2718#define CAN_F0R1_FB7_Pos (7U)
2719#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2720#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2721#define CAN_F0R1_FB8_Pos (8U)
2722#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2723#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2724#define CAN_F0R1_FB9_Pos (9U)
2725#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2726#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2727#define CAN_F0R1_FB10_Pos (10U)
2728#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2729#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2730#define CAN_F0R1_FB11_Pos (11U)
2731#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2732#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2733#define CAN_F0R1_FB12_Pos (12U)
2734#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2735#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2736#define CAN_F0R1_FB13_Pos (13U)
2737#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2738#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2739#define CAN_F0R1_FB14_Pos (14U)
2740#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2741#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2742#define CAN_F0R1_FB15_Pos (15U)
2743#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2744#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2745#define CAN_F0R1_FB16_Pos (16U)
2746#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2747#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2748#define CAN_F0R1_FB17_Pos (17U)
2749#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2750#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2751#define CAN_F0R1_FB18_Pos (18U)
2752#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2753#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2754#define CAN_F0R1_FB19_Pos (19U)
2755#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2756#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2757#define CAN_F0R1_FB20_Pos (20U)
2758#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2759#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2760#define CAN_F0R1_FB21_Pos (21U)
2761#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2762#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2763#define CAN_F0R1_FB22_Pos (22U)
2764#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2765#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2766#define CAN_F0R1_FB23_Pos (23U)
2767#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2768#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2769#define CAN_F0R1_FB24_Pos (24U)
2770#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2771#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2772#define CAN_F0R1_FB25_Pos (25U)
2773#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2774#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2775#define CAN_F0R1_FB26_Pos (26U)
2776#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2777#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2778#define CAN_F0R1_FB27_Pos (27U)
2779#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2780#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2781#define CAN_F0R1_FB28_Pos (28U)
2782#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2783#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2784#define CAN_F0R1_FB29_Pos (29U)
2785#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2786#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2787#define CAN_F0R1_FB30_Pos (30U)
2788#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2789#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2790#define CAN_F0R1_FB31_Pos (31U)
2791#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2792#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2794/******************* Bit definition for CAN_F1R1 register *******************/
2795#define CAN_F1R1_FB0_Pos (0U)
2796#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2797#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2798#define CAN_F1R1_FB1_Pos (1U)
2799#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2800#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2801#define CAN_F1R1_FB2_Pos (2U)
2802#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2803#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2804#define CAN_F1R1_FB3_Pos (3U)
2805#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2806#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2807#define CAN_F1R1_FB4_Pos (4U)
2808#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2809#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2810#define CAN_F1R1_FB5_Pos (5U)
2811#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2812#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2813#define CAN_F1R1_FB6_Pos (6U)
2814#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2815#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2816#define CAN_F1R1_FB7_Pos (7U)
2817#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2818#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2819#define CAN_F1R1_FB8_Pos (8U)
2820#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2821#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2822#define CAN_F1R1_FB9_Pos (9U)
2823#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2824#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2825#define CAN_F1R1_FB10_Pos (10U)
2826#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2827#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2828#define CAN_F1R1_FB11_Pos (11U)
2829#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2830#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2831#define CAN_F1R1_FB12_Pos (12U)
2832#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2833#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2834#define CAN_F1R1_FB13_Pos (13U)
2835#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2836#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2837#define CAN_F1R1_FB14_Pos (14U)
2838#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2839#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2840#define CAN_F1R1_FB15_Pos (15U)
2841#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2842#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2843#define CAN_F1R1_FB16_Pos (16U)
2844#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2845#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2846#define CAN_F1R1_FB17_Pos (17U)
2847#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2848#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2849#define CAN_F1R1_FB18_Pos (18U)
2850#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2851#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2852#define CAN_F1R1_FB19_Pos (19U)
2853#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2854#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2855#define CAN_F1R1_FB20_Pos (20U)
2856#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2857#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2858#define CAN_F1R1_FB21_Pos (21U)
2859#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2860#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2861#define CAN_F1R1_FB22_Pos (22U)
2862#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2863#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2864#define CAN_F1R1_FB23_Pos (23U)
2865#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2866#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2867#define CAN_F1R1_FB24_Pos (24U)
2868#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2869#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2870#define CAN_F1R1_FB25_Pos (25U)
2871#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2872#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2873#define CAN_F1R1_FB26_Pos (26U)
2874#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2875#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2876#define CAN_F1R1_FB27_Pos (27U)
2877#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
2878#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
2879#define CAN_F1R1_FB28_Pos (28U)
2880#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
2881#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
2882#define CAN_F1R1_FB29_Pos (29U)
2883#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
2884#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
2885#define CAN_F1R1_FB30_Pos (30U)
2886#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
2887#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
2888#define CAN_F1R1_FB31_Pos (31U)
2889#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
2890#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
2892/******************* Bit definition for CAN_F2R1 register *******************/
2893#define CAN_F2R1_FB0_Pos (0U)
2894#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
2895#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
2896#define CAN_F2R1_FB1_Pos (1U)
2897#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
2898#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
2899#define CAN_F2R1_FB2_Pos (2U)
2900#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
2901#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
2902#define CAN_F2R1_FB3_Pos (3U)
2903#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
2904#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
2905#define CAN_F2R1_FB4_Pos (4U)
2906#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
2907#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
2908#define CAN_F2R1_FB5_Pos (5U)
2909#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
2910#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
2911#define CAN_F2R1_FB6_Pos (6U)
2912#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
2913#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
2914#define CAN_F2R1_FB7_Pos (7U)
2915#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
2916#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
2917#define CAN_F2R1_FB8_Pos (8U)
2918#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
2919#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
2920#define CAN_F2R1_FB9_Pos (9U)
2921#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
2922#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
2923#define CAN_F2R1_FB10_Pos (10U)
2924#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
2925#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
2926#define CAN_F2R1_FB11_Pos (11U)
2927#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
2928#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
2929#define CAN_F2R1_FB12_Pos (12U)
2930#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
2931#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
2932#define CAN_F2R1_FB13_Pos (13U)
2933#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
2934#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
2935#define CAN_F2R1_FB14_Pos (14U)
2936#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
2937#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
2938#define CAN_F2R1_FB15_Pos (15U)
2939#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
2940#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
2941#define CAN_F2R1_FB16_Pos (16U)
2942#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
2943#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
2944#define CAN_F2R1_FB17_Pos (17U)
2945#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
2946#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
2947#define CAN_F2R1_FB18_Pos (18U)
2948#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
2949#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
2950#define CAN_F2R1_FB19_Pos (19U)
2951#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
2952#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
2953#define CAN_F2R1_FB20_Pos (20U)
2954#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
2955#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
2956#define CAN_F2R1_FB21_Pos (21U)
2957#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
2958#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
2959#define CAN_F2R1_FB22_Pos (22U)
2960#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
2961#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
2962#define CAN_F2R1_FB23_Pos (23U)
2963#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
2964#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
2965#define CAN_F2R1_FB24_Pos (24U)
2966#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
2967#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
2968#define CAN_F2R1_FB25_Pos (25U)
2969#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
2970#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
2971#define CAN_F2R1_FB26_Pos (26U)
2972#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
2973#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
2974#define CAN_F2R1_FB27_Pos (27U)
2975#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
2976#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
2977#define CAN_F2R1_FB28_Pos (28U)
2978#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
2979#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
2980#define CAN_F2R1_FB29_Pos (29U)
2981#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
2982#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
2983#define CAN_F2R1_FB30_Pos (30U)
2984#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
2985#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
2986#define CAN_F2R1_FB31_Pos (31U)
2987#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
2988#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
2990/******************* Bit definition for CAN_F3R1 register *******************/
2991#define CAN_F3R1_FB0_Pos (0U)
2992#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
2993#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
2994#define CAN_F3R1_FB1_Pos (1U)
2995#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
2996#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
2997#define CAN_F3R1_FB2_Pos (2U)
2998#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
2999#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3000#define CAN_F3R1_FB3_Pos (3U)
3001#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3002#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3003#define CAN_F3R1_FB4_Pos (4U)
3004#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3005#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3006#define CAN_F3R1_FB5_Pos (5U)
3007#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3008#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3009#define CAN_F3R1_FB6_Pos (6U)
3010#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3011#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3012#define CAN_F3R1_FB7_Pos (7U)
3013#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3014#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3015#define CAN_F3R1_FB8_Pos (8U)
3016#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3017#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3018#define CAN_F3R1_FB9_Pos (9U)
3019#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3020#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3021#define CAN_F3R1_FB10_Pos (10U)
3022#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3023#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3024#define CAN_F3R1_FB11_Pos (11U)
3025#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3026#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3027#define CAN_F3R1_FB12_Pos (12U)
3028#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3029#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3030#define CAN_F3R1_FB13_Pos (13U)
3031#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3032#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3033#define CAN_F3R1_FB14_Pos (14U)
3034#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3035#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3036#define CAN_F3R1_FB15_Pos (15U)
3037#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3038#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3039#define CAN_F3R1_FB16_Pos (16U)
3040#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3041#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3042#define CAN_F3R1_FB17_Pos (17U)
3043#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3044#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3045#define CAN_F3R1_FB18_Pos (18U)
3046#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3047#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3048#define CAN_F3R1_FB19_Pos (19U)
3049#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3050#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3051#define CAN_F3R1_FB20_Pos (20U)
3052#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3053#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3054#define CAN_F3R1_FB21_Pos (21U)
3055#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3056#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3057#define CAN_F3R1_FB22_Pos (22U)
3058#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3059#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3060#define CAN_F3R1_FB23_Pos (23U)
3061#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3062#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3063#define CAN_F3R1_FB24_Pos (24U)
3064#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3065#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3066#define CAN_F3R1_FB25_Pos (25U)
3067#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3068#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3069#define CAN_F3R1_FB26_Pos (26U)
3070#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3071#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3072#define CAN_F3R1_FB27_Pos (27U)
3073#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3074#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3075#define CAN_F3R1_FB28_Pos (28U)
3076#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3077#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3078#define CAN_F3R1_FB29_Pos (29U)
3079#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3080#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3081#define CAN_F3R1_FB30_Pos (30U)
3082#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3083#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3084#define CAN_F3R1_FB31_Pos (31U)
3085#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3086#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3088/******************* Bit definition for CAN_F4R1 register *******************/
3089#define CAN_F4R1_FB0_Pos (0U)
3090#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3091#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3092#define CAN_F4R1_FB1_Pos (1U)
3093#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3094#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3095#define CAN_F4R1_FB2_Pos (2U)
3096#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3097#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3098#define CAN_F4R1_FB3_Pos (3U)
3099#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3100#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3101#define CAN_F4R1_FB4_Pos (4U)
3102#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3103#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3104#define CAN_F4R1_FB5_Pos (5U)
3105#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3106#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3107#define CAN_F4R1_FB6_Pos (6U)
3108#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3109#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3110#define CAN_F4R1_FB7_Pos (7U)
3111#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3112#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3113#define CAN_F4R1_FB8_Pos (8U)
3114#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3115#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3116#define CAN_F4R1_FB9_Pos (9U)
3117#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3118#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3119#define CAN_F4R1_FB10_Pos (10U)
3120#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3121#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3122#define CAN_F4R1_FB11_Pos (11U)
3123#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3124#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3125#define CAN_F4R1_FB12_Pos (12U)
3126#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3127#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3128#define CAN_F4R1_FB13_Pos (13U)
3129#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3130#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3131#define CAN_F4R1_FB14_Pos (14U)
3132#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3133#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3134#define CAN_F4R1_FB15_Pos (15U)
3135#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3136#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3137#define CAN_F4R1_FB16_Pos (16U)
3138#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3139#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3140#define CAN_F4R1_FB17_Pos (17U)
3141#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3142#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3143#define CAN_F4R1_FB18_Pos (18U)
3144#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3145#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3146#define CAN_F4R1_FB19_Pos (19U)
3147#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3148#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3149#define CAN_F4R1_FB20_Pos (20U)
3150#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3151#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3152#define CAN_F4R1_FB21_Pos (21U)
3153#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3154#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3155#define CAN_F4R1_FB22_Pos (22U)
3156#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3157#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3158#define CAN_F4R1_FB23_Pos (23U)
3159#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3160#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3161#define CAN_F4R1_FB24_Pos (24U)
3162#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3163#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3164#define CAN_F4R1_FB25_Pos (25U)
3165#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3166#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3167#define CAN_F4R1_FB26_Pos (26U)
3168#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3169#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3170#define CAN_F4R1_FB27_Pos (27U)
3171#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3172#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3173#define CAN_F4R1_FB28_Pos (28U)
3174#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3175#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3176#define CAN_F4R1_FB29_Pos (29U)
3177#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3178#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3179#define CAN_F4R1_FB30_Pos (30U)
3180#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3181#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3182#define CAN_F4R1_FB31_Pos (31U)
3183#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3184#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3186/******************* Bit definition for CAN_F5R1 register *******************/
3187#define CAN_F5R1_FB0_Pos (0U)
3188#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3189#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3190#define CAN_F5R1_FB1_Pos (1U)
3191#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3192#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3193#define CAN_F5R1_FB2_Pos (2U)
3194#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3195#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3196#define CAN_F5R1_FB3_Pos (3U)
3197#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3198#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3199#define CAN_F5R1_FB4_Pos (4U)
3200#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3201#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3202#define CAN_F5R1_FB5_Pos (5U)
3203#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3204#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3205#define CAN_F5R1_FB6_Pos (6U)
3206#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3207#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3208#define CAN_F5R1_FB7_Pos (7U)
3209#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3210#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3211#define CAN_F5R1_FB8_Pos (8U)
3212#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3213#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3214#define CAN_F5R1_FB9_Pos (9U)
3215#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3216#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3217#define CAN_F5R1_FB10_Pos (10U)
3218#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3219#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3220#define CAN_F5R1_FB11_Pos (11U)
3221#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3222#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3223#define CAN_F5R1_FB12_Pos (12U)
3224#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3225#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3226#define CAN_F5R1_FB13_Pos (13U)
3227#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3228#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3229#define CAN_F5R1_FB14_Pos (14U)
3230#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3231#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3232#define CAN_F5R1_FB15_Pos (15U)
3233#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3234#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3235#define CAN_F5R1_FB16_Pos (16U)
3236#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3237#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3238#define CAN_F5R1_FB17_Pos (17U)
3239#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3240#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3241#define CAN_F5R1_FB18_Pos (18U)
3242#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3243#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3244#define CAN_F5R1_FB19_Pos (19U)
3245#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3246#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3247#define CAN_F5R1_FB20_Pos (20U)
3248#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3249#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3250#define CAN_F5R1_FB21_Pos (21U)
3251#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3252#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3253#define CAN_F5R1_FB22_Pos (22U)
3254#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3255#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3256#define CAN_F5R1_FB23_Pos (23U)
3257#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3258#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3259#define CAN_F5R1_FB24_Pos (24U)
3260#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3261#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3262#define CAN_F5R1_FB25_Pos (25U)
3263#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3264#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3265#define CAN_F5R1_FB26_Pos (26U)
3266#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3267#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3268#define CAN_F5R1_FB27_Pos (27U)
3269#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3270#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3271#define CAN_F5R1_FB28_Pos (28U)
3272#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3273#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3274#define CAN_F5R1_FB29_Pos (29U)
3275#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3276#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3277#define CAN_F5R1_FB30_Pos (30U)
3278#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3279#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3280#define CAN_F5R1_FB31_Pos (31U)
3281#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3282#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3284/******************* Bit definition for CAN_F6R1 register *******************/
3285#define CAN_F6R1_FB0_Pos (0U)
3286#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3287#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3288#define CAN_F6R1_FB1_Pos (1U)
3289#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3290#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3291#define CAN_F6R1_FB2_Pos (2U)
3292#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3293#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3294#define CAN_F6R1_FB3_Pos (3U)
3295#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3296#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3297#define CAN_F6R1_FB4_Pos (4U)
3298#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3299#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3300#define CAN_F6R1_FB5_Pos (5U)
3301#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3302#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3303#define CAN_F6R1_FB6_Pos (6U)
3304#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3305#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3306#define CAN_F6R1_FB7_Pos (7U)
3307#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3308#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3309#define CAN_F6R1_FB8_Pos (8U)
3310#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3311#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3312#define CAN_F6R1_FB9_Pos (9U)
3313#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3314#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3315#define CAN_F6R1_FB10_Pos (10U)
3316#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3317#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3318#define CAN_F6R1_FB11_Pos (11U)
3319#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3320#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3321#define CAN_F6R1_FB12_Pos (12U)
3322#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3323#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3324#define CAN_F6R1_FB13_Pos (13U)
3325#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3326#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3327#define CAN_F6R1_FB14_Pos (14U)
3328#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3329#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3330#define CAN_F6R1_FB15_Pos (15U)
3331#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3332#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3333#define CAN_F6R1_FB16_Pos (16U)
3334#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3335#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3336#define CAN_F6R1_FB17_Pos (17U)
3337#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3338#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3339#define CAN_F6R1_FB18_Pos (18U)
3340#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3341#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3342#define CAN_F6R1_FB19_Pos (19U)
3343#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3344#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3345#define CAN_F6R1_FB20_Pos (20U)
3346#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3347#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3348#define CAN_F6R1_FB21_Pos (21U)
3349#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3350#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3351#define CAN_F6R1_FB22_Pos (22U)
3352#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3353#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3354#define CAN_F6R1_FB23_Pos (23U)
3355#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3356#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3357#define CAN_F6R1_FB24_Pos (24U)
3358#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3359#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3360#define CAN_F6R1_FB25_Pos (25U)
3361#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3362#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3363#define CAN_F6R1_FB26_Pos (26U)
3364#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3365#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3366#define CAN_F6R1_FB27_Pos (27U)
3367#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3368#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3369#define CAN_F6R1_FB28_Pos (28U)
3370#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3371#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3372#define CAN_F6R1_FB29_Pos (29U)
3373#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3374#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3375#define CAN_F6R1_FB30_Pos (30U)
3376#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3377#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3378#define CAN_F6R1_FB31_Pos (31U)
3379#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3380#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3382/******************* Bit definition for CAN_F7R1 register *******************/
3383#define CAN_F7R1_FB0_Pos (0U)
3384#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3385#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3386#define CAN_F7R1_FB1_Pos (1U)
3387#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3388#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3389#define CAN_F7R1_FB2_Pos (2U)
3390#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3391#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3392#define CAN_F7R1_FB3_Pos (3U)
3393#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3394#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3395#define CAN_F7R1_FB4_Pos (4U)
3396#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3397#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3398#define CAN_F7R1_FB5_Pos (5U)
3399#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3400#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3401#define CAN_F7R1_FB6_Pos (6U)
3402#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3403#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3404#define CAN_F7R1_FB7_Pos (7U)
3405#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3406#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3407#define CAN_F7R1_FB8_Pos (8U)
3408#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3409#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3410#define CAN_F7R1_FB9_Pos (9U)
3411#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3412#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3413#define CAN_F7R1_FB10_Pos (10U)
3414#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3415#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3416#define CAN_F7R1_FB11_Pos (11U)
3417#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3418#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3419#define CAN_F7R1_FB12_Pos (12U)
3420#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3421#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3422#define CAN_F7R1_FB13_Pos (13U)
3423#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3424#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3425#define CAN_F7R1_FB14_Pos (14U)
3426#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3427#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3428#define CAN_F7R1_FB15_Pos (15U)
3429#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3430#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3431#define CAN_F7R1_FB16_Pos (16U)
3432#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3433#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3434#define CAN_F7R1_FB17_Pos (17U)
3435#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3436#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3437#define CAN_F7R1_FB18_Pos (18U)
3438#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3439#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3440#define CAN_F7R1_FB19_Pos (19U)
3441#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3442#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3443#define CAN_F7R1_FB20_Pos (20U)
3444#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3445#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3446#define CAN_F7R1_FB21_Pos (21U)
3447#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3448#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3449#define CAN_F7R1_FB22_Pos (22U)
3450#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3451#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3452#define CAN_F7R1_FB23_Pos (23U)
3453#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3454#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3455#define CAN_F7R1_FB24_Pos (24U)
3456#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3457#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3458#define CAN_F7R1_FB25_Pos (25U)
3459#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3460#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3461#define CAN_F7R1_FB26_Pos (26U)
3462#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3463#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3464#define CAN_F7R1_FB27_Pos (27U)
3465#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3466#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3467#define CAN_F7R1_FB28_Pos (28U)
3468#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3469#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3470#define CAN_F7R1_FB29_Pos (29U)
3471#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3472#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3473#define CAN_F7R1_FB30_Pos (30U)
3474#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3475#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3476#define CAN_F7R1_FB31_Pos (31U)
3477#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3478#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3480/******************* Bit definition for CAN_F8R1 register *******************/
3481#define CAN_F8R1_FB0_Pos (0U)
3482#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3483#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3484#define CAN_F8R1_FB1_Pos (1U)
3485#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3486#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3487#define CAN_F8R1_FB2_Pos (2U)
3488#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3489#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3490#define CAN_F8R1_FB3_Pos (3U)
3491#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3492#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3493#define CAN_F8R1_FB4_Pos (4U)
3494#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3495#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3496#define CAN_F8R1_FB5_Pos (5U)
3497#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3498#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3499#define CAN_F8R1_FB6_Pos (6U)
3500#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3501#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3502#define CAN_F8R1_FB7_Pos (7U)
3503#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3504#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3505#define CAN_F8R1_FB8_Pos (8U)
3506#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3507#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3508#define CAN_F8R1_FB9_Pos (9U)
3509#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3510#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3511#define CAN_F8R1_FB10_Pos (10U)
3512#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3513#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3514#define CAN_F8R1_FB11_Pos (11U)
3515#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3516#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3517#define CAN_F8R1_FB12_Pos (12U)
3518#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3519#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3520#define CAN_F8R1_FB13_Pos (13U)
3521#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3522#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3523#define CAN_F8R1_FB14_Pos (14U)
3524#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3525#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3526#define CAN_F8R1_FB15_Pos (15U)
3527#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3528#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3529#define CAN_F8R1_FB16_Pos (16U)
3530#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3531#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3532#define CAN_F8R1_FB17_Pos (17U)
3533#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3534#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3535#define CAN_F8R1_FB18_Pos (18U)
3536#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3537#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3538#define CAN_F8R1_FB19_Pos (19U)
3539#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3540#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3541#define CAN_F8R1_FB20_Pos (20U)
3542#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3543#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3544#define CAN_F8R1_FB21_Pos (21U)
3545#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3546#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3547#define CAN_F8R1_FB22_Pos (22U)
3548#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3549#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3550#define CAN_F8R1_FB23_Pos (23U)
3551#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3552#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3553#define CAN_F8R1_FB24_Pos (24U)
3554#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3555#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3556#define CAN_F8R1_FB25_Pos (25U)
3557#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3558#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3559#define CAN_F8R1_FB26_Pos (26U)
3560#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3561#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3562#define CAN_F8R1_FB27_Pos (27U)
3563#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3564#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3565#define CAN_F8R1_FB28_Pos (28U)
3566#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3567#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3568#define CAN_F8R1_FB29_Pos (29U)
3569#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3570#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3571#define CAN_F8R1_FB30_Pos (30U)
3572#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3573#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3574#define CAN_F8R1_FB31_Pos (31U)
3575#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3576#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3578/******************* Bit definition for CAN_F9R1 register *******************/
3579#define CAN_F9R1_FB0_Pos (0U)
3580#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3581#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3582#define CAN_F9R1_FB1_Pos (1U)
3583#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3584#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3585#define CAN_F9R1_FB2_Pos (2U)
3586#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3587#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3588#define CAN_F9R1_FB3_Pos (3U)
3589#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3590#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3591#define CAN_F9R1_FB4_Pos (4U)
3592#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3593#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3594#define CAN_F9R1_FB5_Pos (5U)
3595#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3596#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3597#define CAN_F9R1_FB6_Pos (6U)
3598#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3599#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3600#define CAN_F9R1_FB7_Pos (7U)
3601#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3602#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3603#define CAN_F9R1_FB8_Pos (8U)
3604#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3605#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3606#define CAN_F9R1_FB9_Pos (9U)
3607#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3608#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3609#define CAN_F9R1_FB10_Pos (10U)
3610#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3611#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3612#define CAN_F9R1_FB11_Pos (11U)
3613#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3614#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3615#define CAN_F9R1_FB12_Pos (12U)
3616#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3617#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3618#define CAN_F9R1_FB13_Pos (13U)
3619#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3620#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3621#define CAN_F9R1_FB14_Pos (14U)
3622#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3623#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3624#define CAN_F9R1_FB15_Pos (15U)
3625#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3626#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3627#define CAN_F9R1_FB16_Pos (16U)
3628#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3629#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3630#define CAN_F9R1_FB17_Pos (17U)
3631#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3632#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3633#define CAN_F9R1_FB18_Pos (18U)
3634#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3635#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3636#define CAN_F9R1_FB19_Pos (19U)
3637#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3638#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3639#define CAN_F9R1_FB20_Pos (20U)
3640#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3641#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3642#define CAN_F9R1_FB21_Pos (21U)
3643#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3644#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3645#define CAN_F9R1_FB22_Pos (22U)
3646#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3647#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3648#define CAN_F9R1_FB23_Pos (23U)
3649#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3650#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3651#define CAN_F9R1_FB24_Pos (24U)
3652#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3653#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3654#define CAN_F9R1_FB25_Pos (25U)
3655#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3656#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3657#define CAN_F9R1_FB26_Pos (26U)
3658#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3659#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3660#define CAN_F9R1_FB27_Pos (27U)
3661#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3662#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3663#define CAN_F9R1_FB28_Pos (28U)
3664#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3665#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3666#define CAN_F9R1_FB29_Pos (29U)
3667#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3668#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3669#define CAN_F9R1_FB30_Pos (30U)
3670#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3671#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3672#define CAN_F9R1_FB31_Pos (31U)
3673#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3674#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3676/******************* Bit definition for CAN_F10R1 register ******************/
3677#define CAN_F10R1_FB0_Pos (0U)
3678#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3679#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3680#define CAN_F10R1_FB1_Pos (1U)
3681#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3682#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3683#define CAN_F10R1_FB2_Pos (2U)
3684#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3685#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3686#define CAN_F10R1_FB3_Pos (3U)
3687#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3688#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3689#define CAN_F10R1_FB4_Pos (4U)
3690#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3691#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3692#define CAN_F10R1_FB5_Pos (5U)
3693#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3694#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3695#define CAN_F10R1_FB6_Pos (6U)
3696#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3697#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3698#define CAN_F10R1_FB7_Pos (7U)
3699#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3700#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3701#define CAN_F10R1_FB8_Pos (8U)
3702#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3703#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3704#define CAN_F10R1_FB9_Pos (9U)
3705#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3706#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3707#define CAN_F10R1_FB10_Pos (10U)
3708#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3709#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3710#define CAN_F10R1_FB11_Pos (11U)
3711#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3712#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3713#define CAN_F10R1_FB12_Pos (12U)
3714#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3715#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3716#define CAN_F10R1_FB13_Pos (13U)
3717#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3718#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3719#define CAN_F10R1_FB14_Pos (14U)
3720#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3721#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3722#define CAN_F10R1_FB15_Pos (15U)
3723#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3724#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3725#define CAN_F10R1_FB16_Pos (16U)
3726#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3727#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3728#define CAN_F10R1_FB17_Pos (17U)
3729#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3730#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3731#define CAN_F10R1_FB18_Pos (18U)
3732#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3733#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3734#define CAN_F10R1_FB19_Pos (19U)
3735#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3736#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3737#define CAN_F10R1_FB20_Pos (20U)
3738#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3739#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3740#define CAN_F10R1_FB21_Pos (21U)
3741#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3742#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3743#define CAN_F10R1_FB22_Pos (22U)
3744#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3745#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3746#define CAN_F10R1_FB23_Pos (23U)
3747#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3748#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3749#define CAN_F10R1_FB24_Pos (24U)
3750#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3751#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3752#define CAN_F10R1_FB25_Pos (25U)
3753#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3754#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3755#define CAN_F10R1_FB26_Pos (26U)
3756#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3757#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3758#define CAN_F10R1_FB27_Pos (27U)
3759#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3760#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3761#define CAN_F10R1_FB28_Pos (28U)
3762#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3763#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3764#define CAN_F10R1_FB29_Pos (29U)
3765#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3766#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3767#define CAN_F10R1_FB30_Pos (30U)
3768#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3769#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3770#define CAN_F10R1_FB31_Pos (31U)
3771#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3772#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3774/******************* Bit definition for CAN_F11R1 register ******************/
3775#define CAN_F11R1_FB0_Pos (0U)
3776#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3777#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3778#define CAN_F11R1_FB1_Pos (1U)
3779#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3780#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3781#define CAN_F11R1_FB2_Pos (2U)
3782#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3783#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3784#define CAN_F11R1_FB3_Pos (3U)
3785#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3786#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3787#define CAN_F11R1_FB4_Pos (4U)
3788#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3789#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3790#define CAN_F11R1_FB5_Pos (5U)
3791#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3792#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3793#define CAN_F11R1_FB6_Pos (6U)
3794#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3795#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3796#define CAN_F11R1_FB7_Pos (7U)
3797#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3798#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3799#define CAN_F11R1_FB8_Pos (8U)
3800#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3801#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3802#define CAN_F11R1_FB9_Pos (9U)
3803#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3804#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3805#define CAN_F11R1_FB10_Pos (10U)
3806#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3807#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3808#define CAN_F11R1_FB11_Pos (11U)
3809#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3810#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3811#define CAN_F11R1_FB12_Pos (12U)
3812#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3813#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3814#define CAN_F11R1_FB13_Pos (13U)
3815#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3816#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3817#define CAN_F11R1_FB14_Pos (14U)
3818#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3819#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3820#define CAN_F11R1_FB15_Pos (15U)
3821#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3822#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3823#define CAN_F11R1_FB16_Pos (16U)
3824#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3825#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3826#define CAN_F11R1_FB17_Pos (17U)
3827#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3828#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3829#define CAN_F11R1_FB18_Pos (18U)
3830#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3831#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3832#define CAN_F11R1_FB19_Pos (19U)
3833#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3834#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3835#define CAN_F11R1_FB20_Pos (20U)
3836#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3837#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3838#define CAN_F11R1_FB21_Pos (21U)
3839#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3840#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3841#define CAN_F11R1_FB22_Pos (22U)
3842#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3843#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3844#define CAN_F11R1_FB23_Pos (23U)
3845#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3846#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3847#define CAN_F11R1_FB24_Pos (24U)
3848#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3849#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3850#define CAN_F11R1_FB25_Pos (25U)
3851#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3852#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3853#define CAN_F11R1_FB26_Pos (26U)
3854#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3855#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3856#define CAN_F11R1_FB27_Pos (27U)
3857#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3858#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3859#define CAN_F11R1_FB28_Pos (28U)
3860#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3861#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3862#define CAN_F11R1_FB29_Pos (29U)
3863#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3864#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3865#define CAN_F11R1_FB30_Pos (30U)
3866#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3867#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3868#define CAN_F11R1_FB31_Pos (31U)
3869#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3870#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3872/******************* Bit definition for CAN_F12R1 register ******************/
3873#define CAN_F12R1_FB0_Pos (0U)
3874#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3875#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3876#define CAN_F12R1_FB1_Pos (1U)
3877#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
3878#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
3879#define CAN_F12R1_FB2_Pos (2U)
3880#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
3881#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
3882#define CAN_F12R1_FB3_Pos (3U)
3883#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
3884#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
3885#define CAN_F12R1_FB4_Pos (4U)
3886#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
3887#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
3888#define CAN_F12R1_FB5_Pos (5U)
3889#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
3890#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
3891#define CAN_F12R1_FB6_Pos (6U)
3892#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
3893#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
3894#define CAN_F12R1_FB7_Pos (7U)
3895#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
3896#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
3897#define CAN_F12R1_FB8_Pos (8U)
3898#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
3899#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
3900#define CAN_F12R1_FB9_Pos (9U)
3901#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
3902#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
3903#define CAN_F12R1_FB10_Pos (10U)
3904#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
3905#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
3906#define CAN_F12R1_FB11_Pos (11U)
3907#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
3908#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
3909#define CAN_F12R1_FB12_Pos (12U)
3910#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
3911#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
3912#define CAN_F12R1_FB13_Pos (13U)
3913#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
3914#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
3915#define CAN_F12R1_FB14_Pos (14U)
3916#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
3917#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
3918#define CAN_F12R1_FB15_Pos (15U)
3919#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
3920#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
3921#define CAN_F12R1_FB16_Pos (16U)
3922#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
3923#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
3924#define CAN_F12R1_FB17_Pos (17U)
3925#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
3926#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
3927#define CAN_F12R1_FB18_Pos (18U)
3928#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
3929#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
3930#define CAN_F12R1_FB19_Pos (19U)
3931#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
3932#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
3933#define CAN_F12R1_FB20_Pos (20U)
3934#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
3935#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
3936#define CAN_F12R1_FB21_Pos (21U)
3937#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
3938#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
3939#define CAN_F12R1_FB22_Pos (22U)
3940#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
3941#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
3942#define CAN_F12R1_FB23_Pos (23U)
3943#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
3944#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
3945#define CAN_F12R1_FB24_Pos (24U)
3946#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
3947#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
3948#define CAN_F12R1_FB25_Pos (25U)
3949#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
3950#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
3951#define CAN_F12R1_FB26_Pos (26U)
3952#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
3953#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
3954#define CAN_F12R1_FB27_Pos (27U)
3955#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
3956#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
3957#define CAN_F12R1_FB28_Pos (28U)
3958#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
3959#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
3960#define CAN_F12R1_FB29_Pos (29U)
3961#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
3962#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
3963#define CAN_F12R1_FB30_Pos (30U)
3964#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
3965#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
3966#define CAN_F12R1_FB31_Pos (31U)
3967#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
3968#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
3970/******************* Bit definition for CAN_F13R1 register ******************/
3971#define CAN_F13R1_FB0_Pos (0U)
3972#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
3973#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
3974#define CAN_F13R1_FB1_Pos (1U)
3975#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
3976#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
3977#define CAN_F13R1_FB2_Pos (2U)
3978#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
3979#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
3980#define CAN_F13R1_FB3_Pos (3U)
3981#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
3982#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
3983#define CAN_F13R1_FB4_Pos (4U)
3984#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
3985#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
3986#define CAN_F13R1_FB5_Pos (5U)
3987#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
3988#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
3989#define CAN_F13R1_FB6_Pos (6U)
3990#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
3991#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
3992#define CAN_F13R1_FB7_Pos (7U)
3993#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
3994#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
3995#define CAN_F13R1_FB8_Pos (8U)
3996#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
3997#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
3998#define CAN_F13R1_FB9_Pos (9U)
3999#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4000#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4001#define CAN_F13R1_FB10_Pos (10U)
4002#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4003#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4004#define CAN_F13R1_FB11_Pos (11U)
4005#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4006#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4007#define CAN_F13R1_FB12_Pos (12U)
4008#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4009#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4010#define CAN_F13R1_FB13_Pos (13U)
4011#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4012#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4013#define CAN_F13R1_FB14_Pos (14U)
4014#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4015#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4016#define CAN_F13R1_FB15_Pos (15U)
4017#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4018#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4019#define CAN_F13R1_FB16_Pos (16U)
4020#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4021#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4022#define CAN_F13R1_FB17_Pos (17U)
4023#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4024#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4025#define CAN_F13R1_FB18_Pos (18U)
4026#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4027#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4028#define CAN_F13R1_FB19_Pos (19U)
4029#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4030#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4031#define CAN_F13R1_FB20_Pos (20U)
4032#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4033#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4034#define CAN_F13R1_FB21_Pos (21U)
4035#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4036#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4037#define CAN_F13R1_FB22_Pos (22U)
4038#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4039#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4040#define CAN_F13R1_FB23_Pos (23U)
4041#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4042#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4043#define CAN_F13R1_FB24_Pos (24U)
4044#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4045#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4046#define CAN_F13R1_FB25_Pos (25U)
4047#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4048#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4049#define CAN_F13R1_FB26_Pos (26U)
4050#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4051#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4052#define CAN_F13R1_FB27_Pos (27U)
4053#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4054#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4055#define CAN_F13R1_FB28_Pos (28U)
4056#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4057#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4058#define CAN_F13R1_FB29_Pos (29U)
4059#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4060#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4061#define CAN_F13R1_FB30_Pos (30U)
4062#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4063#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4064#define CAN_F13R1_FB31_Pos (31U)
4065#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4066#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4068/******************* Bit definition for CAN_F0R2 register *******************/
4069#define CAN_F0R2_FB0_Pos (0U)
4070#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4071#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4072#define CAN_F0R2_FB1_Pos (1U)
4073#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4074#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4075#define CAN_F0R2_FB2_Pos (2U)
4076#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4077#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4078#define CAN_F0R2_FB3_Pos (3U)
4079#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4080#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4081#define CAN_F0R2_FB4_Pos (4U)
4082#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4083#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4084#define CAN_F0R2_FB5_Pos (5U)
4085#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4086#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4087#define CAN_F0R2_FB6_Pos (6U)
4088#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4089#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4090#define CAN_F0R2_FB7_Pos (7U)
4091#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4092#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4093#define CAN_F0R2_FB8_Pos (8U)
4094#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4095#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4096#define CAN_F0R2_FB9_Pos (9U)
4097#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4098#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4099#define CAN_F0R2_FB10_Pos (10U)
4100#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4101#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4102#define CAN_F0R2_FB11_Pos (11U)
4103#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4104#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4105#define CAN_F0R2_FB12_Pos (12U)
4106#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4107#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4108#define CAN_F0R2_FB13_Pos (13U)
4109#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4110#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4111#define CAN_F0R2_FB14_Pos (14U)
4112#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4113#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4114#define CAN_F0R2_FB15_Pos (15U)
4115#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4116#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4117#define CAN_F0R2_FB16_Pos (16U)
4118#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4119#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4120#define CAN_F0R2_FB17_Pos (17U)
4121#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4122#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4123#define CAN_F0R2_FB18_Pos (18U)
4124#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4125#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4126#define CAN_F0R2_FB19_Pos (19U)
4127#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4128#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4129#define CAN_F0R2_FB20_Pos (20U)
4130#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4131#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4132#define CAN_F0R2_FB21_Pos (21U)
4133#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4134#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4135#define CAN_F0R2_FB22_Pos (22U)
4136#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4137#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4138#define CAN_F0R2_FB23_Pos (23U)
4139#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4140#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4141#define CAN_F0R2_FB24_Pos (24U)
4142#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4143#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4144#define CAN_F0R2_FB25_Pos (25U)
4145#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4146#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4147#define CAN_F0R2_FB26_Pos (26U)
4148#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4149#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4150#define CAN_F0R2_FB27_Pos (27U)
4151#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4152#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4153#define CAN_F0R2_FB28_Pos (28U)
4154#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4155#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4156#define CAN_F0R2_FB29_Pos (29U)
4157#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4158#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4159#define CAN_F0R2_FB30_Pos (30U)
4160#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4161#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4162#define CAN_F0R2_FB31_Pos (31U)
4163#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4164#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4166/******************* Bit definition for CAN_F1R2 register *******************/
4167#define CAN_F1R2_FB0_Pos (0U)
4168#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4169#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4170#define CAN_F1R2_FB1_Pos (1U)
4171#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4172#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4173#define CAN_F1R2_FB2_Pos (2U)
4174#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4175#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4176#define CAN_F1R2_FB3_Pos (3U)
4177#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4178#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4179#define CAN_F1R2_FB4_Pos (4U)
4180#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4181#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4182#define CAN_F1R2_FB5_Pos (5U)
4183#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4184#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4185#define CAN_F1R2_FB6_Pos (6U)
4186#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4187#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4188#define CAN_F1R2_FB7_Pos (7U)
4189#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4190#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4191#define CAN_F1R2_FB8_Pos (8U)
4192#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4193#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4194#define CAN_F1R2_FB9_Pos (9U)
4195#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4196#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4197#define CAN_F1R2_FB10_Pos (10U)
4198#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4199#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4200#define CAN_F1R2_FB11_Pos (11U)
4201#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4202#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4203#define CAN_F1R2_FB12_Pos (12U)
4204#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4205#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4206#define CAN_F1R2_FB13_Pos (13U)
4207#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4208#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4209#define CAN_F1R2_FB14_Pos (14U)
4210#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4211#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4212#define CAN_F1R2_FB15_Pos (15U)
4213#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4214#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4215#define CAN_F1R2_FB16_Pos (16U)
4216#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4217#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4218#define CAN_F1R2_FB17_Pos (17U)
4219#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4220#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4221#define CAN_F1R2_FB18_Pos (18U)
4222#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4223#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4224#define CAN_F1R2_FB19_Pos (19U)
4225#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4226#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4227#define CAN_F1R2_FB20_Pos (20U)
4228#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4229#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4230#define CAN_F1R2_FB21_Pos (21U)
4231#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4232#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4233#define CAN_F1R2_FB22_Pos (22U)
4234#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4235#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4236#define CAN_F1R2_FB23_Pos (23U)
4237#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4238#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4239#define CAN_F1R2_FB24_Pos (24U)
4240#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4241#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4242#define CAN_F1R2_FB25_Pos (25U)
4243#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4244#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4245#define CAN_F1R2_FB26_Pos (26U)
4246#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4247#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4248#define CAN_F1R2_FB27_Pos (27U)
4249#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4250#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4251#define CAN_F1R2_FB28_Pos (28U)
4252#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4253#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4254#define CAN_F1R2_FB29_Pos (29U)
4255#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4256#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4257#define CAN_F1R2_FB30_Pos (30U)
4258#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4259#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4260#define CAN_F1R2_FB31_Pos (31U)
4261#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4262#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4264/******************* Bit definition for CAN_F2R2 register *******************/
4265#define CAN_F2R2_FB0_Pos (0U)
4266#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4267#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4268#define CAN_F2R2_FB1_Pos (1U)
4269#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4270#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4271#define CAN_F2R2_FB2_Pos (2U)
4272#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4273#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4274#define CAN_F2R2_FB3_Pos (3U)
4275#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4276#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4277#define CAN_F2R2_FB4_Pos (4U)
4278#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4279#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4280#define CAN_F2R2_FB5_Pos (5U)
4281#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4282#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4283#define CAN_F2R2_FB6_Pos (6U)
4284#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4285#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4286#define CAN_F2R2_FB7_Pos (7U)
4287#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4288#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4289#define CAN_F2R2_FB8_Pos (8U)
4290#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4291#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4292#define CAN_F2R2_FB9_Pos (9U)
4293#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4294#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4295#define CAN_F2R2_FB10_Pos (10U)
4296#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4297#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4298#define CAN_F2R2_FB11_Pos (11U)
4299#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4300#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4301#define CAN_F2R2_FB12_Pos (12U)
4302#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4303#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4304#define CAN_F2R2_FB13_Pos (13U)
4305#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4306#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4307#define CAN_F2R2_FB14_Pos (14U)
4308#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4309#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4310#define CAN_F2R2_FB15_Pos (15U)
4311#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4312#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4313#define CAN_F2R2_FB16_Pos (16U)
4314#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4315#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4316#define CAN_F2R2_FB17_Pos (17U)
4317#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4318#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4319#define CAN_F2R2_FB18_Pos (18U)
4320#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4321#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4322#define CAN_F2R2_FB19_Pos (19U)
4323#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4324#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4325#define CAN_F2R2_FB20_Pos (20U)
4326#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4327#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4328#define CAN_F2R2_FB21_Pos (21U)
4329#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4330#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4331#define CAN_F2R2_FB22_Pos (22U)
4332#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4333#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4334#define CAN_F2R2_FB23_Pos (23U)
4335#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4336#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4337#define CAN_F2R2_FB24_Pos (24U)
4338#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4339#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4340#define CAN_F2R2_FB25_Pos (25U)
4341#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4342#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4343#define CAN_F2R2_FB26_Pos (26U)
4344#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4345#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4346#define CAN_F2R2_FB27_Pos (27U)
4347#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4348#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4349#define CAN_F2R2_FB28_Pos (28U)
4350#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4351#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4352#define CAN_F2R2_FB29_Pos (29U)
4353#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4354#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4355#define CAN_F2R2_FB30_Pos (30U)
4356#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4357#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4358#define CAN_F2R2_FB31_Pos (31U)
4359#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4360#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4362/******************* Bit definition for CAN_F3R2 register *******************/
4363#define CAN_F3R2_FB0_Pos (0U)
4364#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4365#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4366#define CAN_F3R2_FB1_Pos (1U)
4367#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4368#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4369#define CAN_F3R2_FB2_Pos (2U)
4370#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4371#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4372#define CAN_F3R2_FB3_Pos (3U)
4373#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4374#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4375#define CAN_F3R2_FB4_Pos (4U)
4376#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4377#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4378#define CAN_F3R2_FB5_Pos (5U)
4379#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4380#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4381#define CAN_F3R2_FB6_Pos (6U)
4382#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4383#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4384#define CAN_F3R2_FB7_Pos (7U)
4385#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4386#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4387#define CAN_F3R2_FB8_Pos (8U)
4388#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4389#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4390#define CAN_F3R2_FB9_Pos (9U)
4391#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4392#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4393#define CAN_F3R2_FB10_Pos (10U)
4394#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4395#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4396#define CAN_F3R2_FB11_Pos (11U)
4397#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4398#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4399#define CAN_F3R2_FB12_Pos (12U)
4400#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4401#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4402#define CAN_F3R2_FB13_Pos (13U)
4403#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4404#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4405#define CAN_F3R2_FB14_Pos (14U)
4406#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4407#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4408#define CAN_F3R2_FB15_Pos (15U)
4409#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4410#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4411#define CAN_F3R2_FB16_Pos (16U)
4412#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4413#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4414#define CAN_F3R2_FB17_Pos (17U)
4415#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4416#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4417#define CAN_F3R2_FB18_Pos (18U)
4418#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4419#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4420#define CAN_F3R2_FB19_Pos (19U)
4421#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4422#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4423#define CAN_F3R2_FB20_Pos (20U)
4424#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4425#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4426#define CAN_F3R2_FB21_Pos (21U)
4427#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4428#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4429#define CAN_F3R2_FB22_Pos (22U)
4430#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4431#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4432#define CAN_F3R2_FB23_Pos (23U)
4433#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4434#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4435#define CAN_F3R2_FB24_Pos (24U)
4436#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4437#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4438#define CAN_F3R2_FB25_Pos (25U)
4439#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4440#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4441#define CAN_F3R2_FB26_Pos (26U)
4442#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4443#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4444#define CAN_F3R2_FB27_Pos (27U)
4445#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4446#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4447#define CAN_F3R2_FB28_Pos (28U)
4448#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4449#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4450#define CAN_F3R2_FB29_Pos (29U)
4451#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4452#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4453#define CAN_F3R2_FB30_Pos (30U)
4454#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4455#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4456#define CAN_F3R2_FB31_Pos (31U)
4457#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4458#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4460/******************* Bit definition for CAN_F4R2 register *******************/
4461#define CAN_F4R2_FB0_Pos (0U)
4462#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4463#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4464#define CAN_F4R2_FB1_Pos (1U)
4465#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4466#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4467#define CAN_F4R2_FB2_Pos (2U)
4468#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4469#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4470#define CAN_F4R2_FB3_Pos (3U)
4471#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4472#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4473#define CAN_F4R2_FB4_Pos (4U)
4474#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4475#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4476#define CAN_F4R2_FB5_Pos (5U)
4477#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4478#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4479#define CAN_F4R2_FB6_Pos (6U)
4480#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4481#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4482#define CAN_F4R2_FB7_Pos (7U)
4483#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4484#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4485#define CAN_F4R2_FB8_Pos (8U)
4486#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4487#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4488#define CAN_F4R2_FB9_Pos (9U)
4489#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4490#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4491#define CAN_F4R2_FB10_Pos (10U)
4492#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4493#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4494#define CAN_F4R2_FB11_Pos (11U)
4495#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4496#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4497#define CAN_F4R2_FB12_Pos (12U)
4498#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4499#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4500#define CAN_F4R2_FB13_Pos (13U)
4501#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4502#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4503#define CAN_F4R2_FB14_Pos (14U)
4504#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4505#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4506#define CAN_F4R2_FB15_Pos (15U)
4507#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4508#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4509#define CAN_F4R2_FB16_Pos (16U)
4510#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4511#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4512#define CAN_F4R2_FB17_Pos (17U)
4513#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4514#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4515#define CAN_F4R2_FB18_Pos (18U)
4516#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4517#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4518#define CAN_F4R2_FB19_Pos (19U)
4519#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4520#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4521#define CAN_F4R2_FB20_Pos (20U)
4522#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4523#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4524#define CAN_F4R2_FB21_Pos (21U)
4525#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4526#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4527#define CAN_F4R2_FB22_Pos (22U)
4528#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4529#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4530#define CAN_F4R2_FB23_Pos (23U)
4531#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4532#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4533#define CAN_F4R2_FB24_Pos (24U)
4534#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4535#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4536#define CAN_F4R2_FB25_Pos (25U)
4537#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4538#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4539#define CAN_F4R2_FB26_Pos (26U)
4540#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4541#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4542#define CAN_F4R2_FB27_Pos (27U)
4543#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4544#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4545#define CAN_F4R2_FB28_Pos (28U)
4546#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4547#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4548#define CAN_F4R2_FB29_Pos (29U)
4549#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4550#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4551#define CAN_F4R2_FB30_Pos (30U)
4552#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4553#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4554#define CAN_F4R2_FB31_Pos (31U)
4555#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4556#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4558/******************* Bit definition for CAN_F5R2 register *******************/
4559#define CAN_F5R2_FB0_Pos (0U)
4560#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4561#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4562#define CAN_F5R2_FB1_Pos (1U)
4563#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4564#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4565#define CAN_F5R2_FB2_Pos (2U)
4566#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4567#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4568#define CAN_F5R2_FB3_Pos (3U)
4569#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4570#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4571#define CAN_F5R2_FB4_Pos (4U)
4572#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4573#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4574#define CAN_F5R2_FB5_Pos (5U)
4575#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4576#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4577#define CAN_F5R2_FB6_Pos (6U)
4578#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4579#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4580#define CAN_F5R2_FB7_Pos (7U)
4581#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4582#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4583#define CAN_F5R2_FB8_Pos (8U)
4584#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4585#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4586#define CAN_F5R2_FB9_Pos (9U)
4587#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4588#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4589#define CAN_F5R2_FB10_Pos (10U)
4590#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4591#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4592#define CAN_F5R2_FB11_Pos (11U)
4593#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4594#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4595#define CAN_F5R2_FB12_Pos (12U)
4596#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4597#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4598#define CAN_F5R2_FB13_Pos (13U)
4599#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4600#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4601#define CAN_F5R2_FB14_Pos (14U)
4602#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4603#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4604#define CAN_F5R2_FB15_Pos (15U)
4605#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4606#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4607#define CAN_F5R2_FB16_Pos (16U)
4608#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4609#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4610#define CAN_F5R2_FB17_Pos (17U)
4611#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4612#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4613#define CAN_F5R2_FB18_Pos (18U)
4614#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4615#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4616#define CAN_F5R2_FB19_Pos (19U)
4617#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4618#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4619#define CAN_F5R2_FB20_Pos (20U)
4620#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4621#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4622#define CAN_F5R2_FB21_Pos (21U)
4623#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4624#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4625#define CAN_F5R2_FB22_Pos (22U)
4626#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4627#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4628#define CAN_F5R2_FB23_Pos (23U)
4629#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4630#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4631#define CAN_F5R2_FB24_Pos (24U)
4632#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4633#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4634#define CAN_F5R2_FB25_Pos (25U)
4635#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4636#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4637#define CAN_F5R2_FB26_Pos (26U)
4638#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4639#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4640#define CAN_F5R2_FB27_Pos (27U)
4641#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4642#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4643#define CAN_F5R2_FB28_Pos (28U)
4644#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4645#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4646#define CAN_F5R2_FB29_Pos (29U)
4647#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4648#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4649#define CAN_F5R2_FB30_Pos (30U)
4650#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4651#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4652#define CAN_F5R2_FB31_Pos (31U)
4653#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4654#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4656/******************* Bit definition for CAN_F6R2 register *******************/
4657#define CAN_F6R2_FB0_Pos (0U)
4658#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4659#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4660#define CAN_F6R2_FB1_Pos (1U)
4661#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4662#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4663#define CAN_F6R2_FB2_Pos (2U)
4664#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4665#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4666#define CAN_F6R2_FB3_Pos (3U)
4667#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4668#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4669#define CAN_F6R2_FB4_Pos (4U)
4670#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4671#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4672#define CAN_F6R2_FB5_Pos (5U)
4673#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4674#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4675#define CAN_F6R2_FB6_Pos (6U)
4676#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4677#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4678#define CAN_F6R2_FB7_Pos (7U)
4679#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4680#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4681#define CAN_F6R2_FB8_Pos (8U)
4682#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4683#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4684#define CAN_F6R2_FB9_Pos (9U)
4685#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4686#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4687#define CAN_F6R2_FB10_Pos (10U)
4688#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4689#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4690#define CAN_F6R2_FB11_Pos (11U)
4691#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4692#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4693#define CAN_F6R2_FB12_Pos (12U)
4694#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4695#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4696#define CAN_F6R2_FB13_Pos (13U)
4697#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4698#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4699#define CAN_F6R2_FB14_Pos (14U)
4700#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4701#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4702#define CAN_F6R2_FB15_Pos (15U)
4703#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4704#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4705#define CAN_F6R2_FB16_Pos (16U)
4706#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4707#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4708#define CAN_F6R2_FB17_Pos (17U)
4709#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4710#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4711#define CAN_F6R2_FB18_Pos (18U)
4712#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4713#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4714#define CAN_F6R2_FB19_Pos (19U)
4715#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4716#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4717#define CAN_F6R2_FB20_Pos (20U)
4718#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4719#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4720#define CAN_F6R2_FB21_Pos (21U)
4721#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4722#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4723#define CAN_F6R2_FB22_Pos (22U)
4724#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4725#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4726#define CAN_F6R2_FB23_Pos (23U)
4727#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4728#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4729#define CAN_F6R2_FB24_Pos (24U)
4730#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4731#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4732#define CAN_F6R2_FB25_Pos (25U)
4733#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4734#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4735#define CAN_F6R2_FB26_Pos (26U)
4736#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4737#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4738#define CAN_F6R2_FB27_Pos (27U)
4739#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4740#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4741#define CAN_F6R2_FB28_Pos (28U)
4742#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4743#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4744#define CAN_F6R2_FB29_Pos (29U)
4745#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4746#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4747#define CAN_F6R2_FB30_Pos (30U)
4748#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4749#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4750#define CAN_F6R2_FB31_Pos (31U)
4751#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4752#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4754/******************* Bit definition for CAN_F7R2 register *******************/
4755#define CAN_F7R2_FB0_Pos (0U)
4756#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4757#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4758#define CAN_F7R2_FB1_Pos (1U)
4759#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4760#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4761#define CAN_F7R2_FB2_Pos (2U)
4762#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4763#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4764#define CAN_F7R2_FB3_Pos (3U)
4765#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4766#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4767#define CAN_F7R2_FB4_Pos (4U)
4768#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4769#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4770#define CAN_F7R2_FB5_Pos (5U)
4771#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4772#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4773#define CAN_F7R2_FB6_Pos (6U)
4774#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4775#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4776#define CAN_F7R2_FB7_Pos (7U)
4777#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4778#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4779#define CAN_F7R2_FB8_Pos (8U)
4780#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4781#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4782#define CAN_F7R2_FB9_Pos (9U)
4783#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4784#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4785#define CAN_F7R2_FB10_Pos (10U)
4786#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4787#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4788#define CAN_F7R2_FB11_Pos (11U)
4789#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4790#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4791#define CAN_F7R2_FB12_Pos (12U)
4792#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4793#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4794#define CAN_F7R2_FB13_Pos (13U)
4795#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4796#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4797#define CAN_F7R2_FB14_Pos (14U)
4798#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4799#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4800#define CAN_F7R2_FB15_Pos (15U)
4801#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4802#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4803#define CAN_F7R2_FB16_Pos (16U)
4804#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4805#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4806#define CAN_F7R2_FB17_Pos (17U)
4807#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4808#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4809#define CAN_F7R2_FB18_Pos (18U)
4810#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4811#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4812#define CAN_F7R2_FB19_Pos (19U)
4813#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4814#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4815#define CAN_F7R2_FB20_Pos (20U)
4816#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4817#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4818#define CAN_F7R2_FB21_Pos (21U)
4819#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4820#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4821#define CAN_F7R2_FB22_Pos (22U)
4822#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4823#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4824#define CAN_F7R2_FB23_Pos (23U)
4825#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4826#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4827#define CAN_F7R2_FB24_Pos (24U)
4828#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4829#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4830#define CAN_F7R2_FB25_Pos (25U)
4831#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4832#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4833#define CAN_F7R2_FB26_Pos (26U)
4834#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4835#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4836#define CAN_F7R2_FB27_Pos (27U)
4837#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4838#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4839#define CAN_F7R2_FB28_Pos (28U)
4840#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4841#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4842#define CAN_F7R2_FB29_Pos (29U)
4843#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4844#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4845#define CAN_F7R2_FB30_Pos (30U)
4846#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4847#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4848#define CAN_F7R2_FB31_Pos (31U)
4849#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4850#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4852/******************* Bit definition for CAN_F8R2 register *******************/
4853#define CAN_F8R2_FB0_Pos (0U)
4854#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4855#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4856#define CAN_F8R2_FB1_Pos (1U)
4857#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4858#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4859#define CAN_F8R2_FB2_Pos (2U)
4860#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4861#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4862#define CAN_F8R2_FB3_Pos (3U)
4863#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4864#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4865#define CAN_F8R2_FB4_Pos (4U)
4866#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4867#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4868#define CAN_F8R2_FB5_Pos (5U)
4869#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4870#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4871#define CAN_F8R2_FB6_Pos (6U)
4872#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4873#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4874#define CAN_F8R2_FB7_Pos (7U)
4875#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4876#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4877#define CAN_F8R2_FB8_Pos (8U)
4878#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
4879#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
4880#define CAN_F8R2_FB9_Pos (9U)
4881#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
4882#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
4883#define CAN_F8R2_FB10_Pos (10U)
4884#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
4885#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
4886#define CAN_F8R2_FB11_Pos (11U)
4887#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
4888#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
4889#define CAN_F8R2_FB12_Pos (12U)
4890#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
4891#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
4892#define CAN_F8R2_FB13_Pos (13U)
4893#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
4894#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
4895#define CAN_F8R2_FB14_Pos (14U)
4896#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
4897#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
4898#define CAN_F8R2_FB15_Pos (15U)
4899#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
4900#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
4901#define CAN_F8R2_FB16_Pos (16U)
4902#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
4903#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
4904#define CAN_F8R2_FB17_Pos (17U)
4905#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
4906#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
4907#define CAN_F8R2_FB18_Pos (18U)
4908#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
4909#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
4910#define CAN_F8R2_FB19_Pos (19U)
4911#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
4912#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
4913#define CAN_F8R2_FB20_Pos (20U)
4914#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
4915#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
4916#define CAN_F8R2_FB21_Pos (21U)
4917#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
4918#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
4919#define CAN_F8R2_FB22_Pos (22U)
4920#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
4921#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
4922#define CAN_F8R2_FB23_Pos (23U)
4923#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
4924#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
4925#define CAN_F8R2_FB24_Pos (24U)
4926#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
4927#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
4928#define CAN_F8R2_FB25_Pos (25U)
4929#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
4930#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
4931#define CAN_F8R2_FB26_Pos (26U)
4932#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
4933#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
4934#define CAN_F8R2_FB27_Pos (27U)
4935#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
4936#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
4937#define CAN_F8R2_FB28_Pos (28U)
4938#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
4939#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
4940#define CAN_F8R2_FB29_Pos (29U)
4941#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
4942#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
4943#define CAN_F8R2_FB30_Pos (30U)
4944#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
4945#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
4946#define CAN_F8R2_FB31_Pos (31U)
4947#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
4948#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
4950/******************* Bit definition for CAN_F9R2 register *******************/
4951#define CAN_F9R2_FB0_Pos (0U)
4952#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
4953#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
4954#define CAN_F9R2_FB1_Pos (1U)
4955#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
4956#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
4957#define CAN_F9R2_FB2_Pos (2U)
4958#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
4959#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
4960#define CAN_F9R2_FB3_Pos (3U)
4961#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
4962#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
4963#define CAN_F9R2_FB4_Pos (4U)
4964#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
4965#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
4966#define CAN_F9R2_FB5_Pos (5U)
4967#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
4968#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
4969#define CAN_F9R2_FB6_Pos (6U)
4970#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
4971#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
4972#define CAN_F9R2_FB7_Pos (7U)
4973#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
4974#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
4975#define CAN_F9R2_FB8_Pos (8U)
4976#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
4977#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
4978#define CAN_F9R2_FB9_Pos (9U)
4979#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
4980#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
4981#define CAN_F9R2_FB10_Pos (10U)
4982#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
4983#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
4984#define CAN_F9R2_FB11_Pos (11U)
4985#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
4986#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
4987#define CAN_F9R2_FB12_Pos (12U)
4988#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
4989#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
4990#define CAN_F9R2_FB13_Pos (13U)
4991#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
4992#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
4993#define CAN_F9R2_FB14_Pos (14U)
4994#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
4995#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
4996#define CAN_F9R2_FB15_Pos (15U)
4997#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
4998#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
4999#define CAN_F9R2_FB16_Pos (16U)
5000#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5001#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5002#define CAN_F9R2_FB17_Pos (17U)
5003#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5004#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5005#define CAN_F9R2_FB18_Pos (18U)
5006#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5007#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5008#define CAN_F9R2_FB19_Pos (19U)
5009#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5010#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5011#define CAN_F9R2_FB20_Pos (20U)
5012#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5013#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5014#define CAN_F9R2_FB21_Pos (21U)
5015#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5016#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5017#define CAN_F9R2_FB22_Pos (22U)
5018#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5019#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5020#define CAN_F9R2_FB23_Pos (23U)
5021#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5022#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5023#define CAN_F9R2_FB24_Pos (24U)
5024#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5025#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5026#define CAN_F9R2_FB25_Pos (25U)
5027#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5028#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5029#define CAN_F9R2_FB26_Pos (26U)
5030#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5031#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5032#define CAN_F9R2_FB27_Pos (27U)
5033#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5034#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5035#define CAN_F9R2_FB28_Pos (28U)
5036#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5037#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5038#define CAN_F9R2_FB29_Pos (29U)
5039#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5040#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5041#define CAN_F9R2_FB30_Pos (30U)
5042#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5043#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5044#define CAN_F9R2_FB31_Pos (31U)
5045#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5046#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5048/******************* Bit definition for CAN_F10R2 register ******************/
5049#define CAN_F10R2_FB0_Pos (0U)
5050#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5051#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5052#define CAN_F10R2_FB1_Pos (1U)
5053#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5054#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5055#define CAN_F10R2_FB2_Pos (2U)
5056#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5057#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5058#define CAN_F10R2_FB3_Pos (3U)
5059#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5060#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5061#define CAN_F10R2_FB4_Pos (4U)
5062#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5063#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5064#define CAN_F10R2_FB5_Pos (5U)
5065#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5066#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5067#define CAN_F10R2_FB6_Pos (6U)
5068#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5069#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5070#define CAN_F10R2_FB7_Pos (7U)
5071#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5072#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5073#define CAN_F10R2_FB8_Pos (8U)
5074#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5075#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5076#define CAN_F10R2_FB9_Pos (9U)
5077#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5078#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5079#define CAN_F10R2_FB10_Pos (10U)
5080#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5081#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5082#define CAN_F10R2_FB11_Pos (11U)
5083#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5084#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5085#define CAN_F10R2_FB12_Pos (12U)
5086#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5087#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5088#define CAN_F10R2_FB13_Pos (13U)
5089#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5090#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5091#define CAN_F10R2_FB14_Pos (14U)
5092#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5093#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5094#define CAN_F10R2_FB15_Pos (15U)
5095#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5096#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5097#define CAN_F10R2_FB16_Pos (16U)
5098#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5099#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5100#define CAN_F10R2_FB17_Pos (17U)
5101#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5102#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5103#define CAN_F10R2_FB18_Pos (18U)
5104#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5105#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5106#define CAN_F10R2_FB19_Pos (19U)
5107#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5108#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5109#define CAN_F10R2_FB20_Pos (20U)
5110#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5111#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5112#define CAN_F10R2_FB21_Pos (21U)
5113#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5114#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5115#define CAN_F10R2_FB22_Pos (22U)
5116#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5117#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5118#define CAN_F10R2_FB23_Pos (23U)
5119#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5120#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5121#define CAN_F10R2_FB24_Pos (24U)
5122#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5123#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5124#define CAN_F10R2_FB25_Pos (25U)
5125#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5126#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5127#define CAN_F10R2_FB26_Pos (26U)
5128#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5129#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5130#define CAN_F10R2_FB27_Pos (27U)
5131#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5132#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5133#define CAN_F10R2_FB28_Pos (28U)
5134#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5135#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5136#define CAN_F10R2_FB29_Pos (29U)
5137#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5138#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5139#define CAN_F10R2_FB30_Pos (30U)
5140#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5141#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5142#define CAN_F10R2_FB31_Pos (31U)
5143#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5144#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5146/******************* Bit definition for CAN_F11R2 register ******************/
5147#define CAN_F11R2_FB0_Pos (0U)
5148#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5149#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5150#define CAN_F11R2_FB1_Pos (1U)
5151#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5152#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5153#define CAN_F11R2_FB2_Pos (2U)
5154#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5155#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5156#define CAN_F11R2_FB3_Pos (3U)
5157#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5158#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5159#define CAN_F11R2_FB4_Pos (4U)
5160#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5161#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5162#define CAN_F11R2_FB5_Pos (5U)
5163#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5164#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5165#define CAN_F11R2_FB6_Pos (6U)
5166#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5167#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5168#define CAN_F11R2_FB7_Pos (7U)
5169#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5170#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5171#define CAN_F11R2_FB8_Pos (8U)
5172#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5173#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5174#define CAN_F11R2_FB9_Pos (9U)
5175#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5176#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5177#define CAN_F11R2_FB10_Pos (10U)
5178#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5179#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5180#define CAN_F11R2_FB11_Pos (11U)
5181#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5182#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5183#define CAN_F11R2_FB12_Pos (12U)
5184#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5185#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5186#define CAN_F11R2_FB13_Pos (13U)
5187#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5188#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5189#define CAN_F11R2_FB14_Pos (14U)
5190#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5191#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5192#define CAN_F11R2_FB15_Pos (15U)
5193#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5194#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5195#define CAN_F11R2_FB16_Pos (16U)
5196#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5197#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5198#define CAN_F11R2_FB17_Pos (17U)
5199#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5200#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5201#define CAN_F11R2_FB18_Pos (18U)
5202#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5203#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5204#define CAN_F11R2_FB19_Pos (19U)
5205#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5206#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5207#define CAN_F11R2_FB20_Pos (20U)
5208#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5209#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5210#define CAN_F11R2_FB21_Pos (21U)
5211#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5212#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5213#define CAN_F11R2_FB22_Pos (22U)
5214#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5215#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5216#define CAN_F11R2_FB23_Pos (23U)
5217#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5218#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5219#define CAN_F11R2_FB24_Pos (24U)
5220#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5221#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5222#define CAN_F11R2_FB25_Pos (25U)
5223#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5224#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5225#define CAN_F11R2_FB26_Pos (26U)
5226#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5227#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5228#define CAN_F11R2_FB27_Pos (27U)
5229#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5230#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5231#define CAN_F11R2_FB28_Pos (28U)
5232#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5233#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5234#define CAN_F11R2_FB29_Pos (29U)
5235#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5236#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5237#define CAN_F11R2_FB30_Pos (30U)
5238#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5239#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5240#define CAN_F11R2_FB31_Pos (31U)
5241#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5242#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5244/******************* Bit definition for CAN_F12R2 register ******************/
5245#define CAN_F12R2_FB0_Pos (0U)
5246#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5247#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5248#define CAN_F12R2_FB1_Pos (1U)
5249#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5250#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5251#define CAN_F12R2_FB2_Pos (2U)
5252#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5253#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5254#define CAN_F12R2_FB3_Pos (3U)
5255#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5256#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5257#define CAN_F12R2_FB4_Pos (4U)
5258#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5259#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5260#define CAN_F12R2_FB5_Pos (5U)
5261#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5262#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5263#define CAN_F12R2_FB6_Pos (6U)
5264#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5265#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5266#define CAN_F12R2_FB7_Pos (7U)
5267#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5268#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5269#define CAN_F12R2_FB8_Pos (8U)
5270#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5271#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5272#define CAN_F12R2_FB9_Pos (9U)
5273#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5274#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5275#define CAN_F12R2_FB10_Pos (10U)
5276#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5277#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5278#define CAN_F12R2_FB11_Pos (11U)
5279#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5280#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5281#define CAN_F12R2_FB12_Pos (12U)
5282#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5283#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5284#define CAN_F12R2_FB13_Pos (13U)
5285#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5286#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5287#define CAN_F12R2_FB14_Pos (14U)
5288#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5289#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5290#define CAN_F12R2_FB15_Pos (15U)
5291#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5292#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5293#define CAN_F12R2_FB16_Pos (16U)
5294#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5295#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5296#define CAN_F12R2_FB17_Pos (17U)
5297#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5298#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5299#define CAN_F12R2_FB18_Pos (18U)
5300#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5301#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5302#define CAN_F12R2_FB19_Pos (19U)
5303#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5304#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5305#define CAN_F12R2_FB20_Pos (20U)
5306#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5307#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5308#define CAN_F12R2_FB21_Pos (21U)
5309#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5310#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5311#define CAN_F12R2_FB22_Pos (22U)
5312#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5313#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5314#define CAN_F12R2_FB23_Pos (23U)
5315#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5316#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5317#define CAN_F12R2_FB24_Pos (24U)
5318#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5319#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5320#define CAN_F12R2_FB25_Pos (25U)
5321#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5322#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5323#define CAN_F12R2_FB26_Pos (26U)
5324#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5325#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5326#define CAN_F12R2_FB27_Pos (27U)
5327#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5328#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5329#define CAN_F12R2_FB28_Pos (28U)
5330#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5331#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5332#define CAN_F12R2_FB29_Pos (29U)
5333#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5334#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5335#define CAN_F12R2_FB30_Pos (30U)
5336#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5337#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5338#define CAN_F12R2_FB31_Pos (31U)
5339#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5340#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5342/******************* Bit definition for CAN_F13R2 register ******************/
5343#define CAN_F13R2_FB0_Pos (0U)
5344#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5345#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5346#define CAN_F13R2_FB1_Pos (1U)
5347#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5348#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5349#define CAN_F13R2_FB2_Pos (2U)
5350#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5351#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5352#define CAN_F13R2_FB3_Pos (3U)
5353#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5354#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5355#define CAN_F13R2_FB4_Pos (4U)
5356#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5357#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5358#define CAN_F13R2_FB5_Pos (5U)
5359#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5360#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5361#define CAN_F13R2_FB6_Pos (6U)
5362#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5363#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5364#define CAN_F13R2_FB7_Pos (7U)
5365#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5366#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5367#define CAN_F13R2_FB8_Pos (8U)
5368#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5369#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5370#define CAN_F13R2_FB9_Pos (9U)
5371#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5372#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5373#define CAN_F13R2_FB10_Pos (10U)
5374#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5375#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5376#define CAN_F13R2_FB11_Pos (11U)
5377#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5378#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5379#define CAN_F13R2_FB12_Pos (12U)
5380#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5381#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5382#define CAN_F13R2_FB13_Pos (13U)
5383#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5384#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5385#define CAN_F13R2_FB14_Pos (14U)
5386#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5387#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5388#define CAN_F13R2_FB15_Pos (15U)
5389#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5390#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5391#define CAN_F13R2_FB16_Pos (16U)
5392#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5393#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5394#define CAN_F13R2_FB17_Pos (17U)
5395#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5396#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5397#define CAN_F13R2_FB18_Pos (18U)
5398#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5399#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5400#define CAN_F13R2_FB19_Pos (19U)
5401#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5402#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5403#define CAN_F13R2_FB20_Pos (20U)
5404#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5405#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5406#define CAN_F13R2_FB21_Pos (21U)
5407#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5408#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5409#define CAN_F13R2_FB22_Pos (22U)
5410#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5411#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5412#define CAN_F13R2_FB23_Pos (23U)
5413#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5414#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5415#define CAN_F13R2_FB24_Pos (24U)
5416#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5417#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5418#define CAN_F13R2_FB25_Pos (25U)
5419#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5420#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5421#define CAN_F13R2_FB26_Pos (26U)
5422#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5423#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5424#define CAN_F13R2_FB27_Pos (27U)
5425#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5426#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5427#define CAN_F13R2_FB28_Pos (28U)
5428#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5429#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5430#define CAN_F13R2_FB29_Pos (29U)
5431#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5432#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5433#define CAN_F13R2_FB30_Pos (30U)
5434#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5435#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5436#define CAN_F13R2_FB31_Pos (31U)
5437#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5438#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5440/******************************************************************************/
5441/* */
5442/* HDMI-CEC (CEC) */
5443/* */
5444/******************************************************************************/
5445
5446/******************* Bit definition for CEC_CR register *********************/
5447#define CEC_CR_CECEN_Pos (0U)
5448#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos)
5449#define CEC_CR_CECEN CEC_CR_CECEN_Msk
5450#define CEC_CR_TXSOM_Pos (1U)
5451#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos)
5452#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk
5453#define CEC_CR_TXEOM_Pos (2U)
5454#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos)
5455#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk
5457/******************* Bit definition for CEC_CFGR register *******************/
5458#define CEC_CFGR_SFT_Pos (0U)
5459#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos)
5460#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk
5461#define CEC_CFGR_RXTOL_Pos (3U)
5462#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos)
5463#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk
5464#define CEC_CFGR_BRESTP_Pos (4U)
5465#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos)
5466#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk
5467#define CEC_CFGR_BREGEN_Pos (5U)
5468#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos)
5469#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk
5470#define CEC_CFGR_LBPEGEN_Pos (6U)
5471#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos)
5472#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk
5473#define CEC_CFGR_BRDNOGEN_Pos (7U)
5474#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
5475#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk
5476#define CEC_CFGR_SFTOPT_Pos (8U)
5477#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos)
5478#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk
5479#define CEC_CFGR_OAR_Pos (16U)
5480#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos)
5481#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk
5482#define CEC_CFGR_LSTN_Pos (31U)
5483#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos)
5484#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk
5486/******************* Bit definition for CEC_TXDR register *******************/
5487#define CEC_TXDR_TXD_Pos (0U)
5488#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos)
5489#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk
5491/******************* Bit definition for CEC_RXDR register *******************/
5492#define CEC_RXDR_RXD_Pos (0U)
5493#define CEC_RXDR_RXD_Msk (0xFFU << CEC_RXDR_RXD_Pos)
5494#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk
5496/******************* Bit definition for CEC_ISR register ********************/
5497#define CEC_ISR_RXBR_Pos (0U)
5498#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos)
5499#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk
5500#define CEC_ISR_RXEND_Pos (1U)
5501#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos)
5502#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk
5503#define CEC_ISR_RXOVR_Pos (2U)
5504#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
5505#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk
5506#define CEC_ISR_BRE_Pos (3U)
5507#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos)
5508#define CEC_ISR_BRE CEC_ISR_BRE_Msk
5509#define CEC_ISR_SBPE_Pos (4U)
5510#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos)
5511#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk
5512#define CEC_ISR_LBPE_Pos (5U)
5513#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos)
5514#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk
5515#define CEC_ISR_RXACKE_Pos (6U)
5516#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos)
5517#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk
5518#define CEC_ISR_ARBLST_Pos (7U)
5519#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos)
5520#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk
5521#define CEC_ISR_TXBR_Pos (8U)
5522#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos)
5523#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk
5524#define CEC_ISR_TXEND_Pos (9U)
5525#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos)
5526#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk
5527#define CEC_ISR_TXUDR_Pos (10U)
5528#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos)
5529#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk
5530#define CEC_ISR_TXERR_Pos (11U)
5531#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos)
5532#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk
5533#define CEC_ISR_TXACKE_Pos (12U)
5534#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos)
5535#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk
5537/******************* Bit definition for CEC_IER register ********************/
5538#define CEC_IER_RXBRIE_Pos (0U)
5539#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos)
5540#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk
5541#define CEC_IER_RXENDIE_Pos (1U)
5542#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos)
5543#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk
5544#define CEC_IER_RXOVRIE_Pos (2U)
5545#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos)
5546#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk
5547#define CEC_IER_BREIE_Pos (3U)
5548#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos)
5549#define CEC_IER_BREIE CEC_IER_BREIE_Msk
5550#define CEC_IER_SBPEIE_Pos (4U)
5551#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos)
5552#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk
5553#define CEC_IER_LBPEIE_Pos (5U)
5554#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos)
5555#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk
5556#define CEC_IER_RXACKEIE_Pos (6U)
5557#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos)
5558#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk
5559#define CEC_IER_ARBLSTIE_Pos (7U)
5560#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos)
5561#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk
5562#define CEC_IER_TXBRIE_Pos (8U)
5563#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos)
5564#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk
5565#define CEC_IER_TXENDIE_Pos (9U)
5566#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos)
5567#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk
5568#define CEC_IER_TXUDRIE_Pos (10U)
5569#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos)
5570#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk
5571#define CEC_IER_TXERRIE_Pos (11U)
5572#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos)
5573#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk
5574#define CEC_IER_TXACKEIE_Pos (12U)
5575#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos)
5576#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk
5578/******************************************************************************/
5579/* */
5580/* CRC calculation unit */
5581/* */
5582/******************************************************************************/
5583/******************* Bit definition for CRC_DR register *********************/
5584#define CRC_DR_DR_Pos (0U)
5585#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5586#define CRC_DR_DR CRC_DR_DR_Msk
5588/******************* Bit definition for CRC_IDR register ********************/
5589#define CRC_IDR_IDR_Pos (0U)
5590#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5591#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5593/******************** Bit definition for CRC_CR register ********************/
5594#define CRC_CR_RESET_Pos (0U)
5595#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5596#define CRC_CR_RESET CRC_CR_RESET_Msk
5597#define CRC_CR_POLYSIZE_Pos (3U)
5598#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5599#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5600#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5601#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5602#define CRC_CR_REV_IN_Pos (5U)
5603#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5604#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5605#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5606#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5607#define CRC_CR_REV_OUT_Pos (7U)
5608#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5609#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5611/******************* Bit definition for CRC_INIT register *******************/
5612#define CRC_INIT_INIT_Pos (0U)
5613#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5614#define CRC_INIT_INIT CRC_INIT_INIT_Msk
5616/******************* Bit definition for CRC_POL register ********************/
5617#define CRC_POL_POL_Pos (0U)
5618#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5619#define CRC_POL_POL CRC_POL_POL_Msk
5622/******************************************************************************/
5623/* */
5624/* Digital to Analog Converter */
5625/* */
5626/******************************************************************************/
5627/******************** Bit definition for DAC_CR register ********************/
5628#define DAC_CR_EN1_Pos (0U)
5629#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5630#define DAC_CR_EN1 DAC_CR_EN1_Msk
5631#define DAC_CR_BOFF1_Pos (1U)
5632#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5633#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5634#define DAC_CR_TEN1_Pos (2U)
5635#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5636#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5637#define DAC_CR_TSEL1_Pos (3U)
5638#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5639#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5640#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5641#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5642#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5643#define DAC_CR_WAVE1_Pos (6U)
5644#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5645#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5646#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5647#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5648#define DAC_CR_MAMP1_Pos (8U)
5649#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5650#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5651#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5652#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5653#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5654#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5655#define DAC_CR_DMAEN1_Pos (12U)
5656#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5657#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5658#define DAC_CR_DMAUDRIE1_Pos (13U)
5659#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5660#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5661#define DAC_CR_EN2_Pos (16U)
5662#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5663#define DAC_CR_EN2 DAC_CR_EN2_Msk
5664#define DAC_CR_BOFF2_Pos (17U)
5665#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5666#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5667#define DAC_CR_TEN2_Pos (18U)
5668#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5669#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5670#define DAC_CR_TSEL2_Pos (19U)
5671#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5672#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5673#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5674#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5675#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5676#define DAC_CR_WAVE2_Pos (22U)
5677#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5678#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5679#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5680#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5681#define DAC_CR_MAMP2_Pos (24U)
5682#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5683#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5684#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5685#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5686#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5687#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5688#define DAC_CR_DMAEN2_Pos (28U)
5689#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5690#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5691#define DAC_CR_DMAUDRIE2_Pos (29U)
5692#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5693#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5695/***************** Bit definition for DAC_SWTRIGR register ******************/
5696#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5697#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5698#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5699#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5700#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5701#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5703/***************** Bit definition for DAC_DHR12R1 register ******************/
5704#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5705#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5706#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5708/***************** Bit definition for DAC_DHR12L1 register ******************/
5709#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5710#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5711#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5713/****************** Bit definition for DAC_DHR8R1 register ******************/
5714#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5715#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5716#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5718/***************** Bit definition for DAC_DHR12R2 register ******************/
5719#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5720#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5721#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5723/***************** Bit definition for DAC_DHR12L2 register ******************/
5724#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5725#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5726#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5728/****************** Bit definition for DAC_DHR8R2 register ******************/
5729#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5730#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5731#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5733/***************** Bit definition for DAC_DHR12RD register ******************/
5734#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5735#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5736#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5737#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5738#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5739#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5741/***************** Bit definition for DAC_DHR12LD register ******************/
5742#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5743#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5744#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5745#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5746#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5747#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5749/****************** Bit definition for DAC_DHR8RD register ******************/
5750#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5751#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5752#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5753#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5754#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5755#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5757/******************* Bit definition for DAC_DOR1 register *******************/
5758#define DAC_DOR1_DACC1DOR_Pos (0U)
5759#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5760#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5762/******************* Bit definition for DAC_DOR2 register *******************/
5763#define DAC_DOR2_DACC2DOR_Pos (0U)
5764#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5765#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5767/******************** Bit definition for DAC_SR register ********************/
5768#define DAC_SR_DMAUDR1_Pos (13U)
5769#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5770#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5771#define DAC_SR_DMAUDR2_Pos (29U)
5772#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5773#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5776/******************************************************************************/
5777/* */
5778/* Debug MCU */
5779/* */
5780/******************************************************************************/
5781
5782/******************************************************************************/
5783/* */
5784/* DCMI */
5785/* */
5786/******************************************************************************/
5787/******************** Bits definition for DCMI_CR register ******************/
5788#define DCMI_CR_CAPTURE_Pos (0U)
5789#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
5790#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5791#define DCMI_CR_CM_Pos (1U)
5792#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
5793#define DCMI_CR_CM DCMI_CR_CM_Msk
5794#define DCMI_CR_CROP_Pos (2U)
5795#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
5796#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5797#define DCMI_CR_JPEG_Pos (3U)
5798#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
5799#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5800#define DCMI_CR_ESS_Pos (4U)
5801#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
5802#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5803#define DCMI_CR_PCKPOL_Pos (5U)
5804#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
5805#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5806#define DCMI_CR_HSPOL_Pos (6U)
5807#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
5808#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5809#define DCMI_CR_VSPOL_Pos (7U)
5810#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
5811#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5812#define DCMI_CR_FCRC_0 0x00000100U
5813#define DCMI_CR_FCRC_1 0x00000200U
5814#define DCMI_CR_EDM_0 0x00000400U
5815#define DCMI_CR_EDM_1 0x00000800U
5816#define DCMI_CR_CRE_Pos (12U)
5817#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
5818#define DCMI_CR_CRE DCMI_CR_CRE_Msk
5819#define DCMI_CR_ENABLE_Pos (14U)
5820#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
5821#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5822#define DCMI_CR_BSM_Pos (16U)
5823#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos)
5824#define DCMI_CR_BSM DCMI_CR_BSM_Msk
5825#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos)
5826#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos)
5827#define DCMI_CR_OEBS_Pos (18U)
5828#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
5829#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
5830#define DCMI_CR_LSM_Pos (19U)
5831#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
5832#define DCMI_CR_LSM DCMI_CR_LSM_Msk
5833#define DCMI_CR_OELS_Pos (20U)
5834#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
5835#define DCMI_CR_OELS DCMI_CR_OELS_Msk
5836
5837/******************** Bits definition for DCMI_SR register ******************/
5838#define DCMI_SR_HSYNC_Pos (0U)
5839#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
5840#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5841#define DCMI_SR_VSYNC_Pos (1U)
5842#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
5843#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5844#define DCMI_SR_FNE_Pos (2U)
5845#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
5846#define DCMI_SR_FNE DCMI_SR_FNE_Msk
5847
5848/******************** Bits definition for DCMI_RIS register ****************/
5849#define DCMI_RIS_FRAME_RIS_Pos (0U)
5850#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
5851#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5852#define DCMI_RIS_OVR_RIS_Pos (1U)
5853#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
5854#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5855#define DCMI_RIS_ERR_RIS_Pos (2U)
5856#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
5857#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5858#define DCMI_RIS_VSYNC_RIS_Pos (3U)
5859#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
5860#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5861#define DCMI_RIS_LINE_RIS_Pos (4U)
5862#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
5863#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5864
5865/* Legacy defines */
5866#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5867#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5868#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5869#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5870#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5871
5872/******************** Bits definition for DCMI_IER register *****************/
5873#define DCMI_IER_FRAME_IE_Pos (0U)
5874#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
5875#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5876#define DCMI_IER_OVR_IE_Pos (1U)
5877#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
5878#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5879#define DCMI_IER_ERR_IE_Pos (2U)
5880#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
5881#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5882#define DCMI_IER_VSYNC_IE_Pos (3U)
5883#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
5884#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5885#define DCMI_IER_LINE_IE_Pos (4U)
5886#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
5887#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5888
5889/* Legacy define */
5890#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5891
5892/******************** Bits definition for DCMI_MIS register *****************/
5893#define DCMI_MIS_FRAME_MIS_Pos (0U)
5894#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
5895#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5896#define DCMI_MIS_OVR_MIS_Pos (1U)
5897#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
5898#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5899#define DCMI_MIS_ERR_MIS_Pos (2U)
5900#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
5901#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5902#define DCMI_MIS_VSYNC_MIS_Pos (3U)
5903#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
5904#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5905#define DCMI_MIS_LINE_MIS_Pos (4U)
5906#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
5907#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5908
5909/* Legacy defines */
5910#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5911#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5912#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5913#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5914#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5915
5916/******************** Bits definition for DCMI_ICR register *****************/
5917#define DCMI_ICR_FRAME_ISC_Pos (0U)
5918#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
5919#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5920#define DCMI_ICR_OVR_ISC_Pos (1U)
5921#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
5922#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5923#define DCMI_ICR_ERR_ISC_Pos (2U)
5924#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
5925#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5926#define DCMI_ICR_VSYNC_ISC_Pos (3U)
5927#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
5928#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5929#define DCMI_ICR_LINE_ISC_Pos (4U)
5930#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
5931#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5932
5933/* Legacy defines */
5934#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5935
5936/******************** Bits definition for DCMI_ESCR register ******************/
5937#define DCMI_ESCR_FSC_Pos (0U)
5938#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
5939#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5940#define DCMI_ESCR_LSC_Pos (8U)
5941#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
5942#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5943#define DCMI_ESCR_LEC_Pos (16U)
5944#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
5945#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5946#define DCMI_ESCR_FEC_Pos (24U)
5947#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
5948#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5949
5950/******************** Bits definition for DCMI_ESUR register ******************/
5951#define DCMI_ESUR_FSU_Pos (0U)
5952#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
5953#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5954#define DCMI_ESUR_LSU_Pos (8U)
5955#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
5956#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5957#define DCMI_ESUR_LEU_Pos (16U)
5958#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
5959#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5960#define DCMI_ESUR_FEU_Pos (24U)
5961#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
5962#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5963
5964/******************** Bits definition for DCMI_CWSTRT register ******************/
5965#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5966#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
5967#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5968#define DCMI_CWSTRT_VST_Pos (16U)
5969#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
5970#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5971
5972/******************** Bits definition for DCMI_CWSIZE register ******************/
5973#define DCMI_CWSIZE_CAPCNT_Pos (0U)
5974#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
5975#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5976#define DCMI_CWSIZE_VLINE_Pos (16U)
5977#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
5978#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5979
5980/******************** Bits definition for DCMI_DR register ******************/
5981#define DCMI_DR_BYTE0_Pos (0U)
5982#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
5983#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5984#define DCMI_DR_BYTE1_Pos (8U)
5985#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
5986#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5987#define DCMI_DR_BYTE2_Pos (16U)
5988#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
5989#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5990#define DCMI_DR_BYTE3_Pos (24U)
5991#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
5992#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5993
5994/******************************************************************************/
5995/* */
5996/* DMA Controller */
5997/* */
5998/******************************************************************************/
5999/******************** Bits definition for DMA_SxCR register *****************/
6000#define DMA_SxCR_CHSEL_Pos (25U)
6001#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
6002#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6003#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
6004#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
6005#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
6006#define DMA_SxCR_MBURST_Pos (23U)
6007#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
6008#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6009#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
6010#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
6011#define DMA_SxCR_PBURST_Pos (21U)
6012#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
6013#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6014#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
6015#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
6016#define DMA_SxCR_CT_Pos (19U)
6017#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
6018#define DMA_SxCR_CT DMA_SxCR_CT_Msk
6019#define DMA_SxCR_DBM_Pos (18U)
6020#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
6021#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6022#define DMA_SxCR_PL_Pos (16U)
6023#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
6024#define DMA_SxCR_PL DMA_SxCR_PL_Msk
6025#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
6026#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
6027#define DMA_SxCR_PINCOS_Pos (15U)
6028#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
6029#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6030#define DMA_SxCR_MSIZE_Pos (13U)
6031#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
6032#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6033#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
6034#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
6035#define DMA_SxCR_PSIZE_Pos (11U)
6036#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
6037#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6038#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
6039#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
6040#define DMA_SxCR_MINC_Pos (10U)
6041#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
6042#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6043#define DMA_SxCR_PINC_Pos (9U)
6044#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
6045#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6046#define DMA_SxCR_CIRC_Pos (8U)
6047#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
6048#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6049#define DMA_SxCR_DIR_Pos (6U)
6050#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
6051#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6052#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
6053#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
6054#define DMA_SxCR_PFCTRL_Pos (5U)
6055#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
6056#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6057#define DMA_SxCR_TCIE_Pos (4U)
6058#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
6059#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6060#define DMA_SxCR_HTIE_Pos (3U)
6061#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
6062#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6063#define DMA_SxCR_TEIE_Pos (2U)
6064#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
6065#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6066#define DMA_SxCR_DMEIE_Pos (1U)
6067#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
6068#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6069#define DMA_SxCR_EN_Pos (0U)
6070#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6071#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6072
6073/******************** Bits definition for DMA_SxCNDTR register **************/
6074#define DMA_SxNDT_Pos (0U)
6075#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6076#define DMA_SxNDT DMA_SxNDT_Msk
6077#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6078#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6079#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6080#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6081#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6082#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6083#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6084#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6085#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6086#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6087#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6088#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6089#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6090#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6091#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6092#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6094/******************** Bits definition for DMA_SxFCR register ****************/
6095#define DMA_SxFCR_FEIE_Pos (7U)
6096#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6097#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6098#define DMA_SxFCR_FS_Pos (3U)
6099#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6100#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6101#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6102#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6103#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6104#define DMA_SxFCR_DMDIS_Pos (2U)
6105#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6106#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6107#define DMA_SxFCR_FTH_Pos (0U)
6108#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6109#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6110#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6111#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6113/******************** Bits definition for DMA_LISR register *****************/
6114#define DMA_LISR_TCIF3_Pos (27U)
6115#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6116#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6117#define DMA_LISR_HTIF3_Pos (26U)
6118#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6119#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6120#define DMA_LISR_TEIF3_Pos (25U)
6121#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6122#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6123#define DMA_LISR_DMEIF3_Pos (24U)
6124#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6125#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6126#define DMA_LISR_FEIF3_Pos (22U)
6127#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
6128#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6129#define DMA_LISR_TCIF2_Pos (21U)
6130#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
6131#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6132#define DMA_LISR_HTIF2_Pos (20U)
6133#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
6134#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6135#define DMA_LISR_TEIF2_Pos (19U)
6136#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
6137#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6138#define DMA_LISR_DMEIF2_Pos (18U)
6139#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
6140#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6141#define DMA_LISR_FEIF2_Pos (16U)
6142#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
6143#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6144#define DMA_LISR_TCIF1_Pos (11U)
6145#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
6146#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6147#define DMA_LISR_HTIF1_Pos (10U)
6148#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
6149#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6150#define DMA_LISR_TEIF1_Pos (9U)
6151#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
6152#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6153#define DMA_LISR_DMEIF1_Pos (8U)
6154#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
6155#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6156#define DMA_LISR_FEIF1_Pos (6U)
6157#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
6158#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6159#define DMA_LISR_TCIF0_Pos (5U)
6160#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
6161#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6162#define DMA_LISR_HTIF0_Pos (4U)
6163#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
6164#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6165#define DMA_LISR_TEIF0_Pos (3U)
6166#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
6167#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6168#define DMA_LISR_DMEIF0_Pos (2U)
6169#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
6170#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6171#define DMA_LISR_FEIF0_Pos (0U)
6172#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
6173#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6174
6175/******************** Bits definition for DMA_HISR register *****************/
6176#define DMA_HISR_TCIF7_Pos (27U)
6177#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
6178#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6179#define DMA_HISR_HTIF7_Pos (26U)
6180#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
6181#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6182#define DMA_HISR_TEIF7_Pos (25U)
6183#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6184#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6185#define DMA_HISR_DMEIF7_Pos (24U)
6186#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6187#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6188#define DMA_HISR_FEIF7_Pos (22U)
6189#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6190#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6191#define DMA_HISR_TCIF6_Pos (21U)
6192#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6193#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6194#define DMA_HISR_HTIF6_Pos (20U)
6195#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6196#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6197#define DMA_HISR_TEIF6_Pos (19U)
6198#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6199#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6200#define DMA_HISR_DMEIF6_Pos (18U)
6201#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6202#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6203#define DMA_HISR_FEIF6_Pos (16U)
6204#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6205#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6206#define DMA_HISR_TCIF5_Pos (11U)
6207#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6208#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6209#define DMA_HISR_HTIF5_Pos (10U)
6210#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6211#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6212#define DMA_HISR_TEIF5_Pos (9U)
6213#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6214#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6215#define DMA_HISR_DMEIF5_Pos (8U)
6216#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6217#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6218#define DMA_HISR_FEIF5_Pos (6U)
6219#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6220#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6221#define DMA_HISR_TCIF4_Pos (5U)
6222#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6223#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6224#define DMA_HISR_HTIF4_Pos (4U)
6225#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6226#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6227#define DMA_HISR_TEIF4_Pos (3U)
6228#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6229#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6230#define DMA_HISR_DMEIF4_Pos (2U)
6231#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6232#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6233#define DMA_HISR_FEIF4_Pos (0U)
6234#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6235#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6236
6237/******************** Bits definition for DMA_LIFCR register ****************/
6238#define DMA_LIFCR_CTCIF3_Pos (27U)
6239#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6240#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6241#define DMA_LIFCR_CHTIF3_Pos (26U)
6242#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6243#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6244#define DMA_LIFCR_CTEIF3_Pos (25U)
6245#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6246#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6247#define DMA_LIFCR_CDMEIF3_Pos (24U)
6248#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6249#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6250#define DMA_LIFCR_CFEIF3_Pos (22U)
6251#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6252#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6253#define DMA_LIFCR_CTCIF2_Pos (21U)
6254#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6255#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6256#define DMA_LIFCR_CHTIF2_Pos (20U)
6257#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6258#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6259#define DMA_LIFCR_CTEIF2_Pos (19U)
6260#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6261#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6262#define DMA_LIFCR_CDMEIF2_Pos (18U)
6263#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6264#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6265#define DMA_LIFCR_CFEIF2_Pos (16U)
6266#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6267#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6268#define DMA_LIFCR_CTCIF1_Pos (11U)
6269#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6270#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6271#define DMA_LIFCR_CHTIF1_Pos (10U)
6272#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6273#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6274#define DMA_LIFCR_CTEIF1_Pos (9U)
6275#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6276#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6277#define DMA_LIFCR_CDMEIF1_Pos (8U)
6278#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6279#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6280#define DMA_LIFCR_CFEIF1_Pos (6U)
6281#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6282#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6283#define DMA_LIFCR_CTCIF0_Pos (5U)
6284#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6285#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6286#define DMA_LIFCR_CHTIF0_Pos (4U)
6287#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6288#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6289#define DMA_LIFCR_CTEIF0_Pos (3U)
6290#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6291#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6292#define DMA_LIFCR_CDMEIF0_Pos (2U)
6293#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6294#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6295#define DMA_LIFCR_CFEIF0_Pos (0U)
6296#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6297#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6298
6299/******************** Bits definition for DMA_HIFCR register ****************/
6300#define DMA_HIFCR_CTCIF7_Pos (27U)
6301#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6302#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6303#define DMA_HIFCR_CHTIF7_Pos (26U)
6304#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6305#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6306#define DMA_HIFCR_CTEIF7_Pos (25U)
6307#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6308#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6309#define DMA_HIFCR_CDMEIF7_Pos (24U)
6310#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6311#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6312#define DMA_HIFCR_CFEIF7_Pos (22U)
6313#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6314#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6315#define DMA_HIFCR_CTCIF6_Pos (21U)
6316#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6317#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6318#define DMA_HIFCR_CHTIF6_Pos (20U)
6319#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6320#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6321#define DMA_HIFCR_CTEIF6_Pos (19U)
6322#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6323#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6324#define DMA_HIFCR_CDMEIF6_Pos (18U)
6325#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6326#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6327#define DMA_HIFCR_CFEIF6_Pos (16U)
6328#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6329#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6330#define DMA_HIFCR_CTCIF5_Pos (11U)
6331#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6332#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6333#define DMA_HIFCR_CHTIF5_Pos (10U)
6334#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6335#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6336#define DMA_HIFCR_CTEIF5_Pos (9U)
6337#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6338#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6339#define DMA_HIFCR_CDMEIF5_Pos (8U)
6340#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6341#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6342#define DMA_HIFCR_CFEIF5_Pos (6U)
6343#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6344#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6345#define DMA_HIFCR_CTCIF4_Pos (5U)
6346#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6347#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6348#define DMA_HIFCR_CHTIF4_Pos (4U)
6349#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6350#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6351#define DMA_HIFCR_CTEIF4_Pos (3U)
6352#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6353#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6354#define DMA_HIFCR_CDMEIF4_Pos (2U)
6355#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6356#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6357#define DMA_HIFCR_CFEIF4_Pos (0U)
6358#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6359#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6360
6361/****************** Bit definition for DMA_SxPAR register ********************/
6362#define DMA_SxPAR_PA_Pos (0U)
6363#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6364#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6366/****************** Bit definition for DMA_SxM0AR register ********************/
6367#define DMA_SxM0AR_M0A_Pos (0U)
6368#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6369#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6371/****************** Bit definition for DMA_SxM1AR register ********************/
6372#define DMA_SxM1AR_M1A_Pos (0U)
6373#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6374#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6376/******************************************************************************/
6377/* */
6378/* AHB Master DMA2D Controller (DMA2D) */
6379/* */
6380/******************************************************************************/
6381/******************** Bit definition for DMA2D_CR register ******************/
6382
6383#define DMA2D_CR_START_Pos (0U)
6384#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
6385#define DMA2D_CR_START DMA2D_CR_START_Msk
6386#define DMA2D_CR_SUSP_Pos (1U)
6387#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
6388#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
6389#define DMA2D_CR_ABORT_Pos (2U)
6390#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
6391#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
6392#define DMA2D_CR_TEIE_Pos (8U)
6393#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
6394#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
6395#define DMA2D_CR_TCIE_Pos (9U)
6396#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
6397#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
6398#define DMA2D_CR_TWIE_Pos (10U)
6399#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
6400#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
6401#define DMA2D_CR_CAEIE_Pos (11U)
6402#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
6403#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
6404#define DMA2D_CR_CTCIE_Pos (12U)
6405#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
6406#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
6407#define DMA2D_CR_CEIE_Pos (13U)
6408#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
6409#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
6410#define DMA2D_CR_MODE_Pos (16U)
6411#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos)
6412#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
6413#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
6414#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
6416/******************** Bit definition for DMA2D_ISR register *****************/
6417
6418#define DMA2D_ISR_TEIF_Pos (0U)
6419#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
6420#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
6421#define DMA2D_ISR_TCIF_Pos (1U)
6422#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
6423#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
6424#define DMA2D_ISR_TWIF_Pos (2U)
6425#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
6426#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
6427#define DMA2D_ISR_CAEIF_Pos (3U)
6428#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
6429#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
6430#define DMA2D_ISR_CTCIF_Pos (4U)
6431#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
6432#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
6433#define DMA2D_ISR_CEIF_Pos (5U)
6434#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
6435#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
6437/******************** Bit definition for DMA2D_IFCR register ****************/
6438
6439#define DMA2D_IFCR_CTEIF_Pos (0U)
6440#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
6441#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
6442#define DMA2D_IFCR_CTCIF_Pos (1U)
6443#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
6444#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
6445#define DMA2D_IFCR_CTWIF_Pos (2U)
6446#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
6447#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
6448#define DMA2D_IFCR_CAECIF_Pos (3U)
6449#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
6450#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
6451#define DMA2D_IFCR_CCTCIF_Pos (4U)
6452#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
6453#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
6454#define DMA2D_IFCR_CCEIF_Pos (5U)
6455#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
6456#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
6458/* Legacy defines */
6459#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
6460#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
6461#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
6462#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
6463#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
6464#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
6466/******************** Bit definition for DMA2D_FGMAR register ***************/
6467
6468#define DMA2D_FGMAR_MA_Pos (0U)
6469#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
6470#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
6472/******************** Bit definition for DMA2D_FGOR register ****************/
6473
6474#define DMA2D_FGOR_LO_Pos (0U)
6475#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos)
6476#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
6478/******************** Bit definition for DMA2D_BGMAR register ***************/
6479
6480#define DMA2D_BGMAR_MA_Pos (0U)
6481#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
6482#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
6484/******************** Bit definition for DMA2D_BGOR register ****************/
6485
6486#define DMA2D_BGOR_LO_Pos (0U)
6487#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos)
6488#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
6490/******************** Bit definition for DMA2D_FGPFCCR register *************/
6491
6492#define DMA2D_FGPFCCR_CM_Pos (0U)
6493#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
6494#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
6495#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
6496#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
6497#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
6498#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
6499#define DMA2D_FGPFCCR_CCM_Pos (4U)
6500#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
6501#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
6502#define DMA2D_FGPFCCR_START_Pos (5U)
6503#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
6504#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
6505#define DMA2D_FGPFCCR_CS_Pos (8U)
6506#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
6507#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
6508#define DMA2D_FGPFCCR_AM_Pos (16U)
6509#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
6510#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
6511#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
6512#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
6513#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6514#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
6515#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
6517/******************** Bit definition for DMA2D_FGCOLR register **************/
6518
6519#define DMA2D_FGCOLR_BLUE_Pos (0U)
6520#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
6521#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
6522#define DMA2D_FGCOLR_GREEN_Pos (8U)
6523#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
6524#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
6525#define DMA2D_FGCOLR_RED_Pos (16U)
6526#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
6527#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
6529/******************** Bit definition for DMA2D_BGPFCCR register *************/
6530
6531#define DMA2D_BGPFCCR_CM_Pos (0U)
6532#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
6533#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
6534#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
6535#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
6536#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
6537#define DMA2D_BGPFCCR_CM_3 0x00000008U
6538#define DMA2D_BGPFCCR_CCM_Pos (4U)
6539#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
6540#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
6541#define DMA2D_BGPFCCR_START_Pos (5U)
6542#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
6543#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
6544#define DMA2D_BGPFCCR_CS_Pos (8U)
6545#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
6546#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
6547#define DMA2D_BGPFCCR_AM_Pos (16U)
6548#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
6549#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
6550#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
6551#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
6552#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6553#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
6554#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
6556/******************** Bit definition for DMA2D_BGCOLR register **************/
6557
6558#define DMA2D_BGCOLR_BLUE_Pos (0U)
6559#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
6560#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
6561#define DMA2D_BGCOLR_GREEN_Pos (8U)
6562#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
6563#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
6564#define DMA2D_BGCOLR_RED_Pos (16U)
6565#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
6566#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
6568/******************** Bit definition for DMA2D_FGCMAR register **************/
6569
6570#define DMA2D_FGCMAR_MA_Pos (0U)
6571#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
6572#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
6574/******************** Bit definition for DMA2D_BGCMAR register **************/
6575
6576#define DMA2D_BGCMAR_MA_Pos (0U)
6577#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
6578#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
6580/******************** Bit definition for DMA2D_OPFCCR register **************/
6581
6582#define DMA2D_OPFCCR_CM_Pos (0U)
6583#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
6584#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
6585#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
6586#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
6587#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
6589/******************** Bit definition for DMA2D_OCOLR register ***************/
6590
6593#define DMA2D_OCOLR_BLUE_1 0x000000FFU
6594#define DMA2D_OCOLR_GREEN_1 0x0000FF00U
6595#define DMA2D_OCOLR_RED_1 0x00FF0000U
6596#define DMA2D_OCOLR_ALPHA_1 0xFF000000U
6599#define DMA2D_OCOLR_BLUE_2 0x0000001FU
6600#define DMA2D_OCOLR_GREEN_2 0x000007E0U
6601#define DMA2D_OCOLR_RED_2 0x0000F800U
6604#define DMA2D_OCOLR_BLUE_3 0x0000001FU
6605#define DMA2D_OCOLR_GREEN_3 0x000003E0U
6606#define DMA2D_OCOLR_RED_3 0x00007C00U
6607#define DMA2D_OCOLR_ALPHA_3 0x00008000U
6610#define DMA2D_OCOLR_BLUE_4 0x0000000FU
6611#define DMA2D_OCOLR_GREEN_4 0x000000F0U
6612#define DMA2D_OCOLR_RED_4 0x00000F00U
6613#define DMA2D_OCOLR_ALPHA_4 0x0000F000U
6615/******************** Bit definition for DMA2D_OMAR register ****************/
6616
6617#define DMA2D_OMAR_MA_Pos (0U)
6618#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
6619#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
6621/******************** Bit definition for DMA2D_OOR register *****************/
6622
6623#define DMA2D_OOR_LO_Pos (0U)
6624#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos)
6625#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
6627/******************** Bit definition for DMA2D_NLR register *****************/
6628
6629#define DMA2D_NLR_NL_Pos (0U)
6630#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
6631#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
6632#define DMA2D_NLR_PL_Pos (16U)
6633#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
6634#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
6636/******************** Bit definition for DMA2D_LWR register *****************/
6637
6638#define DMA2D_LWR_LW_Pos (0U)
6639#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
6640#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
6642/******************** Bit definition for DMA2D_AMTCR register ***************/
6643
6644#define DMA2D_AMTCR_EN_Pos (0U)
6645#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
6646#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
6647#define DMA2D_AMTCR_DT_Pos (8U)
6648#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
6649#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
6652/******************** Bit definition for DMA2D_FGCLUT register **************/
6653
6654/******************** Bit definition for DMA2D_BGCLUT register **************/
6655
6656/******************************************************************************/
6657/* */
6658/* External Interrupt/Event Controller */
6659/* */
6660/******************************************************************************/
6661/******************* Bit definition for EXTI_IMR register *******************/
6662#define EXTI_IMR_MR0_Pos (0U)
6663#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6664#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6665#define EXTI_IMR_MR1_Pos (1U)
6666#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6667#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6668#define EXTI_IMR_MR2_Pos (2U)
6669#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6670#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6671#define EXTI_IMR_MR3_Pos (3U)
6672#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6673#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6674#define EXTI_IMR_MR4_Pos (4U)
6675#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6676#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6677#define EXTI_IMR_MR5_Pos (5U)
6678#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6679#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6680#define EXTI_IMR_MR6_Pos (6U)
6681#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6682#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6683#define EXTI_IMR_MR7_Pos (7U)
6684#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6685#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6686#define EXTI_IMR_MR8_Pos (8U)
6687#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6688#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6689#define EXTI_IMR_MR9_Pos (9U)
6690#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6691#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6692#define EXTI_IMR_MR10_Pos (10U)
6693#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6694#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6695#define EXTI_IMR_MR11_Pos (11U)
6696#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6697#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6698#define EXTI_IMR_MR12_Pos (12U)
6699#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6700#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6701#define EXTI_IMR_MR13_Pos (13U)
6702#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6703#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6704#define EXTI_IMR_MR14_Pos (14U)
6705#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6706#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6707#define EXTI_IMR_MR15_Pos (15U)
6708#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6709#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6710#define EXTI_IMR_MR16_Pos (16U)
6711#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6712#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6713#define EXTI_IMR_MR17_Pos (17U)
6714#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6715#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6716#define EXTI_IMR_MR18_Pos (18U)
6717#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6718#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6719#define EXTI_IMR_MR19_Pos (19U)
6720#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6721#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6722#define EXTI_IMR_MR20_Pos (20U)
6723#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6724#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6725#define EXTI_IMR_MR21_Pos (21U)
6726#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6727#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6728#define EXTI_IMR_MR22_Pos (22U)
6729#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6730#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6731#define EXTI_IMR_MR23_Pos (23U)
6732#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos)
6733#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk
6735/* Reference Defines */
6736#define EXTI_IMR_IM0 EXTI_IMR_MR0
6737#define EXTI_IMR_IM1 EXTI_IMR_MR1
6738#define EXTI_IMR_IM2 EXTI_IMR_MR2
6739#define EXTI_IMR_IM3 EXTI_IMR_MR3
6740#define EXTI_IMR_IM4 EXTI_IMR_MR4
6741#define EXTI_IMR_IM5 EXTI_IMR_MR5
6742#define EXTI_IMR_IM6 EXTI_IMR_MR6
6743#define EXTI_IMR_IM7 EXTI_IMR_MR7
6744#define EXTI_IMR_IM8 EXTI_IMR_MR8
6745#define EXTI_IMR_IM9 EXTI_IMR_MR9
6746#define EXTI_IMR_IM10 EXTI_IMR_MR10
6747#define EXTI_IMR_IM11 EXTI_IMR_MR11
6748#define EXTI_IMR_IM12 EXTI_IMR_MR12
6749#define EXTI_IMR_IM13 EXTI_IMR_MR13
6750#define EXTI_IMR_IM14 EXTI_IMR_MR14
6751#define EXTI_IMR_IM15 EXTI_IMR_MR15
6752#define EXTI_IMR_IM16 EXTI_IMR_MR16
6753#define EXTI_IMR_IM17 EXTI_IMR_MR17
6754#define EXTI_IMR_IM18 EXTI_IMR_MR18
6755#define EXTI_IMR_IM19 EXTI_IMR_MR19
6756#define EXTI_IMR_IM20 EXTI_IMR_MR20
6757#define EXTI_IMR_IM21 EXTI_IMR_MR21
6758#define EXTI_IMR_IM22 EXTI_IMR_MR22
6759#define EXTI_IMR_IM23 EXTI_IMR_MR23
6760
6761#define EXTI_IMR_IM_Pos (0U)
6762#define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos)
6763#define EXTI_IMR_IM EXTI_IMR_IM_Msk
6765/******************* Bit definition for EXTI_EMR register *******************/
6766#define EXTI_EMR_MR0_Pos (0U)
6767#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6768#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6769#define EXTI_EMR_MR1_Pos (1U)
6770#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6771#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6772#define EXTI_EMR_MR2_Pos (2U)
6773#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6774#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6775#define EXTI_EMR_MR3_Pos (3U)
6776#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6777#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6778#define EXTI_EMR_MR4_Pos (4U)
6779#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6780#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6781#define EXTI_EMR_MR5_Pos (5U)
6782#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6783#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6784#define EXTI_EMR_MR6_Pos (6U)
6785#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6786#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6787#define EXTI_EMR_MR7_Pos (7U)
6788#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6789#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6790#define EXTI_EMR_MR8_Pos (8U)
6791#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6792#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6793#define EXTI_EMR_MR9_Pos (9U)
6794#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6795#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6796#define EXTI_EMR_MR10_Pos (10U)
6797#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6798#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6799#define EXTI_EMR_MR11_Pos (11U)
6800#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6801#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6802#define EXTI_EMR_MR12_Pos (12U)
6803#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6804#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6805#define EXTI_EMR_MR13_Pos (13U)
6806#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6807#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6808#define EXTI_EMR_MR14_Pos (14U)
6809#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6810#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6811#define EXTI_EMR_MR15_Pos (15U)
6812#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6813#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6814#define EXTI_EMR_MR16_Pos (16U)
6815#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6816#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6817#define EXTI_EMR_MR17_Pos (17U)
6818#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6819#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6820#define EXTI_EMR_MR18_Pos (18U)
6821#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6822#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6823#define EXTI_EMR_MR19_Pos (19U)
6824#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6825#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6826#define EXTI_EMR_MR20_Pos (20U)
6827#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6828#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6829#define EXTI_EMR_MR21_Pos (21U)
6830#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6831#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6832#define EXTI_EMR_MR22_Pos (22U)
6833#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6834#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6835#define EXTI_EMR_MR23_Pos (23U)
6836#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos)
6837#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk
6839/* Reference Defines */
6840#define EXTI_EMR_EM0 EXTI_EMR_MR0
6841#define EXTI_EMR_EM1 EXTI_EMR_MR1
6842#define EXTI_EMR_EM2 EXTI_EMR_MR2
6843#define EXTI_EMR_EM3 EXTI_EMR_MR3
6844#define EXTI_EMR_EM4 EXTI_EMR_MR4
6845#define EXTI_EMR_EM5 EXTI_EMR_MR5
6846#define EXTI_EMR_EM6 EXTI_EMR_MR6
6847#define EXTI_EMR_EM7 EXTI_EMR_MR7
6848#define EXTI_EMR_EM8 EXTI_EMR_MR8
6849#define EXTI_EMR_EM9 EXTI_EMR_MR9
6850#define EXTI_EMR_EM10 EXTI_EMR_MR10
6851#define EXTI_EMR_EM11 EXTI_EMR_MR11
6852#define EXTI_EMR_EM12 EXTI_EMR_MR12
6853#define EXTI_EMR_EM13 EXTI_EMR_MR13
6854#define EXTI_EMR_EM14 EXTI_EMR_MR14
6855#define EXTI_EMR_EM15 EXTI_EMR_MR15
6856#define EXTI_EMR_EM16 EXTI_EMR_MR16
6857#define EXTI_EMR_EM17 EXTI_EMR_MR17
6858#define EXTI_EMR_EM18 EXTI_EMR_MR18
6859#define EXTI_EMR_EM19 EXTI_EMR_MR19
6860#define EXTI_EMR_EM20 EXTI_EMR_MR20
6861#define EXTI_EMR_EM21 EXTI_EMR_MR21
6862#define EXTI_EMR_EM22 EXTI_EMR_MR22
6863#define EXTI_EMR_EM23 EXTI_EMR_MR23
6864
6865
6866/****************** Bit definition for EXTI_RTSR register *******************/
6867#define EXTI_RTSR_TR0_Pos (0U)
6868#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6869#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6870#define EXTI_RTSR_TR1_Pos (1U)
6871#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6872#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6873#define EXTI_RTSR_TR2_Pos (2U)
6874#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6875#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6876#define EXTI_RTSR_TR3_Pos (3U)
6877#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6878#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6879#define EXTI_RTSR_TR4_Pos (4U)
6880#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6881#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6882#define EXTI_RTSR_TR5_Pos (5U)
6883#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6884#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6885#define EXTI_RTSR_TR6_Pos (6U)
6886#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6887#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6888#define EXTI_RTSR_TR7_Pos (7U)
6889#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6890#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6891#define EXTI_RTSR_TR8_Pos (8U)
6892#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6893#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6894#define EXTI_RTSR_TR9_Pos (9U)
6895#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6896#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6897#define EXTI_RTSR_TR10_Pos (10U)
6898#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6899#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6900#define EXTI_RTSR_TR11_Pos (11U)
6901#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6902#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6903#define EXTI_RTSR_TR12_Pos (12U)
6904#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6905#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6906#define EXTI_RTSR_TR13_Pos (13U)
6907#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6908#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6909#define EXTI_RTSR_TR14_Pos (14U)
6910#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6911#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6912#define EXTI_RTSR_TR15_Pos (15U)
6913#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6914#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6915#define EXTI_RTSR_TR16_Pos (16U)
6916#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6917#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6918#define EXTI_RTSR_TR17_Pos (17U)
6919#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6920#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6921#define EXTI_RTSR_TR18_Pos (18U)
6922#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6923#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6924#define EXTI_RTSR_TR19_Pos (19U)
6925#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6926#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6927#define EXTI_RTSR_TR20_Pos (20U)
6928#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6929#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6930#define EXTI_RTSR_TR21_Pos (21U)
6931#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6932#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6933#define EXTI_RTSR_TR22_Pos (22U)
6934#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6935#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6936#define EXTI_RTSR_TR23_Pos (23U)
6937#define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos)
6938#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk
6940/****************** Bit definition for EXTI_FTSR register *******************/
6941#define EXTI_FTSR_TR0_Pos (0U)
6942#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6943#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6944#define EXTI_FTSR_TR1_Pos (1U)
6945#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6946#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6947#define EXTI_FTSR_TR2_Pos (2U)
6948#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6949#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6950#define EXTI_FTSR_TR3_Pos (3U)
6951#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6952#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6953#define EXTI_FTSR_TR4_Pos (4U)
6954#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6955#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6956#define EXTI_FTSR_TR5_Pos (5U)
6957#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6958#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6959#define EXTI_FTSR_TR6_Pos (6U)
6960#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6961#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6962#define EXTI_FTSR_TR7_Pos (7U)
6963#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6964#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6965#define EXTI_FTSR_TR8_Pos (8U)
6966#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6967#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6968#define EXTI_FTSR_TR9_Pos (9U)
6969#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6970#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6971#define EXTI_FTSR_TR10_Pos (10U)
6972#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6973#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6974#define EXTI_FTSR_TR11_Pos (11U)
6975#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6976#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6977#define EXTI_FTSR_TR12_Pos (12U)
6978#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6979#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6980#define EXTI_FTSR_TR13_Pos (13U)
6981#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6982#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6983#define EXTI_FTSR_TR14_Pos (14U)
6984#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6985#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6986#define EXTI_FTSR_TR15_Pos (15U)
6987#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6988#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6989#define EXTI_FTSR_TR16_Pos (16U)
6990#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6991#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6992#define EXTI_FTSR_TR17_Pos (17U)
6993#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6994#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6995#define EXTI_FTSR_TR18_Pos (18U)
6996#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6997#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6998#define EXTI_FTSR_TR19_Pos (19U)
6999#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
7000#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
7001#define EXTI_FTSR_TR20_Pos (20U)
7002#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
7003#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
7004#define EXTI_FTSR_TR21_Pos (21U)
7005#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
7006#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
7007#define EXTI_FTSR_TR22_Pos (22U)
7008#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
7009#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
7010#define EXTI_FTSR_TR23_Pos (23U)
7011#define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos)
7012#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk
7014/****************** Bit definition for EXTI_SWIER register ******************/
7015#define EXTI_SWIER_SWIER0_Pos (0U)
7016#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
7017#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
7018#define EXTI_SWIER_SWIER1_Pos (1U)
7019#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
7020#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
7021#define EXTI_SWIER_SWIER2_Pos (2U)
7022#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
7023#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
7024#define EXTI_SWIER_SWIER3_Pos (3U)
7025#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
7026#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
7027#define EXTI_SWIER_SWIER4_Pos (4U)
7028#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
7029#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
7030#define EXTI_SWIER_SWIER5_Pos (5U)
7031#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
7032#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
7033#define EXTI_SWIER_SWIER6_Pos (6U)
7034#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
7035#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
7036#define EXTI_SWIER_SWIER7_Pos (7U)
7037#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
7038#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
7039#define EXTI_SWIER_SWIER8_Pos (8U)
7040#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
7041#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
7042#define EXTI_SWIER_SWIER9_Pos (9U)
7043#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
7044#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
7045#define EXTI_SWIER_SWIER10_Pos (10U)
7046#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
7047#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
7048#define EXTI_SWIER_SWIER11_Pos (11U)
7049#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
7050#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
7051#define EXTI_SWIER_SWIER12_Pos (12U)
7052#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
7053#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
7054#define EXTI_SWIER_SWIER13_Pos (13U)
7055#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
7056#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
7057#define EXTI_SWIER_SWIER14_Pos (14U)
7058#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
7059#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
7060#define EXTI_SWIER_SWIER15_Pos (15U)
7061#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
7062#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
7063#define EXTI_SWIER_SWIER16_Pos (16U)
7064#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
7065#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
7066#define EXTI_SWIER_SWIER17_Pos (17U)
7067#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
7068#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
7069#define EXTI_SWIER_SWIER18_Pos (18U)
7070#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
7071#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
7072#define EXTI_SWIER_SWIER19_Pos (19U)
7073#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
7074#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
7075#define EXTI_SWIER_SWIER20_Pos (20U)
7076#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
7077#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
7078#define EXTI_SWIER_SWIER21_Pos (21U)
7079#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
7080#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
7081#define EXTI_SWIER_SWIER22_Pos (22U)
7082#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
7083#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
7084#define EXTI_SWIER_SWIER23_Pos (23U)
7085#define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos)
7086#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk
7088/******************* Bit definition for EXTI_PR register ********************/
7089#define EXTI_PR_PR0_Pos (0U)
7090#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
7091#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
7092#define EXTI_PR_PR1_Pos (1U)
7093#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
7094#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
7095#define EXTI_PR_PR2_Pos (2U)
7096#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
7097#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
7098#define EXTI_PR_PR3_Pos (3U)
7099#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
7100#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
7101#define EXTI_PR_PR4_Pos (4U)
7102#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
7103#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
7104#define EXTI_PR_PR5_Pos (5U)
7105#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
7106#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
7107#define EXTI_PR_PR6_Pos (6U)
7108#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
7109#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
7110#define EXTI_PR_PR7_Pos (7U)
7111#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
7112#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
7113#define EXTI_PR_PR8_Pos (8U)
7114#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
7115#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
7116#define EXTI_PR_PR9_Pos (9U)
7117#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
7118#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
7119#define EXTI_PR_PR10_Pos (10U)
7120#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
7121#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
7122#define EXTI_PR_PR11_Pos (11U)
7123#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
7124#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
7125#define EXTI_PR_PR12_Pos (12U)
7126#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
7127#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
7128#define EXTI_PR_PR13_Pos (13U)
7129#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
7130#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
7131#define EXTI_PR_PR14_Pos (14U)
7132#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
7133#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
7134#define EXTI_PR_PR15_Pos (15U)
7135#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
7136#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
7137#define EXTI_PR_PR16_Pos (16U)
7138#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
7139#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
7140#define EXTI_PR_PR17_Pos (17U)
7141#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
7142#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
7143#define EXTI_PR_PR18_Pos (18U)
7144#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
7145#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
7146#define EXTI_PR_PR19_Pos (19U)
7147#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
7148#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
7149#define EXTI_PR_PR20_Pos (20U)
7150#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
7151#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
7152#define EXTI_PR_PR21_Pos (21U)
7153#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
7154#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
7155#define EXTI_PR_PR22_Pos (22U)
7156#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
7157#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
7158#define EXTI_PR_PR23_Pos (23U)
7159#define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos)
7160#define EXTI_PR_PR23 EXTI_PR_PR23_Msk
7162/******************************************************************************/
7163/* */
7164/* FLASH */
7165/* */
7166/******************************************************************************/
7167/*
7168* @brief FLASH Total Sectors Number
7169*/
7170#define FLASH_SECTOR_TOTAL 8
7171
7172/******************* Bits definition for FLASH_ACR register *****************/
7173#define FLASH_ACR_LATENCY_Pos (0U)
7174#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
7175#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7176#define FLASH_ACR_LATENCY_0WS 0x00000000U
7177#define FLASH_ACR_LATENCY_1WS 0x00000001U
7178#define FLASH_ACR_LATENCY_2WS 0x00000002U
7179#define FLASH_ACR_LATENCY_3WS 0x00000003U
7180#define FLASH_ACR_LATENCY_4WS 0x00000004U
7181#define FLASH_ACR_LATENCY_5WS 0x00000005U
7182#define FLASH_ACR_LATENCY_6WS 0x00000006U
7183#define FLASH_ACR_LATENCY_7WS 0x00000007U
7184#define FLASH_ACR_LATENCY_8WS 0x00000008U
7185#define FLASH_ACR_LATENCY_9WS 0x00000009U
7186#define FLASH_ACR_LATENCY_10WS 0x0000000AU
7187#define FLASH_ACR_LATENCY_11WS 0x0000000BU
7188#define FLASH_ACR_LATENCY_12WS 0x0000000CU
7189#define FLASH_ACR_LATENCY_13WS 0x0000000DU
7190#define FLASH_ACR_LATENCY_14WS 0x0000000EU
7191#define FLASH_ACR_LATENCY_15WS 0x0000000FU
7192#define FLASH_ACR_PRFTEN_Pos (8U)
7193#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
7194#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7195#define FLASH_ACR_ARTEN_Pos (9U)
7196#define FLASH_ACR_ARTEN_Msk (0x1UL << FLASH_ACR_ARTEN_Pos)
7197#define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk
7198#define FLASH_ACR_ARTRST_Pos (11U)
7199#define FLASH_ACR_ARTRST_Msk (0x1UL << FLASH_ACR_ARTRST_Pos)
7200#define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk
7201
7202/******************* Bits definition for FLASH_SR register ******************/
7203#define FLASH_SR_EOP_Pos (0U)
7204#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
7205#define FLASH_SR_EOP FLASH_SR_EOP_Msk
7206#define FLASH_SR_OPERR_Pos (1U)
7207#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
7208#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
7209#define FLASH_SR_WRPERR_Pos (4U)
7210#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
7211#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7212#define FLASH_SR_PGAERR_Pos (5U)
7213#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
7214#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7215#define FLASH_SR_PGPERR_Pos (6U)
7216#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
7217#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
7218#define FLASH_SR_ERSERR_Pos (7U)
7219#define FLASH_SR_ERSERR_Msk (0x1UL << FLASH_SR_ERSERR_Pos)
7220#define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk
7221#define FLASH_SR_BSY_Pos (16U)
7222#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
7223#define FLASH_SR_BSY FLASH_SR_BSY_Msk
7224
7225/******************* Bits definition for FLASH_CR register ******************/
7226#define FLASH_CR_PG_Pos (0U)
7227#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
7228#define FLASH_CR_PG FLASH_CR_PG_Msk
7229#define FLASH_CR_SER_Pos (1U)
7230#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
7231#define FLASH_CR_SER FLASH_CR_SER_Msk
7232#define FLASH_CR_MER_Pos (2U)
7233#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
7234#define FLASH_CR_MER FLASH_CR_MER_Msk
7235#define FLASH_CR_SNB_Pos (3U)
7236#define FLASH_CR_SNB_Msk (0xFUL << FLASH_CR_SNB_Pos)
7237#define FLASH_CR_SNB FLASH_CR_SNB_Msk
7238#define FLASH_CR_SNB_0 0x00000008U
7239#define FLASH_CR_SNB_1 0x00000010U
7240#define FLASH_CR_SNB_2 0x00000020U
7241#define FLASH_CR_SNB_3 0x00000040U
7242#define FLASH_CR_PSIZE_Pos (8U)
7243#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
7244#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
7245#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
7246#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
7247#define FLASH_CR_STRT_Pos (16U)
7248#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
7249#define FLASH_CR_STRT FLASH_CR_STRT_Msk
7250#define FLASH_CR_EOPIE_Pos (24U)
7251#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
7252#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7253#define FLASH_CR_ERRIE_Pos (25U)
7254#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
7255#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
7256#define FLASH_CR_LOCK_Pos (31U)
7257#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
7258#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7259
7260/******************* Bits definition for FLASH_OPTCR register ***************/
7261#define FLASH_OPTCR_OPTLOCK_Pos (0U)
7262#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
7263#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
7264#define FLASH_OPTCR_OPTSTRT_Pos (1U)
7265#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
7266#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
7267#define FLASH_OPTCR_BOR_LEV_Pos (2U)
7268#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
7269#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
7270#define FLASH_OPTCR_BOR_LEV_0 (0x1UL << FLASH_OPTCR_BOR_LEV_Pos)
7271#define FLASH_OPTCR_BOR_LEV_1 (0x2UL << FLASH_OPTCR_BOR_LEV_Pos)
7272#define FLASH_OPTCR_WWDG_SW_Pos (4U)
7273#define FLASH_OPTCR_WWDG_SW_Msk (0x1UL << FLASH_OPTCR_WWDG_SW_Pos)
7274#define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk
7275#define FLASH_OPTCR_IWDG_SW_Pos (5U)
7276#define FLASH_OPTCR_IWDG_SW_Msk (0x1UL << FLASH_OPTCR_IWDG_SW_Pos)
7277#define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk
7278#define FLASH_OPTCR_nRST_STOP_Pos (6U)
7279#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
7280#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
7281#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
7282#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
7283#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
7284#define FLASH_OPTCR_RDP_Pos (8U)
7285#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
7286#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
7287#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
7288#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
7289#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
7290#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
7291#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
7292#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
7293#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
7294#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
7295#define FLASH_OPTCR_nWRP_Pos (16U)
7296#define FLASH_OPTCR_nWRP_Msk (0xFFUL << FLASH_OPTCR_nWRP_Pos)
7297#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
7298#define FLASH_OPTCR_nWRP_0 0x00010000U
7299#define FLASH_OPTCR_nWRP_1 0x00020000U
7300#define FLASH_OPTCR_nWRP_2 0x00040000U
7301#define FLASH_OPTCR_nWRP_3 0x00080000U
7302#define FLASH_OPTCR_nWRP_4 0x00100000U
7303#define FLASH_OPTCR_nWRP_5 0x00200000U
7304#define FLASH_OPTCR_nWRP_6 0x00400000U
7305#define FLASH_OPTCR_nWRP_7 0x00800000U
7306#define FLASH_OPTCR_IWDG_STDBY_Pos (30U)
7307#define FLASH_OPTCR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTCR_IWDG_STDBY_Pos)
7308#define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk
7309#define FLASH_OPTCR_IWDG_STOP_Pos (31U)
7310#define FLASH_OPTCR_IWDG_STOP_Msk (0x1UL << FLASH_OPTCR_IWDG_STOP_Pos)
7311#define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk
7312
7313/******************* Bits definition for FLASH_OPTCR1 register ***************/
7314#define FLASH_OPTCR1_BOOT_ADD0_Pos (0U)
7315#define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD0_Pos)
7316#define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk
7317#define FLASH_OPTCR1_BOOT_ADD1_Pos (16U)
7318#define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD1_Pos)
7319#define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk
7320
7321
7322/******************************************************************************/
7323/* */
7324/* Flexible Memory Controller */
7325/* */
7326/******************************************************************************/
7327/****************** Bit definition for FMC_BCR1 register *******************/
7328#define FMC_BCR1_MBKEN_Pos (0U)
7329#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)
7330#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk
7331#define FMC_BCR1_MUXEN_Pos (1U)
7332#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)
7333#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk
7334#define FMC_BCR1_MTYP_Pos (2U)
7335#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)
7336#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk
7337#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)
7338#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)
7339#define FMC_BCR1_MWID_Pos (4U)
7340#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)
7341#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk
7342#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)
7343#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)
7344#define FMC_BCR1_FACCEN_Pos (6U)
7345#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)
7346#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk
7347#define FMC_BCR1_BURSTEN_Pos (8U)
7348#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)
7349#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk
7350#define FMC_BCR1_WAITPOL_Pos (9U)
7351#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)
7352#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk
7353#define FMC_BCR1_WRAPMOD_Pos (10U)
7354#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos)
7355#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk
7356#define FMC_BCR1_WAITCFG_Pos (11U)
7357#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)
7358#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk
7359#define FMC_BCR1_WREN_Pos (12U)
7360#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)
7361#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk
7362#define FMC_BCR1_WAITEN_Pos (13U)
7363#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)
7364#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk
7365#define FMC_BCR1_EXTMOD_Pos (14U)
7366#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)
7367#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk
7368#define FMC_BCR1_ASYNCWAIT_Pos (15U)
7369#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)
7370#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk
7371#define FMC_BCR1_CPSIZE_Pos (16U)
7372#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos)
7373#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk
7374#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos)
7375#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos)
7376#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos)
7377#define FMC_BCR1_CBURSTRW_Pos (19U)
7378#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)
7379#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk
7380#define FMC_BCR1_CCLKEN_Pos (20U)
7381#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
7382#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
7383#define FMC_BCR1_WFDIS_Pos (21U)
7384#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
7385#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
7387/****************** Bit definition for FMC_BCR2 register *******************/
7388#define FMC_BCR2_MBKEN_Pos (0U)
7389#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)
7390#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk
7391#define FMC_BCR2_MUXEN_Pos (1U)
7392#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)
7393#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk
7394#define FMC_BCR2_MTYP_Pos (2U)
7395#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)
7396#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk
7397#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)
7398#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)
7399#define FMC_BCR2_MWID_Pos (4U)
7400#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)
7401#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk
7402#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)
7403#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)
7404#define FMC_BCR2_FACCEN_Pos (6U)
7405#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)
7406#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk
7407#define FMC_BCR2_BURSTEN_Pos (8U)
7408#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)
7409#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk
7410#define FMC_BCR2_WAITPOL_Pos (9U)
7411#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)
7412#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk
7413#define FMC_BCR2_WRAPMOD_Pos (10U)
7414#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos)
7415#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk
7416#define FMC_BCR2_WAITCFG_Pos (11U)
7417#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)
7418#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk
7419#define FMC_BCR2_WREN_Pos (12U)
7420#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)
7421#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk
7422#define FMC_BCR2_WAITEN_Pos (13U)
7423#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)
7424#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk
7425#define FMC_BCR2_EXTMOD_Pos (14U)
7426#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)
7427#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk
7428#define FMC_BCR2_ASYNCWAIT_Pos (15U)
7429#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)
7430#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk
7431#define FMC_BCR2_CPSIZE_Pos (16U)
7432#define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos)
7433#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk
7434#define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos)
7435#define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos)
7436#define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos)
7437#define FMC_BCR2_CBURSTRW_Pos (19U)
7438#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)
7439#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk
7441/****************** Bit definition for FMC_BCR3 register *******************/
7442#define FMC_BCR3_MBKEN_Pos (0U)
7443#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)
7444#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk
7445#define FMC_BCR3_MUXEN_Pos (1U)
7446#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)
7447#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk
7448#define FMC_BCR3_MTYP_Pos (2U)
7449#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)
7450#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk
7451#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)
7452#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)
7453#define FMC_BCR3_MWID_Pos (4U)
7454#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)
7455#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk
7456#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)
7457#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)
7458#define FMC_BCR3_FACCEN_Pos (6U)
7459#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)
7460#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk
7461#define FMC_BCR3_BURSTEN_Pos (8U)
7462#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)
7463#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk
7464#define FMC_BCR3_WAITPOL_Pos (9U)
7465#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)
7466#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk
7467#define FMC_BCR3_WRAPMOD_Pos (10U)
7468#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos)
7469#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk
7470#define FMC_BCR3_WAITCFG_Pos (11U)
7471#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)
7472#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk
7473#define FMC_BCR3_WREN_Pos (12U)
7474#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)
7475#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk
7476#define FMC_BCR3_WAITEN_Pos (13U)
7477#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)
7478#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk
7479#define FMC_BCR3_EXTMOD_Pos (14U)
7480#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)
7481#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk
7482#define FMC_BCR3_ASYNCWAIT_Pos (15U)
7483#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)
7484#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk
7485#define FMC_BCR3_CPSIZE_Pos (16U)
7486#define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos)
7487#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk
7488#define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos)
7489#define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos)
7490#define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos)
7491#define FMC_BCR3_CBURSTRW_Pos (19U)
7492#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)
7493#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk
7495/****************** Bit definition for FMC_BCR4 register *******************/
7496#define FMC_BCR4_MBKEN_Pos (0U)
7497#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)
7498#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk
7499#define FMC_BCR4_MUXEN_Pos (1U)
7500#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)
7501#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk
7502#define FMC_BCR4_MTYP_Pos (2U)
7503#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)
7504#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk
7505#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)
7506#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)
7507#define FMC_BCR4_MWID_Pos (4U)
7508#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)
7509#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk
7510#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)
7511#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)
7512#define FMC_BCR4_FACCEN_Pos (6U)
7513#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)
7514#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk
7515#define FMC_BCR4_BURSTEN_Pos (8U)
7516#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)
7517#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk
7518#define FMC_BCR4_WAITPOL_Pos (9U)
7519#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)
7520#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk
7521#define FMC_BCR4_WRAPMOD_Pos (10U)
7522#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos)
7523#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk
7524#define FMC_BCR4_WAITCFG_Pos (11U)
7525#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)
7526#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk
7527#define FMC_BCR4_WREN_Pos (12U)
7528#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)
7529#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk
7530#define FMC_BCR4_WAITEN_Pos (13U)
7531#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)
7532#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk
7533#define FMC_BCR4_EXTMOD_Pos (14U)
7534#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)
7535#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk
7536#define FMC_BCR4_ASYNCWAIT_Pos (15U)
7537#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)
7538#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk
7539#define FMC_BCR4_CPSIZE_Pos (16U)
7540#define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos)
7541#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk
7542#define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos)
7543#define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos)
7544#define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos)
7545#define FMC_BCR4_CBURSTRW_Pos (19U)
7546#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)
7547#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk
7549/****************** Bit definition for FMC_BTR1 register ******************/
7550#define FMC_BTR1_ADDSET_Pos (0U)
7551#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)
7552#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk
7553#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)
7554#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)
7555#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)
7556#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)
7557#define FMC_BTR1_ADDHLD_Pos (4U)
7558#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)
7559#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk
7560#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)
7561#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)
7562#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)
7563#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)
7564#define FMC_BTR1_DATAST_Pos (8U)
7565#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)
7566#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk
7567#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)
7568#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)
7569#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)
7570#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)
7571#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)
7572#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)
7573#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)
7574#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)
7575#define FMC_BTR1_BUSTURN_Pos (16U)
7576#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)
7577#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk
7578#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)
7579#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)
7580#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)
7581#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)
7582#define FMC_BTR1_CLKDIV_Pos (20U)
7583#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)
7584#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk
7585#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)
7586#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)
7587#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)
7588#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)
7589#define FMC_BTR1_DATLAT_Pos (24U)
7590#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)
7591#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk
7592#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)
7593#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)
7594#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)
7595#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)
7596#define FMC_BTR1_ACCMOD_Pos (28U)
7597#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)
7598#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk
7599#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)
7600#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)
7602/****************** Bit definition for FMC_BTR2 register *******************/
7603#define FMC_BTR2_ADDSET_Pos (0U)
7604#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)
7605#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk
7606#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)
7607#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)
7608#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)
7609#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)
7610#define FMC_BTR2_ADDHLD_Pos (4U)
7611#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)
7612#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk
7613#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)
7614#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)
7615#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)
7616#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)
7617#define FMC_BTR2_DATAST_Pos (8U)
7618#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)
7619#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk
7620#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)
7621#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)
7622#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)
7623#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)
7624#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)
7625#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)
7626#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)
7627#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)
7628#define FMC_BTR2_BUSTURN_Pos (16U)
7629#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)
7630#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk
7631#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)
7632#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)
7633#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)
7634#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)
7635#define FMC_BTR2_CLKDIV_Pos (20U)
7636#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)
7637#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk
7638#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)
7639#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)
7640#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)
7641#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)
7642#define FMC_BTR2_DATLAT_Pos (24U)
7643#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)
7644#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk
7645#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)
7646#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)
7647#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)
7648#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)
7649#define FMC_BTR2_ACCMOD_Pos (28U)
7650#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)
7651#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk
7652#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)
7653#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)
7655/******************* Bit definition for FMC_BTR3 register *******************/
7656#define FMC_BTR3_ADDSET_Pos (0U)
7657#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)
7658#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk
7659#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)
7660#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)
7661#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)
7662#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)
7663#define FMC_BTR3_ADDHLD_Pos (4U)
7664#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)
7665#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk
7666#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)
7667#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)
7668#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)
7669#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)
7670#define FMC_BTR3_DATAST_Pos (8U)
7671#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)
7672#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk
7673#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)
7674#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)
7675#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)
7676#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)
7677#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)
7678#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)
7679#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)
7680#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)
7681#define FMC_BTR3_BUSTURN_Pos (16U)
7682#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)
7683#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk
7684#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)
7685#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)
7686#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)
7687#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)
7688#define FMC_BTR3_CLKDIV_Pos (20U)
7689#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)
7690#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk
7691#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)
7692#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)
7693#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)
7694#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)
7695#define FMC_BTR3_DATLAT_Pos (24U)
7696#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)
7697#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk
7698#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)
7699#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)
7700#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)
7701#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)
7702#define FMC_BTR3_ACCMOD_Pos (28U)
7703#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)
7704#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk
7705#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)
7706#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)
7708/****************** Bit definition for FMC_BTR4 register *******************/
7709#define FMC_BTR4_ADDSET_Pos (0U)
7710#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)
7711#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk
7712#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)
7713#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)
7714#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)
7715#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)
7716#define FMC_BTR4_ADDHLD_Pos (4U)
7717#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)
7718#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk
7719#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)
7720#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)
7721#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)
7722#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)
7723#define FMC_BTR4_DATAST_Pos (8U)
7724#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)
7725#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk
7726#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)
7727#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)
7728#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)
7729#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)
7730#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)
7731#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)
7732#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)
7733#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)
7734#define FMC_BTR4_BUSTURN_Pos (16U)
7735#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)
7736#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk
7737#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)
7738#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)
7739#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)
7740#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)
7741#define FMC_BTR4_CLKDIV_Pos (20U)
7742#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)
7743#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk
7744#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)
7745#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)
7746#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)
7747#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)
7748#define FMC_BTR4_DATLAT_Pos (24U)
7749#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)
7750#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk
7751#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)
7752#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)
7753#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)
7754#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)
7755#define FMC_BTR4_ACCMOD_Pos (28U)
7756#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)
7757#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk
7758#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)
7759#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)
7761/****************** Bit definition for FMC_BWTR1 register ******************/
7762#define FMC_BWTR1_ADDSET_Pos (0U)
7763#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)
7764#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk
7765#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)
7766#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)
7767#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)
7768#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)
7769#define FMC_BWTR1_ADDHLD_Pos (4U)
7770#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)
7771#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk
7772#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)
7773#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)
7774#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)
7775#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)
7776#define FMC_BWTR1_DATAST_Pos (8U)
7777#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)
7778#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk
7779#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)
7780#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)
7781#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)
7782#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)
7783#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)
7784#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)
7785#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)
7786#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)
7787#define FMC_BWTR1_BUSTURN_Pos (16U)
7788#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos)
7789#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk
7790#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos)
7791#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos)
7792#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos)
7793#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos)
7794#define FMC_BWTR1_ACCMOD_Pos (28U)
7795#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)
7796#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk
7797#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)
7798#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)
7800/****************** Bit definition for FMC_BWTR2 register ******************/
7801#define FMC_BWTR2_ADDSET_Pos (0U)
7802#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)
7803#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk
7804#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)
7805#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)
7806#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)
7807#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)
7808#define FMC_BWTR2_ADDHLD_Pos (4U)
7809#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)
7810#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk
7811#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)
7812#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)
7813#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)
7814#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)
7815#define FMC_BWTR2_DATAST_Pos (8U)
7816#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)
7817#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk
7818#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)
7819#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)
7820#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)
7821#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)
7822#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)
7823#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)
7824#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)
7825#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)
7826#define FMC_BWTR2_BUSTURN_Pos (16U)
7827#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos)
7828#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk
7829#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos)
7830#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos)
7831#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos)
7832#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos)
7833#define FMC_BWTR2_ACCMOD_Pos (28U)
7834#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)
7835#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk
7836#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)
7837#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)
7839/****************** Bit definition for FMC_BWTR3 register ******************/
7840#define FMC_BWTR3_ADDSET_Pos (0U)
7841#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)
7842#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk
7843#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)
7844#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)
7845#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)
7846#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)
7847#define FMC_BWTR3_ADDHLD_Pos (4U)
7848#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)
7849#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk
7850#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)
7851#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)
7852#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)
7853#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)
7854#define FMC_BWTR3_DATAST_Pos (8U)
7855#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)
7856#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk
7857#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)
7858#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)
7859#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)
7860#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)
7861#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)
7862#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)
7863#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)
7864#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)
7865#define FMC_BWTR3_BUSTURN_Pos (16U)
7866#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos)
7867#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk
7868#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos)
7869#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos)
7870#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos)
7871#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos)
7872#define FMC_BWTR3_ACCMOD_Pos (28U)
7873#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)
7874#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk
7875#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)
7876#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)
7878/****************** Bit definition for FMC_BWTR4 register ******************/
7879#define FMC_BWTR4_ADDSET_Pos (0U)
7880#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)
7881#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk
7882#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)
7883#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)
7884#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)
7885#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)
7886#define FMC_BWTR4_ADDHLD_Pos (4U)
7887#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)
7888#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk
7889#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)
7890#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)
7891#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)
7892#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)
7893#define FMC_BWTR4_DATAST_Pos (8U)
7894#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)
7895#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk
7896#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)
7897#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)
7898#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)
7899#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)
7900#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)
7901#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)
7902#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)
7903#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)
7904#define FMC_BWTR4_BUSTURN_Pos (16U)
7905#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos)
7906#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk
7907#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos)
7908#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos)
7909#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos)
7910#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos)
7911#define FMC_BWTR4_ACCMOD_Pos (28U)
7912#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)
7913#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk
7914#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)
7915#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)
7917/****************** Bit definition for FMC_PCR register *******************/
7918#define FMC_PCR_PWAITEN_Pos (1U)
7919#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
7920#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
7921#define FMC_PCR_PBKEN_Pos (2U)
7922#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
7923#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
7924#define FMC_PCR_PTYP_Pos (3U)
7925#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
7926#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
7927#define FMC_PCR_PWID_Pos (4U)
7928#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
7929#define FMC_PCR_PWID FMC_PCR_PWID_Msk
7930#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
7931#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
7932#define FMC_PCR_ECCEN_Pos (6U)
7933#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
7934#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
7935#define FMC_PCR_TCLR_Pos (9U)
7936#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
7937#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
7938#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
7939#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
7940#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
7941#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
7942#define FMC_PCR_TAR_Pos (13U)
7943#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
7944#define FMC_PCR_TAR FMC_PCR_TAR_Msk
7945#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
7946#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
7947#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
7948#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
7949#define FMC_PCR_ECCPS_Pos (17U)
7950#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
7951#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
7952#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
7953#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
7954#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
7956/******************* Bit definition for FMC_SR register *******************/
7957#define FMC_SR_IRS_Pos (0U)
7958#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
7959#define FMC_SR_IRS FMC_SR_IRS_Msk
7960#define FMC_SR_ILS_Pos (1U)
7961#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
7962#define FMC_SR_ILS FMC_SR_ILS_Msk
7963#define FMC_SR_IFS_Pos (2U)
7964#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
7965#define FMC_SR_IFS FMC_SR_IFS_Msk
7966#define FMC_SR_IREN_Pos (3U)
7967#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
7968#define FMC_SR_IREN FMC_SR_IREN_Msk
7969#define FMC_SR_ILEN_Pos (4U)
7970#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
7971#define FMC_SR_ILEN FMC_SR_ILEN_Msk
7972#define FMC_SR_IFEN_Pos (5U)
7973#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
7974#define FMC_SR_IFEN FMC_SR_IFEN_Msk
7975#define FMC_SR_FEMPT_Pos (6U)
7976#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
7977#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
7979/****************** Bit definition for FMC_PMEM register ******************/
7980#define FMC_PMEM_MEMSET3_Pos (0U)
7981#define FMC_PMEM_MEMSET3_Msk (0xFFUL << FMC_PMEM_MEMSET3_Pos)
7982#define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk
7983#define FMC_PMEM_MEMSET3_0 (0x01UL << FMC_PMEM_MEMSET3_Pos)
7984#define FMC_PMEM_MEMSET3_1 (0x02UL << FMC_PMEM_MEMSET3_Pos)
7985#define FMC_PMEM_MEMSET3_2 (0x04UL << FMC_PMEM_MEMSET3_Pos)
7986#define FMC_PMEM_MEMSET3_3 (0x08UL << FMC_PMEM_MEMSET3_Pos)
7987#define FMC_PMEM_MEMSET3_4 (0x10UL << FMC_PMEM_MEMSET3_Pos)
7988#define FMC_PMEM_MEMSET3_5 (0x20UL << FMC_PMEM_MEMSET3_Pos)
7989#define FMC_PMEM_MEMSET3_6 (0x40UL << FMC_PMEM_MEMSET3_Pos)
7990#define FMC_PMEM_MEMSET3_7 (0x80UL << FMC_PMEM_MEMSET3_Pos)
7991#define FMC_PMEM_MEMWAIT3_Pos (8U)
7992#define FMC_PMEM_MEMWAIT3_Msk (0xFFUL << FMC_PMEM_MEMWAIT3_Pos)
7993#define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk
7994#define FMC_PMEM_MEMWAIT3_0 (0x01UL << FMC_PMEM_MEMWAIT3_Pos)
7995#define FMC_PMEM_MEMWAIT3_1 (0x02UL << FMC_PMEM_MEMWAIT3_Pos)
7996#define FMC_PMEM_MEMWAIT3_2 (0x04UL << FMC_PMEM_MEMWAIT3_Pos)
7997#define FMC_PMEM_MEMWAIT3_3 (0x08UL << FMC_PMEM_MEMWAIT3_Pos)
7998#define FMC_PMEM_MEMWAIT3_4 (0x10UL << FMC_PMEM_MEMWAIT3_Pos)
7999#define FMC_PMEM_MEMWAIT3_5 (0x20UL << FMC_PMEM_MEMWAIT3_Pos)
8000#define FMC_PMEM_MEMWAIT3_6 (0x40UL << FMC_PMEM_MEMWAIT3_Pos)
8001#define FMC_PMEM_MEMWAIT3_7 (0x80UL << FMC_PMEM_MEMWAIT3_Pos)
8002#define FMC_PMEM_MEMHOLD3_Pos (16U)
8003#define FMC_PMEM_MEMHOLD3_Msk (0xFFUL << FMC_PMEM_MEMHOLD3_Pos)
8004#define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk
8005#define FMC_PMEM_MEMHOLD3_0 (0x01UL << FMC_PMEM_MEMHOLD3_Pos)
8006#define FMC_PMEM_MEMHOLD3_1 (0x02UL << FMC_PMEM_MEMHOLD3_Pos)
8007#define FMC_PMEM_MEMHOLD3_2 (0x04UL << FMC_PMEM_MEMHOLD3_Pos)
8008#define FMC_PMEM_MEMHOLD3_3 (0x08UL << FMC_PMEM_MEMHOLD3_Pos)
8009#define FMC_PMEM_MEMHOLD3_4 (0x10UL << FMC_PMEM_MEMHOLD3_Pos)
8010#define FMC_PMEM_MEMHOLD3_5 (0x20UL << FMC_PMEM_MEMHOLD3_Pos)
8011#define FMC_PMEM_MEMHOLD3_6 (0x40UL << FMC_PMEM_MEMHOLD3_Pos)
8012#define FMC_PMEM_MEMHOLD3_7 (0x80UL << FMC_PMEM_MEMHOLD3_Pos)
8013#define FMC_PMEM_MEMHIZ3_Pos (24U)
8014#define FMC_PMEM_MEMHIZ3_Msk (0xFFUL << FMC_PMEM_MEMHIZ3_Pos)
8015#define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk
8016#define FMC_PMEM_MEMHIZ3_0 (0x01UL << FMC_PMEM_MEMHIZ3_Pos)
8017#define FMC_PMEM_MEMHIZ3_1 (0x02UL << FMC_PMEM_MEMHIZ3_Pos)
8018#define FMC_PMEM_MEMHIZ3_2 (0x04UL << FMC_PMEM_MEMHIZ3_Pos)
8019#define FMC_PMEM_MEMHIZ3_3 (0x08UL << FMC_PMEM_MEMHIZ3_Pos)
8020#define FMC_PMEM_MEMHIZ3_4 (0x10UL << FMC_PMEM_MEMHIZ3_Pos)
8021#define FMC_PMEM_MEMHIZ3_5 (0x20UL << FMC_PMEM_MEMHIZ3_Pos)
8022#define FMC_PMEM_MEMHIZ3_6 (0x40UL << FMC_PMEM_MEMHIZ3_Pos)
8023#define FMC_PMEM_MEMHIZ3_7 (0x80UL << FMC_PMEM_MEMHIZ3_Pos)
8025/****************** Bit definition for FMC_PATT register ******************/
8026#define FMC_PATT_ATTSET3_Pos (0U)
8027#define FMC_PATT_ATTSET3_Msk (0xFFUL << FMC_PATT_ATTSET3_Pos)
8028#define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk
8029#define FMC_PATT_ATTSET3_0 (0x01UL << FMC_PATT_ATTSET3_Pos)
8030#define FMC_PATT_ATTSET3_1 (0x02UL << FMC_PATT_ATTSET3_Pos)
8031#define FMC_PATT_ATTSET3_2 (0x04UL << FMC_PATT_ATTSET3_Pos)
8032#define FMC_PATT_ATTSET3_3 (0x08UL << FMC_PATT_ATTSET3_Pos)
8033#define FMC_PATT_ATTSET3_4 (0x10UL << FMC_PATT_ATTSET3_Pos)
8034#define FMC_PATT_ATTSET3_5 (0x20UL << FMC_PATT_ATTSET3_Pos)
8035#define FMC_PATT_ATTSET3_6 (0x40UL << FMC_PATT_ATTSET3_Pos)
8036#define FMC_PATT_ATTSET3_7 (0x80UL << FMC_PATT_ATTSET3_Pos)
8037#define FMC_PATT_ATTWAIT3_Pos (8U)
8038#define FMC_PATT_ATTWAIT3_Msk (0xFFUL << FMC_PATT_ATTWAIT3_Pos)
8039#define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk
8040#define FMC_PATT_ATTWAIT3_0 (0x01UL << FMC_PATT_ATTWAIT3_Pos)
8041#define FMC_PATT_ATTWAIT3_1 (0x02UL << FMC_PATT_ATTWAIT3_Pos)
8042#define FMC_PATT_ATTWAIT3_2 (0x04UL << FMC_PATT_ATTWAIT3_Pos)
8043#define FMC_PATT_ATTWAIT3_3 (0x08UL << FMC_PATT_ATTWAIT3_Pos)
8044#define FMC_PATT_ATTWAIT3_4 (0x10UL << FMC_PATT_ATTWAIT3_Pos)
8045#define FMC_PATT_ATTWAIT3_5 (0x20UL << FMC_PATT_ATTWAIT3_Pos)
8046#define FMC_PATT_ATTWAIT3_6 (0x40UL << FMC_PATT_ATTWAIT3_Pos)
8047#define FMC_PATT_ATTWAIT3_7 (0x80UL << FMC_PATT_ATTWAIT3_Pos)
8048#define FMC_PATT_ATTHOLD3_Pos (16U)
8049#define FMC_PATT_ATTHOLD3_Msk (0xFFUL << FMC_PATT_ATTHOLD3_Pos)
8050#define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk
8051#define FMC_PATT_ATTHOLD3_0 (0x01UL << FMC_PATT_ATTHOLD3_Pos)
8052#define FMC_PATT_ATTHOLD3_1 (0x02UL << FMC_PATT_ATTHOLD3_Pos)
8053#define FMC_PATT_ATTHOLD3_2 (0x04UL << FMC_PATT_ATTHOLD3_Pos)
8054#define FMC_PATT_ATTHOLD3_3 (0x08UL << FMC_PATT_ATTHOLD3_Pos)
8055#define FMC_PATT_ATTHOLD3_4 (0x10UL << FMC_PATT_ATTHOLD3_Pos)
8056#define FMC_PATT_ATTHOLD3_5 (0x20UL << FMC_PATT_ATTHOLD3_Pos)
8057#define FMC_PATT_ATTHOLD3_6 (0x40UL << FMC_PATT_ATTHOLD3_Pos)
8058#define FMC_PATT_ATTHOLD3_7 (0x80UL << FMC_PATT_ATTHOLD3_Pos)
8059#define FMC_PATT_ATTHIZ3_Pos (24U)
8060#define FMC_PATT_ATTHIZ3_Msk (0xFFUL << FMC_PATT_ATTHIZ3_Pos)
8061#define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk
8062#define FMC_PATT_ATTHIZ3_0 (0x01UL << FMC_PATT_ATTHIZ3_Pos)
8063#define FMC_PATT_ATTHIZ3_1 (0x02UL << FMC_PATT_ATTHIZ3_Pos)
8064#define FMC_PATT_ATTHIZ3_2 (0x04UL << FMC_PATT_ATTHIZ3_Pos)
8065#define FMC_PATT_ATTHIZ3_3 (0x08UL << FMC_PATT_ATTHIZ3_Pos)
8066#define FMC_PATT_ATTHIZ3_4 (0x10UL << FMC_PATT_ATTHIZ3_Pos)
8067#define FMC_PATT_ATTHIZ3_5 (0x20UL << FMC_PATT_ATTHIZ3_Pos)
8068#define FMC_PATT_ATTHIZ3_6 (0x40UL << FMC_PATT_ATTHIZ3_Pos)
8069#define FMC_PATT_ATTHIZ3_7 (0x80UL << FMC_PATT_ATTHIZ3_Pos)
8071/****************** Bit definition for FMC_ECCR register ******************/
8072#define FMC_ECCR_ECC3_Pos (0U)
8073#define FMC_ECCR_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC3_Pos)
8074#define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk
8076/****************** Bit definition for FMC_SDCR1 register ******************/
8077#define FMC_SDCR1_NC_Pos (0U)
8078#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos)
8079#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk
8080#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos)
8081#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos)
8082#define FMC_SDCR1_NR_Pos (2U)
8083#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos)
8084#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk
8085#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos)
8086#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos)
8087#define FMC_SDCR1_MWID_Pos (4U)
8088#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos)
8089#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk
8090#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos)
8091#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos)
8092#define FMC_SDCR1_NB_Pos (6U)
8093#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos)
8094#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk
8095#define FMC_SDCR1_CAS_Pos (7U)
8096#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos)
8097#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk
8098#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos)
8099#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos)
8100#define FMC_SDCR1_WP_Pos (9U)
8101#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos)
8102#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk
8103#define FMC_SDCR1_SDCLK_Pos (10U)
8104#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos)
8105#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk
8106#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos)
8107#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos)
8108#define FMC_SDCR1_RBURST_Pos (12U)
8109#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos)
8110#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk
8111#define FMC_SDCR1_RPIPE_Pos (13U)
8112#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos)
8113#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk
8114#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos)
8115#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos)
8117/****************** Bit definition for FMC_SDCR2 register ******************/
8118#define FMC_SDCR2_NC_Pos (0U)
8119#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos)
8120#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk
8121#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos)
8122#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos)
8123#define FMC_SDCR2_NR_Pos (2U)
8124#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos)
8125#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk
8126#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos)
8127#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos)
8128#define FMC_SDCR2_MWID_Pos (4U)
8129#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos)
8130#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk
8131#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos)
8132#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos)
8133#define FMC_SDCR2_NB_Pos (6U)
8134#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos)
8135#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk
8136#define FMC_SDCR2_CAS_Pos (7U)
8137#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos)
8138#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk
8139#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos)
8140#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos)
8141#define FMC_SDCR2_WP_Pos (9U)
8142#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos)
8143#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk
8144#define FMC_SDCR2_SDCLK_Pos (10U)
8145#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos)
8146#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk
8147#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos)
8148#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos)
8149#define FMC_SDCR2_RBURST_Pos (12U)
8150#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos)
8151#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk
8152#define FMC_SDCR2_RPIPE_Pos (13U)
8153#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos)
8154#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk
8155#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos)
8156#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos)
8158/****************** Bit definition for FMC_SDTR1 register ******************/
8159#define FMC_SDTR1_TMRD_Pos (0U)
8160#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos)
8161#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk
8162#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos)
8163#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos)
8164#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos)
8165#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos)
8166#define FMC_SDTR1_TXSR_Pos (4U)
8167#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos)
8168#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk
8169#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos)
8170#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos)
8171#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos)
8172#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos)
8173#define FMC_SDTR1_TRAS_Pos (8U)
8174#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos)
8175#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk
8176#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos)
8177#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos)
8178#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos)
8179#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos)
8180#define FMC_SDTR1_TRC_Pos (12U)
8181#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos)
8182#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk
8183#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos)
8184#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos)
8185#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos)
8186#define FMC_SDTR1_TWR_Pos (16U)
8187#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos)
8188#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk
8189#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos)
8190#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos)
8191#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos)
8192#define FMC_SDTR1_TRP_Pos (20U)
8193#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos)
8194#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk
8195#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos)
8196#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos)
8197#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos)
8198#define FMC_SDTR1_TRCD_Pos (24U)
8199#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos)
8200#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk
8201#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos)
8202#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos)
8203#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos)
8205/****************** Bit definition for FMC_SDTR2 register ******************/
8206#define FMC_SDTR2_TMRD_Pos (0U)
8207#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos)
8208#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk
8209#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos)
8210#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos)
8211#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos)
8212#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos)
8213#define FMC_SDTR2_TXSR_Pos (4U)
8214#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos)
8215#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk
8216#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos)
8217#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos)
8218#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos)
8219#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos)
8220#define FMC_SDTR2_TRAS_Pos (8U)
8221#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos)
8222#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk
8223#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos)
8224#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos)
8225#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos)
8226#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos)
8227#define FMC_SDTR2_TRC_Pos (12U)
8228#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos)
8229#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk
8230#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos)
8231#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos)
8232#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos)
8233#define FMC_SDTR2_TWR_Pos (16U)
8234#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos)
8235#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk
8236#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos)
8237#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos)
8238#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos)
8239#define FMC_SDTR2_TRP_Pos (20U)
8240#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos)
8241#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk
8242#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos)
8243#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos)
8244#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos)
8245#define FMC_SDTR2_TRCD_Pos (24U)
8246#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos)
8247#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk
8248#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos)
8249#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos)
8250#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos)
8252/****************** Bit definition for FMC_SDCMR register ******************/
8253#define FMC_SDCMR_MODE_Pos (0U)
8254#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
8255#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
8256#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
8257#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
8258#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos)
8259#define FMC_SDCMR_CTB2_Pos (3U)
8260#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
8261#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
8262#define FMC_SDCMR_CTB1_Pos (4U)
8263#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
8264#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
8265#define FMC_SDCMR_NRFS_Pos (5U)
8266#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
8267#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
8268#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
8269#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
8270#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
8271#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
8272#define FMC_SDCMR_MRD_Pos (9U)
8273#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
8274#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
8276/****************** Bit definition for FMC_SDRTR register ******************/
8277#define FMC_SDRTR_CRE_Pos (0U)
8278#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
8279#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
8280#define FMC_SDRTR_COUNT_Pos (1U)
8281#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
8282#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
8283#define FMC_SDRTR_REIE_Pos (14U)
8284#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
8285#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
8287/****************** Bit definition for FMC_SDSR register ******************/
8288#define FMC_SDSR_RE_Pos (0U)
8289#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
8290#define FMC_SDSR_RE FMC_SDSR_RE_Msk
8291#define FMC_SDSR_MODES1_Pos (1U)
8292#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
8293#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
8294#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
8295#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
8296#define FMC_SDSR_MODES2_Pos (3U)
8297#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
8298#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
8299#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
8300#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
8301#define FMC_SDSR_BUSY_Pos (5U)
8302#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos)
8303#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk
8305/******************************************************************************/
8306/* */
8307/* General Purpose I/O */
8308/* */
8309/******************************************************************************/
8310/****************** Bits definition for GPIO_MODER register *****************/
8311#define GPIO_MODER_MODER0_Pos (0U)
8312#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
8313#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8314#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
8315#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
8316#define GPIO_MODER_MODER1_Pos (2U)
8317#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
8318#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8319#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
8320#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
8321#define GPIO_MODER_MODER2_Pos (4U)
8322#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
8323#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8324#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
8325#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
8326#define GPIO_MODER_MODER3_Pos (6U)
8327#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
8328#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8329#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
8330#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
8331#define GPIO_MODER_MODER4_Pos (8U)
8332#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
8333#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8334#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
8335#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
8336#define GPIO_MODER_MODER5_Pos (10U)
8337#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
8338#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8339#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
8340#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
8341#define GPIO_MODER_MODER6_Pos (12U)
8342#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
8343#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8344#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
8345#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
8346#define GPIO_MODER_MODER7_Pos (14U)
8347#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
8348#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8349#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
8350#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
8351#define GPIO_MODER_MODER8_Pos (16U)
8352#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
8353#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8354#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
8355#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
8356#define GPIO_MODER_MODER9_Pos (18U)
8357#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
8358#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8359#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
8360#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
8361#define GPIO_MODER_MODER10_Pos (20U)
8362#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
8363#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8364#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
8365#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
8366#define GPIO_MODER_MODER11_Pos (22U)
8367#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
8368#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8369#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
8370#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
8371#define GPIO_MODER_MODER12_Pos (24U)
8372#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
8373#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8374#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
8375#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
8376#define GPIO_MODER_MODER13_Pos (26U)
8377#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
8378#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8379#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
8380#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
8381#define GPIO_MODER_MODER14_Pos (28U)
8382#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
8383#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8384#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
8385#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
8386#define GPIO_MODER_MODER15_Pos (30U)
8387#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
8388#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8389#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
8390#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
8392/****************** Bits definition for GPIO_OTYPER register ****************/
8393#define GPIO_OTYPER_OT0_Pos (0U)
8394#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
8395#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8396#define GPIO_OTYPER_OT1_Pos (1U)
8397#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
8398#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8399#define GPIO_OTYPER_OT2_Pos (2U)
8400#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
8401#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8402#define GPIO_OTYPER_OT3_Pos (3U)
8403#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
8404#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8405#define GPIO_OTYPER_OT4_Pos (4U)
8406#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
8407#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8408#define GPIO_OTYPER_OT5_Pos (5U)
8409#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
8410#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8411#define GPIO_OTYPER_OT6_Pos (6U)
8412#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
8413#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8414#define GPIO_OTYPER_OT7_Pos (7U)
8415#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
8416#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8417#define GPIO_OTYPER_OT8_Pos (8U)
8418#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
8419#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8420#define GPIO_OTYPER_OT9_Pos (9U)
8421#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
8422#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8423#define GPIO_OTYPER_OT10_Pos (10U)
8424#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
8425#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8426#define GPIO_OTYPER_OT11_Pos (11U)
8427#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
8428#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8429#define GPIO_OTYPER_OT12_Pos (12U)
8430#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
8431#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8432#define GPIO_OTYPER_OT13_Pos (13U)
8433#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
8434#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8435#define GPIO_OTYPER_OT14_Pos (14U)
8436#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
8437#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8438#define GPIO_OTYPER_OT15_Pos (15U)
8439#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
8440#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8441
8442/* Legacy defines */
8443#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8444#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8445#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8446#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8447#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8448#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8449#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8450#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8451#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8452#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8453#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8454#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8455#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8456#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8457#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8458#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8459
8460/****************** Bits definition for GPIO_OSPEEDR register ***************/
8461#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
8462#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
8463#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
8464#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
8465#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
8466#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
8467#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
8468#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
8469#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
8470#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
8471#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
8472#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
8473#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
8474#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
8475#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
8476#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
8477#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
8478#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
8479#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
8480#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
8481#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
8482#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
8483#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
8484#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
8485#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
8486#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
8487#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
8488#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
8489#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
8490#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
8491#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
8492#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
8493#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
8494#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
8495#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
8496#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
8497#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
8498#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
8499#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
8500#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
8501#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
8502#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
8503#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
8504#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
8505#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
8506#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
8507#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
8508#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
8509#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
8510#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
8511#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
8512#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
8513#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
8514#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
8515#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
8516#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
8517#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
8518#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
8519#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
8520#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
8521#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
8522#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
8523#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
8524#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
8525#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
8526#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
8527#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
8528#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
8529#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
8530#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
8531#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
8532#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
8533#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
8534#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
8535#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
8536#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
8537#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
8538#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
8539#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
8540#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
8542/* legacy defines */
8543#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
8544#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
8545#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
8546#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
8547#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
8548#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
8549#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
8550#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
8551#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
8552#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
8553#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
8554#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
8555#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
8556#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
8557#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
8558#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
8559#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
8560#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
8561#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
8562#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
8563#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
8564#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
8565#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
8566#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
8567#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
8568#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
8569#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
8570#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
8571#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
8572#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
8573#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
8574#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
8575#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
8576#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
8577#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
8578#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
8579#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
8580#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
8581#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
8582#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
8583#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
8584#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
8585#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
8586#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
8587#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
8588#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
8589#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
8590#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
8591#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
8592#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
8593#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
8594#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
8595#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
8596#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
8597#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
8598#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
8599#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
8600#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
8601#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
8602#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
8603#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
8604#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
8605#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
8606#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
8607#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
8608#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
8609#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
8610#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
8611#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
8612#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
8613#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
8614#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
8615#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
8616#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
8617#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
8618#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
8619#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
8620#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
8621#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
8622#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
8623
8624/****************** Bits definition for GPIO_PUPDR register *****************/
8625#define GPIO_PUPDR_PUPDR0_Pos (0U)
8626#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos)
8627#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
8628#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos)
8629#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos)
8630#define GPIO_PUPDR_PUPDR1_Pos (2U)
8631#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos)
8632#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
8633#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos)
8634#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos)
8635#define GPIO_PUPDR_PUPDR2_Pos (4U)
8636#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos)
8637#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
8638#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos)
8639#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos)
8640#define GPIO_PUPDR_PUPDR3_Pos (6U)
8641#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos)
8642#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
8643#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos)
8644#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos)
8645#define GPIO_PUPDR_PUPDR4_Pos (8U)
8646#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos)
8647#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
8648#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos)
8649#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos)
8650#define GPIO_PUPDR_PUPDR5_Pos (10U)
8651#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos)
8652#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
8653#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos)
8654#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos)
8655#define GPIO_PUPDR_PUPDR6_Pos (12U)
8656#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos)
8657#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
8658#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos)
8659#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos)
8660#define GPIO_PUPDR_PUPDR7_Pos (14U)
8661#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos)
8662#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
8663#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos)
8664#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos)
8665#define GPIO_PUPDR_PUPDR8_Pos (16U)
8666#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos)
8667#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
8668#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos)
8669#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos)
8670#define GPIO_PUPDR_PUPDR9_Pos (18U)
8671#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos)
8672#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
8673#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos)
8674#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos)
8675#define GPIO_PUPDR_PUPDR10_Pos (20U)
8676#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos)
8677#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
8678#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)
8679#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)
8680#define GPIO_PUPDR_PUPDR11_Pos (22U)
8681#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos)
8682#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
8683#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)
8684#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)
8685#define GPIO_PUPDR_PUPDR12_Pos (24U)
8686#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos)
8687#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
8688#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)
8689#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)
8690#define GPIO_PUPDR_PUPDR13_Pos (26U)
8691#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos)
8692#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
8693#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)
8694#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)
8695#define GPIO_PUPDR_PUPDR14_Pos (28U)
8696#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos)
8697#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
8698#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)
8699#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)
8700#define GPIO_PUPDR_PUPDR15_Pos (30U)
8701#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos)
8702#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
8703#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)
8704#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)
8706/****************** Bits definition for GPIO_IDR register *******************/
8707#define GPIO_IDR_ID0_Pos (0U)
8708#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
8709#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8710#define GPIO_IDR_ID1_Pos (1U)
8711#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
8712#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8713#define GPIO_IDR_ID2_Pos (2U)
8714#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
8715#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8716#define GPIO_IDR_ID3_Pos (3U)
8717#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
8718#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8719#define GPIO_IDR_ID4_Pos (4U)
8720#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
8721#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8722#define GPIO_IDR_ID5_Pos (5U)
8723#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
8724#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8725#define GPIO_IDR_ID6_Pos (6U)
8726#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
8727#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8728#define GPIO_IDR_ID7_Pos (7U)
8729#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
8730#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8731#define GPIO_IDR_ID8_Pos (8U)
8732#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
8733#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8734#define GPIO_IDR_ID9_Pos (9U)
8735#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
8736#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8737#define GPIO_IDR_ID10_Pos (10U)
8738#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
8739#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8740#define GPIO_IDR_ID11_Pos (11U)
8741#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
8742#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8743#define GPIO_IDR_ID12_Pos (12U)
8744#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
8745#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8746#define GPIO_IDR_ID13_Pos (13U)
8747#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
8748#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8749#define GPIO_IDR_ID14_Pos (14U)
8750#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
8751#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8752#define GPIO_IDR_ID15_Pos (15U)
8753#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
8754#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8755
8756/* Legacy defines */
8757#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8758#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8759#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8760#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8761#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8762#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8763#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8764#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8765#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8766#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8767#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8768#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8769#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8770#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8771#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8772#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8773
8774/****************** Bits definition for GPIO_ODR register *******************/
8775#define GPIO_ODR_OD0_Pos (0U)
8776#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
8777#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8778#define GPIO_ODR_OD1_Pos (1U)
8779#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
8780#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8781#define GPIO_ODR_OD2_Pos (2U)
8782#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
8783#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8784#define GPIO_ODR_OD3_Pos (3U)
8785#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
8786#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8787#define GPIO_ODR_OD4_Pos (4U)
8788#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
8789#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8790#define GPIO_ODR_OD5_Pos (5U)
8791#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
8792#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8793#define GPIO_ODR_OD6_Pos (6U)
8794#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
8795#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8796#define GPIO_ODR_OD7_Pos (7U)
8797#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
8798#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8799#define GPIO_ODR_OD8_Pos (8U)
8800#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
8801#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8802#define GPIO_ODR_OD9_Pos (9U)
8803#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
8804#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8805#define GPIO_ODR_OD10_Pos (10U)
8806#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
8807#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8808#define GPIO_ODR_OD11_Pos (11U)
8809#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
8810#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8811#define GPIO_ODR_OD12_Pos (12U)
8812#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
8813#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8814#define GPIO_ODR_OD13_Pos (13U)
8815#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
8816#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8817#define GPIO_ODR_OD14_Pos (14U)
8818#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
8819#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8820#define GPIO_ODR_OD15_Pos (15U)
8821#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
8822#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8823
8824/* Legacy defines */
8825#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8826#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8827#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8828#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8829#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8830#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8831#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8832#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8833#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8834#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8835#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8836#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8837#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8838#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8839#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8840#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8841
8842/****************** Bits definition for GPIO_BSRR register ******************/
8843#define GPIO_BSRR_BS0_Pos (0U)
8844#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
8845#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8846#define GPIO_BSRR_BS1_Pos (1U)
8847#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
8848#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8849#define GPIO_BSRR_BS2_Pos (2U)
8850#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
8851#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8852#define GPIO_BSRR_BS3_Pos (3U)
8853#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
8854#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8855#define GPIO_BSRR_BS4_Pos (4U)
8856#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
8857#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8858#define GPIO_BSRR_BS5_Pos (5U)
8859#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
8860#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8861#define GPIO_BSRR_BS6_Pos (6U)
8862#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
8863#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8864#define GPIO_BSRR_BS7_Pos (7U)
8865#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
8866#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8867#define GPIO_BSRR_BS8_Pos (8U)
8868#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
8869#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8870#define GPIO_BSRR_BS9_Pos (9U)
8871#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
8872#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8873#define GPIO_BSRR_BS10_Pos (10U)
8874#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
8875#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8876#define GPIO_BSRR_BS11_Pos (11U)
8877#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
8878#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8879#define GPIO_BSRR_BS12_Pos (12U)
8880#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
8881#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8882#define GPIO_BSRR_BS13_Pos (13U)
8883#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
8884#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8885#define GPIO_BSRR_BS14_Pos (14U)
8886#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
8887#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8888#define GPIO_BSRR_BS15_Pos (15U)
8889#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
8890#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8891#define GPIO_BSRR_BR0_Pos (16U)
8892#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
8893#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8894#define GPIO_BSRR_BR1_Pos (17U)
8895#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
8896#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8897#define GPIO_BSRR_BR2_Pos (18U)
8898#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
8899#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8900#define GPIO_BSRR_BR3_Pos (19U)
8901#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
8902#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8903#define GPIO_BSRR_BR4_Pos (20U)
8904#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8905#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8906#define GPIO_BSRR_BR5_Pos (21U)
8907#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8908#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8909#define GPIO_BSRR_BR6_Pos (22U)
8910#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8911#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8912#define GPIO_BSRR_BR7_Pos (23U)
8913#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8914#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8915#define GPIO_BSRR_BR8_Pos (24U)
8916#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8917#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8918#define GPIO_BSRR_BR9_Pos (25U)
8919#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8920#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8921#define GPIO_BSRR_BR10_Pos (26U)
8922#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8923#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8924#define GPIO_BSRR_BR11_Pos (27U)
8925#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8926#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8927#define GPIO_BSRR_BR12_Pos (28U)
8928#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8929#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8930#define GPIO_BSRR_BR13_Pos (29U)
8931#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8932#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8933#define GPIO_BSRR_BR14_Pos (30U)
8934#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8935#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8936#define GPIO_BSRR_BR15_Pos (31U)
8937#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8938#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8939
8940/* Legacy defines */
8941#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8942#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8943#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8944#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8945#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8946#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8947#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8948#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8949#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8950#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8951#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8952#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8953#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8954#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8955#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8956#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8957#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8958#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8959#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8960#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8961#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8962#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8963#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8964#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8965#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8966#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8967#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8968#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8969#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8970#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8971#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8972#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8973
8974/****************** Bit definition for GPIO_LCKR register *********************/
8975#define GPIO_LCKR_LCK0_Pos (0U)
8976#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8977#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8978#define GPIO_LCKR_LCK1_Pos (1U)
8979#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8980#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8981#define GPIO_LCKR_LCK2_Pos (2U)
8982#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8983#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8984#define GPIO_LCKR_LCK3_Pos (3U)
8985#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8986#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8987#define GPIO_LCKR_LCK4_Pos (4U)
8988#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8989#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8990#define GPIO_LCKR_LCK5_Pos (5U)
8991#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8992#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8993#define GPIO_LCKR_LCK6_Pos (6U)
8994#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8995#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8996#define GPIO_LCKR_LCK7_Pos (7U)
8997#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8998#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8999#define GPIO_LCKR_LCK8_Pos (8U)
9000#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
9001#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
9002#define GPIO_LCKR_LCK9_Pos (9U)
9003#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
9004#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
9005#define GPIO_LCKR_LCK10_Pos (10U)
9006#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
9007#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
9008#define GPIO_LCKR_LCK11_Pos (11U)
9009#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
9010#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
9011#define GPIO_LCKR_LCK12_Pos (12U)
9012#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
9013#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
9014#define GPIO_LCKR_LCK13_Pos (13U)
9015#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
9016#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
9017#define GPIO_LCKR_LCK14_Pos (14U)
9018#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
9019#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
9020#define GPIO_LCKR_LCK15_Pos (15U)
9021#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
9022#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
9023#define GPIO_LCKR_LCKK_Pos (16U)
9024#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
9025#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
9026
9027/****************** Bit definition for GPIO_AFRL register *********************/
9028#define GPIO_AFRL_AFRL0_Pos (0U)
9029#define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos)
9030#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
9031#define GPIO_AFRL_AFRL0_0 (0x1UL << GPIO_AFRL_AFRL0_Pos)
9032#define GPIO_AFRL_AFRL0_1 (0x2UL << GPIO_AFRL_AFRL0_Pos)
9033#define GPIO_AFRL_AFRL0_2 (0x4UL << GPIO_AFRL_AFRL0_Pos)
9034#define GPIO_AFRL_AFRL0_3 (0x8UL << GPIO_AFRL_AFRL0_Pos)
9035#define GPIO_AFRL_AFRL1_Pos (4U)
9036#define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos)
9037#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
9038#define GPIO_AFRL_AFRL1_0 (0x1UL << GPIO_AFRL_AFRL1_Pos)
9039#define GPIO_AFRL_AFRL1_1 (0x2UL << GPIO_AFRL_AFRL1_Pos)
9040#define GPIO_AFRL_AFRL1_2 (0x4UL << GPIO_AFRL_AFRL1_Pos)
9041#define GPIO_AFRL_AFRL1_3 (0x8UL << GPIO_AFRL_AFRL1_Pos)
9042#define GPIO_AFRL_AFRL2_Pos (8U)
9043#define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos)
9044#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
9045#define GPIO_AFRL_AFRL2_0 (0x1UL << GPIO_AFRL_AFRL2_Pos)
9046#define GPIO_AFRL_AFRL2_1 (0x2UL << GPIO_AFRL_AFRL2_Pos)
9047#define GPIO_AFRL_AFRL2_2 (0x4UL << GPIO_AFRL_AFRL2_Pos)
9048#define GPIO_AFRL_AFRL2_3 (0x8UL << GPIO_AFRL_AFRL2_Pos)
9049#define GPIO_AFRL_AFRL3_Pos (12U)
9050#define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos)
9051#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
9052#define GPIO_AFRL_AFRL3_0 (0x1UL << GPIO_AFRL_AFRL3_Pos)
9053#define GPIO_AFRL_AFRL3_1 (0x2UL << GPIO_AFRL_AFRL3_Pos)
9054#define GPIO_AFRL_AFRL3_2 (0x4UL << GPIO_AFRL_AFRL3_Pos)
9055#define GPIO_AFRL_AFRL3_3 (0x8UL << GPIO_AFRL_AFRL3_Pos)
9056#define GPIO_AFRL_AFRL4_Pos (16U)
9057#define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos)
9058#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
9059#define GPIO_AFRL_AFRL4_0 (0x1UL << GPIO_AFRL_AFRL4_Pos)
9060#define GPIO_AFRL_AFRL4_1 (0x2UL << GPIO_AFRL_AFRL4_Pos)
9061#define GPIO_AFRL_AFRL4_2 (0x4UL << GPIO_AFRL_AFRL4_Pos)
9062#define GPIO_AFRL_AFRL4_3 (0x8UL << GPIO_AFRL_AFRL4_Pos)
9063#define GPIO_AFRL_AFRL5_Pos (20U)
9064#define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos)
9065#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
9066#define GPIO_AFRL_AFRL5_0 (0x1UL << GPIO_AFRL_AFRL5_Pos)
9067#define GPIO_AFRL_AFRL5_1 (0x2UL << GPIO_AFRL_AFRL5_Pos)
9068#define GPIO_AFRL_AFRL5_2 (0x4UL << GPIO_AFRL_AFRL5_Pos)
9069#define GPIO_AFRL_AFRL5_3 (0x8UL << GPIO_AFRL_AFRL5_Pos)
9070#define GPIO_AFRL_AFRL6_Pos (24U)
9071#define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos)
9072#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
9073#define GPIO_AFRL_AFRL6_0 (0x1UL << GPIO_AFRL_AFRL6_Pos)
9074#define GPIO_AFRL_AFRL6_1 (0x2UL << GPIO_AFRL_AFRL6_Pos)
9075#define GPIO_AFRL_AFRL6_2 (0x4UL << GPIO_AFRL_AFRL6_Pos)
9076#define GPIO_AFRL_AFRL6_3 (0x8UL << GPIO_AFRL_AFRL6_Pos)
9077#define GPIO_AFRL_AFRL7_Pos (28U)
9078#define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos)
9079#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
9080#define GPIO_AFRL_AFRL7_0 (0x1UL << GPIO_AFRL_AFRL7_Pos)
9081#define GPIO_AFRL_AFRL7_1 (0x2UL << GPIO_AFRL_AFRL7_Pos)
9082#define GPIO_AFRL_AFRL7_2 (0x4UL << GPIO_AFRL_AFRL7_Pos)
9083#define GPIO_AFRL_AFRL7_3 (0x8UL << GPIO_AFRL_AFRL7_Pos)
9085/****************** Bit definition for GPIO_AFRH register *********************/
9086#define GPIO_AFRH_AFRH0_Pos (0U)
9087#define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos)
9088#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
9089#define GPIO_AFRH_AFRH0_0 (0x1UL << GPIO_AFRH_AFRH0_Pos)
9090#define GPIO_AFRH_AFRH0_1 (0x2UL << GPIO_AFRH_AFRH0_Pos)
9091#define GPIO_AFRH_AFRH0_2 (0x4UL << GPIO_AFRH_AFRH0_Pos)
9092#define GPIO_AFRH_AFRH0_3 (0x8UL << GPIO_AFRH_AFRH0_Pos)
9093#define GPIO_AFRH_AFRH1_Pos (4U)
9094#define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos)
9095#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
9096#define GPIO_AFRH_AFRH1_0 (0x1UL << GPIO_AFRH_AFRH1_Pos)
9097#define GPIO_AFRH_AFRH1_1 (0x2UL << GPIO_AFRH_AFRH1_Pos)
9098#define GPIO_AFRH_AFRH1_2 (0x4UL << GPIO_AFRH_AFRH1_Pos)
9099#define GPIO_AFRH_AFRH1_3 (0x8UL << GPIO_AFRH_AFRH1_Pos)
9100#define GPIO_AFRH_AFRH2_Pos (8U)
9101#define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos)
9102#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
9103#define GPIO_AFRH_AFRH2_0 (0x1UL << GPIO_AFRH_AFRH2_Pos)
9104#define GPIO_AFRH_AFRH2_1 (0x2UL << GPIO_AFRH_AFRH2_Pos)
9105#define GPIO_AFRH_AFRH2_2 (0x4UL << GPIO_AFRH_AFRH2_Pos)
9106#define GPIO_AFRH_AFRH2_3 (0x8UL << GPIO_AFRH_AFRH2_Pos)
9107#define GPIO_AFRH_AFRH3_Pos (12U)
9108#define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos)
9109#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
9110#define GPIO_AFRH_AFRH3_0 (0x1UL << GPIO_AFRH_AFRH3_Pos)
9111#define GPIO_AFRH_AFRH3_1 (0x2UL << GPIO_AFRH_AFRH3_Pos)
9112#define GPIO_AFRH_AFRH3_2 (0x4UL << GPIO_AFRH_AFRH3_Pos)
9113#define GPIO_AFRH_AFRH3_3 (0x8UL << GPIO_AFRH_AFRH3_Pos)
9114#define GPIO_AFRH_AFRH4_Pos (16U)
9115#define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos)
9116#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
9117#define GPIO_AFRH_AFRH4_0 (0x1UL << GPIO_AFRH_AFRH4_Pos)
9118#define GPIO_AFRH_AFRH4_1 (0x2UL << GPIO_AFRH_AFRH4_Pos)
9119#define GPIO_AFRH_AFRH4_2 (0x4UL << GPIO_AFRH_AFRH4_Pos)
9120#define GPIO_AFRH_AFRH4_3 (0x8UL << GPIO_AFRH_AFRH4_Pos)
9121#define GPIO_AFRH_AFRH5_Pos (20U)
9122#define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos)
9123#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
9124#define GPIO_AFRH_AFRH5_0 (0x1UL << GPIO_AFRH_AFRH5_Pos)
9125#define GPIO_AFRH_AFRH5_1 (0x2UL << GPIO_AFRH_AFRH5_Pos)
9126#define GPIO_AFRH_AFRH5_2 (0x4UL << GPIO_AFRH_AFRH5_Pos)
9127#define GPIO_AFRH_AFRH5_3 (0x8UL << GPIO_AFRH_AFRH5_Pos)
9128#define GPIO_AFRH_AFRH6_Pos (24U)
9129#define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos)
9130#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
9131#define GPIO_AFRH_AFRH6_0 (0x1UL << GPIO_AFRH_AFRH6_Pos)
9132#define GPIO_AFRH_AFRH6_1 (0x2UL << GPIO_AFRH_AFRH6_Pos)
9133#define GPIO_AFRH_AFRH6_2 (0x4UL << GPIO_AFRH_AFRH6_Pos)
9134#define GPIO_AFRH_AFRH6_3 (0x8UL << GPIO_AFRH_AFRH6_Pos)
9135#define GPIO_AFRH_AFRH7_Pos (28U)
9136#define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos)
9137#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
9138#define GPIO_AFRH_AFRH7_0 (0x1UL << GPIO_AFRH_AFRH7_Pos)
9139#define GPIO_AFRH_AFRH7_1 (0x2UL << GPIO_AFRH_AFRH7_Pos)
9140#define GPIO_AFRH_AFRH7_2 (0x4UL << GPIO_AFRH_AFRH7_Pos)
9141#define GPIO_AFRH_AFRH7_3 (0x8UL << GPIO_AFRH_AFRH7_Pos)
9144/******************************************************************************/
9145/* */
9146/* Inter-integrated Circuit Interface (I2C) */
9147/* */
9148/******************************************************************************/
9149/******************* Bit definition for I2C_CR1 register *******************/
9150#define I2C_CR1_PE_Pos (0U)
9151#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
9152#define I2C_CR1_PE I2C_CR1_PE_Msk
9153#define I2C_CR1_TXIE_Pos (1U)
9154#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
9155#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
9156#define I2C_CR1_RXIE_Pos (2U)
9157#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
9158#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
9159#define I2C_CR1_ADDRIE_Pos (3U)
9160#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
9161#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
9162#define I2C_CR1_NACKIE_Pos (4U)
9163#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
9164#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
9165#define I2C_CR1_STOPIE_Pos (5U)
9166#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
9167#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
9168#define I2C_CR1_TCIE_Pos (6U)
9169#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
9170#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
9171#define I2C_CR1_ERRIE_Pos (7U)
9172#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
9173#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
9174#define I2C_CR1_DNF_Pos (8U)
9175#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
9176#define I2C_CR1_DNF I2C_CR1_DNF_Msk
9177#define I2C_CR1_ANFOFF_Pos (12U)
9178#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
9179#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
9180#define I2C_CR1_TXDMAEN_Pos (14U)
9181#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
9182#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
9183#define I2C_CR1_RXDMAEN_Pos (15U)
9184#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
9185#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
9186#define I2C_CR1_SBC_Pos (16U)
9187#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
9188#define I2C_CR1_SBC I2C_CR1_SBC_Msk
9189#define I2C_CR1_NOSTRETCH_Pos (17U)
9190#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
9191#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
9192#define I2C_CR1_GCEN_Pos (19U)
9193#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
9194#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
9195#define I2C_CR1_SMBHEN_Pos (20U)
9196#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
9197#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
9198#define I2C_CR1_SMBDEN_Pos (21U)
9199#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
9200#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
9201#define I2C_CR1_ALERTEN_Pos (22U)
9202#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
9203#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
9204#define I2C_CR1_PECEN_Pos (23U)
9205#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
9206#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
9208/* Legacy define */
9209#define I2C_CR1_DFN I2C_CR1_DNF
9211/****************** Bit definition for I2C_CR2 register ********************/
9212#define I2C_CR2_SADD_Pos (0U)
9213#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
9214#define I2C_CR2_SADD I2C_CR2_SADD_Msk
9215#define I2C_CR2_RD_WRN_Pos (10U)
9216#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
9217#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
9218#define I2C_CR2_ADD10_Pos (11U)
9219#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
9220#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
9221#define I2C_CR2_HEAD10R_Pos (12U)
9222#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
9223#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
9224#define I2C_CR2_START_Pos (13U)
9225#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
9226#define I2C_CR2_START I2C_CR2_START_Msk
9227#define I2C_CR2_STOP_Pos (14U)
9228#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
9229#define I2C_CR2_STOP I2C_CR2_STOP_Msk
9230#define I2C_CR2_NACK_Pos (15U)
9231#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
9232#define I2C_CR2_NACK I2C_CR2_NACK_Msk
9233#define I2C_CR2_NBYTES_Pos (16U)
9234#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
9235#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
9236#define I2C_CR2_RELOAD_Pos (24U)
9237#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
9238#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
9239#define I2C_CR2_AUTOEND_Pos (25U)
9240#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
9241#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
9242#define I2C_CR2_PECBYTE_Pos (26U)
9243#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
9244#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
9246/******************* Bit definition for I2C_OAR1 register ******************/
9247#define I2C_OAR1_OA1_Pos (0U)
9248#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
9249#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
9250#define I2C_OAR1_OA1MODE_Pos (10U)
9251#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
9252#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
9253#define I2C_OAR1_OA1EN_Pos (15U)
9254#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
9255#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
9257/******************* Bit definition for I2C_OAR2 register ******************/
9258#define I2C_OAR2_OA2_Pos (1U)
9259#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
9260#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
9261#define I2C_OAR2_OA2MSK_Pos (8U)
9262#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
9263#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
9264#define I2C_OAR2_OA2NOMASK 0x00000000U
9265#define I2C_OAR2_OA2MASK01_Pos (8U)
9266#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
9267#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
9268#define I2C_OAR2_OA2MASK02_Pos (9U)
9269#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
9270#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
9271#define I2C_OAR2_OA2MASK03_Pos (8U)
9272#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
9273#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
9274#define I2C_OAR2_OA2MASK04_Pos (10U)
9275#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
9276#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
9277#define I2C_OAR2_OA2MASK05_Pos (8U)
9278#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
9279#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
9280#define I2C_OAR2_OA2MASK06_Pos (9U)
9281#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
9282#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
9283#define I2C_OAR2_OA2MASK07_Pos (8U)
9284#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
9285#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
9286#define I2C_OAR2_OA2EN_Pos (15U)
9287#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
9288#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
9290/******************* Bit definition for I2C_TIMINGR register *******************/
9291#define I2C_TIMINGR_SCLL_Pos (0U)
9292#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
9293#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
9294#define I2C_TIMINGR_SCLH_Pos (8U)
9295#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
9296#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
9297#define I2C_TIMINGR_SDADEL_Pos (16U)
9298#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
9299#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
9300#define I2C_TIMINGR_SCLDEL_Pos (20U)
9301#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
9302#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
9303#define I2C_TIMINGR_PRESC_Pos (28U)
9304#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
9305#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
9307/******************* Bit definition for I2C_TIMEOUTR register *******************/
9308#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9309#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
9310#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
9311#define I2C_TIMEOUTR_TIDLE_Pos (12U)
9312#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
9313#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
9314#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9315#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
9316#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
9317#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9318#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
9319#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
9320#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
9321#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
9322#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
9324/****************** Bit definition for I2C_ISR register *********************/
9325#define I2C_ISR_TXE_Pos (0U)
9326#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
9327#define I2C_ISR_TXE I2C_ISR_TXE_Msk
9328#define I2C_ISR_TXIS_Pos (1U)
9329#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
9330#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
9331#define I2C_ISR_RXNE_Pos (2U)
9332#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
9333#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
9334#define I2C_ISR_ADDR_Pos (3U)
9335#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
9336#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
9337#define I2C_ISR_NACKF_Pos (4U)
9338#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
9339#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
9340#define I2C_ISR_STOPF_Pos (5U)
9341#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
9342#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
9343#define I2C_ISR_TC_Pos (6U)
9344#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
9345#define I2C_ISR_TC I2C_ISR_TC_Msk
9346#define I2C_ISR_TCR_Pos (7U)
9347#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
9348#define I2C_ISR_TCR I2C_ISR_TCR_Msk
9349#define I2C_ISR_BERR_Pos (8U)
9350#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
9351#define I2C_ISR_BERR I2C_ISR_BERR_Msk
9352#define I2C_ISR_ARLO_Pos (9U)
9353#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
9354#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
9355#define I2C_ISR_OVR_Pos (10U)
9356#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
9357#define I2C_ISR_OVR I2C_ISR_OVR_Msk
9358#define I2C_ISR_PECERR_Pos (11U)
9359#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
9360#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
9361#define I2C_ISR_TIMEOUT_Pos (12U)
9362#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
9363#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
9364#define I2C_ISR_ALERT_Pos (13U)
9365#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
9366#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
9367#define I2C_ISR_BUSY_Pos (15U)
9368#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
9369#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
9370#define I2C_ISR_DIR_Pos (16U)
9371#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
9372#define I2C_ISR_DIR I2C_ISR_DIR_Msk
9373#define I2C_ISR_ADDCODE_Pos (17U)
9374#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
9375#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
9377/****************** Bit definition for I2C_ICR register *********************/
9378#define I2C_ICR_ADDRCF_Pos (3U)
9379#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
9380#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
9381#define I2C_ICR_NACKCF_Pos (4U)
9382#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
9383#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
9384#define I2C_ICR_STOPCF_Pos (5U)
9385#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
9386#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
9387#define I2C_ICR_BERRCF_Pos (8U)
9388#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
9389#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
9390#define I2C_ICR_ARLOCF_Pos (9U)
9391#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
9392#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
9393#define I2C_ICR_OVRCF_Pos (10U)
9394#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
9395#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
9396#define I2C_ICR_PECCF_Pos (11U)
9397#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
9398#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
9399#define I2C_ICR_TIMOUTCF_Pos (12U)
9400#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
9401#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
9402#define I2C_ICR_ALERTCF_Pos (13U)
9403#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
9404#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
9406/****************** Bit definition for I2C_PECR register *********************/
9407#define I2C_PECR_PEC_Pos (0U)
9408#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
9409#define I2C_PECR_PEC I2C_PECR_PEC_Msk
9411/****************** Bit definition for I2C_RXDR register *********************/
9412#define I2C_RXDR_RXDATA_Pos (0U)
9413#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
9414#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
9416/****************** Bit definition for I2C_TXDR register *********************/
9417#define I2C_TXDR_TXDATA_Pos (0U)
9418#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
9419#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
9422/******************************************************************************/
9423/* */
9424/* Independent WATCHDOG */
9425/* */
9426/******************************************************************************/
9427/******************* Bit definition for IWDG_KR register ********************/
9428#define IWDG_KR_KEY_Pos (0U)
9429#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
9430#define IWDG_KR_KEY IWDG_KR_KEY_Msk
9432/******************* Bit definition for IWDG_PR register ********************/
9433#define IWDG_PR_PR_Pos (0U)
9434#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
9435#define IWDG_PR_PR IWDG_PR_PR_Msk
9436#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
9437#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
9438#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
9440/******************* Bit definition for IWDG_RLR register *******************/
9441#define IWDG_RLR_RL_Pos (0U)
9442#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
9443#define IWDG_RLR_RL IWDG_RLR_RL_Msk
9445/******************* Bit definition for IWDG_SR register ********************/
9446#define IWDG_SR_PVU_Pos (0U)
9447#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
9448#define IWDG_SR_PVU IWDG_SR_PVU_Msk
9449#define IWDG_SR_RVU_Pos (1U)
9450#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
9451#define IWDG_SR_RVU IWDG_SR_RVU_Msk
9452#define IWDG_SR_WVU_Pos (2U)
9453#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
9454#define IWDG_SR_WVU IWDG_SR_WVU_Msk
9456/******************* Bit definition for IWDG_KR register ********************/
9457#define IWDG_WINR_WIN_Pos (0U)
9458#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
9459#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
9462/******************************************************************************/
9463/* */
9464/* Power Control */
9465/* */
9466/******************************************************************************/
9467/******************** Bit definition for PWR_CR1 register ********************/
9468#define PWR_CR1_LPDS_Pos (0U)
9469#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos)
9470#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk
9471#define PWR_CR1_PDDS_Pos (1U)
9472#define PWR_CR1_PDDS_Msk (0x1UL << PWR_CR1_PDDS_Pos)
9473#define PWR_CR1_PDDS PWR_CR1_PDDS_Msk
9474#define PWR_CR1_CSBF_Pos (3U)
9475#define PWR_CR1_CSBF_Msk (0x1UL << PWR_CR1_CSBF_Pos)
9476#define PWR_CR1_CSBF PWR_CR1_CSBF_Msk
9477#define PWR_CR1_PVDE_Pos (4U)
9478#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos)
9479#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk
9480#define PWR_CR1_PLS_Pos (5U)
9481#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos)
9482#define PWR_CR1_PLS PWR_CR1_PLS_Msk
9483#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos)
9484#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos)
9485#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos)
9488#define PWR_CR1_PLS_LEV0 0x00000000U
9489#define PWR_CR1_PLS_LEV1_Pos (5U)
9490#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos)
9491#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk
9492#define PWR_CR1_PLS_LEV2_Pos (6U)
9493#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos)
9494#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk
9495#define PWR_CR1_PLS_LEV3_Pos (5U)
9496#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos)
9497#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk
9498#define PWR_CR1_PLS_LEV4_Pos (7U)
9499#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos)
9500#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk
9501#define PWR_CR1_PLS_LEV5_Pos (5U)
9502#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos)
9503#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk
9504#define PWR_CR1_PLS_LEV6_Pos (6U)
9505#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos)
9506#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk
9507#define PWR_CR1_PLS_LEV7_Pos (5U)
9508#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos)
9509#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk
9510#define PWR_CR1_DBP_Pos (8U)
9511#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
9512#define PWR_CR1_DBP PWR_CR1_DBP_Msk
9513#define PWR_CR1_FPDS_Pos (9U)
9514#define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos)
9515#define PWR_CR1_FPDS PWR_CR1_FPDS_Msk
9516#define PWR_CR1_LPUDS_Pos (10U)
9517#define PWR_CR1_LPUDS_Msk (0x1UL << PWR_CR1_LPUDS_Pos)
9518#define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk
9519#define PWR_CR1_MRUDS_Pos (11U)
9520#define PWR_CR1_MRUDS_Msk (0x1UL << PWR_CR1_MRUDS_Pos)
9521#define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk
9522#define PWR_CR1_ADCDC1_Pos (13U)
9523#define PWR_CR1_ADCDC1_Msk (0x1UL << PWR_CR1_ADCDC1_Pos)
9524#define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk
9525#define PWR_CR1_VOS_Pos (14U)
9526#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)
9527#define PWR_CR1_VOS PWR_CR1_VOS_Msk
9528#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)
9529#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)
9530#define PWR_CR1_ODEN_Pos (16U)
9531#define PWR_CR1_ODEN_Msk (0x1UL << PWR_CR1_ODEN_Pos)
9532#define PWR_CR1_ODEN PWR_CR1_ODEN_Msk
9533#define PWR_CR1_ODSWEN_Pos (17U)
9534#define PWR_CR1_ODSWEN_Msk (0x1UL << PWR_CR1_ODSWEN_Pos)
9535#define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk
9536#define PWR_CR1_UDEN_Pos (18U)
9537#define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos)
9538#define PWR_CR1_UDEN PWR_CR1_UDEN_Msk
9539#define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos)
9540#define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos)
9542/******************* Bit definition for PWR_CSR1 register ********************/
9543#define PWR_CSR1_WUIF_Pos (0U)
9544#define PWR_CSR1_WUIF_Msk (0x1UL << PWR_CSR1_WUIF_Pos)
9545#define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk
9546#define PWR_CSR1_SBF_Pos (1U)
9547#define PWR_CSR1_SBF_Msk (0x1UL << PWR_CSR1_SBF_Pos)
9548#define PWR_CSR1_SBF PWR_CSR1_SBF_Msk
9549#define PWR_CSR1_PVDO_Pos (2U)
9550#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos)
9551#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk
9552#define PWR_CSR1_BRR_Pos (3U)
9553#define PWR_CSR1_BRR_Msk (0x1UL << PWR_CSR1_BRR_Pos)
9554#define PWR_CSR1_BRR PWR_CSR1_BRR_Msk
9555#define PWR_CSR1_EIWUP_Pos (8U)
9556#define PWR_CSR1_EIWUP_Msk (0x1UL << PWR_CSR1_EIWUP_Pos)
9557#define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk
9558#define PWR_CSR1_BRE_Pos (9U)
9559#define PWR_CSR1_BRE_Msk (0x1UL << PWR_CSR1_BRE_Pos)
9560#define PWR_CSR1_BRE PWR_CSR1_BRE_Msk
9561#define PWR_CSR1_VOSRDY_Pos (14U)
9562#define PWR_CSR1_VOSRDY_Msk (0x1UL << PWR_CSR1_VOSRDY_Pos)
9563#define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk
9564#define PWR_CSR1_ODRDY_Pos (16U)
9565#define PWR_CSR1_ODRDY_Msk (0x1UL << PWR_CSR1_ODRDY_Pos)
9566#define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk
9567#define PWR_CSR1_ODSWRDY_Pos (17U)
9568#define PWR_CSR1_ODSWRDY_Msk (0x1UL << PWR_CSR1_ODSWRDY_Pos)
9569#define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk
9570#define PWR_CSR1_UDRDY_Pos (18U)
9571#define PWR_CSR1_UDRDY_Msk (0x3UL << PWR_CSR1_UDRDY_Pos)
9572#define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk
9574/* Legacy define */
9575#define PWR_CSR1_UDSWRDY PWR_CSR1_UDRDY
9576
9577/******************** Bit definition for PWR_CR2 register ********************/
9578#define PWR_CR2_CWUPF1_Pos (0U)
9579#define PWR_CR2_CWUPF1_Msk (0x1UL << PWR_CR2_CWUPF1_Pos)
9580#define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk
9581#define PWR_CR2_CWUPF2_Pos (1U)
9582#define PWR_CR2_CWUPF2_Msk (0x1UL << PWR_CR2_CWUPF2_Pos)
9583#define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk
9584#define PWR_CR2_CWUPF3_Pos (2U)
9585#define PWR_CR2_CWUPF3_Msk (0x1UL << PWR_CR2_CWUPF3_Pos)
9586#define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk
9587#define PWR_CR2_CWUPF4_Pos (3U)
9588#define PWR_CR2_CWUPF4_Msk (0x1UL << PWR_CR2_CWUPF4_Pos)
9589#define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk
9590#define PWR_CR2_CWUPF5_Pos (4U)
9591#define PWR_CR2_CWUPF5_Msk (0x1UL << PWR_CR2_CWUPF5_Pos)
9592#define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk
9593#define PWR_CR2_CWUPF6_Pos (5U)
9594#define PWR_CR2_CWUPF6_Msk (0x1UL << PWR_CR2_CWUPF6_Pos)
9595#define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk
9596#define PWR_CR2_WUPP1_Pos (8U)
9597#define PWR_CR2_WUPP1_Msk (0x1UL << PWR_CR2_WUPP1_Pos)
9598#define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk
9599#define PWR_CR2_WUPP2_Pos (9U)
9600#define PWR_CR2_WUPP2_Msk (0x1UL << PWR_CR2_WUPP2_Pos)
9601#define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk
9602#define PWR_CR2_WUPP3_Pos (10U)
9603#define PWR_CR2_WUPP3_Msk (0x1UL << PWR_CR2_WUPP3_Pos)
9604#define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk
9605#define PWR_CR2_WUPP4_Pos (11U)
9606#define PWR_CR2_WUPP4_Msk (0x1UL << PWR_CR2_WUPP4_Pos)
9607#define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk
9608#define PWR_CR2_WUPP5_Pos (12U)
9609#define PWR_CR2_WUPP5_Msk (0x1UL << PWR_CR2_WUPP5_Pos)
9610#define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk
9611#define PWR_CR2_WUPP6_Pos (13U)
9612#define PWR_CR2_WUPP6_Msk (0x1UL << PWR_CR2_WUPP6_Pos)
9613#define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk
9615/******************* Bit definition for PWR_CSR2 register ********************/
9616#define PWR_CSR2_WUPF1_Pos (0U)
9617#define PWR_CSR2_WUPF1_Msk (0x1UL << PWR_CSR2_WUPF1_Pos)
9618#define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk
9619#define PWR_CSR2_WUPF2_Pos (1U)
9620#define PWR_CSR2_WUPF2_Msk (0x1UL << PWR_CSR2_WUPF2_Pos)
9621#define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk
9622#define PWR_CSR2_WUPF3_Pos (2U)
9623#define PWR_CSR2_WUPF3_Msk (0x1UL << PWR_CSR2_WUPF3_Pos)
9624#define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk
9625#define PWR_CSR2_WUPF4_Pos (3U)
9626#define PWR_CSR2_WUPF4_Msk (0x1UL << PWR_CSR2_WUPF4_Pos)
9627#define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk
9628#define PWR_CSR2_WUPF5_Pos (4U)
9629#define PWR_CSR2_WUPF5_Msk (0x1UL << PWR_CSR2_WUPF5_Pos)
9630#define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk
9631#define PWR_CSR2_WUPF6_Pos (5U)
9632#define PWR_CSR2_WUPF6_Msk (0x1UL << PWR_CSR2_WUPF6_Pos)
9633#define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk
9634#define PWR_CSR2_EWUP1_Pos (8U)
9635#define PWR_CSR2_EWUP1_Msk (0x1UL << PWR_CSR2_EWUP1_Pos)
9636#define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk
9637#define PWR_CSR2_EWUP2_Pos (9U)
9638#define PWR_CSR2_EWUP2_Msk (0x1UL << PWR_CSR2_EWUP2_Pos)
9639#define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk
9640#define PWR_CSR2_EWUP3_Pos (10U)
9641#define PWR_CSR2_EWUP3_Msk (0x1UL << PWR_CSR2_EWUP3_Pos)
9642#define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk
9643#define PWR_CSR2_EWUP4_Pos (11U)
9644#define PWR_CSR2_EWUP4_Msk (0x1UL << PWR_CSR2_EWUP4_Pos)
9645#define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk
9646#define PWR_CSR2_EWUP5_Pos (12U)
9647#define PWR_CSR2_EWUP5_Msk (0x1UL << PWR_CSR2_EWUP5_Pos)
9648#define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk
9649#define PWR_CSR2_EWUP6_Pos (13U)
9650#define PWR_CSR2_EWUP6_Msk (0x1UL << PWR_CSR2_EWUP6_Pos)
9651#define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk
9653/******************************************************************************/
9654/* */
9655/* QUADSPI */
9656/* */
9657/******************************************************************************/
9658/* QUADSPI IP version */
9659#define QSPI1_V1_0
9660/***************** Bit definition for QUADSPI_CR register *******************/
9661#define QUADSPI_CR_EN_Pos (0U)
9662#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
9663#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
9664#define QUADSPI_CR_ABORT_Pos (1U)
9665#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
9666#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
9667#define QUADSPI_CR_DMAEN_Pos (2U)
9668#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
9669#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
9670#define QUADSPI_CR_TCEN_Pos (3U)
9671#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
9672#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
9673#define QUADSPI_CR_SSHIFT_Pos (4U)
9674#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
9675#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
9676#define QUADSPI_CR_DFM_Pos (6U)
9677#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
9678#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
9679#define QUADSPI_CR_FSEL_Pos (7U)
9680#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
9681#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
9682#define QUADSPI_CR_FTHRES_Pos (8U)
9683#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
9684#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
9685#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos)
9686#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos)
9687#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos)
9688#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos)
9689#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
9690#define QUADSPI_CR_TEIE_Pos (16U)
9691#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
9692#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
9693#define QUADSPI_CR_TCIE_Pos (17U)
9694#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
9695#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
9696#define QUADSPI_CR_FTIE_Pos (18U)
9697#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
9698#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
9699#define QUADSPI_CR_SMIE_Pos (19U)
9700#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
9701#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
9702#define QUADSPI_CR_TOIE_Pos (20U)
9703#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
9704#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
9705#define QUADSPI_CR_APMS_Pos (22U)
9706#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
9707#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
9708#define QUADSPI_CR_PMM_Pos (23U)
9709#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
9710#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
9711#define QUADSPI_CR_PRESCALER_Pos (24U)
9712#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
9713#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
9714#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
9715#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
9716#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
9717#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
9718#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
9719#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
9720#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
9721#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
9723/***************** Bit definition for QUADSPI_DCR register ******************/
9724#define QUADSPI_DCR_CKMODE_Pos (0U)
9725#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
9726#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
9727#define QUADSPI_DCR_CSHT_Pos (8U)
9728#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
9729#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
9730#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
9731#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
9732#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
9733#define QUADSPI_DCR_FSIZE_Pos (16U)
9734#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
9735#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
9736#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
9737#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
9738#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
9739#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
9740#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
9742/****************** Bit definition for QUADSPI_SR register *******************/
9743#define QUADSPI_SR_TEF_Pos (0U)
9744#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
9745#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
9746#define QUADSPI_SR_TCF_Pos (1U)
9747#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
9748#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
9749#define QUADSPI_SR_FTF_Pos (2U)
9750#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
9751#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
9752#define QUADSPI_SR_SMF_Pos (3U)
9753#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
9754#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
9755#define QUADSPI_SR_TOF_Pos (4U)
9756#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
9757#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
9758#define QUADSPI_SR_BUSY_Pos (5U)
9759#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
9760#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
9761#define QUADSPI_SR_FLEVEL_Pos (8U)
9762#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
9763#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
9764#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
9765#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
9766#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
9767#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
9768#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
9769#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
9771/****************** Bit definition for QUADSPI_FCR register ******************/
9772#define QUADSPI_FCR_CTEF_Pos (0U)
9773#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
9774#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
9775#define QUADSPI_FCR_CTCF_Pos (1U)
9776#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
9777#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
9778#define QUADSPI_FCR_CSMF_Pos (3U)
9779#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
9780#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
9781#define QUADSPI_FCR_CTOF_Pos (4U)
9782#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
9783#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
9785/****************** Bit definition for QUADSPI_DLR register ******************/
9786#define QUADSPI_DLR_DL_Pos (0U)
9787#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
9788#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
9790/****************** Bit definition for QUADSPI_CCR register ******************/
9791#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
9792#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
9793#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
9794#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
9795#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
9796#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
9797#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
9798#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
9799#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
9800#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
9801#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
9802#define QUADSPI_CCR_IMODE_Pos (8U)
9803#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
9804#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
9805#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
9806#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
9807#define QUADSPI_CCR_ADMODE_Pos (10U)
9808#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
9809#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
9810#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
9811#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
9812#define QUADSPI_CCR_ADSIZE_Pos (12U)
9813#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
9814#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
9815#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
9816#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
9817#define QUADSPI_CCR_ABMODE_Pos (14U)
9818#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
9819#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
9820#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
9821#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
9822#define QUADSPI_CCR_ABSIZE_Pos (16U)
9823#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
9824#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
9825#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
9826#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
9827#define QUADSPI_CCR_DCYC_Pos (18U)
9828#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
9829#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
9830#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
9831#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
9832#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
9833#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
9834#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
9835#define QUADSPI_CCR_DMODE_Pos (24U)
9836#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
9837#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
9838#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
9839#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
9840#define QUADSPI_CCR_FMODE_Pos (26U)
9841#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
9842#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
9843#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
9844#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
9845#define QUADSPI_CCR_SIOO_Pos (28U)
9846#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
9847#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
9848#define QUADSPI_CCR_DHHC_Pos (30U)
9849#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
9850#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
9851#define QUADSPI_CCR_DDRM_Pos (31U)
9852#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
9853#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
9854/****************** Bit definition for QUADSPI_AR register *******************/
9855#define QUADSPI_AR_ADDRESS_Pos (0U)
9856#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
9857#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
9859/****************** Bit definition for QUADSPI_ABR register ******************/
9860#define QUADSPI_ABR_ALTERNATE_Pos (0U)
9861#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
9862#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
9864/****************** Bit definition for QUADSPI_DR register *******************/
9865#define QUADSPI_DR_DATA_Pos (0U)
9866#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
9867#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
9869/****************** Bit definition for QUADSPI_PSMKR register ****************/
9870#define QUADSPI_PSMKR_MASK_Pos (0U)
9871#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
9872#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
9874/****************** Bit definition for QUADSPI_PSMAR register ****************/
9875#define QUADSPI_PSMAR_MATCH_Pos (0U)
9876#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
9877#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
9879/****************** Bit definition for QUADSPI_PIR register *****************/
9880#define QUADSPI_PIR_INTERVAL_Pos (0U)
9881#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
9882#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
9884/****************** Bit definition for QUADSPI_LPTR register *****************/
9885#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
9886#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
9887#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
9889/******************************************************************************/
9890/* */
9891/* Reset and Clock Control */
9892/* */
9893/******************************************************************************/
9894/******************** Bit definition for RCC_CR register ********************/
9895#define RCC_CR_HSION_Pos (0U)
9896#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
9897#define RCC_CR_HSION RCC_CR_HSION_Msk
9898#define RCC_CR_HSIRDY_Pos (1U)
9899#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
9900#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9901#define RCC_CR_HSITRIM_Pos (3U)
9902#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
9903#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9904#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
9905#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
9906#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
9907#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
9908#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
9909#define RCC_CR_HSICAL_Pos (8U)
9910#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
9911#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9912#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
9913#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
9914#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
9915#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
9916#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
9917#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
9918#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
9919#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
9920#define RCC_CR_HSEON_Pos (16U)
9921#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
9922#define RCC_CR_HSEON RCC_CR_HSEON_Msk
9923#define RCC_CR_HSERDY_Pos (17U)
9924#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
9925#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9926#define RCC_CR_HSEBYP_Pos (18U)
9927#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
9928#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9929#define RCC_CR_CSSON_Pos (19U)
9930#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
9931#define RCC_CR_CSSON RCC_CR_CSSON_Msk
9932#define RCC_CR_PLLON_Pos (24U)
9933#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
9934#define RCC_CR_PLLON RCC_CR_PLLON_Msk
9935#define RCC_CR_PLLRDY_Pos (25U)
9936#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
9937#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9938#define RCC_CR_PLLI2SON_Pos (26U)
9939#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
9940#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9941#define RCC_CR_PLLI2SRDY_Pos (27U)
9942#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
9943#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9944#define RCC_CR_PLLSAION_Pos (28U)
9945#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos)
9946#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
9947#define RCC_CR_PLLSAIRDY_Pos (29U)
9948#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos)
9949#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
9950
9951/******************** Bit definition for RCC_PLLCFGR register ***************/
9952#define RCC_PLLCFGR_PLLM_Pos (0U)
9953#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
9954#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9955#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
9956#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
9957#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
9958#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
9959#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
9960#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
9961#define RCC_PLLCFGR_PLLN_Pos (6U)
9962#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
9963#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9964#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
9965#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
9966#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
9967#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
9968#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
9969#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
9970#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
9971#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
9972#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
9973#define RCC_PLLCFGR_PLLP_Pos (16U)
9974#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
9975#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9976#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
9977#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
9978#define RCC_PLLCFGR_PLLSRC_Pos (22U)
9979#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
9980#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9981#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9982#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
9983#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9984#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9985#define RCC_PLLCFGR_PLLQ_Pos (24U)
9986#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
9987#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9988#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
9989#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
9990#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
9991#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
9994/******************** Bit definition for RCC_CFGR register ******************/
9996#define RCC_CFGR_SW_Pos (0U)
9997#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
9998#define RCC_CFGR_SW RCC_CFGR_SW_Msk
9999#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
10000#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
10001#define RCC_CFGR_SW_HSI 0x00000000U
10002#define RCC_CFGR_SW_HSE 0x00000001U
10003#define RCC_CFGR_SW_PLL 0x00000002U
10006#define RCC_CFGR_SWS_Pos (2U)
10007#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
10008#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
10009#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
10010#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
10011#define RCC_CFGR_SWS_HSI 0x00000000U
10012#define RCC_CFGR_SWS_HSE 0x00000004U
10013#define RCC_CFGR_SWS_PLL 0x00000008U
10016#define RCC_CFGR_HPRE_Pos (4U)
10017#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
10018#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
10019#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
10020#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
10021#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
10022#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
10024#define RCC_CFGR_HPRE_DIV1 0x00000000U
10025#define RCC_CFGR_HPRE_DIV2 0x00000080U
10026#define RCC_CFGR_HPRE_DIV4 0x00000090U
10027#define RCC_CFGR_HPRE_DIV8 0x000000A0U
10028#define RCC_CFGR_HPRE_DIV16 0x000000B0U
10029#define RCC_CFGR_HPRE_DIV64 0x000000C0U
10030#define RCC_CFGR_HPRE_DIV128 0x000000D0U
10031#define RCC_CFGR_HPRE_DIV256 0x000000E0U
10032#define RCC_CFGR_HPRE_DIV512 0x000000F0U
10035#define RCC_CFGR_PPRE1_Pos (10U)
10036#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
10037#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
10038#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
10039#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
10040#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
10042#define RCC_CFGR_PPRE1_DIV1 0x00000000U
10043#define RCC_CFGR_PPRE1_DIV2 0x00001000U
10044#define RCC_CFGR_PPRE1_DIV4 0x00001400U
10045#define RCC_CFGR_PPRE1_DIV8 0x00001800U
10046#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
10049#define RCC_CFGR_PPRE2_Pos (13U)
10050#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
10051#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
10052#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
10053#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
10054#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
10056#define RCC_CFGR_PPRE2_DIV1 0x00000000U
10057#define RCC_CFGR_PPRE2_DIV2 0x00008000U
10058#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
10059#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
10060#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
10063#define RCC_CFGR_RTCPRE_Pos (16U)
10064#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
10065#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
10066#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
10067#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
10068#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
10069#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
10070#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
10073#define RCC_CFGR_MCO1_Pos (21U)
10074#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
10075#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
10076#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
10077#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
10079#define RCC_CFGR_I2SSRC_Pos (23U)
10080#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
10081#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
10082
10083#define RCC_CFGR_MCO1PRE_Pos (24U)
10084#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
10085#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
10086#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
10087#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
10088#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
10090#define RCC_CFGR_MCO2PRE_Pos (27U)
10091#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
10092#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
10093#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
10094#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
10095#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
10097#define RCC_CFGR_MCO2_Pos (30U)
10098#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
10099#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
10100#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
10101#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
10103/******************** Bit definition for RCC_CIR register *******************/
10104#define RCC_CIR_LSIRDYF_Pos (0U)
10105#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
10106#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
10107#define RCC_CIR_LSERDYF_Pos (1U)
10108#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
10109#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
10110#define RCC_CIR_HSIRDYF_Pos (2U)
10111#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
10112#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
10113#define RCC_CIR_HSERDYF_Pos (3U)
10114#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
10115#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
10116#define RCC_CIR_PLLRDYF_Pos (4U)
10117#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
10118#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
10119#define RCC_CIR_PLLI2SRDYF_Pos (5U)
10120#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
10121#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
10122#define RCC_CIR_PLLSAIRDYF_Pos (6U)
10123#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)
10124#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
10125#define RCC_CIR_CSSF_Pos (7U)
10126#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
10127#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
10128#define RCC_CIR_LSIRDYIE_Pos (8U)
10129#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
10130#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
10131#define RCC_CIR_LSERDYIE_Pos (9U)
10132#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
10133#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
10134#define RCC_CIR_HSIRDYIE_Pos (10U)
10135#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
10136#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
10137#define RCC_CIR_HSERDYIE_Pos (11U)
10138#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
10139#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
10140#define RCC_CIR_PLLRDYIE_Pos (12U)
10141#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
10142#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
10143#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
10144#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
10145#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
10146#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
10147#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)
10148#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
10149#define RCC_CIR_LSIRDYC_Pos (16U)
10150#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
10151#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
10152#define RCC_CIR_LSERDYC_Pos (17U)
10153#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
10154#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
10155#define RCC_CIR_HSIRDYC_Pos (18U)
10156#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
10157#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
10158#define RCC_CIR_HSERDYC_Pos (19U)
10159#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
10160#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
10161#define RCC_CIR_PLLRDYC_Pos (20U)
10162#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
10163#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
10164#define RCC_CIR_PLLI2SRDYC_Pos (21U)
10165#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
10166#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
10167#define RCC_CIR_PLLSAIRDYC_Pos (22U)
10168#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)
10169#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
10170#define RCC_CIR_CSSC_Pos (23U)
10171#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
10172#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
10173
10174/******************** Bit definition for RCC_AHB1RSTR register **************/
10175#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
10176#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
10177#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
10178#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
10179#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
10180#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
10181#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
10182#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
10183#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
10184#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
10185#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
10186#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
10187#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
10188#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
10189#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
10190#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
10191#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
10192#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
10193#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
10194#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
10195#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
10196#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
10197#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
10198#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
10199#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
10200#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
10201#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
10202#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
10203#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos)
10204#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
10205#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
10206#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos)
10207#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
10208#define RCC_AHB1RSTR_CRCRST_Pos (12U)
10209#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
10210#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10211#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
10212#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
10213#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10214#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
10215#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
10216#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10217#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
10218#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos)
10219#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
10220#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
10221#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
10222#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
10223#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
10224#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
10225#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
10226
10227/******************** Bit definition for RCC_AHB2RSTR register **************/
10228#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
10229#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
10230#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
10231#define RCC_AHB2RSTR_RNGRST_Pos (6U)
10232#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
10233#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
10234#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
10235#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
10236#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
10237
10238/******************** Bit definition for RCC_AHB3RSTR register **************/
10239
10240#define RCC_AHB3RSTR_FMCRST_Pos (0U)
10241#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
10242#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
10243#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
10244#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
10245#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
10246
10247/******************** Bit definition for RCC_APB1RSTR register **************/
10248#define RCC_APB1RSTR_TIM2RST_Pos (0U)
10249#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
10250#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
10251#define RCC_APB1RSTR_TIM3RST_Pos (1U)
10252#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
10253#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
10254#define RCC_APB1RSTR_TIM4RST_Pos (2U)
10255#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
10256#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
10257#define RCC_APB1RSTR_TIM5RST_Pos (3U)
10258#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
10259#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
10260#define RCC_APB1RSTR_TIM6RST_Pos (4U)
10261#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
10262#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
10263#define RCC_APB1RSTR_TIM7RST_Pos (5U)
10264#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
10265#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
10266#define RCC_APB1RSTR_TIM12RST_Pos (6U)
10267#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
10268#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
10269#define RCC_APB1RSTR_TIM13RST_Pos (7U)
10270#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
10271#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
10272#define RCC_APB1RSTR_TIM14RST_Pos (8U)
10273#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
10274#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
10275#define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
10276#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)
10277#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
10278#define RCC_APB1RSTR_WWDGRST_Pos (11U)
10279#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
10280#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
10281#define RCC_APB1RSTR_SPI2RST_Pos (14U)
10282#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
10283#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
10284#define RCC_APB1RSTR_SPI3RST_Pos (15U)
10285#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
10286#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
10287#define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
10288#define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR_SPDIFRXRST_Pos)
10289#define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
10290#define RCC_APB1RSTR_USART2RST_Pos (17U)
10291#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
10292#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
10293#define RCC_APB1RSTR_USART3RST_Pos (18U)
10294#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
10295#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
10296#define RCC_APB1RSTR_UART4RST_Pos (19U)
10297#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
10298#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
10299#define RCC_APB1RSTR_UART5RST_Pos (20U)
10300#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
10301#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
10302#define RCC_APB1RSTR_I2C1RST_Pos (21U)
10303#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
10304#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
10305#define RCC_APB1RSTR_I2C2RST_Pos (22U)
10306#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
10307#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
10308#define RCC_APB1RSTR_I2C3RST_Pos (23U)
10309#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
10310#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
10311#define RCC_APB1RSTR_I2C4RST_Pos (24U)
10312#define RCC_APB1RSTR_I2C4RST_Msk (0x1UL << RCC_APB1RSTR_I2C4RST_Pos)
10313#define RCC_APB1RSTR_I2C4RST RCC_APB1RSTR_I2C4RST_Msk
10314#define RCC_APB1RSTR_CAN1RST_Pos (25U)
10315#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
10316#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
10317#define RCC_APB1RSTR_CAN2RST_Pos (26U)
10318#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
10319#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
10320#define RCC_APB1RSTR_CECRST_Pos (27U)
10321#define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos)
10322#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
10323#define RCC_APB1RSTR_PWRRST_Pos (28U)
10324#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
10325#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
10326#define RCC_APB1RSTR_DACRST_Pos (29U)
10327#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
10328#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
10329#define RCC_APB1RSTR_UART7RST_Pos (30U)
10330#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos)
10331#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
10332#define RCC_APB1RSTR_UART8RST_Pos (31U)
10333#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos)
10334#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
10335
10336/******************** Bit definition for RCC_APB2RSTR register **************/
10337#define RCC_APB2RSTR_TIM1RST_Pos (0U)
10338#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
10339#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
10340#define RCC_APB2RSTR_TIM8RST_Pos (1U)
10341#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
10342#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
10343#define RCC_APB2RSTR_USART1RST_Pos (4U)
10344#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
10345#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
10346#define RCC_APB2RSTR_USART6RST_Pos (5U)
10347#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
10348#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
10349#define RCC_APB2RSTR_ADCRST_Pos (8U)
10350#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
10351#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
10352#define RCC_APB2RSTR_SDMMC1RST_Pos (11U)
10353#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos)
10354#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
10355#define RCC_APB2RSTR_SPI1RST_Pos (12U)
10356#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
10357#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
10358#define RCC_APB2RSTR_SPI4RST_Pos (13U)
10359#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
10360#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
10361#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
10362#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
10363#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
10364#define RCC_APB2RSTR_TIM9RST_Pos (16U)
10365#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
10366#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
10367#define RCC_APB2RSTR_TIM10RST_Pos (17U)
10368#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
10369#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
10370#define RCC_APB2RSTR_TIM11RST_Pos (18U)
10371#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
10372#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
10373#define RCC_APB2RSTR_SPI5RST_Pos (20U)
10374#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
10375#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
10376#define RCC_APB2RSTR_SPI6RST_Pos (21U)
10377#define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)
10378#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
10379#define RCC_APB2RSTR_SAI1RST_Pos (22U)
10380#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
10381#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
10382#define RCC_APB2RSTR_SAI2RST_Pos (23U)
10383#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
10384#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
10385
10386/******************** Bit definition for RCC_AHB1ENR register ***************/
10387#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
10388#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
10389#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
10390#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
10391#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
10392#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
10393#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
10394#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
10395#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
10396#define RCC_AHB1ENR_GPIODEN_Pos (3U)
10397#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
10398#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
10399#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
10400#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
10401#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
10402#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
10403#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
10404#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
10405#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
10406#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
10407#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
10408#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
10409#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
10410#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
10411#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
10412#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
10413#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
10414#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
10415#define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)
10416#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
10417#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
10418#define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)
10419#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
10420#define RCC_AHB1ENR_CRCEN_Pos (12U)
10421#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
10422#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
10423#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
10424#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
10425#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
10426#define RCC_AHB1ENR_DTCMRAMEN_Pos (20U)
10427#define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1UL << RCC_AHB1ENR_DTCMRAMEN_Pos)
10428#define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk
10429#define RCC_AHB1ENR_DMA1EN_Pos (21U)
10430#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
10431#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
10432#define RCC_AHB1ENR_DMA2EN_Pos (22U)
10433#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
10434#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
10435#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
10436#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)
10437#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
10438#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
10439#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
10440#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
10441#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
10442#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
10443#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
10444#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
10445#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
10446#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
10447#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
10448#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
10449#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
10450#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
10451#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
10452#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
10453#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
10454#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
10455#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
10456
10457/******************** Bit definition for RCC_AHB2ENR register ***************/
10458#define RCC_AHB2ENR_DCMIEN_Pos (0U)
10459#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
10460#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
10461#define RCC_AHB2ENR_RNGEN_Pos (6U)
10462#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
10463#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
10464#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
10465#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
10466#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
10467
10468/******************** Bit definition for RCC_AHB3ENR register ***************/
10469#define RCC_AHB3ENR_FMCEN_Pos (0U)
10470#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
10471#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
10472#define RCC_AHB3ENR_QSPIEN_Pos (1U)
10473#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
10474#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
10475
10476/******************** Bit definition for RCC_APB1ENR register ***************/
10477#define RCC_APB1ENR_TIM2EN_Pos (0U)
10478#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
10479#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
10480#define RCC_APB1ENR_TIM3EN_Pos (1U)
10481#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
10482#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
10483#define RCC_APB1ENR_TIM4EN_Pos (2U)
10484#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
10485#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
10486#define RCC_APB1ENR_TIM5EN_Pos (3U)
10487#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
10488#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
10489#define RCC_APB1ENR_TIM6EN_Pos (4U)
10490#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
10491#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
10492#define RCC_APB1ENR_TIM7EN_Pos (5U)
10493#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
10494#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
10495#define RCC_APB1ENR_TIM12EN_Pos (6U)
10496#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
10497#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
10498#define RCC_APB1ENR_TIM13EN_Pos (7U)
10499#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
10500#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
10501#define RCC_APB1ENR_TIM14EN_Pos (8U)
10502#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
10503#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
10504#define RCC_APB1ENR_LPTIM1EN_Pos (9U)
10505#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)
10506#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
10507#define RCC_APB1ENR_WWDGEN_Pos (11U)
10508#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
10509#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
10510#define RCC_APB1ENR_SPI2EN_Pos (14U)
10511#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
10512#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
10513#define RCC_APB1ENR_SPI3EN_Pos (15U)
10514#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
10515#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
10516#define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
10517#define RCC_APB1ENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR_SPDIFRXEN_Pos)
10518#define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
10519#define RCC_APB1ENR_USART2EN_Pos (17U)
10520#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
10521#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
10522#define RCC_APB1ENR_USART3EN_Pos (18U)
10523#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
10524#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
10525#define RCC_APB1ENR_UART4EN_Pos (19U)
10526#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
10527#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
10528#define RCC_APB1ENR_UART5EN_Pos (20U)
10529#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
10530#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
10531#define RCC_APB1ENR_I2C1EN_Pos (21U)
10532#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
10533#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
10534#define RCC_APB1ENR_I2C2EN_Pos (22U)
10535#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
10536#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
10537#define RCC_APB1ENR_I2C3EN_Pos (23U)
10538#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
10539#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
10540#define RCC_APB1ENR_I2C4EN_Pos (24U)
10541#define RCC_APB1ENR_I2C4EN_Msk (0x1UL << RCC_APB1ENR_I2C4EN_Pos)
10542#define RCC_APB1ENR_I2C4EN RCC_APB1ENR_I2C4EN_Msk
10543#define RCC_APB1ENR_CAN1EN_Pos (25U)
10544#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
10545#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
10546#define RCC_APB1ENR_CAN2EN_Pos (26U)
10547#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
10548#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
10549#define RCC_APB1ENR_CECEN_Pos (27U)
10550#define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos)
10551#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
10552#define RCC_APB1ENR_PWREN_Pos (28U)
10553#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
10554#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
10555#define RCC_APB1ENR_DACEN_Pos (29U)
10556#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
10557#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
10558#define RCC_APB1ENR_UART7EN_Pos (30U)
10559#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos)
10560#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
10561#define RCC_APB1ENR_UART8EN_Pos (31U)
10562#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos)
10563#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
10564
10565/******************** Bit definition for RCC_APB2ENR register ***************/
10566#define RCC_APB2ENR_TIM1EN_Pos (0U)
10567#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
10568#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
10569#define RCC_APB2ENR_TIM8EN_Pos (1U)
10570#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
10571#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
10572#define RCC_APB2ENR_USART1EN_Pos (4U)
10573#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
10574#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
10575#define RCC_APB2ENR_USART6EN_Pos (5U)
10576#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
10577#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
10578#define RCC_APB2ENR_ADC1EN_Pos (8U)
10579#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
10580#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
10581#define RCC_APB2ENR_ADC2EN_Pos (9U)
10582#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
10583#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
10584#define RCC_APB2ENR_ADC3EN_Pos (10U)
10585#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
10586#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
10587#define RCC_APB2ENR_SDMMC1EN_Pos (11U)
10588#define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos)
10589#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
10590#define RCC_APB2ENR_SPI1EN_Pos (12U)
10591#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
10592#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
10593#define RCC_APB2ENR_SPI4EN_Pos (13U)
10594#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
10595#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
10596#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
10597#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
10598#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
10599#define RCC_APB2ENR_TIM9EN_Pos (16U)
10600#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
10601#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
10602#define RCC_APB2ENR_TIM10EN_Pos (17U)
10603#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
10604#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
10605#define RCC_APB2ENR_TIM11EN_Pos (18U)
10606#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
10607#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
10608#define RCC_APB2ENR_SPI5EN_Pos (20U)
10609#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
10610#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
10611#define RCC_APB2ENR_SPI6EN_Pos (21U)
10612#define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos)
10613#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
10614#define RCC_APB2ENR_SAI1EN_Pos (22U)
10615#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
10616#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
10617#define RCC_APB2ENR_SAI2EN_Pos (23U)
10618#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
10619#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
10620
10621/******************** Bit definition for RCC_AHB1LPENR register *************/
10622#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
10623#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
10624#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
10625#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
10626#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
10627#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
10628#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
10629#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
10630#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
10631#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
10632#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
10633#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
10634#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
10635#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
10636#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
10637#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
10638#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
10639#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
10640#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
10641#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
10642#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
10643#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
10644#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
10645#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
10646#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
10647#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
10648#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
10649#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
10650#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos)
10651#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
10652#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
10653#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos)
10654#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
10655#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
10656#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
10657#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
10658#define RCC_AHB1LPENR_AXILPEN_Pos (13U)
10659#define RCC_AHB1LPENR_AXILPEN_Msk (0x1UL << RCC_AHB1LPENR_AXILPEN_Pos)
10660#define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk
10661#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
10662#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
10663#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
10664#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
10665#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
10666#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
10667#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
10668#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
10669#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
10670#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
10671#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
10672#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
10673#define RCC_AHB1LPENR_DTCMLPEN_Pos (20U)
10674#define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1UL << RCC_AHB1LPENR_DTCMLPEN_Pos)
10675#define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk
10676#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
10677#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
10678#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
10679#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
10680#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
10681#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
10682#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
10683#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos)
10684#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
10685#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
10686#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
10687#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
10688#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
10689#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
10690#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
10691#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
10692#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
10693#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
10694#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
10695#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
10696#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
10697#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
10698#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
10699#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
10700#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
10701#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
10702#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
10703
10704/******************** Bit definition for RCC_AHB2LPENR register *************/
10705#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
10706#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
10707#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
10708#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
10709#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
10710#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
10711#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
10712#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
10713#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
10714
10715/******************** Bit definition for RCC_AHB3LPENR register *************/
10716#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
10717#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
10718#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
10719#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
10720#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
10721#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
10722/******************** Bit definition for RCC_APB1LPENR register *************/
10723#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
10724#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
10725#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
10726#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
10727#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
10728#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
10729#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
10730#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
10731#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
10732#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
10733#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
10734#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
10735#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
10736#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
10737#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
10738#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
10739#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
10740#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
10741#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
10742#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
10743#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
10744#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
10745#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
10746#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
10747#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
10748#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
10749#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
10750#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
10751#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos)
10752#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
10753#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
10754#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
10755#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
10756#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
10757#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
10758#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
10759#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
10760#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
10761#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
10762#define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
10763#define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR_SPDIFRXLPEN_Pos)
10764#define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
10765#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
10766#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
10767#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
10768#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
10769#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
10770#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
10771#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
10772#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
10773#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
10774#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
10775#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
10776#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
10777#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
10778#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
10779#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
10780#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
10781#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
10782#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
10783#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
10784#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
10785#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
10786#define RCC_APB1LPENR_I2C4LPEN_Pos (24U)
10787#define RCC_APB1LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C4LPEN_Pos)
10788#define RCC_APB1LPENR_I2C4LPEN RCC_APB1LPENR_I2C4LPEN_Msk
10789#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
10790#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
10791#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
10792#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
10793#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
10794#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
10795#define RCC_APB1LPENR_CECLPEN_Pos (27U)
10796#define RCC_APB1LPENR_CECLPEN_Msk (0x1UL << RCC_APB1LPENR_CECLPEN_Pos)
10797#define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
10798#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
10799#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
10800#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
10801#define RCC_APB1LPENR_DACLPEN_Pos (29U)
10802#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
10803#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
10804#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
10805#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos)
10806#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
10807#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
10808#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos)
10809#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
10810
10811/******************** Bit definition for RCC_APB2LPENR register *************/
10812#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
10813#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
10814#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
10815#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
10816#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
10817#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
10818#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
10819#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
10820#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
10821#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
10822#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
10823#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
10824#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
10825#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
10826#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
10827#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
10828#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
10829#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
10830#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
10831#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
10832#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
10833#define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U)
10834#define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC1LPEN_Pos)
10835#define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk
10836#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
10837#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
10838#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
10839#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
10840#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
10841#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
10842#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
10843#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
10844#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
10845#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
10846#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
10847#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
10848#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
10849#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
10850#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
10851#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
10852#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
10853#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
10854#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
10855#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
10856#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
10857#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
10858#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos)
10859#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
10860#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
10861#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
10862#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
10863#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
10864#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)
10865#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
10866
10867/******************** Bit definition for RCC_BDCR register ******************/
10868#define RCC_BDCR_LSEON_Pos (0U)
10869#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
10870#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10871#define RCC_BDCR_LSERDY_Pos (1U)
10872#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
10873#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10874#define RCC_BDCR_LSEBYP_Pos (2U)
10875#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
10876#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10877#define RCC_BDCR_LSEDRV_Pos (3U)
10878#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
10879#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
10880#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
10881#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
10882#define RCC_BDCR_RTCSEL_Pos (8U)
10883#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
10884#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10885#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
10886#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
10887#define RCC_BDCR_RTCEN_Pos (15U)
10888#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
10889#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10890#define RCC_BDCR_BDRST_Pos (16U)
10891#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
10892#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10893
10894/******************** Bit definition for RCC_CSR register *******************/
10895#define RCC_CSR_LSION_Pos (0U)
10896#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
10897#define RCC_CSR_LSION RCC_CSR_LSION_Msk
10898#define RCC_CSR_LSIRDY_Pos (1U)
10899#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
10900#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10901#define RCC_CSR_RMVF_Pos (24U)
10902#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
10903#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10904#define RCC_CSR_BORRSTF_Pos (25U)
10905#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
10906#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10907#define RCC_CSR_PINRSTF_Pos (26U)
10908#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
10909#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10910#define RCC_CSR_PORRSTF_Pos (27U)
10911#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
10912#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10913#define RCC_CSR_SFTRSTF_Pos (28U)
10914#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
10915#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10916#define RCC_CSR_IWDGRSTF_Pos (29U)
10917#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
10918#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10919#define RCC_CSR_WWDGRSTF_Pos (30U)
10920#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
10921#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10922#define RCC_CSR_LPWRRSTF_Pos (31U)
10923#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
10924#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10925
10926/******************** Bit definition for RCC_SSCGR register *****************/
10927#define RCC_SSCGR_MODPER_Pos (0U)
10928#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
10929#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10930#define RCC_SSCGR_INCSTEP_Pos (13U)
10931#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
10932#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10933#define RCC_SSCGR_SPREADSEL_Pos (30U)
10934#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
10935#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10936#define RCC_SSCGR_SSCGEN_Pos (31U)
10937#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
10938#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10939
10940/******************** Bit definition for RCC_PLLI2SCFGR register ************/
10941#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10942#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10943#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10944#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10945#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10946#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10947#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10948#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10949#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10950#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10951#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10952#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10953#define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
10954#define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
10955#define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
10956#define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
10957#define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
10958#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
10959#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10960#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
10961#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10962#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10963#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10964#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10965#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10966#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10967#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10968#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10969#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10970#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10972/******************** Bit definition for RCC_PLLSAICFGR register ************/
10973#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
10974#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10975#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
10976#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10977#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10978#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10979#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10980#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10981#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10982#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10983#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10984#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10985#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
10986#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
10987#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
10988#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
10989#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
10990#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
10991#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
10992#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
10993#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
10994#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
10995#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
10996#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
10997#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
10998#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
10999#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
11000#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11001#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11002#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11004/******************** Bit definition for RCC_DCKCFGR1 register ***************/
11005#define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U)
11006#define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11007#define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk
11008#define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11009#define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11010#define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11011#define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11012#define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11014#define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U)
11015#define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11016#define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk
11017#define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11018#define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11019#define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11020#define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11021#define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11023#define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U)
11024#define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos)
11025#define RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR_Msk
11026#define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos)
11027#define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos)
11029#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
11030#define RCC_DCKCFGR1_SAI1SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI1SEL_Pos)
11031#define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk
11032#define RCC_DCKCFGR1_SAI1SEL_0 (0x1UL << RCC_DCKCFGR1_SAI1SEL_Pos)
11033#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos)
11035#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
11036#define RCC_DCKCFGR1_SAI2SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI2SEL_Pos)
11037#define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk
11038#define RCC_DCKCFGR1_SAI2SEL_0 (0x1UL << RCC_DCKCFGR1_SAI2SEL_Pos)
11039#define RCC_DCKCFGR1_SAI2SEL_1 (0x2UL << RCC_DCKCFGR1_SAI2SEL_Pos)
11041#define RCC_DCKCFGR1_TIMPRE_Pos (24U)
11042#define RCC_DCKCFGR1_TIMPRE_Msk (0x1UL << RCC_DCKCFGR1_TIMPRE_Pos)
11043#define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk
11044
11045/******************** Bit definition for RCC_DCKCFGR2 register ***************/
11046#define RCC_DCKCFGR2_USART1SEL_Pos (0U)
11047#define RCC_DCKCFGR2_USART1SEL_Msk (0x3UL << RCC_DCKCFGR2_USART1SEL_Pos)
11048#define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk
11049#define RCC_DCKCFGR2_USART1SEL_0 (0x1UL << RCC_DCKCFGR2_USART1SEL_Pos)
11050#define RCC_DCKCFGR2_USART1SEL_1 (0x2UL << RCC_DCKCFGR2_USART1SEL_Pos)
11051#define RCC_DCKCFGR2_USART2SEL_Pos (2U)
11052#define RCC_DCKCFGR2_USART2SEL_Msk (0x3UL << RCC_DCKCFGR2_USART2SEL_Pos)
11053#define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk
11054#define RCC_DCKCFGR2_USART2SEL_0 (0x1UL << RCC_DCKCFGR2_USART2SEL_Pos)
11055#define RCC_DCKCFGR2_USART2SEL_1 (0x2UL << RCC_DCKCFGR2_USART2SEL_Pos)
11056#define RCC_DCKCFGR2_USART3SEL_Pos (4U)
11057#define RCC_DCKCFGR2_USART3SEL_Msk (0x3UL << RCC_DCKCFGR2_USART3SEL_Pos)
11058#define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk
11059#define RCC_DCKCFGR2_USART3SEL_0 (0x1UL << RCC_DCKCFGR2_USART3SEL_Pos)
11060#define RCC_DCKCFGR2_USART3SEL_1 (0x2UL << RCC_DCKCFGR2_USART3SEL_Pos)
11061#define RCC_DCKCFGR2_UART4SEL_Pos (6U)
11062#define RCC_DCKCFGR2_UART4SEL_Msk (0x3UL << RCC_DCKCFGR2_UART4SEL_Pos)
11063#define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk
11064#define RCC_DCKCFGR2_UART4SEL_0 (0x1UL << RCC_DCKCFGR2_UART4SEL_Pos)
11065#define RCC_DCKCFGR2_UART4SEL_1 (0x2UL << RCC_DCKCFGR2_UART4SEL_Pos)
11066#define RCC_DCKCFGR2_UART5SEL_Pos (8U)
11067#define RCC_DCKCFGR2_UART5SEL_Msk (0x3UL << RCC_DCKCFGR2_UART5SEL_Pos)
11068#define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk
11069#define RCC_DCKCFGR2_UART5SEL_0 (0x1UL << RCC_DCKCFGR2_UART5SEL_Pos)
11070#define RCC_DCKCFGR2_UART5SEL_1 (0x2UL << RCC_DCKCFGR2_UART5SEL_Pos)
11071#define RCC_DCKCFGR2_USART6SEL_Pos (10U)
11072#define RCC_DCKCFGR2_USART6SEL_Msk (0x3UL << RCC_DCKCFGR2_USART6SEL_Pos)
11073#define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk
11074#define RCC_DCKCFGR2_USART6SEL_0 (0x1UL << RCC_DCKCFGR2_USART6SEL_Pos)
11075#define RCC_DCKCFGR2_USART6SEL_1 (0x2UL << RCC_DCKCFGR2_USART6SEL_Pos)
11076#define RCC_DCKCFGR2_UART7SEL_Pos (12U)
11077#define RCC_DCKCFGR2_UART7SEL_Msk (0x3UL << RCC_DCKCFGR2_UART7SEL_Pos)
11078#define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk
11079#define RCC_DCKCFGR2_UART7SEL_0 (0x1UL << RCC_DCKCFGR2_UART7SEL_Pos)
11080#define RCC_DCKCFGR2_UART7SEL_1 (0x2UL << RCC_DCKCFGR2_UART7SEL_Pos)
11081#define RCC_DCKCFGR2_UART8SEL_Pos (14U)
11082#define RCC_DCKCFGR2_UART8SEL_Msk (0x3UL << RCC_DCKCFGR2_UART8SEL_Pos)
11083#define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk
11084#define RCC_DCKCFGR2_UART8SEL_0 (0x1UL << RCC_DCKCFGR2_UART8SEL_Pos)
11085#define RCC_DCKCFGR2_UART8SEL_1 (0x2UL << RCC_DCKCFGR2_UART8SEL_Pos)
11086#define RCC_DCKCFGR2_I2C1SEL_Pos (16U)
11087#define RCC_DCKCFGR2_I2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C1SEL_Pos)
11088#define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk
11089#define RCC_DCKCFGR2_I2C1SEL_0 (0x1UL << RCC_DCKCFGR2_I2C1SEL_Pos)
11090#define RCC_DCKCFGR2_I2C1SEL_1 (0x2UL << RCC_DCKCFGR2_I2C1SEL_Pos)
11091#define RCC_DCKCFGR2_I2C2SEL_Pos (18U)
11092#define RCC_DCKCFGR2_I2C2SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C2SEL_Pos)
11093#define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk
11094#define RCC_DCKCFGR2_I2C2SEL_0 (0x1UL << RCC_DCKCFGR2_I2C2SEL_Pos)
11095#define RCC_DCKCFGR2_I2C2SEL_1 (0x2UL << RCC_DCKCFGR2_I2C2SEL_Pos)
11096#define RCC_DCKCFGR2_I2C3SEL_Pos (20U)
11097#define RCC_DCKCFGR2_I2C3SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C3SEL_Pos)
11098#define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk
11099#define RCC_DCKCFGR2_I2C3SEL_0 (0x1UL << RCC_DCKCFGR2_I2C3SEL_Pos)
11100#define RCC_DCKCFGR2_I2C3SEL_1 (0x2UL << RCC_DCKCFGR2_I2C3SEL_Pos)
11101#define RCC_DCKCFGR2_I2C4SEL_Pos (22U)
11102#define RCC_DCKCFGR2_I2C4SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C4SEL_Pos)
11103#define RCC_DCKCFGR2_I2C4SEL RCC_DCKCFGR2_I2C4SEL_Msk
11104#define RCC_DCKCFGR2_I2C4SEL_0 (0x1UL << RCC_DCKCFGR2_I2C4SEL_Pos)
11105#define RCC_DCKCFGR2_I2C4SEL_1 (0x2UL << RCC_DCKCFGR2_I2C4SEL_Pos)
11106#define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U)
11107#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
11108#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
11109#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
11110#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
11111#define RCC_DCKCFGR2_CECSEL_Pos (26U)
11112#define RCC_DCKCFGR2_CECSEL_Msk (0x1UL << RCC_DCKCFGR2_CECSEL_Pos)
11113#define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
11114#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
11115#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos)
11116#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
11117#define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U)
11118#define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC1SEL_Pos)
11119#define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk
11120
11121/******************************************************************************/
11122/* */
11123/* RNG */
11124/* */
11125/******************************************************************************/
11126/******************** Bits definition for RNG_CR register *******************/
11127#define RNG_CR_RNGEN_Pos (2U)
11128#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
11129#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
11130#define RNG_CR_IE_Pos (3U)
11131#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
11132#define RNG_CR_IE RNG_CR_IE_Msk
11133
11134/******************** Bits definition for RNG_SR register *******************/
11135#define RNG_SR_DRDY_Pos (0U)
11136#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
11137#define RNG_SR_DRDY RNG_SR_DRDY_Msk
11138#define RNG_SR_CECS_Pos (1U)
11139#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
11140#define RNG_SR_CECS RNG_SR_CECS_Msk
11141#define RNG_SR_SECS_Pos (2U)
11142#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
11143#define RNG_SR_SECS RNG_SR_SECS_Msk
11144#define RNG_SR_CEIS_Pos (5U)
11145#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
11146#define RNG_SR_CEIS RNG_SR_CEIS_Msk
11147#define RNG_SR_SEIS_Pos (6U)
11148#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
11149#define RNG_SR_SEIS RNG_SR_SEIS_Msk
11150
11151/******************************************************************************/
11152/* */
11153/* Real-Time Clock (RTC) */
11154/* */
11155/******************************************************************************/
11156/******************** Bits definition for RTC_TR register *******************/
11157#define RTC_TR_PM_Pos (22U)
11158#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
11159#define RTC_TR_PM RTC_TR_PM_Msk
11160#define RTC_TR_HT_Pos (20U)
11161#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
11162#define RTC_TR_HT RTC_TR_HT_Msk
11163#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
11164#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
11165#define RTC_TR_HU_Pos (16U)
11166#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
11167#define RTC_TR_HU RTC_TR_HU_Msk
11168#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
11169#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
11170#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
11171#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
11172#define RTC_TR_MNT_Pos (12U)
11173#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
11174#define RTC_TR_MNT RTC_TR_MNT_Msk
11175#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
11176#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
11177#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
11178#define RTC_TR_MNU_Pos (8U)
11179#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
11180#define RTC_TR_MNU RTC_TR_MNU_Msk
11181#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
11182#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
11183#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
11184#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
11185#define RTC_TR_ST_Pos (4U)
11186#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
11187#define RTC_TR_ST RTC_TR_ST_Msk
11188#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
11189#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
11190#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
11191#define RTC_TR_SU_Pos (0U)
11192#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
11193#define RTC_TR_SU RTC_TR_SU_Msk
11194#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
11195#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
11196#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
11197#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
11199/******************** Bits definition for RTC_DR register *******************/
11200#define RTC_DR_YT_Pos (20U)
11201#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
11202#define RTC_DR_YT RTC_DR_YT_Msk
11203#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
11204#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
11205#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
11206#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
11207#define RTC_DR_YU_Pos (16U)
11208#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
11209#define RTC_DR_YU RTC_DR_YU_Msk
11210#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
11211#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
11212#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
11213#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
11214#define RTC_DR_WDU_Pos (13U)
11215#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
11216#define RTC_DR_WDU RTC_DR_WDU_Msk
11217#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
11218#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
11219#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
11220#define RTC_DR_MT_Pos (12U)
11221#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
11222#define RTC_DR_MT RTC_DR_MT_Msk
11223#define RTC_DR_MU_Pos (8U)
11224#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
11225#define RTC_DR_MU RTC_DR_MU_Msk
11226#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
11227#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
11228#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
11229#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
11230#define RTC_DR_DT_Pos (4U)
11231#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
11232#define RTC_DR_DT RTC_DR_DT_Msk
11233#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
11234#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
11235#define RTC_DR_DU_Pos (0U)
11236#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
11237#define RTC_DR_DU RTC_DR_DU_Msk
11238#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
11239#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
11240#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
11241#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
11243/******************** Bits definition for RTC_CR register *******************/
11244#define RTC_CR_ITSE_Pos (24U)
11245#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
11246#define RTC_CR_ITSE RTC_CR_ITSE_Msk
11247#define RTC_CR_COE_Pos (23U)
11248#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
11249#define RTC_CR_COE RTC_CR_COE_Msk
11250#define RTC_CR_OSEL_Pos (21U)
11251#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
11252#define RTC_CR_OSEL RTC_CR_OSEL_Msk
11253#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
11254#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
11255#define RTC_CR_POL_Pos (20U)
11256#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
11257#define RTC_CR_POL RTC_CR_POL_Msk
11258#define RTC_CR_COSEL_Pos (19U)
11259#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
11260#define RTC_CR_COSEL RTC_CR_COSEL_Msk
11261#define RTC_CR_BKP_Pos (18U)
11262#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
11263#define RTC_CR_BKP RTC_CR_BKP_Msk
11264#define RTC_CR_SUB1H_Pos (17U)
11265#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
11266#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11267#define RTC_CR_ADD1H_Pos (16U)
11268#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
11269#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11270#define RTC_CR_TSIE_Pos (15U)
11271#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
11272#define RTC_CR_TSIE RTC_CR_TSIE_Msk
11273#define RTC_CR_WUTIE_Pos (14U)
11274#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
11275#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11276#define RTC_CR_ALRBIE_Pos (13U)
11277#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
11278#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11279#define RTC_CR_ALRAIE_Pos (12U)
11280#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
11281#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11282#define RTC_CR_TSE_Pos (11U)
11283#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
11284#define RTC_CR_TSE RTC_CR_TSE_Msk
11285#define RTC_CR_WUTE_Pos (10U)
11286#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
11287#define RTC_CR_WUTE RTC_CR_WUTE_Msk
11288#define RTC_CR_ALRBE_Pos (9U)
11289#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
11290#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11291#define RTC_CR_ALRAE_Pos (8U)
11292#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
11293#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11294#define RTC_CR_FMT_Pos (6U)
11295#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
11296#define RTC_CR_FMT RTC_CR_FMT_Msk
11297#define RTC_CR_BYPSHAD_Pos (5U)
11298#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
11299#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11300#define RTC_CR_REFCKON_Pos (4U)
11301#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
11302#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11303#define RTC_CR_TSEDGE_Pos (3U)
11304#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
11305#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11306#define RTC_CR_WUCKSEL_Pos (0U)
11307#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
11308#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11309#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
11310#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
11311#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
11313/* Legacy define */
11314#define RTC_CR_BCK RTC_CR_BKP
11315
11316/******************** Bits definition for RTC_ISR register ******************/
11317#define RTC_ISR_ITSF_Pos (17U)
11318#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
11319#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
11320#define RTC_ISR_RECALPF_Pos (16U)
11321#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
11322#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11323#define RTC_ISR_TAMP3F_Pos (15U)
11324#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
11325#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
11326#define RTC_ISR_TAMP2F_Pos (14U)
11327#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
11328#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11329#define RTC_ISR_TAMP1F_Pos (13U)
11330#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
11331#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11332#define RTC_ISR_TSOVF_Pos (12U)
11333#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
11334#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11335#define RTC_ISR_TSF_Pos (11U)
11336#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
11337#define RTC_ISR_TSF RTC_ISR_TSF_Msk
11338#define RTC_ISR_WUTF_Pos (10U)
11339#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
11340#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11341#define RTC_ISR_ALRBF_Pos (9U)
11342#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
11343#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11344#define RTC_ISR_ALRAF_Pos (8U)
11345#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
11346#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11347#define RTC_ISR_INIT_Pos (7U)
11348#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
11349#define RTC_ISR_INIT RTC_ISR_INIT_Msk
11350#define RTC_ISR_INITF_Pos (6U)
11351#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
11352#define RTC_ISR_INITF RTC_ISR_INITF_Msk
11353#define RTC_ISR_RSF_Pos (5U)
11354#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
11355#define RTC_ISR_RSF RTC_ISR_RSF_Msk
11356#define RTC_ISR_INITS_Pos (4U)
11357#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
11358#define RTC_ISR_INITS RTC_ISR_INITS_Msk
11359#define RTC_ISR_SHPF_Pos (3U)
11360#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
11361#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11362#define RTC_ISR_WUTWF_Pos (2U)
11363#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
11364#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11365#define RTC_ISR_ALRBWF_Pos (1U)
11366#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
11367#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11368#define RTC_ISR_ALRAWF_Pos (0U)
11369#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
11370#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11371
11372/******************** Bits definition for RTC_PRER register *****************/
11373#define RTC_PRER_PREDIV_A_Pos (16U)
11374#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
11375#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11376#define RTC_PRER_PREDIV_S_Pos (0U)
11377#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
11378#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11379
11380/******************** Bits definition for RTC_WUTR register *****************/
11381#define RTC_WUTR_WUT_Pos (0U)
11382#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
11383#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11384
11385/******************** Bits definition for RTC_ALRMAR register ***************/
11386#define RTC_ALRMAR_MSK4_Pos (31U)
11387#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
11388#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11389#define RTC_ALRMAR_WDSEL_Pos (30U)
11390#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
11391#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11392#define RTC_ALRMAR_DT_Pos (28U)
11393#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
11394#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11395#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
11396#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
11397#define RTC_ALRMAR_DU_Pos (24U)
11398#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
11399#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11400#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
11401#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
11402#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
11403#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
11404#define RTC_ALRMAR_MSK3_Pos (23U)
11405#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
11406#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11407#define RTC_ALRMAR_PM_Pos (22U)
11408#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
11409#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11410#define RTC_ALRMAR_HT_Pos (20U)
11411#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
11412#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11413#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
11414#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
11415#define RTC_ALRMAR_HU_Pos (16U)
11416#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
11417#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11418#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
11419#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
11420#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
11421#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
11422#define RTC_ALRMAR_MSK2_Pos (15U)
11423#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
11424#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11425#define RTC_ALRMAR_MNT_Pos (12U)
11426#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
11427#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11428#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
11429#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
11430#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
11431#define RTC_ALRMAR_MNU_Pos (8U)
11432#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
11433#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11434#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
11435#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
11436#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
11437#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
11438#define RTC_ALRMAR_MSK1_Pos (7U)
11439#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
11440#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
11441#define RTC_ALRMAR_ST_Pos (4U)
11442#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
11443#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
11444#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
11445#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
11446#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
11447#define RTC_ALRMAR_SU_Pos (0U)
11448#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
11449#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
11450#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
11451#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
11452#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
11453#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
11455/******************** Bits definition for RTC_ALRMBR register ***************/
11456#define RTC_ALRMBR_MSK4_Pos (31U)
11457#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
11458#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
11459#define RTC_ALRMBR_WDSEL_Pos (30U)
11460#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
11461#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
11462#define RTC_ALRMBR_DT_Pos (28U)
11463#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
11464#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
11465#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
11466#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
11467#define RTC_ALRMBR_DU_Pos (24U)
11468#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
11469#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11470#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
11471#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
11472#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
11473#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
11474#define RTC_ALRMBR_MSK3_Pos (23U)
11475#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
11476#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11477#define RTC_ALRMBR_PM_Pos (22U)
11478#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
11479#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11480#define RTC_ALRMBR_HT_Pos (20U)
11481#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
11482#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11483#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
11484#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
11485#define RTC_ALRMBR_HU_Pos (16U)
11486#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
11487#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11488#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
11489#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
11490#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
11491#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
11492#define RTC_ALRMBR_MSK2_Pos (15U)
11493#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
11494#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
11495#define RTC_ALRMBR_MNT_Pos (12U)
11496#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
11497#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
11498#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
11499#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
11500#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
11501#define RTC_ALRMBR_MNU_Pos (8U)
11502#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
11503#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
11504#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
11505#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
11506#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
11507#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
11508#define RTC_ALRMBR_MSK1_Pos (7U)
11509#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
11510#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
11511#define RTC_ALRMBR_ST_Pos (4U)
11512#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
11513#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
11514#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
11515#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
11516#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
11517#define RTC_ALRMBR_SU_Pos (0U)
11518#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
11519#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
11520#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
11521#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
11522#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
11523#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
11525/******************** Bits definition for RTC_WPR register ******************/
11526#define RTC_WPR_KEY_Pos (0U)
11527#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
11528#define RTC_WPR_KEY RTC_WPR_KEY_Msk
11529
11530/******************** Bits definition for RTC_SSR register ******************/
11531#define RTC_SSR_SS_Pos (0U)
11532#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
11533#define RTC_SSR_SS RTC_SSR_SS_Msk
11534
11535/******************** Bits definition for RTC_SHIFTR register ***************/
11536#define RTC_SHIFTR_SUBFS_Pos (0U)
11537#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
11538#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
11539#define RTC_SHIFTR_ADD1S_Pos (31U)
11540#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
11541#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
11542
11543/******************** Bits definition for RTC_TSTR register *****************/
11544#define RTC_TSTR_PM_Pos (22U)
11545#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
11546#define RTC_TSTR_PM RTC_TSTR_PM_Msk
11547#define RTC_TSTR_HT_Pos (20U)
11548#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
11549#define RTC_TSTR_HT RTC_TSTR_HT_Msk
11550#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
11551#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
11552#define RTC_TSTR_HU_Pos (16U)
11553#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
11554#define RTC_TSTR_HU RTC_TSTR_HU_Msk
11555#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
11556#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
11557#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
11558#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
11559#define RTC_TSTR_MNT_Pos (12U)
11560#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
11561#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
11562#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
11563#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
11564#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
11565#define RTC_TSTR_MNU_Pos (8U)
11566#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
11567#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
11568#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
11569#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
11570#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
11571#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
11572#define RTC_TSTR_ST_Pos (4U)
11573#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
11574#define RTC_TSTR_ST RTC_TSTR_ST_Msk
11575#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
11576#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
11577#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
11578#define RTC_TSTR_SU_Pos (0U)
11579#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
11580#define RTC_TSTR_SU RTC_TSTR_SU_Msk
11581#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
11582#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
11583#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
11584#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
11586/******************** Bits definition for RTC_TSDR register *****************/
11587#define RTC_TSDR_WDU_Pos (13U)
11588#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
11589#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
11590#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
11591#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
11592#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
11593#define RTC_TSDR_MT_Pos (12U)
11594#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
11595#define RTC_TSDR_MT RTC_TSDR_MT_Msk
11596#define RTC_TSDR_MU_Pos (8U)
11597#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
11598#define RTC_TSDR_MU RTC_TSDR_MU_Msk
11599#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
11600#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
11601#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
11602#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
11603#define RTC_TSDR_DT_Pos (4U)
11604#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
11605#define RTC_TSDR_DT RTC_TSDR_DT_Msk
11606#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
11607#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
11608#define RTC_TSDR_DU_Pos (0U)
11609#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
11610#define RTC_TSDR_DU RTC_TSDR_DU_Msk
11611#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
11612#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
11613#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
11614#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
11616/******************** Bits definition for RTC_TSSSR register ****************/
11617#define RTC_TSSSR_SS_Pos (0U)
11618#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
11619#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
11620
11621/******************** Bits definition for RTC_CAL register *****************/
11622#define RTC_CALR_CALP_Pos (15U)
11623#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
11624#define RTC_CALR_CALP RTC_CALR_CALP_Msk
11625#define RTC_CALR_CALW8_Pos (14U)
11626#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
11627#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
11628#define RTC_CALR_CALW16_Pos (13U)
11629#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
11630#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
11631#define RTC_CALR_CALM_Pos (0U)
11632#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
11633#define RTC_CALR_CALM RTC_CALR_CALM_Msk
11634#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
11635#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
11636#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
11637#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
11638#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
11639#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
11640#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
11641#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
11642#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
11644/******************** Bits definition for RTC_TAMPCR register ****************/
11645#define RTC_TAMPCR_TAMP3MF_Pos (24U)
11646#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
11647#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
11648#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
11649#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
11650#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
11651#define RTC_TAMPCR_TAMP3IE_Pos (22U)
11652#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
11653#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
11654#define RTC_TAMPCR_TAMP2MF_Pos (21U)
11655#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
11656#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
11657#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
11658#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
11659#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
11660#define RTC_TAMPCR_TAMP2IE_Pos (19U)
11661#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
11662#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
11663#define RTC_TAMPCR_TAMP1MF_Pos (18U)
11664#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
11665#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
11666#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
11667#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
11668#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
11669#define RTC_TAMPCR_TAMP1IE_Pos (16U)
11670#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
11671#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
11672#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
11673#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
11674#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
11675#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
11676#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
11677#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
11678#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
11679#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
11680#define RTC_TAMPCR_TAMPFLT_Pos (11U)
11681#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
11682#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
11683#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
11684#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
11685#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
11686#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
11687#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
11688#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
11689#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
11690#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
11691#define RTC_TAMPCR_TAMPTS_Pos (7U)
11692#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
11693#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
11694#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
11695#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
11696#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
11697#define RTC_TAMPCR_TAMP3E_Pos (5U)
11698#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
11699#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
11700#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
11701#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
11702#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
11703#define RTC_TAMPCR_TAMP2E_Pos (3U)
11704#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
11705#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
11706#define RTC_TAMPCR_TAMPIE_Pos (2U)
11707#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
11708#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
11709#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
11710#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
11711#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
11712#define RTC_TAMPCR_TAMP1E_Pos (0U)
11713#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
11714#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
11715
11716/* Legacy defines */
11717#define RTC_TAMPCR_TAMP3_TRG RTC_TAMPCR_TAMP3TRG
11718#define RTC_TAMPCR_TAMP2_TRG RTC_TAMPCR_TAMP2TRG
11719#define RTC_TAMPCR_TAMP1_TRG RTC_TAMPCR_TAMP1TRG
11720
11721/******************** Bits definition for RTC_ALRMASSR register *************/
11722#define RTC_ALRMASSR_MASKSS_Pos (24U)
11723#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
11724#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
11725#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
11726#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
11727#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
11728#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
11729#define RTC_ALRMASSR_SS_Pos (0U)
11730#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
11731#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
11732
11733/******************** Bits definition for RTC_ALRMBSSR register *************/
11734#define RTC_ALRMBSSR_MASKSS_Pos (24U)
11735#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
11736#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
11737#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
11738#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
11739#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
11740#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
11741#define RTC_ALRMBSSR_SS_Pos (0U)
11742#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
11743#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
11744
11745/******************** Bits definition for RTC_OR register ****************/
11746#define RTC_OR_TSINSEL_Pos (1U)
11747#define RTC_OR_TSINSEL_Msk (0x3UL << RTC_OR_TSINSEL_Pos)
11748#define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk
11749#define RTC_OR_TSINSEL_0 (0x1UL << RTC_OR_TSINSEL_Pos)
11750#define RTC_OR_TSINSEL_1 (0x2UL << RTC_OR_TSINSEL_Pos)
11751#define RTC_OR_ALARMOUTTYPE_Pos (3U)
11752#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
11753#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
11754/* Legacy defines*/
11755#define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE
11756
11757/******************** Bits definition for RTC_BKP0R register ****************/
11758#define RTC_BKP0R_Pos (0U)
11759#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
11760#define RTC_BKP0R RTC_BKP0R_Msk
11761
11762/******************** Bits definition for RTC_BKP1R register ****************/
11763#define RTC_BKP1R_Pos (0U)
11764#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
11765#define RTC_BKP1R RTC_BKP1R_Msk
11766
11767/******************** Bits definition for RTC_BKP2R register ****************/
11768#define RTC_BKP2R_Pos (0U)
11769#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
11770#define RTC_BKP2R RTC_BKP2R_Msk
11771
11772/******************** Bits definition for RTC_BKP3R register ****************/
11773#define RTC_BKP3R_Pos (0U)
11774#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
11775#define RTC_BKP3R RTC_BKP3R_Msk
11776
11777/******************** Bits definition for RTC_BKP4R register ****************/
11778#define RTC_BKP4R_Pos (0U)
11779#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
11780#define RTC_BKP4R RTC_BKP4R_Msk
11781
11782/******************** Bits definition for RTC_BKP5R register ****************/
11783#define RTC_BKP5R_Pos (0U)
11784#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
11785#define RTC_BKP5R RTC_BKP5R_Msk
11786
11787/******************** Bits definition for RTC_BKP6R register ****************/
11788#define RTC_BKP6R_Pos (0U)
11789#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
11790#define RTC_BKP6R RTC_BKP6R_Msk
11791
11792/******************** Bits definition for RTC_BKP7R register ****************/
11793#define RTC_BKP7R_Pos (0U)
11794#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
11795#define RTC_BKP7R RTC_BKP7R_Msk
11796
11797/******************** Bits definition for RTC_BKP8R register ****************/
11798#define RTC_BKP8R_Pos (0U)
11799#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
11800#define RTC_BKP8R RTC_BKP8R_Msk
11801
11802/******************** Bits definition for RTC_BKP9R register ****************/
11803#define RTC_BKP9R_Pos (0U)
11804#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
11805#define RTC_BKP9R RTC_BKP9R_Msk
11806
11807/******************** Bits definition for RTC_BKP10R register ***************/
11808#define RTC_BKP10R_Pos (0U)
11809#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
11810#define RTC_BKP10R RTC_BKP10R_Msk
11811
11812/******************** Bits definition for RTC_BKP11R register ***************/
11813#define RTC_BKP11R_Pos (0U)
11814#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
11815#define RTC_BKP11R RTC_BKP11R_Msk
11816
11817/******************** Bits definition for RTC_BKP12R register ***************/
11818#define RTC_BKP12R_Pos (0U)
11819#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
11820#define RTC_BKP12R RTC_BKP12R_Msk
11821
11822/******************** Bits definition for RTC_BKP13R register ***************/
11823#define RTC_BKP13R_Pos (0U)
11824#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
11825#define RTC_BKP13R RTC_BKP13R_Msk
11826
11827/******************** Bits definition for RTC_BKP14R register ***************/
11828#define RTC_BKP14R_Pos (0U)
11829#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
11830#define RTC_BKP14R RTC_BKP14R_Msk
11831
11832/******************** Bits definition for RTC_BKP15R register ***************/
11833#define RTC_BKP15R_Pos (0U)
11834#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
11835#define RTC_BKP15R RTC_BKP15R_Msk
11836
11837/******************** Bits definition for RTC_BKP16R register ***************/
11838#define RTC_BKP16R_Pos (0U)
11839#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
11840#define RTC_BKP16R RTC_BKP16R_Msk
11841
11842/******************** Bits definition for RTC_BKP17R register ***************/
11843#define RTC_BKP17R_Pos (0U)
11844#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
11845#define RTC_BKP17R RTC_BKP17R_Msk
11846
11847/******************** Bits definition for RTC_BKP18R register ***************/
11848#define RTC_BKP18R_Pos (0U)
11849#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
11850#define RTC_BKP18R RTC_BKP18R_Msk
11851
11852/******************** Bits definition for RTC_BKP19R register ***************/
11853#define RTC_BKP19R_Pos (0U)
11854#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
11855#define RTC_BKP19R RTC_BKP19R_Msk
11856
11857/******************** Bits definition for RTC_BKP20R register ***************/
11858#define RTC_BKP20R_Pos (0U)
11859#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
11860#define RTC_BKP20R RTC_BKP20R_Msk
11861
11862/******************** Bits definition for RTC_BKP21R register ***************/
11863#define RTC_BKP21R_Pos (0U)
11864#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
11865#define RTC_BKP21R RTC_BKP21R_Msk
11866
11867/******************** Bits definition for RTC_BKP22R register ***************/
11868#define RTC_BKP22R_Pos (0U)
11869#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
11870#define RTC_BKP22R RTC_BKP22R_Msk
11871
11872/******************** Bits definition for RTC_BKP23R register ***************/
11873#define RTC_BKP23R_Pos (0U)
11874#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
11875#define RTC_BKP23R RTC_BKP23R_Msk
11876
11877/******************** Bits definition for RTC_BKP24R register ***************/
11878#define RTC_BKP24R_Pos (0U)
11879#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
11880#define RTC_BKP24R RTC_BKP24R_Msk
11881
11882/******************** Bits definition for RTC_BKP25R register ***************/
11883#define RTC_BKP25R_Pos (0U)
11884#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
11885#define RTC_BKP25R RTC_BKP25R_Msk
11886
11887/******************** Bits definition for RTC_BKP26R register ***************/
11888#define RTC_BKP26R_Pos (0U)
11889#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
11890#define RTC_BKP26R RTC_BKP26R_Msk
11891
11892/******************** Bits definition for RTC_BKP27R register ***************/
11893#define RTC_BKP27R_Pos (0U)
11894#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
11895#define RTC_BKP27R RTC_BKP27R_Msk
11896
11897/******************** Bits definition for RTC_BKP28R register ***************/
11898#define RTC_BKP28R_Pos (0U)
11899#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
11900#define RTC_BKP28R RTC_BKP28R_Msk
11901
11902/******************** Bits definition for RTC_BKP29R register ***************/
11903#define RTC_BKP29R_Pos (0U)
11904#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
11905#define RTC_BKP29R RTC_BKP29R_Msk
11906
11907/******************** Bits definition for RTC_BKP30R register ***************/
11908#define RTC_BKP30R_Pos (0U)
11909#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
11910#define RTC_BKP30R RTC_BKP30R_Msk
11911
11912/******************** Bits definition for RTC_BKP31R register ***************/
11913#define RTC_BKP31R_Pos (0U)
11914#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
11915#define RTC_BKP31R RTC_BKP31R_Msk
11916
11917/******************** Number of backup registers ******************************/
11918#define RTC_BKP_NUMBER 0x00000020U
11919
11920/******************************************************************************/
11921/* */
11922/* Serial Audio Interface */
11923/* */
11924/******************************************************************************/
11925/******************** Bit definition for SAI_GCR register *******************/
11926#define SAI_GCR_SYNCIN_Pos (0U)
11927#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
11928#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
11929#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
11930#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
11932#define SAI_GCR_SYNCOUT_Pos (4U)
11933#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
11934#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
11935#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
11936#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
11938/******************* Bit definition for SAI_xCR1 register *******************/
11939#define SAI_xCR1_MODE_Pos (0U)
11940#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
11941#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
11942#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
11943#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
11945#define SAI_xCR1_PRTCFG_Pos (2U)
11946#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
11947#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
11948#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
11949#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
11951#define SAI_xCR1_DS_Pos (5U)
11952#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
11953#define SAI_xCR1_DS SAI_xCR1_DS_Msk
11954#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
11955#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
11956#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
11958#define SAI_xCR1_LSBFIRST_Pos (8U)
11959#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
11960#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
11961#define SAI_xCR1_CKSTR_Pos (9U)
11962#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
11963#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
11965#define SAI_xCR1_SYNCEN_Pos (10U)
11966#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
11967#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
11968#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
11969#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
11971#define SAI_xCR1_MONO_Pos (12U)
11972#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
11973#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
11974#define SAI_xCR1_OUTDRIV_Pos (13U)
11975#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
11976#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
11977#define SAI_xCR1_SAIEN_Pos (16U)
11978#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
11979#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
11980#define SAI_xCR1_DMAEN_Pos (17U)
11981#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
11982#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
11983#define SAI_xCR1_NODIV_Pos (19U)
11984#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
11985#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
11987#define SAI_xCR1_MCKDIV_Pos (20U)
11988#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
11989#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
11990#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
11991#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
11992#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
11993#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
11995/******************* Bit definition for SAI_xCR2 register *******************/
11996#define SAI_xCR2_FTH_Pos (0U)
11997#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
11998#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
11999#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
12000#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
12001#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
12003#define SAI_xCR2_FFLUSH_Pos (3U)
12004#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
12005#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
12006#define SAI_xCR2_TRIS_Pos (4U)
12007#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
12008#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
12009#define SAI_xCR2_MUTE_Pos (5U)
12010#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
12011#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
12012#define SAI_xCR2_MUTEVAL_Pos (6U)
12013#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
12014#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
12016#define SAI_xCR2_MUTECNT_Pos (7U)
12017#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
12018#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
12019#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
12020#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
12021#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
12022#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
12023#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
12024#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
12026#define SAI_xCR2_CPL_Pos (13U)
12027#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
12028#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
12030#define SAI_xCR2_COMP_Pos (14U)
12031#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
12032#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
12033#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
12034#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
12036/****************** Bit definition for SAI_xFRCR register *******************/
12037#define SAI_xFRCR_FRL_Pos (0U)
12038#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
12039#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
12040#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
12041#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
12042#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
12043#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
12044#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
12045#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
12046#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
12047#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
12049#define SAI_xFRCR_FSALL_Pos (8U)
12050#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
12051#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
12052#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
12053#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
12054#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
12055#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
12056#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
12057#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
12058#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
12060#define SAI_xFRCR_FSDEF_Pos (16U)
12061#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
12062#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
12063#define SAI_xFRCR_FSPOL_Pos (17U)
12064#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
12065#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
12066#define SAI_xFRCR_FSOFF_Pos (18U)
12067#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
12068#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
12070/* Legacy define */
12071#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
12072
12073/****************** Bit definition for SAI_xSLOTR register *******************/
12074#define SAI_xSLOTR_FBOFF_Pos (0U)
12075#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
12076#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
12077#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
12078#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
12079#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
12080#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
12081#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
12083#define SAI_xSLOTR_SLOTSZ_Pos (6U)
12084#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
12085#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
12086#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
12087#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
12089#define SAI_xSLOTR_NBSLOT_Pos (8U)
12090#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
12091#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
12092#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
12093#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
12094#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
12095#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
12097#define SAI_xSLOTR_SLOTEN_Pos (16U)
12098#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
12099#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
12101/******************* Bit definition for SAI_xIMR register *******************/
12102#define SAI_xIMR_OVRUDRIE_Pos (0U)
12103#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
12104#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
12105#define SAI_xIMR_MUTEDETIE_Pos (1U)
12106#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
12107#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
12108#define SAI_xIMR_WCKCFGIE_Pos (2U)
12109#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
12110#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
12111#define SAI_xIMR_FREQIE_Pos (3U)
12112#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
12113#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
12114#define SAI_xIMR_CNRDYIE_Pos (4U)
12115#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
12116#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
12117#define SAI_xIMR_AFSDETIE_Pos (5U)
12118#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
12119#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
12120#define SAI_xIMR_LFSDETIE_Pos (6U)
12121#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
12122#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
12124/******************** Bit definition for SAI_xSR register *******************/
12125#define SAI_xSR_OVRUDR_Pos (0U)
12126#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
12127#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
12128#define SAI_xSR_MUTEDET_Pos (1U)
12129#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
12130#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
12131#define SAI_xSR_WCKCFG_Pos (2U)
12132#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
12133#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
12134#define SAI_xSR_FREQ_Pos (3U)
12135#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
12136#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
12137#define SAI_xSR_CNRDY_Pos (4U)
12138#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
12139#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
12140#define SAI_xSR_AFSDET_Pos (5U)
12141#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
12142#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
12143#define SAI_xSR_LFSDET_Pos (6U)
12144#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
12145#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
12147#define SAI_xSR_FLVL_Pos (16U)
12148#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
12149#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
12150#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
12151#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
12152#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
12154/****************** Bit definition for SAI_xCLRFR register ******************/
12155#define SAI_xCLRFR_COVRUDR_Pos (0U)
12156#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
12157#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
12158#define SAI_xCLRFR_CMUTEDET_Pos (1U)
12159#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
12160#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
12161#define SAI_xCLRFR_CWCKCFG_Pos (2U)
12162#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
12163#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
12164#define SAI_xCLRFR_CFREQ_Pos (3U)
12165#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
12166#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
12167#define SAI_xCLRFR_CCNRDY_Pos (4U)
12168#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
12169#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
12170#define SAI_xCLRFR_CAFSDET_Pos (5U)
12171#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
12172#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
12173#define SAI_xCLRFR_CLFSDET_Pos (6U)
12174#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
12175#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
12177/****************** Bit definition for SAI_xDR register *********************/
12178#define SAI_xDR_DATA_Pos (0U)
12179#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
12180#define SAI_xDR_DATA SAI_xDR_DATA_Msk
12181
12182/******************************************************************************/
12183/* */
12184/* SPDIF-RX Interface */
12185/* */
12186/******************************************************************************/
12187/******************** Bit definition for SPDIF_CR register *******************/
12188#define SPDIFRX_CR_SPDIFEN_Pos (0U)
12189#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
12190#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk
12191#define SPDIFRX_CR_RXDMAEN_Pos (2U)
12192#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
12193#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk
12194#define SPDIFRX_CR_RXSTEO_Pos (3U)
12195#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
12196#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk
12197#define SPDIFRX_CR_DRFMT_Pos (4U)
12198#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos)
12199#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk
12200#define SPDIFRX_CR_PMSK_Pos (6U)
12201#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos)
12202#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk
12203#define SPDIFRX_CR_VMSK_Pos (7U)
12204#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos)
12205#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk
12206#define SPDIFRX_CR_CUMSK_Pos (8U)
12207#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos)
12208#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk
12209#define SPDIFRX_CR_PTMSK_Pos (9U)
12210#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos)
12211#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk
12212#define SPDIFRX_CR_CBDMAEN_Pos (10U)
12213#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
12214#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk
12215#define SPDIFRX_CR_CHSEL_Pos (11U)
12216#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos)
12217#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk
12218#define SPDIFRX_CR_NBTR_Pos (12U)
12219#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos)
12220#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk
12221#define SPDIFRX_CR_WFA_Pos (14U)
12222#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos)
12223#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk
12224#define SPDIFRX_CR_INSEL_Pos (16U)
12225#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos)
12226#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk
12228/******************* Bit definition for SPDIFRX_IMR register *******************/
12229#define SPDIFRX_IMR_RXNEIE_Pos (0U)
12230#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
12231#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk
12232#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
12233#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
12234#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk
12235#define SPDIFRX_IMR_PERRIE_Pos (2U)
12236#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
12237#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk
12238#define SPDIFRX_IMR_OVRIE_Pos (3U)
12239#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
12240#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk
12241#define SPDIFRX_IMR_SBLKIE_Pos (4U)
12242#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
12243#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk
12244#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
12245#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
12246#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk
12247#define SPDIFRX_IMR_IFEIE_Pos (6U)
12248#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
12249#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk
12251/******************* Bit definition for SPDIFRX_SR register *******************/
12252#define SPDIFRX_SR_RXNE_Pos (0U)
12253#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos)
12254#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk
12255#define SPDIFRX_SR_CSRNE_Pos (1U)
12256#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos)
12257#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk
12258#define SPDIFRX_SR_PERR_Pos (2U)
12259#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos)
12260#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk
12261#define SPDIFRX_SR_OVR_Pos (3U)
12262#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos)
12263#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk
12264#define SPDIFRX_SR_SBD_Pos (4U)
12265#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos)
12266#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk
12267#define SPDIFRX_SR_SYNCD_Pos (5U)
12268#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos)
12269#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk
12270#define SPDIFRX_SR_FERR_Pos (6U)
12271#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos)
12272#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk
12273#define SPDIFRX_SR_SERR_Pos (7U)
12274#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos)
12275#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk
12276#define SPDIFRX_SR_TERR_Pos (8U)
12277#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos)
12278#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk
12279#define SPDIFRX_SR_WIDTH5_Pos (16U)
12280#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
12281#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk
12283/******************* Bit definition for SPDIFRX_IFCR register *******************/
12284#define SPDIFRX_IFCR_PERRCF_Pos (2U)
12285#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
12286#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk
12287#define SPDIFRX_IFCR_OVRCF_Pos (3U)
12288#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
12289#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk
12290#define SPDIFRX_IFCR_SBDCF_Pos (4U)
12291#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
12292#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk
12293#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
12294#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
12295#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk
12297/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
12298#define SPDIFRX_DR0_DR_Pos (0U)
12299#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
12300#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk
12301#define SPDIFRX_DR0_PE_Pos (24U)
12302#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos)
12303#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk
12304#define SPDIFRX_DR0_V_Pos (25U)
12305#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos)
12306#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk
12307#define SPDIFRX_DR0_U_Pos (26U)
12308#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos)
12309#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk
12310#define SPDIFRX_DR0_C_Pos (27U)
12311#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos)
12312#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk
12313#define SPDIFRX_DR0_PT_Pos (28U)
12314#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos)
12315#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk
12317/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
12318#define SPDIFRX_DR1_DR_Pos (8U)
12319#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
12320#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk
12321#define SPDIFRX_DR1_PT_Pos (4U)
12322#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos)
12323#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk
12324#define SPDIFRX_DR1_C_Pos (3U)
12325#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos)
12326#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk
12327#define SPDIFRX_DR1_U_Pos (2U)
12328#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos)
12329#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk
12330#define SPDIFRX_DR1_V_Pos (1U)
12331#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos)
12332#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk
12333#define SPDIFRX_DR1_PE_Pos (0U)
12334#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos)
12335#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk
12337/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
12338#define SPDIFRX_DR1_DRNL1_Pos (16U)
12339#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
12340#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk
12341#define SPDIFRX_DR1_DRNL2_Pos (0U)
12342#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
12343#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk
12345/******************* Bit definition for SPDIFRX_CSR register *******************/
12346#define SPDIFRX_CSR_USR_Pos (0U)
12347#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
12348#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk
12349#define SPDIFRX_CSR_CS_Pos (16U)
12350#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos)
12351#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk
12352#define SPDIFRX_CSR_SOB_Pos (24U)
12353#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos)
12354#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk
12356/******************* Bit definition for SPDIFRX_DIR register *******************/
12357#define SPDIFRX_DIR_THI_Pos (0U)
12358#define SPDIFRX_DIR_THI_Msk (0x13FFUL << SPDIFRX_DIR_THI_Pos)
12359#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk
12360#define SPDIFRX_DIR_TLO_Pos (16U)
12361#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
12362#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk
12364/******************************************************************************/
12365/* */
12366/* SD host Interface */
12367/* */
12368/******************************************************************************/
12369/****************** Bit definition for SDMMC_POWER register ******************/
12370#define SDMMC_POWER_PWRCTRL_Pos (0U)
12371#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
12372#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
12373#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
12374#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
12376/****************** Bit definition for SDMMC_CLKCR register ******************/
12377#define SDMMC_CLKCR_CLKDIV_Pos (0U)
12378#define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)
12379#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
12380#define SDMMC_CLKCR_CLKEN_Pos (8U)
12381#define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos)
12382#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk
12383#define SDMMC_CLKCR_PWRSAV_Pos (9U)
12384#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
12385#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
12386#define SDMMC_CLKCR_BYPASS_Pos (10U)
12387#define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos)
12388#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk
12390#define SDMMC_CLKCR_WIDBUS_Pos (11U)
12391#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
12392#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
12393#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
12394#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
12396#define SDMMC_CLKCR_NEGEDGE_Pos (13U)
12397#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
12398#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
12399#define SDMMC_CLKCR_HWFC_EN_Pos (14U)
12400#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
12401#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
12403/******************* Bit definition for SDMMC_ARG register *******************/
12404#define SDMMC_ARG_CMDARG_Pos (0U)
12405#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
12406#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
12408/******************* Bit definition for SDMMC_CMD register *******************/
12409#define SDMMC_CMD_CMDINDEX_Pos (0U)
12410#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
12411#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
12413#define SDMMC_CMD_WAITRESP_Pos (6U)
12414#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
12415#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
12416#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
12417#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
12419#define SDMMC_CMD_WAITINT_Pos (8U)
12420#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
12421#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
12422#define SDMMC_CMD_WAITPEND_Pos (9U)
12423#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
12424#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
12425#define SDMMC_CMD_CPSMEN_Pos (10U)
12426#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
12427#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
12428#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
12429#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)
12430#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk
12432/***************** Bit definition for SDMMC_RESPCMD register *****************/
12433#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
12434#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
12435#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
12437/****************** Bit definition for SDMMC_RESP0 register ******************/
12438#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
12439#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
12440#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk
12442/****************** Bit definition for SDMMC_RESP1 register ******************/
12443#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
12444#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
12445#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
12447/****************** Bit definition for SDMMC_RESP2 register ******************/
12448#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
12449#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
12450#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
12452/****************** Bit definition for SDMMC_RESP3 register ******************/
12453#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
12454#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
12455#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
12457/****************** Bit definition for SDMMC_RESP4 register ******************/
12458#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
12459#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
12460#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
12462/****************** Bit definition for SDMMC_DTIMER register *****************/
12463#define SDMMC_DTIMER_DATATIME_Pos (0U)
12464#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
12465#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
12467/****************** Bit definition for SDMMC_DLEN register *******************/
12468#define SDMMC_DLEN_DATALENGTH_Pos (0U)
12469#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
12470#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
12472/****************** Bit definition for SDMMC_DCTRL register ******************/
12473#define SDMMC_DCTRL_DTEN_Pos (0U)
12474#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
12475#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
12476#define SDMMC_DCTRL_DTDIR_Pos (1U)
12477#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
12478#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
12479#define SDMMC_DCTRL_DTMODE_Pos (2U)
12480#define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
12481#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
12482#define SDMMC_DCTRL_DMAEN_Pos (3U)
12483#define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos)
12484#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk
12486#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
12487#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12488#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
12489#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12490#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12491#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12492#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12494#define SDMMC_DCTRL_RWSTART_Pos (8U)
12495#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
12496#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
12497#define SDMMC_DCTRL_RWSTOP_Pos (9U)
12498#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
12499#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
12500#define SDMMC_DCTRL_RWMOD_Pos (10U)
12501#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
12502#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
12503#define SDMMC_DCTRL_SDIOEN_Pos (11U)
12504#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
12505#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
12507/****************** Bit definition for SDMMC_DCOUNT register *****************/
12508#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
12509#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
12510#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
12512/****************** Bit definition for SDMMC_STA registe ********************/
12513#define SDMMC_STA_CCRCFAIL_Pos (0U)
12514#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
12515#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
12516#define SDMMC_STA_DCRCFAIL_Pos (1U)
12517#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
12518#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
12519#define SDMMC_STA_CTIMEOUT_Pos (2U)
12520#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
12521#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
12522#define SDMMC_STA_DTIMEOUT_Pos (3U)
12523#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
12524#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
12525#define SDMMC_STA_TXUNDERR_Pos (4U)
12526#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
12527#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
12528#define SDMMC_STA_RXOVERR_Pos (5U)
12529#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
12530#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
12531#define SDMMC_STA_CMDREND_Pos (6U)
12532#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
12533#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
12534#define SDMMC_STA_CMDSENT_Pos (7U)
12535#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
12536#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
12537#define SDMMC_STA_DATAEND_Pos (8U)
12538#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
12539#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
12540#define SDMMC_STA_DBCKEND_Pos (10U)
12541#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
12542#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
12543#define SDMMC_STA_CMDACT_Pos (11U)
12544#define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos)
12545#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk
12546#define SDMMC_STA_TXACT_Pos (12U)
12547#define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos)
12548#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk
12549#define SDMMC_STA_RXACT_Pos (13U)
12550#define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos)
12551#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk
12552#define SDMMC_STA_TXFIFOHE_Pos (14U)
12553#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
12554#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
12555#define SDMMC_STA_RXFIFOHF_Pos (15U)
12556#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
12557#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
12558#define SDMMC_STA_TXFIFOF_Pos (16U)
12559#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
12560#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
12561#define SDMMC_STA_RXFIFOF_Pos (17U)
12562#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
12563#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
12564#define SDMMC_STA_TXFIFOE_Pos (18U)
12565#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
12566#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
12567#define SDMMC_STA_RXFIFOE_Pos (19U)
12568#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
12569#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
12570#define SDMMC_STA_TXDAVL_Pos (20U)
12571#define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos)
12572#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk
12573#define SDMMC_STA_RXDAVL_Pos (21U)
12574#define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos)
12575#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk
12576#define SDMMC_STA_SDIOIT_Pos (22U)
12577#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
12578#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
12580/******************* Bit definition for SDMMC_ICR register *******************/
12581#define SDMMC_ICR_CCRCFAILC_Pos (0U)
12582#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
12583#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
12584#define SDMMC_ICR_DCRCFAILC_Pos (1U)
12585#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
12586#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
12587#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
12588#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
12589#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
12590#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
12591#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
12592#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
12593#define SDMMC_ICR_TXUNDERRC_Pos (4U)
12594#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
12595#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
12596#define SDMMC_ICR_RXOVERRC_Pos (5U)
12597#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
12598#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
12599#define SDMMC_ICR_CMDRENDC_Pos (6U)
12600#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
12601#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
12602#define SDMMC_ICR_CMDSENTC_Pos (7U)
12603#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
12604#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
12605#define SDMMC_ICR_DATAENDC_Pos (8U)
12606#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
12607#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
12608#define SDMMC_ICR_DBCKENDC_Pos (10U)
12609#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
12610#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
12611#define SDMMC_ICR_SDIOITC_Pos (22U)
12612#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
12613#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
12615/****************** Bit definition for SDMMC_MASK register *******************/
12616#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
12617#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
12618#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
12619#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
12620#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
12621#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
12622#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
12623#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
12624#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
12625#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
12626#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
12627#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
12628#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
12629#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
12630#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
12631#define SDMMC_MASK_RXOVERRIE_Pos (5U)
12632#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
12633#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
12634#define SDMMC_MASK_CMDRENDIE_Pos (6U)
12635#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
12636#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
12637#define SDMMC_MASK_CMDSENTIE_Pos (7U)
12638#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
12639#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
12640#define SDMMC_MASK_DATAENDIE_Pos (8U)
12641#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
12642#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
12643#define SDMMC_MASK_DBCKENDIE_Pos (10U)
12644#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
12645#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
12646#define SDMMC_MASK_CMDACTIE_Pos (11U)
12647#define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos)
12648#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk
12649#define SDMMC_MASK_TXACTIE_Pos (12U)
12650#define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos)
12651#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk
12652#define SDMMC_MASK_RXACTIE_Pos (13U)
12653#define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos)
12654#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk
12655#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
12656#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
12657#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
12658#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
12659#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
12660#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
12661#define SDMMC_MASK_TXFIFOFIE_Pos (16U)
12662#define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)
12663#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk
12664#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
12665#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
12666#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
12667#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
12668#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
12669#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
12670#define SDMMC_MASK_RXFIFOEIE_Pos (19U)
12671#define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)
12672#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk
12673#define SDMMC_MASK_TXDAVLIE_Pos (20U)
12674#define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)
12675#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk
12676#define SDMMC_MASK_RXDAVLIE_Pos (21U)
12677#define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)
12678#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk
12679#define SDMMC_MASK_SDIOITIE_Pos (22U)
12680#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
12681#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
12683/***************** Bit definition for SDMMC_FIFOCNT register *****************/
12684#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
12685#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos)
12686#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk
12688/****************** Bit definition for SDMMC_FIFO register *******************/
12689#define SDMMC_FIFO_FIFODATA_Pos (0U)
12690#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
12691#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
12693/******************************************************************************/
12694/* */
12695/* Serial Peripheral Interface (SPI) */
12696/* */
12697/******************************************************************************/
12698/******************* Bit definition for SPI_CR1 register ********************/
12699#define SPI_CR1_CPHA_Pos (0U)
12700#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
12701#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
12702#define SPI_CR1_CPOL_Pos (1U)
12703#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
12704#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
12705#define SPI_CR1_MSTR_Pos (2U)
12706#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
12707#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
12708#define SPI_CR1_BR_Pos (3U)
12709#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
12710#define SPI_CR1_BR SPI_CR1_BR_Msk
12711#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
12712#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
12713#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
12714#define SPI_CR1_SPE_Pos (6U)
12715#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
12716#define SPI_CR1_SPE SPI_CR1_SPE_Msk
12717#define SPI_CR1_LSBFIRST_Pos (7U)
12718#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
12719#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
12720#define SPI_CR1_SSI_Pos (8U)
12721#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
12722#define SPI_CR1_SSI SPI_CR1_SSI_Msk
12723#define SPI_CR1_SSM_Pos (9U)
12724#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
12725#define SPI_CR1_SSM SPI_CR1_SSM_Msk
12726#define SPI_CR1_RXONLY_Pos (10U)
12727#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
12728#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
12729#define SPI_CR1_CRCL_Pos (11U)
12730#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
12731#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
12732#define SPI_CR1_CRCNEXT_Pos (12U)
12733#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
12734#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
12735#define SPI_CR1_CRCEN_Pos (13U)
12736#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
12737#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
12738#define SPI_CR1_BIDIOE_Pos (14U)
12739#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
12740#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
12741#define SPI_CR1_BIDIMODE_Pos (15U)
12742#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
12743#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
12745/******************* Bit definition for SPI_CR2 register ********************/
12746#define SPI_CR2_RXDMAEN_Pos (0U)
12747#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
12748#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
12749#define SPI_CR2_TXDMAEN_Pos (1U)
12750#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
12751#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
12752#define SPI_CR2_SSOE_Pos (2U)
12753#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
12754#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
12755#define SPI_CR2_NSSP_Pos (3U)
12756#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
12757#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
12758#define SPI_CR2_FRF_Pos (4U)
12759#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
12760#define SPI_CR2_FRF SPI_CR2_FRF_Msk
12761#define SPI_CR2_ERRIE_Pos (5U)
12762#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
12763#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
12764#define SPI_CR2_RXNEIE_Pos (6U)
12765#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
12766#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
12767#define SPI_CR2_TXEIE_Pos (7U)
12768#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
12769#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
12770#define SPI_CR2_DS_Pos (8U)
12771#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
12772#define SPI_CR2_DS SPI_CR2_DS_Msk
12773#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
12774#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
12775#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
12776#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
12777#define SPI_CR2_FRXTH_Pos (12U)
12778#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
12779#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
12780#define SPI_CR2_LDMARX_Pos (13U)
12781#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
12782#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
12783#define SPI_CR2_LDMATX_Pos (14U)
12784#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
12785#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
12787/******************** Bit definition for SPI_SR register ********************/
12788#define SPI_SR_RXNE_Pos (0U)
12789#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
12790#define SPI_SR_RXNE SPI_SR_RXNE_Msk
12791#define SPI_SR_TXE_Pos (1U)
12792#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
12793#define SPI_SR_TXE SPI_SR_TXE_Msk
12794#define SPI_SR_CHSIDE_Pos (2U)
12795#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
12796#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
12797#define SPI_SR_UDR_Pos (3U)
12798#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
12799#define SPI_SR_UDR SPI_SR_UDR_Msk
12800#define SPI_SR_CRCERR_Pos (4U)
12801#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
12802#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
12803#define SPI_SR_MODF_Pos (5U)
12804#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
12805#define SPI_SR_MODF SPI_SR_MODF_Msk
12806#define SPI_SR_OVR_Pos (6U)
12807#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
12808#define SPI_SR_OVR SPI_SR_OVR_Msk
12809#define SPI_SR_BSY_Pos (7U)
12810#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
12811#define SPI_SR_BSY SPI_SR_BSY_Msk
12812#define SPI_SR_FRE_Pos (8U)
12813#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
12814#define SPI_SR_FRE SPI_SR_FRE_Msk
12815#define SPI_SR_FRLVL_Pos (9U)
12816#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
12817#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
12818#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
12819#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
12820#define SPI_SR_FTLVL_Pos (11U)
12821#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
12822#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
12823#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
12824#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
12826/******************** Bit definition for SPI_DR register ********************/
12827#define SPI_DR_DR_Pos (0U)
12828#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
12829#define SPI_DR_DR SPI_DR_DR_Msk
12831/******************* Bit definition for SPI_CRCPR register ******************/
12832#define SPI_CRCPR_CRCPOLY_Pos (0U)
12833#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
12834#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
12836/****************** Bit definition for SPI_RXCRCR register ******************/
12837#define SPI_RXCRCR_RXCRC_Pos (0U)
12838#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
12839#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
12841/****************** Bit definition for SPI_TXCRCR register ******************/
12842#define SPI_TXCRCR_TXCRC_Pos (0U)
12843#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
12844#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
12846/****************** Bit definition for SPI_I2SCFGR register *****************/
12847#define SPI_I2SCFGR_CHLEN_Pos (0U)
12848#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
12849#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
12850#define SPI_I2SCFGR_DATLEN_Pos (1U)
12851#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
12852#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
12853#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
12854#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
12855#define SPI_I2SCFGR_CKPOL_Pos (3U)
12856#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
12857#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
12858#define SPI_I2SCFGR_I2SSTD_Pos (4U)
12859#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
12860#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
12861#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
12862#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
12863#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
12864#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
12865#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
12866#define SPI_I2SCFGR_I2SCFG_Pos (8U)
12867#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
12868#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
12869#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
12870#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
12871#define SPI_I2SCFGR_I2SE_Pos (10U)
12872#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
12873#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
12874#define SPI_I2SCFGR_I2SMOD_Pos (11U)
12875#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
12876#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
12877#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
12878#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
12879#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
12881/****************** Bit definition for SPI_I2SPR register *******************/
12882#define SPI_I2SPR_I2SDIV_Pos (0U)
12883#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
12884#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
12885#define SPI_I2SPR_ODD_Pos (8U)
12886#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
12887#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
12888#define SPI_I2SPR_MCKOE_Pos (9U)
12889#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
12890#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
12893/******************************************************************************/
12894/* */
12895/* SYSCFG */
12896/* */
12897/******************************************************************************/
12898/****************** Bit definition for SYSCFG_MEMRMP register ***************/
12899#define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U)
12900#define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1UL << SYSCFG_MEMRMP_MEM_BOOT_Pos)
12901#define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk
12904#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
12905#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
12906#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk
12907#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
12908#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
12910/****************** Bit definition for SYSCFG_PMC register ******************/
12911#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
12912#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos)
12913#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk
12914#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
12915#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos)
12916#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk
12917#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
12918#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos)
12919#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk
12920#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
12921#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos)
12922#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk
12923#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
12924#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos)
12925#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk
12926#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
12927#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos)
12928#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk
12929#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
12930#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos)
12931#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk
12932#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
12933#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos)
12934#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk
12936#define SYSCFG_PMC_ADCxDC2_Pos (16U)
12937#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)
12938#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk
12939#define SYSCFG_PMC_ADC1DC2_Pos (16U)
12940#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
12941#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
12942#define SYSCFG_PMC_ADC2DC2_Pos (17U)
12943#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)
12944#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk
12945#define SYSCFG_PMC_ADC3DC2_Pos (18U)
12946#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)
12947#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk
12949#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
12950#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
12951#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
12953/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
12954#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
12955#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
12956#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
12957#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
12958#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
12959#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
12960#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
12961#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
12962#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
12963#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
12964#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
12965#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
12969#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
12970#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
12971#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
12972#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
12973#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
12974#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
12975#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
12976#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
12977#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
12978#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
12979#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
12984#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
12985#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
12986#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
12987#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
12988#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
12989#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
12990#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
12991#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
12992#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
12993#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
12994#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
12999#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
13000#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
13001#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
13002#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
13003#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
13004#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
13005#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
13006#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
13007#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
13008#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
13009#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
13014#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
13015#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
13016#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
13017#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
13018#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
13019#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
13020#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
13021#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
13022#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
13023#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
13024#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
13026/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
13027#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
13028#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
13029#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
13030#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
13031#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
13032#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
13033#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
13034#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
13035#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
13036#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
13037#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
13038#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
13042#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
13043#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
13044#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
13045#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
13046#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
13047#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
13048#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
13049#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
13050#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
13051#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
13052#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
13057#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
13058#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
13059#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
13060#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
13061#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
13062#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
13063#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
13064#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
13065#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
13066#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
13067#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
13072#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
13073#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
13074#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
13075#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
13076#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
13077#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
13078#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
13079#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
13080#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
13081#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
13082#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
13087#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
13088#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
13089#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
13090#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
13091#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
13092#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
13093#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
13094#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
13095#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
13096#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
13097#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
13099/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
13100#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
13101#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
13102#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
13103#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
13104#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
13105#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
13106#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
13107#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
13108#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
13109#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
13110#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
13111#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
13116#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
13117#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
13118#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
13119#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
13120#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
13121#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
13122#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
13123#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
13124#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
13125#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
13130#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
13131#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
13132#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
13133#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
13134#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
13135#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
13136#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
13137#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
13138#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
13139#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
13144#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
13145#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
13146#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
13147#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
13148#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
13149#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
13150#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
13151#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
13152#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
13153#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
13158#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
13159#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
13160#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
13161#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
13162#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
13163#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
13164#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
13165#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
13166#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
13167#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
13170/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13171#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13172#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
13173#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
13174#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13175#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
13176#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
13177#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13178#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
13179#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
13180#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13181#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
13182#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
13186#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
13187#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
13188#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
13189#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
13190#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
13191#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
13192#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
13193#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
13194#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
13195#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
13200#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
13201#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
13202#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
13203#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
13204#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
13205#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
13206#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
13207#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
13208#define SYSCFG_EXTICR4_EXTI13_PI 0x0080U
13209#define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U
13214#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
13215#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
13216#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
13217#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
13218#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
13219#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
13220#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
13221#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
13222#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
13223#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
13228#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
13229#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
13230#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
13231#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
13232#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
13233#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
13234#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
13235#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
13236#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
13237#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
13240/****************** Bit definition for SYSCFG_CMPCR register ****************/
13241#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
13242#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
13243#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
13244#define SYSCFG_CMPCR_READY_Pos (8U)
13245#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
13246#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
13248/******************************************************************************/
13249/* */
13250/* TIM */
13251/* */
13252/******************************************************************************/
13253/******************* Bit definition for TIM_CR1 register ********************/
13254#define TIM_CR1_CEN_Pos (0U)
13255#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
13256#define TIM_CR1_CEN TIM_CR1_CEN_Msk
13257#define TIM_CR1_UDIS_Pos (1U)
13258#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
13259#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
13260#define TIM_CR1_URS_Pos (2U)
13261#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
13262#define TIM_CR1_URS TIM_CR1_URS_Msk
13263#define TIM_CR1_OPM_Pos (3U)
13264#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
13265#define TIM_CR1_OPM TIM_CR1_OPM_Msk
13266#define TIM_CR1_DIR_Pos (4U)
13267#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
13268#define TIM_CR1_DIR TIM_CR1_DIR_Msk
13270#define TIM_CR1_CMS_Pos (5U)
13271#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
13272#define TIM_CR1_CMS TIM_CR1_CMS_Msk
13273#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
13274#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
13276#define TIM_CR1_ARPE_Pos (7U)
13277#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
13278#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
13280#define TIM_CR1_CKD_Pos (8U)
13281#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
13282#define TIM_CR1_CKD TIM_CR1_CKD_Msk
13283#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
13284#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
13285#define TIM_CR1_UIFREMAP_Pos (11U)
13286#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
13287#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
13289/******************* Bit definition for TIM_CR2 register ********************/
13290#define TIM_CR2_CCPC_Pos (0U)
13291#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
13292#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
13293#define TIM_CR2_CCUS_Pos (2U)
13294#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
13295#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
13296#define TIM_CR2_CCDS_Pos (3U)
13297#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
13298#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
13300#define TIM_CR2_OIS5_Pos (16U)
13301#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
13302#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
13303#define TIM_CR2_OIS6_Pos (18U)
13304#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
13305#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
13307#define TIM_CR2_MMS_Pos (4U)
13308#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
13309#define TIM_CR2_MMS TIM_CR2_MMS_Msk
13310#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
13311#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
13312#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
13314#define TIM_CR2_MMS2_Pos (20U)
13315#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
13316#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
13317#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
13318#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
13319#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
13320#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
13322#define TIM_CR2_TI1S_Pos (7U)
13323#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
13324#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
13325#define TIM_CR2_OIS1_Pos (8U)
13326#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
13327#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
13328#define TIM_CR2_OIS1N_Pos (9U)
13329#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
13330#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
13331#define TIM_CR2_OIS2_Pos (10U)
13332#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
13333#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
13334#define TIM_CR2_OIS2N_Pos (11U)
13335#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
13336#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
13337#define TIM_CR2_OIS3_Pos (12U)
13338#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
13339#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
13340#define TIM_CR2_OIS3N_Pos (13U)
13341#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
13342#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
13343#define TIM_CR2_OIS4_Pos (14U)
13344#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
13345#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
13347/******************* Bit definition for TIM_SMCR register *******************/
13348#define TIM_SMCR_SMS_Pos (0U)
13349#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
13350#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
13351#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
13352#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
13353#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
13354#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
13356#define TIM_SMCR_TS_Pos (4U)
13357#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
13358#define TIM_SMCR_TS TIM_SMCR_TS_Msk
13359#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
13360#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
13361#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
13363#define TIM_SMCR_MSM_Pos (7U)
13364#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
13365#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
13367#define TIM_SMCR_ETF_Pos (8U)
13368#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
13369#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
13370#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
13371#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
13372#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
13373#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
13375#define TIM_SMCR_ETPS_Pos (12U)
13376#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
13377#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
13378#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
13379#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
13381#define TIM_SMCR_ECE_Pos (14U)
13382#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
13383#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
13384#define TIM_SMCR_ETP_Pos (15U)
13385#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
13386#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
13388/******************* Bit definition for TIM_DIER register *******************/
13389#define TIM_DIER_UIE_Pos (0U)
13390#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
13391#define TIM_DIER_UIE TIM_DIER_UIE_Msk
13392#define TIM_DIER_CC1IE_Pos (1U)
13393#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
13394#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
13395#define TIM_DIER_CC2IE_Pos (2U)
13396#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
13397#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
13398#define TIM_DIER_CC3IE_Pos (3U)
13399#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
13400#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
13401#define TIM_DIER_CC4IE_Pos (4U)
13402#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
13403#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
13404#define TIM_DIER_COMIE_Pos (5U)
13405#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
13406#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
13407#define TIM_DIER_TIE_Pos (6U)
13408#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
13409#define TIM_DIER_TIE TIM_DIER_TIE_Msk
13410#define TIM_DIER_BIE_Pos (7U)
13411#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
13412#define TIM_DIER_BIE TIM_DIER_BIE_Msk
13413#define TIM_DIER_UDE_Pos (8U)
13414#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
13415#define TIM_DIER_UDE TIM_DIER_UDE_Msk
13416#define TIM_DIER_CC1DE_Pos (9U)
13417#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
13418#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
13419#define TIM_DIER_CC2DE_Pos (10U)
13420#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
13421#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
13422#define TIM_DIER_CC3DE_Pos (11U)
13423#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
13424#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
13425#define TIM_DIER_CC4DE_Pos (12U)
13426#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
13427#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
13428#define TIM_DIER_COMDE_Pos (13U)
13429#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
13430#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
13431#define TIM_DIER_TDE_Pos (14U)
13432#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
13433#define TIM_DIER_TDE TIM_DIER_TDE_Msk
13435/******************** Bit definition for TIM_SR register ********************/
13436#define TIM_SR_UIF_Pos (0U)
13437#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
13438#define TIM_SR_UIF TIM_SR_UIF_Msk
13439#define TIM_SR_CC1IF_Pos (1U)
13440#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
13441#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
13442#define TIM_SR_CC2IF_Pos (2U)
13443#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
13444#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
13445#define TIM_SR_CC3IF_Pos (3U)
13446#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
13447#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
13448#define TIM_SR_CC4IF_Pos (4U)
13449#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
13450#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
13451#define TIM_SR_COMIF_Pos (5U)
13452#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
13453#define TIM_SR_COMIF TIM_SR_COMIF_Msk
13454#define TIM_SR_TIF_Pos (6U)
13455#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
13456#define TIM_SR_TIF TIM_SR_TIF_Msk
13457#define TIM_SR_BIF_Pos (7U)
13458#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
13459#define TIM_SR_BIF TIM_SR_BIF_Msk
13460#define TIM_SR_B2IF_Pos (8U)
13461#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
13462#define TIM_SR_B2IF TIM_SR_B2IF_Msk
13463#define TIM_SR_CC1OF_Pos (9U)
13464#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
13465#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
13466#define TIM_SR_CC2OF_Pos (10U)
13467#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
13468#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
13469#define TIM_SR_CC3OF_Pos (11U)
13470#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
13471#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
13472#define TIM_SR_CC4OF_Pos (12U)
13473#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
13474#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
13475#define TIM_SR_SBIF_Pos (13U)
13476#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
13477#define TIM_SR_SBIF TIM_SR_SBIF_Msk
13478#define TIM_SR_CC5IF_Pos (16U)
13479#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
13480#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
13481#define TIM_SR_CC6IF_Pos (17U)
13482#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
13483#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
13485/******************* Bit definition for TIM_EGR register ********************/
13486#define TIM_EGR_UG_Pos (0U)
13487#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
13488#define TIM_EGR_UG TIM_EGR_UG_Msk
13489#define TIM_EGR_CC1G_Pos (1U)
13490#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
13491#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
13492#define TIM_EGR_CC2G_Pos (2U)
13493#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
13494#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
13495#define TIM_EGR_CC3G_Pos (3U)
13496#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
13497#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
13498#define TIM_EGR_CC4G_Pos (4U)
13499#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
13500#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
13501#define TIM_EGR_COMG_Pos (5U)
13502#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
13503#define TIM_EGR_COMG TIM_EGR_COMG_Msk
13504#define TIM_EGR_TG_Pos (6U)
13505#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
13506#define TIM_EGR_TG TIM_EGR_TG_Msk
13507#define TIM_EGR_BG_Pos (7U)
13508#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
13509#define TIM_EGR_BG TIM_EGR_BG_Msk
13510#define TIM_EGR_B2G_Pos (8U)
13511#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
13512#define TIM_EGR_B2G TIM_EGR_B2G_Msk
13514/****************** Bit definition for TIM_CCMR1 register *******************/
13515#define TIM_CCMR1_CC1S_Pos (0U)
13516#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
13517#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
13518#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
13519#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
13521#define TIM_CCMR1_OC1FE_Pos (2U)
13522#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
13523#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
13524#define TIM_CCMR1_OC1PE_Pos (3U)
13525#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
13526#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
13528#define TIM_CCMR1_OC1M_Pos (4U)
13529#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
13530#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
13531#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
13532#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
13533#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
13534#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
13536#define TIM_CCMR1_OC1CE_Pos (7U)
13537#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
13538#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
13540#define TIM_CCMR1_CC2S_Pos (8U)
13541#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
13542#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
13543#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
13544#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
13546#define TIM_CCMR1_OC2FE_Pos (10U)
13547#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
13548#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
13549#define TIM_CCMR1_OC2PE_Pos (11U)
13550#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
13551#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
13553#define TIM_CCMR1_OC2M_Pos (12U)
13554#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
13555#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
13556#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
13557#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
13558#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
13559#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
13561#define TIM_CCMR1_OC2CE_Pos (15U)
13562#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
13563#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
13565/*----------------------------------------------------------------------------*/
13566
13567#define TIM_CCMR1_IC1PSC_Pos (2U)
13568#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
13569#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
13570#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
13571#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
13573#define TIM_CCMR1_IC1F_Pos (4U)
13574#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
13575#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
13576#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
13577#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
13578#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
13579#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
13581#define TIM_CCMR1_IC2PSC_Pos (10U)
13582#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
13583#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
13584#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
13585#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
13587#define TIM_CCMR1_IC2F_Pos (12U)
13588#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
13589#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
13590#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
13591#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
13592#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
13593#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
13595/****************** Bit definition for TIM_CCMR2 register *******************/
13596#define TIM_CCMR2_CC3S_Pos (0U)
13597#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
13598#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
13599#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
13600#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
13602#define TIM_CCMR2_OC3FE_Pos (2U)
13603#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
13604#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
13605#define TIM_CCMR2_OC3PE_Pos (3U)
13606#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
13607#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
13609#define TIM_CCMR2_OC3M_Pos (4U)
13610#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
13611#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
13612#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)
13613#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)
13614#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)
13615#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
13619#define TIM_CCMR2_OC3CE_Pos (7U)
13620#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
13621#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
13623#define TIM_CCMR2_CC4S_Pos (8U)
13624#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
13625#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
13626#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
13627#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
13629#define TIM_CCMR2_OC4FE_Pos (10U)
13630#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
13631#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
13632#define TIM_CCMR2_OC4PE_Pos (11U)
13633#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
13634#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
13636#define TIM_CCMR2_OC4M_Pos (12U)
13637#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
13638#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
13639#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)
13640#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)
13641#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)
13642#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
13644#define TIM_CCMR2_OC4CE_Pos (15U)
13645#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
13646#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
13648/*----------------------------------------------------------------------------*/
13649
13650#define TIM_CCMR2_IC3PSC_Pos (2U)
13651#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
13652#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
13653#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
13654#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
13656#define TIM_CCMR2_IC3F_Pos (4U)
13657#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
13658#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
13659#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
13660#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
13661#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
13662#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
13664#define TIM_CCMR2_IC4PSC_Pos (10U)
13665#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
13666#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
13667#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
13668#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
13670#define TIM_CCMR2_IC4F_Pos (12U)
13671#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
13672#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
13673#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
13674#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
13675#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
13676#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
13678/******************* Bit definition for TIM_CCER register *******************/
13679#define TIM_CCER_CC1E_Pos (0U)
13680#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
13681#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
13682#define TIM_CCER_CC1P_Pos (1U)
13683#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
13684#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
13685#define TIM_CCER_CC1NE_Pos (2U)
13686#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
13687#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
13688#define TIM_CCER_CC1NP_Pos (3U)
13689#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
13690#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
13691#define TIM_CCER_CC2E_Pos (4U)
13692#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
13693#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
13694#define TIM_CCER_CC2P_Pos (5U)
13695#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
13696#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
13697#define TIM_CCER_CC2NE_Pos (6U)
13698#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
13699#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
13700#define TIM_CCER_CC2NP_Pos (7U)
13701#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
13702#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
13703#define TIM_CCER_CC3E_Pos (8U)
13704#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
13705#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
13706#define TIM_CCER_CC3P_Pos (9U)
13707#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
13708#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
13709#define TIM_CCER_CC3NE_Pos (10U)
13710#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
13711#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
13712#define TIM_CCER_CC3NP_Pos (11U)
13713#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
13714#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
13715#define TIM_CCER_CC4E_Pos (12U)
13716#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
13717#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
13718#define TIM_CCER_CC4P_Pos (13U)
13719#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
13720#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
13721#define TIM_CCER_CC4NP_Pos (15U)
13722#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
13723#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
13724#define TIM_CCER_CC5E_Pos (16U)
13725#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
13726#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
13727#define TIM_CCER_CC5P_Pos (17U)
13728#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
13729#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
13730#define TIM_CCER_CC6E_Pos (20U)
13731#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
13732#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
13733#define TIM_CCER_CC6P_Pos (21U)
13734#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
13735#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
13738/******************* Bit definition for TIM_CNT register ********************/
13739#define TIM_CNT_CNT_Pos (0U)
13740#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
13741#define TIM_CNT_CNT TIM_CNT_CNT_Msk
13742#define TIM_CNT_UIFCPY_Pos (31U)
13743#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
13744#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
13746/******************* Bit definition for TIM_PSC register ********************/
13747#define TIM_PSC_PSC_Pos (0U)
13748#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
13749#define TIM_PSC_PSC TIM_PSC_PSC_Msk
13751/******************* Bit definition for TIM_ARR register ********************/
13752#define TIM_ARR_ARR_Pos (0U)
13753#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
13754#define TIM_ARR_ARR TIM_ARR_ARR_Msk
13756/******************* Bit definition for TIM_RCR register ********************/
13757#define TIM_RCR_REP_Pos (0U)
13758#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)
13759#define TIM_RCR_REP TIM_RCR_REP_Msk
13761/******************* Bit definition for TIM_CCR1 register *******************/
13762#define TIM_CCR1_CCR1_Pos (0U)
13763#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
13764#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
13766/******************* Bit definition for TIM_CCR2 register *******************/
13767#define TIM_CCR2_CCR2_Pos (0U)
13768#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
13769#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
13771/******************* Bit definition for TIM_CCR3 register *******************/
13772#define TIM_CCR3_CCR3_Pos (0U)
13773#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
13774#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
13776/******************* Bit definition for TIM_CCR4 register *******************/
13777#define TIM_CCR4_CCR4_Pos (0U)
13778#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
13779#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
13781/******************* Bit definition for TIM_BDTR register *******************/
13782#define TIM_BDTR_DTG_Pos (0U)
13783#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
13784#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
13785#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
13786#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
13787#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
13788#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
13789#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
13790#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
13791#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
13792#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
13794#define TIM_BDTR_LOCK_Pos (8U)
13795#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
13796#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
13797#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
13798#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
13800#define TIM_BDTR_OSSI_Pos (10U)
13801#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
13802#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
13803#define TIM_BDTR_OSSR_Pos (11U)
13804#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
13805#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
13806#define TIM_BDTR_BKE_Pos (12U)
13807#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
13808#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
13809#define TIM_BDTR_BKP_Pos (13U)
13810#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
13811#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
13812#define TIM_BDTR_AOE_Pos (14U)
13813#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
13814#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
13815#define TIM_BDTR_MOE_Pos (15U)
13816#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
13817#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
13818#define TIM_BDTR_BKF_Pos (16U)
13819#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
13820#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
13821#define TIM_BDTR_BK2F_Pos (20U)
13822#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
13823#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
13824#define TIM_BDTR_BK2E_Pos (24U)
13825#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
13826#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
13827#define TIM_BDTR_BK2P_Pos (25U)
13828#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
13829#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
13831/******************* Bit definition for TIM_DCR register ********************/
13832#define TIM_DCR_DBA_Pos (0U)
13833#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
13834#define TIM_DCR_DBA TIM_DCR_DBA_Msk
13835#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
13836#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
13837#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
13838#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
13839#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
13841#define TIM_DCR_DBL_Pos (8U)
13842#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
13843#define TIM_DCR_DBL TIM_DCR_DBL_Msk
13844#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
13845#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
13846#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
13847#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
13848#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
13850/******************* Bit definition for TIM_DMAR register *******************/
13851#define TIM_DMAR_DMAB_Pos (0U)
13852#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
13853#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
13855/******************* Bit definition for TIM_OR regiter *********************/
13856#define TIM_OR_TI4_RMP_Pos (6U)
13857#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
13858#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
13859#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
13860#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
13861#define TIM_OR_ITR1_RMP_Pos (10U)
13862#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
13863#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
13864#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
13865#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
13867/******************* Bit definition for TIM2_OR register *******************/
13868#define TIM2_OR_ITR1_RMP_Pos (10U)
13869#define TIM2_OR_ITR1_RMP_Msk (0x3UL << TIM2_OR_ITR1_RMP_Pos)
13870#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk
13871#define TIM2_OR_ITR1_RMP_0 (0x1UL << TIM2_OR_ITR1_RMP_Pos)
13872#define TIM2_OR_ITR1_RMP_1 (0x2UL << TIM2_OR_ITR1_RMP_Pos)
13874/******************* Bit definition for TIM5_OR register *******************/
13875#define TIM5_OR_TI4_RMP_Pos (6U)
13876#define TIM5_OR_TI4_RMP_Msk (0x3UL << TIM5_OR_TI4_RMP_Pos)
13877#define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk
13878#define TIM5_OR_TI4_RMP_0 (0x1UL << TIM5_OR_TI4_RMP_Pos)
13879#define TIM5_OR_TI4_RMP_1 (0x2UL << TIM5_OR_TI4_RMP_Pos)
13881/******************* Bit definition for TIM11_OR register *******************/
13882#define TIM11_OR_TI1_RMP_Pos (0U)
13883#define TIM11_OR_TI1_RMP_Msk (0x3UL << TIM11_OR_TI1_RMP_Pos)
13884#define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk
13885#define TIM11_OR_TI1_RMP_0 (0x1UL << TIM11_OR_TI1_RMP_Pos)
13886#define TIM11_OR_TI1_RMP_1 (0x2UL << TIM11_OR_TI1_RMP_Pos)
13888/****************** Bit definition for TIM_CCMR3 register *******************/
13889#define TIM_CCMR3_OC5FE_Pos (2U)
13890#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
13891#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
13892#define TIM_CCMR3_OC5PE_Pos (3U)
13893#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
13894#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
13896#define TIM_CCMR3_OC5M_Pos (4U)
13897#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
13898#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
13899#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)
13900#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)
13901#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)
13902#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
13904#define TIM_CCMR3_OC5CE_Pos (7U)
13905#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
13906#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
13908#define TIM_CCMR3_OC6FE_Pos (10U)
13909#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
13910#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
13911#define TIM_CCMR3_OC6PE_Pos (11U)
13912#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
13913#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
13915#define TIM_CCMR3_OC6M_Pos (12U)
13916#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
13917#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
13918#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)
13919#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)
13920#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)
13921#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
13923#define TIM_CCMR3_OC6CE_Pos (15U)
13924#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
13925#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
13927/******************* Bit definition for TIM_CCR5 register *******************/
13928#define TIM_CCR5_CCR5_Pos (0U)
13929#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
13930#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
13931#define TIM_CCR5_GC5C1_Pos (29U)
13932#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
13933#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
13934#define TIM_CCR5_GC5C2_Pos (30U)
13935#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
13936#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
13937#define TIM_CCR5_GC5C3_Pos (31U)
13938#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
13939#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
13941/******************* Bit definition for TIM_CCR6 register *******************/
13942#define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU)
13945/******************************************************************************/
13946/* */
13947/* Low Power Timer (LPTIM) */
13948/* */
13949/******************************************************************************/
13950/****************** Bit definition for LPTIM_ISR register *******************/
13951#define LPTIM_ISR_CMPM_Pos (0U)
13952#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
13953#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
13954#define LPTIM_ISR_ARRM_Pos (1U)
13955#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
13956#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
13957#define LPTIM_ISR_EXTTRIG_Pos (2U)
13958#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
13959#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
13960#define LPTIM_ISR_CMPOK_Pos (3U)
13961#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
13962#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
13963#define LPTIM_ISR_ARROK_Pos (4U)
13964#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
13965#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
13966#define LPTIM_ISR_UP_Pos (5U)
13967#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
13968#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
13969#define LPTIM_ISR_DOWN_Pos (6U)
13970#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
13971#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
13973/****************** Bit definition for LPTIM_ICR register *******************/
13974#define LPTIM_ICR_CMPMCF_Pos (0U)
13975#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
13976#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
13977#define LPTIM_ICR_ARRMCF_Pos (1U)
13978#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
13979#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
13980#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
13981#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
13982#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
13983#define LPTIM_ICR_CMPOKCF_Pos (3U)
13984#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
13985#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
13986#define LPTIM_ICR_ARROKCF_Pos (4U)
13987#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
13988#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
13989#define LPTIM_ICR_UPCF_Pos (5U)
13990#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
13991#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
13992#define LPTIM_ICR_DOWNCF_Pos (6U)
13993#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
13994#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
13996/****************** Bit definition for LPTIM_IER register *******************/
13997#define LPTIM_IER_CMPMIE_Pos (0U)
13998#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
13999#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
14000#define LPTIM_IER_ARRMIE_Pos (1U)
14001#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
14002#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
14003#define LPTIM_IER_EXTTRIGIE_Pos (2U)
14004#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
14005#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
14006#define LPTIM_IER_CMPOKIE_Pos (3U)
14007#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
14008#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
14009#define LPTIM_IER_ARROKIE_Pos (4U)
14010#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
14011#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
14012#define LPTIM_IER_UPIE_Pos (5U)
14013#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
14014#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
14015#define LPTIM_IER_DOWNIE_Pos (6U)
14016#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
14017#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
14019/****************** Bit definition for LPTIM_CFGR register*******************/
14020#define LPTIM_CFGR_CKSEL_Pos (0U)
14021#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
14022#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
14024#define LPTIM_CFGR_CKPOL_Pos (1U)
14025#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
14026#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
14027#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
14028#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
14030#define LPTIM_CFGR_CKFLT_Pos (3U)
14031#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
14032#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
14033#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
14034#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
14036#define LPTIM_CFGR_TRGFLT_Pos (6U)
14037#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
14038#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
14039#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
14040#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
14042#define LPTIM_CFGR_PRESC_Pos (9U)
14043#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
14044#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
14045#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
14046#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
14047#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
14049#define LPTIM_CFGR_TRIGSEL_Pos (13U)
14050#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
14051#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
14052#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
14053#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
14054#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
14056#define LPTIM_CFGR_TRIGEN_Pos (17U)
14057#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
14058#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
14059#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
14060#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
14062#define LPTIM_CFGR_TIMOUT_Pos (19U)
14063#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
14064#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
14065#define LPTIM_CFGR_WAVE_Pos (20U)
14066#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
14067#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
14068#define LPTIM_CFGR_WAVPOL_Pos (21U)
14069#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
14070#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
14071#define LPTIM_CFGR_PRELOAD_Pos (22U)
14072#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
14073#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
14074#define LPTIM_CFGR_COUNTMODE_Pos (23U)
14075#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
14076#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
14077#define LPTIM_CFGR_ENC_Pos (24U)
14078#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
14079#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
14081/****************** Bit definition for LPTIM_CR register ********************/
14082#define LPTIM_CR_ENABLE_Pos (0U)
14083#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
14084#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
14085#define LPTIM_CR_SNGSTRT_Pos (1U)
14086#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
14087#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
14088#define LPTIM_CR_CNTSTRT_Pos (2U)
14089#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
14090#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
14092/****************** Bit definition for LPTIM_CMP register *******************/
14093#define LPTIM_CMP_CMP_Pos (0U)
14094#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
14095#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
14097/****************** Bit definition for LPTIM_ARR register *******************/
14098#define LPTIM_ARR_ARR_Pos (0U)
14099#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
14100#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
14102/****************** Bit definition for LPTIM_CNT register *******************/
14103#define LPTIM_CNT_CNT_Pos (0U)
14104#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
14105#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
14106/******************************************************************************/
14107/* */
14108/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
14109/* */
14110/******************************************************************************/
14111/****************** Bit definition for USART_CR1 register *******************/
14112#define USART_CR1_UE_Pos (0U)
14113#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
14114#define USART_CR1_UE USART_CR1_UE_Msk
14115#define USART_CR1_RE_Pos (2U)
14116#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
14117#define USART_CR1_RE USART_CR1_RE_Msk
14118#define USART_CR1_TE_Pos (3U)
14119#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
14120#define USART_CR1_TE USART_CR1_TE_Msk
14121#define USART_CR1_IDLEIE_Pos (4U)
14122#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
14123#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
14124#define USART_CR1_RXNEIE_Pos (5U)
14125#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
14126#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
14127#define USART_CR1_TCIE_Pos (6U)
14128#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
14129#define USART_CR1_TCIE USART_CR1_TCIE_Msk
14130#define USART_CR1_TXEIE_Pos (7U)
14131#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
14132#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
14133#define USART_CR1_PEIE_Pos (8U)
14134#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
14135#define USART_CR1_PEIE USART_CR1_PEIE_Msk
14136#define USART_CR1_PS_Pos (9U)
14137#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
14138#define USART_CR1_PS USART_CR1_PS_Msk
14139#define USART_CR1_PCE_Pos (10U)
14140#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
14141#define USART_CR1_PCE USART_CR1_PCE_Msk
14142#define USART_CR1_WAKE_Pos (11U)
14143#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
14144#define USART_CR1_WAKE USART_CR1_WAKE_Msk
14145#define USART_CR1_M_Pos (12U)
14146#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
14147#define USART_CR1_M USART_CR1_M_Msk
14148#define USART_CR1_M0 (0x00001UL << USART_CR1_M_Pos)
14149#define USART_CR1_MME_Pos (13U)
14150#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
14151#define USART_CR1_MME USART_CR1_MME_Msk
14152#define USART_CR1_CMIE_Pos (14U)
14153#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
14154#define USART_CR1_CMIE USART_CR1_CMIE_Msk
14155#define USART_CR1_OVER8_Pos (15U)
14156#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
14157#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
14158#define USART_CR1_DEDT_Pos (16U)
14159#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
14160#define USART_CR1_DEDT USART_CR1_DEDT_Msk
14161#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
14162#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
14163#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
14164#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
14165#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
14166#define USART_CR1_DEAT_Pos (21U)
14167#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
14168#define USART_CR1_DEAT USART_CR1_DEAT_Msk
14169#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
14170#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
14171#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
14172#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
14173#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
14174#define USART_CR1_RTOIE_Pos (26U)
14175#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
14176#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
14177#define USART_CR1_EOBIE_Pos (27U)
14178#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
14179#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
14180#define USART_CR1_M1 0x10000000U
14182/* Legacy defines */
14183#define USART_CR1_M_0 USART_CR1_M0
14184#define USART_CR1_M_1 USART_CR1_M1
14186/****************** Bit definition for USART_CR2 register *******************/
14187#define USART_CR2_ADDM7_Pos (4U)
14188#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
14189#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
14190#define USART_CR2_LBDL_Pos (5U)
14191#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
14192#define USART_CR2_LBDL USART_CR2_LBDL_Msk
14193#define USART_CR2_LBDIE_Pos (6U)
14194#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
14195#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
14196#define USART_CR2_LBCL_Pos (8U)
14197#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
14198#define USART_CR2_LBCL USART_CR2_LBCL_Msk
14199#define USART_CR2_CPHA_Pos (9U)
14200#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
14201#define USART_CR2_CPHA USART_CR2_CPHA_Msk
14202#define USART_CR2_CPOL_Pos (10U)
14203#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
14204#define USART_CR2_CPOL USART_CR2_CPOL_Msk
14205#define USART_CR2_CLKEN_Pos (11U)
14206#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
14207#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
14208#define USART_CR2_STOP_Pos (12U)
14209#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
14210#define USART_CR2_STOP USART_CR2_STOP_Msk
14211#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
14212#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
14213#define USART_CR2_LINEN_Pos (14U)
14214#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
14215#define USART_CR2_LINEN USART_CR2_LINEN_Msk
14216#define USART_CR2_SWAP_Pos (15U)
14217#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
14218#define USART_CR2_SWAP USART_CR2_SWAP_Msk
14219#define USART_CR2_RXINV_Pos (16U)
14220#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
14221#define USART_CR2_RXINV USART_CR2_RXINV_Msk
14222#define USART_CR2_TXINV_Pos (17U)
14223#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
14224#define USART_CR2_TXINV USART_CR2_TXINV_Msk
14225#define USART_CR2_DATAINV_Pos (18U)
14226#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
14227#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
14228#define USART_CR2_MSBFIRST_Pos (19U)
14229#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
14230#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
14231#define USART_CR2_ABREN_Pos (20U)
14232#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
14233#define USART_CR2_ABREN USART_CR2_ABREN_Msk
14234#define USART_CR2_ABRMODE_Pos (21U)
14235#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
14236#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
14237#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
14238#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
14239#define USART_CR2_RTOEN_Pos (23U)
14240#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
14241#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
14242#define USART_CR2_ADD_Pos (24U)
14243#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
14244#define USART_CR2_ADD USART_CR2_ADD_Msk
14246/****************** Bit definition for USART_CR3 register *******************/
14247#define USART_CR3_EIE_Pos (0U)
14248#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
14249#define USART_CR3_EIE USART_CR3_EIE_Msk
14250#define USART_CR3_IREN_Pos (1U)
14251#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
14252#define USART_CR3_IREN USART_CR3_IREN_Msk
14253#define USART_CR3_IRLP_Pos (2U)
14254#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
14255#define USART_CR3_IRLP USART_CR3_IRLP_Msk
14256#define USART_CR3_HDSEL_Pos (3U)
14257#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
14258#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
14259#define USART_CR3_NACK_Pos (4U)
14260#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
14261#define USART_CR3_NACK USART_CR3_NACK_Msk
14262#define USART_CR3_SCEN_Pos (5U)
14263#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
14264#define USART_CR3_SCEN USART_CR3_SCEN_Msk
14265#define USART_CR3_DMAR_Pos (6U)
14266#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
14267#define USART_CR3_DMAR USART_CR3_DMAR_Msk
14268#define USART_CR3_DMAT_Pos (7U)
14269#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
14270#define USART_CR3_DMAT USART_CR3_DMAT_Msk
14271#define USART_CR3_RTSE_Pos (8U)
14272#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
14273#define USART_CR3_RTSE USART_CR3_RTSE_Msk
14274#define USART_CR3_CTSE_Pos (9U)
14275#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
14276#define USART_CR3_CTSE USART_CR3_CTSE_Msk
14277#define USART_CR3_CTSIE_Pos (10U)
14278#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
14279#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
14280#define USART_CR3_ONEBIT_Pos (11U)
14281#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
14282#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
14283#define USART_CR3_OVRDIS_Pos (12U)
14284#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
14285#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
14286#define USART_CR3_DDRE_Pos (13U)
14287#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
14288#define USART_CR3_DDRE USART_CR3_DDRE_Msk
14289#define USART_CR3_DEM_Pos (14U)
14290#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
14291#define USART_CR3_DEM USART_CR3_DEM_Msk
14292#define USART_CR3_DEP_Pos (15U)
14293#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
14294#define USART_CR3_DEP USART_CR3_DEP_Msk
14295#define USART_CR3_SCARCNT_Pos (17U)
14296#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
14297#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
14298#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
14299#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
14300#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
14302/****************** Bit definition for USART_BRR register *******************/
14303#define USART_BRR_DIV_FRACTION_Pos (0U)
14304#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
14305#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
14306#define USART_BRR_DIV_MANTISSA_Pos (4U)
14307#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
14308#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
14310/****************** Bit definition for USART_GTPR register ******************/
14311#define USART_GTPR_PSC_Pos (0U)
14312#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
14313#define USART_GTPR_PSC USART_GTPR_PSC_Msk
14314#define USART_GTPR_GT_Pos (8U)
14315#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
14316#define USART_GTPR_GT USART_GTPR_GT_Msk
14319/******************* Bit definition for USART_RTOR register *****************/
14320#define USART_RTOR_RTO_Pos (0U)
14321#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
14322#define USART_RTOR_RTO USART_RTOR_RTO_Msk
14323#define USART_RTOR_BLEN_Pos (24U)
14324#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
14325#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
14327/******************* Bit definition for USART_RQR register ******************/
14328#define USART_RQR_ABRRQ_Pos (0U)
14329#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
14330#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
14331#define USART_RQR_SBKRQ_Pos (1U)
14332#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
14333#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
14334#define USART_RQR_MMRQ_Pos (2U)
14335#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
14336#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
14337#define USART_RQR_RXFRQ_Pos (3U)
14338#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
14339#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
14340#define USART_RQR_TXFRQ_Pos (4U)
14341#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
14342#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
14344/******************* Bit definition for USART_ISR register ******************/
14345#define USART_ISR_PE_Pos (0U)
14346#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
14347#define USART_ISR_PE USART_ISR_PE_Msk
14348#define USART_ISR_FE_Pos (1U)
14349#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
14350#define USART_ISR_FE USART_ISR_FE_Msk
14351#define USART_ISR_NE_Pos (2U)
14352#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
14353#define USART_ISR_NE USART_ISR_NE_Msk
14354#define USART_ISR_ORE_Pos (3U)
14355#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
14356#define USART_ISR_ORE USART_ISR_ORE_Msk
14357#define USART_ISR_IDLE_Pos (4U)
14358#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
14359#define USART_ISR_IDLE USART_ISR_IDLE_Msk
14360#define USART_ISR_RXNE_Pos (5U)
14361#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
14362#define USART_ISR_RXNE USART_ISR_RXNE_Msk
14363#define USART_ISR_TC_Pos (6U)
14364#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
14365#define USART_ISR_TC USART_ISR_TC_Msk
14366#define USART_ISR_TXE_Pos (7U)
14367#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
14368#define USART_ISR_TXE USART_ISR_TXE_Msk
14369#define USART_ISR_LBDF_Pos (8U)
14370#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
14371#define USART_ISR_LBDF USART_ISR_LBDF_Msk
14372#define USART_ISR_CTSIF_Pos (9U)
14373#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
14374#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
14375#define USART_ISR_CTS_Pos (10U)
14376#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
14377#define USART_ISR_CTS USART_ISR_CTS_Msk
14378#define USART_ISR_RTOF_Pos (11U)
14379#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
14380#define USART_ISR_RTOF USART_ISR_RTOF_Msk
14381#define USART_ISR_EOBF_Pos (12U)
14382#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
14383#define USART_ISR_EOBF USART_ISR_EOBF_Msk
14384#define USART_ISR_ABRE_Pos (14U)
14385#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
14386#define USART_ISR_ABRE USART_ISR_ABRE_Msk
14387#define USART_ISR_ABRF_Pos (15U)
14388#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
14389#define USART_ISR_ABRF USART_ISR_ABRF_Msk
14390#define USART_ISR_BUSY_Pos (16U)
14391#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
14392#define USART_ISR_BUSY USART_ISR_BUSY_Msk
14393#define USART_ISR_CMF_Pos (17U)
14394#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
14395#define USART_ISR_CMF USART_ISR_CMF_Msk
14396#define USART_ISR_SBKF_Pos (18U)
14397#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
14398#define USART_ISR_SBKF USART_ISR_SBKF_Msk
14399#define USART_ISR_RWU_Pos (19U)
14400#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
14401#define USART_ISR_RWU USART_ISR_RWU_Msk
14402#define USART_ISR_TEACK_Pos (21U)
14403#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
14404#define USART_ISR_TEACK USART_ISR_TEACK_Msk
14405/* Legacy define */
14406#define USART_ISR_LBD USART_ISR_LBDF
14407
14408/******************* Bit definition for USART_ICR register ******************/
14409#define USART_ICR_PECF_Pos (0U)
14410#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
14411#define USART_ICR_PECF USART_ICR_PECF_Msk
14412#define USART_ICR_FECF_Pos (1U)
14413#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
14414#define USART_ICR_FECF USART_ICR_FECF_Msk
14415#define USART_ICR_NCF_Pos (2U)
14416#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)
14417#define USART_ICR_NCF USART_ICR_NCF_Msk
14418#define USART_ICR_ORECF_Pos (3U)
14419#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
14420#define USART_ICR_ORECF USART_ICR_ORECF_Msk
14421#define USART_ICR_IDLECF_Pos (4U)
14422#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
14423#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
14424#define USART_ICR_TCCF_Pos (6U)
14425#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
14426#define USART_ICR_TCCF USART_ICR_TCCF_Msk
14427#define USART_ICR_LBDCF_Pos (8U)
14428#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
14429#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
14430#define USART_ICR_CTSCF_Pos (9U)
14431#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
14432#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
14433#define USART_ICR_RTOCF_Pos (11U)
14434#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
14435#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
14436#define USART_ICR_EOBCF_Pos (12U)
14437#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
14438#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
14439#define USART_ICR_CMCF_Pos (17U)
14440#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
14441#define USART_ICR_CMCF USART_ICR_CMCF_Msk
14443/******************* Bit definition for USART_RDR register ******************/
14444#define USART_RDR_RDR_Pos (0U)
14445#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
14446#define USART_RDR_RDR USART_RDR_RDR_Msk
14448/******************* Bit definition for USART_TDR register ******************/
14449#define USART_TDR_TDR_Pos (0U)
14450#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
14451#define USART_TDR_TDR USART_TDR_TDR_Msk
14453/******************************************************************************/
14454/* */
14455/* Window WATCHDOG */
14456/* */
14457/******************************************************************************/
14458/******************* Bit definition for WWDG_CR register ********************/
14459#define WWDG_CR_T_Pos (0U)
14460#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
14461#define WWDG_CR_T WWDG_CR_T_Msk
14462#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
14463#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
14464#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
14465#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
14466#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
14467#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
14468#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
14470/* Legacy defines */
14471#define WWDG_CR_T0 WWDG_CR_T_0
14472#define WWDG_CR_T1 WWDG_CR_T_1
14473#define WWDG_CR_T2 WWDG_CR_T_2
14474#define WWDG_CR_T3 WWDG_CR_T_3
14475#define WWDG_CR_T4 WWDG_CR_T_4
14476#define WWDG_CR_T5 WWDG_CR_T_5
14477#define WWDG_CR_T6 WWDG_CR_T_6
14479#define WWDG_CR_WDGA_Pos (7U)
14480#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
14481#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
14483/******************* Bit definition for WWDG_CFR register *******************/
14484#define WWDG_CFR_W_Pos (0U)
14485#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
14486#define WWDG_CFR_W WWDG_CFR_W_Msk
14487#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
14488#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
14489#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
14490#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
14491#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
14492#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
14493#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
14495/* Legacy defines */
14496#define WWDG_CFR_W0 WWDG_CFR_W_0
14497#define WWDG_CFR_W1 WWDG_CFR_W_1
14498#define WWDG_CFR_W2 WWDG_CFR_W_2
14499#define WWDG_CFR_W3 WWDG_CFR_W_3
14500#define WWDG_CFR_W4 WWDG_CFR_W_4
14501#define WWDG_CFR_W5 WWDG_CFR_W_5
14502#define WWDG_CFR_W6 WWDG_CFR_W_6
14504#define WWDG_CFR_WDGTB_Pos (7U)
14505#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
14506#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
14507#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
14508#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
14510/* Legacy defines */
14511#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
14512#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
14514#define WWDG_CFR_EWI_Pos (9U)
14515#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
14516#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
14518/******************* Bit definition for WWDG_SR register ********************/
14519#define WWDG_SR_EWIF_Pos (0U)
14520#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
14521#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
14523/******************************************************************************/
14524/* */
14525/* DBG */
14526/* */
14527/******************************************************************************/
14528/******************** Bit definition for DBGMCU_IDCODE register *************/
14529#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
14530#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
14531#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
14532#define DBGMCU_IDCODE_REV_ID_Pos (16U)
14533#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
14534#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
14535
14536/******************** Bit definition for DBGMCU_CR register *****************/
14537#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
14538#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
14539#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
14540#define DBGMCU_CR_DBG_STOP_Pos (1U)
14541#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
14542#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
14543#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
14544#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
14545#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
14546#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
14547#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
14548#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
14549
14550#define DBGMCU_CR_TRACE_MODE_Pos (6U)
14551#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
14552#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
14553#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
14554#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
14556/******************** Bit definition for DBGMCU_APB1_FZ register ************/
14557#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
14558#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
14559#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
14560#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
14561#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
14562#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
14563#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
14564#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
14565#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
14566#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
14567#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
14568#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
14569#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
14570#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
14571#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
14572#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
14573#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
14574#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
14575#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
14576#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
14577#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
14578#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
14579#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
14580#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
14581#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
14582#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
14583#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
14584#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
14585#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos)
14586#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
14587#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
14588#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
14589#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
14590#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
14591#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
14592#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
14593#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
14594#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
14595#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
14596#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
14597#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
14598#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
14599#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
14600#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
14601#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
14602#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
14603#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
14604#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
14605#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
14606#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
14607#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
14608#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
14609#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
14610#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
14611
14612/******************** Bit definition for DBGMCU_APB2_FZ register ************/
14613#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
14614#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
14615#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
14616#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
14617#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
14618#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
14619#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
14620#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
14621#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
14622#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
14623#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
14624#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
14625#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
14626#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
14627#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
14628
14629/******************************************************************************/
14630/* */
14631/* Ethernet MAC Registers bits definitions */
14632/* */
14633/******************************************************************************/
14634/* Bit definition for Ethernet MAC Control Register register */
14635#define ETH_MACCR_WD_Pos (23U)
14636#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
14637#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
14638#define ETH_MACCR_JD_Pos (22U)
14639#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
14640#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
14641#define ETH_MACCR_IFG_Pos (17U)
14642#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
14643#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
14644#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
14645#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
14646#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
14647#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
14648#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
14649#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
14650#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
14651#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
14652#define ETH_MACCR_CSD_Pos (16U)
14653#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
14654#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
14655#define ETH_MACCR_FES_Pos (14U)
14656#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
14657#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
14658#define ETH_MACCR_ROD_Pos (13U)
14659#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
14660#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
14661#define ETH_MACCR_LM_Pos (12U)
14662#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
14663#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
14664#define ETH_MACCR_DM_Pos (11U)
14665#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
14666#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
14667#define ETH_MACCR_IPCO_Pos (10U)
14668#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
14669#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
14670#define ETH_MACCR_RD_Pos (9U)
14671#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
14672#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
14673#define ETH_MACCR_APCS_Pos (7U)
14674#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
14675#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
14676#define ETH_MACCR_BL_Pos (5U)
14677#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
14678#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
14679 a transmission attempt during retries after a collision: 0 =< r <2^k */
14680#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
14681#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
14682#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
14683#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
14684#define ETH_MACCR_DC_Pos (4U)
14685#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
14686#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
14687#define ETH_MACCR_TE_Pos (3U)
14688#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
14689#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
14690#define ETH_MACCR_RE_Pos (2U)
14691#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
14692#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
14693
14694/* Bit definition for Ethernet MAC Frame Filter Register */
14695#define ETH_MACFFR_RA_Pos (31U)
14696#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
14697#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
14698#define ETH_MACFFR_HPF_Pos (10U)
14699#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
14700#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
14701#define ETH_MACFFR_SAF_Pos (9U)
14702#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
14703#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
14704#define ETH_MACFFR_SAIF_Pos (8U)
14705#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
14706#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
14707#define ETH_MACFFR_PCF_Pos (6U)
14708#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
14709#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
14710#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
14711#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
14712#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
14713#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
14714#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
14715#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
14716#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
14717#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
14718#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
14719#define ETH_MACFFR_BFD_Pos (5U)
14720#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
14721#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
14722#define ETH_MACFFR_PAM_Pos (4U)
14723#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
14724#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
14725#define ETH_MACFFR_DAIF_Pos (3U)
14726#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
14727#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
14728#define ETH_MACFFR_HM_Pos (2U)
14729#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
14730#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
14731#define ETH_MACFFR_HU_Pos (1U)
14732#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
14733#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
14734#define ETH_MACFFR_PM_Pos (0U)
14735#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
14736#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
14737
14738/* Bit definition for Ethernet MAC Hash Table High Register */
14739#define ETH_MACHTHR_HTH_Pos (0U)
14740#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
14741#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
14742
14743/* Bit definition for Ethernet MAC Hash Table Low Register */
14744#define ETH_MACHTLR_HTL_Pos (0U)
14745#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
14746#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
14747
14748/* Bit definition for Ethernet MAC MII Address Register */
14749#define ETH_MACMIIAR_PA_Pos (11U)
14750#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
14751#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
14752#define ETH_MACMIIAR_MR_Pos (6U)
14753#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
14754#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
14755#define ETH_MACMIIAR_CR_Pos (2U)
14756#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
14757#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
14758#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
14759#define ETH_MACMIIAR_CR_Div62_Pos (2U)
14760#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
14761#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
14762#define ETH_MACMIIAR_CR_Div16_Pos (3U)
14763#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
14764#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
14765#define ETH_MACMIIAR_CR_Div26_Pos (2U)
14766#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
14767#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
14768#define ETH_MACMIIAR_CR_Div102_Pos (4U)
14769#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
14770#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
14771#define ETH_MACMIIAR_MW_Pos (1U)
14772#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
14773#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
14774#define ETH_MACMIIAR_MB_Pos (0U)
14775#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
14776#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
14777
14778/* Bit definition for Ethernet MAC MII Data Register */
14779#define ETH_MACMIIDR_MD_Pos (0U)
14780#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
14781#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
14782
14783/* Bit definition for Ethernet MAC Flow Control Register */
14784#define ETH_MACFCR_PT_Pos (16U)
14785#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
14786#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
14787#define ETH_MACFCR_ZQPD_Pos (7U)
14788#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
14789#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
14790#define ETH_MACFCR_PLT_Pos (4U)
14791#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
14792#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
14793#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
14794#define ETH_MACFCR_PLT_Minus28_Pos (4U)
14795#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
14796#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
14797#define ETH_MACFCR_PLT_Minus144_Pos (5U)
14798#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
14799#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
14800#define ETH_MACFCR_PLT_Minus256_Pos (4U)
14801#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
14802#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
14803#define ETH_MACFCR_UPFD_Pos (3U)
14804#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
14805#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
14806#define ETH_MACFCR_RFCE_Pos (2U)
14807#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
14808#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
14809#define ETH_MACFCR_TFCE_Pos (1U)
14810#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
14811#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
14812#define ETH_MACFCR_FCBBPA_Pos (0U)
14813#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
14814#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
14815
14816/* Bit definition for Ethernet MAC VLAN Tag Register */
14817#define ETH_MACVLANTR_VLANTC_Pos (16U)
14818#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
14819#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
14820#define ETH_MACVLANTR_VLANTI_Pos (0U)
14821#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
14822#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
14823
14824/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
14825#define ETH_MACRWUFFR_D_Pos (0U)
14826#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
14827#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
14828/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
14829 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
14830/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
14831 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
14832 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
14833 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
14834 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
14835 RSVD - Filter1 Command - RSVD - Filter0 Command
14836 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
14837 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
14838 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
14839
14840/* Bit definition for Ethernet MAC PMT Control and Status Register */
14841#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
14842#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
14843#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
14844#define ETH_MACPMTCSR_GU_Pos (9U)
14845#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
14846#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
14847#define ETH_MACPMTCSR_WFR_Pos (6U)
14848#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
14849#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
14850#define ETH_MACPMTCSR_MPR_Pos (5U)
14851#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
14852#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
14853#define ETH_MACPMTCSR_WFE_Pos (2U)
14854#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
14855#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
14856#define ETH_MACPMTCSR_MPE_Pos (1U)
14857#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
14858#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
14859#define ETH_MACPMTCSR_PD_Pos (0U)
14860#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
14861#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
14862
14863/* Bit definition for Ethernet MAC debug Register */
14864#define ETH_MACDBGR_TFF_Pos (25U)
14865#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
14866#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
14867#define ETH_MACDBGR_TFNE_Pos (24U)
14868#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
14869#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
14870#define ETH_MACDBGR_TPWA_Pos (22U)
14871#define ETH_MACDBGR_TPWA_Msk (0x1UL << ETH_MACDBGR_TPWA_Pos)
14872#define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */
14873#define ETH_MACDBGR_TFRS_Pos (20U)
14874#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
14875#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
14876#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
14877#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
14878#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
14879#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
14880#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
14881#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
14882#define ETH_MACDBGR_TFRS_READ_Pos (20U)
14883#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
14884#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
14885#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
14886#define ETH_MACDBGR_MTP_Pos (19U)
14887#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
14888#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
14889#define ETH_MACDBGR_MTFCS_Pos (17U)
14890#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
14891#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
14892#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
14893#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
14894#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
14895#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
14896#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
14897#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
14898#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
14899#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
14900#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
14901#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
14902#define ETH_MACDBGR_MMTEA_Pos (16U)
14903#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
14904#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
14905#define ETH_MACDBGR_RFFL_Pos (8U)
14906#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
14907#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
14908#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
14909#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
14910#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
14911#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
14912#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
14913#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
14914#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
14915#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
14916#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
14917#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
14918#define ETH_MACDBGR_RFRCS_Pos (5U)
14919#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
14920#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
14921#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
14922#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
14923#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
14924#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
14925#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
14926#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
14927#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
14928#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
14929#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
14930#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
14931#define ETH_MACDBGR_RFWRA_Pos (4U)
14932#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
14933#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
14934#define ETH_MACDBGR_MSFRWCS_Pos (1U)
14935#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
14936#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
14937#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
14938#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
14939#define ETH_MACDBGR_MMRPEA_Pos (0U)
14940#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
14941#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
14942
14943/* Bit definition for Ethernet MAC Status Register */
14944#define ETH_MACSR_TSTS_Pos (9U)
14945#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
14946#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
14947#define ETH_MACSR_MMCTS_Pos (6U)
14948#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
14949#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
14950#define ETH_MACSR_MMMCRS_Pos (5U)
14951#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
14952#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
14953#define ETH_MACSR_MMCS_Pos (4U)
14954#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
14955#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
14956#define ETH_MACSR_PMTS_Pos (3U)
14957#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
14958#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
14959
14960/* Bit definition for Ethernet MAC Interrupt Mask Register */
14961#define ETH_MACIMR_TSTIM_Pos (9U)
14962#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
14963#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
14964#define ETH_MACIMR_PMTIM_Pos (3U)
14965#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
14966#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
14967
14968/* Bit definition for Ethernet MAC Address0 High Register */
14969#define ETH_MACA0HR_MACA0H_Pos (0U)
14970#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
14971#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
14972
14973/* Bit definition for Ethernet MAC Address0 Low Register */
14974#define ETH_MACA0LR_MACA0L_Pos (0U)
14975#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
14976#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
14977
14978/* Bit definition for Ethernet MAC Address1 High Register */
14979#define ETH_MACA1HR_AE_Pos (31U)
14980#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
14981#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
14982#define ETH_MACA1HR_SA_Pos (30U)
14983#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
14984#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
14985#define ETH_MACA1HR_MBC_Pos (24U)
14986#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
14987#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
14988#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
14989#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
14990#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
14991#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
14992#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
14993#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
14994#define ETH_MACA1HR_MACA1H_Pos (0U)
14995#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
14996#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
14997
14998/* Bit definition for Ethernet MAC Address1 Low Register */
14999#define ETH_MACA1LR_MACA1L_Pos (0U)
15000#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
15001#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
15002
15003/* Bit definition for Ethernet MAC Address2 High Register */
15004#define ETH_MACA2HR_AE_Pos (31U)
15005#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
15006#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
15007#define ETH_MACA2HR_SA_Pos (30U)
15008#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
15009#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
15010#define ETH_MACA2HR_MBC_Pos (24U)
15011#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
15012#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
15013#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
15014#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
15015#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
15016#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
15017#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
15018#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
15019#define ETH_MACA2HR_MACA2H_Pos (0U)
15020#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
15021#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
15022
15023/* Bit definition for Ethernet MAC Address2 Low Register */
15024#define ETH_MACA2LR_MACA2L_Pos (0U)
15025#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
15026#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
15027
15028/* Bit definition for Ethernet MAC Address3 High Register */
15029#define ETH_MACA3HR_AE_Pos (31U)
15030#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
15031#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
15032#define ETH_MACA3HR_SA_Pos (30U)
15033#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
15034#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
15035#define ETH_MACA3HR_MBC_Pos (24U)
15036#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
15037#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
15038#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
15039#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
15040#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
15041#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
15042#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
15043#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
15044#define ETH_MACA3HR_MACA3H_Pos (0U)
15045#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
15046#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
15047
15048/* Bit definition for Ethernet MAC Address3 Low Register */
15049#define ETH_MACA3LR_MACA3L_Pos (0U)
15050#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
15051#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
15052
15053/******************************************************************************/
15054/* Ethernet MMC Registers bits definition */
15055/******************************************************************************/
15056
15057/* Bit definition for Ethernet MMC Contol Register */
15058#define ETH_MMCCR_MCFHP_Pos (5U)
15059#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
15060#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
15061#define ETH_MMCCR_MCP_Pos (4U)
15062#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
15063#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
15064#define ETH_MMCCR_MCF_Pos (3U)
15065#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
15066#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
15067#define ETH_MMCCR_ROR_Pos (2U)
15068#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
15069#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
15070#define ETH_MMCCR_CSR_Pos (1U)
15071#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
15072#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
15073#define ETH_MMCCR_CR_Pos (0U)
15074#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
15075#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
15076
15077/* Bit definition for Ethernet MMC Receive Interrupt Register */
15078#define ETH_MMCRIR_RGUFS_Pos (17U)
15079#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
15080#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
15081#define ETH_MMCRIR_RFAES_Pos (6U)
15082#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
15083#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
15084#define ETH_MMCRIR_RFCES_Pos (5U)
15085#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
15086#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
15087
15088/* Bit definition for Ethernet MMC Transmit Interrupt Register */
15089#define ETH_MMCTIR_TGFS_Pos (21U)
15090#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
15091#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
15092#define ETH_MMCTIR_TGFMSCS_Pos (15U)
15093#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
15094#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
15095#define ETH_MMCTIR_TGFSCS_Pos (14U)
15096#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
15097#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
15098
15099/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
15100#define ETH_MMCRIMR_RGUFM_Pos (17U)
15101#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
15102#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
15103#define ETH_MMCRIMR_RFAEM_Pos (6U)
15104#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
15105#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
15106#define ETH_MMCRIMR_RFCEM_Pos (5U)
15107#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
15108#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
15109
15110/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
15111#define ETH_MMCTIMR_TGFM_Pos (21U)
15112#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
15113#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
15114#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
15115#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
15116#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
15117#define ETH_MMCTIMR_TGFSCM_Pos (14U)
15118#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
15119#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
15120
15121/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
15122#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
15123#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
15124#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
15125
15126/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
15127#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
15128#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
15129#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
15130
15131/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
15132#define ETH_MMCTGFCR_TGFC_Pos (0U)
15133#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
15134#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
15135
15136/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
15137#define ETH_MMCRFCECR_RFCEC_Pos (0U)
15138#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
15139#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
15140
15141/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
15142#define ETH_MMCRFAECR_RFAEC_Pos (0U)
15143#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
15144#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
15145
15146/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
15147#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
15148#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
15149#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
15150
15151/******************************************************************************/
15152/* Ethernet PTP Registers bits definition */
15153/******************************************************************************/
15154
15155/* Bit definition for Ethernet PTP Time Stamp Contol Register */
15156#define ETH_PTPTSCR_TSCNT_Pos (16U)
15157#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
15158#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
15159#define ETH_PTPTSSR_TSSMRME_Pos (15U)
15160#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos)
15161#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
15162#define ETH_PTPTSSR_TSSEME_Pos (14U)
15163#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos)
15164#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
15165#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
15166#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos)
15167#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15168#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
15169#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos)
15170#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15171#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
15172#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos)
15173#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15174#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
15175#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos)
15176#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15177#define ETH_PTPTSSR_TSSSR_Pos (9U)
15178#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos)
15179#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
15180#define ETH_PTPTSSR_TSSARFE_Pos (8U)
15181#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos)
15182#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
15183
15184#define ETH_PTPTSCR_TSARU_Pos (5U)
15185#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
15186#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
15187#define ETH_PTPTSCR_TSITE_Pos (4U)
15188#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
15189#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
15190#define ETH_PTPTSCR_TSSTU_Pos (3U)
15191#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
15192#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
15193#define ETH_PTPTSCR_TSSTI_Pos (2U)
15194#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
15195#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
15196#define ETH_PTPTSCR_TSFCU_Pos (1U)
15197#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
15198#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
15199#define ETH_PTPTSCR_TSE_Pos (0U)
15200#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
15201#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
15202
15203/* Bit definition for Ethernet PTP Sub-Second Increment Register */
15204#define ETH_PTPSSIR_STSSI_Pos (0U)
15205#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
15206#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
15207
15208/* Bit definition for Ethernet PTP Time Stamp High Register */
15209#define ETH_PTPTSHR_STS_Pos (0U)
15210#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
15211#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
15212
15213/* Bit definition for Ethernet PTP Time Stamp Low Register */
15214#define ETH_PTPTSLR_STPNS_Pos (31U)
15215#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
15216#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
15217#define ETH_PTPTSLR_STSS_Pos (0U)
15218#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
15219#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
15220
15221/* Bit definition for Ethernet PTP Time Stamp High Update Register */
15222#define ETH_PTPTSHUR_TSUS_Pos (0U)
15223#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
15224#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
15225
15226/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
15227#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
15228#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
15229#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
15230#define ETH_PTPTSLUR_TSUSS_Pos (0U)
15231#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
15232#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
15233
15234/* Bit definition for Ethernet PTP Time Stamp Addend Register */
15235#define ETH_PTPTSAR_TSA_Pos (0U)
15236#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
15237#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
15238
15239/* Bit definition for Ethernet PTP Target Time High Register */
15240#define ETH_PTPTTHR_TTSH_Pos (0U)
15241#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
15242#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
15243
15244/* Bit definition for Ethernet PTP Target Time Low Register */
15245#define ETH_PTPTTLR_TTSL_Pos (0U)
15246#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
15247#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
15248
15249/* Bit definition for Ethernet PTP Time Stamp Status Register */
15250#define ETH_PTPTSSR_TSTTR_Pos (5U)
15251#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
15252#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
15253#define ETH_PTPTSSR_TSSO_Pos (4U)
15254#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
15255#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
15256
15257/* Bit definition for Ethernet PTP PPS Control Register */
15258#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
15259#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos)
15260#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
15261
15262/******************************************************************************/
15263/* Ethernet DMA Registers bits definition */
15264/******************************************************************************/
15265
15266/* Bit definition for Ethernet DMA Bus Mode Register */
15267#define ETH_DMABMR_AAB_Pos (25U)
15268#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
15269#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
15270#define ETH_DMABMR_FPM_Pos (24U)
15271#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
15272#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
15273#define ETH_DMABMR_USP_Pos (23U)
15274#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
15275#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
15276#define ETH_DMABMR_RDP_Pos (17U)
15277#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
15278#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
15279#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
15280#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
15281#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15282#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15283#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15284#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15285#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15286#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15287#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15288#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15289#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
15290#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
15291#define ETH_DMABMR_FB_Pos (16U)
15292#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
15293#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
15294#define ETH_DMABMR_RTPR_Pos (14U)
15295#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
15296#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
15297#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
15298#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
15299#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
15300#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
15301#define ETH_DMABMR_PBL_Pos (8U)
15302#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
15303#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
15304#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
15305#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
15306#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15307#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15308#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15309#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15310#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15311#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15312#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15313#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15314#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
15315#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
15316#define ETH_DMABMR_EDE_Pos (7U)
15317#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
15318#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
15319#define ETH_DMABMR_DSL_Pos (2U)
15320#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
15321#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
15322#define ETH_DMABMR_DA_Pos (1U)
15323#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
15324#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
15325#define ETH_DMABMR_SR_Pos (0U)
15326#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
15327#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
15328
15329/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
15330#define ETH_DMATPDR_TPD_Pos (0U)
15331#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
15332#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
15333
15334/* Bit definition for Ethernet DMA Receive Poll Demand Register */
15335#define ETH_DMARPDR_RPD_Pos (0U)
15336#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
15337#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
15338
15339/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
15340#define ETH_DMARDLAR_SRL_Pos (0U)
15341#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
15342#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
15343
15344/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
15345#define ETH_DMATDLAR_STL_Pos (0U)
15346#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
15347#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
15348
15349/* Bit definition for Ethernet DMA Status Register */
15350#define ETH_DMASR_TSTS_Pos (29U)
15351#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
15352#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
15353#define ETH_DMASR_PMTS_Pos (28U)
15354#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
15355#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
15356#define ETH_DMASR_MMCS_Pos (27U)
15357#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
15358#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
15359#define ETH_DMASR_EBS_Pos (23U)
15360#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
15361#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
15362 /* combination with EBS[2:0] for GetFlagStatus function */
15363#define ETH_DMASR_EBS_DescAccess_Pos (25U)
15364#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
15365#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
15366#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
15367#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
15368#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
15369#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
15370#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
15371#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
15372#define ETH_DMASR_TPS_Pos (20U)
15373#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
15374#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
15375#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
15376#define ETH_DMASR_TPS_Fetching_Pos (20U)
15377#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
15378#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
15379#define ETH_DMASR_TPS_Waiting_Pos (21U)
15380#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
15381#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
15382#define ETH_DMASR_TPS_Reading_Pos (20U)
15383#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
15384#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
15385#define ETH_DMASR_TPS_Suspended_Pos (21U)
15386#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
15387#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
15388#define ETH_DMASR_TPS_Closing_Pos (20U)
15389#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
15390#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
15391#define ETH_DMASR_RPS_Pos (17U)
15392#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
15393#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
15394#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
15395#define ETH_DMASR_RPS_Fetching_Pos (17U)
15396#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
15397#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
15398#define ETH_DMASR_RPS_Waiting_Pos (17U)
15399#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
15400#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
15401#define ETH_DMASR_RPS_Suspended_Pos (19U)
15402#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
15403#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
15404#define ETH_DMASR_RPS_Closing_Pos (17U)
15405#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
15406#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
15407#define ETH_DMASR_RPS_Queuing_Pos (17U)
15408#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
15409#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
15410#define ETH_DMASR_NIS_Pos (16U)
15411#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
15412#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
15413#define ETH_DMASR_AIS_Pos (15U)
15414#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
15415#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
15416#define ETH_DMASR_ERS_Pos (14U)
15417#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
15418#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
15419#define ETH_DMASR_FBES_Pos (13U)
15420#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
15421#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
15422#define ETH_DMASR_ETS_Pos (10U)
15423#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
15424#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
15425#define ETH_DMASR_RWTS_Pos (9U)
15426#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
15427#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
15428#define ETH_DMASR_RPSS_Pos (8U)
15429#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
15430#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
15431#define ETH_DMASR_RBUS_Pos (7U)
15432#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
15433#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
15434#define ETH_DMASR_RS_Pos (6U)
15435#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
15436#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
15437#define ETH_DMASR_TUS_Pos (5U)
15438#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
15439#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
15440#define ETH_DMASR_ROS_Pos (4U)
15441#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
15442#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
15443#define ETH_DMASR_TJTS_Pos (3U)
15444#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
15445#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
15446#define ETH_DMASR_TBUS_Pos (2U)
15447#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
15448#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
15449#define ETH_DMASR_TPSS_Pos (1U)
15450#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
15451#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
15452#define ETH_DMASR_TS_Pos (0U)
15453#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
15454#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
15455
15456/* Bit definition for Ethernet DMA Operation Mode Register */
15457#define ETH_DMAOMR_DTCEFD_Pos (26U)
15458#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
15459#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
15460#define ETH_DMAOMR_RSF_Pos (25U)
15461#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
15462#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
15463#define ETH_DMAOMR_DFRF_Pos (24U)
15464#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
15465#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
15466#define ETH_DMAOMR_TSF_Pos (21U)
15467#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
15468#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
15469#define ETH_DMAOMR_FTF_Pos (20U)
15470#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
15471#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
15472#define ETH_DMAOMR_TTC_Pos (14U)
15473#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
15474#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
15475#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
15476#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
15477#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
15478#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
15479#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
15480#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
15481#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
15482#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
15483#define ETH_DMAOMR_ST_Pos (13U)
15484#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
15485#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
15486#define ETH_DMAOMR_FEF_Pos (7U)
15487#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
15488#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
15489#define ETH_DMAOMR_FUGF_Pos (6U)
15490#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
15491#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
15492#define ETH_DMAOMR_RTC_Pos (3U)
15493#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
15494#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
15495#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
15496#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
15497#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
15498#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
15499#define ETH_DMAOMR_OSF_Pos (2U)
15500#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
15501#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
15502#define ETH_DMAOMR_SR_Pos (1U)
15503#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
15504#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
15505
15506/* Bit definition for Ethernet DMA Interrupt Enable Register */
15507#define ETH_DMAIER_NISE_Pos (16U)
15508#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
15509#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
15510#define ETH_DMAIER_AISE_Pos (15U)
15511#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
15512#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
15513#define ETH_DMAIER_ERIE_Pos (14U)
15514#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
15515#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
15516#define ETH_DMAIER_FBEIE_Pos (13U)
15517#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
15518#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
15519#define ETH_DMAIER_ETIE_Pos (10U)
15520#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
15521#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
15522#define ETH_DMAIER_RWTIE_Pos (9U)
15523#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
15524#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
15525#define ETH_DMAIER_RPSIE_Pos (8U)
15526#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
15527#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
15528#define ETH_DMAIER_RBUIE_Pos (7U)
15529#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
15530#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
15531#define ETH_DMAIER_RIE_Pos (6U)
15532#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
15533#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
15534#define ETH_DMAIER_TUIE_Pos (5U)
15535#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
15536#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
15537#define ETH_DMAIER_ROIE_Pos (4U)
15538#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
15539#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
15540#define ETH_DMAIER_TJTIE_Pos (3U)
15541#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
15542#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
15543#define ETH_DMAIER_TBUIE_Pos (2U)
15544#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
15545#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
15546#define ETH_DMAIER_TPSIE_Pos (1U)
15547#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
15548#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
15549#define ETH_DMAIER_TIE_Pos (0U)
15550#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
15551#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
15552
15553/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
15554#define ETH_DMAMFBOCR_OFOC_Pos (28U)
15555#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
15556#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
15557#define ETH_DMAMFBOCR_MFA_Pos (17U)
15558#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
15559#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
15560#define ETH_DMAMFBOCR_OMFC_Pos (16U)
15561#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
15562#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
15563#define ETH_DMAMFBOCR_MFC_Pos (0U)
15564#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
15565#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
15566
15567/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
15568#define ETH_DMACHTDR_HTDAP_Pos (0U)
15569#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
15570#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
15571
15572/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
15573#define ETH_DMACHRDR_HRDAP_Pos (0U)
15574#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
15575#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
15576
15577/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
15578#define ETH_DMACHTBAR_HTBAP_Pos (0U)
15579#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
15580#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
15581
15582/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
15583#define ETH_DMACHRBAR_HRBAP_Pos (0U)
15584#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
15585#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
15586
15587/******************************************************************************/
15588/* */
15589/* USB_OTG */
15590/* */
15591/******************************************************************************/
15592/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
15593#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
15594#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
15595#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
15596#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
15597#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
15598#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
15599#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
15600#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
15601#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
15602#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
15603#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
15604#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
15605#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
15606#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
15607#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
15608#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
15609#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
15610#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
15611#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
15612#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
15613#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
15614#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
15615#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
15616#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
15617#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
15618#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
15619#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
15620#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
15621#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
15622#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
15623#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
15624#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
15625#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
15626#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
15627#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
15628#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
15629#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
15630#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
15631#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
15632#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
15633#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
15634#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
15635#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
15636#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
15637#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
15638#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
15639#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
15640#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
15641#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
15642#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
15643#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
15644#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
15645#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
15646#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
15648/******************** Bit definition for USB_OTG_HCFG register ********************/
15649#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
15650#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
15651#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
15652#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
15653#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
15654#define USB_OTG_HCFG_FSLSS_Pos (2U)
15655#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
15656#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
15658/******************** Bit definition for USB_OTG_DCFG register ********************/
15659#define USB_OTG_DCFG_DSPD_Pos (0U)
15660#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
15661#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
15662#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
15663#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
15664#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
15665#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
15666#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
15668#define USB_OTG_DCFG_DAD_Pos (4U)
15669#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
15670#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
15671#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
15672#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
15673#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
15674#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
15675#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
15676#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
15677#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
15679#define USB_OTG_DCFG_PFIVL_Pos (11U)
15680#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
15681#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
15682#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
15683#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
15685#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
15686#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
15687#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
15688#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
15689#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
15691/******************** Bit definition for USB_OTG_PCGCR register ********************/
15692#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
15693#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
15694#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
15695#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
15696#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
15697#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
15698#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
15699#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
15700#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
15702/******************** Bit definition for USB_OTG_GOTGINT register ********************/
15703#define USB_OTG_GOTGINT_SEDET_Pos (2U)
15704#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
15705#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
15706#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
15707#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
15708#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
15709#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
15710#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
15711#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
15712#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
15713#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
15714#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
15715#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
15716#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
15717#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
15718#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
15719#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
15720#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
15721#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
15722#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos)
15723#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk
15725/******************** Bit definition for USB_OTG_DCTL register ********************/
15726#define USB_OTG_DCTL_RWUSIG_Pos (0U)
15727#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
15728#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
15729#define USB_OTG_DCTL_SDIS_Pos (1U)
15730#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
15731#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
15732#define USB_OTG_DCTL_GINSTS_Pos (2U)
15733#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
15734#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
15735#define USB_OTG_DCTL_GONSTS_Pos (3U)
15736#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
15737#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
15739#define USB_OTG_DCTL_TCTL_Pos (4U)
15740#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
15741#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
15742#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
15743#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
15744#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
15745#define USB_OTG_DCTL_SGINAK_Pos (7U)
15746#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
15747#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
15748#define USB_OTG_DCTL_CGINAK_Pos (8U)
15749#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
15750#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
15751#define USB_OTG_DCTL_SGONAK_Pos (9U)
15752#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
15753#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
15754#define USB_OTG_DCTL_CGONAK_Pos (10U)
15755#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
15756#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
15757#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
15758#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
15759#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
15761/******************** Bit definition for USB_OTG_HFIR register ********************/
15762#define USB_OTG_HFIR_FRIVL_Pos (0U)
15763#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
15764#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
15766/******************** Bit definition for USB_OTG_HFNUM register ********************/
15767#define USB_OTG_HFNUM_FRNUM_Pos (0U)
15768#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
15769#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
15770#define USB_OTG_HFNUM_FTREM_Pos (16U)
15771#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
15772#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
15774/******************** Bit definition for USB_OTG_DSTS register ********************/
15775#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
15776#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
15777#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
15779#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
15780#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
15781#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
15782#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
15783#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
15784#define USB_OTG_DSTS_EERR_Pos (3U)
15785#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
15786#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
15787#define USB_OTG_DSTS_FNSOF_Pos (8U)
15788#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
15789#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
15791/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
15792#define USB_OTG_GAHBCFG_GINT_Pos (0U)
15793#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
15794#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
15795#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
15796#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15797#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
15798#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15799#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15800#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15801#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15802#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
15803#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
15804#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
15805#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
15806#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
15807#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
15808#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
15809#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
15810#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
15811#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
15813/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
15814#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
15815#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15816#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
15817#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15818#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15819#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
15820#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
15821#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
15822#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
15823#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
15824#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
15825#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
15826#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
15827#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
15828#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
15829#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
15830#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
15831#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
15832#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
15833#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
15834#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
15835#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
15836#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
15837#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
15838#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
15839#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
15840#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
15841#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
15842#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
15843#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
15844#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
15845#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
15846#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
15847#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
15848#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
15849#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
15850#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
15851#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
15852#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
15853#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
15854#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
15855#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
15856#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
15857#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
15858#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
15859#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
15860#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
15861#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
15862#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
15863#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
15864#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
15865#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
15866#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
15867#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
15868#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
15869#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
15870#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
15871#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
15872#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
15873#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
15874#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
15876/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
15877#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
15878#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
15879#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
15880#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
15881#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
15882#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
15883#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
15884#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
15885#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
15886#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
15887#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
15888#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
15889#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
15890#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
15891#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
15892#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
15893#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15894#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
15895#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15896#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15897#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15898#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15899#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
15900#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
15901#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
15902#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
15903#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
15904#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
15905#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
15907/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
15908#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
15909#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
15910#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
15911#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
15912#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
15913#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
15914#define USB_OTG_DIEPMSK_TOM_Pos (3U)
15915#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
15916#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
15917#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
15918#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
15919#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
15920#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
15921#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
15922#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
15923#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
15924#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
15925#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
15926#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
15927#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
15928#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
15929#define USB_OTG_DIEPMSK_BIM_Pos (9U)
15930#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
15931#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
15933/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
15934#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
15935#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
15936#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
15937#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
15938#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15939#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
15940#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15941#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15942#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15943#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15944#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15945#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15946#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15947#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
15949#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
15950#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15951#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
15952#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15953#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15954#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15955#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15956#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15957#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15958#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15959#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
15961/******************** Bit definition for USB_OTG_HAINT register ********************/
15962#define USB_OTG_HAINT_HAINT_Pos (0U)
15963#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
15964#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
15966/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
15967#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
15968#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
15969#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
15970#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
15971#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
15972#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
15973#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
15974#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
15975#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
15976#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
15977#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
15978#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
15979#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
15980#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
15981#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
15982#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
15983#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
15984#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
15985#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
15986#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
15987#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
15988#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
15989#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
15990#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
15991#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
15992#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
15993#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
15994#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
15995#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
15996#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
15997#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
15998#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
15999#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
16000#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
16001#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
16002#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
16004/******************** Bit definition for USB_OTG_GINTSTS register ********************/
16005#define USB_OTG_GINTSTS_CMOD_Pos (0U)
16006#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
16007#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
16008#define USB_OTG_GINTSTS_MMIS_Pos (1U)
16009#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
16010#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
16011#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
16012#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
16013#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
16014#define USB_OTG_GINTSTS_SOF_Pos (3U)
16015#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
16016#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
16017#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
16018#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
16019#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
16020#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
16021#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
16022#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
16023#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
16024#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
16025#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
16026#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
16027#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
16028#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
16029#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
16030#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
16031#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
16032#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
16033#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
16034#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
16035#define USB_OTG_GINTSTS_USBRST_Pos (12U)
16036#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
16037#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
16038#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
16039#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
16040#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
16041#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
16042#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
16043#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
16044#define USB_OTG_GINTSTS_EOPF_Pos (15U)
16045#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
16046#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
16047#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
16048#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
16049#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
16050#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
16051#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
16052#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
16053#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
16054#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
16055#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
16056#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
16057#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
16058#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
16059#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
16060#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
16061#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
16062#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
16063#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
16064#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
16065#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
16066#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
16067#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
16068#define USB_OTG_GINTSTS_HCINT_Pos (25U)
16069#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
16070#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
16071#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
16072#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
16073#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
16074#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
16075#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
16076#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
16077#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
16078#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
16079#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
16080#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
16081#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
16082#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
16083#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
16084#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
16085#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
16086#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
16087#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
16088#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
16090/******************** Bit definition for USB_OTG_GINTMSK register ********************/
16091#define USB_OTG_GINTMSK_MMISM_Pos (1U)
16092#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
16093#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
16094#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
16095#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
16096#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
16097#define USB_OTG_GINTMSK_SOFM_Pos (3U)
16098#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
16099#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
16100#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
16101#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
16102#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
16103#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
16104#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
16105#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
16106#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
16107#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
16108#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
16109#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
16110#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
16111#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
16112#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
16113#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
16114#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
16115#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
16116#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
16117#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
16118#define USB_OTG_GINTMSK_USBRST_Pos (12U)
16119#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
16120#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
16121#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
16122#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
16123#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
16124#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
16125#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
16126#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
16127#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
16128#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
16129#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
16130#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
16131#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
16132#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
16133#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
16134#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
16135#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
16136#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
16137#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
16138#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
16139#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
16140#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
16141#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
16142#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
16143#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
16144#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
16145#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
16146#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
16147#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
16148#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
16149#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
16150#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
16151#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
16152#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
16153#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
16154#define USB_OTG_GINTMSK_HCIM_Pos (25U)
16155#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
16156#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
16157#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
16158#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
16159#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
16160#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
16161#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
16162#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
16163#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
16164#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
16165#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
16166#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
16167#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
16168#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
16169#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
16170#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
16171#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
16172#define USB_OTG_GINTMSK_WUIM_Pos (31U)
16173#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
16174#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
16176/******************** Bit definition for USB_OTG_DAINT register ********************/
16177#define USB_OTG_DAINT_IEPINT_Pos (0U)
16178#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
16179#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
16180#define USB_OTG_DAINT_OEPINT_Pos (16U)
16181#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
16182#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
16184/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
16185#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
16186#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
16187#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
16189/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
16190#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
16191#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
16192#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
16193#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
16194#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
16195#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
16196#define USB_OTG_GRXSTSP_DPID_Pos (15U)
16197#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
16198#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
16199#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
16200#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
16201#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
16203/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
16204#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
16205#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
16206#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
16207#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
16208#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
16209#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
16211/******************** Bit definition for OTG register ********************/
16212
16213#define USB_OTG_CHNUM_Pos (0U)
16214#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
16215#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
16216#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
16217#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
16218#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
16219#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
16220#define USB_OTG_BCNT_Pos (4U)
16221#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
16222#define USB_OTG_BCNT USB_OTG_BCNT_Msk
16224#define USB_OTG_DPID_Pos (15U)
16225#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
16226#define USB_OTG_DPID USB_OTG_DPID_Msk
16227#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
16228#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
16230#define USB_OTG_PKTSTS_Pos (17U)
16231#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
16232#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
16233#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
16234#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
16235#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
16236#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
16238#define USB_OTG_EPNUM_Pos (0U)
16239#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
16240#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
16241#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
16242#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
16243#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
16244#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
16246#define USB_OTG_FRMNUM_Pos (21U)
16247#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
16248#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
16249#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
16250#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
16251#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
16252#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
16254/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
16255#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
16256#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
16257#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
16259/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
16260#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
16261#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
16262#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
16264/******************** Bit definition for OTG register ********************/
16265#define USB_OTG_NPTXFSA_Pos (0U)
16266#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
16267#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
16268#define USB_OTG_NPTXFD_Pos (16U)
16269#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
16270#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
16271#define USB_OTG_TX0FSA_Pos (0U)
16272#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
16273#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
16274#define USB_OTG_TX0FD_Pos (16U)
16275#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
16276#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
16278/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
16279#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
16280#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
16281#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
16283/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
16284#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
16285#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
16286#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
16288#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
16289#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16290#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
16291#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16292#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16293#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16294#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16295#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16296#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16297#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16298#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16300#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
16301#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16302#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
16303#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16304#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16305#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16306#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16307#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16308#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16309#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16311/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
16312#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
16313#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
16314#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
16315#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
16316#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
16317#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
16319#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
16320#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16321#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
16322#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16323#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16324#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16325#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16326#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16327#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16328#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16329#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16330#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16331#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
16332#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
16333#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
16335#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
16336#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16337#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
16338#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16339#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16340#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16341#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16342#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16343#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16344#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16345#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16346#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16347#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
16348#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
16349#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
16351/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
16352#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
16353#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
16354#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
16356/******************** Bit definition for USB_OTG_DEACHINT register ********************/
16357#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
16358#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
16359#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
16360#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
16361#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
16362#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
16364/******************** Bit definition for USB_OTG_GCCFG register ********************/
16365#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
16366#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
16367#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
16368#define USB_OTG_GCCFG_VBDEN_Pos (21U)
16369#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
16370#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
16372/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
16373#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
16374#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
16375#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
16376#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
16377#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
16378#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
16380/******************** Bit definition for USB_OTG_CID register ********************/
16381#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
16382#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
16383#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
16385/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
16386#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
16387#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
16388#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
16389#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
16390#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
16391#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
16392#define USB_OTG_GLPMCFG_BESL_Pos (2U)
16393#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
16394#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
16395#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
16396#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
16397#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
16398#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
16399#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
16400#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
16401#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
16402#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
16403#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
16404#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
16405#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
16406#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
16407#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
16408#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
16409#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
16410#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
16411#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
16412#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
16413#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
16414#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
16415#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
16416#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
16417#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
16418#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
16419#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
16420#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
16421#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
16422#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
16423#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
16424#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
16425#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
16426#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
16427#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
16428#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
16429#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
16430#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
16432/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
16433#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
16434#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
16435#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
16436#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
16437#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
16438#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
16439#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
16440#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
16441#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
16442#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
16443#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
16444#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
16445#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
16446#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
16447#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
16448#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
16449#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
16450#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
16451#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
16452#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
16453#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
16454#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
16455#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
16456#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
16457#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
16458#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
16459#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
16461/******************** Bit definition for USB_OTG_HPRT register ********************/
16462#define USB_OTG_HPRT_PCSTS_Pos (0U)
16463#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
16464#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
16465#define USB_OTG_HPRT_PCDET_Pos (1U)
16466#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
16467#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
16468#define USB_OTG_HPRT_PENA_Pos (2U)
16469#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
16470#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
16471#define USB_OTG_HPRT_PENCHNG_Pos (3U)
16472#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
16473#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
16474#define USB_OTG_HPRT_POCA_Pos (4U)
16475#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
16476#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
16477#define USB_OTG_HPRT_POCCHNG_Pos (5U)
16478#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
16479#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
16480#define USB_OTG_HPRT_PRES_Pos (6U)
16481#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
16482#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
16483#define USB_OTG_HPRT_PSUSP_Pos (7U)
16484#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
16485#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
16486#define USB_OTG_HPRT_PRST_Pos (8U)
16487#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
16488#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
16490#define USB_OTG_HPRT_PLSTS_Pos (10U)
16491#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
16492#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
16493#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
16494#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
16495#define USB_OTG_HPRT_PPWR_Pos (12U)
16496#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
16497#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
16499#define USB_OTG_HPRT_PTCTL_Pos (13U)
16500#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
16501#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
16502#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
16503#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
16504#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
16505#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
16507#define USB_OTG_HPRT_PSPD_Pos (17U)
16508#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
16509#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
16510#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
16511#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
16513/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
16514#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
16515#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
16516#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
16517#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
16518#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
16519#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
16520#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
16521#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
16522#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
16523#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
16524#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
16525#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
16526#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
16527#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
16528#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
16529#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
16530#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
16531#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
16532#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
16533#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
16534#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
16535#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
16536#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
16537#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
16538#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
16539#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
16540#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
16541#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
16542#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
16543#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
16544#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
16545#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
16546#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
16548/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
16549#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
16550#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
16551#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
16552#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
16553#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
16554#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
16556/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
16557#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
16558#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
16559#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
16560#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
16561#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
16562#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
16563#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
16564#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
16565#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
16566#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
16567#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
16568#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
16570#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
16571#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
16572#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
16573#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
16574#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
16575#define USB_OTG_DIEPCTL_STALL_Pos (21U)
16576#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
16577#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
16579#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
16580#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16581#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
16582#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16583#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16584#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16585#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
16586#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
16587#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
16588#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
16589#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
16590#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
16591#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
16592#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
16593#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
16594#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
16595#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
16596#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
16597#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
16598#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
16599#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
16600#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
16601#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
16602#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
16603#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
16605/******************** Bit definition for USB_OTG_HCCHAR register ********************/
16606#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
16607#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
16608#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
16610#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
16611#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
16612#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
16613#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
16614#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
16615#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
16616#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
16617#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
16618#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
16619#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
16620#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
16621#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
16622#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
16624#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
16625#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
16626#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
16627#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
16628#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
16630#define USB_OTG_HCCHAR_MC_Pos (20U)
16631#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
16632#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
16633#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
16634#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
16636#define USB_OTG_HCCHAR_DAD_Pos (22U)
16637#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
16638#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
16639#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
16640#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
16641#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
16642#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
16643#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
16644#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
16645#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
16646#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
16647#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
16648#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
16649#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
16650#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
16651#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
16652#define USB_OTG_HCCHAR_CHENA_Pos (31U)
16653#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
16654#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
16656/******************** Bit definition for USB_OTG_HCSPLT register ********************/
16657
16658#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
16659#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
16660#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
16661#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16662#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16663#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16664#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16665#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16666#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16667#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
16669#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
16670#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
16671#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
16672#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16673#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16674#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16675#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16676#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16677#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16678#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
16680#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
16681#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
16682#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
16683#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
16684#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
16685#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
16686#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
16687#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
16688#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
16689#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
16690#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
16692/******************** Bit definition for USB_OTG_HCINT register ********************/
16693#define USB_OTG_HCINT_XFRC_Pos (0U)
16694#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
16695#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
16696#define USB_OTG_HCINT_CHH_Pos (1U)
16697#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
16698#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
16699#define USB_OTG_HCINT_AHBERR_Pos (2U)
16700#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
16701#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
16702#define USB_OTG_HCINT_STALL_Pos (3U)
16703#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
16704#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
16705#define USB_OTG_HCINT_NAK_Pos (4U)
16706#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
16707#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
16708#define USB_OTG_HCINT_ACK_Pos (5U)
16709#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
16710#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
16711#define USB_OTG_HCINT_NYET_Pos (6U)
16712#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
16713#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
16714#define USB_OTG_HCINT_TXERR_Pos (7U)
16715#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
16716#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
16717#define USB_OTG_HCINT_BBERR_Pos (8U)
16718#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
16719#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
16720#define USB_OTG_HCINT_FRMOR_Pos (9U)
16721#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
16722#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
16723#define USB_OTG_HCINT_DTERR_Pos (10U)
16724#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
16725#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
16727/******************** Bit definition for USB_OTG_DIEPINT register ********************/
16728#define USB_OTG_DIEPINT_XFRC_Pos (0U)
16729#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
16730#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
16731#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
16732#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
16733#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
16734#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
16735#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
16736#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
16737#define USB_OTG_DIEPINT_TOC_Pos (3U)
16738#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
16739#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
16740#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
16741#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
16742#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
16743#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
16744#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
16745#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
16746#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
16747#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
16748#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
16749#define USB_OTG_DIEPINT_TXFE_Pos (7U)
16750#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
16751#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
16752#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
16753#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
16754#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
16755#define USB_OTG_DIEPINT_BNA_Pos (9U)
16756#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
16757#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
16758#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
16759#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
16760#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
16761#define USB_OTG_DIEPINT_BERR_Pos (12U)
16762#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
16763#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
16764#define USB_OTG_DIEPINT_NAK_Pos (13U)
16765#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
16766#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
16768/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
16769#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
16770#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
16771#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
16772#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
16773#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
16774#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
16775#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
16776#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
16777#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
16778#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
16779#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
16780#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
16781#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
16782#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
16783#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
16784#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
16785#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
16786#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
16787#define USB_OTG_HCINTMSK_NYET_Pos (6U)
16788#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
16789#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
16790#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
16791#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
16792#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
16793#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
16794#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
16795#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
16796#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
16797#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
16798#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
16799#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
16800#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
16801#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
16803/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
16804
16805#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
16806#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
16807#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
16808#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
16809#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
16810#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
16811#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
16812#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
16813#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
16814/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
16815#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
16816#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
16817#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
16818#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
16819#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
16820#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
16821#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
16822#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
16823#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
16824#define USB_OTG_HCTSIZ_DPID_Pos (29U)
16825#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
16826#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
16827#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
16828#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
16830/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
16831#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
16832#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
16833#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
16835/******************** Bit definition for USB_OTG_HCDMA register ********************/
16836#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
16837#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
16838#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
16840/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
16841#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
16842#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
16843#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
16845/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
16846#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
16847#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
16848#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
16849#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
16850#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
16851#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
16853/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
16854#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
16855#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
16856#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
16857#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
16858#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
16859#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
16860#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
16861#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
16862#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
16863#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
16864#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
16865#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
16866#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
16867#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
16868#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
16869#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
16870#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
16871#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
16872#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
16873#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
16874#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
16875#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
16876#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
16877#define USB_OTG_DOEPCTL_STALL_Pos (21U)
16878#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
16879#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
16880#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
16881#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
16882#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
16883#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
16884#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
16885#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
16886#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
16887#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
16888#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
16889#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
16890#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
16891#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
16893/******************** Bit definition for USB_OTG_DOEPINT register ********************/
16894#define USB_OTG_DOEPINT_XFRC_Pos (0U)
16895#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
16896#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
16897#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
16898#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
16899#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
16900#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
16901#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
16902#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
16903#define USB_OTG_DOEPINT_STUP_Pos (3U)
16904#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
16905#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
16906#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
16907#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
16908#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
16909#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
16910#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
16911#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
16912#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
16913#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
16914#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
16915#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
16916#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
16917#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
16918#define USB_OTG_DOEPINT_NAK_Pos (13U)
16919#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
16920#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
16921#define USB_OTG_DOEPINT_NYET_Pos (14U)
16922#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
16923#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
16924#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
16925#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
16926#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
16928/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
16929#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
16930#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
16931#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
16932#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
16933#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
16934#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
16936#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
16937#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
16938#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
16939#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
16940#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
16942/******************** Bit definition for PCGCCTL register ********************/
16943#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
16944#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
16945#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
16946#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
16947#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
16948#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
16949#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
16950#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
16951#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
16968/******************************* ADC Instances ********************************/
16969#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
16970 ((__INSTANCE__) == ADC2) || \
16971 ((__INSTANCE__) == ADC3))
16972#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
16973
16974#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
16975
16976/******************************* CAN Instances ********************************/
16977#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
16978 ((__INSTANCE__) == CAN2))
16979/******************************* CRC Instances ********************************/
16980#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
16981
16982/******************************* DAC Instances ********************************/
16983#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)
16984
16985/******************************* DCMI Instances *******************************/
16986#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
16987
16988
16989/******************************* DMA2D Instances *******************************/
16990#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
16991
16992/******************************** DMA Instances *******************************/
16993#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
16994 ((__INSTANCE__) == DMA1_Stream1) || \
16995 ((__INSTANCE__) == DMA1_Stream2) || \
16996 ((__INSTANCE__) == DMA1_Stream3) || \
16997 ((__INSTANCE__) == DMA1_Stream4) || \
16998 ((__INSTANCE__) == DMA1_Stream5) || \
16999 ((__INSTANCE__) == DMA1_Stream6) || \
17000 ((__INSTANCE__) == DMA1_Stream7) || \
17001 ((__INSTANCE__) == DMA2_Stream0) || \
17002 ((__INSTANCE__) == DMA2_Stream1) || \
17003 ((__INSTANCE__) == DMA2_Stream2) || \
17004 ((__INSTANCE__) == DMA2_Stream3) || \
17005 ((__INSTANCE__) == DMA2_Stream4) || \
17006 ((__INSTANCE__) == DMA2_Stream5) || \
17007 ((__INSTANCE__) == DMA2_Stream6) || \
17008 ((__INSTANCE__) == DMA2_Stream7))
17009
17010/******************************* GPIO Instances *******************************/
17011#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
17012 ((__INSTANCE__) == GPIOB) || \
17013 ((__INSTANCE__) == GPIOC) || \
17014 ((__INSTANCE__) == GPIOD) || \
17015 ((__INSTANCE__) == GPIOE) || \
17016 ((__INSTANCE__) == GPIOF) || \
17017 ((__INSTANCE__) == GPIOG) || \
17018 ((__INSTANCE__) == GPIOH) || \
17019 ((__INSTANCE__) == GPIOI) || \
17020 ((__INSTANCE__) == GPIOJ) || \
17021 ((__INSTANCE__) == GPIOK))
17022
17023#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
17024 ((__INSTANCE__) == GPIOB) || \
17025 ((__INSTANCE__) == GPIOC) || \
17026 ((__INSTANCE__) == GPIOD) || \
17027 ((__INSTANCE__) == GPIOE) || \
17028 ((__INSTANCE__) == GPIOF) || \
17029 ((__INSTANCE__) == GPIOG) || \
17030 ((__INSTANCE__) == GPIOH) || \
17031 ((__INSTANCE__) == GPIOI) || \
17032 ((__INSTANCE__) == GPIOJ) || \
17033 ((__INSTANCE__) == GPIOK))
17034
17035/****************************** CEC Instances *********************************/
17036#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
17037
17038/****************************** QSPI Instances *********************************/
17039#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
17040
17041
17042/******************************** I2C Instances *******************************/
17043#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
17044 ((__INSTANCE__) == I2C2) || \
17045 ((__INSTANCE__) == I2C3) || \
17046 ((__INSTANCE__) == I2C4))
17047
17048/****************************** SMBUS Instances *******************************/
17049#define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
17050 ((__INSTANCE__) == I2C2) || \
17051 ((__INSTANCE__) == I2C3) || \
17052 ((__INSTANCE__) == I2C4))
17053
17054
17055/******************************** I2S Instances *******************************/
17056#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
17057 ((__INSTANCE__) == SPI2) || \
17058 ((__INSTANCE__) == SPI3))
17059
17060/******************************* LPTIM Instances ********************************/
17061#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
17062
17063
17064
17065
17066
17067/******************************* RNG Instances ********************************/
17068#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
17069
17070/****************************** RTC Instances *********************************/
17071#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
17072
17073/******************************* SAI Instances ********************************/
17074#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
17075 ((__PERIPH__) == SAI1_Block_B) || \
17076 ((__PERIPH__) == SAI2_Block_A) || \
17077 ((__PERIPH__) == SAI2_Block_B))
17078/* Legacy define */
17079#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
17080
17081/******************************** SDMMC Instances *******************************/
17082#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
17083
17084/****************************** SPDIFRX Instances *********************************/
17085#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
17086
17087/******************************** SPI Instances *******************************/
17088#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
17089 ((__INSTANCE__) == SPI2) || \
17090 ((__INSTANCE__) == SPI3) || \
17091 ((__INSTANCE__) == SPI4) || \
17092 ((__INSTANCE__) == SPI5) || \
17093 ((__INSTANCE__) == SPI6))
17094
17095/****************** TIM Instances : All supported instances *******************/
17096#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17097 ((__INSTANCE__) == TIM2) || \
17098 ((__INSTANCE__) == TIM3) || \
17099 ((__INSTANCE__) == TIM4) || \
17100 ((__INSTANCE__) == TIM5) || \
17101 ((__INSTANCE__) == TIM6) || \
17102 ((__INSTANCE__) == TIM7) || \
17103 ((__INSTANCE__) == TIM8) || \
17104 ((__INSTANCE__) == TIM9) || \
17105 ((__INSTANCE__) == TIM10) || \
17106 ((__INSTANCE__) == TIM11) || \
17107 ((__INSTANCE__) == TIM12) || \
17108 ((__INSTANCE__) == TIM13) || \
17109 ((__INSTANCE__) == TIM14))
17110
17111/****************** TIM Instances : supporting 32 bits counter ****************/
17112#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
17113 ((__INSTANCE__) == TIM5))
17114
17115/****************** TIM Instances : supporting the break function *************/
17116#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17117 ((INSTANCE) == TIM8))
17118
17119/************** TIM Instances : supporting Break source selection *************/
17120#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17121 ((INSTANCE) == TIM8))
17122
17123/****************** TIM Instances : supporting 2 break inputs *****************/
17124#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17125 ((INSTANCE) == TIM8))
17126
17127/************* TIM Instances : at least 1 capture/compare channel *************/
17128#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17129 ((__INSTANCE__) == TIM2) || \
17130 ((__INSTANCE__) == TIM3) || \
17131 ((__INSTANCE__) == TIM4) || \
17132 ((__INSTANCE__) == TIM5) || \
17133 ((__INSTANCE__) == TIM8) || \
17134 ((__INSTANCE__) == TIM9) || \
17135 ((__INSTANCE__) == TIM10) || \
17136 ((__INSTANCE__) == TIM11) || \
17137 ((__INSTANCE__) == TIM12) || \
17138 ((__INSTANCE__) == TIM13) || \
17139 ((__INSTANCE__) == TIM14))
17140
17141/************ TIM Instances : at least 2 capture/compare channels *************/
17142#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17143 ((__INSTANCE__) == TIM2) || \
17144 ((__INSTANCE__) == TIM3) || \
17145 ((__INSTANCE__) == TIM4) || \
17146 ((__INSTANCE__) == TIM5) || \
17147 ((__INSTANCE__) == TIM8) || \
17148 ((__INSTANCE__) == TIM9) || \
17149 ((__INSTANCE__) == TIM12))
17150
17151/************ TIM Instances : at least 3 capture/compare channels *************/
17152#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17153 ((__INSTANCE__) == TIM2) || \
17154 ((__INSTANCE__) == TIM3) || \
17155 ((__INSTANCE__) == TIM4) || \
17156 ((__INSTANCE__) == TIM5) || \
17157 ((__INSTANCE__) == TIM8))
17158
17159/************ TIM Instances : at least 4 capture/compare channels *************/
17160#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17161 ((__INSTANCE__) == TIM2) || \
17162 ((__INSTANCE__) == TIM3) || \
17163 ((__INSTANCE__) == TIM4) || \
17164 ((__INSTANCE__) == TIM5) || \
17165 ((__INSTANCE__) == TIM8))
17166
17167/****************** TIM Instances : at least 5 capture/compare channels *******/
17168#define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17169 ((__INSTANCE__) == TIM8))
17170
17171/****************** TIM Instances : at least 6 capture/compare channels *******/
17172#define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17173 ((__INSTANCE__) == TIM8))
17174
17175/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
17176#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17177 ((__INSTANCE__) == TIM8))
17178
17179/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
17180#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17181 ((__INSTANCE__) == TIM8) || \
17182 ((__INSTANCE__) == TIM2) || \
17183 ((__INSTANCE__) == TIM3) || \
17184 ((__INSTANCE__) == TIM4) || \
17185 ((__INSTANCE__) == TIM5) || \
17186 ((__INSTANCE__) == TIM6) || \
17187 ((__INSTANCE__) == TIM7))
17188
17189/************ TIM Instances : DMA requests generation (CCxDE) *****************/
17190#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17191 ((__INSTANCE__) == TIM2) || \
17192 ((__INSTANCE__) == TIM3) || \
17193 ((__INSTANCE__) == TIM4) || \
17194 ((__INSTANCE__) == TIM5) || \
17195 ((__INSTANCE__) == TIM8))
17196
17197/******************** TIM Instances : DMA burst feature ***********************/
17198#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17199 ((__INSTANCE__) == TIM2) || \
17200 ((__INSTANCE__) == TIM3) || \
17201 ((__INSTANCE__) == TIM4) || \
17202 ((__INSTANCE__) == TIM5) || \
17203 ((__INSTANCE__) == TIM8))
17204
17205/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
17206#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
17207 (((__INSTANCE__) == TIM1) || \
17208 ((__INSTANCE__) == TIM8))
17209
17210/****************** TIM Instances : supporting counting mode selection ********/
17211#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17212 ((__INSTANCE__) == TIM2) || \
17213 ((__INSTANCE__) == TIM3) || \
17214 ((__INSTANCE__) == TIM4) || \
17215 ((__INSTANCE__) == TIM5) || \
17216 ((__INSTANCE__) == TIM8))
17217
17218/****************** TIM Instances : supporting encoder interface **************/
17219#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17220 ((__INSTANCE__) == TIM2) || \
17221 ((__INSTANCE__) == TIM3) || \
17222 ((__INSTANCE__) == TIM4) || \
17223 ((__INSTANCE__) == TIM5) || \
17224 ((__INSTANCE__) == TIM8))
17225
17226/****************** TIM Instances : supporting OCxREF clear *******************/
17227#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
17228 (((__INSTANCE__) == TIM2) || \
17229 ((__INSTANCE__) == TIM3) || \
17230 ((__INSTANCE__) == TIM4) || \
17231 ((__INSTANCE__) == TIM5))
17232
17233/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
17234#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
17235 (((__INSTANCE__) == TIM1) || \
17236 ((__INSTANCE__) == TIM2) || \
17237 ((__INSTANCE__) == TIM3) || \
17238 ((__INSTANCE__) == TIM4) || \
17239 ((__INSTANCE__) == TIM5) || \
17240 ((__INSTANCE__) == TIM8))
17241
17242/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
17243#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
17244 (((__INSTANCE__) == TIM1) || \
17245 ((__INSTANCE__) == TIM2) || \
17246 ((__INSTANCE__) == TIM3) || \
17247 ((__INSTANCE__) == TIM4) || \
17248 ((__INSTANCE__) == TIM5) || \
17249 ((__INSTANCE__) == TIM8))
17250
17251/******************** TIM Instances : Advanced-control timers *****************/
17252#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17253 ((__INSTANCE__) == TIM8))
17254
17255/******************* TIM Instances : Timer input XOR function *****************/
17256#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17257 ((__INSTANCE__) == TIM2) || \
17258 ((__INSTANCE__) == TIM3) || \
17259 ((__INSTANCE__) == TIM4) || \
17260 ((__INSTANCE__) == TIM5) || \
17261 ((__INSTANCE__) == TIM8))
17262
17263/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
17264#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17265 ((__INSTANCE__) == TIM2) || \
17266 ((__INSTANCE__) == TIM3) || \
17267 ((__INSTANCE__) == TIM4) || \
17268 ((__INSTANCE__) == TIM5) || \
17269 ((__INSTANCE__) == TIM6) || \
17270 ((__INSTANCE__) == TIM7) || \
17271 ((__INSTANCE__) == TIM8))
17272
17273/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
17274#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17275 ((__INSTANCE__) == TIM2) || \
17276 ((__INSTANCE__) == TIM3) || \
17277 ((__INSTANCE__) == TIM4) || \
17278 ((__INSTANCE__) == TIM5) || \
17279 ((__INSTANCE__) == TIM8) || \
17280 ((__INSTANCE__) == TIM9) || \
17281 ((__INSTANCE__) == TIM12))
17282
17283/***************** TIM Instances : external trigger input available ************/
17284#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17285 ((__INSTANCE__) == TIM2) || \
17286 ((__INSTANCE__) == TIM3) || \
17287 ((__INSTANCE__) == TIM4) || \
17288 ((__INSTANCE__) == TIM5) || \
17289 ((__INSTANCE__) == TIM8))
17290
17291/****************** TIM Instances : remapping capability **********************/
17292#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
17293 ((__INSTANCE__) == TIM5) || \
17294 ((__INSTANCE__) == TIM11))
17295
17296/******************* TIM Instances : output(s) available **********************/
17297#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
17298 ((((__INSTANCE__) == TIM1) && \
17299 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17300 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17301 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17302 ((__CHANNEL__) == TIM_CHANNEL_4) || \
17303 ((__CHANNEL__) == TIM_CHANNEL_5) || \
17304 ((__CHANNEL__) == TIM_CHANNEL_6))) \
17305 || \
17306 (((__INSTANCE__) == TIM2) && \
17307 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17308 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17309 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17310 ((__CHANNEL__) == TIM_CHANNEL_4))) \
17311 || \
17312 (((__INSTANCE__) == TIM3) && \
17313 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17314 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17315 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17316 ((__CHANNEL__) == TIM_CHANNEL_4))) \
17317 || \
17318 (((__INSTANCE__) == TIM4) && \
17319 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17320 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17321 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17322 ((__CHANNEL__) == TIM_CHANNEL_4))) \
17323 || \
17324 (((__INSTANCE__) == TIM5) && \
17325 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17326 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17327 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17328 ((__CHANNEL__) == TIM_CHANNEL_4))) \
17329 || \
17330 (((__INSTANCE__) == TIM8) && \
17331 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17332 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17333 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17334 ((__CHANNEL__) == TIM_CHANNEL_4) || \
17335 ((__CHANNEL__) == TIM_CHANNEL_5) || \
17336 ((__CHANNEL__) == TIM_CHANNEL_6))) \
17337 || \
17338 (((__INSTANCE__) == TIM9) && \
17339 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17340 ((__CHANNEL__) == TIM_CHANNEL_2))) \
17341 || \
17342 (((__INSTANCE__) == TIM10) && \
17343 (((__CHANNEL__) == TIM_CHANNEL_1))) \
17344 || \
17345 (((__INSTANCE__) == TIM11) && \
17346 (((__CHANNEL__) == TIM_CHANNEL_1))) \
17347 || \
17348 (((__INSTANCE__) == TIM12) && \
17349 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17350 ((__CHANNEL__) == TIM_CHANNEL_2))) \
17351 || \
17352 (((__INSTANCE__) == TIM13) && \
17353 (((__CHANNEL__) == TIM_CHANNEL_1))) \
17354 || \
17355 (((__INSTANCE__) == TIM14) && \
17356 (((__CHANNEL__) == TIM_CHANNEL_1))))
17357
17358/************ TIM Instances : complementary output(s) available ***************/
17359#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
17360 ((((__INSTANCE__) == TIM1) && \
17361 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17362 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17363 ((__CHANNEL__) == TIM_CHANNEL_3))) \
17364 || \
17365 (((__INSTANCE__) == TIM8) && \
17366 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17367 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17368 ((__CHANNEL__) == TIM_CHANNEL_3))))
17369
17370/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
17371#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
17372 (((__INSTANCE__) == TIM1) || \
17373 ((__INSTANCE__) == TIM8) )
17374
17375/****************** TIM Instances : supporting clock division *****************/
17376#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17377 ((__INSTANCE__) == TIM2) || \
17378 ((__INSTANCE__) == TIM3) || \
17379 ((__INSTANCE__) == TIM4) || \
17380 ((__INSTANCE__) == TIM5) || \
17381 ((__INSTANCE__) == TIM8) || \
17382 ((__INSTANCE__) == TIM9) || \
17383 ((__INSTANCE__) == TIM10) || \
17384 ((__INSTANCE__) == TIM11) || \
17385 ((__INSTANCE__) == TIM12) || \
17386 ((__INSTANCE__) == TIM13) || \
17387 ((__INSTANCE__) == TIM14))
17388
17389/****************** TIM Instances : supporting repetition counter *************/
17390#define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17391 ((__INSTANCE__) == TIM8))
17392
17393/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
17394#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17395 ((__INSTANCE__) == TIM2) || \
17396 ((__INSTANCE__) == TIM3) || \
17397 ((__INSTANCE__) == TIM4) || \
17398 ((__INSTANCE__) == TIM5) || \
17399 ((__INSTANCE__) == TIM8) || \
17400 ((__INSTANCE__) == TIM9) || \
17401 ((__INSTANCE__) == TIM12))
17402
17403/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
17404#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17405 ((__INSTANCE__) == TIM2) || \
17406 ((__INSTANCE__) == TIM3) || \
17407 ((__INSTANCE__) == TIM4) || \
17408 ((__INSTANCE__) == TIM5) || \
17409 ((__INSTANCE__) == TIM8))
17410
17411/****************** TIM Instances : supporting Hall sensor interface **********/
17412#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17413 ((__INSTANCE__) == TIM2) || \
17414 ((__INSTANCE__) == TIM3) || \
17415 ((__INSTANCE__) == TIM4) || \
17416 ((__INSTANCE__) == TIM5) || \
17417 ((__INSTANCE__) == TIM8))
17418
17419/****************** TIM Instances : supporting commutation event generation ***/
17420#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17421 ((__INSTANCE__) == TIM8))
17422
17423/******************** USART Instances : Synchronous mode **********************/
17424#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
17425 ((__INSTANCE__) == USART2) || \
17426 ((__INSTANCE__) == USART3) || \
17427 ((__INSTANCE__) == USART6))
17428
17429/******************** UART Instances : Asynchronous mode **********************/
17430#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
17431 ((__INSTANCE__) == USART2) || \
17432 ((__INSTANCE__) == USART3) || \
17433 ((__INSTANCE__) == UART4) || \
17434 ((__INSTANCE__) == UART5) || \
17435 ((__INSTANCE__) == USART6) || \
17436 ((__INSTANCE__) == UART7) || \
17437 ((__INSTANCE__) == UART8))
17438
17439/****************** UART Instances : Auto Baud Rate detection ****************/
17440#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
17441 ((__INSTANCE__) == USART2) || \
17442 ((__INSTANCE__) == USART3) || \
17443 ((__INSTANCE__) == USART6))
17444
17445/****************** UART Instances : Driver Enable *****************/
17446#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
17447 ((__INSTANCE__) == USART2) || \
17448 ((__INSTANCE__) == USART3) || \
17449 ((__INSTANCE__) == UART4) || \
17450 ((__INSTANCE__) == UART5) || \
17451 ((__INSTANCE__) == USART6) || \
17452 ((__INSTANCE__) == UART7) || \
17453 ((__INSTANCE__) == UART8))
17454
17455/******************** UART Instances : Half-Duplex mode **********************/
17456#define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
17457 ((__INSTANCE__) == USART2) || \
17458 ((__INSTANCE__) == USART3) || \
17459 ((__INSTANCE__) == UART4) || \
17460 ((__INSTANCE__) == UART5) || \
17461 ((__INSTANCE__) == USART6) || \
17462 ((__INSTANCE__) == UART7) || \
17463 ((__INSTANCE__) == UART8))
17464
17465/****************** UART Instances : Hardware Flow control ********************/
17466#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
17467 ((__INSTANCE__) == USART2) || \
17468 ((__INSTANCE__) == USART3) || \
17469 ((__INSTANCE__) == UART4) || \
17470 ((__INSTANCE__) == UART5) || \
17471 ((__INSTANCE__) == USART6) || \
17472 ((__INSTANCE__) == UART7) || \
17473 ((__INSTANCE__) == UART8))
17474
17475/******************** UART Instances : LIN mode **********************/
17476#define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
17477 ((__INSTANCE__) == USART2) || \
17478 ((__INSTANCE__) == USART3) || \
17479 ((__INSTANCE__) == UART4) || \
17480 ((__INSTANCE__) == UART5) || \
17481 ((__INSTANCE__) == USART6) || \
17482 ((__INSTANCE__) == UART7) || \
17483 ((__INSTANCE__) == UART8))
17484
17485/********************* UART Instances : Smart card mode ***********************/
17486#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
17487 ((__INSTANCE__) == USART2) || \
17488 ((__INSTANCE__) == USART3) || \
17489 ((__INSTANCE__) == USART6))
17490
17491/*********************** UART Instances : IRDA mode ***************************/
17492#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
17493 ((__INSTANCE__) == USART2) || \
17494 ((__INSTANCE__) == USART3) || \
17495 ((__INSTANCE__) == UART4) || \
17496 ((__INSTANCE__) == UART5) || \
17497 ((__INSTANCE__) == USART6) || \
17498 ((__INSTANCE__) == UART7) || \
17499 ((__INSTANCE__) == UART8))
17500
17501/****************************** IWDG Instances ********************************/
17502#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
17503
17504/****************************** WWDG Instances ********************************/
17505#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
17506
17507/*********************** PCD Instances ****************************************/
17508#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
17509 ((INSTANCE) == USB_OTG_HS))
17510
17511/*********************** HCD Instances ****************************************/
17512#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
17513 ((INSTANCE) == USB_OTG_HS))
17514
17515/******************************************************************************/
17516/* For a painless codes migration between the STM32F7xx device product */
17517/* lines, the aliases defined below are put in place to overcome the */
17518/* differences in the interrupt handlers and IRQn definitions. */
17519/* No need to update developed interrupt code when moving across */
17520/* product lines within the same STM32F7 Family */
17521/******************************************************************************/
17522
17523/* Aliases for __IRQn */
17524#define HASH_RNG_IRQn RNG_IRQn
17525
17526/* Aliases for __IRQHandler */
17527#define HASH_RNG_IRQHandler RNG_IRQHandler
17528
17541#ifdef __cplusplus
17542}
17543#endif /* __cplusplus */
17544
17545#endif /* __STM32F745xx_H */
17546
17547
__IO
#define __IO
Definition core_cm3.h:170
__I
#define __I
Definition core_cm3.h:167
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f745xx.h:49
PendSV_IRQn
@ PendSV_IRQn
Definition stm32f745xx.h:57
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition stm32f745xx.h:122
EXTI2_IRQn
@ EXTI2_IRQn
Definition stm32f745xx.h:68
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition stm32f745xx.h:73
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition stm32f745xx.h:82
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition stm32f745xx.h:63
SPDIF_RX_IRQn
@ SPDIF_RX_IRQn
Definition stm32f745xx.h:154
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition stm32f745xx.h:135
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition stm32f745xx.h:116
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition stm32f745xx.h:129
UART7_IRQn
@ UART7_IRQn
Definition stm32f745xx.h:141
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition stm32f745xx.h:92
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition stm32f745xx.h:93
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition stm32f745xx.h:52
SAI1_IRQn
@ SAI1_IRQn
Definition stm32f745xx.h:146
TIM4_IRQn
@ TIM4_IRQn
Definition stm32f745xx.h:90
TIM2_IRQn
@ TIM2_IRQn
Definition stm32f745xx.h:88
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition stm32f745xx.h:130
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition stm32f745xx.h:103
USART2_IRQn
@ USART2_IRQn
Definition stm32f745xx.h:98
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition stm32f745xx.h:119
SVCall_IRQn
@ SVCall_IRQn
Definition stm32f745xx.h:55
ADC_IRQn
@ ADC_IRQn
Definition stm32f745xx.h:78
SPI3_IRQn
@ SPI3_IRQn
Definition stm32f745xx.h:111
SPI2_IRQn
@ SPI2_IRQn
Definition stm32f745xx.h:96
TIM7_IRQn
@ TIM7_IRQn
Definition stm32f745xx.h:115
UART8_IRQn
@ UART8_IRQn
Definition stm32f745xx.h:142
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition stm32f745xx.h:126
RCC_IRQn
@ RCC_IRQn
Definition stm32f745xx.h:65
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition stm32f745xx.h:114
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition stm32f745xx.h:134
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition stm32f745xx.h:94
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition stm32f745xx.h:149
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition stm32f745xx.h:106
UsageFault_IRQn
@ UsageFault_IRQn
Definition stm32f745xx.h:54
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition stm32f745xx.h:153
SysTick_IRQn
@ SysTick_IRQn
Definition stm32f745xx.h:58
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition stm32f745xx.h:133
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition stm32f745xx.h:132
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition stm32f745xx.h:124
BusFault_IRQn
@ BusFault_IRQn
Definition stm32f745xx.h:53
CEC_IRQn
@ CEC_IRQn
Definition stm32f745xx.h:151
SPI5_IRQn
@ SPI5_IRQn
Definition stm32f745xx.h:144
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition stm32f745xx.h:56
RNG_IRQn
@ RNG_IRQn
Definition stm32f745xx.h:139
FLASH_IRQn
@ FLASH_IRQn
Definition stm32f745xx.h:64
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition stm32f745xx.h:128
WWDG_IRQn
@ WWDG_IRQn
Definition stm32f745xx.h:60
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition stm32f745xx.h:91
TIM3_IRQn
@ TIM3_IRQn
Definition stm32f745xx.h:89
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition stm32f745xx.h:117
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition stm32f745xx.h:79
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition stm32f745xx.h:136
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition stm32f745xx.h:109
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition stm32f745xx.h:71
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition stm32f745xx.h:100
SPI4_IRQn
@ SPI4_IRQn
Definition stm32f745xx.h:143
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f745xx.h:85
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition stm32f745xx.h:83
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition stm32f745xx.h:72
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition stm32f745xx.h:150
SPI6_IRQn
@ SPI6_IRQn
Definition stm32f745xx.h:145
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition stm32f745xx.h:127
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition stm32f745xx.h:102
FPU_IRQn
@ FPU_IRQn
Definition stm32f745xx.h:140
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition stm32f745xx.h:104
USART6_IRQn
@ USART6_IRQn
Definition stm32f745xx.h:131
SPI1_IRQn
@ SPI1_IRQn
Definition stm32f745xx.h:95
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition stm32f745xx.h:137
PVD_IRQn
@ PVD_IRQn
Definition stm32f745xx.h:61
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f745xx.h:86
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition stm32f745xx.h:84
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition stm32f745xx.h:125
FMC_IRQn
@ FMC_IRQn
Definition stm32f745xx.h:108
EXTI0_IRQn
@ EXTI0_IRQn
Definition stm32f745xx.h:66
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition stm32f745xx.h:80
EXTI4_IRQn
@ EXTI4_IRQn
Definition stm32f745xx.h:70
SAI2_IRQn
@ SAI2_IRQn
Definition stm32f745xx.h:148
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition stm32f745xx.h:118
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f745xx.h:62
UART5_IRQn
@ UART5_IRQn
Definition stm32f745xx.h:113
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition stm32f745xx.h:76
DMA2D_IRQn
@ DMA2D_IRQn
Definition stm32f745xx.h:147
DCMI_IRQn
@ DCMI_IRQn
Definition stm32f745xx.h:138
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition stm32f745xx.h:152
ETH_IRQn
@ ETH_IRQn
Definition stm32f745xx.h:121
USART1_IRQn
@ USART1_IRQn
Definition stm32f745xx.h:97
EXTI3_IRQn
@ EXTI3_IRQn
Definition stm32f745xx.h:69
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition stm32f745xx.h:51
UART4_IRQn
@ UART4_IRQn
Definition stm32f745xx.h:112
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition stm32f745xx.h:105
EXTI1_IRQn
@ EXTI1_IRQn
Definition stm32f745xx.h:67
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition stm32f745xx.h:120
TIM5_IRQn
@ TIM5_IRQn
Definition stm32f745xx.h:110
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition stm32f745xx.h:107
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f745xx.h:75
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition stm32f745xx.h:77
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition stm32f745xx.h:87
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition stm32f745xx.h:123
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition stm32f745xx.h:81
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition stm32f745xx.h:74
USART3_IRQn
@ USART3_IRQn
Definition stm32f745xx.h:99
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition stm32f745xx.h:101
PMC
#define PMC
Definition MK60D10.h:8809
ADC_Common_TypeDef
Definition stm32f107xc.h:187
ADC_TypeDef
Analog to Digital Converter
Definition stm32f107xc.h:163
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition stm32f107xc.h:267
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition stm32f107xc.h:279
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition stm32f107xc.h:255
CAN_TypeDef
Controller Area Network.
Definition stm32f107xc.h:289
CEC_TypeDef
HDMI-CEC.
Definition stm32f745xx.h:287
CEC_TypeDef::CFGR
__IO uint32_t CFGR
Definition stm32f745xx.h:289
CEC_TypeDef::CR
__IO uint32_t CR
Definition stm32f745xx.h:288
CEC_TypeDef::TXDR
__IO uint32_t TXDR
Definition stm32f745xx.h:290
CEC_TypeDef::IER
__IO uint32_t IER
Definition stm32f745xx.h:293
CEC_TypeDef::RXDR
__IO uint32_t RXDR
Definition stm32f745xx.h:291
CEC_TypeDef::ISR
__IO uint32_t ISR
Definition stm32f745xx.h:292
CRC_TypeDef
CRC calculation unit.
Definition stm32f107xc.h:319
CRC_TypeDef::POL
__IO uint32_t POL
Definition stm32f745xx.h:309
CRC_TypeDef::INIT
__IO uint32_t INIT
Definition stm32f745xx.h:308
CRC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32f745xx.h:307
DAC_TypeDef
Digital to Analog Converter.
Definition stm32f107xc.h:332
DBGMCU_TypeDef
Debug MCU.
Definition stm32f107xc.h:353
DCMI_TypeDef
DCMI.
Definition stm32f207xx.h:325
DMA2D_TypeDef
DMA2D Controller.
Definition stm32f427xx.h:373
DMA_Stream_TypeDef
DMA Controller.
Definition stm32f207xx.h:344
DMA_TypeDef
Definition stm32f107xc.h:371
ETH_TypeDef
Ethernet MAC.
Definition stm32f107xc.h:383
EXTI_TypeDef
External Interrupt/Event Controller.
Definition stm32f107xc.h:455
FLASH_TypeDef
FLASH Registers.
Definition stm32f107xc.h:469
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition stm32f427xx.h:517
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition stm32f427xx.h:508
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition stm32f469xx.h:611
FMC_Bank3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition stm32f745xx.h:555
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition stm32f427xx.h:560
GPIO_TypeDef
General Purpose I/O.
Definition stm32f107xc.h:502
I2C_TypeDef
Inter Integrated Circuit Interface.
Definition stm32f107xc.h:529
I2C_TypeDef::ISR
__IO uint32_t ISR
Definition stm32f745xx.h:615
I2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition stm32f745xx.h:618
I2C_TypeDef::PECR
__IO uint32_t PECR
Definition stm32f745xx.h:617
I2C_TypeDef::ICR
__IO uint32_t ICR
Definition stm32f745xx.h:616
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition stm32f745xx.h:613
I2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition stm32f745xx.h:614
I2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition stm32f745xx.h:619
IWDG_TypeDef
Independent WATCHDOG.
Definition stm32f107xc.h:546
IWDG_TypeDef::WINR
__IO uint32_t WINR
Definition stm32f745xx.h:632
LPTIM_TypeDef
LPTIMIMER.
Definition stm32f745xx.h:892
LPTIM_TypeDef::ICR
__IO uint32_t ICR
Definition stm32f745xx.h:894
LPTIM_TypeDef::ARR
__IO uint32_t ARR
Definition stm32f745xx.h:899
LPTIM_TypeDef::CMP
__IO uint32_t CMP
Definition stm32f745xx.h:898
LPTIM_TypeDef::CFGR
__IO uint32_t CFGR
Definition stm32f745xx.h:896
LPTIM_TypeDef::IER
__IO uint32_t IER
Definition stm32f745xx.h:895
LPTIM_TypeDef::ISR
__IO uint32_t ISR
Definition stm32f745xx.h:893
LPTIM_TypeDef::CNT
__IO uint32_t CNT
Definition stm32f745xx.h:900
LPTIM_TypeDef::CR
__IO uint32_t CR
Definition stm32f745xx.h:897
PWR_TypeDef
Power Control.
Definition stm32f107xc.h:558
PWR_TypeDef::CR1
__IO uint32_t CR1
Definition stm32f745xx.h:643
PWR_TypeDef::CSR1
__IO uint32_t CSR1
Definition stm32f745xx.h:644
PWR_TypeDef::CSR2
__IO uint32_t CSR2
Definition stm32f745xx.h:646
PWR_TypeDef::CR2
__IO uint32_t CR2
Definition stm32f745xx.h:645
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition stm32f469xx.h:909
RCC_TypeDef
Reset and Clock Control.
Definition stm32f107xc.h:568
RCC_TypeDef::DCKCFGR1
__IO uint32_t DCKCFGR1
Definition stm32f745xx.h:687
RCC_TypeDef::DCKCFGR2
__IO uint32_t DCKCFGR2
Definition stm32f745xx.h:688
RNG_TypeDef
RNG.
Definition stm32f207xx.h:782
RTC_TypeDef
Real-Time Clock.
Definition stm32f107xc.h:590
RTC_TypeDef::BKP25R
__IO uint32_t BKP25R
Definition stm32f745xx.h:743
RTC_TypeDef::BKP21R
__IO uint32_t BKP21R
Definition stm32f745xx.h:739
RTC_TypeDef::BKP30R
__IO uint32_t BKP30R
Definition stm32f745xx.h:748
RTC_TypeDef::reserved
uint32_t reserved
Definition stm32f745xx.h:704
RTC_TypeDef::BKP20R
__IO uint32_t BKP20R
Definition stm32f745xx.h:738
RTC_TypeDef::BKP31R
__IO uint32_t BKP31R
Definition stm32f745xx.h:749
RTC_TypeDef::BKP27R
__IO uint32_t BKP27R
Definition stm32f745xx.h:745
RTC_TypeDef::BKP22R
__IO uint32_t BKP22R
Definition stm32f745xx.h:740
RTC_TypeDef::BKP23R
__IO uint32_t BKP23R
Definition stm32f745xx.h:741
RTC_TypeDef::BKP29R
__IO uint32_t BKP29R
Definition stm32f745xx.h:747
RTC_TypeDef::BKP26R
__IO uint32_t BKP26R
Definition stm32f745xx.h:744
RTC_TypeDef::BKP28R
__IO uint32_t BKP28R
Definition stm32f745xx.h:746
RTC_TypeDef::BKP24R
__IO uint32_t BKP24R
Definition stm32f745xx.h:742
RTC_TypeDef::TAMPCR
__IO uint32_t TAMPCR
Definition stm32f745xx.h:714
RTC_TypeDef::OR
__IO uint32_t OR
Definition stm32f745xx.h:717
SAI_Block_TypeDef
Definition stm32f427xx.h:737
SAI_TypeDef
Serial Audio Interface.
Definition stm32f427xx.h:732
SDMMC_TypeDef
SD host Interface.
Definition stm32f745xx.h:794
SDMMC_TypeDef::FIFOCNT
__I uint32_t FIFOCNT
Definition stm32f745xx.h:812
SDMMC_TypeDef::RESPCMD
__I uint32_t RESPCMD
Definition stm32f745xx.h:799
SDMMC_TypeDef::RESP2
__I uint32_t RESP2
Definition stm32f745xx.h:801
SDMMC_TypeDef::DLEN
__IO uint32_t DLEN
Definition stm32f745xx.h:805
SDMMC_TypeDef::MASK
__IO uint32_t MASK
Definition stm32f745xx.h:810
SDMMC_TypeDef::DCOUNT
__I uint32_t DCOUNT
Definition stm32f745xx.h:807
SDMMC_TypeDef::ICR
__IO uint32_t ICR
Definition stm32f745xx.h:809
SDMMC_TypeDef::STA
__I uint32_t STA
Definition stm32f745xx.h:808
SDMMC_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition stm32f745xx.h:806
SDMMC_TypeDef::ARG
__IO uint32_t ARG
Definition stm32f745xx.h:797
SDMMC_TypeDef::POWER
__IO uint32_t POWER
Definition stm32f745xx.h:795
SDMMC_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition stm32f745xx.h:804
SDMMC_TypeDef::FIFO
__IO uint32_t FIFO
Definition stm32f745xx.h:814
SDMMC_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition stm32f745xx.h:796
SDMMC_TypeDef::RESP1
__I uint32_t RESP1
Definition stm32f745xx.h:800
SDMMC_TypeDef::CMD
__IO uint32_t CMD
Definition stm32f745xx.h:798
SDMMC_TypeDef::RESP3
__I uint32_t RESP3
Definition stm32f745xx.h:802
SDMMC_TypeDef::RESP4
__I uint32_t RESP4
Definition stm32f745xx.h:803
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition stm32f745xx.h:779
SPDIFRX_TypeDef::IMR
__IO uint32_t IMR
Definition stm32f745xx.h:781
SPDIFRX_TypeDef::IFCR
__IO uint32_t IFCR
Definition stm32f745xx.h:783
SPDIFRX_TypeDef::DIR
__IO uint32_t DIR
Definition stm32f745xx.h:786
SPDIFRX_TypeDef::CSR
__IO uint32_t CSR
Definition stm32f745xx.h:785
SPDIFRX_TypeDef::DR
__IO uint32_t DR
Definition stm32f745xx.h:784
SPDIFRX_TypeDef::SR
__IO uint32_t SR
Definition stm32f745xx.h:782
SPDIFRX_TypeDef::CR
__IO uint32_t CR
Definition stm32f745xx.h:780
SPI_TypeDef
Serial Peripheral Interface.
Definition stm32f107xc.h:608
SYSCFG_TypeDef
System configuration controller.
Definition stm32f207xx.h:542
TIM_TypeDef
TIM Timers.
Definition stm32f107xc.h:624
TIM_TypeDef::CCR6
__IO uint32_t CCR6
Definition stm32f745xx.h:884
TIM_TypeDef::CCMR3
__IO uint32_t CCMR3
Definition stm32f745xx.h:882
TIM_TypeDef::CCR5
__IO uint32_t CCR5
Definition stm32f745xx.h:883
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32f107xc.h:654
USART_TypeDef::TDR
__IO uint32_t TDR
Definition stm32f745xx.h:920
USART_TypeDef::RTOR
__IO uint32_t RTOR
Definition stm32f745xx.h:915
USART_TypeDef::ISR
__IO uint32_t ISR
Definition stm32f745xx.h:917
USART_TypeDef::RDR
__IO uint32_t RDR
Definition stm32f745xx.h:919
USART_TypeDef::ICR
__IO uint32_t ICR
Definition stm32f745xx.h:918
USART_TypeDef::RQR
__IO uint32_t RQR
Definition stm32f745xx.h:916
USB_OTG_DeviceTypeDef
__device_Registers
Definition stm32f107xc.h:696
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition stm32f107xc.h:670
USB_OTG_GlobalTypeDef::Reserved7
uint32_t Reserved7
Definition stm32f745xx.h:975
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition stm32f107xc.h:770
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition stm32f107xc.h:755
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition stm32f107xc.h:724
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition stm32f107xc.h:740
WWDG_TypeDef
Window WATCHDOG.
Definition stm32f107xc.h:785
system_stm32f7xx.h
CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.