mikroSDK Reference Manual
stm32f756xx.h
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1
34#ifndef __STM32F756xx_H
35#define __STM32F756xx_H
36
37#ifdef __cplusplus
38 extern "C" {
39#endif /* __cplusplus */
40
49typedef enum
50{
51/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
52 NonMaskableInt_IRQn = -14,
53 MemoryManagement_IRQn = -12,
54 BusFault_IRQn = -11,
55 UsageFault_IRQn = -10,
56 SVCall_IRQn = -5,
57 DebugMonitor_IRQn = -4,
58 PendSV_IRQn = -2,
59 SysTick_IRQn = -1,
60/****** STM32 specific Interrupt Numbers **********************************************************************/
61 WWDG_IRQn = 0,
62 PVD_IRQn = 1,
63 TAMP_STAMP_IRQn = 2,
64 RTC_WKUP_IRQn = 3,
65 FLASH_IRQn = 4,
66 RCC_IRQn = 5,
67 EXTI0_IRQn = 6,
68 EXTI1_IRQn = 7,
69 EXTI2_IRQn = 8,
70 EXTI3_IRQn = 9,
71 EXTI4_IRQn = 10,
72 DMA1_Stream0_IRQn = 11,
73 DMA1_Stream1_IRQn = 12,
74 DMA1_Stream2_IRQn = 13,
75 DMA1_Stream3_IRQn = 14,
76 DMA1_Stream4_IRQn = 15,
77 DMA1_Stream5_IRQn = 16,
78 DMA1_Stream6_IRQn = 17,
79 ADC_IRQn = 18,
80 CAN1_TX_IRQn = 19,
81 CAN1_RX0_IRQn = 20,
82 CAN1_RX1_IRQn = 21,
83 CAN1_SCE_IRQn = 22,
84 EXTI9_5_IRQn = 23,
85 TIM1_BRK_TIM9_IRQn = 24,
86 TIM1_UP_TIM10_IRQn = 25,
87 TIM1_TRG_COM_TIM11_IRQn = 26,
88 TIM1_CC_IRQn = 27,
89 TIM2_IRQn = 28,
90 TIM3_IRQn = 29,
91 TIM4_IRQn = 30,
92 I2C1_EV_IRQn = 31,
93 I2C1_ER_IRQn = 32,
94 I2C2_EV_IRQn = 33,
95 I2C2_ER_IRQn = 34,
96 SPI1_IRQn = 35,
97 SPI2_IRQn = 36,
98 USART1_IRQn = 37,
99 USART2_IRQn = 38,
100 USART3_IRQn = 39,
101 EXTI15_10_IRQn = 40,
102 RTC_Alarm_IRQn = 41,
103 OTG_FS_WKUP_IRQn = 42,
104 TIM8_BRK_TIM12_IRQn = 43,
105 TIM8_UP_TIM13_IRQn = 44,
106 TIM8_TRG_COM_TIM14_IRQn = 45,
107 TIM8_CC_IRQn = 46,
108 DMA1_Stream7_IRQn = 47,
109 FMC_IRQn = 48,
110 SDMMC1_IRQn = 49,
111 TIM5_IRQn = 50,
112 SPI3_IRQn = 51,
113 UART4_IRQn = 52,
114 UART5_IRQn = 53,
115 TIM6_DAC_IRQn = 54,
116 TIM7_IRQn = 55,
117 DMA2_Stream0_IRQn = 56,
118 DMA2_Stream1_IRQn = 57,
119 DMA2_Stream2_IRQn = 58,
120 DMA2_Stream3_IRQn = 59,
121 DMA2_Stream4_IRQn = 60,
122 ETH_IRQn = 61,
123 ETH_WKUP_IRQn = 62,
124 CAN2_TX_IRQn = 63,
125 CAN2_RX0_IRQn = 64,
126 CAN2_RX1_IRQn = 65,
127 CAN2_SCE_IRQn = 66,
128 OTG_FS_IRQn = 67,
129 DMA2_Stream5_IRQn = 68,
130 DMA2_Stream6_IRQn = 69,
131 DMA2_Stream7_IRQn = 70,
132 USART6_IRQn = 71,
133 I2C3_EV_IRQn = 72,
134 I2C3_ER_IRQn = 73,
135 OTG_HS_EP1_OUT_IRQn = 74,
136 OTG_HS_EP1_IN_IRQn = 75,
137 OTG_HS_WKUP_IRQn = 76,
138 OTG_HS_IRQn = 77,
139 DCMI_IRQn = 78,
140 CRYP_IRQn = 79,
141 HASH_RNG_IRQn = 80,
142 FPU_IRQn = 81,
143 UART7_IRQn = 82,
144 UART8_IRQn = 83,
145 SPI4_IRQn = 84,
146 SPI5_IRQn = 85,
147 SPI6_IRQn = 86,
148 SAI1_IRQn = 87,
149 LTDC_IRQn = 88,
150 LTDC_ER_IRQn = 89,
151 DMA2D_IRQn = 90,
152 SAI2_IRQn = 91,
153 QUADSPI_IRQn = 92,
154 LPTIM1_IRQn = 93,
155 CEC_IRQn = 94,
156 I2C4_EV_IRQn = 95,
157 I2C4_ER_IRQn = 96,
158 SPDIF_RX_IRQn = 97,
159} IRQn_Type;
160
168#define __CM7_REV 0x0001U
169#define __MPU_PRESENT 1
170#define __NVIC_PRIO_BITS 4
171#define __Vendor_SysTickConfig 0
172#define __FPU_PRESENT 1
173#define __ICACHE_PRESENT 1
174#define __DCACHE_PRESENT 1
175#include "core_cm7.h"
178#include "system_stm32f7xx.h"
179#include <stdint.h>
180
189typedef struct
190{
191 __IO uint32_t SR;
192 __IO uint32_t CR1;
193 __IO uint32_t CR2;
194 __IO uint32_t SMPR1;
195 __IO uint32_t SMPR2;
196 __IO uint32_t JOFR1;
197 __IO uint32_t JOFR2;
198 __IO uint32_t JOFR3;
199 __IO uint32_t JOFR4;
200 __IO uint32_t HTR;
201 __IO uint32_t LTR;
202 __IO uint32_t SQR1;
203 __IO uint32_t SQR2;
204 __IO uint32_t SQR3;
205 __IO uint32_t JSQR;
206 __IO uint32_t JDR1;
207 __IO uint32_t JDR2;
208 __IO uint32_t JDR3;
209 __IO uint32_t JDR4;
210 __IO uint32_t DR;
211} ADC_TypeDef;
212
213typedef struct
214{
215 __IO uint32_t CSR;
216 __IO uint32_t CCR;
217 __IO uint32_t CDR;
219} ADC_Common_TypeDef;
220
221
226typedef struct
227{
228 __IO uint32_t TIR;
229 __IO uint32_t TDTR;
230 __IO uint32_t TDLR;
231 __IO uint32_t TDHR;
232} CAN_TxMailBox_TypeDef;
233
238typedef struct
239{
240 __IO uint32_t RIR;
241 __IO uint32_t RDTR;
242 __IO uint32_t RDLR;
243 __IO uint32_t RDHR;
244} CAN_FIFOMailBox_TypeDef;
245
250typedef struct
251{
252 __IO uint32_t FR1;
253 __IO uint32_t FR2;
254} CAN_FilterRegister_TypeDef;
255
260typedef struct
261{
262 __IO uint32_t MCR;
263 __IO uint32_t MSR;
264 __IO uint32_t TSR;
265 __IO uint32_t RF0R;
266 __IO uint32_t RF1R;
267 __IO uint32_t IER;
268 __IO uint32_t ESR;
269 __IO uint32_t BTR;
270 uint32_t RESERVED0[88];
271 CAN_TxMailBox_TypeDef sTxMailBox[3];
272 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
273 uint32_t RESERVED1[12];
274 __IO uint32_t FMR;
275 __IO uint32_t FM1R;
276 uint32_t RESERVED2;
277 __IO uint32_t FS1R;
278 uint32_t RESERVED3;
279 __IO uint32_t FFA1R;
280 uint32_t RESERVED4;
281 __IO uint32_t FA1R;
282 uint32_t RESERVED5[8];
283 CAN_FilterRegister_TypeDef sFilterRegister[28];
284} CAN_TypeDef;
285
290typedef struct
291{
292 __IO uint32_t CR;
293 __IO uint32_t CFGR;
294 __IO uint32_t TXDR;
295 __IO uint32_t RXDR;
296 __IO uint32_t ISR;
297 __IO uint32_t IER;
298}CEC_TypeDef;
299
304typedef struct
305{
306 __IO uint32_t DR;
307 __IO uint8_t IDR;
308 uint8_t RESERVED0;
309 uint16_t RESERVED1;
310 __IO uint32_t CR;
311 uint32_t RESERVED2;
312 __IO uint32_t INIT;
313 __IO uint32_t POL;
314} CRC_TypeDef;
315
320typedef struct
321{
322 __IO uint32_t CR;
323 __IO uint32_t SWTRIGR;
324 __IO uint32_t DHR12R1;
325 __IO uint32_t DHR12L1;
326 __IO uint32_t DHR8R1;
327 __IO uint32_t DHR12R2;
328 __IO uint32_t DHR12L2;
329 __IO uint32_t DHR8R2;
330 __IO uint32_t DHR12RD;
331 __IO uint32_t DHR12LD;
332 __IO uint32_t DHR8RD;
333 __IO uint32_t DOR1;
334 __IO uint32_t DOR2;
335 __IO uint32_t SR;
336} DAC_TypeDef;
337
338
343typedef struct
344{
345 __IO uint32_t IDCODE;
346 __IO uint32_t CR;
347 __IO uint32_t APB1FZ;
348 __IO uint32_t APB2FZ;
349}DBGMCU_TypeDef;
350
355typedef struct
356{
357 __IO uint32_t CR;
358 __IO uint32_t SR;
359 __IO uint32_t RISR;
360 __IO uint32_t IER;
361 __IO uint32_t MISR;
362 __IO uint32_t ICR;
363 __IO uint32_t ESCR;
364 __IO uint32_t ESUR;
365 __IO uint32_t CWSTRTR;
366 __IO uint32_t CWSIZER;
367 __IO uint32_t DR;
368} DCMI_TypeDef;
369
374typedef struct
375{
376 __IO uint32_t CR;
377 __IO uint32_t NDTR;
378 __IO uint32_t PAR;
379 __IO uint32_t M0AR;
380 __IO uint32_t M1AR;
381 __IO uint32_t FCR;
382} DMA_Stream_TypeDef;
383
384typedef struct
385{
386 __IO uint32_t LISR;
387 __IO uint32_t HISR;
388 __IO uint32_t LIFCR;
389 __IO uint32_t HIFCR;
390} DMA_TypeDef;
391
396typedef struct
397{
398 __IO uint32_t CR;
399 __IO uint32_t ISR;
400 __IO uint32_t IFCR;
401 __IO uint32_t FGMAR;
402 __IO uint32_t FGOR;
403 __IO uint32_t BGMAR;
404 __IO uint32_t BGOR;
405 __IO uint32_t FGPFCCR;
406 __IO uint32_t FGCOLR;
407 __IO uint32_t BGPFCCR;
408 __IO uint32_t BGCOLR;
409 __IO uint32_t FGCMAR;
410 __IO uint32_t BGCMAR;
411 __IO uint32_t OPFCCR;
412 __IO uint32_t OCOLR;
413 __IO uint32_t OMAR;
414 __IO uint32_t OOR;
415 __IO uint32_t NLR;
416 __IO uint32_t LWR;
417 __IO uint32_t AMTCR;
418 uint32_t RESERVED[236];
419 __IO uint32_t FGCLUT[256];
420 __IO uint32_t BGCLUT[256];
421} DMA2D_TypeDef;
422
423
428typedef struct
429{
430 __IO uint32_t MACCR;
431 __IO uint32_t MACFFR;
432 __IO uint32_t MACHTHR;
433 __IO uint32_t MACHTLR;
434 __IO uint32_t MACMIIAR;
435 __IO uint32_t MACMIIDR;
436 __IO uint32_t MACFCR;
437 __IO uint32_t MACVLANTR; /* 8 */
438 uint32_t RESERVED0[2];
439 __IO uint32_t MACRWUFFR; /* 11 */
440 __IO uint32_t MACPMTCSR;
441 uint32_t RESERVED1;
442 __IO uint32_t MACDBGR;
443 __IO uint32_t MACSR; /* 15 */
444 __IO uint32_t MACIMR;
445 __IO uint32_t MACA0HR;
446 __IO uint32_t MACA0LR;
447 __IO uint32_t MACA1HR;
448 __IO uint32_t MACA1LR;
449 __IO uint32_t MACA2HR;
450 __IO uint32_t MACA2LR;
451 __IO uint32_t MACA3HR;
452 __IO uint32_t MACA3LR; /* 24 */
453 uint32_t RESERVED2[40];
454 __IO uint32_t MMCCR; /* 65 */
455 __IO uint32_t MMCRIR;
456 __IO uint32_t MMCTIR;
457 __IO uint32_t MMCRIMR;
458 __IO uint32_t MMCTIMR; /* 69 */
459 uint32_t RESERVED3[14];
460 __IO uint32_t MMCTGFSCCR; /* 84 */
461 __IO uint32_t MMCTGFMSCCR;
462 uint32_t RESERVED4[5];
463 __IO uint32_t MMCTGFCR;
464 uint32_t RESERVED5[10];
465 __IO uint32_t MMCRFCECR;
466 __IO uint32_t MMCRFAECR;
467 uint32_t RESERVED6[10];
468 __IO uint32_t MMCRGUFCR;
469 uint32_t RESERVED7[334];
470 __IO uint32_t PTPTSCR;
471 __IO uint32_t PTPSSIR;
472 __IO uint32_t PTPTSHR;
473 __IO uint32_t PTPTSLR;
474 __IO uint32_t PTPTSHUR;
475 __IO uint32_t PTPTSLUR;
476 __IO uint32_t PTPTSAR;
477 __IO uint32_t PTPTTHR;
478 __IO uint32_t PTPTTLR;
479 __IO uint32_t RESERVED8;
480 __IO uint32_t PTPTSSR;
481 __IO uint32_t PTPPPSCR;
482 uint32_t RESERVED9[564];
483 __IO uint32_t DMABMR;
484 __IO uint32_t DMATPDR;
485 __IO uint32_t DMARPDR;
486 __IO uint32_t DMARDLAR;
487 __IO uint32_t DMATDLAR;
488 __IO uint32_t DMASR;
489 __IO uint32_t DMAOMR;
490 __IO uint32_t DMAIER;
491 __IO uint32_t DMAMFBOCR;
492 __IO uint32_t DMARSWTR;
493 uint32_t RESERVED10[8];
494 __IO uint32_t DMACHTDR;
495 __IO uint32_t DMACHRDR;
496 __IO uint32_t DMACHTBAR;
497 __IO uint32_t DMACHRBAR;
498} ETH_TypeDef;
499
504typedef struct
505{
506 __IO uint32_t IMR;
507 __IO uint32_t EMR;
508 __IO uint32_t RTSR;
509 __IO uint32_t FTSR;
510 __IO uint32_t SWIER;
511 __IO uint32_t PR;
512} EXTI_TypeDef;
513
518typedef struct
519{
520 __IO uint32_t ACR;
521 __IO uint32_t KEYR;
522 __IO uint32_t OPTKEYR;
523 __IO uint32_t SR;
524 __IO uint32_t CR;
525 __IO uint32_t OPTCR;
526 __IO uint32_t OPTCR1;
527} FLASH_TypeDef;
528
529
530
535typedef struct
536{
537 __IO uint32_t BTCR[8];
538} FMC_Bank1_TypeDef;
539
544typedef struct
545{
546 __IO uint32_t BWTR[7];
547} FMC_Bank1E_TypeDef;
548
553typedef struct
554{
555 __IO uint32_t PCR;
556 __IO uint32_t SR;
557 __IO uint32_t PMEM;
558 __IO uint32_t PATT;
559 uint32_t RESERVED0;
560 __IO uint32_t ECCR;
561} FMC_Bank3_TypeDef;
562
567typedef struct
568{
569 __IO uint32_t SDCR[2];
570 __IO uint32_t SDTR[2];
571 __IO uint32_t SDCMR;
572 __IO uint32_t SDRTR;
573 __IO uint32_t SDSR;
574} FMC_Bank5_6_TypeDef;
575
576
581typedef struct
582{
583 __IO uint32_t MODER;
584 __IO uint32_t OTYPER;
585 __IO uint32_t OSPEEDR;
586 __IO uint32_t PUPDR;
587 __IO uint32_t IDR;
588 __IO uint32_t ODR;
589 __IO uint32_t BSRR;
590 __IO uint32_t LCKR;
591 __IO uint32_t AFR[2];
592} GPIO_TypeDef;
593
598typedef struct
599{
600 __IO uint32_t MEMRMP;
601 __IO uint32_t PMC;
602 __IO uint32_t EXTICR[4];
603 uint32_t RESERVED[2];
604 __IO uint32_t CMPCR;
605} SYSCFG_TypeDef;
606
611typedef struct
612{
613 __IO uint32_t CR1;
614 __IO uint32_t CR2;
615 __IO uint32_t OAR1;
616 __IO uint32_t OAR2;
617 __IO uint32_t TIMINGR;
618 __IO uint32_t TIMEOUTR;
619 __IO uint32_t ISR;
620 __IO uint32_t ICR;
621 __IO uint32_t PECR;
622 __IO uint32_t RXDR;
623 __IO uint32_t TXDR;
624} I2C_TypeDef;
625
630typedef struct
631{
632 __IO uint32_t KR;
633 __IO uint32_t PR;
634 __IO uint32_t RLR;
635 __IO uint32_t SR;
636 __IO uint32_t WINR;
637} IWDG_TypeDef;
638
639
644typedef struct
645{
646 uint32_t RESERVED0[2];
647 __IO uint32_t SSCR;
648 __IO uint32_t BPCR;
649 __IO uint32_t AWCR;
650 __IO uint32_t TWCR;
651 __IO uint32_t GCR;
652 uint32_t RESERVED1[2];
653 __IO uint32_t SRCR;
654 uint32_t RESERVED2[1];
655 __IO uint32_t BCCR;
656 uint32_t RESERVED3[1];
657 __IO uint32_t IER;
658 __IO uint32_t ISR;
659 __IO uint32_t ICR;
660 __IO uint32_t LIPCR;
661 __IO uint32_t CPSR;
662 __IO uint32_t CDSR;
663} LTDC_TypeDef;
664
669typedef struct
670{
671 __IO uint32_t CR;
672 __IO uint32_t WHPCR;
673 __IO uint32_t WVPCR;
674 __IO uint32_t CKCR;
675 __IO uint32_t PFCR;
676 __IO uint32_t CACR;
677 __IO uint32_t DCCR;
678 __IO uint32_t BFCR;
679 uint32_t RESERVED0[2];
680 __IO uint32_t CFBAR;
681 __IO uint32_t CFBLR;
682 __IO uint32_t CFBLNR;
683 uint32_t RESERVED1[3];
684 __IO uint32_t CLUTWR;
686} LTDC_Layer_TypeDef;
687
692typedef struct
693{
694 __IO uint32_t CR1;
695 __IO uint32_t CSR1;
696 __IO uint32_t CR2;
697 __IO uint32_t CSR2;
698} PWR_TypeDef;
699
700
705typedef struct
706{
707 __IO uint32_t CR;
708 __IO uint32_t PLLCFGR;
709 __IO uint32_t CFGR;
710 __IO uint32_t CIR;
711 __IO uint32_t AHB1RSTR;
712 __IO uint32_t AHB2RSTR;
713 __IO uint32_t AHB3RSTR;
714 uint32_t RESERVED0;
715 __IO uint32_t APB1RSTR;
716 __IO uint32_t APB2RSTR;
717 uint32_t RESERVED1[2];
718 __IO uint32_t AHB1ENR;
719 __IO uint32_t AHB2ENR;
720 __IO uint32_t AHB3ENR;
721 uint32_t RESERVED2;
722 __IO uint32_t APB1ENR;
723 __IO uint32_t APB2ENR;
724 uint32_t RESERVED3[2];
725 __IO uint32_t AHB1LPENR;
726 __IO uint32_t AHB2LPENR;
727 __IO uint32_t AHB3LPENR;
728 uint32_t RESERVED4;
729 __IO uint32_t APB1LPENR;
730 __IO uint32_t APB2LPENR;
731 uint32_t RESERVED5[2];
732 __IO uint32_t BDCR;
733 __IO uint32_t CSR;
734 uint32_t RESERVED6[2];
735 __IO uint32_t SSCGR;
736 __IO uint32_t PLLI2SCFGR;
737 __IO uint32_t PLLSAICFGR;
738 __IO uint32_t DCKCFGR1;
739 __IO uint32_t DCKCFGR2;
741} RCC_TypeDef;
742
747typedef struct
748{
749 __IO uint32_t TR;
750 __IO uint32_t DR;
751 __IO uint32_t CR;
752 __IO uint32_t ISR;
753 __IO uint32_t PRER;
754 __IO uint32_t WUTR;
755 uint32_t reserved;
756 __IO uint32_t ALRMAR;
757 __IO uint32_t ALRMBR;
758 __IO uint32_t WPR;
759 __IO uint32_t SSR;
760 __IO uint32_t SHIFTR;
761 __IO uint32_t TSTR;
762 __IO uint32_t TSDR;
763 __IO uint32_t TSSSR;
764 __IO uint32_t CALR;
765 __IO uint32_t TAMPCR;
766 __IO uint32_t ALRMASSR;
767 __IO uint32_t ALRMBSSR;
768 __IO uint32_t OR;
769 __IO uint32_t BKP0R;
770 __IO uint32_t BKP1R;
771 __IO uint32_t BKP2R;
772 __IO uint32_t BKP3R;
773 __IO uint32_t BKP4R;
774 __IO uint32_t BKP5R;
775 __IO uint32_t BKP6R;
776 __IO uint32_t BKP7R;
777 __IO uint32_t BKP8R;
778 __IO uint32_t BKP9R;
779 __IO uint32_t BKP10R;
780 __IO uint32_t BKP11R;
781 __IO uint32_t BKP12R;
782 __IO uint32_t BKP13R;
783 __IO uint32_t BKP14R;
784 __IO uint32_t BKP15R;
785 __IO uint32_t BKP16R;
786 __IO uint32_t BKP17R;
787 __IO uint32_t BKP18R;
788 __IO uint32_t BKP19R;
789 __IO uint32_t BKP20R;
790 __IO uint32_t BKP21R;
791 __IO uint32_t BKP22R;
792 __IO uint32_t BKP23R;
793 __IO uint32_t BKP24R;
794 __IO uint32_t BKP25R;
795 __IO uint32_t BKP26R;
796 __IO uint32_t BKP27R;
797 __IO uint32_t BKP28R;
798 __IO uint32_t BKP29R;
799 __IO uint32_t BKP30R;
800 __IO uint32_t BKP31R;
801} RTC_TypeDef;
802
803
808typedef struct
809{
810 __IO uint32_t GCR;
811} SAI_TypeDef;
812
813typedef struct
814{
815 __IO uint32_t CR1;
816 __IO uint32_t CR2;
817 __IO uint32_t FRCR;
818 __IO uint32_t SLOTR;
819 __IO uint32_t IMR;
820 __IO uint32_t SR;
821 __IO uint32_t CLRFR;
822 __IO uint32_t DR;
823} SAI_Block_TypeDef;
824
829typedef struct
830{
831 __IO uint32_t CR;
832 __IO uint32_t IMR;
833 __IO uint32_t SR;
834 __IO uint32_t IFCR;
835 __IO uint32_t DR;
836 __IO uint32_t CSR;
837 __IO uint32_t DIR;
838} SPDIFRX_TypeDef;
839
844typedef struct
845{
846 __IO uint32_t POWER;
847 __IO uint32_t CLKCR;
848 __IO uint32_t ARG;
849 __IO uint32_t CMD;
850 __I uint32_t RESPCMD;
851 __I uint32_t RESP1;
852 __I uint32_t RESP2;
853 __I uint32_t RESP3;
854 __I uint32_t RESP4;
855 __IO uint32_t DTIMER;
856 __IO uint32_t DLEN;
857 __IO uint32_t DCTRL;
858 __I uint32_t DCOUNT;
859 __I uint32_t STA;
860 __IO uint32_t ICR;
861 __IO uint32_t MASK;
862 uint32_t RESERVED0[2];
863 __I uint32_t FIFOCNT;
864 uint32_t RESERVED1[13];
865 __IO uint32_t FIFO;
866} SDMMC_TypeDef;
867
872typedef struct
873{
874 __IO uint32_t CR1;
875 __IO uint32_t CR2;
876 __IO uint32_t SR;
877 __IO uint32_t DR;
878 __IO uint32_t CRCPR;
879 __IO uint32_t RXCRCR;
880 __IO uint32_t TXCRCR;
881 __IO uint32_t I2SCFGR;
882 __IO uint32_t I2SPR;
883} SPI_TypeDef;
884
889typedef struct
890{
891 __IO uint32_t CR;
892 __IO uint32_t DCR;
893 __IO uint32_t SR;
894 __IO uint32_t FCR;
895 __IO uint32_t DLR;
896 __IO uint32_t CCR;
897 __IO uint32_t AR;
898 __IO uint32_t ABR;
899 __IO uint32_t DR;
900 __IO uint32_t PSMKR;
901 __IO uint32_t PSMAR;
902 __IO uint32_t PIR;
903 __IO uint32_t LPTR;
904} QUADSPI_TypeDef;
905
910typedef struct
911{
912 __IO uint32_t CR1;
913 __IO uint32_t CR2;
914 __IO uint32_t SMCR;
915 __IO uint32_t DIER;
916 __IO uint32_t SR;
917 __IO uint32_t EGR;
918 __IO uint32_t CCMR1;
919 __IO uint32_t CCMR2;
920 __IO uint32_t CCER;
921 __IO uint32_t CNT;
922 __IO uint32_t PSC;
923 __IO uint32_t ARR;
924 __IO uint32_t RCR;
925 __IO uint32_t CCR1;
926 __IO uint32_t CCR2;
927 __IO uint32_t CCR3;
928 __IO uint32_t CCR4;
929 __IO uint32_t BDTR;
930 __IO uint32_t DCR;
931 __IO uint32_t DMAR;
932 __IO uint32_t OR;
933 __IO uint32_t CCMR3;
934 __IO uint32_t CCR5;
935 __IO uint32_t CCR6;
937} TIM_TypeDef;
938
942typedef struct
943{
944 __IO uint32_t ISR;
945 __IO uint32_t ICR;
946 __IO uint32_t IER;
947 __IO uint32_t CFGR;
948 __IO uint32_t CR;
949 __IO uint32_t CMP;
950 __IO uint32_t ARR;
951 __IO uint32_t CNT;
952} LPTIM_TypeDef;
953
954
959typedef struct
960{
961 __IO uint32_t CR1;
962 __IO uint32_t CR2;
963 __IO uint32_t CR3;
964 __IO uint32_t BRR;
965 __IO uint32_t GTPR;
966 __IO uint32_t RTOR;
967 __IO uint32_t RQR;
968 __IO uint32_t ISR;
969 __IO uint32_t ICR;
970 __IO uint32_t RDR;
971 __IO uint32_t TDR;
972} USART_TypeDef;
973
974
979typedef struct
980{
981 __IO uint32_t CR;
982 __IO uint32_t CFR;
983 __IO uint32_t SR;
984} WWDG_TypeDef;
985
990typedef struct
991{
992 __IO uint32_t CR;
993 __IO uint32_t SR;
994 __IO uint32_t DIN;
995 __IO uint32_t DOUT;
996 __IO uint32_t DMACR;
997 __IO uint32_t IMSCR;
998 __IO uint32_t RISR;
999 __IO uint32_t MISR;
1000 __IO uint32_t K0LR;
1001 __IO uint32_t K0RR;
1002 __IO uint32_t K1LR;
1003 __IO uint32_t K1RR;
1004 __IO uint32_t K2LR;
1005 __IO uint32_t K2RR;
1006 __IO uint32_t K3LR;
1007 __IO uint32_t K3RR;
1008 __IO uint32_t IV0LR;
1009 __IO uint32_t IV0RR;
1010 __IO uint32_t IV1LR;
1011 __IO uint32_t IV1RR;
1012 __IO uint32_t CSGCMCCM0R;
1013 __IO uint32_t CSGCMCCM1R;
1014 __IO uint32_t CSGCMCCM2R;
1015 __IO uint32_t CSGCMCCM3R;
1016 __IO uint32_t CSGCMCCM4R;
1017 __IO uint32_t CSGCMCCM5R;
1018 __IO uint32_t CSGCMCCM6R;
1019 __IO uint32_t CSGCMCCM7R;
1020 __IO uint32_t CSGCM0R;
1021 __IO uint32_t CSGCM1R;
1022 __IO uint32_t CSGCM2R;
1023 __IO uint32_t CSGCM3R;
1024 __IO uint32_t CSGCM4R;
1025 __IO uint32_t CSGCM5R;
1026 __IO uint32_t CSGCM6R;
1027 __IO uint32_t CSGCM7R;
1028} CRYP_TypeDef;
1029
1034typedef struct
1035{
1036 __IO uint32_t CR;
1037 __IO uint32_t DIN;
1038 __IO uint32_t STR;
1039 __IO uint32_t HR[5];
1040 __IO uint32_t IMR;
1041 __IO uint32_t SR;
1042 uint32_t RESERVED[52];
1043 __IO uint32_t CSR[54];
1044} HASH_TypeDef;
1045
1050typedef struct
1051{
1052 __IO uint32_t HR[8];
1053} HASH_DIGEST_TypeDef;
1054
1059typedef struct
1060{
1061 __IO uint32_t CR;
1062 __IO uint32_t SR;
1063 __IO uint32_t DR;
1064} RNG_TypeDef;
1065
1073typedef struct
1074{
1075 __IO uint32_t GOTGCTL;
1076 __IO uint32_t GOTGINT;
1077 __IO uint32_t GAHBCFG;
1078 __IO uint32_t GUSBCFG;
1079 __IO uint32_t GRSTCTL;
1080 __IO uint32_t GINTSTS;
1081 __IO uint32_t GINTMSK;
1082 __IO uint32_t GRXSTSR;
1083 __IO uint32_t GRXSTSP;
1084 __IO uint32_t GRXFSIZ;
1085 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1086 __IO uint32_t HNPTXSTS;
1087 uint32_t Reserved30[2];
1088 __IO uint32_t GCCFG;
1089 __IO uint32_t CID;
1090 uint32_t Reserved5[3];
1091 __IO uint32_t GHWCFG3;
1092 uint32_t Reserved6;
1093 __IO uint32_t GLPMCFG;
1094 uint32_t Reserved7;
1095 __IO uint32_t GDFIFOCFG;
1096 uint32_t Reserved43[40];
1097 __IO uint32_t HPTXFSIZ;
1098 __IO uint32_t DIEPTXF[0x0F];
1099} USB_OTG_GlobalTypeDef;
1100
1101
1105typedef struct
1106{
1107 __IO uint32_t DCFG;
1108 __IO uint32_t DCTL;
1109 __IO uint32_t DSTS;
1110 uint32_t Reserved0C;
1111 __IO uint32_t DIEPMSK;
1112 __IO uint32_t DOEPMSK;
1113 __IO uint32_t DAINT;
1114 __IO uint32_t DAINTMSK;
1115 uint32_t Reserved20;
1116 uint32_t Reserved9;
1117 __IO uint32_t DVBUSDIS;
1118 __IO uint32_t DVBUSPULSE;
1119 __IO uint32_t DTHRCTL;
1120 __IO uint32_t DIEPEMPMSK;
1121 __IO uint32_t DEACHINT;
1122 __IO uint32_t DEACHMSK;
1123 uint32_t Reserved40;
1124 __IO uint32_t DINEP1MSK;
1125 uint32_t Reserved44[15];
1126 __IO uint32_t DOUTEP1MSK;
1127} USB_OTG_DeviceTypeDef;
1128
1129
1133typedef struct
1134{
1135 __IO uint32_t DIEPCTL;
1136 uint32_t Reserved04;
1137 __IO uint32_t DIEPINT;
1138 uint32_t Reserved0C;
1139 __IO uint32_t DIEPTSIZ;
1140 __IO uint32_t DIEPDMA;
1141 __IO uint32_t DTXFSTS;
1142 uint32_t Reserved18;
1143} USB_OTG_INEndpointTypeDef;
1144
1145
1149typedef struct
1150{
1151 __IO uint32_t DOEPCTL;
1152 uint32_t Reserved04;
1153 __IO uint32_t DOEPINT;
1154 uint32_t Reserved0C;
1155 __IO uint32_t DOEPTSIZ;
1156 __IO uint32_t DOEPDMA;
1157 uint32_t Reserved18[2];
1158} USB_OTG_OUTEndpointTypeDef;
1159
1160
1164typedef struct
1165{
1166 __IO uint32_t HCFG;
1167 __IO uint32_t HFIR;
1168 __IO uint32_t HFNUM;
1169 uint32_t Reserved40C;
1170 __IO uint32_t HPTXSTS;
1171 __IO uint32_t HAINT;
1172 __IO uint32_t HAINTMSK;
1173} USB_OTG_HostTypeDef;
1174
1178typedef struct
1179{
1180 __IO uint32_t HCCHAR;
1181 __IO uint32_t HCSPLT;
1182 __IO uint32_t HCINT;
1183 __IO uint32_t HCINTMSK;
1184 __IO uint32_t HCTSIZ;
1185 __IO uint32_t HCDMA;
1186 uint32_t Reserved[2];
1187} USB_OTG_HostChannelTypeDef;
1198#define RAMITCM_BASE 0x00000000UL
1199#define FLASHITCM_BASE 0x00200000UL
1200#define FLASHAXI_BASE 0x08000000UL
1201#define RAMDTCM_BASE 0x20000000UL
1202#define PERIPH_BASE 0x40000000UL
1203#define BKPSRAM_BASE 0x40024000UL
1204#define QSPI_BASE 0x90000000UL
1205#define FMC_R_BASE 0xA0000000UL
1206#define QSPI_R_BASE 0xA0001000UL
1207#define SRAM1_BASE 0x20010000UL
1208#define SRAM2_BASE 0x2004C000UL
1209#define FLASH_END 0x080FFFFFUL
1210#define FLASH_OTP_BASE 0x1FF0F000UL
1211#define FLASH_OTP_END 0x1FF0F41FUL
1213/* Legacy define */
1214#define FLASH_BASE FLASHAXI_BASE
1215
1217#define APB1PERIPH_BASE PERIPH_BASE
1218#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1219#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1220#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
1221
1223#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1224#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1225#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1226#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1227#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1228#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1229#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
1230#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
1231#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
1232#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
1233#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1234#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1235#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1236#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1237#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1238#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL)
1239#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1240#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1241#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1242#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1243#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1244#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1245#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
1246#define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL)
1247#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1248#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1249#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL)
1250#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1251#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1252#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
1253#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
1254
1256#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
1257#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
1258#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
1259#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
1260#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
1261#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
1262#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
1263#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)
1264#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)
1265#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1266#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
1267#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
1268#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
1269#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
1270#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
1271#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
1272#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
1273#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
1274#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
1275#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)
1276#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
1277#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
1278#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
1279#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
1280#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
1281#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL)
1282#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL)
1284#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
1285#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1286#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1287#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1288#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1289#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1290#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1291#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1292#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
1293#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
1294#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
1295#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1296#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1297#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1298#define UID_BASE 0x1FF0F420UL
1299#define FLASHSIZE_BASE 0x1FF0F442UL
1300#define PACKAGE_BASE 0x1FF0F7E0UL
1301/* Legacy define */
1302#define PACKAGESIZE_BASE PACKAGE_BASE
1303
1304#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1305#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1306#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1307#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1308#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1309#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1310#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1311#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1312#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1313#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1314#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1315#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1316#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1317#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1318#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1319#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1320#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1321#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1322#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
1323#define ETH_MAC_BASE (ETH_BASE)
1324#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
1325#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
1326#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
1327#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
1329#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1330#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000UL)
1331#define HASH_BASE (AHB2PERIPH_BASE + 0x60400UL)
1332#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710UL)
1333#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1335#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1336#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1337#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1338#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
1339
1340/* Debug MCU registers base address */
1341#define DBGMCU_BASE 0xE0042000UL
1342
1344#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1345#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1346
1347#define USB_OTG_GLOBAL_BASE 0x0000UL
1348#define USB_OTG_DEVICE_BASE 0x0800UL
1349#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL
1350#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL
1351#define USB_OTG_EP_REG_SIZE 0x0020UL
1352#define USB_OTG_HOST_BASE 0x0400UL
1353#define USB_OTG_HOST_PORT_BASE 0x0440UL
1354#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL
1355#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL
1356#define USB_OTG_PCGCCTL_BASE 0x0E00UL
1357#define USB_OTG_FIFO_BASE 0x1000UL
1358#define USB_OTG_FIFO_SIZE 0x1000UL
1359
1367#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1368#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1369#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1370#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1371#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1372#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1373#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1374#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1375#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1376#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1377#define RTC ((RTC_TypeDef *) RTC_BASE)
1378#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1379#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1380#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1381#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1382#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1383#define USART2 ((USART_TypeDef *) USART2_BASE)
1384#define USART3 ((USART_TypeDef *) USART3_BASE)
1385#define UART4 ((USART_TypeDef *) UART4_BASE)
1386#define UART5 ((USART_TypeDef *) UART5_BASE)
1387#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1388#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1389#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1390#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1391#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1392#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1393#define CEC ((CEC_TypeDef *) CEC_BASE)
1394#define PWR ((PWR_TypeDef *) PWR_BASE)
1395#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1396#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1397#define UART7 ((USART_TypeDef *) UART7_BASE)
1398#define UART8 ((USART_TypeDef *) UART8_BASE)
1399#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1400#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1401#define USART1 ((USART_TypeDef *) USART1_BASE)
1402#define USART6 ((USART_TypeDef *) USART6_BASE)
1403#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1404#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1405#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1406#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1407#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
1408#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1409#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1410#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1411#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1412#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1413#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1414#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1415#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1416#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1417#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1418#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1419#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1420#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1421#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1422#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1423#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1424#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1425#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1426#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1427#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1428#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1429#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1430#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1431#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1432#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1433#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1434#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1435#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1436#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1437#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1438#define CRC ((CRC_TypeDef *) CRC_BASE)
1439#define RCC ((RCC_TypeDef *) RCC_BASE)
1440#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1441#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1442#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1443#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1444#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1445#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1446#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1447#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1448#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1449#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1450#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1451#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1452#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1453#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1454#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1455#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1456#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1457#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1458#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1459#define ETH ((ETH_TypeDef *) ETH_BASE)
1460#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1461#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1462#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1463#define HASH ((HASH_TypeDef *) HASH_BASE)
1464#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1465#define RNG ((RNG_TypeDef *) RNG_BASE)
1466#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1467#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1468#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1469#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1470#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1471#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1472#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1473#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1474
1487/******************************************************************************/
1488/* Peripheral Registers_Bits_Definition */
1489/******************************************************************************/
1490
1491/******************************************************************************/
1492/* */
1493/* Analog to Digital Converter */
1494/* */
1495/******************************************************************************/
1496#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A))
1497#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF0F44C))
1498#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF0F44E))
1500/******************** Bit definition for ADC_SR register ********************/
1501#define ADC_SR_AWD_Pos (0U)
1502#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1503#define ADC_SR_AWD ADC_SR_AWD_Msk
1504#define ADC_SR_EOC_Pos (1U)
1505#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1506#define ADC_SR_EOC ADC_SR_EOC_Msk
1507#define ADC_SR_JEOC_Pos (2U)
1508#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1509#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1510#define ADC_SR_JSTRT_Pos (3U)
1511#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1512#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1513#define ADC_SR_STRT_Pos (4U)
1514#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1515#define ADC_SR_STRT ADC_SR_STRT_Msk
1516#define ADC_SR_OVR_Pos (5U)
1517#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1518#define ADC_SR_OVR ADC_SR_OVR_Msk
1520/******************* Bit definition for ADC_CR1 register ********************/
1521#define ADC_CR1_AWDCH_Pos (0U)
1522#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1523#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1524#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1525#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1526#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1527#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1528#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1529#define ADC_CR1_EOCIE_Pos (5U)
1530#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1531#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1532#define ADC_CR1_AWDIE_Pos (6U)
1533#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1534#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1535#define ADC_CR1_JEOCIE_Pos (7U)
1536#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1537#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1538#define ADC_CR1_SCAN_Pos (8U)
1539#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1540#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1541#define ADC_CR1_AWDSGL_Pos (9U)
1542#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1543#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1544#define ADC_CR1_JAUTO_Pos (10U)
1545#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1546#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1547#define ADC_CR1_DISCEN_Pos (11U)
1548#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1549#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1550#define ADC_CR1_JDISCEN_Pos (12U)
1551#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1552#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1553#define ADC_CR1_DISCNUM_Pos (13U)
1554#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1555#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1556#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1557#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1558#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1559#define ADC_CR1_JAWDEN_Pos (22U)
1560#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1561#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1562#define ADC_CR1_AWDEN_Pos (23U)
1563#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1564#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1565#define ADC_CR1_RES_Pos (24U)
1566#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1567#define ADC_CR1_RES ADC_CR1_RES_Msk
1568#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1569#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1570#define ADC_CR1_OVRIE_Pos (26U)
1571#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1572#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1574/******************* Bit definition for ADC_CR2 register ********************/
1575#define ADC_CR2_ADON_Pos (0U)
1576#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1577#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1578#define ADC_CR2_CONT_Pos (1U)
1579#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1580#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1581#define ADC_CR2_DMA_Pos (8U)
1582#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1583#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1584#define ADC_CR2_DDS_Pos (9U)
1585#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1586#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1587#define ADC_CR2_EOCS_Pos (10U)
1588#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1589#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1590#define ADC_CR2_ALIGN_Pos (11U)
1591#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1592#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1593#define ADC_CR2_JEXTSEL_Pos (16U)
1594#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1595#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1596#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1597#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1598#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1599#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1600#define ADC_CR2_JEXTEN_Pos (20U)
1601#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1602#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1603#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1604#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1605#define ADC_CR2_JSWSTART_Pos (22U)
1606#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1607#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1608#define ADC_CR2_EXTSEL_Pos (24U)
1609#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1610#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1611#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1612#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1613#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1614#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1615#define ADC_CR2_EXTEN_Pos (28U)
1616#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1617#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1618#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1619#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1620#define ADC_CR2_SWSTART_Pos (30U)
1621#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1622#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1624/****************** Bit definition for ADC_SMPR1 register *******************/
1625#define ADC_SMPR1_SMP10_Pos (0U)
1626#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1627#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1628#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1629#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1630#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1631#define ADC_SMPR1_SMP11_Pos (3U)
1632#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1633#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1634#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1635#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1636#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1637#define ADC_SMPR1_SMP12_Pos (6U)
1638#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1639#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1640#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1641#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1642#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1643#define ADC_SMPR1_SMP13_Pos (9U)
1644#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1645#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1646#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1647#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1648#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1649#define ADC_SMPR1_SMP14_Pos (12U)
1650#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1651#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1652#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1653#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1654#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1655#define ADC_SMPR1_SMP15_Pos (15U)
1656#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1657#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1658#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1659#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1660#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1661#define ADC_SMPR1_SMP16_Pos (18U)
1662#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1663#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1664#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1665#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1666#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1667#define ADC_SMPR1_SMP17_Pos (21U)
1668#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1669#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1670#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1671#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1672#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1673#define ADC_SMPR1_SMP18_Pos (24U)
1674#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1675#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1676#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1677#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1678#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1680/****************** Bit definition for ADC_SMPR2 register *******************/
1681#define ADC_SMPR2_SMP0_Pos (0U)
1682#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1683#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1684#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1685#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1686#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1687#define ADC_SMPR2_SMP1_Pos (3U)
1688#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1689#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1690#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1691#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1692#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1693#define ADC_SMPR2_SMP2_Pos (6U)
1694#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1695#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1696#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1697#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1698#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1699#define ADC_SMPR2_SMP3_Pos (9U)
1700#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1701#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1702#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1703#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1704#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1705#define ADC_SMPR2_SMP4_Pos (12U)
1706#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1707#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1708#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1709#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1710#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1711#define ADC_SMPR2_SMP5_Pos (15U)
1712#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1713#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1714#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1715#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1716#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1717#define ADC_SMPR2_SMP6_Pos (18U)
1718#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1719#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1720#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1721#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1722#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1723#define ADC_SMPR2_SMP7_Pos (21U)
1724#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1725#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1726#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1727#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1728#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1729#define ADC_SMPR2_SMP8_Pos (24U)
1730#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1731#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1732#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1733#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1734#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1735#define ADC_SMPR2_SMP9_Pos (27U)
1736#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1737#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1738#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1739#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1740#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1742/****************** Bit definition for ADC_JOFR1 register *******************/
1743#define ADC_JOFR1_JOFFSET1_Pos (0U)
1744#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1745#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1747/****************** Bit definition for ADC_JOFR2 register *******************/
1748#define ADC_JOFR2_JOFFSET2_Pos (0U)
1749#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1750#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1752/****************** Bit definition for ADC_JOFR3 register *******************/
1753#define ADC_JOFR3_JOFFSET3_Pos (0U)
1754#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1755#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1757/****************** Bit definition for ADC_JOFR4 register *******************/
1758#define ADC_JOFR4_JOFFSET4_Pos (0U)
1759#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1760#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1762/******************* Bit definition for ADC_HTR register ********************/
1763#define ADC_HTR_HT_Pos (0U)
1764#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1765#define ADC_HTR_HT ADC_HTR_HT_Msk
1767/******************* Bit definition for ADC_LTR register ********************/
1768#define ADC_LTR_LT_Pos (0U)
1769#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1770#define ADC_LTR_LT ADC_LTR_LT_Msk
1772/******************* Bit definition for ADC_SQR1 register *******************/
1773#define ADC_SQR1_SQ13_Pos (0U)
1774#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1775#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1776#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1777#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1778#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1779#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1780#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1781#define ADC_SQR1_SQ14_Pos (5U)
1782#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1783#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1784#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1785#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1786#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1787#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1788#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1789#define ADC_SQR1_SQ15_Pos (10U)
1790#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1791#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1792#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1793#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1794#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1795#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1796#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1797#define ADC_SQR1_SQ16_Pos (15U)
1798#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1799#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1800#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1801#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1802#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1803#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1804#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1805#define ADC_SQR1_L_Pos (20U)
1806#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1807#define ADC_SQR1_L ADC_SQR1_L_Msk
1808#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1809#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1810#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1811#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1813/******************* Bit definition for ADC_SQR2 register *******************/
1814#define ADC_SQR2_SQ7_Pos (0U)
1815#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1816#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1817#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1818#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1819#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1820#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1821#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1822#define ADC_SQR2_SQ8_Pos (5U)
1823#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1824#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1825#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1826#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1827#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1828#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1829#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1830#define ADC_SQR2_SQ9_Pos (10U)
1831#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1832#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1833#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1834#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1835#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1836#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1837#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1838#define ADC_SQR2_SQ10_Pos (15U)
1839#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1840#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1841#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1842#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1843#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1844#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1845#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1846#define ADC_SQR2_SQ11_Pos (20U)
1847#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1848#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1849#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1850#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1851#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1852#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1853#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1854#define ADC_SQR2_SQ12_Pos (25U)
1855#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1856#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1857#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1858#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1859#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1860#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1861#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1863/******************* Bit definition for ADC_SQR3 register *******************/
1864#define ADC_SQR3_SQ1_Pos (0U)
1865#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1866#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1867#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1868#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1869#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1870#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1871#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1872#define ADC_SQR3_SQ2_Pos (5U)
1873#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1874#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1875#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1876#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1877#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1878#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1879#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1880#define ADC_SQR3_SQ3_Pos (10U)
1881#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1882#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1883#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1884#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1885#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1886#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1887#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1888#define ADC_SQR3_SQ4_Pos (15U)
1889#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1890#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1891#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1892#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1893#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1894#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1895#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1896#define ADC_SQR3_SQ5_Pos (20U)
1897#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1898#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1899#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1900#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1901#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1902#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1903#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1904#define ADC_SQR3_SQ6_Pos (25U)
1905#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1906#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1907#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1908#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1909#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1910#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1911#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1913/******************* Bit definition for ADC_JSQR register *******************/
1914#define ADC_JSQR_JSQ1_Pos (0U)
1915#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1916#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1917#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1918#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1919#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1920#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1921#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1922#define ADC_JSQR_JSQ2_Pos (5U)
1923#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1924#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1925#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1926#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1927#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1928#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1929#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1930#define ADC_JSQR_JSQ3_Pos (10U)
1931#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1932#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1933#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1934#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1935#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1936#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1937#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1938#define ADC_JSQR_JSQ4_Pos (15U)
1939#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1940#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1941#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1942#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1943#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1944#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1945#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1946#define ADC_JSQR_JL_Pos (20U)
1947#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1948#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1949#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1950#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1952/******************* Bit definition for ADC_JDR1 register *******************/
1953#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU)
1955/******************* Bit definition for ADC_JDR2 register *******************/
1956#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU)
1958/******************* Bit definition for ADC_JDR3 register *******************/
1959#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU)
1961/******************* Bit definition for ADC_JDR4 register *******************/
1962#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU)
1964/******************** Bit definition for ADC_DR register ********************/
1965#define ADC_DR_DATA_Pos (0U)
1966#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1967#define ADC_DR_DATA ADC_DR_DATA_Msk
1968#define ADC_DR_ADC2DATA_Pos (16U)
1969#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1970#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1972/******************* Bit definition for ADC_CSR register ********************/
1973#define ADC_CSR_AWD1_Pos (0U)
1974#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1975#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1976#define ADC_CSR_EOC1_Pos (1U)
1977#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1978#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1979#define ADC_CSR_JEOC1_Pos (2U)
1980#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1981#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1982#define ADC_CSR_JSTRT1_Pos (3U)
1983#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1984#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1985#define ADC_CSR_STRT1_Pos (4U)
1986#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1987#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1988#define ADC_CSR_OVR1_Pos (5U)
1989#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1990#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1991#define ADC_CSR_AWD2_Pos (8U)
1992#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1993#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1994#define ADC_CSR_EOC2_Pos (9U)
1995#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1996#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1997#define ADC_CSR_JEOC2_Pos (10U)
1998#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1999#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
2000#define ADC_CSR_JSTRT2_Pos (11U)
2001#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
2002#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
2003#define ADC_CSR_STRT2_Pos (12U)
2004#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
2005#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
2006#define ADC_CSR_OVR2_Pos (13U)
2007#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
2008#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
2009#define ADC_CSR_AWD3_Pos (16U)
2010#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
2011#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
2012#define ADC_CSR_EOC3_Pos (17U)
2013#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
2014#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
2015#define ADC_CSR_JEOC3_Pos (18U)
2016#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
2017#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
2018#define ADC_CSR_JSTRT3_Pos (19U)
2019#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
2020#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
2021#define ADC_CSR_STRT3_Pos (20U)
2022#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
2023#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
2024#define ADC_CSR_OVR3_Pos (21U)
2025#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
2026#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
2028/* Legacy defines */
2029#define ADC_CSR_DOVR1 ADC_CSR_OVR1
2030#define ADC_CSR_DOVR2 ADC_CSR_OVR2
2031#define ADC_CSR_DOVR3 ADC_CSR_OVR3
2032
2033
2034/******************* Bit definition for ADC_CCR register ********************/
2035#define ADC_CCR_MULTI_Pos (0U)
2036#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
2037#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
2038#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
2039#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
2040#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
2041#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
2042#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
2043#define ADC_CCR_DELAY_Pos (8U)
2044#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
2045#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
2046#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
2047#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
2048#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
2049#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
2050#define ADC_CCR_DDS_Pos (13U)
2051#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
2052#define ADC_CCR_DDS ADC_CCR_DDS_Msk
2053#define ADC_CCR_DMA_Pos (14U)
2054#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
2055#define ADC_CCR_DMA ADC_CCR_DMA_Msk
2056#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
2057#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
2058#define ADC_CCR_ADCPRE_Pos (16U)
2059#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
2060#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
2061#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
2062#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
2063#define ADC_CCR_VBATE_Pos (22U)
2064#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
2065#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
2066#define ADC_CCR_TSVREFE_Pos (23U)
2067#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
2068#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
2070/******************* Bit definition for ADC_CDR register ********************/
2071#define ADC_CDR_DATA1_Pos (0U)
2072#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
2073#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
2074#define ADC_CDR_DATA2_Pos (16U)
2075#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
2076#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
2078/* Legacy defines */
2079#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
2080#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
2081
2082/******************************************************************************/
2083/* */
2084/* Controller Area Network */
2085/* */
2086/******************************************************************************/
2088/******************* Bit definition for CAN_MCR register ********************/
2089#define CAN_MCR_INRQ_Pos (0U)
2090#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
2091#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
2092#define CAN_MCR_SLEEP_Pos (1U)
2093#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
2094#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
2095#define CAN_MCR_TXFP_Pos (2U)
2096#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
2097#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
2098#define CAN_MCR_RFLM_Pos (3U)
2099#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
2100#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
2101#define CAN_MCR_NART_Pos (4U)
2102#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
2103#define CAN_MCR_NART CAN_MCR_NART_Msk
2104#define CAN_MCR_AWUM_Pos (5U)
2105#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
2106#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
2107#define CAN_MCR_ABOM_Pos (6U)
2108#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
2109#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
2110#define CAN_MCR_TTCM_Pos (7U)
2111#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
2112#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
2113#define CAN_MCR_RESET_Pos (15U)
2114#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
2115#define CAN_MCR_RESET CAN_MCR_RESET_Msk
2117/******************* Bit definition for CAN_MSR register ********************/
2118#define CAN_MSR_INAK_Pos (0U)
2119#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
2120#define CAN_MSR_INAK CAN_MSR_INAK_Msk
2121#define CAN_MSR_SLAK_Pos (1U)
2122#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
2123#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
2124#define CAN_MSR_ERRI_Pos (2U)
2125#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
2126#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
2127#define CAN_MSR_WKUI_Pos (3U)
2128#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
2129#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
2130#define CAN_MSR_SLAKI_Pos (4U)
2131#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
2132#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
2133#define CAN_MSR_TXM_Pos (8U)
2134#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
2135#define CAN_MSR_TXM CAN_MSR_TXM_Msk
2136#define CAN_MSR_RXM_Pos (9U)
2137#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
2138#define CAN_MSR_RXM CAN_MSR_RXM_Msk
2139#define CAN_MSR_SAMP_Pos (10U)
2140#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
2141#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
2142#define CAN_MSR_RX_Pos (11U)
2143#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
2144#define CAN_MSR_RX CAN_MSR_RX_Msk
2146/******************* Bit definition for CAN_TSR register ********************/
2147#define CAN_TSR_RQCP0_Pos (0U)
2148#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
2149#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
2150#define CAN_TSR_TXOK0_Pos (1U)
2151#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
2152#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
2153#define CAN_TSR_ALST0_Pos (2U)
2154#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
2155#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
2156#define CAN_TSR_TERR0_Pos (3U)
2157#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
2158#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
2159#define CAN_TSR_ABRQ0_Pos (7U)
2160#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
2161#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
2162#define CAN_TSR_RQCP1_Pos (8U)
2163#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2164#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2165#define CAN_TSR_TXOK1_Pos (9U)
2166#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2167#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2168#define CAN_TSR_ALST1_Pos (10U)
2169#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2170#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2171#define CAN_TSR_TERR1_Pos (11U)
2172#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2173#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2174#define CAN_TSR_ABRQ1_Pos (15U)
2175#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2176#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2177#define CAN_TSR_RQCP2_Pos (16U)
2178#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2179#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2180#define CAN_TSR_TXOK2_Pos (17U)
2181#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2182#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2183#define CAN_TSR_ALST2_Pos (18U)
2184#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2185#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2186#define CAN_TSR_TERR2_Pos (19U)
2187#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2188#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2189#define CAN_TSR_ABRQ2_Pos (23U)
2190#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2191#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2192#define CAN_TSR_CODE_Pos (24U)
2193#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2194#define CAN_TSR_CODE CAN_TSR_CODE_Msk
2196#define CAN_TSR_TME_Pos (26U)
2197#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2198#define CAN_TSR_TME CAN_TSR_TME_Msk
2199#define CAN_TSR_TME0_Pos (26U)
2200#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2201#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2202#define CAN_TSR_TME1_Pos (27U)
2203#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2204#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2205#define CAN_TSR_TME2_Pos (28U)
2206#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2207#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2209#define CAN_TSR_LOW_Pos (29U)
2210#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2211#define CAN_TSR_LOW CAN_TSR_LOW_Msk
2212#define CAN_TSR_LOW0_Pos (29U)
2213#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2214#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2215#define CAN_TSR_LOW1_Pos (30U)
2216#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2217#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2218#define CAN_TSR_LOW2_Pos (31U)
2219#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2220#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2222/******************* Bit definition for CAN_RF0R register *******************/
2223#define CAN_RF0R_FMP0_Pos (0U)
2224#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2225#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2226#define CAN_RF0R_FULL0_Pos (3U)
2227#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2228#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2229#define CAN_RF0R_FOVR0_Pos (4U)
2230#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2231#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2232#define CAN_RF0R_RFOM0_Pos (5U)
2233#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2234#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2236/******************* Bit definition for CAN_RF1R register *******************/
2237#define CAN_RF1R_FMP1_Pos (0U)
2238#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2239#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2240#define CAN_RF1R_FULL1_Pos (3U)
2241#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2242#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2243#define CAN_RF1R_FOVR1_Pos (4U)
2244#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2245#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2246#define CAN_RF1R_RFOM1_Pos (5U)
2247#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2248#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2250/******************** Bit definition for CAN_IER register *******************/
2251#define CAN_IER_TMEIE_Pos (0U)
2252#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2253#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2254#define CAN_IER_FMPIE0_Pos (1U)
2255#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2256#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2257#define CAN_IER_FFIE0_Pos (2U)
2258#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2259#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2260#define CAN_IER_FOVIE0_Pos (3U)
2261#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2262#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2263#define CAN_IER_FMPIE1_Pos (4U)
2264#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2265#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2266#define CAN_IER_FFIE1_Pos (5U)
2267#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2268#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2269#define CAN_IER_FOVIE1_Pos (6U)
2270#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2271#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2272#define CAN_IER_EWGIE_Pos (8U)
2273#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2274#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2275#define CAN_IER_EPVIE_Pos (9U)
2276#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2277#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2278#define CAN_IER_BOFIE_Pos (10U)
2279#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2280#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2281#define CAN_IER_LECIE_Pos (11U)
2282#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2283#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2284#define CAN_IER_ERRIE_Pos (15U)
2285#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2286#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2287#define CAN_IER_WKUIE_Pos (16U)
2288#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2289#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2290#define CAN_IER_SLKIE_Pos (17U)
2291#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2292#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2294/******************** Bit definition for CAN_ESR register *******************/
2295#define CAN_ESR_EWGF_Pos (0U)
2296#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2297#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2298#define CAN_ESR_EPVF_Pos (1U)
2299#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2300#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2301#define CAN_ESR_BOFF_Pos (2U)
2302#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2303#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2305#define CAN_ESR_LEC_Pos (4U)
2306#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2307#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2308#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2309#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2310#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2312#define CAN_ESR_TEC_Pos (16U)
2313#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2314#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2315#define CAN_ESR_REC_Pos (24U)
2316#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2317#define CAN_ESR_REC CAN_ESR_REC_Msk
2319/******************* Bit definition for CAN_BTR register ********************/
2320#define CAN_BTR_BRP_Pos (0U)
2321#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2322#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2323#define CAN_BTR_TS1_Pos (16U)
2324#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2325#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2326#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2327#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2328#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2329#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2330#define CAN_BTR_TS2_Pos (20U)
2331#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2332#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2333#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2334#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2335#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2336#define CAN_BTR_SJW_Pos (24U)
2337#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2338#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2339#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2340#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2341#define CAN_BTR_LBKM_Pos (30U)
2342#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2343#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2344#define CAN_BTR_SILM_Pos (31U)
2345#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2346#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2349/****************** Bit definition for CAN_TI0R register ********************/
2350#define CAN_TI0R_TXRQ_Pos (0U)
2351#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2352#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2353#define CAN_TI0R_RTR_Pos (1U)
2354#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2355#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2356#define CAN_TI0R_IDE_Pos (2U)
2357#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2358#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2359#define CAN_TI0R_EXID_Pos (3U)
2360#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2361#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2362#define CAN_TI0R_STID_Pos (21U)
2363#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2364#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2366/****************** Bit definition for CAN_TDT0R register *******************/
2367#define CAN_TDT0R_DLC_Pos (0U)
2368#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2369#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2370#define CAN_TDT0R_TGT_Pos (8U)
2371#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2372#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2373#define CAN_TDT0R_TIME_Pos (16U)
2374#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2375#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2377/****************** Bit definition for CAN_TDL0R register *******************/
2378#define CAN_TDL0R_DATA0_Pos (0U)
2379#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2380#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2381#define CAN_TDL0R_DATA1_Pos (8U)
2382#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2383#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2384#define CAN_TDL0R_DATA2_Pos (16U)
2385#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2386#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2387#define CAN_TDL0R_DATA3_Pos (24U)
2388#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2389#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2391/****************** Bit definition for CAN_TDH0R register *******************/
2392#define CAN_TDH0R_DATA4_Pos (0U)
2393#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2394#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2395#define CAN_TDH0R_DATA5_Pos (8U)
2396#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2397#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2398#define CAN_TDH0R_DATA6_Pos (16U)
2399#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2400#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2401#define CAN_TDH0R_DATA7_Pos (24U)
2402#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2403#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2405/******************* Bit definition for CAN_TI1R register *******************/
2406#define CAN_TI1R_TXRQ_Pos (0U)
2407#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2408#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2409#define CAN_TI1R_RTR_Pos (1U)
2410#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2411#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2412#define CAN_TI1R_IDE_Pos (2U)
2413#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2414#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2415#define CAN_TI1R_EXID_Pos (3U)
2416#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2417#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2418#define CAN_TI1R_STID_Pos (21U)
2419#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2420#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2422/******************* Bit definition for CAN_TDT1R register ******************/
2423#define CAN_TDT1R_DLC_Pos (0U)
2424#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2425#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2426#define CAN_TDT1R_TGT_Pos (8U)
2427#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2428#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2429#define CAN_TDT1R_TIME_Pos (16U)
2430#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2431#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2433/******************* Bit definition for CAN_TDL1R register ******************/
2434#define CAN_TDL1R_DATA0_Pos (0U)
2435#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2436#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2437#define CAN_TDL1R_DATA1_Pos (8U)
2438#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2439#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2440#define CAN_TDL1R_DATA2_Pos (16U)
2441#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2442#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2443#define CAN_TDL1R_DATA3_Pos (24U)
2444#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2445#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2447/******************* Bit definition for CAN_TDH1R register ******************/
2448#define CAN_TDH1R_DATA4_Pos (0U)
2449#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2450#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2451#define CAN_TDH1R_DATA5_Pos (8U)
2452#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2453#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2454#define CAN_TDH1R_DATA6_Pos (16U)
2455#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2456#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2457#define CAN_TDH1R_DATA7_Pos (24U)
2458#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2459#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2461/******************* Bit definition for CAN_TI2R register *******************/
2462#define CAN_TI2R_TXRQ_Pos (0U)
2463#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2464#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2465#define CAN_TI2R_RTR_Pos (1U)
2466#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2467#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2468#define CAN_TI2R_IDE_Pos (2U)
2469#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2470#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2471#define CAN_TI2R_EXID_Pos (3U)
2472#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2473#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2474#define CAN_TI2R_STID_Pos (21U)
2475#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2476#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2478/******************* Bit definition for CAN_TDT2R register ******************/
2479#define CAN_TDT2R_DLC_Pos (0U)
2480#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2481#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2482#define CAN_TDT2R_TGT_Pos (8U)
2483#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2484#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2485#define CAN_TDT2R_TIME_Pos (16U)
2486#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2487#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2489/******************* Bit definition for CAN_TDL2R register ******************/
2490#define CAN_TDL2R_DATA0_Pos (0U)
2491#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2492#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2493#define CAN_TDL2R_DATA1_Pos (8U)
2494#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2495#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2496#define CAN_TDL2R_DATA2_Pos (16U)
2497#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2498#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2499#define CAN_TDL2R_DATA3_Pos (24U)
2500#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2501#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2503/******************* Bit definition for CAN_TDH2R register ******************/
2504#define CAN_TDH2R_DATA4_Pos (0U)
2505#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2506#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2507#define CAN_TDH2R_DATA5_Pos (8U)
2508#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2509#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2510#define CAN_TDH2R_DATA6_Pos (16U)
2511#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2512#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2513#define CAN_TDH2R_DATA7_Pos (24U)
2514#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2515#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2517/******************* Bit definition for CAN_RI0R register *******************/
2518#define CAN_RI0R_RTR_Pos (1U)
2519#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2520#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2521#define CAN_RI0R_IDE_Pos (2U)
2522#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2523#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2524#define CAN_RI0R_EXID_Pos (3U)
2525#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2526#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2527#define CAN_RI0R_STID_Pos (21U)
2528#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2529#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2531/******************* Bit definition for CAN_RDT0R register ******************/
2532#define CAN_RDT0R_DLC_Pos (0U)
2533#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2534#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2535#define CAN_RDT0R_FMI_Pos (8U)
2536#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2537#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2538#define CAN_RDT0R_TIME_Pos (16U)
2539#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2540#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2542/******************* Bit definition for CAN_RDL0R register ******************/
2543#define CAN_RDL0R_DATA0_Pos (0U)
2544#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2545#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2546#define CAN_RDL0R_DATA1_Pos (8U)
2547#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2548#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2549#define CAN_RDL0R_DATA2_Pos (16U)
2550#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2551#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2552#define CAN_RDL0R_DATA3_Pos (24U)
2553#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2554#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2556/******************* Bit definition for CAN_RDH0R register ******************/
2557#define CAN_RDH0R_DATA4_Pos (0U)
2558#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2559#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2560#define CAN_RDH0R_DATA5_Pos (8U)
2561#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2562#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2563#define CAN_RDH0R_DATA6_Pos (16U)
2564#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2565#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2566#define CAN_RDH0R_DATA7_Pos (24U)
2567#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2568#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2570/******************* Bit definition for CAN_RI1R register *******************/
2571#define CAN_RI1R_RTR_Pos (1U)
2572#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2573#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2574#define CAN_RI1R_IDE_Pos (2U)
2575#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2576#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2577#define CAN_RI1R_EXID_Pos (3U)
2578#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2579#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2580#define CAN_RI1R_STID_Pos (21U)
2581#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2582#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2584/******************* Bit definition for CAN_RDT1R register ******************/
2585#define CAN_RDT1R_DLC_Pos (0U)
2586#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2587#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2588#define CAN_RDT1R_FMI_Pos (8U)
2589#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2590#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2591#define CAN_RDT1R_TIME_Pos (16U)
2592#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2593#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2595/******************* Bit definition for CAN_RDL1R register ******************/
2596#define CAN_RDL1R_DATA0_Pos (0U)
2597#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2598#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2599#define CAN_RDL1R_DATA1_Pos (8U)
2600#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2601#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2602#define CAN_RDL1R_DATA2_Pos (16U)
2603#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2604#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2605#define CAN_RDL1R_DATA3_Pos (24U)
2606#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2607#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2609/******************* Bit definition for CAN_RDH1R register ******************/
2610#define CAN_RDH1R_DATA4_Pos (0U)
2611#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2612#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2613#define CAN_RDH1R_DATA5_Pos (8U)
2614#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2615#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2616#define CAN_RDH1R_DATA6_Pos (16U)
2617#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2618#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2619#define CAN_RDH1R_DATA7_Pos (24U)
2620#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2621#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2624/******************* Bit definition for CAN_FMR register ********************/
2625#define CAN_FMR_FINIT ((uint8_t)0x01U)
2626#define CAN_FMR_CAN2SB_Pos (8U)
2627#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2628#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2630/******************* Bit definition for CAN_FM1R register *******************/
2631#define CAN_FM1R_FBM_Pos (0U)
2632#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
2633#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2634#define CAN_FM1R_FBM0_Pos (0U)
2635#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2636#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2637#define CAN_FM1R_FBM1_Pos (1U)
2638#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2639#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2640#define CAN_FM1R_FBM2_Pos (2U)
2641#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2642#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2643#define CAN_FM1R_FBM3_Pos (3U)
2644#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2645#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2646#define CAN_FM1R_FBM4_Pos (4U)
2647#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2648#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2649#define CAN_FM1R_FBM5_Pos (5U)
2650#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2651#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2652#define CAN_FM1R_FBM6_Pos (6U)
2653#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2654#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2655#define CAN_FM1R_FBM7_Pos (7U)
2656#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2657#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2658#define CAN_FM1R_FBM8_Pos (8U)
2659#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2660#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2661#define CAN_FM1R_FBM9_Pos (9U)
2662#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2663#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2664#define CAN_FM1R_FBM10_Pos (10U)
2665#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2666#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2667#define CAN_FM1R_FBM11_Pos (11U)
2668#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2669#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2670#define CAN_FM1R_FBM12_Pos (12U)
2671#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2672#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2673#define CAN_FM1R_FBM13_Pos (13U)
2674#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2675#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2677/******************* Bit definition for CAN_FS1R register *******************/
2678#define CAN_FS1R_FSC_Pos (0U)
2679#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
2680#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2681#define CAN_FS1R_FSC0_Pos (0U)
2682#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2683#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2684#define CAN_FS1R_FSC1_Pos (1U)
2685#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2686#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2687#define CAN_FS1R_FSC2_Pos (2U)
2688#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2689#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2690#define CAN_FS1R_FSC3_Pos (3U)
2691#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2692#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2693#define CAN_FS1R_FSC4_Pos (4U)
2694#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2695#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2696#define CAN_FS1R_FSC5_Pos (5U)
2697#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2698#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2699#define CAN_FS1R_FSC6_Pos (6U)
2700#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2701#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2702#define CAN_FS1R_FSC7_Pos (7U)
2703#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2704#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2705#define CAN_FS1R_FSC8_Pos (8U)
2706#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2707#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2708#define CAN_FS1R_FSC9_Pos (9U)
2709#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2710#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2711#define CAN_FS1R_FSC10_Pos (10U)
2712#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2713#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2714#define CAN_FS1R_FSC11_Pos (11U)
2715#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2716#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2717#define CAN_FS1R_FSC12_Pos (12U)
2718#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2719#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2720#define CAN_FS1R_FSC13_Pos (13U)
2721#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2722#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2724/****************** Bit definition for CAN_FFA1R register *******************/
2725#define CAN_FFA1R_FFA_Pos (0U)
2726#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
2727#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2728#define CAN_FFA1R_FFA0_Pos (0U)
2729#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2730#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2731#define CAN_FFA1R_FFA1_Pos (1U)
2732#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2733#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2734#define CAN_FFA1R_FFA2_Pos (2U)
2735#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2736#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2737#define CAN_FFA1R_FFA3_Pos (3U)
2738#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2739#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2740#define CAN_FFA1R_FFA4_Pos (4U)
2741#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2742#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2743#define CAN_FFA1R_FFA5_Pos (5U)
2744#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2745#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2746#define CAN_FFA1R_FFA6_Pos (6U)
2747#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2748#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2749#define CAN_FFA1R_FFA7_Pos (7U)
2750#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2751#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2752#define CAN_FFA1R_FFA8_Pos (8U)
2753#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2754#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2755#define CAN_FFA1R_FFA9_Pos (9U)
2756#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2757#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2758#define CAN_FFA1R_FFA10_Pos (10U)
2759#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2760#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2761#define CAN_FFA1R_FFA11_Pos (11U)
2762#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2763#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2764#define CAN_FFA1R_FFA12_Pos (12U)
2765#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2766#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2767#define CAN_FFA1R_FFA13_Pos (13U)
2768#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2769#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2771/******************* Bit definition for CAN_FA1R register *******************/
2772#define CAN_FA1R_FACT_Pos (0U)
2773#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
2774#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2775#define CAN_FA1R_FACT0_Pos (0U)
2776#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2777#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2778#define CAN_FA1R_FACT1_Pos (1U)
2779#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2780#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2781#define CAN_FA1R_FACT2_Pos (2U)
2782#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2783#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2784#define CAN_FA1R_FACT3_Pos (3U)
2785#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2786#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2787#define CAN_FA1R_FACT4_Pos (4U)
2788#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2789#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2790#define CAN_FA1R_FACT5_Pos (5U)
2791#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2792#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2793#define CAN_FA1R_FACT6_Pos (6U)
2794#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2795#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2796#define CAN_FA1R_FACT7_Pos (7U)
2797#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2798#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2799#define CAN_FA1R_FACT8_Pos (8U)
2800#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2801#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2802#define CAN_FA1R_FACT9_Pos (9U)
2803#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2804#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2805#define CAN_FA1R_FACT10_Pos (10U)
2806#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2807#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2808#define CAN_FA1R_FACT11_Pos (11U)
2809#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2810#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2811#define CAN_FA1R_FACT12_Pos (12U)
2812#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2813#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2814#define CAN_FA1R_FACT13_Pos (13U)
2815#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2816#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2818/******************* Bit definition for CAN_F0R1 register *******************/
2819#define CAN_F0R1_FB0_Pos (0U)
2820#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2821#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2822#define CAN_F0R1_FB1_Pos (1U)
2823#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2824#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2825#define CAN_F0R1_FB2_Pos (2U)
2826#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2827#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2828#define CAN_F0R1_FB3_Pos (3U)
2829#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2830#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2831#define CAN_F0R1_FB4_Pos (4U)
2832#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2833#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2834#define CAN_F0R1_FB5_Pos (5U)
2835#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2836#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2837#define CAN_F0R1_FB6_Pos (6U)
2838#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2839#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2840#define CAN_F0R1_FB7_Pos (7U)
2841#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2842#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2843#define CAN_F0R1_FB8_Pos (8U)
2844#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2845#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2846#define CAN_F0R1_FB9_Pos (9U)
2847#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2848#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2849#define CAN_F0R1_FB10_Pos (10U)
2850#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2851#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2852#define CAN_F0R1_FB11_Pos (11U)
2853#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2854#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2855#define CAN_F0R1_FB12_Pos (12U)
2856#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2857#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2858#define CAN_F0R1_FB13_Pos (13U)
2859#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2860#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2861#define CAN_F0R1_FB14_Pos (14U)
2862#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2863#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2864#define CAN_F0R1_FB15_Pos (15U)
2865#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2866#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2867#define CAN_F0R1_FB16_Pos (16U)
2868#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2869#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2870#define CAN_F0R1_FB17_Pos (17U)
2871#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2872#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2873#define CAN_F0R1_FB18_Pos (18U)
2874#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2875#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2876#define CAN_F0R1_FB19_Pos (19U)
2877#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2878#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2879#define CAN_F0R1_FB20_Pos (20U)
2880#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2881#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2882#define CAN_F0R1_FB21_Pos (21U)
2883#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2884#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2885#define CAN_F0R1_FB22_Pos (22U)
2886#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2887#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2888#define CAN_F0R1_FB23_Pos (23U)
2889#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2890#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2891#define CAN_F0R1_FB24_Pos (24U)
2892#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2893#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2894#define CAN_F0R1_FB25_Pos (25U)
2895#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2896#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2897#define CAN_F0R1_FB26_Pos (26U)
2898#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2899#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2900#define CAN_F0R1_FB27_Pos (27U)
2901#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2902#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2903#define CAN_F0R1_FB28_Pos (28U)
2904#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2905#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2906#define CAN_F0R1_FB29_Pos (29U)
2907#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2908#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2909#define CAN_F0R1_FB30_Pos (30U)
2910#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2911#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2912#define CAN_F0R1_FB31_Pos (31U)
2913#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2914#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2916/******************* Bit definition for CAN_F1R1 register *******************/
2917#define CAN_F1R1_FB0_Pos (0U)
2918#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2919#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2920#define CAN_F1R1_FB1_Pos (1U)
2921#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2922#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2923#define CAN_F1R1_FB2_Pos (2U)
2924#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2925#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2926#define CAN_F1R1_FB3_Pos (3U)
2927#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2928#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2929#define CAN_F1R1_FB4_Pos (4U)
2930#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2931#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2932#define CAN_F1R1_FB5_Pos (5U)
2933#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2934#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2935#define CAN_F1R1_FB6_Pos (6U)
2936#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2937#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2938#define CAN_F1R1_FB7_Pos (7U)
2939#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2940#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2941#define CAN_F1R1_FB8_Pos (8U)
2942#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2943#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2944#define CAN_F1R1_FB9_Pos (9U)
2945#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2946#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2947#define CAN_F1R1_FB10_Pos (10U)
2948#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2949#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2950#define CAN_F1R1_FB11_Pos (11U)
2951#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2952#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2953#define CAN_F1R1_FB12_Pos (12U)
2954#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2955#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2956#define CAN_F1R1_FB13_Pos (13U)
2957#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2958#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2959#define CAN_F1R1_FB14_Pos (14U)
2960#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2961#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2962#define CAN_F1R1_FB15_Pos (15U)
2963#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2964#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2965#define CAN_F1R1_FB16_Pos (16U)
2966#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2967#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2968#define CAN_F1R1_FB17_Pos (17U)
2969#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2970#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2971#define CAN_F1R1_FB18_Pos (18U)
2972#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2973#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2974#define CAN_F1R1_FB19_Pos (19U)
2975#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2976#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2977#define CAN_F1R1_FB20_Pos (20U)
2978#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2979#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2980#define CAN_F1R1_FB21_Pos (21U)
2981#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2982#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2983#define CAN_F1R1_FB22_Pos (22U)
2984#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2985#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2986#define CAN_F1R1_FB23_Pos (23U)
2987#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2988#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2989#define CAN_F1R1_FB24_Pos (24U)
2990#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2991#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2992#define CAN_F1R1_FB25_Pos (25U)
2993#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2994#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2995#define CAN_F1R1_FB26_Pos (26U)
2996#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2997#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2998#define CAN_F1R1_FB27_Pos (27U)
2999#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3000#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3001#define CAN_F1R1_FB28_Pos (28U)
3002#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3003#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3004#define CAN_F1R1_FB29_Pos (29U)
3005#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3006#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3007#define CAN_F1R1_FB30_Pos (30U)
3008#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3009#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3010#define CAN_F1R1_FB31_Pos (31U)
3011#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3012#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3014/******************* Bit definition for CAN_F2R1 register *******************/
3015#define CAN_F2R1_FB0_Pos (0U)
3016#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
3017#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
3018#define CAN_F2R1_FB1_Pos (1U)
3019#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
3020#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
3021#define CAN_F2R1_FB2_Pos (2U)
3022#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
3023#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
3024#define CAN_F2R1_FB3_Pos (3U)
3025#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
3026#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
3027#define CAN_F2R1_FB4_Pos (4U)
3028#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
3029#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
3030#define CAN_F2R1_FB5_Pos (5U)
3031#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
3032#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
3033#define CAN_F2R1_FB6_Pos (6U)
3034#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
3035#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
3036#define CAN_F2R1_FB7_Pos (7U)
3037#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
3038#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
3039#define CAN_F2R1_FB8_Pos (8U)
3040#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
3041#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
3042#define CAN_F2R1_FB9_Pos (9U)
3043#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
3044#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
3045#define CAN_F2R1_FB10_Pos (10U)
3046#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
3047#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
3048#define CAN_F2R1_FB11_Pos (11U)
3049#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
3050#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
3051#define CAN_F2R1_FB12_Pos (12U)
3052#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
3053#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
3054#define CAN_F2R1_FB13_Pos (13U)
3055#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
3056#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
3057#define CAN_F2R1_FB14_Pos (14U)
3058#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
3059#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
3060#define CAN_F2R1_FB15_Pos (15U)
3061#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
3062#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
3063#define CAN_F2R1_FB16_Pos (16U)
3064#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
3065#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
3066#define CAN_F2R1_FB17_Pos (17U)
3067#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
3068#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
3069#define CAN_F2R1_FB18_Pos (18U)
3070#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
3071#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
3072#define CAN_F2R1_FB19_Pos (19U)
3073#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
3074#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
3075#define CAN_F2R1_FB20_Pos (20U)
3076#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
3077#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
3078#define CAN_F2R1_FB21_Pos (21U)
3079#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
3080#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
3081#define CAN_F2R1_FB22_Pos (22U)
3082#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
3083#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
3084#define CAN_F2R1_FB23_Pos (23U)
3085#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
3086#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
3087#define CAN_F2R1_FB24_Pos (24U)
3088#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
3089#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
3090#define CAN_F2R1_FB25_Pos (25U)
3091#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
3092#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
3093#define CAN_F2R1_FB26_Pos (26U)
3094#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
3095#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
3096#define CAN_F2R1_FB27_Pos (27U)
3097#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
3098#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3099#define CAN_F2R1_FB28_Pos (28U)
3100#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3101#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3102#define CAN_F2R1_FB29_Pos (29U)
3103#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3104#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3105#define CAN_F2R1_FB30_Pos (30U)
3106#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3107#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3108#define CAN_F2R1_FB31_Pos (31U)
3109#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3110#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3112/******************* Bit definition for CAN_F3R1 register *******************/
3113#define CAN_F3R1_FB0_Pos (0U)
3114#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3115#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3116#define CAN_F3R1_FB1_Pos (1U)
3117#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3118#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3119#define CAN_F3R1_FB2_Pos (2U)
3120#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3121#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3122#define CAN_F3R1_FB3_Pos (3U)
3123#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3124#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3125#define CAN_F3R1_FB4_Pos (4U)
3126#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3127#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3128#define CAN_F3R1_FB5_Pos (5U)
3129#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3130#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3131#define CAN_F3R1_FB6_Pos (6U)
3132#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3133#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3134#define CAN_F3R1_FB7_Pos (7U)
3135#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3136#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3137#define CAN_F3R1_FB8_Pos (8U)
3138#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3139#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3140#define CAN_F3R1_FB9_Pos (9U)
3141#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3142#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3143#define CAN_F3R1_FB10_Pos (10U)
3144#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3145#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3146#define CAN_F3R1_FB11_Pos (11U)
3147#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3148#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3149#define CAN_F3R1_FB12_Pos (12U)
3150#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3151#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3152#define CAN_F3R1_FB13_Pos (13U)
3153#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3154#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3155#define CAN_F3R1_FB14_Pos (14U)
3156#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3157#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3158#define CAN_F3R1_FB15_Pos (15U)
3159#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3160#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3161#define CAN_F3R1_FB16_Pos (16U)
3162#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3163#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3164#define CAN_F3R1_FB17_Pos (17U)
3165#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3166#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3167#define CAN_F3R1_FB18_Pos (18U)
3168#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3169#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3170#define CAN_F3R1_FB19_Pos (19U)
3171#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3172#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3173#define CAN_F3R1_FB20_Pos (20U)
3174#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3175#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3176#define CAN_F3R1_FB21_Pos (21U)
3177#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3178#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3179#define CAN_F3R1_FB22_Pos (22U)
3180#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3181#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3182#define CAN_F3R1_FB23_Pos (23U)
3183#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3184#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3185#define CAN_F3R1_FB24_Pos (24U)
3186#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3187#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3188#define CAN_F3R1_FB25_Pos (25U)
3189#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3190#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3191#define CAN_F3R1_FB26_Pos (26U)
3192#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3193#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3194#define CAN_F3R1_FB27_Pos (27U)
3195#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3196#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3197#define CAN_F3R1_FB28_Pos (28U)
3198#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3199#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3200#define CAN_F3R1_FB29_Pos (29U)
3201#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3202#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3203#define CAN_F3R1_FB30_Pos (30U)
3204#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3205#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3206#define CAN_F3R1_FB31_Pos (31U)
3207#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3208#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3210/******************* Bit definition for CAN_F4R1 register *******************/
3211#define CAN_F4R1_FB0_Pos (0U)
3212#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3213#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3214#define CAN_F4R1_FB1_Pos (1U)
3215#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3216#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3217#define CAN_F4R1_FB2_Pos (2U)
3218#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3219#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3220#define CAN_F4R1_FB3_Pos (3U)
3221#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3222#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3223#define CAN_F4R1_FB4_Pos (4U)
3224#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3225#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3226#define CAN_F4R1_FB5_Pos (5U)
3227#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3228#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3229#define CAN_F4R1_FB6_Pos (6U)
3230#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3231#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3232#define CAN_F4R1_FB7_Pos (7U)
3233#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3234#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3235#define CAN_F4R1_FB8_Pos (8U)
3236#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3237#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3238#define CAN_F4R1_FB9_Pos (9U)
3239#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3240#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3241#define CAN_F4R1_FB10_Pos (10U)
3242#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3243#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3244#define CAN_F4R1_FB11_Pos (11U)
3245#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3246#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3247#define CAN_F4R1_FB12_Pos (12U)
3248#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3249#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3250#define CAN_F4R1_FB13_Pos (13U)
3251#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3252#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3253#define CAN_F4R1_FB14_Pos (14U)
3254#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3255#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3256#define CAN_F4R1_FB15_Pos (15U)
3257#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3258#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3259#define CAN_F4R1_FB16_Pos (16U)
3260#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3261#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3262#define CAN_F4R1_FB17_Pos (17U)
3263#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3264#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3265#define CAN_F4R1_FB18_Pos (18U)
3266#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3267#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3268#define CAN_F4R1_FB19_Pos (19U)
3269#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3270#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3271#define CAN_F4R1_FB20_Pos (20U)
3272#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3273#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3274#define CAN_F4R1_FB21_Pos (21U)
3275#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3276#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3277#define CAN_F4R1_FB22_Pos (22U)
3278#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3279#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3280#define CAN_F4R1_FB23_Pos (23U)
3281#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3282#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3283#define CAN_F4R1_FB24_Pos (24U)
3284#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3285#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3286#define CAN_F4R1_FB25_Pos (25U)
3287#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3288#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3289#define CAN_F4R1_FB26_Pos (26U)
3290#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3291#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3292#define CAN_F4R1_FB27_Pos (27U)
3293#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3294#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3295#define CAN_F4R1_FB28_Pos (28U)
3296#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3297#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3298#define CAN_F4R1_FB29_Pos (29U)
3299#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3300#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3301#define CAN_F4R1_FB30_Pos (30U)
3302#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3303#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3304#define CAN_F4R1_FB31_Pos (31U)
3305#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3306#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3308/******************* Bit definition for CAN_F5R1 register *******************/
3309#define CAN_F5R1_FB0_Pos (0U)
3310#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3311#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3312#define CAN_F5R1_FB1_Pos (1U)
3313#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3314#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3315#define CAN_F5R1_FB2_Pos (2U)
3316#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3317#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3318#define CAN_F5R1_FB3_Pos (3U)
3319#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3320#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3321#define CAN_F5R1_FB4_Pos (4U)
3322#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3323#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3324#define CAN_F5R1_FB5_Pos (5U)
3325#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3326#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3327#define CAN_F5R1_FB6_Pos (6U)
3328#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3329#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3330#define CAN_F5R1_FB7_Pos (7U)
3331#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3332#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3333#define CAN_F5R1_FB8_Pos (8U)
3334#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3335#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3336#define CAN_F5R1_FB9_Pos (9U)
3337#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3338#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3339#define CAN_F5R1_FB10_Pos (10U)
3340#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3341#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3342#define CAN_F5R1_FB11_Pos (11U)
3343#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3344#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3345#define CAN_F5R1_FB12_Pos (12U)
3346#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3347#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3348#define CAN_F5R1_FB13_Pos (13U)
3349#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3350#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3351#define CAN_F5R1_FB14_Pos (14U)
3352#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3353#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3354#define CAN_F5R1_FB15_Pos (15U)
3355#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3356#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3357#define CAN_F5R1_FB16_Pos (16U)
3358#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3359#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3360#define CAN_F5R1_FB17_Pos (17U)
3361#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3362#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3363#define CAN_F5R1_FB18_Pos (18U)
3364#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3365#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3366#define CAN_F5R1_FB19_Pos (19U)
3367#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3368#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3369#define CAN_F5R1_FB20_Pos (20U)
3370#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3371#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3372#define CAN_F5R1_FB21_Pos (21U)
3373#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3374#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3375#define CAN_F5R1_FB22_Pos (22U)
3376#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3377#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3378#define CAN_F5R1_FB23_Pos (23U)
3379#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3380#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3381#define CAN_F5R1_FB24_Pos (24U)
3382#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3383#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3384#define CAN_F5R1_FB25_Pos (25U)
3385#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3386#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3387#define CAN_F5R1_FB26_Pos (26U)
3388#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3389#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3390#define CAN_F5R1_FB27_Pos (27U)
3391#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3392#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3393#define CAN_F5R1_FB28_Pos (28U)
3394#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3395#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3396#define CAN_F5R1_FB29_Pos (29U)
3397#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3398#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3399#define CAN_F5R1_FB30_Pos (30U)
3400#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3401#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3402#define CAN_F5R1_FB31_Pos (31U)
3403#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3404#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3406/******************* Bit definition for CAN_F6R1 register *******************/
3407#define CAN_F6R1_FB0_Pos (0U)
3408#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3409#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3410#define CAN_F6R1_FB1_Pos (1U)
3411#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3412#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3413#define CAN_F6R1_FB2_Pos (2U)
3414#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3415#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3416#define CAN_F6R1_FB3_Pos (3U)
3417#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3418#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3419#define CAN_F6R1_FB4_Pos (4U)
3420#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3421#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3422#define CAN_F6R1_FB5_Pos (5U)
3423#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3424#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3425#define CAN_F6R1_FB6_Pos (6U)
3426#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3427#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3428#define CAN_F6R1_FB7_Pos (7U)
3429#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3430#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3431#define CAN_F6R1_FB8_Pos (8U)
3432#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3433#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3434#define CAN_F6R1_FB9_Pos (9U)
3435#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3436#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3437#define CAN_F6R1_FB10_Pos (10U)
3438#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3439#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3440#define CAN_F6R1_FB11_Pos (11U)
3441#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3442#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3443#define CAN_F6R1_FB12_Pos (12U)
3444#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3445#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3446#define CAN_F6R1_FB13_Pos (13U)
3447#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3448#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3449#define CAN_F6R1_FB14_Pos (14U)
3450#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3451#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3452#define CAN_F6R1_FB15_Pos (15U)
3453#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3454#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3455#define CAN_F6R1_FB16_Pos (16U)
3456#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3457#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3458#define CAN_F6R1_FB17_Pos (17U)
3459#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3460#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3461#define CAN_F6R1_FB18_Pos (18U)
3462#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3463#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3464#define CAN_F6R1_FB19_Pos (19U)
3465#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3466#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3467#define CAN_F6R1_FB20_Pos (20U)
3468#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3469#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3470#define CAN_F6R1_FB21_Pos (21U)
3471#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3472#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3473#define CAN_F6R1_FB22_Pos (22U)
3474#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3475#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3476#define CAN_F6R1_FB23_Pos (23U)
3477#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3478#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3479#define CAN_F6R1_FB24_Pos (24U)
3480#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3481#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3482#define CAN_F6R1_FB25_Pos (25U)
3483#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3484#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3485#define CAN_F6R1_FB26_Pos (26U)
3486#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3487#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3488#define CAN_F6R1_FB27_Pos (27U)
3489#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3490#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3491#define CAN_F6R1_FB28_Pos (28U)
3492#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3493#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3494#define CAN_F6R1_FB29_Pos (29U)
3495#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3496#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3497#define CAN_F6R1_FB30_Pos (30U)
3498#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3499#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3500#define CAN_F6R1_FB31_Pos (31U)
3501#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3502#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3504/******************* Bit definition for CAN_F7R1 register *******************/
3505#define CAN_F7R1_FB0_Pos (0U)
3506#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3507#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3508#define CAN_F7R1_FB1_Pos (1U)
3509#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3510#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3511#define CAN_F7R1_FB2_Pos (2U)
3512#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3513#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3514#define CAN_F7R1_FB3_Pos (3U)
3515#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3516#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3517#define CAN_F7R1_FB4_Pos (4U)
3518#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3519#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3520#define CAN_F7R1_FB5_Pos (5U)
3521#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3522#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3523#define CAN_F7R1_FB6_Pos (6U)
3524#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3525#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3526#define CAN_F7R1_FB7_Pos (7U)
3527#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3528#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3529#define CAN_F7R1_FB8_Pos (8U)
3530#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3531#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3532#define CAN_F7R1_FB9_Pos (9U)
3533#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3534#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3535#define CAN_F7R1_FB10_Pos (10U)
3536#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3537#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3538#define CAN_F7R1_FB11_Pos (11U)
3539#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3540#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3541#define CAN_F7R1_FB12_Pos (12U)
3542#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3543#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3544#define CAN_F7R1_FB13_Pos (13U)
3545#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3546#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3547#define CAN_F7R1_FB14_Pos (14U)
3548#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3549#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3550#define CAN_F7R1_FB15_Pos (15U)
3551#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3552#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3553#define CAN_F7R1_FB16_Pos (16U)
3554#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3555#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3556#define CAN_F7R1_FB17_Pos (17U)
3557#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3558#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3559#define CAN_F7R1_FB18_Pos (18U)
3560#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3561#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3562#define CAN_F7R1_FB19_Pos (19U)
3563#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3564#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3565#define CAN_F7R1_FB20_Pos (20U)
3566#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3567#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3568#define CAN_F7R1_FB21_Pos (21U)
3569#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3570#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3571#define CAN_F7R1_FB22_Pos (22U)
3572#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3573#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3574#define CAN_F7R1_FB23_Pos (23U)
3575#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3576#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3577#define CAN_F7R1_FB24_Pos (24U)
3578#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3579#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3580#define CAN_F7R1_FB25_Pos (25U)
3581#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3582#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3583#define CAN_F7R1_FB26_Pos (26U)
3584#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3585#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3586#define CAN_F7R1_FB27_Pos (27U)
3587#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3588#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3589#define CAN_F7R1_FB28_Pos (28U)
3590#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3591#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3592#define CAN_F7R1_FB29_Pos (29U)
3593#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3594#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3595#define CAN_F7R1_FB30_Pos (30U)
3596#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3597#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3598#define CAN_F7R1_FB31_Pos (31U)
3599#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3600#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3602/******************* Bit definition for CAN_F8R1 register *******************/
3603#define CAN_F8R1_FB0_Pos (0U)
3604#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3605#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3606#define CAN_F8R1_FB1_Pos (1U)
3607#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3608#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3609#define CAN_F8R1_FB2_Pos (2U)
3610#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3611#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3612#define CAN_F8R1_FB3_Pos (3U)
3613#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3614#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3615#define CAN_F8R1_FB4_Pos (4U)
3616#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3617#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3618#define CAN_F8R1_FB5_Pos (5U)
3619#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3620#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3621#define CAN_F8R1_FB6_Pos (6U)
3622#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3623#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3624#define CAN_F8R1_FB7_Pos (7U)
3625#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3626#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3627#define CAN_F8R1_FB8_Pos (8U)
3628#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3629#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3630#define CAN_F8R1_FB9_Pos (9U)
3631#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3632#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3633#define CAN_F8R1_FB10_Pos (10U)
3634#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3635#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3636#define CAN_F8R1_FB11_Pos (11U)
3637#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3638#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3639#define CAN_F8R1_FB12_Pos (12U)
3640#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3641#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3642#define CAN_F8R1_FB13_Pos (13U)
3643#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3644#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3645#define CAN_F8R1_FB14_Pos (14U)
3646#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3647#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3648#define CAN_F8R1_FB15_Pos (15U)
3649#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3650#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3651#define CAN_F8R1_FB16_Pos (16U)
3652#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3653#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3654#define CAN_F8R1_FB17_Pos (17U)
3655#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3656#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3657#define CAN_F8R1_FB18_Pos (18U)
3658#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3659#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3660#define CAN_F8R1_FB19_Pos (19U)
3661#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3662#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3663#define CAN_F8R1_FB20_Pos (20U)
3664#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3665#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3666#define CAN_F8R1_FB21_Pos (21U)
3667#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3668#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3669#define CAN_F8R1_FB22_Pos (22U)
3670#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3671#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3672#define CAN_F8R1_FB23_Pos (23U)
3673#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3674#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3675#define CAN_F8R1_FB24_Pos (24U)
3676#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3677#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3678#define CAN_F8R1_FB25_Pos (25U)
3679#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3680#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3681#define CAN_F8R1_FB26_Pos (26U)
3682#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3683#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3684#define CAN_F8R1_FB27_Pos (27U)
3685#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3686#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3687#define CAN_F8R1_FB28_Pos (28U)
3688#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3689#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3690#define CAN_F8R1_FB29_Pos (29U)
3691#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3692#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3693#define CAN_F8R1_FB30_Pos (30U)
3694#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3695#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3696#define CAN_F8R1_FB31_Pos (31U)
3697#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3698#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3700/******************* Bit definition for CAN_F9R1 register *******************/
3701#define CAN_F9R1_FB0_Pos (0U)
3702#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3703#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3704#define CAN_F9R1_FB1_Pos (1U)
3705#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3706#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3707#define CAN_F9R1_FB2_Pos (2U)
3708#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3709#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3710#define CAN_F9R1_FB3_Pos (3U)
3711#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3712#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3713#define CAN_F9R1_FB4_Pos (4U)
3714#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3715#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3716#define CAN_F9R1_FB5_Pos (5U)
3717#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3718#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3719#define CAN_F9R1_FB6_Pos (6U)
3720#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3721#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3722#define CAN_F9R1_FB7_Pos (7U)
3723#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3724#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3725#define CAN_F9R1_FB8_Pos (8U)
3726#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3727#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3728#define CAN_F9R1_FB9_Pos (9U)
3729#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3730#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3731#define CAN_F9R1_FB10_Pos (10U)
3732#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3733#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3734#define CAN_F9R1_FB11_Pos (11U)
3735#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3736#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3737#define CAN_F9R1_FB12_Pos (12U)
3738#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3739#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3740#define CAN_F9R1_FB13_Pos (13U)
3741#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3742#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3743#define CAN_F9R1_FB14_Pos (14U)
3744#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3745#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3746#define CAN_F9R1_FB15_Pos (15U)
3747#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3748#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3749#define CAN_F9R1_FB16_Pos (16U)
3750#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3751#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3752#define CAN_F9R1_FB17_Pos (17U)
3753#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3754#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3755#define CAN_F9R1_FB18_Pos (18U)
3756#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3757#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3758#define CAN_F9R1_FB19_Pos (19U)
3759#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3760#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3761#define CAN_F9R1_FB20_Pos (20U)
3762#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3763#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3764#define CAN_F9R1_FB21_Pos (21U)
3765#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3766#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3767#define CAN_F9R1_FB22_Pos (22U)
3768#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3769#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3770#define CAN_F9R1_FB23_Pos (23U)
3771#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3772#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3773#define CAN_F9R1_FB24_Pos (24U)
3774#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3775#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3776#define CAN_F9R1_FB25_Pos (25U)
3777#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3778#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3779#define CAN_F9R1_FB26_Pos (26U)
3780#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3781#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3782#define CAN_F9R1_FB27_Pos (27U)
3783#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3784#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3785#define CAN_F9R1_FB28_Pos (28U)
3786#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3787#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3788#define CAN_F9R1_FB29_Pos (29U)
3789#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3790#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3791#define CAN_F9R1_FB30_Pos (30U)
3792#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3793#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3794#define CAN_F9R1_FB31_Pos (31U)
3795#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3796#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3798/******************* Bit definition for CAN_F10R1 register ******************/
3799#define CAN_F10R1_FB0_Pos (0U)
3800#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3801#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3802#define CAN_F10R1_FB1_Pos (1U)
3803#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3804#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3805#define CAN_F10R1_FB2_Pos (2U)
3806#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3807#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3808#define CAN_F10R1_FB3_Pos (3U)
3809#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3810#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3811#define CAN_F10R1_FB4_Pos (4U)
3812#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3813#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3814#define CAN_F10R1_FB5_Pos (5U)
3815#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3816#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3817#define CAN_F10R1_FB6_Pos (6U)
3818#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3819#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3820#define CAN_F10R1_FB7_Pos (7U)
3821#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3822#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3823#define CAN_F10R1_FB8_Pos (8U)
3824#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3825#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3826#define CAN_F10R1_FB9_Pos (9U)
3827#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3828#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3829#define CAN_F10R1_FB10_Pos (10U)
3830#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3831#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3832#define CAN_F10R1_FB11_Pos (11U)
3833#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3834#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3835#define CAN_F10R1_FB12_Pos (12U)
3836#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3837#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3838#define CAN_F10R1_FB13_Pos (13U)
3839#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3840#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3841#define CAN_F10R1_FB14_Pos (14U)
3842#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3843#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3844#define CAN_F10R1_FB15_Pos (15U)
3845#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3846#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3847#define CAN_F10R1_FB16_Pos (16U)
3848#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3849#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3850#define CAN_F10R1_FB17_Pos (17U)
3851#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3852#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3853#define CAN_F10R1_FB18_Pos (18U)
3854#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3855#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3856#define CAN_F10R1_FB19_Pos (19U)
3857#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3858#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3859#define CAN_F10R1_FB20_Pos (20U)
3860#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3861#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3862#define CAN_F10R1_FB21_Pos (21U)
3863#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3864#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3865#define CAN_F10R1_FB22_Pos (22U)
3866#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3867#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3868#define CAN_F10R1_FB23_Pos (23U)
3869#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3870#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3871#define CAN_F10R1_FB24_Pos (24U)
3872#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3873#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3874#define CAN_F10R1_FB25_Pos (25U)
3875#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3876#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3877#define CAN_F10R1_FB26_Pos (26U)
3878#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3879#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3880#define CAN_F10R1_FB27_Pos (27U)
3881#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3882#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3883#define CAN_F10R1_FB28_Pos (28U)
3884#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3885#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3886#define CAN_F10R1_FB29_Pos (29U)
3887#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3888#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3889#define CAN_F10R1_FB30_Pos (30U)
3890#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3891#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3892#define CAN_F10R1_FB31_Pos (31U)
3893#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3894#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3896/******************* Bit definition for CAN_F11R1 register ******************/
3897#define CAN_F11R1_FB0_Pos (0U)
3898#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3899#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3900#define CAN_F11R1_FB1_Pos (1U)
3901#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3902#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3903#define CAN_F11R1_FB2_Pos (2U)
3904#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3905#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3906#define CAN_F11R1_FB3_Pos (3U)
3907#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3908#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3909#define CAN_F11R1_FB4_Pos (4U)
3910#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3911#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3912#define CAN_F11R1_FB5_Pos (5U)
3913#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3914#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3915#define CAN_F11R1_FB6_Pos (6U)
3916#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3917#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3918#define CAN_F11R1_FB7_Pos (7U)
3919#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3920#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3921#define CAN_F11R1_FB8_Pos (8U)
3922#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3923#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3924#define CAN_F11R1_FB9_Pos (9U)
3925#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3926#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3927#define CAN_F11R1_FB10_Pos (10U)
3928#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3929#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3930#define CAN_F11R1_FB11_Pos (11U)
3931#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3932#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3933#define CAN_F11R1_FB12_Pos (12U)
3934#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3935#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3936#define CAN_F11R1_FB13_Pos (13U)
3937#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3938#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3939#define CAN_F11R1_FB14_Pos (14U)
3940#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3941#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3942#define CAN_F11R1_FB15_Pos (15U)
3943#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3944#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3945#define CAN_F11R1_FB16_Pos (16U)
3946#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3947#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3948#define CAN_F11R1_FB17_Pos (17U)
3949#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3950#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3951#define CAN_F11R1_FB18_Pos (18U)
3952#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3953#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3954#define CAN_F11R1_FB19_Pos (19U)
3955#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3956#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3957#define CAN_F11R1_FB20_Pos (20U)
3958#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3959#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3960#define CAN_F11R1_FB21_Pos (21U)
3961#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3962#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3963#define CAN_F11R1_FB22_Pos (22U)
3964#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3965#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3966#define CAN_F11R1_FB23_Pos (23U)
3967#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3968#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3969#define CAN_F11R1_FB24_Pos (24U)
3970#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3971#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3972#define CAN_F11R1_FB25_Pos (25U)
3973#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3974#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3975#define CAN_F11R1_FB26_Pos (26U)
3976#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3977#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3978#define CAN_F11R1_FB27_Pos (27U)
3979#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3980#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3981#define CAN_F11R1_FB28_Pos (28U)
3982#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3983#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3984#define CAN_F11R1_FB29_Pos (29U)
3985#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3986#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3987#define CAN_F11R1_FB30_Pos (30U)
3988#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3989#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3990#define CAN_F11R1_FB31_Pos (31U)
3991#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3992#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3994/******************* Bit definition for CAN_F12R1 register ******************/
3995#define CAN_F12R1_FB0_Pos (0U)
3996#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3997#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3998#define CAN_F12R1_FB1_Pos (1U)
3999#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4000#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4001#define CAN_F12R1_FB2_Pos (2U)
4002#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4003#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4004#define CAN_F12R1_FB3_Pos (3U)
4005#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4006#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4007#define CAN_F12R1_FB4_Pos (4U)
4008#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4009#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4010#define CAN_F12R1_FB5_Pos (5U)
4011#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4012#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4013#define CAN_F12R1_FB6_Pos (6U)
4014#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4015#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
4016#define CAN_F12R1_FB7_Pos (7U)
4017#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
4018#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
4019#define CAN_F12R1_FB8_Pos (8U)
4020#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
4021#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
4022#define CAN_F12R1_FB9_Pos (9U)
4023#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
4024#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
4025#define CAN_F12R1_FB10_Pos (10U)
4026#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
4027#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
4028#define CAN_F12R1_FB11_Pos (11U)
4029#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
4030#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
4031#define CAN_F12R1_FB12_Pos (12U)
4032#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
4033#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
4034#define CAN_F12R1_FB13_Pos (13U)
4035#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
4036#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
4037#define CAN_F12R1_FB14_Pos (14U)
4038#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
4039#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
4040#define CAN_F12R1_FB15_Pos (15U)
4041#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
4042#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
4043#define CAN_F12R1_FB16_Pos (16U)
4044#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
4045#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
4046#define CAN_F12R1_FB17_Pos (17U)
4047#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
4048#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
4049#define CAN_F12R1_FB18_Pos (18U)
4050#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
4051#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
4052#define CAN_F12R1_FB19_Pos (19U)
4053#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
4054#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
4055#define CAN_F12R1_FB20_Pos (20U)
4056#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
4057#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
4058#define CAN_F12R1_FB21_Pos (21U)
4059#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
4060#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
4061#define CAN_F12R1_FB22_Pos (22U)
4062#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
4063#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
4064#define CAN_F12R1_FB23_Pos (23U)
4065#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
4066#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
4067#define CAN_F12R1_FB24_Pos (24U)
4068#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
4069#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
4070#define CAN_F12R1_FB25_Pos (25U)
4071#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
4072#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
4073#define CAN_F12R1_FB26_Pos (26U)
4074#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
4075#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
4076#define CAN_F12R1_FB27_Pos (27U)
4077#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
4078#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
4079#define CAN_F12R1_FB28_Pos (28U)
4080#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
4081#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
4082#define CAN_F12R1_FB29_Pos (29U)
4083#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
4084#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
4085#define CAN_F12R1_FB30_Pos (30U)
4086#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
4087#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
4088#define CAN_F12R1_FB31_Pos (31U)
4089#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
4090#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
4092/******************* Bit definition for CAN_F13R1 register ******************/
4093#define CAN_F13R1_FB0_Pos (0U)
4094#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
4095#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
4096#define CAN_F13R1_FB1_Pos (1U)
4097#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
4098#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4099#define CAN_F13R1_FB2_Pos (2U)
4100#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4101#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4102#define CAN_F13R1_FB3_Pos (3U)
4103#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4104#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4105#define CAN_F13R1_FB4_Pos (4U)
4106#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4107#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4108#define CAN_F13R1_FB5_Pos (5U)
4109#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4110#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4111#define CAN_F13R1_FB6_Pos (6U)
4112#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4113#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4114#define CAN_F13R1_FB7_Pos (7U)
4115#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4116#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4117#define CAN_F13R1_FB8_Pos (8U)
4118#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4119#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4120#define CAN_F13R1_FB9_Pos (9U)
4121#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4122#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4123#define CAN_F13R1_FB10_Pos (10U)
4124#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4125#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4126#define CAN_F13R1_FB11_Pos (11U)
4127#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4128#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4129#define CAN_F13R1_FB12_Pos (12U)
4130#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4131#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4132#define CAN_F13R1_FB13_Pos (13U)
4133#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4134#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4135#define CAN_F13R1_FB14_Pos (14U)
4136#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4137#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4138#define CAN_F13R1_FB15_Pos (15U)
4139#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4140#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4141#define CAN_F13R1_FB16_Pos (16U)
4142#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4143#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4144#define CAN_F13R1_FB17_Pos (17U)
4145#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4146#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4147#define CAN_F13R1_FB18_Pos (18U)
4148#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4149#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4150#define CAN_F13R1_FB19_Pos (19U)
4151#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4152#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4153#define CAN_F13R1_FB20_Pos (20U)
4154#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4155#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4156#define CAN_F13R1_FB21_Pos (21U)
4157#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4158#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4159#define CAN_F13R1_FB22_Pos (22U)
4160#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4161#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4162#define CAN_F13R1_FB23_Pos (23U)
4163#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4164#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4165#define CAN_F13R1_FB24_Pos (24U)
4166#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4167#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4168#define CAN_F13R1_FB25_Pos (25U)
4169#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4170#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4171#define CAN_F13R1_FB26_Pos (26U)
4172#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4173#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4174#define CAN_F13R1_FB27_Pos (27U)
4175#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4176#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4177#define CAN_F13R1_FB28_Pos (28U)
4178#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4179#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4180#define CAN_F13R1_FB29_Pos (29U)
4181#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4182#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4183#define CAN_F13R1_FB30_Pos (30U)
4184#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4185#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4186#define CAN_F13R1_FB31_Pos (31U)
4187#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4188#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4190/******************* Bit definition for CAN_F0R2 register *******************/
4191#define CAN_F0R2_FB0_Pos (0U)
4192#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4193#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4194#define CAN_F0R2_FB1_Pos (1U)
4195#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4196#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4197#define CAN_F0R2_FB2_Pos (2U)
4198#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4199#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4200#define CAN_F0R2_FB3_Pos (3U)
4201#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4202#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4203#define CAN_F0R2_FB4_Pos (4U)
4204#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4205#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4206#define CAN_F0R2_FB5_Pos (5U)
4207#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4208#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4209#define CAN_F0R2_FB6_Pos (6U)
4210#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4211#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4212#define CAN_F0R2_FB7_Pos (7U)
4213#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4214#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4215#define CAN_F0R2_FB8_Pos (8U)
4216#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4217#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4218#define CAN_F0R2_FB9_Pos (9U)
4219#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4220#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4221#define CAN_F0R2_FB10_Pos (10U)
4222#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4223#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4224#define CAN_F0R2_FB11_Pos (11U)
4225#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4226#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4227#define CAN_F0R2_FB12_Pos (12U)
4228#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4229#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4230#define CAN_F0R2_FB13_Pos (13U)
4231#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4232#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4233#define CAN_F0R2_FB14_Pos (14U)
4234#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4235#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4236#define CAN_F0R2_FB15_Pos (15U)
4237#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4238#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4239#define CAN_F0R2_FB16_Pos (16U)
4240#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4241#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4242#define CAN_F0R2_FB17_Pos (17U)
4243#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4244#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4245#define CAN_F0R2_FB18_Pos (18U)
4246#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4247#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4248#define CAN_F0R2_FB19_Pos (19U)
4249#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4250#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4251#define CAN_F0R2_FB20_Pos (20U)
4252#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4253#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4254#define CAN_F0R2_FB21_Pos (21U)
4255#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4256#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4257#define CAN_F0R2_FB22_Pos (22U)
4258#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4259#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4260#define CAN_F0R2_FB23_Pos (23U)
4261#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4262#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4263#define CAN_F0R2_FB24_Pos (24U)
4264#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4265#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4266#define CAN_F0R2_FB25_Pos (25U)
4267#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4268#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4269#define CAN_F0R2_FB26_Pos (26U)
4270#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4271#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4272#define CAN_F0R2_FB27_Pos (27U)
4273#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4274#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4275#define CAN_F0R2_FB28_Pos (28U)
4276#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4277#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4278#define CAN_F0R2_FB29_Pos (29U)
4279#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4280#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4281#define CAN_F0R2_FB30_Pos (30U)
4282#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4283#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4284#define CAN_F0R2_FB31_Pos (31U)
4285#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4286#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4288/******************* Bit definition for CAN_F1R2 register *******************/
4289#define CAN_F1R2_FB0_Pos (0U)
4290#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4291#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4292#define CAN_F1R2_FB1_Pos (1U)
4293#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4294#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4295#define CAN_F1R2_FB2_Pos (2U)
4296#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4297#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4298#define CAN_F1R2_FB3_Pos (3U)
4299#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4300#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4301#define CAN_F1R2_FB4_Pos (4U)
4302#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4303#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4304#define CAN_F1R2_FB5_Pos (5U)
4305#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4306#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4307#define CAN_F1R2_FB6_Pos (6U)
4308#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4309#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4310#define CAN_F1R2_FB7_Pos (7U)
4311#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4312#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4313#define CAN_F1R2_FB8_Pos (8U)
4314#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4315#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4316#define CAN_F1R2_FB9_Pos (9U)
4317#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4318#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4319#define CAN_F1R2_FB10_Pos (10U)
4320#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4321#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4322#define CAN_F1R2_FB11_Pos (11U)
4323#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4324#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4325#define CAN_F1R2_FB12_Pos (12U)
4326#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4327#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4328#define CAN_F1R2_FB13_Pos (13U)
4329#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4330#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4331#define CAN_F1R2_FB14_Pos (14U)
4332#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4333#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4334#define CAN_F1R2_FB15_Pos (15U)
4335#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4336#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4337#define CAN_F1R2_FB16_Pos (16U)
4338#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4339#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4340#define CAN_F1R2_FB17_Pos (17U)
4341#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4342#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4343#define CAN_F1R2_FB18_Pos (18U)
4344#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4345#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4346#define CAN_F1R2_FB19_Pos (19U)
4347#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4348#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4349#define CAN_F1R2_FB20_Pos (20U)
4350#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4351#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4352#define CAN_F1R2_FB21_Pos (21U)
4353#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4354#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4355#define CAN_F1R2_FB22_Pos (22U)
4356#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4357#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4358#define CAN_F1R2_FB23_Pos (23U)
4359#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4360#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4361#define CAN_F1R2_FB24_Pos (24U)
4362#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4363#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4364#define CAN_F1R2_FB25_Pos (25U)
4365#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4366#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4367#define CAN_F1R2_FB26_Pos (26U)
4368#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4369#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4370#define CAN_F1R2_FB27_Pos (27U)
4371#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4372#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4373#define CAN_F1R2_FB28_Pos (28U)
4374#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4375#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4376#define CAN_F1R2_FB29_Pos (29U)
4377#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4378#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4379#define CAN_F1R2_FB30_Pos (30U)
4380#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4381#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4382#define CAN_F1R2_FB31_Pos (31U)
4383#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4384#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4386/******************* Bit definition for CAN_F2R2 register *******************/
4387#define CAN_F2R2_FB0_Pos (0U)
4388#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4389#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4390#define CAN_F2R2_FB1_Pos (1U)
4391#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4392#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4393#define CAN_F2R2_FB2_Pos (2U)
4394#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4395#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4396#define CAN_F2R2_FB3_Pos (3U)
4397#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4398#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4399#define CAN_F2R2_FB4_Pos (4U)
4400#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4401#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4402#define CAN_F2R2_FB5_Pos (5U)
4403#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4404#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4405#define CAN_F2R2_FB6_Pos (6U)
4406#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4407#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4408#define CAN_F2R2_FB7_Pos (7U)
4409#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4410#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4411#define CAN_F2R2_FB8_Pos (8U)
4412#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4413#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4414#define CAN_F2R2_FB9_Pos (9U)
4415#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4416#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4417#define CAN_F2R2_FB10_Pos (10U)
4418#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4419#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4420#define CAN_F2R2_FB11_Pos (11U)
4421#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4422#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4423#define CAN_F2R2_FB12_Pos (12U)
4424#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4425#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4426#define CAN_F2R2_FB13_Pos (13U)
4427#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4428#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4429#define CAN_F2R2_FB14_Pos (14U)
4430#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4431#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4432#define CAN_F2R2_FB15_Pos (15U)
4433#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4434#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4435#define CAN_F2R2_FB16_Pos (16U)
4436#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4437#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4438#define CAN_F2R2_FB17_Pos (17U)
4439#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4440#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4441#define CAN_F2R2_FB18_Pos (18U)
4442#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4443#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4444#define CAN_F2R2_FB19_Pos (19U)
4445#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4446#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4447#define CAN_F2R2_FB20_Pos (20U)
4448#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4449#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4450#define CAN_F2R2_FB21_Pos (21U)
4451#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4452#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4453#define CAN_F2R2_FB22_Pos (22U)
4454#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4455#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4456#define CAN_F2R2_FB23_Pos (23U)
4457#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4458#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4459#define CAN_F2R2_FB24_Pos (24U)
4460#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4461#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4462#define CAN_F2R2_FB25_Pos (25U)
4463#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4464#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4465#define CAN_F2R2_FB26_Pos (26U)
4466#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4467#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4468#define CAN_F2R2_FB27_Pos (27U)
4469#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4470#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4471#define CAN_F2R2_FB28_Pos (28U)
4472#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4473#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4474#define CAN_F2R2_FB29_Pos (29U)
4475#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4476#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4477#define CAN_F2R2_FB30_Pos (30U)
4478#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4479#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4480#define CAN_F2R2_FB31_Pos (31U)
4481#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4482#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4484/******************* Bit definition for CAN_F3R2 register *******************/
4485#define CAN_F3R2_FB0_Pos (0U)
4486#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4487#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4488#define CAN_F3R2_FB1_Pos (1U)
4489#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4490#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4491#define CAN_F3R2_FB2_Pos (2U)
4492#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4493#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4494#define CAN_F3R2_FB3_Pos (3U)
4495#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4496#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4497#define CAN_F3R2_FB4_Pos (4U)
4498#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4499#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4500#define CAN_F3R2_FB5_Pos (5U)
4501#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4502#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4503#define CAN_F3R2_FB6_Pos (6U)
4504#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4505#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4506#define CAN_F3R2_FB7_Pos (7U)
4507#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4508#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4509#define CAN_F3R2_FB8_Pos (8U)
4510#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4511#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4512#define CAN_F3R2_FB9_Pos (9U)
4513#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4514#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4515#define CAN_F3R2_FB10_Pos (10U)
4516#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4517#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4518#define CAN_F3R2_FB11_Pos (11U)
4519#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4520#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4521#define CAN_F3R2_FB12_Pos (12U)
4522#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4523#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4524#define CAN_F3R2_FB13_Pos (13U)
4525#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4526#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4527#define CAN_F3R2_FB14_Pos (14U)
4528#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4529#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4530#define CAN_F3R2_FB15_Pos (15U)
4531#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4532#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4533#define CAN_F3R2_FB16_Pos (16U)
4534#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4535#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4536#define CAN_F3R2_FB17_Pos (17U)
4537#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4538#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4539#define CAN_F3R2_FB18_Pos (18U)
4540#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4541#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4542#define CAN_F3R2_FB19_Pos (19U)
4543#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4544#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4545#define CAN_F3R2_FB20_Pos (20U)
4546#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4547#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4548#define CAN_F3R2_FB21_Pos (21U)
4549#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4550#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4551#define CAN_F3R2_FB22_Pos (22U)
4552#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4553#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4554#define CAN_F3R2_FB23_Pos (23U)
4555#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4556#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4557#define CAN_F3R2_FB24_Pos (24U)
4558#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4559#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4560#define CAN_F3R2_FB25_Pos (25U)
4561#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4562#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4563#define CAN_F3R2_FB26_Pos (26U)
4564#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4565#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4566#define CAN_F3R2_FB27_Pos (27U)
4567#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4568#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4569#define CAN_F3R2_FB28_Pos (28U)
4570#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4571#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4572#define CAN_F3R2_FB29_Pos (29U)
4573#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4574#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4575#define CAN_F3R2_FB30_Pos (30U)
4576#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4577#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4578#define CAN_F3R2_FB31_Pos (31U)
4579#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4580#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4582/******************* Bit definition for CAN_F4R2 register *******************/
4583#define CAN_F4R2_FB0_Pos (0U)
4584#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4585#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4586#define CAN_F4R2_FB1_Pos (1U)
4587#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4588#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4589#define CAN_F4R2_FB2_Pos (2U)
4590#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4591#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4592#define CAN_F4R2_FB3_Pos (3U)
4593#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4594#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4595#define CAN_F4R2_FB4_Pos (4U)
4596#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4597#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4598#define CAN_F4R2_FB5_Pos (5U)
4599#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4600#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4601#define CAN_F4R2_FB6_Pos (6U)
4602#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4603#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4604#define CAN_F4R2_FB7_Pos (7U)
4605#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4606#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4607#define CAN_F4R2_FB8_Pos (8U)
4608#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4609#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4610#define CAN_F4R2_FB9_Pos (9U)
4611#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4612#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4613#define CAN_F4R2_FB10_Pos (10U)
4614#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4615#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4616#define CAN_F4R2_FB11_Pos (11U)
4617#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4618#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4619#define CAN_F4R2_FB12_Pos (12U)
4620#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4621#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4622#define CAN_F4R2_FB13_Pos (13U)
4623#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4624#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4625#define CAN_F4R2_FB14_Pos (14U)
4626#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4627#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4628#define CAN_F4R2_FB15_Pos (15U)
4629#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4630#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4631#define CAN_F4R2_FB16_Pos (16U)
4632#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4633#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4634#define CAN_F4R2_FB17_Pos (17U)
4635#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4636#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4637#define CAN_F4R2_FB18_Pos (18U)
4638#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4639#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4640#define CAN_F4R2_FB19_Pos (19U)
4641#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4642#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4643#define CAN_F4R2_FB20_Pos (20U)
4644#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4645#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4646#define CAN_F4R2_FB21_Pos (21U)
4647#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4648#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4649#define CAN_F4R2_FB22_Pos (22U)
4650#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4651#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4652#define CAN_F4R2_FB23_Pos (23U)
4653#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4654#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4655#define CAN_F4R2_FB24_Pos (24U)
4656#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4657#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4658#define CAN_F4R2_FB25_Pos (25U)
4659#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4660#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4661#define CAN_F4R2_FB26_Pos (26U)
4662#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4663#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4664#define CAN_F4R2_FB27_Pos (27U)
4665#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4666#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4667#define CAN_F4R2_FB28_Pos (28U)
4668#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4669#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4670#define CAN_F4R2_FB29_Pos (29U)
4671#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4672#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4673#define CAN_F4R2_FB30_Pos (30U)
4674#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4675#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4676#define CAN_F4R2_FB31_Pos (31U)
4677#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4678#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4680/******************* Bit definition for CAN_F5R2 register *******************/
4681#define CAN_F5R2_FB0_Pos (0U)
4682#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4683#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4684#define CAN_F5R2_FB1_Pos (1U)
4685#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4686#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4687#define CAN_F5R2_FB2_Pos (2U)
4688#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4689#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4690#define CAN_F5R2_FB3_Pos (3U)
4691#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4692#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4693#define CAN_F5R2_FB4_Pos (4U)
4694#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4695#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4696#define CAN_F5R2_FB5_Pos (5U)
4697#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4698#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4699#define CAN_F5R2_FB6_Pos (6U)
4700#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4701#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4702#define CAN_F5R2_FB7_Pos (7U)
4703#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4704#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4705#define CAN_F5R2_FB8_Pos (8U)
4706#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4707#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4708#define CAN_F5R2_FB9_Pos (9U)
4709#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4710#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4711#define CAN_F5R2_FB10_Pos (10U)
4712#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4713#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4714#define CAN_F5R2_FB11_Pos (11U)
4715#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4716#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4717#define CAN_F5R2_FB12_Pos (12U)
4718#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4719#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4720#define CAN_F5R2_FB13_Pos (13U)
4721#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4722#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4723#define CAN_F5R2_FB14_Pos (14U)
4724#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4725#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4726#define CAN_F5R2_FB15_Pos (15U)
4727#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4728#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4729#define CAN_F5R2_FB16_Pos (16U)
4730#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4731#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4732#define CAN_F5R2_FB17_Pos (17U)
4733#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4734#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4735#define CAN_F5R2_FB18_Pos (18U)
4736#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4737#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4738#define CAN_F5R2_FB19_Pos (19U)
4739#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4740#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4741#define CAN_F5R2_FB20_Pos (20U)
4742#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4743#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4744#define CAN_F5R2_FB21_Pos (21U)
4745#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4746#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4747#define CAN_F5R2_FB22_Pos (22U)
4748#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4749#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4750#define CAN_F5R2_FB23_Pos (23U)
4751#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4752#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4753#define CAN_F5R2_FB24_Pos (24U)
4754#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4755#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4756#define CAN_F5R2_FB25_Pos (25U)
4757#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4758#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4759#define CAN_F5R2_FB26_Pos (26U)
4760#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4761#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4762#define CAN_F5R2_FB27_Pos (27U)
4763#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4764#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4765#define CAN_F5R2_FB28_Pos (28U)
4766#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4767#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4768#define CAN_F5R2_FB29_Pos (29U)
4769#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4770#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4771#define CAN_F5R2_FB30_Pos (30U)
4772#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4773#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4774#define CAN_F5R2_FB31_Pos (31U)
4775#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4776#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4778/******************* Bit definition for CAN_F6R2 register *******************/
4779#define CAN_F6R2_FB0_Pos (0U)
4780#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4781#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4782#define CAN_F6R2_FB1_Pos (1U)
4783#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4784#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4785#define CAN_F6R2_FB2_Pos (2U)
4786#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4787#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4788#define CAN_F6R2_FB3_Pos (3U)
4789#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4790#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4791#define CAN_F6R2_FB4_Pos (4U)
4792#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4793#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4794#define CAN_F6R2_FB5_Pos (5U)
4795#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4796#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4797#define CAN_F6R2_FB6_Pos (6U)
4798#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4799#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4800#define CAN_F6R2_FB7_Pos (7U)
4801#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4802#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4803#define CAN_F6R2_FB8_Pos (8U)
4804#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4805#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4806#define CAN_F6R2_FB9_Pos (9U)
4807#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4808#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4809#define CAN_F6R2_FB10_Pos (10U)
4810#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4811#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4812#define CAN_F6R2_FB11_Pos (11U)
4813#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4814#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4815#define CAN_F6R2_FB12_Pos (12U)
4816#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4817#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4818#define CAN_F6R2_FB13_Pos (13U)
4819#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4820#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4821#define CAN_F6R2_FB14_Pos (14U)
4822#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4823#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4824#define CAN_F6R2_FB15_Pos (15U)
4825#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4826#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4827#define CAN_F6R2_FB16_Pos (16U)
4828#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4829#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4830#define CAN_F6R2_FB17_Pos (17U)
4831#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4832#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4833#define CAN_F6R2_FB18_Pos (18U)
4834#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4835#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4836#define CAN_F6R2_FB19_Pos (19U)
4837#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4838#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4839#define CAN_F6R2_FB20_Pos (20U)
4840#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4841#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4842#define CAN_F6R2_FB21_Pos (21U)
4843#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4844#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4845#define CAN_F6R2_FB22_Pos (22U)
4846#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4847#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4848#define CAN_F6R2_FB23_Pos (23U)
4849#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4850#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4851#define CAN_F6R2_FB24_Pos (24U)
4852#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4853#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4854#define CAN_F6R2_FB25_Pos (25U)
4855#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4856#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4857#define CAN_F6R2_FB26_Pos (26U)
4858#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4859#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4860#define CAN_F6R2_FB27_Pos (27U)
4861#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4862#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4863#define CAN_F6R2_FB28_Pos (28U)
4864#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4865#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4866#define CAN_F6R2_FB29_Pos (29U)
4867#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4868#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4869#define CAN_F6R2_FB30_Pos (30U)
4870#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4871#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4872#define CAN_F6R2_FB31_Pos (31U)
4873#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4874#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4876/******************* Bit definition for CAN_F7R2 register *******************/
4877#define CAN_F7R2_FB0_Pos (0U)
4878#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4879#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4880#define CAN_F7R2_FB1_Pos (1U)
4881#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4882#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4883#define CAN_F7R2_FB2_Pos (2U)
4884#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4885#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4886#define CAN_F7R2_FB3_Pos (3U)
4887#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4888#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4889#define CAN_F7R2_FB4_Pos (4U)
4890#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4891#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4892#define CAN_F7R2_FB5_Pos (5U)
4893#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4894#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4895#define CAN_F7R2_FB6_Pos (6U)
4896#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4897#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4898#define CAN_F7R2_FB7_Pos (7U)
4899#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4900#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4901#define CAN_F7R2_FB8_Pos (8U)
4902#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4903#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4904#define CAN_F7R2_FB9_Pos (9U)
4905#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4906#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4907#define CAN_F7R2_FB10_Pos (10U)
4908#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4909#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4910#define CAN_F7R2_FB11_Pos (11U)
4911#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4912#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4913#define CAN_F7R2_FB12_Pos (12U)
4914#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4915#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4916#define CAN_F7R2_FB13_Pos (13U)
4917#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4918#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4919#define CAN_F7R2_FB14_Pos (14U)
4920#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4921#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4922#define CAN_F7R2_FB15_Pos (15U)
4923#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4924#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4925#define CAN_F7R2_FB16_Pos (16U)
4926#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4927#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4928#define CAN_F7R2_FB17_Pos (17U)
4929#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4930#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4931#define CAN_F7R2_FB18_Pos (18U)
4932#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4933#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4934#define CAN_F7R2_FB19_Pos (19U)
4935#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4936#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4937#define CAN_F7R2_FB20_Pos (20U)
4938#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4939#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4940#define CAN_F7R2_FB21_Pos (21U)
4941#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4942#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4943#define CAN_F7R2_FB22_Pos (22U)
4944#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4945#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4946#define CAN_F7R2_FB23_Pos (23U)
4947#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4948#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4949#define CAN_F7R2_FB24_Pos (24U)
4950#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4951#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4952#define CAN_F7R2_FB25_Pos (25U)
4953#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4954#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4955#define CAN_F7R2_FB26_Pos (26U)
4956#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4957#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4958#define CAN_F7R2_FB27_Pos (27U)
4959#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4960#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4961#define CAN_F7R2_FB28_Pos (28U)
4962#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4963#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4964#define CAN_F7R2_FB29_Pos (29U)
4965#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4966#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4967#define CAN_F7R2_FB30_Pos (30U)
4968#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4969#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4970#define CAN_F7R2_FB31_Pos (31U)
4971#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4972#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4974/******************* Bit definition for CAN_F8R2 register *******************/
4975#define CAN_F8R2_FB0_Pos (0U)
4976#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4977#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4978#define CAN_F8R2_FB1_Pos (1U)
4979#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4980#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4981#define CAN_F8R2_FB2_Pos (2U)
4982#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4983#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4984#define CAN_F8R2_FB3_Pos (3U)
4985#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4986#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4987#define CAN_F8R2_FB4_Pos (4U)
4988#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4989#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4990#define CAN_F8R2_FB5_Pos (5U)
4991#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4992#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4993#define CAN_F8R2_FB6_Pos (6U)
4994#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4995#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4996#define CAN_F8R2_FB7_Pos (7U)
4997#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4998#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4999#define CAN_F8R2_FB8_Pos (8U)
5000#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5001#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5002#define CAN_F8R2_FB9_Pos (9U)
5003#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5004#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5005#define CAN_F8R2_FB10_Pos (10U)
5006#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5007#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5008#define CAN_F8R2_FB11_Pos (11U)
5009#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5010#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5011#define CAN_F8R2_FB12_Pos (12U)
5012#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5013#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5014#define CAN_F8R2_FB13_Pos (13U)
5015#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
5016#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
5017#define CAN_F8R2_FB14_Pos (14U)
5018#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
5019#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
5020#define CAN_F8R2_FB15_Pos (15U)
5021#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
5022#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
5023#define CAN_F8R2_FB16_Pos (16U)
5024#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
5025#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
5026#define CAN_F8R2_FB17_Pos (17U)
5027#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
5028#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
5029#define CAN_F8R2_FB18_Pos (18U)
5030#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
5031#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
5032#define CAN_F8R2_FB19_Pos (19U)
5033#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
5034#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
5035#define CAN_F8R2_FB20_Pos (20U)
5036#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
5037#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
5038#define CAN_F8R2_FB21_Pos (21U)
5039#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
5040#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
5041#define CAN_F8R2_FB22_Pos (22U)
5042#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
5043#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
5044#define CAN_F8R2_FB23_Pos (23U)
5045#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
5046#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
5047#define CAN_F8R2_FB24_Pos (24U)
5048#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
5049#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
5050#define CAN_F8R2_FB25_Pos (25U)
5051#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
5052#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
5053#define CAN_F8R2_FB26_Pos (26U)
5054#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
5055#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
5056#define CAN_F8R2_FB27_Pos (27U)
5057#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
5058#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
5059#define CAN_F8R2_FB28_Pos (28U)
5060#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
5061#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
5062#define CAN_F8R2_FB29_Pos (29U)
5063#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
5064#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
5065#define CAN_F8R2_FB30_Pos (30U)
5066#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
5067#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
5068#define CAN_F8R2_FB31_Pos (31U)
5069#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
5070#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
5072/******************* Bit definition for CAN_F9R2 register *******************/
5073#define CAN_F9R2_FB0_Pos (0U)
5074#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
5075#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
5076#define CAN_F9R2_FB1_Pos (1U)
5077#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
5078#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
5079#define CAN_F9R2_FB2_Pos (2U)
5080#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
5081#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
5082#define CAN_F9R2_FB3_Pos (3U)
5083#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
5084#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
5085#define CAN_F9R2_FB4_Pos (4U)
5086#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
5087#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
5088#define CAN_F9R2_FB5_Pos (5U)
5089#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
5090#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
5091#define CAN_F9R2_FB6_Pos (6U)
5092#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
5093#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
5094#define CAN_F9R2_FB7_Pos (7U)
5095#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
5096#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
5097#define CAN_F9R2_FB8_Pos (8U)
5098#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5099#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5100#define CAN_F9R2_FB9_Pos (9U)
5101#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5102#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5103#define CAN_F9R2_FB10_Pos (10U)
5104#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5105#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5106#define CAN_F9R2_FB11_Pos (11U)
5107#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5108#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5109#define CAN_F9R2_FB12_Pos (12U)
5110#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5111#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5112#define CAN_F9R2_FB13_Pos (13U)
5113#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5114#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5115#define CAN_F9R2_FB14_Pos (14U)
5116#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5117#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5118#define CAN_F9R2_FB15_Pos (15U)
5119#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5120#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5121#define CAN_F9R2_FB16_Pos (16U)
5122#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5123#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5124#define CAN_F9R2_FB17_Pos (17U)
5125#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5126#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5127#define CAN_F9R2_FB18_Pos (18U)
5128#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5129#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5130#define CAN_F9R2_FB19_Pos (19U)
5131#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5132#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5133#define CAN_F9R2_FB20_Pos (20U)
5134#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5135#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5136#define CAN_F9R2_FB21_Pos (21U)
5137#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5138#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5139#define CAN_F9R2_FB22_Pos (22U)
5140#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5141#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5142#define CAN_F9R2_FB23_Pos (23U)
5143#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5144#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5145#define CAN_F9R2_FB24_Pos (24U)
5146#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5147#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5148#define CAN_F9R2_FB25_Pos (25U)
5149#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5150#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5151#define CAN_F9R2_FB26_Pos (26U)
5152#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5153#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5154#define CAN_F9R2_FB27_Pos (27U)
5155#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5156#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5157#define CAN_F9R2_FB28_Pos (28U)
5158#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5159#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5160#define CAN_F9R2_FB29_Pos (29U)
5161#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5162#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5163#define CAN_F9R2_FB30_Pos (30U)
5164#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5165#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5166#define CAN_F9R2_FB31_Pos (31U)
5167#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5168#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5170/******************* Bit definition for CAN_F10R2 register ******************/
5171#define CAN_F10R2_FB0_Pos (0U)
5172#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5173#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5174#define CAN_F10R2_FB1_Pos (1U)
5175#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5176#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5177#define CAN_F10R2_FB2_Pos (2U)
5178#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5179#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5180#define CAN_F10R2_FB3_Pos (3U)
5181#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5182#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5183#define CAN_F10R2_FB4_Pos (4U)
5184#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5185#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5186#define CAN_F10R2_FB5_Pos (5U)
5187#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5188#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5189#define CAN_F10R2_FB6_Pos (6U)
5190#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5191#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5192#define CAN_F10R2_FB7_Pos (7U)
5193#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5194#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5195#define CAN_F10R2_FB8_Pos (8U)
5196#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5197#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5198#define CAN_F10R2_FB9_Pos (9U)
5199#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5200#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5201#define CAN_F10R2_FB10_Pos (10U)
5202#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5203#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5204#define CAN_F10R2_FB11_Pos (11U)
5205#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5206#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5207#define CAN_F10R2_FB12_Pos (12U)
5208#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5209#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5210#define CAN_F10R2_FB13_Pos (13U)
5211#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5212#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5213#define CAN_F10R2_FB14_Pos (14U)
5214#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5215#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5216#define CAN_F10R2_FB15_Pos (15U)
5217#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5218#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5219#define CAN_F10R2_FB16_Pos (16U)
5220#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5221#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5222#define CAN_F10R2_FB17_Pos (17U)
5223#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5224#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5225#define CAN_F10R2_FB18_Pos (18U)
5226#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5227#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5228#define CAN_F10R2_FB19_Pos (19U)
5229#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5230#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5231#define CAN_F10R2_FB20_Pos (20U)
5232#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5233#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5234#define CAN_F10R2_FB21_Pos (21U)
5235#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5236#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5237#define CAN_F10R2_FB22_Pos (22U)
5238#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5239#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5240#define CAN_F10R2_FB23_Pos (23U)
5241#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5242#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5243#define CAN_F10R2_FB24_Pos (24U)
5244#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5245#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5246#define CAN_F10R2_FB25_Pos (25U)
5247#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5248#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5249#define CAN_F10R2_FB26_Pos (26U)
5250#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5251#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5252#define CAN_F10R2_FB27_Pos (27U)
5253#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5254#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5255#define CAN_F10R2_FB28_Pos (28U)
5256#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5257#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5258#define CAN_F10R2_FB29_Pos (29U)
5259#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5260#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5261#define CAN_F10R2_FB30_Pos (30U)
5262#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5263#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5264#define CAN_F10R2_FB31_Pos (31U)
5265#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5266#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5268/******************* Bit definition for CAN_F11R2 register ******************/
5269#define CAN_F11R2_FB0_Pos (0U)
5270#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5271#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5272#define CAN_F11R2_FB1_Pos (1U)
5273#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5274#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5275#define CAN_F11R2_FB2_Pos (2U)
5276#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5277#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5278#define CAN_F11R2_FB3_Pos (3U)
5279#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5280#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5281#define CAN_F11R2_FB4_Pos (4U)
5282#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5283#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5284#define CAN_F11R2_FB5_Pos (5U)
5285#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5286#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5287#define CAN_F11R2_FB6_Pos (6U)
5288#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5289#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5290#define CAN_F11R2_FB7_Pos (7U)
5291#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5292#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5293#define CAN_F11R2_FB8_Pos (8U)
5294#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5295#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5296#define CAN_F11R2_FB9_Pos (9U)
5297#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5298#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5299#define CAN_F11R2_FB10_Pos (10U)
5300#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5301#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5302#define CAN_F11R2_FB11_Pos (11U)
5303#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5304#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5305#define CAN_F11R2_FB12_Pos (12U)
5306#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5307#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5308#define CAN_F11R2_FB13_Pos (13U)
5309#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5310#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5311#define CAN_F11R2_FB14_Pos (14U)
5312#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5313#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5314#define CAN_F11R2_FB15_Pos (15U)
5315#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5316#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5317#define CAN_F11R2_FB16_Pos (16U)
5318#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5319#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5320#define CAN_F11R2_FB17_Pos (17U)
5321#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5322#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5323#define CAN_F11R2_FB18_Pos (18U)
5324#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5325#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5326#define CAN_F11R2_FB19_Pos (19U)
5327#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5328#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5329#define CAN_F11R2_FB20_Pos (20U)
5330#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5331#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5332#define CAN_F11R2_FB21_Pos (21U)
5333#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5334#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5335#define CAN_F11R2_FB22_Pos (22U)
5336#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5337#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5338#define CAN_F11R2_FB23_Pos (23U)
5339#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5340#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5341#define CAN_F11R2_FB24_Pos (24U)
5342#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5343#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5344#define CAN_F11R2_FB25_Pos (25U)
5345#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5346#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5347#define CAN_F11R2_FB26_Pos (26U)
5348#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5349#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5350#define CAN_F11R2_FB27_Pos (27U)
5351#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5352#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5353#define CAN_F11R2_FB28_Pos (28U)
5354#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5355#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5356#define CAN_F11R2_FB29_Pos (29U)
5357#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5358#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5359#define CAN_F11R2_FB30_Pos (30U)
5360#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5361#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5362#define CAN_F11R2_FB31_Pos (31U)
5363#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5364#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5366/******************* Bit definition for CAN_F12R2 register ******************/
5367#define CAN_F12R2_FB0_Pos (0U)
5368#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5369#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5370#define CAN_F12R2_FB1_Pos (1U)
5371#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5372#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5373#define CAN_F12R2_FB2_Pos (2U)
5374#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5375#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5376#define CAN_F12R2_FB3_Pos (3U)
5377#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5378#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5379#define CAN_F12R2_FB4_Pos (4U)
5380#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5381#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5382#define CAN_F12R2_FB5_Pos (5U)
5383#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5384#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5385#define CAN_F12R2_FB6_Pos (6U)
5386#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5387#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5388#define CAN_F12R2_FB7_Pos (7U)
5389#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5390#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5391#define CAN_F12R2_FB8_Pos (8U)
5392#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5393#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5394#define CAN_F12R2_FB9_Pos (9U)
5395#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5396#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5397#define CAN_F12R2_FB10_Pos (10U)
5398#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5399#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5400#define CAN_F12R2_FB11_Pos (11U)
5401#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5402#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5403#define CAN_F12R2_FB12_Pos (12U)
5404#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5405#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5406#define CAN_F12R2_FB13_Pos (13U)
5407#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5408#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5409#define CAN_F12R2_FB14_Pos (14U)
5410#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5411#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5412#define CAN_F12R2_FB15_Pos (15U)
5413#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5414#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5415#define CAN_F12R2_FB16_Pos (16U)
5416#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5417#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5418#define CAN_F12R2_FB17_Pos (17U)
5419#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5420#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5421#define CAN_F12R2_FB18_Pos (18U)
5422#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5423#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5424#define CAN_F12R2_FB19_Pos (19U)
5425#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5426#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5427#define CAN_F12R2_FB20_Pos (20U)
5428#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5429#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5430#define CAN_F12R2_FB21_Pos (21U)
5431#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5432#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5433#define CAN_F12R2_FB22_Pos (22U)
5434#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5435#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5436#define CAN_F12R2_FB23_Pos (23U)
5437#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5438#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5439#define CAN_F12R2_FB24_Pos (24U)
5440#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5441#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5442#define CAN_F12R2_FB25_Pos (25U)
5443#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5444#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5445#define CAN_F12R2_FB26_Pos (26U)
5446#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5447#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5448#define CAN_F12R2_FB27_Pos (27U)
5449#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5450#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5451#define CAN_F12R2_FB28_Pos (28U)
5452#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5453#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5454#define CAN_F12R2_FB29_Pos (29U)
5455#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5456#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5457#define CAN_F12R2_FB30_Pos (30U)
5458#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5459#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5460#define CAN_F12R2_FB31_Pos (31U)
5461#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5462#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5464/******************* Bit definition for CAN_F13R2 register ******************/
5465#define CAN_F13R2_FB0_Pos (0U)
5466#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5467#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5468#define CAN_F13R2_FB1_Pos (1U)
5469#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5470#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5471#define CAN_F13R2_FB2_Pos (2U)
5472#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5473#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5474#define CAN_F13R2_FB3_Pos (3U)
5475#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5476#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5477#define CAN_F13R2_FB4_Pos (4U)
5478#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5479#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5480#define CAN_F13R2_FB5_Pos (5U)
5481#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5482#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5483#define CAN_F13R2_FB6_Pos (6U)
5484#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5485#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5486#define CAN_F13R2_FB7_Pos (7U)
5487#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5488#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5489#define CAN_F13R2_FB8_Pos (8U)
5490#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5491#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5492#define CAN_F13R2_FB9_Pos (9U)
5493#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5494#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5495#define CAN_F13R2_FB10_Pos (10U)
5496#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5497#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5498#define CAN_F13R2_FB11_Pos (11U)
5499#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5500#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5501#define CAN_F13R2_FB12_Pos (12U)
5502#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5503#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5504#define CAN_F13R2_FB13_Pos (13U)
5505#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5506#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5507#define CAN_F13R2_FB14_Pos (14U)
5508#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5509#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5510#define CAN_F13R2_FB15_Pos (15U)
5511#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5512#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5513#define CAN_F13R2_FB16_Pos (16U)
5514#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5515#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5516#define CAN_F13R2_FB17_Pos (17U)
5517#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5518#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5519#define CAN_F13R2_FB18_Pos (18U)
5520#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5521#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5522#define CAN_F13R2_FB19_Pos (19U)
5523#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5524#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5525#define CAN_F13R2_FB20_Pos (20U)
5526#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5527#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5528#define CAN_F13R2_FB21_Pos (21U)
5529#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5530#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5531#define CAN_F13R2_FB22_Pos (22U)
5532#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5533#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5534#define CAN_F13R2_FB23_Pos (23U)
5535#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5536#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5537#define CAN_F13R2_FB24_Pos (24U)
5538#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5539#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5540#define CAN_F13R2_FB25_Pos (25U)
5541#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5542#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5543#define CAN_F13R2_FB26_Pos (26U)
5544#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5545#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5546#define CAN_F13R2_FB27_Pos (27U)
5547#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5548#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5549#define CAN_F13R2_FB28_Pos (28U)
5550#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5551#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5552#define CAN_F13R2_FB29_Pos (29U)
5553#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5554#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5555#define CAN_F13R2_FB30_Pos (30U)
5556#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5557#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5558#define CAN_F13R2_FB31_Pos (31U)
5559#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5560#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5562/******************************************************************************/
5563/* */
5564/* HDMI-CEC (CEC) */
5565/* */
5566/******************************************************************************/
5567
5568/******************* Bit definition for CEC_CR register *********************/
5569#define CEC_CR_CECEN_Pos (0U)
5570#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos)
5571#define CEC_CR_CECEN CEC_CR_CECEN_Msk
5572#define CEC_CR_TXSOM_Pos (1U)
5573#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos)
5574#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk
5575#define CEC_CR_TXEOM_Pos (2U)
5576#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos)
5577#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk
5579/******************* Bit definition for CEC_CFGR register *******************/
5580#define CEC_CFGR_SFT_Pos (0U)
5581#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos)
5582#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk
5583#define CEC_CFGR_RXTOL_Pos (3U)
5584#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos)
5585#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk
5586#define CEC_CFGR_BRESTP_Pos (4U)
5587#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos)
5588#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk
5589#define CEC_CFGR_BREGEN_Pos (5U)
5590#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos)
5591#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk
5592#define CEC_CFGR_LBPEGEN_Pos (6U)
5593#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos)
5594#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk
5595#define CEC_CFGR_BRDNOGEN_Pos (7U)
5596#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
5597#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk
5598#define CEC_CFGR_SFTOPT_Pos (8U)
5599#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos)
5600#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk
5601#define CEC_CFGR_OAR_Pos (16U)
5602#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos)
5603#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk
5604#define CEC_CFGR_LSTN_Pos (31U)
5605#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos)
5606#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk
5608/******************* Bit definition for CEC_TXDR register *******************/
5609#define CEC_TXDR_TXD_Pos (0U)
5610#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos)
5611#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk
5613/******************* Bit definition for CEC_RXDR register *******************/
5614#define CEC_RXDR_RXD_Pos (0U)
5615#define CEC_RXDR_RXD_Msk (0xFFU << CEC_RXDR_RXD_Pos)
5616#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk
5618/******************* Bit definition for CEC_ISR register ********************/
5619#define CEC_ISR_RXBR_Pos (0U)
5620#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos)
5621#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk
5622#define CEC_ISR_RXEND_Pos (1U)
5623#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos)
5624#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk
5625#define CEC_ISR_RXOVR_Pos (2U)
5626#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
5627#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk
5628#define CEC_ISR_BRE_Pos (3U)
5629#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos)
5630#define CEC_ISR_BRE CEC_ISR_BRE_Msk
5631#define CEC_ISR_SBPE_Pos (4U)
5632#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos)
5633#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk
5634#define CEC_ISR_LBPE_Pos (5U)
5635#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos)
5636#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk
5637#define CEC_ISR_RXACKE_Pos (6U)
5638#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos)
5639#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk
5640#define CEC_ISR_ARBLST_Pos (7U)
5641#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos)
5642#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk
5643#define CEC_ISR_TXBR_Pos (8U)
5644#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos)
5645#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk
5646#define CEC_ISR_TXEND_Pos (9U)
5647#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos)
5648#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk
5649#define CEC_ISR_TXUDR_Pos (10U)
5650#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos)
5651#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk
5652#define CEC_ISR_TXERR_Pos (11U)
5653#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos)
5654#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk
5655#define CEC_ISR_TXACKE_Pos (12U)
5656#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos)
5657#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk
5659/******************* Bit definition for CEC_IER register ********************/
5660#define CEC_IER_RXBRIE_Pos (0U)
5661#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos)
5662#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk
5663#define CEC_IER_RXENDIE_Pos (1U)
5664#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos)
5665#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk
5666#define CEC_IER_RXOVRIE_Pos (2U)
5667#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos)
5668#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk
5669#define CEC_IER_BREIE_Pos (3U)
5670#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos)
5671#define CEC_IER_BREIE CEC_IER_BREIE_Msk
5672#define CEC_IER_SBPEIE_Pos (4U)
5673#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos)
5674#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk
5675#define CEC_IER_LBPEIE_Pos (5U)
5676#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos)
5677#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk
5678#define CEC_IER_RXACKEIE_Pos (6U)
5679#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos)
5680#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk
5681#define CEC_IER_ARBLSTIE_Pos (7U)
5682#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos)
5683#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk
5684#define CEC_IER_TXBRIE_Pos (8U)
5685#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos)
5686#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk
5687#define CEC_IER_TXENDIE_Pos (9U)
5688#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos)
5689#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk
5690#define CEC_IER_TXUDRIE_Pos (10U)
5691#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos)
5692#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk
5693#define CEC_IER_TXERRIE_Pos (11U)
5694#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos)
5695#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk
5696#define CEC_IER_TXACKEIE_Pos (12U)
5697#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos)
5698#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk
5700/******************************************************************************/
5701/* */
5702/* CRC calculation unit */
5703/* */
5704/******************************************************************************/
5705/******************* Bit definition for CRC_DR register *********************/
5706#define CRC_DR_DR_Pos (0U)
5707#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5708#define CRC_DR_DR CRC_DR_DR_Msk
5710/******************* Bit definition for CRC_IDR register ********************/
5711#define CRC_IDR_IDR_Pos (0U)
5712#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5713#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5715/******************** Bit definition for CRC_CR register ********************/
5716#define CRC_CR_RESET_Pos (0U)
5717#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5718#define CRC_CR_RESET CRC_CR_RESET_Msk
5719#define CRC_CR_POLYSIZE_Pos (3U)
5720#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5721#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5722#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5723#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5724#define CRC_CR_REV_IN_Pos (5U)
5725#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5726#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5727#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5728#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5729#define CRC_CR_REV_OUT_Pos (7U)
5730#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5731#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5733/******************* Bit definition for CRC_INIT register *******************/
5734#define CRC_INIT_INIT_Pos (0U)
5735#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5736#define CRC_INIT_INIT CRC_INIT_INIT_Msk
5738/******************* Bit definition for CRC_POL register ********************/
5739#define CRC_POL_POL_Pos (0U)
5740#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5741#define CRC_POL_POL CRC_POL_POL_Msk
5743/******************************************************************************/
5744/* */
5745/* Crypto Processor */
5746/* */
5747/******************************************************************************/
5748/******************* Bits definition for CRYP_CR register ********************/
5749#define CRYP_CR_ALGODIR_Pos (2U)
5750#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos)
5751#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
5752
5753#define CRYP_CR_ALGOMODE_Pos (3U)
5754#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos)
5755#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
5756#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos)
5757#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos)
5758#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos)
5759#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
5760#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
5761#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos)
5762#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
5763#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
5764#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos)
5765#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
5766#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
5767#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos)
5768#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
5769#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
5770#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)
5771#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
5772#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
5773#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)
5774#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
5775#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
5776#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)
5777#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
5778#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
5779#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)
5780#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
5781#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
5782#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)
5783#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
5784#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
5785#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos)
5786#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
5787
5788#define CRYP_CR_DATATYPE_Pos (6U)
5789#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos)
5790#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
5791#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos)
5792#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos)
5793#define CRYP_CR_KEYSIZE_Pos (8U)
5794#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos)
5795#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
5796#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos)
5797#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos)
5798#define CRYP_CR_FFLUSH_Pos (14U)
5799#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos)
5800#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
5801#define CRYP_CR_CRYPEN_Pos (15U)
5802#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos)
5803#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
5804
5805#define CRYP_CR_GCM_CCMPH_Pos (16U)
5806#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos)
5807#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
5808#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos)
5809#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos)
5810#define CRYP_CR_ALGOMODE_3 0x00080000U
5811
5812/****************** Bits definition for CRYP_SR register *********************/
5813#define CRYP_SR_IFEM_Pos (0U)
5814#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos)
5815#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
5816#define CRYP_SR_IFNF_Pos (1U)
5817#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos)
5818#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
5819#define CRYP_SR_OFNE_Pos (2U)
5820#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos)
5821#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
5822#define CRYP_SR_OFFU_Pos (3U)
5823#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos)
5824#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
5825#define CRYP_SR_BUSY_Pos (4U)
5826#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos)
5827#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
5828/****************** Bits definition for CRYP_DMACR register ******************/
5829#define CRYP_DMACR_DIEN_Pos (0U)
5830#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos)
5831#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
5832#define CRYP_DMACR_DOEN_Pos (1U)
5833#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos)
5834#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
5835/***************** Bits definition for CRYP_IMSCR register ******************/
5836#define CRYP_IMSCR_INIM_Pos (0U)
5837#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos)
5838#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
5839#define CRYP_IMSCR_OUTIM_Pos (1U)
5840#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos)
5841#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
5842/****************** Bits definition for CRYP_RISR register *******************/
5843#define CRYP_RISR_OUTRIS_Pos (0U)
5844#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos)
5845#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
5846#define CRYP_RISR_INRIS_Pos (1U)
5847#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos)
5848#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
5849/****************** Bits definition for CRYP_MISR register *******************/
5850#define CRYP_MISR_INMIS_Pos (0U)
5851#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos)
5852#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
5853#define CRYP_MISR_OUTMIS_Pos (1U)
5854#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos)
5855#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
5856
5857/******************************************************************************/
5858/* */
5859/* Digital to Analog Converter */
5860/* */
5861/******************************************************************************/
5862/******************** Bit definition for DAC_CR register ********************/
5863#define DAC_CR_EN1_Pos (0U)
5864#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5865#define DAC_CR_EN1 DAC_CR_EN1_Msk
5866#define DAC_CR_BOFF1_Pos (1U)
5867#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5868#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5869#define DAC_CR_TEN1_Pos (2U)
5870#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5871#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5872#define DAC_CR_TSEL1_Pos (3U)
5873#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5874#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5875#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5876#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5877#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5878#define DAC_CR_WAVE1_Pos (6U)
5879#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5880#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5881#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5882#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5883#define DAC_CR_MAMP1_Pos (8U)
5884#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5885#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5886#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5887#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5888#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5889#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5890#define DAC_CR_DMAEN1_Pos (12U)
5891#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5892#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5893#define DAC_CR_DMAUDRIE1_Pos (13U)
5894#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5895#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5896#define DAC_CR_EN2_Pos (16U)
5897#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5898#define DAC_CR_EN2 DAC_CR_EN2_Msk
5899#define DAC_CR_BOFF2_Pos (17U)
5900#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5901#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5902#define DAC_CR_TEN2_Pos (18U)
5903#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5904#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5905#define DAC_CR_TSEL2_Pos (19U)
5906#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5907#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5908#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5909#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5910#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5911#define DAC_CR_WAVE2_Pos (22U)
5912#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5913#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5914#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5915#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5916#define DAC_CR_MAMP2_Pos (24U)
5917#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5918#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5919#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5920#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5921#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5922#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5923#define DAC_CR_DMAEN2_Pos (28U)
5924#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5925#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5926#define DAC_CR_DMAUDRIE2_Pos (29U)
5927#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5928#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5930/***************** Bit definition for DAC_SWTRIGR register ******************/
5931#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5932#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5933#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5934#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5935#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5936#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5938/***************** Bit definition for DAC_DHR12R1 register ******************/
5939#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5940#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5941#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5943/***************** Bit definition for DAC_DHR12L1 register ******************/
5944#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5945#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5946#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5948/****************** Bit definition for DAC_DHR8R1 register ******************/
5949#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5950#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5951#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5953/***************** Bit definition for DAC_DHR12R2 register ******************/
5954#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5955#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5956#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5958/***************** Bit definition for DAC_DHR12L2 register ******************/
5959#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5960#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5961#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5963/****************** Bit definition for DAC_DHR8R2 register ******************/
5964#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5965#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5966#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5968/***************** Bit definition for DAC_DHR12RD register ******************/
5969#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5970#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5971#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5972#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5973#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5974#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5976/***************** Bit definition for DAC_DHR12LD register ******************/
5977#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5978#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5979#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5980#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5981#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5982#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5984/****************** Bit definition for DAC_DHR8RD register ******************/
5985#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5986#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5987#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5988#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5989#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5990#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5992/******************* Bit definition for DAC_DOR1 register *******************/
5993#define DAC_DOR1_DACC1DOR_Pos (0U)
5994#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5995#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5997/******************* Bit definition for DAC_DOR2 register *******************/
5998#define DAC_DOR2_DACC2DOR_Pos (0U)
5999#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6000#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6002/******************** Bit definition for DAC_SR register ********************/
6003#define DAC_SR_DMAUDR1_Pos (13U)
6004#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6005#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6006#define DAC_SR_DMAUDR2_Pos (29U)
6007#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6008#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6011/******************************************************************************/
6012/* */
6013/* Debug MCU */
6014/* */
6015/******************************************************************************/
6016
6017/******************************************************************************/
6018/* */
6019/* DCMI */
6020/* */
6021/******************************************************************************/
6022/******************** Bits definition for DCMI_CR register ******************/
6023#define DCMI_CR_CAPTURE_Pos (0U)
6024#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
6025#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6026#define DCMI_CR_CM_Pos (1U)
6027#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
6028#define DCMI_CR_CM DCMI_CR_CM_Msk
6029#define DCMI_CR_CROP_Pos (2U)
6030#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
6031#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6032#define DCMI_CR_JPEG_Pos (3U)
6033#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
6034#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6035#define DCMI_CR_ESS_Pos (4U)
6036#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
6037#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6038#define DCMI_CR_PCKPOL_Pos (5U)
6039#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
6040#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6041#define DCMI_CR_HSPOL_Pos (6U)
6042#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
6043#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6044#define DCMI_CR_VSPOL_Pos (7U)
6045#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
6046#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6047#define DCMI_CR_FCRC_0 0x00000100U
6048#define DCMI_CR_FCRC_1 0x00000200U
6049#define DCMI_CR_EDM_0 0x00000400U
6050#define DCMI_CR_EDM_1 0x00000800U
6051#define DCMI_CR_CRE_Pos (12U)
6052#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
6053#define DCMI_CR_CRE DCMI_CR_CRE_Msk
6054#define DCMI_CR_ENABLE_Pos (14U)
6055#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
6056#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6057#define DCMI_CR_BSM_Pos (16U)
6058#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos)
6059#define DCMI_CR_BSM DCMI_CR_BSM_Msk
6060#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos)
6061#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos)
6062#define DCMI_CR_OEBS_Pos (18U)
6063#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
6064#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6065#define DCMI_CR_LSM_Pos (19U)
6066#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
6067#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6068#define DCMI_CR_OELS_Pos (20U)
6069#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
6070#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6071
6072/******************** Bits definition for DCMI_SR register ******************/
6073#define DCMI_SR_HSYNC_Pos (0U)
6074#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
6075#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6076#define DCMI_SR_VSYNC_Pos (1U)
6077#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
6078#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6079#define DCMI_SR_FNE_Pos (2U)
6080#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
6081#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6082
6083/******************** Bits definition for DCMI_RIS register ****************/
6084#define DCMI_RIS_FRAME_RIS_Pos (0U)
6085#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
6086#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6087#define DCMI_RIS_OVR_RIS_Pos (1U)
6088#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
6089#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6090#define DCMI_RIS_ERR_RIS_Pos (2U)
6091#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
6092#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6093#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6094#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
6095#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6096#define DCMI_RIS_LINE_RIS_Pos (4U)
6097#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
6098#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6099
6100/* Legacy defines */
6101#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
6102#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
6103#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
6104#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
6105#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
6106
6107/******************** Bits definition for DCMI_IER register *****************/
6108#define DCMI_IER_FRAME_IE_Pos (0U)
6109#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
6110#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6111#define DCMI_IER_OVR_IE_Pos (1U)
6112#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
6113#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6114#define DCMI_IER_ERR_IE_Pos (2U)
6115#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
6116#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6117#define DCMI_IER_VSYNC_IE_Pos (3U)
6118#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
6119#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6120#define DCMI_IER_LINE_IE_Pos (4U)
6121#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
6122#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6123
6124/* Legacy define */
6125#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
6126
6127/******************** Bits definition for DCMI_MIS register *****************/
6128#define DCMI_MIS_FRAME_MIS_Pos (0U)
6129#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
6130#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6131#define DCMI_MIS_OVR_MIS_Pos (1U)
6132#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
6133#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6134#define DCMI_MIS_ERR_MIS_Pos (2U)
6135#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
6136#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6137#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6138#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
6139#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6140#define DCMI_MIS_LINE_MIS_Pos (4U)
6141#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
6142#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6143
6144/* Legacy defines */
6145#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
6146#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
6147#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
6148#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
6149#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
6150
6151/******************** Bits definition for DCMI_ICR register *****************/
6152#define DCMI_ICR_FRAME_ISC_Pos (0U)
6153#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
6154#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6155#define DCMI_ICR_OVR_ISC_Pos (1U)
6156#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
6157#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6158#define DCMI_ICR_ERR_ISC_Pos (2U)
6159#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
6160#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6161#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6162#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
6163#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6164#define DCMI_ICR_LINE_ISC_Pos (4U)
6165#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
6166#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6167
6168/* Legacy defines */
6169#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
6170
6171/******************** Bits definition for DCMI_ESCR register ******************/
6172#define DCMI_ESCR_FSC_Pos (0U)
6173#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6174#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6175#define DCMI_ESCR_LSC_Pos (8U)
6176#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6177#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6178#define DCMI_ESCR_LEC_Pos (16U)
6179#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6180#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6181#define DCMI_ESCR_FEC_Pos (24U)
6182#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6183#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6184
6185/******************** Bits definition for DCMI_ESUR register ******************/
6186#define DCMI_ESUR_FSU_Pos (0U)
6187#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6188#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6189#define DCMI_ESUR_LSU_Pos (8U)
6190#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6191#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6192#define DCMI_ESUR_LEU_Pos (16U)
6193#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6194#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6195#define DCMI_ESUR_FEU_Pos (24U)
6196#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6197#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6198
6199/******************** Bits definition for DCMI_CWSTRT register ******************/
6200#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6201#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6202#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6203#define DCMI_CWSTRT_VST_Pos (16U)
6204#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6205#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6206
6207/******************** Bits definition for DCMI_CWSIZE register ******************/
6208#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6209#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6210#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6211#define DCMI_CWSIZE_VLINE_Pos (16U)
6212#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6213#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6214
6215/******************** Bits definition for DCMI_DR register ******************/
6216#define DCMI_DR_BYTE0_Pos (0U)
6217#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6218#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6219#define DCMI_DR_BYTE1_Pos (8U)
6220#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6221#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6222#define DCMI_DR_BYTE2_Pos (16U)
6223#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6224#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6225#define DCMI_DR_BYTE3_Pos (24U)
6226#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6227#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6228
6229/******************************************************************************/
6230/* */
6231/* DMA Controller */
6232/* */
6233/******************************************************************************/
6234/******************** Bits definition for DMA_SxCR register *****************/
6235#define DMA_SxCR_CHSEL_Pos (25U)
6236#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
6237#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6238#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
6239#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
6240#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
6241#define DMA_SxCR_MBURST_Pos (23U)
6242#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
6243#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6244#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
6245#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
6246#define DMA_SxCR_PBURST_Pos (21U)
6247#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
6248#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6249#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
6250#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
6251#define DMA_SxCR_CT_Pos (19U)
6252#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
6253#define DMA_SxCR_CT DMA_SxCR_CT_Msk
6254#define DMA_SxCR_DBM_Pos (18U)
6255#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
6256#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6257#define DMA_SxCR_PL_Pos (16U)
6258#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
6259#define DMA_SxCR_PL DMA_SxCR_PL_Msk
6260#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
6261#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
6262#define DMA_SxCR_PINCOS_Pos (15U)
6263#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
6264#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6265#define DMA_SxCR_MSIZE_Pos (13U)
6266#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
6267#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6268#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
6269#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
6270#define DMA_SxCR_PSIZE_Pos (11U)
6271#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
6272#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6273#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
6274#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
6275#define DMA_SxCR_MINC_Pos (10U)
6276#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
6277#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6278#define DMA_SxCR_PINC_Pos (9U)
6279#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
6280#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6281#define DMA_SxCR_CIRC_Pos (8U)
6282#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
6283#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6284#define DMA_SxCR_DIR_Pos (6U)
6285#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
6286#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6287#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
6288#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
6289#define DMA_SxCR_PFCTRL_Pos (5U)
6290#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
6291#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6292#define DMA_SxCR_TCIE_Pos (4U)
6293#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
6294#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6295#define DMA_SxCR_HTIE_Pos (3U)
6296#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
6297#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6298#define DMA_SxCR_TEIE_Pos (2U)
6299#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
6300#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6301#define DMA_SxCR_DMEIE_Pos (1U)
6302#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
6303#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6304#define DMA_SxCR_EN_Pos (0U)
6305#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6306#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6307
6308/******************** Bits definition for DMA_SxCNDTR register **************/
6309#define DMA_SxNDT_Pos (0U)
6310#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6311#define DMA_SxNDT DMA_SxNDT_Msk
6312#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6313#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6314#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6315#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6316#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6317#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6318#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6319#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6320#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6321#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6322#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6323#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6324#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6325#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6326#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6327#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6329/******************** Bits definition for DMA_SxFCR register ****************/
6330#define DMA_SxFCR_FEIE_Pos (7U)
6331#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6332#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6333#define DMA_SxFCR_FS_Pos (3U)
6334#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6335#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6336#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6337#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6338#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6339#define DMA_SxFCR_DMDIS_Pos (2U)
6340#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6341#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6342#define DMA_SxFCR_FTH_Pos (0U)
6343#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6344#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6345#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6346#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6348/******************** Bits definition for DMA_LISR register *****************/
6349#define DMA_LISR_TCIF3_Pos (27U)
6350#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6351#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6352#define DMA_LISR_HTIF3_Pos (26U)
6353#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6354#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6355#define DMA_LISR_TEIF3_Pos (25U)
6356#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6357#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6358#define DMA_LISR_DMEIF3_Pos (24U)
6359#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6360#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6361#define DMA_LISR_FEIF3_Pos (22U)
6362#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
6363#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6364#define DMA_LISR_TCIF2_Pos (21U)
6365#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
6366#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6367#define DMA_LISR_HTIF2_Pos (20U)
6368#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
6369#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6370#define DMA_LISR_TEIF2_Pos (19U)
6371#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
6372#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6373#define DMA_LISR_DMEIF2_Pos (18U)
6374#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
6375#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6376#define DMA_LISR_FEIF2_Pos (16U)
6377#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
6378#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6379#define DMA_LISR_TCIF1_Pos (11U)
6380#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
6381#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6382#define DMA_LISR_HTIF1_Pos (10U)
6383#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
6384#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6385#define DMA_LISR_TEIF1_Pos (9U)
6386#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
6387#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6388#define DMA_LISR_DMEIF1_Pos (8U)
6389#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
6390#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6391#define DMA_LISR_FEIF1_Pos (6U)
6392#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
6393#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6394#define DMA_LISR_TCIF0_Pos (5U)
6395#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
6396#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6397#define DMA_LISR_HTIF0_Pos (4U)
6398#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
6399#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6400#define DMA_LISR_TEIF0_Pos (3U)
6401#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
6402#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6403#define DMA_LISR_DMEIF0_Pos (2U)
6404#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
6405#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6406#define DMA_LISR_FEIF0_Pos (0U)
6407#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
6408#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6409
6410/******************** Bits definition for DMA_HISR register *****************/
6411#define DMA_HISR_TCIF7_Pos (27U)
6412#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
6413#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6414#define DMA_HISR_HTIF7_Pos (26U)
6415#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
6416#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6417#define DMA_HISR_TEIF7_Pos (25U)
6418#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6419#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6420#define DMA_HISR_DMEIF7_Pos (24U)
6421#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6422#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6423#define DMA_HISR_FEIF7_Pos (22U)
6424#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6425#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6426#define DMA_HISR_TCIF6_Pos (21U)
6427#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6428#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6429#define DMA_HISR_HTIF6_Pos (20U)
6430#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6431#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6432#define DMA_HISR_TEIF6_Pos (19U)
6433#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6434#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6435#define DMA_HISR_DMEIF6_Pos (18U)
6436#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6437#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6438#define DMA_HISR_FEIF6_Pos (16U)
6439#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6440#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6441#define DMA_HISR_TCIF5_Pos (11U)
6442#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6443#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6444#define DMA_HISR_HTIF5_Pos (10U)
6445#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6446#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6447#define DMA_HISR_TEIF5_Pos (9U)
6448#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6449#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6450#define DMA_HISR_DMEIF5_Pos (8U)
6451#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6452#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6453#define DMA_HISR_FEIF5_Pos (6U)
6454#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6455#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6456#define DMA_HISR_TCIF4_Pos (5U)
6457#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6458#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6459#define DMA_HISR_HTIF4_Pos (4U)
6460#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6461#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6462#define DMA_HISR_TEIF4_Pos (3U)
6463#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6464#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6465#define DMA_HISR_DMEIF4_Pos (2U)
6466#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6467#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6468#define DMA_HISR_FEIF4_Pos (0U)
6469#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6470#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6471
6472/******************** Bits definition for DMA_LIFCR register ****************/
6473#define DMA_LIFCR_CTCIF3_Pos (27U)
6474#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6475#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6476#define DMA_LIFCR_CHTIF3_Pos (26U)
6477#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6478#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6479#define DMA_LIFCR_CTEIF3_Pos (25U)
6480#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6481#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6482#define DMA_LIFCR_CDMEIF3_Pos (24U)
6483#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6484#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6485#define DMA_LIFCR_CFEIF3_Pos (22U)
6486#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6487#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6488#define DMA_LIFCR_CTCIF2_Pos (21U)
6489#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6490#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6491#define DMA_LIFCR_CHTIF2_Pos (20U)
6492#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6493#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6494#define DMA_LIFCR_CTEIF2_Pos (19U)
6495#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6496#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6497#define DMA_LIFCR_CDMEIF2_Pos (18U)
6498#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6499#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6500#define DMA_LIFCR_CFEIF2_Pos (16U)
6501#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6502#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6503#define DMA_LIFCR_CTCIF1_Pos (11U)
6504#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6505#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6506#define DMA_LIFCR_CHTIF1_Pos (10U)
6507#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6508#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6509#define DMA_LIFCR_CTEIF1_Pos (9U)
6510#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6511#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6512#define DMA_LIFCR_CDMEIF1_Pos (8U)
6513#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6514#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6515#define DMA_LIFCR_CFEIF1_Pos (6U)
6516#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6517#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6518#define DMA_LIFCR_CTCIF0_Pos (5U)
6519#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6520#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6521#define DMA_LIFCR_CHTIF0_Pos (4U)
6522#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6523#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6524#define DMA_LIFCR_CTEIF0_Pos (3U)
6525#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6526#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6527#define DMA_LIFCR_CDMEIF0_Pos (2U)
6528#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6529#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6530#define DMA_LIFCR_CFEIF0_Pos (0U)
6531#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6532#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6533
6534/******************** Bits definition for DMA_HIFCR register ****************/
6535#define DMA_HIFCR_CTCIF7_Pos (27U)
6536#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6537#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6538#define DMA_HIFCR_CHTIF7_Pos (26U)
6539#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6540#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6541#define DMA_HIFCR_CTEIF7_Pos (25U)
6542#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6543#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6544#define DMA_HIFCR_CDMEIF7_Pos (24U)
6545#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6546#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6547#define DMA_HIFCR_CFEIF7_Pos (22U)
6548#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6549#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6550#define DMA_HIFCR_CTCIF6_Pos (21U)
6551#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6552#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6553#define DMA_HIFCR_CHTIF6_Pos (20U)
6554#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6555#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6556#define DMA_HIFCR_CTEIF6_Pos (19U)
6557#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6558#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6559#define DMA_HIFCR_CDMEIF6_Pos (18U)
6560#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6561#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6562#define DMA_HIFCR_CFEIF6_Pos (16U)
6563#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6564#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6565#define DMA_HIFCR_CTCIF5_Pos (11U)
6566#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6567#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6568#define DMA_HIFCR_CHTIF5_Pos (10U)
6569#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6570#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6571#define DMA_HIFCR_CTEIF5_Pos (9U)
6572#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6573#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6574#define DMA_HIFCR_CDMEIF5_Pos (8U)
6575#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6576#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6577#define DMA_HIFCR_CFEIF5_Pos (6U)
6578#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6579#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6580#define DMA_HIFCR_CTCIF4_Pos (5U)
6581#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6582#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6583#define DMA_HIFCR_CHTIF4_Pos (4U)
6584#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6585#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6586#define DMA_HIFCR_CTEIF4_Pos (3U)
6587#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6588#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6589#define DMA_HIFCR_CDMEIF4_Pos (2U)
6590#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6591#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6592#define DMA_HIFCR_CFEIF4_Pos (0U)
6593#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6594#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6595
6596/****************** Bit definition for DMA_SxPAR register ********************/
6597#define DMA_SxPAR_PA_Pos (0U)
6598#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6599#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6601/****************** Bit definition for DMA_SxM0AR register ********************/
6602#define DMA_SxM0AR_M0A_Pos (0U)
6603#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6604#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6606/****************** Bit definition for DMA_SxM1AR register ********************/
6607#define DMA_SxM1AR_M1A_Pos (0U)
6608#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6609#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6611/******************************************************************************/
6612/* */
6613/* AHB Master DMA2D Controller (DMA2D) */
6614/* */
6615/******************************************************************************/
6616/******************** Bit definition for DMA2D_CR register ******************/
6617
6618#define DMA2D_CR_START_Pos (0U)
6619#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
6620#define DMA2D_CR_START DMA2D_CR_START_Msk
6621#define DMA2D_CR_SUSP_Pos (1U)
6622#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
6623#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
6624#define DMA2D_CR_ABORT_Pos (2U)
6625#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
6626#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
6627#define DMA2D_CR_TEIE_Pos (8U)
6628#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
6629#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
6630#define DMA2D_CR_TCIE_Pos (9U)
6631#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
6632#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
6633#define DMA2D_CR_TWIE_Pos (10U)
6634#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
6635#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
6636#define DMA2D_CR_CAEIE_Pos (11U)
6637#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
6638#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
6639#define DMA2D_CR_CTCIE_Pos (12U)
6640#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
6641#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
6642#define DMA2D_CR_CEIE_Pos (13U)
6643#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
6644#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
6645#define DMA2D_CR_MODE_Pos (16U)
6646#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos)
6647#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
6648#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
6649#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
6651/******************** Bit definition for DMA2D_ISR register *****************/
6652
6653#define DMA2D_ISR_TEIF_Pos (0U)
6654#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
6655#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
6656#define DMA2D_ISR_TCIF_Pos (1U)
6657#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
6658#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
6659#define DMA2D_ISR_TWIF_Pos (2U)
6660#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
6661#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
6662#define DMA2D_ISR_CAEIF_Pos (3U)
6663#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
6664#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
6665#define DMA2D_ISR_CTCIF_Pos (4U)
6666#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
6667#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
6668#define DMA2D_ISR_CEIF_Pos (5U)
6669#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
6670#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
6672/******************** Bit definition for DMA2D_IFCR register ****************/
6673
6674#define DMA2D_IFCR_CTEIF_Pos (0U)
6675#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
6676#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
6677#define DMA2D_IFCR_CTCIF_Pos (1U)
6678#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
6679#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
6680#define DMA2D_IFCR_CTWIF_Pos (2U)
6681#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
6682#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
6683#define DMA2D_IFCR_CAECIF_Pos (3U)
6684#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
6685#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
6686#define DMA2D_IFCR_CCTCIF_Pos (4U)
6687#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
6688#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
6689#define DMA2D_IFCR_CCEIF_Pos (5U)
6690#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
6691#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
6693/* Legacy defines */
6694#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
6695#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
6696#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
6697#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
6698#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
6699#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
6701/******************** Bit definition for DMA2D_FGMAR register ***************/
6702
6703#define DMA2D_FGMAR_MA_Pos (0U)
6704#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
6705#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
6707/******************** Bit definition for DMA2D_FGOR register ****************/
6708
6709#define DMA2D_FGOR_LO_Pos (0U)
6710#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos)
6711#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
6713/******************** Bit definition for DMA2D_BGMAR register ***************/
6714
6715#define DMA2D_BGMAR_MA_Pos (0U)
6716#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
6717#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
6719/******************** Bit definition for DMA2D_BGOR register ****************/
6720
6721#define DMA2D_BGOR_LO_Pos (0U)
6722#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos)
6723#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
6725/******************** Bit definition for DMA2D_FGPFCCR register *************/
6726
6727#define DMA2D_FGPFCCR_CM_Pos (0U)
6728#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
6729#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
6730#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
6731#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
6732#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
6733#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
6734#define DMA2D_FGPFCCR_CCM_Pos (4U)
6735#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
6736#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
6737#define DMA2D_FGPFCCR_START_Pos (5U)
6738#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
6739#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
6740#define DMA2D_FGPFCCR_CS_Pos (8U)
6741#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
6742#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
6743#define DMA2D_FGPFCCR_AM_Pos (16U)
6744#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
6745#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
6746#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
6747#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
6748#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6749#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
6750#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
6752/******************** Bit definition for DMA2D_FGCOLR register **************/
6753
6754#define DMA2D_FGCOLR_BLUE_Pos (0U)
6755#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
6756#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
6757#define DMA2D_FGCOLR_GREEN_Pos (8U)
6758#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
6759#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
6760#define DMA2D_FGCOLR_RED_Pos (16U)
6761#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
6762#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
6764/******************** Bit definition for DMA2D_BGPFCCR register *************/
6765
6766#define DMA2D_BGPFCCR_CM_Pos (0U)
6767#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
6768#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
6769#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
6770#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
6771#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
6772#define DMA2D_BGPFCCR_CM_3 0x00000008U
6773#define DMA2D_BGPFCCR_CCM_Pos (4U)
6774#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
6775#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
6776#define DMA2D_BGPFCCR_START_Pos (5U)
6777#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
6778#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
6779#define DMA2D_BGPFCCR_CS_Pos (8U)
6780#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
6781#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
6782#define DMA2D_BGPFCCR_AM_Pos (16U)
6783#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
6784#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
6785#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
6786#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
6787#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6788#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
6789#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
6791/******************** Bit definition for DMA2D_BGCOLR register **************/
6792
6793#define DMA2D_BGCOLR_BLUE_Pos (0U)
6794#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
6795#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
6796#define DMA2D_BGCOLR_GREEN_Pos (8U)
6797#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
6798#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
6799#define DMA2D_BGCOLR_RED_Pos (16U)
6800#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
6801#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
6803/******************** Bit definition for DMA2D_FGCMAR register **************/
6804
6805#define DMA2D_FGCMAR_MA_Pos (0U)
6806#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
6807#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
6809/******************** Bit definition for DMA2D_BGCMAR register **************/
6810
6811#define DMA2D_BGCMAR_MA_Pos (0U)
6812#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
6813#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
6815/******************** Bit definition for DMA2D_OPFCCR register **************/
6816
6817#define DMA2D_OPFCCR_CM_Pos (0U)
6818#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
6819#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
6820#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
6821#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
6822#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
6824/******************** Bit definition for DMA2D_OCOLR register ***************/
6825
6828#define DMA2D_OCOLR_BLUE_1 0x000000FFU
6829#define DMA2D_OCOLR_GREEN_1 0x0000FF00U
6830#define DMA2D_OCOLR_RED_1 0x00FF0000U
6831#define DMA2D_OCOLR_ALPHA_1 0xFF000000U
6834#define DMA2D_OCOLR_BLUE_2 0x0000001FU
6835#define DMA2D_OCOLR_GREEN_2 0x000007E0U
6836#define DMA2D_OCOLR_RED_2 0x0000F800U
6839#define DMA2D_OCOLR_BLUE_3 0x0000001FU
6840#define DMA2D_OCOLR_GREEN_3 0x000003E0U
6841#define DMA2D_OCOLR_RED_3 0x00007C00U
6842#define DMA2D_OCOLR_ALPHA_3 0x00008000U
6845#define DMA2D_OCOLR_BLUE_4 0x0000000FU
6846#define DMA2D_OCOLR_GREEN_4 0x000000F0U
6847#define DMA2D_OCOLR_RED_4 0x00000F00U
6848#define DMA2D_OCOLR_ALPHA_4 0x0000F000U
6850/******************** Bit definition for DMA2D_OMAR register ****************/
6851
6852#define DMA2D_OMAR_MA_Pos (0U)
6853#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
6854#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
6856/******************** Bit definition for DMA2D_OOR register *****************/
6857
6858#define DMA2D_OOR_LO_Pos (0U)
6859#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos)
6860#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
6862/******************** Bit definition for DMA2D_NLR register *****************/
6863
6864#define DMA2D_NLR_NL_Pos (0U)
6865#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
6866#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
6867#define DMA2D_NLR_PL_Pos (16U)
6868#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
6869#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
6871/******************** Bit definition for DMA2D_LWR register *****************/
6872
6873#define DMA2D_LWR_LW_Pos (0U)
6874#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
6875#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
6877/******************** Bit definition for DMA2D_AMTCR register ***************/
6878
6879#define DMA2D_AMTCR_EN_Pos (0U)
6880#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
6881#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
6882#define DMA2D_AMTCR_DT_Pos (8U)
6883#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
6884#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
6887/******************** Bit definition for DMA2D_FGCLUT register **************/
6888
6889/******************** Bit definition for DMA2D_BGCLUT register **************/
6890
6891/******************************************************************************/
6892/* */
6893/* External Interrupt/Event Controller */
6894/* */
6895/******************************************************************************/
6896/******************* Bit definition for EXTI_IMR register *******************/
6897#define EXTI_IMR_MR0_Pos (0U)
6898#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6899#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6900#define EXTI_IMR_MR1_Pos (1U)
6901#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6902#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6903#define EXTI_IMR_MR2_Pos (2U)
6904#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6905#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6906#define EXTI_IMR_MR3_Pos (3U)
6907#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6908#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6909#define EXTI_IMR_MR4_Pos (4U)
6910#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6911#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6912#define EXTI_IMR_MR5_Pos (5U)
6913#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6914#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6915#define EXTI_IMR_MR6_Pos (6U)
6916#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6917#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6918#define EXTI_IMR_MR7_Pos (7U)
6919#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6920#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6921#define EXTI_IMR_MR8_Pos (8U)
6922#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6923#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6924#define EXTI_IMR_MR9_Pos (9U)
6925#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6926#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6927#define EXTI_IMR_MR10_Pos (10U)
6928#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6929#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6930#define EXTI_IMR_MR11_Pos (11U)
6931#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6932#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6933#define EXTI_IMR_MR12_Pos (12U)
6934#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6935#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6936#define EXTI_IMR_MR13_Pos (13U)
6937#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6938#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6939#define EXTI_IMR_MR14_Pos (14U)
6940#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6941#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6942#define EXTI_IMR_MR15_Pos (15U)
6943#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6944#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6945#define EXTI_IMR_MR16_Pos (16U)
6946#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6947#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6948#define EXTI_IMR_MR17_Pos (17U)
6949#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6950#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6951#define EXTI_IMR_MR18_Pos (18U)
6952#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6953#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6954#define EXTI_IMR_MR19_Pos (19U)
6955#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6956#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6957#define EXTI_IMR_MR20_Pos (20U)
6958#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6959#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6960#define EXTI_IMR_MR21_Pos (21U)
6961#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6962#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6963#define EXTI_IMR_MR22_Pos (22U)
6964#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6965#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6966#define EXTI_IMR_MR23_Pos (23U)
6967#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos)
6968#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk
6970/* Reference Defines */
6971#define EXTI_IMR_IM0 EXTI_IMR_MR0
6972#define EXTI_IMR_IM1 EXTI_IMR_MR1
6973#define EXTI_IMR_IM2 EXTI_IMR_MR2
6974#define EXTI_IMR_IM3 EXTI_IMR_MR3
6975#define EXTI_IMR_IM4 EXTI_IMR_MR4
6976#define EXTI_IMR_IM5 EXTI_IMR_MR5
6977#define EXTI_IMR_IM6 EXTI_IMR_MR6
6978#define EXTI_IMR_IM7 EXTI_IMR_MR7
6979#define EXTI_IMR_IM8 EXTI_IMR_MR8
6980#define EXTI_IMR_IM9 EXTI_IMR_MR9
6981#define EXTI_IMR_IM10 EXTI_IMR_MR10
6982#define EXTI_IMR_IM11 EXTI_IMR_MR11
6983#define EXTI_IMR_IM12 EXTI_IMR_MR12
6984#define EXTI_IMR_IM13 EXTI_IMR_MR13
6985#define EXTI_IMR_IM14 EXTI_IMR_MR14
6986#define EXTI_IMR_IM15 EXTI_IMR_MR15
6987#define EXTI_IMR_IM16 EXTI_IMR_MR16
6988#define EXTI_IMR_IM17 EXTI_IMR_MR17
6989#define EXTI_IMR_IM18 EXTI_IMR_MR18
6990#define EXTI_IMR_IM19 EXTI_IMR_MR19
6991#define EXTI_IMR_IM20 EXTI_IMR_MR20
6992#define EXTI_IMR_IM21 EXTI_IMR_MR21
6993#define EXTI_IMR_IM22 EXTI_IMR_MR22
6994#define EXTI_IMR_IM23 EXTI_IMR_MR23
6995
6996#define EXTI_IMR_IM_Pos (0U)
6997#define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos)
6998#define EXTI_IMR_IM EXTI_IMR_IM_Msk
7000/******************* Bit definition for EXTI_EMR register *******************/
7001#define EXTI_EMR_MR0_Pos (0U)
7002#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
7003#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
7004#define EXTI_EMR_MR1_Pos (1U)
7005#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
7006#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
7007#define EXTI_EMR_MR2_Pos (2U)
7008#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
7009#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
7010#define EXTI_EMR_MR3_Pos (3U)
7011#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
7012#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
7013#define EXTI_EMR_MR4_Pos (4U)
7014#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
7015#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
7016#define EXTI_EMR_MR5_Pos (5U)
7017#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
7018#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
7019#define EXTI_EMR_MR6_Pos (6U)
7020#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
7021#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
7022#define EXTI_EMR_MR7_Pos (7U)
7023#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
7024#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
7025#define EXTI_EMR_MR8_Pos (8U)
7026#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
7027#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
7028#define EXTI_EMR_MR9_Pos (9U)
7029#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
7030#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
7031#define EXTI_EMR_MR10_Pos (10U)
7032#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
7033#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
7034#define EXTI_EMR_MR11_Pos (11U)
7035#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
7036#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
7037#define EXTI_EMR_MR12_Pos (12U)
7038#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
7039#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
7040#define EXTI_EMR_MR13_Pos (13U)
7041#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
7042#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
7043#define EXTI_EMR_MR14_Pos (14U)
7044#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
7045#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
7046#define EXTI_EMR_MR15_Pos (15U)
7047#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
7048#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
7049#define EXTI_EMR_MR16_Pos (16U)
7050#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
7051#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
7052#define EXTI_EMR_MR17_Pos (17U)
7053#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
7054#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
7055#define EXTI_EMR_MR18_Pos (18U)
7056#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
7057#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
7058#define EXTI_EMR_MR19_Pos (19U)
7059#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
7060#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
7061#define EXTI_EMR_MR20_Pos (20U)
7062#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
7063#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
7064#define EXTI_EMR_MR21_Pos (21U)
7065#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
7066#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
7067#define EXTI_EMR_MR22_Pos (22U)
7068#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
7069#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
7070#define EXTI_EMR_MR23_Pos (23U)
7071#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos)
7072#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk
7074/* Reference Defines */
7075#define EXTI_EMR_EM0 EXTI_EMR_MR0
7076#define EXTI_EMR_EM1 EXTI_EMR_MR1
7077#define EXTI_EMR_EM2 EXTI_EMR_MR2
7078#define EXTI_EMR_EM3 EXTI_EMR_MR3
7079#define EXTI_EMR_EM4 EXTI_EMR_MR4
7080#define EXTI_EMR_EM5 EXTI_EMR_MR5
7081#define EXTI_EMR_EM6 EXTI_EMR_MR6
7082#define EXTI_EMR_EM7 EXTI_EMR_MR7
7083#define EXTI_EMR_EM8 EXTI_EMR_MR8
7084#define EXTI_EMR_EM9 EXTI_EMR_MR9
7085#define EXTI_EMR_EM10 EXTI_EMR_MR10
7086#define EXTI_EMR_EM11 EXTI_EMR_MR11
7087#define EXTI_EMR_EM12 EXTI_EMR_MR12
7088#define EXTI_EMR_EM13 EXTI_EMR_MR13
7089#define EXTI_EMR_EM14 EXTI_EMR_MR14
7090#define EXTI_EMR_EM15 EXTI_EMR_MR15
7091#define EXTI_EMR_EM16 EXTI_EMR_MR16
7092#define EXTI_EMR_EM17 EXTI_EMR_MR17
7093#define EXTI_EMR_EM18 EXTI_EMR_MR18
7094#define EXTI_EMR_EM19 EXTI_EMR_MR19
7095#define EXTI_EMR_EM20 EXTI_EMR_MR20
7096#define EXTI_EMR_EM21 EXTI_EMR_MR21
7097#define EXTI_EMR_EM22 EXTI_EMR_MR22
7098#define EXTI_EMR_EM23 EXTI_EMR_MR23
7099
7100
7101/****************** Bit definition for EXTI_RTSR register *******************/
7102#define EXTI_RTSR_TR0_Pos (0U)
7103#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
7104#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
7105#define EXTI_RTSR_TR1_Pos (1U)
7106#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
7107#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
7108#define EXTI_RTSR_TR2_Pos (2U)
7109#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
7110#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
7111#define EXTI_RTSR_TR3_Pos (3U)
7112#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
7113#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
7114#define EXTI_RTSR_TR4_Pos (4U)
7115#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
7116#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
7117#define EXTI_RTSR_TR5_Pos (5U)
7118#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
7119#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
7120#define EXTI_RTSR_TR6_Pos (6U)
7121#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
7122#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
7123#define EXTI_RTSR_TR7_Pos (7U)
7124#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
7125#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
7126#define EXTI_RTSR_TR8_Pos (8U)
7127#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
7128#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
7129#define EXTI_RTSR_TR9_Pos (9U)
7130#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
7131#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
7132#define EXTI_RTSR_TR10_Pos (10U)
7133#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
7134#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
7135#define EXTI_RTSR_TR11_Pos (11U)
7136#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
7137#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
7138#define EXTI_RTSR_TR12_Pos (12U)
7139#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
7140#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
7141#define EXTI_RTSR_TR13_Pos (13U)
7142#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
7143#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
7144#define EXTI_RTSR_TR14_Pos (14U)
7145#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
7146#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
7147#define EXTI_RTSR_TR15_Pos (15U)
7148#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
7149#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
7150#define EXTI_RTSR_TR16_Pos (16U)
7151#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
7152#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
7153#define EXTI_RTSR_TR17_Pos (17U)
7154#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
7155#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
7156#define EXTI_RTSR_TR18_Pos (18U)
7157#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
7158#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
7159#define EXTI_RTSR_TR19_Pos (19U)
7160#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
7161#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
7162#define EXTI_RTSR_TR20_Pos (20U)
7163#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
7164#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
7165#define EXTI_RTSR_TR21_Pos (21U)
7166#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
7167#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
7168#define EXTI_RTSR_TR22_Pos (22U)
7169#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
7170#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
7171#define EXTI_RTSR_TR23_Pos (23U)
7172#define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos)
7173#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk
7175/****************** Bit definition for EXTI_FTSR register *******************/
7176#define EXTI_FTSR_TR0_Pos (0U)
7177#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
7178#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
7179#define EXTI_FTSR_TR1_Pos (1U)
7180#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
7181#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
7182#define EXTI_FTSR_TR2_Pos (2U)
7183#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
7184#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
7185#define EXTI_FTSR_TR3_Pos (3U)
7186#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
7187#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
7188#define EXTI_FTSR_TR4_Pos (4U)
7189#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
7190#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
7191#define EXTI_FTSR_TR5_Pos (5U)
7192#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
7193#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
7194#define EXTI_FTSR_TR6_Pos (6U)
7195#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
7196#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
7197#define EXTI_FTSR_TR7_Pos (7U)
7198#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
7199#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
7200#define EXTI_FTSR_TR8_Pos (8U)
7201#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
7202#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
7203#define EXTI_FTSR_TR9_Pos (9U)
7204#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
7205#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
7206#define EXTI_FTSR_TR10_Pos (10U)
7207#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
7208#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
7209#define EXTI_FTSR_TR11_Pos (11U)
7210#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
7211#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
7212#define EXTI_FTSR_TR12_Pos (12U)
7213#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
7214#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
7215#define EXTI_FTSR_TR13_Pos (13U)
7216#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
7217#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
7218#define EXTI_FTSR_TR14_Pos (14U)
7219#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
7220#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
7221#define EXTI_FTSR_TR15_Pos (15U)
7222#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
7223#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
7224#define EXTI_FTSR_TR16_Pos (16U)
7225#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
7226#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
7227#define EXTI_FTSR_TR17_Pos (17U)
7228#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
7229#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
7230#define EXTI_FTSR_TR18_Pos (18U)
7231#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
7232#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
7233#define EXTI_FTSR_TR19_Pos (19U)
7234#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
7235#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
7236#define EXTI_FTSR_TR20_Pos (20U)
7237#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
7238#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
7239#define EXTI_FTSR_TR21_Pos (21U)
7240#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
7241#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
7242#define EXTI_FTSR_TR22_Pos (22U)
7243#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
7244#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
7245#define EXTI_FTSR_TR23_Pos (23U)
7246#define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos)
7247#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk
7249/****************** Bit definition for EXTI_SWIER register ******************/
7250#define EXTI_SWIER_SWIER0_Pos (0U)
7251#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
7252#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
7253#define EXTI_SWIER_SWIER1_Pos (1U)
7254#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
7255#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
7256#define EXTI_SWIER_SWIER2_Pos (2U)
7257#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
7258#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
7259#define EXTI_SWIER_SWIER3_Pos (3U)
7260#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
7261#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
7262#define EXTI_SWIER_SWIER4_Pos (4U)
7263#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
7264#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
7265#define EXTI_SWIER_SWIER5_Pos (5U)
7266#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
7267#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
7268#define EXTI_SWIER_SWIER6_Pos (6U)
7269#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
7270#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
7271#define EXTI_SWIER_SWIER7_Pos (7U)
7272#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
7273#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
7274#define EXTI_SWIER_SWIER8_Pos (8U)
7275#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
7276#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
7277#define EXTI_SWIER_SWIER9_Pos (9U)
7278#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
7279#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
7280#define EXTI_SWIER_SWIER10_Pos (10U)
7281#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
7282#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
7283#define EXTI_SWIER_SWIER11_Pos (11U)
7284#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
7285#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
7286#define EXTI_SWIER_SWIER12_Pos (12U)
7287#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
7288#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
7289#define EXTI_SWIER_SWIER13_Pos (13U)
7290#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
7291#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
7292#define EXTI_SWIER_SWIER14_Pos (14U)
7293#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
7294#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
7295#define EXTI_SWIER_SWIER15_Pos (15U)
7296#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
7297#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
7298#define EXTI_SWIER_SWIER16_Pos (16U)
7299#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
7300#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
7301#define EXTI_SWIER_SWIER17_Pos (17U)
7302#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
7303#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
7304#define EXTI_SWIER_SWIER18_Pos (18U)
7305#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
7306#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
7307#define EXTI_SWIER_SWIER19_Pos (19U)
7308#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
7309#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
7310#define EXTI_SWIER_SWIER20_Pos (20U)
7311#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
7312#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
7313#define EXTI_SWIER_SWIER21_Pos (21U)
7314#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
7315#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
7316#define EXTI_SWIER_SWIER22_Pos (22U)
7317#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
7318#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
7319#define EXTI_SWIER_SWIER23_Pos (23U)
7320#define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos)
7321#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk
7323/******************* Bit definition for EXTI_PR register ********************/
7324#define EXTI_PR_PR0_Pos (0U)
7325#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
7326#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
7327#define EXTI_PR_PR1_Pos (1U)
7328#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
7329#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
7330#define EXTI_PR_PR2_Pos (2U)
7331#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
7332#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
7333#define EXTI_PR_PR3_Pos (3U)
7334#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
7335#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
7336#define EXTI_PR_PR4_Pos (4U)
7337#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
7338#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
7339#define EXTI_PR_PR5_Pos (5U)
7340#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
7341#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
7342#define EXTI_PR_PR6_Pos (6U)
7343#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
7344#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
7345#define EXTI_PR_PR7_Pos (7U)
7346#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
7347#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
7348#define EXTI_PR_PR8_Pos (8U)
7349#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
7350#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
7351#define EXTI_PR_PR9_Pos (9U)
7352#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
7353#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
7354#define EXTI_PR_PR10_Pos (10U)
7355#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
7356#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
7357#define EXTI_PR_PR11_Pos (11U)
7358#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
7359#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
7360#define EXTI_PR_PR12_Pos (12U)
7361#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
7362#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
7363#define EXTI_PR_PR13_Pos (13U)
7364#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
7365#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
7366#define EXTI_PR_PR14_Pos (14U)
7367#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
7368#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
7369#define EXTI_PR_PR15_Pos (15U)
7370#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
7371#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
7372#define EXTI_PR_PR16_Pos (16U)
7373#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
7374#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
7375#define EXTI_PR_PR17_Pos (17U)
7376#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
7377#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
7378#define EXTI_PR_PR18_Pos (18U)
7379#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
7380#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
7381#define EXTI_PR_PR19_Pos (19U)
7382#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
7383#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
7384#define EXTI_PR_PR20_Pos (20U)
7385#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
7386#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
7387#define EXTI_PR_PR21_Pos (21U)
7388#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
7389#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
7390#define EXTI_PR_PR22_Pos (22U)
7391#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
7392#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
7393#define EXTI_PR_PR23_Pos (23U)
7394#define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos)
7395#define EXTI_PR_PR23 EXTI_PR_PR23_Msk
7397/******************************************************************************/
7398/* */
7399/* FLASH */
7400/* */
7401/******************************************************************************/
7402/*
7403* @brief FLASH Total Sectors Number
7404*/
7405#define FLASH_SECTOR_TOTAL 8
7406
7407/******************* Bits definition for FLASH_ACR register *****************/
7408#define FLASH_ACR_LATENCY_Pos (0U)
7409#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
7410#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7411#define FLASH_ACR_LATENCY_0WS 0x00000000U
7412#define FLASH_ACR_LATENCY_1WS 0x00000001U
7413#define FLASH_ACR_LATENCY_2WS 0x00000002U
7414#define FLASH_ACR_LATENCY_3WS 0x00000003U
7415#define FLASH_ACR_LATENCY_4WS 0x00000004U
7416#define FLASH_ACR_LATENCY_5WS 0x00000005U
7417#define FLASH_ACR_LATENCY_6WS 0x00000006U
7418#define FLASH_ACR_LATENCY_7WS 0x00000007U
7419#define FLASH_ACR_LATENCY_8WS 0x00000008U
7420#define FLASH_ACR_LATENCY_9WS 0x00000009U
7421#define FLASH_ACR_LATENCY_10WS 0x0000000AU
7422#define FLASH_ACR_LATENCY_11WS 0x0000000BU
7423#define FLASH_ACR_LATENCY_12WS 0x0000000CU
7424#define FLASH_ACR_LATENCY_13WS 0x0000000DU
7425#define FLASH_ACR_LATENCY_14WS 0x0000000EU
7426#define FLASH_ACR_LATENCY_15WS 0x0000000FU
7427#define FLASH_ACR_PRFTEN_Pos (8U)
7428#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
7429#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7430#define FLASH_ACR_ARTEN_Pos (9U)
7431#define FLASH_ACR_ARTEN_Msk (0x1UL << FLASH_ACR_ARTEN_Pos)
7432#define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk
7433#define FLASH_ACR_ARTRST_Pos (11U)
7434#define FLASH_ACR_ARTRST_Msk (0x1UL << FLASH_ACR_ARTRST_Pos)
7435#define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk
7436
7437/******************* Bits definition for FLASH_SR register ******************/
7438#define FLASH_SR_EOP_Pos (0U)
7439#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
7440#define FLASH_SR_EOP FLASH_SR_EOP_Msk
7441#define FLASH_SR_OPERR_Pos (1U)
7442#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
7443#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
7444#define FLASH_SR_WRPERR_Pos (4U)
7445#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
7446#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7447#define FLASH_SR_PGAERR_Pos (5U)
7448#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
7449#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7450#define FLASH_SR_PGPERR_Pos (6U)
7451#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
7452#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
7453#define FLASH_SR_ERSERR_Pos (7U)
7454#define FLASH_SR_ERSERR_Msk (0x1UL << FLASH_SR_ERSERR_Pos)
7455#define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk
7456#define FLASH_SR_BSY_Pos (16U)
7457#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
7458#define FLASH_SR_BSY FLASH_SR_BSY_Msk
7459
7460/******************* Bits definition for FLASH_CR register ******************/
7461#define FLASH_CR_PG_Pos (0U)
7462#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
7463#define FLASH_CR_PG FLASH_CR_PG_Msk
7464#define FLASH_CR_SER_Pos (1U)
7465#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
7466#define FLASH_CR_SER FLASH_CR_SER_Msk
7467#define FLASH_CR_MER_Pos (2U)
7468#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
7469#define FLASH_CR_MER FLASH_CR_MER_Msk
7470#define FLASH_CR_SNB_Pos (3U)
7471#define FLASH_CR_SNB_Msk (0xFUL << FLASH_CR_SNB_Pos)
7472#define FLASH_CR_SNB FLASH_CR_SNB_Msk
7473#define FLASH_CR_SNB_0 0x00000008U
7474#define FLASH_CR_SNB_1 0x00000010U
7475#define FLASH_CR_SNB_2 0x00000020U
7476#define FLASH_CR_SNB_3 0x00000040U
7477#define FLASH_CR_PSIZE_Pos (8U)
7478#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
7479#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
7480#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
7481#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
7482#define FLASH_CR_STRT_Pos (16U)
7483#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
7484#define FLASH_CR_STRT FLASH_CR_STRT_Msk
7485#define FLASH_CR_EOPIE_Pos (24U)
7486#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
7487#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7488#define FLASH_CR_ERRIE_Pos (25U)
7489#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
7490#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
7491#define FLASH_CR_LOCK_Pos (31U)
7492#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
7493#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7494
7495/******************* Bits definition for FLASH_OPTCR register ***************/
7496#define FLASH_OPTCR_OPTLOCK_Pos (0U)
7497#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
7498#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
7499#define FLASH_OPTCR_OPTSTRT_Pos (1U)
7500#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
7501#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
7502#define FLASH_OPTCR_BOR_LEV_Pos (2U)
7503#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
7504#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
7505#define FLASH_OPTCR_BOR_LEV_0 (0x1UL << FLASH_OPTCR_BOR_LEV_Pos)
7506#define FLASH_OPTCR_BOR_LEV_1 (0x2UL << FLASH_OPTCR_BOR_LEV_Pos)
7507#define FLASH_OPTCR_WWDG_SW_Pos (4U)
7508#define FLASH_OPTCR_WWDG_SW_Msk (0x1UL << FLASH_OPTCR_WWDG_SW_Pos)
7509#define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk
7510#define FLASH_OPTCR_IWDG_SW_Pos (5U)
7511#define FLASH_OPTCR_IWDG_SW_Msk (0x1UL << FLASH_OPTCR_IWDG_SW_Pos)
7512#define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk
7513#define FLASH_OPTCR_nRST_STOP_Pos (6U)
7514#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
7515#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
7516#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
7517#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
7518#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
7519#define FLASH_OPTCR_RDP_Pos (8U)
7520#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
7521#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
7522#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
7523#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
7524#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
7525#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
7526#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
7527#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
7528#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
7529#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
7530#define FLASH_OPTCR_nWRP_Pos (16U)
7531#define FLASH_OPTCR_nWRP_Msk (0xFFUL << FLASH_OPTCR_nWRP_Pos)
7532#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
7533#define FLASH_OPTCR_nWRP_0 0x00010000U
7534#define FLASH_OPTCR_nWRP_1 0x00020000U
7535#define FLASH_OPTCR_nWRP_2 0x00040000U
7536#define FLASH_OPTCR_nWRP_3 0x00080000U
7537#define FLASH_OPTCR_nWRP_4 0x00100000U
7538#define FLASH_OPTCR_nWRP_5 0x00200000U
7539#define FLASH_OPTCR_nWRP_6 0x00400000U
7540#define FLASH_OPTCR_nWRP_7 0x00800000U
7541#define FLASH_OPTCR_IWDG_STDBY_Pos (30U)
7542#define FLASH_OPTCR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTCR_IWDG_STDBY_Pos)
7543#define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk
7544#define FLASH_OPTCR_IWDG_STOP_Pos (31U)
7545#define FLASH_OPTCR_IWDG_STOP_Msk (0x1UL << FLASH_OPTCR_IWDG_STOP_Pos)
7546#define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk
7547
7548/******************* Bits definition for FLASH_OPTCR1 register ***************/
7549#define FLASH_OPTCR1_BOOT_ADD0_Pos (0U)
7550#define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD0_Pos)
7551#define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk
7552#define FLASH_OPTCR1_BOOT_ADD1_Pos (16U)
7553#define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD1_Pos)
7554#define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk
7555
7556
7557/******************************************************************************/
7558/* */
7559/* Flexible Memory Controller */
7560/* */
7561/******************************************************************************/
7562/****************** Bit definition for FMC_BCR1 register *******************/
7563#define FMC_BCR1_MBKEN_Pos (0U)
7564#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)
7565#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk
7566#define FMC_BCR1_MUXEN_Pos (1U)
7567#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)
7568#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk
7569#define FMC_BCR1_MTYP_Pos (2U)
7570#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)
7571#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk
7572#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)
7573#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)
7574#define FMC_BCR1_MWID_Pos (4U)
7575#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)
7576#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk
7577#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)
7578#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)
7579#define FMC_BCR1_FACCEN_Pos (6U)
7580#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)
7581#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk
7582#define FMC_BCR1_BURSTEN_Pos (8U)
7583#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)
7584#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk
7585#define FMC_BCR1_WAITPOL_Pos (9U)
7586#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)
7587#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk
7588#define FMC_BCR1_WRAPMOD_Pos (10U)
7589#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos)
7590#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk
7591#define FMC_BCR1_WAITCFG_Pos (11U)
7592#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)
7593#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk
7594#define FMC_BCR1_WREN_Pos (12U)
7595#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)
7596#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk
7597#define FMC_BCR1_WAITEN_Pos (13U)
7598#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)
7599#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk
7600#define FMC_BCR1_EXTMOD_Pos (14U)
7601#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)
7602#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk
7603#define FMC_BCR1_ASYNCWAIT_Pos (15U)
7604#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)
7605#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk
7606#define FMC_BCR1_CPSIZE_Pos (16U)
7607#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos)
7608#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk
7609#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos)
7610#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos)
7611#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos)
7612#define FMC_BCR1_CBURSTRW_Pos (19U)
7613#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)
7614#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk
7615#define FMC_BCR1_CCLKEN_Pos (20U)
7616#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
7617#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
7618#define FMC_BCR1_WFDIS_Pos (21U)
7619#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
7620#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
7622/****************** Bit definition for FMC_BCR2 register *******************/
7623#define FMC_BCR2_MBKEN_Pos (0U)
7624#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)
7625#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk
7626#define FMC_BCR2_MUXEN_Pos (1U)
7627#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)
7628#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk
7629#define FMC_BCR2_MTYP_Pos (2U)
7630#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)
7631#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk
7632#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)
7633#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)
7634#define FMC_BCR2_MWID_Pos (4U)
7635#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)
7636#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk
7637#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)
7638#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)
7639#define FMC_BCR2_FACCEN_Pos (6U)
7640#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)
7641#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk
7642#define FMC_BCR2_BURSTEN_Pos (8U)
7643#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)
7644#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk
7645#define FMC_BCR2_WAITPOL_Pos (9U)
7646#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)
7647#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk
7648#define FMC_BCR2_WRAPMOD_Pos (10U)
7649#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos)
7650#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk
7651#define FMC_BCR2_WAITCFG_Pos (11U)
7652#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)
7653#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk
7654#define FMC_BCR2_WREN_Pos (12U)
7655#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)
7656#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk
7657#define FMC_BCR2_WAITEN_Pos (13U)
7658#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)
7659#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk
7660#define FMC_BCR2_EXTMOD_Pos (14U)
7661#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)
7662#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk
7663#define FMC_BCR2_ASYNCWAIT_Pos (15U)
7664#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)
7665#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk
7666#define FMC_BCR2_CPSIZE_Pos (16U)
7667#define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos)
7668#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk
7669#define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos)
7670#define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos)
7671#define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos)
7672#define FMC_BCR2_CBURSTRW_Pos (19U)
7673#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)
7674#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk
7676/****************** Bit definition for FMC_BCR3 register *******************/
7677#define FMC_BCR3_MBKEN_Pos (0U)
7678#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)
7679#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk
7680#define FMC_BCR3_MUXEN_Pos (1U)
7681#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)
7682#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk
7683#define FMC_BCR3_MTYP_Pos (2U)
7684#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)
7685#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk
7686#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)
7687#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)
7688#define FMC_BCR3_MWID_Pos (4U)
7689#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)
7690#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk
7691#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)
7692#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)
7693#define FMC_BCR3_FACCEN_Pos (6U)
7694#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)
7695#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk
7696#define FMC_BCR3_BURSTEN_Pos (8U)
7697#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)
7698#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk
7699#define FMC_BCR3_WAITPOL_Pos (9U)
7700#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)
7701#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk
7702#define FMC_BCR3_WRAPMOD_Pos (10U)
7703#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos)
7704#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk
7705#define FMC_BCR3_WAITCFG_Pos (11U)
7706#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)
7707#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk
7708#define FMC_BCR3_WREN_Pos (12U)
7709#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)
7710#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk
7711#define FMC_BCR3_WAITEN_Pos (13U)
7712#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)
7713#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk
7714#define FMC_BCR3_EXTMOD_Pos (14U)
7715#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)
7716#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk
7717#define FMC_BCR3_ASYNCWAIT_Pos (15U)
7718#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)
7719#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk
7720#define FMC_BCR3_CPSIZE_Pos (16U)
7721#define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos)
7722#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk
7723#define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos)
7724#define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos)
7725#define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos)
7726#define FMC_BCR3_CBURSTRW_Pos (19U)
7727#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)
7728#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk
7730/****************** Bit definition for FMC_BCR4 register *******************/
7731#define FMC_BCR4_MBKEN_Pos (0U)
7732#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)
7733#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk
7734#define FMC_BCR4_MUXEN_Pos (1U)
7735#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)
7736#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk
7737#define FMC_BCR4_MTYP_Pos (2U)
7738#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)
7739#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk
7740#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)
7741#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)
7742#define FMC_BCR4_MWID_Pos (4U)
7743#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)
7744#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk
7745#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)
7746#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)
7747#define FMC_BCR4_FACCEN_Pos (6U)
7748#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)
7749#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk
7750#define FMC_BCR4_BURSTEN_Pos (8U)
7751#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)
7752#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk
7753#define FMC_BCR4_WAITPOL_Pos (9U)
7754#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)
7755#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk
7756#define FMC_BCR4_WRAPMOD_Pos (10U)
7757#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos)
7758#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk
7759#define FMC_BCR4_WAITCFG_Pos (11U)
7760#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)
7761#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk
7762#define FMC_BCR4_WREN_Pos (12U)
7763#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)
7764#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk
7765#define FMC_BCR4_WAITEN_Pos (13U)
7766#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)
7767#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk
7768#define FMC_BCR4_EXTMOD_Pos (14U)
7769#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)
7770#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk
7771#define FMC_BCR4_ASYNCWAIT_Pos (15U)
7772#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)
7773#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk
7774#define FMC_BCR4_CPSIZE_Pos (16U)
7775#define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos)
7776#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk
7777#define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos)
7778#define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos)
7779#define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos)
7780#define FMC_BCR4_CBURSTRW_Pos (19U)
7781#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)
7782#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk
7784/****************** Bit definition for FMC_BTR1 register ******************/
7785#define FMC_BTR1_ADDSET_Pos (0U)
7786#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)
7787#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk
7788#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)
7789#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)
7790#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)
7791#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)
7792#define FMC_BTR1_ADDHLD_Pos (4U)
7793#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)
7794#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk
7795#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)
7796#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)
7797#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)
7798#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)
7799#define FMC_BTR1_DATAST_Pos (8U)
7800#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)
7801#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk
7802#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)
7803#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)
7804#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)
7805#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)
7806#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)
7807#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)
7808#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)
7809#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)
7810#define FMC_BTR1_BUSTURN_Pos (16U)
7811#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)
7812#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk
7813#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)
7814#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)
7815#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)
7816#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)
7817#define FMC_BTR1_CLKDIV_Pos (20U)
7818#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)
7819#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk
7820#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)
7821#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)
7822#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)
7823#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)
7824#define FMC_BTR1_DATLAT_Pos (24U)
7825#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)
7826#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk
7827#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)
7828#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)
7829#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)
7830#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)
7831#define FMC_BTR1_ACCMOD_Pos (28U)
7832#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)
7833#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk
7834#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)
7835#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)
7837/****************** Bit definition for FMC_BTR2 register *******************/
7838#define FMC_BTR2_ADDSET_Pos (0U)
7839#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)
7840#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk
7841#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)
7842#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)
7843#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)
7844#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)
7845#define FMC_BTR2_ADDHLD_Pos (4U)
7846#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)
7847#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk
7848#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)
7849#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)
7850#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)
7851#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)
7852#define FMC_BTR2_DATAST_Pos (8U)
7853#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)
7854#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk
7855#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)
7856#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)
7857#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)
7858#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)
7859#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)
7860#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)
7861#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)
7862#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)
7863#define FMC_BTR2_BUSTURN_Pos (16U)
7864#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)
7865#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk
7866#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)
7867#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)
7868#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)
7869#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)
7870#define FMC_BTR2_CLKDIV_Pos (20U)
7871#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)
7872#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk
7873#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)
7874#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)
7875#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)
7876#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)
7877#define FMC_BTR2_DATLAT_Pos (24U)
7878#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)
7879#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk
7880#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)
7881#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)
7882#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)
7883#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)
7884#define FMC_BTR2_ACCMOD_Pos (28U)
7885#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)
7886#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk
7887#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)
7888#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)
7890/******************* Bit definition for FMC_BTR3 register *******************/
7891#define FMC_BTR3_ADDSET_Pos (0U)
7892#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)
7893#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk
7894#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)
7895#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)
7896#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)
7897#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)
7898#define FMC_BTR3_ADDHLD_Pos (4U)
7899#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)
7900#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk
7901#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)
7902#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)
7903#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)
7904#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)
7905#define FMC_BTR3_DATAST_Pos (8U)
7906#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)
7907#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk
7908#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)
7909#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)
7910#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)
7911#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)
7912#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)
7913#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)
7914#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)
7915#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)
7916#define FMC_BTR3_BUSTURN_Pos (16U)
7917#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)
7918#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk
7919#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)
7920#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)
7921#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)
7922#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)
7923#define FMC_BTR3_CLKDIV_Pos (20U)
7924#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)
7925#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk
7926#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)
7927#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)
7928#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)
7929#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)
7930#define FMC_BTR3_DATLAT_Pos (24U)
7931#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)
7932#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk
7933#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)
7934#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)
7935#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)
7936#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)
7937#define FMC_BTR3_ACCMOD_Pos (28U)
7938#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)
7939#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk
7940#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)
7941#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)
7943/****************** Bit definition for FMC_BTR4 register *******************/
7944#define FMC_BTR4_ADDSET_Pos (0U)
7945#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)
7946#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk
7947#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)
7948#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)
7949#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)
7950#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)
7951#define FMC_BTR4_ADDHLD_Pos (4U)
7952#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)
7953#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk
7954#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)
7955#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)
7956#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)
7957#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)
7958#define FMC_BTR4_DATAST_Pos (8U)
7959#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)
7960#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk
7961#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)
7962#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)
7963#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)
7964#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)
7965#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)
7966#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)
7967#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)
7968#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)
7969#define FMC_BTR4_BUSTURN_Pos (16U)
7970#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)
7971#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk
7972#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)
7973#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)
7974#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)
7975#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)
7976#define FMC_BTR4_CLKDIV_Pos (20U)
7977#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)
7978#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk
7979#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)
7980#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)
7981#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)
7982#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)
7983#define FMC_BTR4_DATLAT_Pos (24U)
7984#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)
7985#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk
7986#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)
7987#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)
7988#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)
7989#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)
7990#define FMC_BTR4_ACCMOD_Pos (28U)
7991#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)
7992#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk
7993#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)
7994#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)
7996/****************** Bit definition for FMC_BWTR1 register ******************/
7997#define FMC_BWTR1_ADDSET_Pos (0U)
7998#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)
7999#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk
8000#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)
8001#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)
8002#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)
8003#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)
8004#define FMC_BWTR1_ADDHLD_Pos (4U)
8005#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)
8006#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk
8007#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)
8008#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)
8009#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)
8010#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)
8011#define FMC_BWTR1_DATAST_Pos (8U)
8012#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)
8013#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk
8014#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)
8015#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)
8016#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)
8017#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)
8018#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)
8019#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)
8020#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)
8021#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)
8022#define FMC_BWTR1_BUSTURN_Pos (16U)
8023#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos)
8024#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk
8025#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos)
8026#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos)
8027#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos)
8028#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos)
8029#define FMC_BWTR1_ACCMOD_Pos (28U)
8030#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)
8031#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk
8032#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)
8033#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)
8035/****************** Bit definition for FMC_BWTR2 register ******************/
8036#define FMC_BWTR2_ADDSET_Pos (0U)
8037#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)
8038#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk
8039#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)
8040#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)
8041#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)
8042#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)
8043#define FMC_BWTR2_ADDHLD_Pos (4U)
8044#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)
8045#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk
8046#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)
8047#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)
8048#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)
8049#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)
8050#define FMC_BWTR2_DATAST_Pos (8U)
8051#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)
8052#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk
8053#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)
8054#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)
8055#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)
8056#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)
8057#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)
8058#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)
8059#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)
8060#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)
8061#define FMC_BWTR2_BUSTURN_Pos (16U)
8062#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos)
8063#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk
8064#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos)
8065#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos)
8066#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos)
8067#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos)
8068#define FMC_BWTR2_ACCMOD_Pos (28U)
8069#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)
8070#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk
8071#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)
8072#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)
8074/****************** Bit definition for FMC_BWTR3 register ******************/
8075#define FMC_BWTR3_ADDSET_Pos (0U)
8076#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)
8077#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk
8078#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)
8079#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)
8080#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)
8081#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)
8082#define FMC_BWTR3_ADDHLD_Pos (4U)
8083#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)
8084#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk
8085#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)
8086#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)
8087#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)
8088#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)
8089#define FMC_BWTR3_DATAST_Pos (8U)
8090#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)
8091#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk
8092#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)
8093#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)
8094#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)
8095#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)
8096#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)
8097#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)
8098#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)
8099#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)
8100#define FMC_BWTR3_BUSTURN_Pos (16U)
8101#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos)
8102#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk
8103#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos)
8104#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos)
8105#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos)
8106#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos)
8107#define FMC_BWTR3_ACCMOD_Pos (28U)
8108#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)
8109#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk
8110#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)
8111#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)
8113/****************** Bit definition for FMC_BWTR4 register ******************/
8114#define FMC_BWTR4_ADDSET_Pos (0U)
8115#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)
8116#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk
8117#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)
8118#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)
8119#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)
8120#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)
8121#define FMC_BWTR4_ADDHLD_Pos (4U)
8122#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)
8123#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk
8124#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)
8125#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)
8126#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)
8127#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)
8128#define FMC_BWTR4_DATAST_Pos (8U)
8129#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)
8130#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk
8131#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)
8132#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)
8133#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)
8134#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)
8135#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)
8136#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)
8137#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)
8138#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)
8139#define FMC_BWTR4_BUSTURN_Pos (16U)
8140#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos)
8141#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk
8142#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos)
8143#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos)
8144#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos)
8145#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos)
8146#define FMC_BWTR4_ACCMOD_Pos (28U)
8147#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)
8148#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk
8149#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)
8150#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)
8152/****************** Bit definition for FMC_PCR register *******************/
8153#define FMC_PCR_PWAITEN_Pos (1U)
8154#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
8155#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
8156#define FMC_PCR_PBKEN_Pos (2U)
8157#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
8158#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
8159#define FMC_PCR_PTYP_Pos (3U)
8160#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
8161#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
8162#define FMC_PCR_PWID_Pos (4U)
8163#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
8164#define FMC_PCR_PWID FMC_PCR_PWID_Msk
8165#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
8166#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
8167#define FMC_PCR_ECCEN_Pos (6U)
8168#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
8169#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
8170#define FMC_PCR_TCLR_Pos (9U)
8171#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
8172#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
8173#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
8174#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
8175#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
8176#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
8177#define FMC_PCR_TAR_Pos (13U)
8178#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
8179#define FMC_PCR_TAR FMC_PCR_TAR_Msk
8180#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
8181#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
8182#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
8183#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
8184#define FMC_PCR_ECCPS_Pos (17U)
8185#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
8186#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
8187#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
8188#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
8189#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
8191/******************* Bit definition for FMC_SR register *******************/
8192#define FMC_SR_IRS_Pos (0U)
8193#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
8194#define FMC_SR_IRS FMC_SR_IRS_Msk
8195#define FMC_SR_ILS_Pos (1U)
8196#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
8197#define FMC_SR_ILS FMC_SR_ILS_Msk
8198#define FMC_SR_IFS_Pos (2U)
8199#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
8200#define FMC_SR_IFS FMC_SR_IFS_Msk
8201#define FMC_SR_IREN_Pos (3U)
8202#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
8203#define FMC_SR_IREN FMC_SR_IREN_Msk
8204#define FMC_SR_ILEN_Pos (4U)
8205#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
8206#define FMC_SR_ILEN FMC_SR_ILEN_Msk
8207#define FMC_SR_IFEN_Pos (5U)
8208#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
8209#define FMC_SR_IFEN FMC_SR_IFEN_Msk
8210#define FMC_SR_FEMPT_Pos (6U)
8211#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
8212#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
8214/****************** Bit definition for FMC_PMEM register ******************/
8215#define FMC_PMEM_MEMSET3_Pos (0U)
8216#define FMC_PMEM_MEMSET3_Msk (0xFFUL << FMC_PMEM_MEMSET3_Pos)
8217#define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk
8218#define FMC_PMEM_MEMSET3_0 (0x01UL << FMC_PMEM_MEMSET3_Pos)
8219#define FMC_PMEM_MEMSET3_1 (0x02UL << FMC_PMEM_MEMSET3_Pos)
8220#define FMC_PMEM_MEMSET3_2 (0x04UL << FMC_PMEM_MEMSET3_Pos)
8221#define FMC_PMEM_MEMSET3_3 (0x08UL << FMC_PMEM_MEMSET3_Pos)
8222#define FMC_PMEM_MEMSET3_4 (0x10UL << FMC_PMEM_MEMSET3_Pos)
8223#define FMC_PMEM_MEMSET3_5 (0x20UL << FMC_PMEM_MEMSET3_Pos)
8224#define FMC_PMEM_MEMSET3_6 (0x40UL << FMC_PMEM_MEMSET3_Pos)
8225#define FMC_PMEM_MEMSET3_7 (0x80UL << FMC_PMEM_MEMSET3_Pos)
8226#define FMC_PMEM_MEMWAIT3_Pos (8U)
8227#define FMC_PMEM_MEMWAIT3_Msk (0xFFUL << FMC_PMEM_MEMWAIT3_Pos)
8228#define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk
8229#define FMC_PMEM_MEMWAIT3_0 (0x01UL << FMC_PMEM_MEMWAIT3_Pos)
8230#define FMC_PMEM_MEMWAIT3_1 (0x02UL << FMC_PMEM_MEMWAIT3_Pos)
8231#define FMC_PMEM_MEMWAIT3_2 (0x04UL << FMC_PMEM_MEMWAIT3_Pos)
8232#define FMC_PMEM_MEMWAIT3_3 (0x08UL << FMC_PMEM_MEMWAIT3_Pos)
8233#define FMC_PMEM_MEMWAIT3_4 (0x10UL << FMC_PMEM_MEMWAIT3_Pos)
8234#define FMC_PMEM_MEMWAIT3_5 (0x20UL << FMC_PMEM_MEMWAIT3_Pos)
8235#define FMC_PMEM_MEMWAIT3_6 (0x40UL << FMC_PMEM_MEMWAIT3_Pos)
8236#define FMC_PMEM_MEMWAIT3_7 (0x80UL << FMC_PMEM_MEMWAIT3_Pos)
8237#define FMC_PMEM_MEMHOLD3_Pos (16U)
8238#define FMC_PMEM_MEMHOLD3_Msk (0xFFUL << FMC_PMEM_MEMHOLD3_Pos)
8239#define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk
8240#define FMC_PMEM_MEMHOLD3_0 (0x01UL << FMC_PMEM_MEMHOLD3_Pos)
8241#define FMC_PMEM_MEMHOLD3_1 (0x02UL << FMC_PMEM_MEMHOLD3_Pos)
8242#define FMC_PMEM_MEMHOLD3_2 (0x04UL << FMC_PMEM_MEMHOLD3_Pos)
8243#define FMC_PMEM_MEMHOLD3_3 (0x08UL << FMC_PMEM_MEMHOLD3_Pos)
8244#define FMC_PMEM_MEMHOLD3_4 (0x10UL << FMC_PMEM_MEMHOLD3_Pos)
8245#define FMC_PMEM_MEMHOLD3_5 (0x20UL << FMC_PMEM_MEMHOLD3_Pos)
8246#define FMC_PMEM_MEMHOLD3_6 (0x40UL << FMC_PMEM_MEMHOLD3_Pos)
8247#define FMC_PMEM_MEMHOLD3_7 (0x80UL << FMC_PMEM_MEMHOLD3_Pos)
8248#define FMC_PMEM_MEMHIZ3_Pos (24U)
8249#define FMC_PMEM_MEMHIZ3_Msk (0xFFUL << FMC_PMEM_MEMHIZ3_Pos)
8250#define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk
8251#define FMC_PMEM_MEMHIZ3_0 (0x01UL << FMC_PMEM_MEMHIZ3_Pos)
8252#define FMC_PMEM_MEMHIZ3_1 (0x02UL << FMC_PMEM_MEMHIZ3_Pos)
8253#define FMC_PMEM_MEMHIZ3_2 (0x04UL << FMC_PMEM_MEMHIZ3_Pos)
8254#define FMC_PMEM_MEMHIZ3_3 (0x08UL << FMC_PMEM_MEMHIZ3_Pos)
8255#define FMC_PMEM_MEMHIZ3_4 (0x10UL << FMC_PMEM_MEMHIZ3_Pos)
8256#define FMC_PMEM_MEMHIZ3_5 (0x20UL << FMC_PMEM_MEMHIZ3_Pos)
8257#define FMC_PMEM_MEMHIZ3_6 (0x40UL << FMC_PMEM_MEMHIZ3_Pos)
8258#define FMC_PMEM_MEMHIZ3_7 (0x80UL << FMC_PMEM_MEMHIZ3_Pos)
8260/****************** Bit definition for FMC_PATT register ******************/
8261#define FMC_PATT_ATTSET3_Pos (0U)
8262#define FMC_PATT_ATTSET3_Msk (0xFFUL << FMC_PATT_ATTSET3_Pos)
8263#define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk
8264#define FMC_PATT_ATTSET3_0 (0x01UL << FMC_PATT_ATTSET3_Pos)
8265#define FMC_PATT_ATTSET3_1 (0x02UL << FMC_PATT_ATTSET3_Pos)
8266#define FMC_PATT_ATTSET3_2 (0x04UL << FMC_PATT_ATTSET3_Pos)
8267#define FMC_PATT_ATTSET3_3 (0x08UL << FMC_PATT_ATTSET3_Pos)
8268#define FMC_PATT_ATTSET3_4 (0x10UL << FMC_PATT_ATTSET3_Pos)
8269#define FMC_PATT_ATTSET3_5 (0x20UL << FMC_PATT_ATTSET3_Pos)
8270#define FMC_PATT_ATTSET3_6 (0x40UL << FMC_PATT_ATTSET3_Pos)
8271#define FMC_PATT_ATTSET3_7 (0x80UL << FMC_PATT_ATTSET3_Pos)
8272#define FMC_PATT_ATTWAIT3_Pos (8U)
8273#define FMC_PATT_ATTWAIT3_Msk (0xFFUL << FMC_PATT_ATTWAIT3_Pos)
8274#define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk
8275#define FMC_PATT_ATTWAIT3_0 (0x01UL << FMC_PATT_ATTWAIT3_Pos)
8276#define FMC_PATT_ATTWAIT3_1 (0x02UL << FMC_PATT_ATTWAIT3_Pos)
8277#define FMC_PATT_ATTWAIT3_2 (0x04UL << FMC_PATT_ATTWAIT3_Pos)
8278#define FMC_PATT_ATTWAIT3_3 (0x08UL << FMC_PATT_ATTWAIT3_Pos)
8279#define FMC_PATT_ATTWAIT3_4 (0x10UL << FMC_PATT_ATTWAIT3_Pos)
8280#define FMC_PATT_ATTWAIT3_5 (0x20UL << FMC_PATT_ATTWAIT3_Pos)
8281#define FMC_PATT_ATTWAIT3_6 (0x40UL << FMC_PATT_ATTWAIT3_Pos)
8282#define FMC_PATT_ATTWAIT3_7 (0x80UL << FMC_PATT_ATTWAIT3_Pos)
8283#define FMC_PATT_ATTHOLD3_Pos (16U)
8284#define FMC_PATT_ATTHOLD3_Msk (0xFFUL << FMC_PATT_ATTHOLD3_Pos)
8285#define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk
8286#define FMC_PATT_ATTHOLD3_0 (0x01UL << FMC_PATT_ATTHOLD3_Pos)
8287#define FMC_PATT_ATTHOLD3_1 (0x02UL << FMC_PATT_ATTHOLD3_Pos)
8288#define FMC_PATT_ATTHOLD3_2 (0x04UL << FMC_PATT_ATTHOLD3_Pos)
8289#define FMC_PATT_ATTHOLD3_3 (0x08UL << FMC_PATT_ATTHOLD3_Pos)
8290#define FMC_PATT_ATTHOLD3_4 (0x10UL << FMC_PATT_ATTHOLD3_Pos)
8291#define FMC_PATT_ATTHOLD3_5 (0x20UL << FMC_PATT_ATTHOLD3_Pos)
8292#define FMC_PATT_ATTHOLD3_6 (0x40UL << FMC_PATT_ATTHOLD3_Pos)
8293#define FMC_PATT_ATTHOLD3_7 (0x80UL << FMC_PATT_ATTHOLD3_Pos)
8294#define FMC_PATT_ATTHIZ3_Pos (24U)
8295#define FMC_PATT_ATTHIZ3_Msk (0xFFUL << FMC_PATT_ATTHIZ3_Pos)
8296#define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk
8297#define FMC_PATT_ATTHIZ3_0 (0x01UL << FMC_PATT_ATTHIZ3_Pos)
8298#define FMC_PATT_ATTHIZ3_1 (0x02UL << FMC_PATT_ATTHIZ3_Pos)
8299#define FMC_PATT_ATTHIZ3_2 (0x04UL << FMC_PATT_ATTHIZ3_Pos)
8300#define FMC_PATT_ATTHIZ3_3 (0x08UL << FMC_PATT_ATTHIZ3_Pos)
8301#define FMC_PATT_ATTHIZ3_4 (0x10UL << FMC_PATT_ATTHIZ3_Pos)
8302#define FMC_PATT_ATTHIZ3_5 (0x20UL << FMC_PATT_ATTHIZ3_Pos)
8303#define FMC_PATT_ATTHIZ3_6 (0x40UL << FMC_PATT_ATTHIZ3_Pos)
8304#define FMC_PATT_ATTHIZ3_7 (0x80UL << FMC_PATT_ATTHIZ3_Pos)
8306/****************** Bit definition for FMC_ECCR register ******************/
8307#define FMC_ECCR_ECC3_Pos (0U)
8308#define FMC_ECCR_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC3_Pos)
8309#define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk
8311/****************** Bit definition for FMC_SDCR1 register ******************/
8312#define FMC_SDCR1_NC_Pos (0U)
8313#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos)
8314#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk
8315#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos)
8316#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos)
8317#define FMC_SDCR1_NR_Pos (2U)
8318#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos)
8319#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk
8320#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos)
8321#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos)
8322#define FMC_SDCR1_MWID_Pos (4U)
8323#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos)
8324#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk
8325#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos)
8326#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos)
8327#define FMC_SDCR1_NB_Pos (6U)
8328#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos)
8329#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk
8330#define FMC_SDCR1_CAS_Pos (7U)
8331#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos)
8332#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk
8333#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos)
8334#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos)
8335#define FMC_SDCR1_WP_Pos (9U)
8336#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos)
8337#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk
8338#define FMC_SDCR1_SDCLK_Pos (10U)
8339#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos)
8340#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk
8341#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos)
8342#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos)
8343#define FMC_SDCR1_RBURST_Pos (12U)
8344#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos)
8345#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk
8346#define FMC_SDCR1_RPIPE_Pos (13U)
8347#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos)
8348#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk
8349#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos)
8350#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos)
8352/****************** Bit definition for FMC_SDCR2 register ******************/
8353#define FMC_SDCR2_NC_Pos (0U)
8354#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos)
8355#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk
8356#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos)
8357#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos)
8358#define FMC_SDCR2_NR_Pos (2U)
8359#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos)
8360#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk
8361#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos)
8362#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos)
8363#define FMC_SDCR2_MWID_Pos (4U)
8364#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos)
8365#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk
8366#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos)
8367#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos)
8368#define FMC_SDCR2_NB_Pos (6U)
8369#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos)
8370#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk
8371#define FMC_SDCR2_CAS_Pos (7U)
8372#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos)
8373#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk
8374#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos)
8375#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos)
8376#define FMC_SDCR2_WP_Pos (9U)
8377#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos)
8378#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk
8379#define FMC_SDCR2_SDCLK_Pos (10U)
8380#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos)
8381#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk
8382#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos)
8383#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos)
8384#define FMC_SDCR2_RBURST_Pos (12U)
8385#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos)
8386#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk
8387#define FMC_SDCR2_RPIPE_Pos (13U)
8388#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos)
8389#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk
8390#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos)
8391#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos)
8393/****************** Bit definition for FMC_SDTR1 register ******************/
8394#define FMC_SDTR1_TMRD_Pos (0U)
8395#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos)
8396#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk
8397#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos)
8398#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos)
8399#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos)
8400#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos)
8401#define FMC_SDTR1_TXSR_Pos (4U)
8402#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos)
8403#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk
8404#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos)
8405#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos)
8406#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos)
8407#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos)
8408#define FMC_SDTR1_TRAS_Pos (8U)
8409#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos)
8410#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk
8411#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos)
8412#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos)
8413#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos)
8414#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos)
8415#define FMC_SDTR1_TRC_Pos (12U)
8416#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos)
8417#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk
8418#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos)
8419#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos)
8420#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos)
8421#define FMC_SDTR1_TWR_Pos (16U)
8422#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos)
8423#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk
8424#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos)
8425#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos)
8426#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos)
8427#define FMC_SDTR1_TRP_Pos (20U)
8428#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos)
8429#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk
8430#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos)
8431#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos)
8432#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos)
8433#define FMC_SDTR1_TRCD_Pos (24U)
8434#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos)
8435#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk
8436#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos)
8437#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos)
8438#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos)
8440/****************** Bit definition for FMC_SDTR2 register ******************/
8441#define FMC_SDTR2_TMRD_Pos (0U)
8442#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos)
8443#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk
8444#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos)
8445#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos)
8446#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos)
8447#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos)
8448#define FMC_SDTR2_TXSR_Pos (4U)
8449#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos)
8450#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk
8451#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos)
8452#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos)
8453#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos)
8454#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos)
8455#define FMC_SDTR2_TRAS_Pos (8U)
8456#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos)
8457#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk
8458#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos)
8459#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos)
8460#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos)
8461#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos)
8462#define FMC_SDTR2_TRC_Pos (12U)
8463#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos)
8464#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk
8465#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos)
8466#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos)
8467#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos)
8468#define FMC_SDTR2_TWR_Pos (16U)
8469#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos)
8470#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk
8471#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos)
8472#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos)
8473#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos)
8474#define FMC_SDTR2_TRP_Pos (20U)
8475#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos)
8476#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk
8477#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos)
8478#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos)
8479#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos)
8480#define FMC_SDTR2_TRCD_Pos (24U)
8481#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos)
8482#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk
8483#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos)
8484#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos)
8485#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos)
8487/****************** Bit definition for FMC_SDCMR register ******************/
8488#define FMC_SDCMR_MODE_Pos (0U)
8489#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
8490#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
8491#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
8492#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
8493#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos)
8494#define FMC_SDCMR_CTB2_Pos (3U)
8495#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
8496#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
8497#define FMC_SDCMR_CTB1_Pos (4U)
8498#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
8499#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
8500#define FMC_SDCMR_NRFS_Pos (5U)
8501#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
8502#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
8503#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
8504#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
8505#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
8506#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
8507#define FMC_SDCMR_MRD_Pos (9U)
8508#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
8509#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
8511/****************** Bit definition for FMC_SDRTR register ******************/
8512#define FMC_SDRTR_CRE_Pos (0U)
8513#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
8514#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
8515#define FMC_SDRTR_COUNT_Pos (1U)
8516#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
8517#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
8518#define FMC_SDRTR_REIE_Pos (14U)
8519#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
8520#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
8522/****************** Bit definition for FMC_SDSR register ******************/
8523#define FMC_SDSR_RE_Pos (0U)
8524#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
8525#define FMC_SDSR_RE FMC_SDSR_RE_Msk
8526#define FMC_SDSR_MODES1_Pos (1U)
8527#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
8528#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
8529#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
8530#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
8531#define FMC_SDSR_MODES2_Pos (3U)
8532#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
8533#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
8534#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
8535#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
8536#define FMC_SDSR_BUSY_Pos (5U)
8537#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos)
8538#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk
8540/******************************************************************************/
8541/* */
8542/* General Purpose I/O */
8543/* */
8544/******************************************************************************/
8545/****************** Bits definition for GPIO_MODER register *****************/
8546#define GPIO_MODER_MODER0_Pos (0U)
8547#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
8548#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
8549#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
8550#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
8551#define GPIO_MODER_MODER1_Pos (2U)
8552#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
8553#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
8554#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
8555#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
8556#define GPIO_MODER_MODER2_Pos (4U)
8557#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
8558#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
8559#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
8560#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
8561#define GPIO_MODER_MODER3_Pos (6U)
8562#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
8563#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
8564#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
8565#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
8566#define GPIO_MODER_MODER4_Pos (8U)
8567#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
8568#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
8569#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
8570#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
8571#define GPIO_MODER_MODER5_Pos (10U)
8572#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
8573#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
8574#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
8575#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
8576#define GPIO_MODER_MODER6_Pos (12U)
8577#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
8578#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
8579#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
8580#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
8581#define GPIO_MODER_MODER7_Pos (14U)
8582#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
8583#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
8584#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
8585#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
8586#define GPIO_MODER_MODER8_Pos (16U)
8587#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
8588#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
8589#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
8590#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
8591#define GPIO_MODER_MODER9_Pos (18U)
8592#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
8593#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
8594#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
8595#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
8596#define GPIO_MODER_MODER10_Pos (20U)
8597#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
8598#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
8599#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
8600#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
8601#define GPIO_MODER_MODER11_Pos (22U)
8602#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
8603#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
8604#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
8605#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
8606#define GPIO_MODER_MODER12_Pos (24U)
8607#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
8608#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
8609#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
8610#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
8611#define GPIO_MODER_MODER13_Pos (26U)
8612#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
8613#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
8614#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
8615#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
8616#define GPIO_MODER_MODER14_Pos (28U)
8617#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
8618#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
8619#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
8620#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
8621#define GPIO_MODER_MODER15_Pos (30U)
8622#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
8623#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
8624#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
8625#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
8627/****************** Bits definition for GPIO_OTYPER register ****************/
8628#define GPIO_OTYPER_OT0_Pos (0U)
8629#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
8630#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8631#define GPIO_OTYPER_OT1_Pos (1U)
8632#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
8633#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8634#define GPIO_OTYPER_OT2_Pos (2U)
8635#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
8636#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8637#define GPIO_OTYPER_OT3_Pos (3U)
8638#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
8639#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8640#define GPIO_OTYPER_OT4_Pos (4U)
8641#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
8642#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8643#define GPIO_OTYPER_OT5_Pos (5U)
8644#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
8645#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8646#define GPIO_OTYPER_OT6_Pos (6U)
8647#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
8648#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8649#define GPIO_OTYPER_OT7_Pos (7U)
8650#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
8651#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8652#define GPIO_OTYPER_OT8_Pos (8U)
8653#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
8654#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8655#define GPIO_OTYPER_OT9_Pos (9U)
8656#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
8657#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8658#define GPIO_OTYPER_OT10_Pos (10U)
8659#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
8660#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8661#define GPIO_OTYPER_OT11_Pos (11U)
8662#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
8663#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8664#define GPIO_OTYPER_OT12_Pos (12U)
8665#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
8666#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8667#define GPIO_OTYPER_OT13_Pos (13U)
8668#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
8669#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8670#define GPIO_OTYPER_OT14_Pos (14U)
8671#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
8672#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8673#define GPIO_OTYPER_OT15_Pos (15U)
8674#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
8675#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8676
8677/* Legacy defines */
8678#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8679#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8680#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8681#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8682#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8683#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8684#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8685#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8686#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8687#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8688#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8689#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8690#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8691#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8692#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8693#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8694
8695/****************** Bits definition for GPIO_OSPEEDR register ***************/
8696#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
8697#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
8698#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
8699#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
8700#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
8701#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
8702#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
8703#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
8704#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
8705#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
8706#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
8707#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
8708#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
8709#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
8710#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
8711#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
8712#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
8713#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
8714#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
8715#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
8716#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
8717#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
8718#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
8719#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
8720#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
8721#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
8722#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
8723#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
8724#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
8725#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
8726#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
8727#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
8728#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
8729#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
8730#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
8731#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
8732#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
8733#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
8734#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
8735#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
8736#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
8737#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
8738#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
8739#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
8740#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
8741#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
8742#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
8743#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
8744#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
8745#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
8746#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
8747#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
8748#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
8749#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
8750#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
8751#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
8752#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
8753#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
8754#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
8755#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
8756#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
8757#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
8758#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
8759#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
8760#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
8761#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
8762#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
8763#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
8764#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
8765#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
8766#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
8767#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
8768#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
8769#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
8770#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
8771#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
8772#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
8773#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
8774#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
8775#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
8777/* legacy defines */
8778#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
8779#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
8780#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
8781#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
8782#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
8783#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
8784#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
8785#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
8786#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
8787#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
8788#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
8789#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
8790#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
8791#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
8792#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
8793#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
8794#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
8795#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
8796#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
8797#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
8798#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
8799#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
8800#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
8801#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
8802#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
8803#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
8804#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
8805#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
8806#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
8807#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
8808#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
8809#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
8810#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
8811#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
8812#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
8813#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
8814#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
8815#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
8816#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
8817#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
8818#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
8819#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
8820#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
8821#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
8822#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
8823#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
8824#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
8825#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
8826#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
8827#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
8828#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
8829#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
8830#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
8831#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
8832#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
8833#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
8834#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
8835#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
8836#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
8837#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
8838#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
8839#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
8840#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
8841#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
8842#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
8843#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
8844#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
8845#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
8846#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
8847#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
8848#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
8849#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
8850#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
8851#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
8852#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
8853#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
8854#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
8855#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
8856#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
8857#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
8858
8859/****************** Bits definition for GPIO_PUPDR register *****************/
8860#define GPIO_PUPDR_PUPDR0_Pos (0U)
8861#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos)
8862#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
8863#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos)
8864#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos)
8865#define GPIO_PUPDR_PUPDR1_Pos (2U)
8866#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos)
8867#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
8868#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos)
8869#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos)
8870#define GPIO_PUPDR_PUPDR2_Pos (4U)
8871#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos)
8872#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
8873#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos)
8874#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos)
8875#define GPIO_PUPDR_PUPDR3_Pos (6U)
8876#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos)
8877#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
8878#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos)
8879#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos)
8880#define GPIO_PUPDR_PUPDR4_Pos (8U)
8881#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos)
8882#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
8883#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos)
8884#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos)
8885#define GPIO_PUPDR_PUPDR5_Pos (10U)
8886#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos)
8887#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
8888#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos)
8889#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos)
8890#define GPIO_PUPDR_PUPDR6_Pos (12U)
8891#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos)
8892#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
8893#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos)
8894#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos)
8895#define GPIO_PUPDR_PUPDR7_Pos (14U)
8896#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos)
8897#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
8898#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos)
8899#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos)
8900#define GPIO_PUPDR_PUPDR8_Pos (16U)
8901#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos)
8902#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
8903#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos)
8904#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos)
8905#define GPIO_PUPDR_PUPDR9_Pos (18U)
8906#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos)
8907#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
8908#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos)
8909#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos)
8910#define GPIO_PUPDR_PUPDR10_Pos (20U)
8911#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos)
8912#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
8913#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)
8914#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)
8915#define GPIO_PUPDR_PUPDR11_Pos (22U)
8916#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos)
8917#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
8918#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)
8919#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)
8920#define GPIO_PUPDR_PUPDR12_Pos (24U)
8921#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos)
8922#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
8923#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)
8924#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)
8925#define GPIO_PUPDR_PUPDR13_Pos (26U)
8926#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos)
8927#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
8928#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)
8929#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)
8930#define GPIO_PUPDR_PUPDR14_Pos (28U)
8931#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos)
8932#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
8933#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)
8934#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)
8935#define GPIO_PUPDR_PUPDR15_Pos (30U)
8936#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos)
8937#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
8938#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)
8939#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)
8941/****************** Bits definition for GPIO_IDR register *******************/
8942#define GPIO_IDR_ID0_Pos (0U)
8943#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
8944#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8945#define GPIO_IDR_ID1_Pos (1U)
8946#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
8947#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8948#define GPIO_IDR_ID2_Pos (2U)
8949#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
8950#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8951#define GPIO_IDR_ID3_Pos (3U)
8952#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
8953#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8954#define GPIO_IDR_ID4_Pos (4U)
8955#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
8956#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8957#define GPIO_IDR_ID5_Pos (5U)
8958#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
8959#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8960#define GPIO_IDR_ID6_Pos (6U)
8961#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
8962#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8963#define GPIO_IDR_ID7_Pos (7U)
8964#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
8965#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8966#define GPIO_IDR_ID8_Pos (8U)
8967#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
8968#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8969#define GPIO_IDR_ID9_Pos (9U)
8970#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
8971#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8972#define GPIO_IDR_ID10_Pos (10U)
8973#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
8974#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8975#define GPIO_IDR_ID11_Pos (11U)
8976#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
8977#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8978#define GPIO_IDR_ID12_Pos (12U)
8979#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
8980#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8981#define GPIO_IDR_ID13_Pos (13U)
8982#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
8983#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8984#define GPIO_IDR_ID14_Pos (14U)
8985#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
8986#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8987#define GPIO_IDR_ID15_Pos (15U)
8988#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
8989#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8990
8991/* Legacy defines */
8992#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8993#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8994#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8995#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8996#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8997#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8998#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8999#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
9000#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
9001#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
9002#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
9003#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
9004#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
9005#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
9006#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
9007#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
9008
9009/****************** Bits definition for GPIO_ODR register *******************/
9010#define GPIO_ODR_OD0_Pos (0U)
9011#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
9012#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
9013#define GPIO_ODR_OD1_Pos (1U)
9014#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
9015#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
9016#define GPIO_ODR_OD2_Pos (2U)
9017#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
9018#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
9019#define GPIO_ODR_OD3_Pos (3U)
9020#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
9021#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
9022#define GPIO_ODR_OD4_Pos (4U)
9023#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
9024#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
9025#define GPIO_ODR_OD5_Pos (5U)
9026#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
9027#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
9028#define GPIO_ODR_OD6_Pos (6U)
9029#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
9030#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
9031#define GPIO_ODR_OD7_Pos (7U)
9032#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
9033#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
9034#define GPIO_ODR_OD8_Pos (8U)
9035#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
9036#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
9037#define GPIO_ODR_OD9_Pos (9U)
9038#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
9039#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
9040#define GPIO_ODR_OD10_Pos (10U)
9041#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
9042#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
9043#define GPIO_ODR_OD11_Pos (11U)
9044#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
9045#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
9046#define GPIO_ODR_OD12_Pos (12U)
9047#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
9048#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
9049#define GPIO_ODR_OD13_Pos (13U)
9050#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
9051#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
9052#define GPIO_ODR_OD14_Pos (14U)
9053#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
9054#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
9055#define GPIO_ODR_OD15_Pos (15U)
9056#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
9057#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
9058
9059/* Legacy defines */
9060#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
9061#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
9062#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
9063#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
9064#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
9065#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
9066#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
9067#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
9068#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
9069#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
9070#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
9071#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
9072#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
9073#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
9074#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
9075#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
9076
9077/****************** Bits definition for GPIO_BSRR register ******************/
9078#define GPIO_BSRR_BS0_Pos (0U)
9079#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
9080#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
9081#define GPIO_BSRR_BS1_Pos (1U)
9082#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
9083#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
9084#define GPIO_BSRR_BS2_Pos (2U)
9085#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
9086#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
9087#define GPIO_BSRR_BS3_Pos (3U)
9088#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
9089#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
9090#define GPIO_BSRR_BS4_Pos (4U)
9091#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
9092#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
9093#define GPIO_BSRR_BS5_Pos (5U)
9094#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
9095#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
9096#define GPIO_BSRR_BS6_Pos (6U)
9097#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
9098#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
9099#define GPIO_BSRR_BS7_Pos (7U)
9100#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
9101#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
9102#define GPIO_BSRR_BS8_Pos (8U)
9103#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
9104#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
9105#define GPIO_BSRR_BS9_Pos (9U)
9106#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
9107#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
9108#define GPIO_BSRR_BS10_Pos (10U)
9109#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
9110#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
9111#define GPIO_BSRR_BS11_Pos (11U)
9112#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
9113#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
9114#define GPIO_BSRR_BS12_Pos (12U)
9115#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
9116#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
9117#define GPIO_BSRR_BS13_Pos (13U)
9118#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
9119#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
9120#define GPIO_BSRR_BS14_Pos (14U)
9121#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
9122#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
9123#define GPIO_BSRR_BS15_Pos (15U)
9124#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
9125#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
9126#define GPIO_BSRR_BR0_Pos (16U)
9127#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
9128#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
9129#define GPIO_BSRR_BR1_Pos (17U)
9130#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
9131#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
9132#define GPIO_BSRR_BR2_Pos (18U)
9133#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
9134#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
9135#define GPIO_BSRR_BR3_Pos (19U)
9136#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
9137#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
9138#define GPIO_BSRR_BR4_Pos (20U)
9139#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
9140#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
9141#define GPIO_BSRR_BR5_Pos (21U)
9142#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
9143#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
9144#define GPIO_BSRR_BR6_Pos (22U)
9145#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
9146#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
9147#define GPIO_BSRR_BR7_Pos (23U)
9148#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
9149#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
9150#define GPIO_BSRR_BR8_Pos (24U)
9151#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
9152#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
9153#define GPIO_BSRR_BR9_Pos (25U)
9154#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
9155#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
9156#define GPIO_BSRR_BR10_Pos (26U)
9157#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
9158#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
9159#define GPIO_BSRR_BR11_Pos (27U)
9160#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
9161#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
9162#define GPIO_BSRR_BR12_Pos (28U)
9163#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
9164#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
9165#define GPIO_BSRR_BR13_Pos (29U)
9166#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
9167#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
9168#define GPIO_BSRR_BR14_Pos (30U)
9169#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
9170#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
9171#define GPIO_BSRR_BR15_Pos (31U)
9172#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
9173#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
9174
9175/* Legacy defines */
9176#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
9177#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
9178#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
9179#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
9180#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
9181#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
9182#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
9183#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
9184#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
9185#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
9186#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
9187#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
9188#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
9189#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
9190#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
9191#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
9192#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
9193#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
9194#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
9195#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
9196#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
9197#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
9198#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
9199#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
9200#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
9201#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
9202#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
9203#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
9204#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
9205#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
9206#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
9207#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
9208
9209/****************** Bit definition for GPIO_LCKR register *********************/
9210#define GPIO_LCKR_LCK0_Pos (0U)
9211#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
9212#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
9213#define GPIO_LCKR_LCK1_Pos (1U)
9214#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
9215#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
9216#define GPIO_LCKR_LCK2_Pos (2U)
9217#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
9218#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
9219#define GPIO_LCKR_LCK3_Pos (3U)
9220#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
9221#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
9222#define GPIO_LCKR_LCK4_Pos (4U)
9223#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
9224#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
9225#define GPIO_LCKR_LCK5_Pos (5U)
9226#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
9227#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
9228#define GPIO_LCKR_LCK6_Pos (6U)
9229#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
9230#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
9231#define GPIO_LCKR_LCK7_Pos (7U)
9232#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
9233#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
9234#define GPIO_LCKR_LCK8_Pos (8U)
9235#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
9236#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
9237#define GPIO_LCKR_LCK9_Pos (9U)
9238#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
9239#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
9240#define GPIO_LCKR_LCK10_Pos (10U)
9241#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
9242#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
9243#define GPIO_LCKR_LCK11_Pos (11U)
9244#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
9245#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
9246#define GPIO_LCKR_LCK12_Pos (12U)
9247#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
9248#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
9249#define GPIO_LCKR_LCK13_Pos (13U)
9250#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
9251#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
9252#define GPIO_LCKR_LCK14_Pos (14U)
9253#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
9254#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
9255#define GPIO_LCKR_LCK15_Pos (15U)
9256#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
9257#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
9258#define GPIO_LCKR_LCKK_Pos (16U)
9259#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
9260#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
9261
9262/****************** Bit definition for GPIO_AFRL register *********************/
9263#define GPIO_AFRL_AFRL0_Pos (0U)
9264#define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos)
9265#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
9266#define GPIO_AFRL_AFRL0_0 (0x1UL << GPIO_AFRL_AFRL0_Pos)
9267#define GPIO_AFRL_AFRL0_1 (0x2UL << GPIO_AFRL_AFRL0_Pos)
9268#define GPIO_AFRL_AFRL0_2 (0x4UL << GPIO_AFRL_AFRL0_Pos)
9269#define GPIO_AFRL_AFRL0_3 (0x8UL << GPIO_AFRL_AFRL0_Pos)
9270#define GPIO_AFRL_AFRL1_Pos (4U)
9271#define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos)
9272#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
9273#define GPIO_AFRL_AFRL1_0 (0x1UL << GPIO_AFRL_AFRL1_Pos)
9274#define GPIO_AFRL_AFRL1_1 (0x2UL << GPIO_AFRL_AFRL1_Pos)
9275#define GPIO_AFRL_AFRL1_2 (0x4UL << GPIO_AFRL_AFRL1_Pos)
9276#define GPIO_AFRL_AFRL1_3 (0x8UL << GPIO_AFRL_AFRL1_Pos)
9277#define GPIO_AFRL_AFRL2_Pos (8U)
9278#define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos)
9279#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
9280#define GPIO_AFRL_AFRL2_0 (0x1UL << GPIO_AFRL_AFRL2_Pos)
9281#define GPIO_AFRL_AFRL2_1 (0x2UL << GPIO_AFRL_AFRL2_Pos)
9282#define GPIO_AFRL_AFRL2_2 (0x4UL << GPIO_AFRL_AFRL2_Pos)
9283#define GPIO_AFRL_AFRL2_3 (0x8UL << GPIO_AFRL_AFRL2_Pos)
9284#define GPIO_AFRL_AFRL3_Pos (12U)
9285#define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos)
9286#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
9287#define GPIO_AFRL_AFRL3_0 (0x1UL << GPIO_AFRL_AFRL3_Pos)
9288#define GPIO_AFRL_AFRL3_1 (0x2UL << GPIO_AFRL_AFRL3_Pos)
9289#define GPIO_AFRL_AFRL3_2 (0x4UL << GPIO_AFRL_AFRL3_Pos)
9290#define GPIO_AFRL_AFRL3_3 (0x8UL << GPIO_AFRL_AFRL3_Pos)
9291#define GPIO_AFRL_AFRL4_Pos (16U)
9292#define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos)
9293#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
9294#define GPIO_AFRL_AFRL4_0 (0x1UL << GPIO_AFRL_AFRL4_Pos)
9295#define GPIO_AFRL_AFRL4_1 (0x2UL << GPIO_AFRL_AFRL4_Pos)
9296#define GPIO_AFRL_AFRL4_2 (0x4UL << GPIO_AFRL_AFRL4_Pos)
9297#define GPIO_AFRL_AFRL4_3 (0x8UL << GPIO_AFRL_AFRL4_Pos)
9298#define GPIO_AFRL_AFRL5_Pos (20U)
9299#define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos)
9300#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
9301#define GPIO_AFRL_AFRL5_0 (0x1UL << GPIO_AFRL_AFRL5_Pos)
9302#define GPIO_AFRL_AFRL5_1 (0x2UL << GPIO_AFRL_AFRL5_Pos)
9303#define GPIO_AFRL_AFRL5_2 (0x4UL << GPIO_AFRL_AFRL5_Pos)
9304#define GPIO_AFRL_AFRL5_3 (0x8UL << GPIO_AFRL_AFRL5_Pos)
9305#define GPIO_AFRL_AFRL6_Pos (24U)
9306#define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos)
9307#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
9308#define GPIO_AFRL_AFRL6_0 (0x1UL << GPIO_AFRL_AFRL6_Pos)
9309#define GPIO_AFRL_AFRL6_1 (0x2UL << GPIO_AFRL_AFRL6_Pos)
9310#define GPIO_AFRL_AFRL6_2 (0x4UL << GPIO_AFRL_AFRL6_Pos)
9311#define GPIO_AFRL_AFRL6_3 (0x8UL << GPIO_AFRL_AFRL6_Pos)
9312#define GPIO_AFRL_AFRL7_Pos (28U)
9313#define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos)
9314#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
9315#define GPIO_AFRL_AFRL7_0 (0x1UL << GPIO_AFRL_AFRL7_Pos)
9316#define GPIO_AFRL_AFRL7_1 (0x2UL << GPIO_AFRL_AFRL7_Pos)
9317#define GPIO_AFRL_AFRL7_2 (0x4UL << GPIO_AFRL_AFRL7_Pos)
9318#define GPIO_AFRL_AFRL7_3 (0x8UL << GPIO_AFRL_AFRL7_Pos)
9320/****************** Bit definition for GPIO_AFRH register *********************/
9321#define GPIO_AFRH_AFRH0_Pos (0U)
9322#define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos)
9323#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
9324#define GPIO_AFRH_AFRH0_0 (0x1UL << GPIO_AFRH_AFRH0_Pos)
9325#define GPIO_AFRH_AFRH0_1 (0x2UL << GPIO_AFRH_AFRH0_Pos)
9326#define GPIO_AFRH_AFRH0_2 (0x4UL << GPIO_AFRH_AFRH0_Pos)
9327#define GPIO_AFRH_AFRH0_3 (0x8UL << GPIO_AFRH_AFRH0_Pos)
9328#define GPIO_AFRH_AFRH1_Pos (4U)
9329#define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos)
9330#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
9331#define GPIO_AFRH_AFRH1_0 (0x1UL << GPIO_AFRH_AFRH1_Pos)
9332#define GPIO_AFRH_AFRH1_1 (0x2UL << GPIO_AFRH_AFRH1_Pos)
9333#define GPIO_AFRH_AFRH1_2 (0x4UL << GPIO_AFRH_AFRH1_Pos)
9334#define GPIO_AFRH_AFRH1_3 (0x8UL << GPIO_AFRH_AFRH1_Pos)
9335#define GPIO_AFRH_AFRH2_Pos (8U)
9336#define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos)
9337#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
9338#define GPIO_AFRH_AFRH2_0 (0x1UL << GPIO_AFRH_AFRH2_Pos)
9339#define GPIO_AFRH_AFRH2_1 (0x2UL << GPIO_AFRH_AFRH2_Pos)
9340#define GPIO_AFRH_AFRH2_2 (0x4UL << GPIO_AFRH_AFRH2_Pos)
9341#define GPIO_AFRH_AFRH2_3 (0x8UL << GPIO_AFRH_AFRH2_Pos)
9342#define GPIO_AFRH_AFRH3_Pos (12U)
9343#define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos)
9344#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
9345#define GPIO_AFRH_AFRH3_0 (0x1UL << GPIO_AFRH_AFRH3_Pos)
9346#define GPIO_AFRH_AFRH3_1 (0x2UL << GPIO_AFRH_AFRH3_Pos)
9347#define GPIO_AFRH_AFRH3_2 (0x4UL << GPIO_AFRH_AFRH3_Pos)
9348#define GPIO_AFRH_AFRH3_3 (0x8UL << GPIO_AFRH_AFRH3_Pos)
9349#define GPIO_AFRH_AFRH4_Pos (16U)
9350#define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos)
9351#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
9352#define GPIO_AFRH_AFRH4_0 (0x1UL << GPIO_AFRH_AFRH4_Pos)
9353#define GPIO_AFRH_AFRH4_1 (0x2UL << GPIO_AFRH_AFRH4_Pos)
9354#define GPIO_AFRH_AFRH4_2 (0x4UL << GPIO_AFRH_AFRH4_Pos)
9355#define GPIO_AFRH_AFRH4_3 (0x8UL << GPIO_AFRH_AFRH4_Pos)
9356#define GPIO_AFRH_AFRH5_Pos (20U)
9357#define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos)
9358#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
9359#define GPIO_AFRH_AFRH5_0 (0x1UL << GPIO_AFRH_AFRH5_Pos)
9360#define GPIO_AFRH_AFRH5_1 (0x2UL << GPIO_AFRH_AFRH5_Pos)
9361#define GPIO_AFRH_AFRH5_2 (0x4UL << GPIO_AFRH_AFRH5_Pos)
9362#define GPIO_AFRH_AFRH5_3 (0x8UL << GPIO_AFRH_AFRH5_Pos)
9363#define GPIO_AFRH_AFRH6_Pos (24U)
9364#define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos)
9365#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
9366#define GPIO_AFRH_AFRH6_0 (0x1UL << GPIO_AFRH_AFRH6_Pos)
9367#define GPIO_AFRH_AFRH6_1 (0x2UL << GPIO_AFRH_AFRH6_Pos)
9368#define GPIO_AFRH_AFRH6_2 (0x4UL << GPIO_AFRH_AFRH6_Pos)
9369#define GPIO_AFRH_AFRH6_3 (0x8UL << GPIO_AFRH_AFRH6_Pos)
9370#define GPIO_AFRH_AFRH7_Pos (28U)
9371#define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos)
9372#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
9373#define GPIO_AFRH_AFRH7_0 (0x1UL << GPIO_AFRH_AFRH7_Pos)
9374#define GPIO_AFRH_AFRH7_1 (0x2UL << GPIO_AFRH_AFRH7_Pos)
9375#define GPIO_AFRH_AFRH7_2 (0x4UL << GPIO_AFRH_AFRH7_Pos)
9376#define GPIO_AFRH_AFRH7_3 (0x8UL << GPIO_AFRH_AFRH7_Pos)
9378/******************************************************************************/
9379/* */
9380/* HASH */
9381/* */
9382/******************************************************************************/
9383/****************** Bits definition for HASH_CR register ********************/
9384#define HASH_CR_INIT_Pos (2U)
9385#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos)
9386#define HASH_CR_INIT HASH_CR_INIT_Msk
9387#define HASH_CR_DMAE_Pos (3U)
9388#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos)
9389#define HASH_CR_DMAE HASH_CR_DMAE_Msk
9390#define HASH_CR_DATATYPE_Pos (4U)
9391#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos)
9392#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
9393#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos)
9394#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos)
9395#define HASH_CR_MODE_Pos (6U)
9396#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos)
9397#define HASH_CR_MODE HASH_CR_MODE_Msk
9398#define HASH_CR_ALGO_Pos (7U)
9399#define HASH_CR_ALGO_Msk (0x801UL << HASH_CR_ALGO_Pos)
9400#define HASH_CR_ALGO HASH_CR_ALGO_Msk
9401#define HASH_CR_ALGO_0 (0x001UL << HASH_CR_ALGO_Pos)
9402#define HASH_CR_ALGO_1 (0x800UL << HASH_CR_ALGO_Pos)
9403#define HASH_CR_NBW_Pos (8U)
9404#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos)
9405#define HASH_CR_NBW HASH_CR_NBW_Msk
9406#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos)
9407#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos)
9408#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos)
9409#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos)
9410#define HASH_CR_DINNE_Pos (12U)
9411#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos)
9412#define HASH_CR_DINNE HASH_CR_DINNE_Msk
9413#define HASH_CR_MDMAT_Pos (13U)
9414#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos)
9415#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
9416#define HASH_CR_LKEY_Pos (16U)
9417#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos)
9418#define HASH_CR_LKEY HASH_CR_LKEY_Msk
9419
9420/****************** Bits definition for HASH_STR register *******************/
9421#define HASH_STR_NBLW_Pos (0U)
9422#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos)
9423#define HASH_STR_NBLW HASH_STR_NBLW_Msk
9424#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos)
9425#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos)
9426#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos)
9427#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos)
9428#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos)
9429#define HASH_STR_DCAL_Pos (8U)
9430#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos)
9431#define HASH_STR_DCAL HASH_STR_DCAL_Msk
9432
9433/* legacy defines */
9434#define HASH_STR_NBW HASH_STR_NBLW
9435#define HASH_STR_NBW_0 HASH_STR_NBLW_0
9436#define HASH_STR_NBW_1 HASH_STR_NBLW_1
9437#define HASH_STR_NBW_2 HASH_STR_NBLW_2
9438#define HASH_STR_NBW_3 HASH_STR_NBLW_3
9439#define HASH_STR_NBW_4 HASH_STR_NBLW_4
9440
9441/****************** Bits definition for HASH_IMR register *******************/
9442#define HASH_IMR_DINIE_Pos (0U)
9443#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos)
9444#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
9445#define HASH_IMR_DCIE_Pos (1U)
9446#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos)
9447#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
9448
9449/* legacy defines */
9450#define HASH_IMR_DINIM HASH_IMR_DINIE
9451#define HASH_IMR_DCIM HASH_IMR_DCIE
9452/****************** Bits definition for HASH_SR register ********************/
9453#define HASH_SR_DINIS_Pos (0U)
9454#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos)
9455#define HASH_SR_DINIS HASH_SR_DINIS_Msk
9456#define HASH_SR_DCIS_Pos (1U)
9457#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos)
9458#define HASH_SR_DCIS HASH_SR_DCIS_Msk
9459#define HASH_SR_DMAS_Pos (2U)
9460#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos)
9461#define HASH_SR_DMAS HASH_SR_DMAS_Msk
9462#define HASH_SR_BUSY_Pos (3U)
9463#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos)
9464#define HASH_SR_BUSY HASH_SR_BUSY_Msk
9465
9466/******************************************************************************/
9467/* */
9468/* Inter-integrated Circuit Interface (I2C) */
9469/* */
9470/******************************************************************************/
9471/******************* Bit definition for I2C_CR1 register *******************/
9472#define I2C_CR1_PE_Pos (0U)
9473#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
9474#define I2C_CR1_PE I2C_CR1_PE_Msk
9475#define I2C_CR1_TXIE_Pos (1U)
9476#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
9477#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
9478#define I2C_CR1_RXIE_Pos (2U)
9479#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
9480#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
9481#define I2C_CR1_ADDRIE_Pos (3U)
9482#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
9483#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
9484#define I2C_CR1_NACKIE_Pos (4U)
9485#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
9486#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
9487#define I2C_CR1_STOPIE_Pos (5U)
9488#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
9489#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
9490#define I2C_CR1_TCIE_Pos (6U)
9491#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
9492#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
9493#define I2C_CR1_ERRIE_Pos (7U)
9494#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
9495#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
9496#define I2C_CR1_DNF_Pos (8U)
9497#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
9498#define I2C_CR1_DNF I2C_CR1_DNF_Msk
9499#define I2C_CR1_ANFOFF_Pos (12U)
9500#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
9501#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
9502#define I2C_CR1_TXDMAEN_Pos (14U)
9503#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
9504#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
9505#define I2C_CR1_RXDMAEN_Pos (15U)
9506#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
9507#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
9508#define I2C_CR1_SBC_Pos (16U)
9509#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
9510#define I2C_CR1_SBC I2C_CR1_SBC_Msk
9511#define I2C_CR1_NOSTRETCH_Pos (17U)
9512#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
9513#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
9514#define I2C_CR1_GCEN_Pos (19U)
9515#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
9516#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
9517#define I2C_CR1_SMBHEN_Pos (20U)
9518#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
9519#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
9520#define I2C_CR1_SMBDEN_Pos (21U)
9521#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
9522#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
9523#define I2C_CR1_ALERTEN_Pos (22U)
9524#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
9525#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
9526#define I2C_CR1_PECEN_Pos (23U)
9527#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
9528#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
9530/* Legacy define */
9531#define I2C_CR1_DFN I2C_CR1_DNF
9533/****************** Bit definition for I2C_CR2 register ********************/
9534#define I2C_CR2_SADD_Pos (0U)
9535#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
9536#define I2C_CR2_SADD I2C_CR2_SADD_Msk
9537#define I2C_CR2_RD_WRN_Pos (10U)
9538#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
9539#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
9540#define I2C_CR2_ADD10_Pos (11U)
9541#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
9542#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
9543#define I2C_CR2_HEAD10R_Pos (12U)
9544#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
9545#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
9546#define I2C_CR2_START_Pos (13U)
9547#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
9548#define I2C_CR2_START I2C_CR2_START_Msk
9549#define I2C_CR2_STOP_Pos (14U)
9550#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
9551#define I2C_CR2_STOP I2C_CR2_STOP_Msk
9552#define I2C_CR2_NACK_Pos (15U)
9553#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
9554#define I2C_CR2_NACK I2C_CR2_NACK_Msk
9555#define I2C_CR2_NBYTES_Pos (16U)
9556#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
9557#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
9558#define I2C_CR2_RELOAD_Pos (24U)
9559#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
9560#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
9561#define I2C_CR2_AUTOEND_Pos (25U)
9562#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
9563#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
9564#define I2C_CR2_PECBYTE_Pos (26U)
9565#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
9566#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
9568/******************* Bit definition for I2C_OAR1 register ******************/
9569#define I2C_OAR1_OA1_Pos (0U)
9570#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
9571#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
9572#define I2C_OAR1_OA1MODE_Pos (10U)
9573#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
9574#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
9575#define I2C_OAR1_OA1EN_Pos (15U)
9576#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
9577#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
9579/******************* Bit definition for I2C_OAR2 register ******************/
9580#define I2C_OAR2_OA2_Pos (1U)
9581#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
9582#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
9583#define I2C_OAR2_OA2MSK_Pos (8U)
9584#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
9585#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
9586#define I2C_OAR2_OA2NOMASK 0x00000000U
9587#define I2C_OAR2_OA2MASK01_Pos (8U)
9588#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
9589#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
9590#define I2C_OAR2_OA2MASK02_Pos (9U)
9591#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
9592#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
9593#define I2C_OAR2_OA2MASK03_Pos (8U)
9594#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
9595#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
9596#define I2C_OAR2_OA2MASK04_Pos (10U)
9597#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
9598#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
9599#define I2C_OAR2_OA2MASK05_Pos (8U)
9600#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
9601#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
9602#define I2C_OAR2_OA2MASK06_Pos (9U)
9603#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
9604#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
9605#define I2C_OAR2_OA2MASK07_Pos (8U)
9606#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
9607#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
9608#define I2C_OAR2_OA2EN_Pos (15U)
9609#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
9610#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
9612/******************* Bit definition for I2C_TIMINGR register *******************/
9613#define I2C_TIMINGR_SCLL_Pos (0U)
9614#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
9615#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
9616#define I2C_TIMINGR_SCLH_Pos (8U)
9617#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
9618#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
9619#define I2C_TIMINGR_SDADEL_Pos (16U)
9620#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
9621#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
9622#define I2C_TIMINGR_SCLDEL_Pos (20U)
9623#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
9624#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
9625#define I2C_TIMINGR_PRESC_Pos (28U)
9626#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
9627#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
9629/******************* Bit definition for I2C_TIMEOUTR register *******************/
9630#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9631#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
9632#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
9633#define I2C_TIMEOUTR_TIDLE_Pos (12U)
9634#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
9635#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
9636#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9637#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
9638#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
9639#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9640#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
9641#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
9642#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
9643#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
9644#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
9646/****************** Bit definition for I2C_ISR register *********************/
9647#define I2C_ISR_TXE_Pos (0U)
9648#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
9649#define I2C_ISR_TXE I2C_ISR_TXE_Msk
9650#define I2C_ISR_TXIS_Pos (1U)
9651#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
9652#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
9653#define I2C_ISR_RXNE_Pos (2U)
9654#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
9655#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
9656#define I2C_ISR_ADDR_Pos (3U)
9657#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
9658#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
9659#define I2C_ISR_NACKF_Pos (4U)
9660#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
9661#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
9662#define I2C_ISR_STOPF_Pos (5U)
9663#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
9664#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
9665#define I2C_ISR_TC_Pos (6U)
9666#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
9667#define I2C_ISR_TC I2C_ISR_TC_Msk
9668#define I2C_ISR_TCR_Pos (7U)
9669#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
9670#define I2C_ISR_TCR I2C_ISR_TCR_Msk
9671#define I2C_ISR_BERR_Pos (8U)
9672#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
9673#define I2C_ISR_BERR I2C_ISR_BERR_Msk
9674#define I2C_ISR_ARLO_Pos (9U)
9675#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
9676#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
9677#define I2C_ISR_OVR_Pos (10U)
9678#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
9679#define I2C_ISR_OVR I2C_ISR_OVR_Msk
9680#define I2C_ISR_PECERR_Pos (11U)
9681#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
9682#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
9683#define I2C_ISR_TIMEOUT_Pos (12U)
9684#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
9685#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
9686#define I2C_ISR_ALERT_Pos (13U)
9687#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
9688#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
9689#define I2C_ISR_BUSY_Pos (15U)
9690#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
9691#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
9692#define I2C_ISR_DIR_Pos (16U)
9693#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
9694#define I2C_ISR_DIR I2C_ISR_DIR_Msk
9695#define I2C_ISR_ADDCODE_Pos (17U)
9696#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
9697#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
9699/****************** Bit definition for I2C_ICR register *********************/
9700#define I2C_ICR_ADDRCF_Pos (3U)
9701#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
9702#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
9703#define I2C_ICR_NACKCF_Pos (4U)
9704#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
9705#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
9706#define I2C_ICR_STOPCF_Pos (5U)
9707#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
9708#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
9709#define I2C_ICR_BERRCF_Pos (8U)
9710#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
9711#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
9712#define I2C_ICR_ARLOCF_Pos (9U)
9713#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
9714#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
9715#define I2C_ICR_OVRCF_Pos (10U)
9716#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
9717#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
9718#define I2C_ICR_PECCF_Pos (11U)
9719#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
9720#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
9721#define I2C_ICR_TIMOUTCF_Pos (12U)
9722#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
9723#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
9724#define I2C_ICR_ALERTCF_Pos (13U)
9725#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
9726#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
9728/****************** Bit definition for I2C_PECR register *********************/
9729#define I2C_PECR_PEC_Pos (0U)
9730#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
9731#define I2C_PECR_PEC I2C_PECR_PEC_Msk
9733/****************** Bit definition for I2C_RXDR register *********************/
9734#define I2C_RXDR_RXDATA_Pos (0U)
9735#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
9736#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
9738/****************** Bit definition for I2C_TXDR register *********************/
9739#define I2C_TXDR_TXDATA_Pos (0U)
9740#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
9741#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
9744/******************************************************************************/
9745/* */
9746/* Independent WATCHDOG */
9747/* */
9748/******************************************************************************/
9749/******************* Bit definition for IWDG_KR register ********************/
9750#define IWDG_KR_KEY_Pos (0U)
9751#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
9752#define IWDG_KR_KEY IWDG_KR_KEY_Msk
9754/******************* Bit definition for IWDG_PR register ********************/
9755#define IWDG_PR_PR_Pos (0U)
9756#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
9757#define IWDG_PR_PR IWDG_PR_PR_Msk
9758#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
9759#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
9760#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
9762/******************* Bit definition for IWDG_RLR register *******************/
9763#define IWDG_RLR_RL_Pos (0U)
9764#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
9765#define IWDG_RLR_RL IWDG_RLR_RL_Msk
9767/******************* Bit definition for IWDG_SR register ********************/
9768#define IWDG_SR_PVU_Pos (0U)
9769#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
9770#define IWDG_SR_PVU IWDG_SR_PVU_Msk
9771#define IWDG_SR_RVU_Pos (1U)
9772#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
9773#define IWDG_SR_RVU IWDG_SR_RVU_Msk
9774#define IWDG_SR_WVU_Pos (2U)
9775#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
9776#define IWDG_SR_WVU IWDG_SR_WVU_Msk
9778/******************* Bit definition for IWDG_KR register ********************/
9779#define IWDG_WINR_WIN_Pos (0U)
9780#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
9781#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
9783/******************************************************************************/
9784/* */
9785/* LCD-TFT Display Controller (LTDC) */
9786/* */
9787/******************************************************************************/
9788
9789/******************** Bit definition for LTDC_SSCR register *****************/
9790
9791#define LTDC_SSCR_VSH_Pos (0U)
9792#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
9793#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
9794#define LTDC_SSCR_HSW_Pos (16U)
9795#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
9796#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
9798/******************** Bit definition for LTDC_BPCR register *****************/
9799
9800#define LTDC_BPCR_AVBP_Pos (0U)
9801#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
9802#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
9803#define LTDC_BPCR_AHBP_Pos (16U)
9804#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
9805#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
9807/******************** Bit definition for LTDC_AWCR register *****************/
9808
9809#define LTDC_AWCR_AAH_Pos (0U)
9810#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
9811#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
9812#define LTDC_AWCR_AAW_Pos (16U)
9813#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
9814#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
9816/******************** Bit definition for LTDC_TWCR register *****************/
9817
9818#define LTDC_TWCR_TOTALH_Pos (0U)
9819#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
9820#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
9821#define LTDC_TWCR_TOTALW_Pos (16U)
9822#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
9823#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
9825/******************** Bit definition for LTDC_GCR register ******************/
9826
9827#define LTDC_GCR_LTDCEN_Pos (0U)
9828#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
9829#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
9830#define LTDC_GCR_DBW_Pos (4U)
9831#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
9832#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
9833#define LTDC_GCR_DGW_Pos (8U)
9834#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
9835#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
9836#define LTDC_GCR_DRW_Pos (12U)
9837#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
9838#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
9839#define LTDC_GCR_DEN_Pos (16U)
9840#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
9841#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
9842#define LTDC_GCR_PCPOL_Pos (28U)
9843#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
9844#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
9845#define LTDC_GCR_DEPOL_Pos (29U)
9846#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
9847#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
9848#define LTDC_GCR_VSPOL_Pos (30U)
9849#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
9850#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
9851#define LTDC_GCR_HSPOL_Pos (31U)
9852#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
9853#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
9855/* Legacy define */
9856#define LTDC_GCR_DTEN LTDC_GCR_DEN
9857
9858/******************** Bit definition for LTDC_SRCR register *****************/
9859
9860#define LTDC_SRCR_IMR_Pos (0U)
9861#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
9862#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
9863#define LTDC_SRCR_VBR_Pos (1U)
9864#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
9865#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
9867/******************** Bit definition for LTDC_BCCR register *****************/
9868
9869#define LTDC_BCCR_BCBLUE_Pos (0U)
9870#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
9871#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
9872#define LTDC_BCCR_BCGREEN_Pos (8U)
9873#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
9874#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
9875#define LTDC_BCCR_BCRED_Pos (16U)
9876#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
9877#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
9879/******************** Bit definition for LTDC_IER register ******************/
9880
9881#define LTDC_IER_LIE_Pos (0U)
9882#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
9883#define LTDC_IER_LIE LTDC_IER_LIE_Msk
9884#define LTDC_IER_FUIE_Pos (1U)
9885#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
9886#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
9887#define LTDC_IER_TERRIE_Pos (2U)
9888#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
9889#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
9890#define LTDC_IER_RRIE_Pos (3U)
9891#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
9892#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
9894/******************** Bit definition for LTDC_ISR register ******************/
9895
9896#define LTDC_ISR_LIF_Pos (0U)
9897#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
9898#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
9899#define LTDC_ISR_FUIF_Pos (1U)
9900#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
9901#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
9902#define LTDC_ISR_TERRIF_Pos (2U)
9903#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
9904#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
9905#define LTDC_ISR_RRIF_Pos (3U)
9906#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
9907#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
9909/******************** Bit definition for LTDC_ICR register ******************/
9910
9911#define LTDC_ICR_CLIF_Pos (0U)
9912#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
9913#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
9914#define LTDC_ICR_CFUIF_Pos (1U)
9915#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
9916#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
9917#define LTDC_ICR_CTERRIF_Pos (2U)
9918#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
9919#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
9920#define LTDC_ICR_CRRIF_Pos (3U)
9921#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
9922#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
9924/******************** Bit definition for LTDC_LIPCR register ****************/
9925
9926#define LTDC_LIPCR_LIPOS_Pos (0U)
9927#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
9928#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
9930/******************** Bit definition for LTDC_CPSR register *****************/
9931
9932#define LTDC_CPSR_CYPOS_Pos (0U)
9933#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
9934#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
9935#define LTDC_CPSR_CXPOS_Pos (16U)
9936#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
9937#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
9939/******************** Bit definition for LTDC_CDSR register *****************/
9940
9941#define LTDC_CDSR_VDES_Pos (0U)
9942#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
9943#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
9944#define LTDC_CDSR_HDES_Pos (1U)
9945#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
9946#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
9947#define LTDC_CDSR_VSYNCS_Pos (2U)
9948#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
9949#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
9950#define LTDC_CDSR_HSYNCS_Pos (3U)
9951#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
9952#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
9954/******************** Bit definition for LTDC_LxCR register *****************/
9955
9956#define LTDC_LxCR_LEN_Pos (0U)
9957#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
9958#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
9959#define LTDC_LxCR_COLKEN_Pos (1U)
9960#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
9961#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
9962#define LTDC_LxCR_CLUTEN_Pos (4U)
9963#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
9964#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
9966/******************** Bit definition for LTDC_LxWHPCR register **************/
9967
9968#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
9969#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
9970#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
9971#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
9972#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
9973#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
9975/******************** Bit definition for LTDC_LxWVPCR register **************/
9976
9977#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
9978#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
9979#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
9980#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
9981#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
9982#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
9984/******************** Bit definition for LTDC_LxCKCR register ***************/
9985
9986#define LTDC_LxCKCR_CKBLUE_Pos (0U)
9987#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
9988#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
9989#define LTDC_LxCKCR_CKGREEN_Pos (8U)
9990#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
9991#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
9992#define LTDC_LxCKCR_CKRED_Pos (16U)
9993#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
9994#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
9996/******************** Bit definition for LTDC_LxPFCR register ***************/
9997
9998#define LTDC_LxPFCR_PF_Pos (0U)
9999#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
10000#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
10002/******************** Bit definition for LTDC_LxCACR register ***************/
10003
10004#define LTDC_LxCACR_CONSTA_Pos (0U)
10005#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
10006#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
10008/******************** Bit definition for LTDC_LxDCCR register ***************/
10009
10010#define LTDC_LxDCCR_DCBLUE_Pos (0U)
10011#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
10012#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
10013#define LTDC_LxDCCR_DCGREEN_Pos (8U)
10014#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
10015#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
10016#define LTDC_LxDCCR_DCRED_Pos (16U)
10017#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
10018#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
10019#define LTDC_LxDCCR_DCALPHA_Pos (24U)
10020#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
10021#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
10023/******************** Bit definition for LTDC_LxBFCR register ***************/
10024
10025#define LTDC_LxBFCR_BF2_Pos (0U)
10026#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
10027#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
10028#define LTDC_LxBFCR_BF1_Pos (8U)
10029#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
10030#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
10032/******************** Bit definition for LTDC_LxCFBAR register **************/
10033
10034#define LTDC_LxCFBAR_CFBADD_Pos (0U)
10035#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
10036#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
10038/******************** Bit definition for LTDC_LxCFBLR register **************/
10039
10040#define LTDC_LxCFBLR_CFBLL_Pos (0U)
10041#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
10042#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
10043#define LTDC_LxCFBLR_CFBP_Pos (16U)
10044#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
10045#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
10047/******************** Bit definition for LTDC_LxCFBLNR register *************/
10048
10049#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
10050#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
10051#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
10053/******************** Bit definition for LTDC_LxCLUTWR register *************/
10054
10055#define LTDC_LxCLUTWR_BLUE_Pos (0U)
10056#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
10057#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
10058#define LTDC_LxCLUTWR_GREEN_Pos (8U)
10059#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
10060#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
10061#define LTDC_LxCLUTWR_RED_Pos (16U)
10062#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
10063#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
10064#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
10065#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
10066#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
10068/******************************************************************************/
10069/* */
10070/* Power Control */
10071/* */
10072/******************************************************************************/
10073/******************** Bit definition for PWR_CR1 register ********************/
10074#define PWR_CR1_LPDS_Pos (0U)
10075#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos)
10076#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk
10077#define PWR_CR1_PDDS_Pos (1U)
10078#define PWR_CR1_PDDS_Msk (0x1UL << PWR_CR1_PDDS_Pos)
10079#define PWR_CR1_PDDS PWR_CR1_PDDS_Msk
10080#define PWR_CR1_CSBF_Pos (3U)
10081#define PWR_CR1_CSBF_Msk (0x1UL << PWR_CR1_CSBF_Pos)
10082#define PWR_CR1_CSBF PWR_CR1_CSBF_Msk
10083#define PWR_CR1_PVDE_Pos (4U)
10084#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos)
10085#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk
10086#define PWR_CR1_PLS_Pos (5U)
10087#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos)
10088#define PWR_CR1_PLS PWR_CR1_PLS_Msk
10089#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos)
10090#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos)
10091#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos)
10094#define PWR_CR1_PLS_LEV0 0x00000000U
10095#define PWR_CR1_PLS_LEV1_Pos (5U)
10096#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos)
10097#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk
10098#define PWR_CR1_PLS_LEV2_Pos (6U)
10099#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos)
10100#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk
10101#define PWR_CR1_PLS_LEV3_Pos (5U)
10102#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos)
10103#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk
10104#define PWR_CR1_PLS_LEV4_Pos (7U)
10105#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos)
10106#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk
10107#define PWR_CR1_PLS_LEV5_Pos (5U)
10108#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos)
10109#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk
10110#define PWR_CR1_PLS_LEV6_Pos (6U)
10111#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos)
10112#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk
10113#define PWR_CR1_PLS_LEV7_Pos (5U)
10114#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos)
10115#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk
10116#define PWR_CR1_DBP_Pos (8U)
10117#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
10118#define PWR_CR1_DBP PWR_CR1_DBP_Msk
10119#define PWR_CR1_FPDS_Pos (9U)
10120#define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos)
10121#define PWR_CR1_FPDS PWR_CR1_FPDS_Msk
10122#define PWR_CR1_LPUDS_Pos (10U)
10123#define PWR_CR1_LPUDS_Msk (0x1UL << PWR_CR1_LPUDS_Pos)
10124#define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk
10125#define PWR_CR1_MRUDS_Pos (11U)
10126#define PWR_CR1_MRUDS_Msk (0x1UL << PWR_CR1_MRUDS_Pos)
10127#define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk
10128#define PWR_CR1_ADCDC1_Pos (13U)
10129#define PWR_CR1_ADCDC1_Msk (0x1UL << PWR_CR1_ADCDC1_Pos)
10130#define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk
10131#define PWR_CR1_VOS_Pos (14U)
10132#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)
10133#define PWR_CR1_VOS PWR_CR1_VOS_Msk
10134#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)
10135#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)
10136#define PWR_CR1_ODEN_Pos (16U)
10137#define PWR_CR1_ODEN_Msk (0x1UL << PWR_CR1_ODEN_Pos)
10138#define PWR_CR1_ODEN PWR_CR1_ODEN_Msk
10139#define PWR_CR1_ODSWEN_Pos (17U)
10140#define PWR_CR1_ODSWEN_Msk (0x1UL << PWR_CR1_ODSWEN_Pos)
10141#define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk
10142#define PWR_CR1_UDEN_Pos (18U)
10143#define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos)
10144#define PWR_CR1_UDEN PWR_CR1_UDEN_Msk
10145#define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos)
10146#define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos)
10148/******************* Bit definition for PWR_CSR1 register ********************/
10149#define PWR_CSR1_WUIF_Pos (0U)
10150#define PWR_CSR1_WUIF_Msk (0x1UL << PWR_CSR1_WUIF_Pos)
10151#define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk
10152#define PWR_CSR1_SBF_Pos (1U)
10153#define PWR_CSR1_SBF_Msk (0x1UL << PWR_CSR1_SBF_Pos)
10154#define PWR_CSR1_SBF PWR_CSR1_SBF_Msk
10155#define PWR_CSR1_PVDO_Pos (2U)
10156#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos)
10157#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk
10158#define PWR_CSR1_BRR_Pos (3U)
10159#define PWR_CSR1_BRR_Msk (0x1UL << PWR_CSR1_BRR_Pos)
10160#define PWR_CSR1_BRR PWR_CSR1_BRR_Msk
10161#define PWR_CSR1_EIWUP_Pos (8U)
10162#define PWR_CSR1_EIWUP_Msk (0x1UL << PWR_CSR1_EIWUP_Pos)
10163#define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk
10164#define PWR_CSR1_BRE_Pos (9U)
10165#define PWR_CSR1_BRE_Msk (0x1UL << PWR_CSR1_BRE_Pos)
10166#define PWR_CSR1_BRE PWR_CSR1_BRE_Msk
10167#define PWR_CSR1_VOSRDY_Pos (14U)
10168#define PWR_CSR1_VOSRDY_Msk (0x1UL << PWR_CSR1_VOSRDY_Pos)
10169#define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk
10170#define PWR_CSR1_ODRDY_Pos (16U)
10171#define PWR_CSR1_ODRDY_Msk (0x1UL << PWR_CSR1_ODRDY_Pos)
10172#define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk
10173#define PWR_CSR1_ODSWRDY_Pos (17U)
10174#define PWR_CSR1_ODSWRDY_Msk (0x1UL << PWR_CSR1_ODSWRDY_Pos)
10175#define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk
10176#define PWR_CSR1_UDRDY_Pos (18U)
10177#define PWR_CSR1_UDRDY_Msk (0x3UL << PWR_CSR1_UDRDY_Pos)
10178#define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk
10180/* Legacy define */
10181#define PWR_CSR1_UDSWRDY PWR_CSR1_UDRDY
10182
10183/******************** Bit definition for PWR_CR2 register ********************/
10184#define PWR_CR2_CWUPF1_Pos (0U)
10185#define PWR_CR2_CWUPF1_Msk (0x1UL << PWR_CR2_CWUPF1_Pos)
10186#define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk
10187#define PWR_CR2_CWUPF2_Pos (1U)
10188#define PWR_CR2_CWUPF2_Msk (0x1UL << PWR_CR2_CWUPF2_Pos)
10189#define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk
10190#define PWR_CR2_CWUPF3_Pos (2U)
10191#define PWR_CR2_CWUPF3_Msk (0x1UL << PWR_CR2_CWUPF3_Pos)
10192#define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk
10193#define PWR_CR2_CWUPF4_Pos (3U)
10194#define PWR_CR2_CWUPF4_Msk (0x1UL << PWR_CR2_CWUPF4_Pos)
10195#define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk
10196#define PWR_CR2_CWUPF5_Pos (4U)
10197#define PWR_CR2_CWUPF5_Msk (0x1UL << PWR_CR2_CWUPF5_Pos)
10198#define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk
10199#define PWR_CR2_CWUPF6_Pos (5U)
10200#define PWR_CR2_CWUPF6_Msk (0x1UL << PWR_CR2_CWUPF6_Pos)
10201#define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk
10202#define PWR_CR2_WUPP1_Pos (8U)
10203#define PWR_CR2_WUPP1_Msk (0x1UL << PWR_CR2_WUPP1_Pos)
10204#define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk
10205#define PWR_CR2_WUPP2_Pos (9U)
10206#define PWR_CR2_WUPP2_Msk (0x1UL << PWR_CR2_WUPP2_Pos)
10207#define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk
10208#define PWR_CR2_WUPP3_Pos (10U)
10209#define PWR_CR2_WUPP3_Msk (0x1UL << PWR_CR2_WUPP3_Pos)
10210#define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk
10211#define PWR_CR2_WUPP4_Pos (11U)
10212#define PWR_CR2_WUPP4_Msk (0x1UL << PWR_CR2_WUPP4_Pos)
10213#define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk
10214#define PWR_CR2_WUPP5_Pos (12U)
10215#define PWR_CR2_WUPP5_Msk (0x1UL << PWR_CR2_WUPP5_Pos)
10216#define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk
10217#define PWR_CR2_WUPP6_Pos (13U)
10218#define PWR_CR2_WUPP6_Msk (0x1UL << PWR_CR2_WUPP6_Pos)
10219#define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk
10221/******************* Bit definition for PWR_CSR2 register ********************/
10222#define PWR_CSR2_WUPF1_Pos (0U)
10223#define PWR_CSR2_WUPF1_Msk (0x1UL << PWR_CSR2_WUPF1_Pos)
10224#define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk
10225#define PWR_CSR2_WUPF2_Pos (1U)
10226#define PWR_CSR2_WUPF2_Msk (0x1UL << PWR_CSR2_WUPF2_Pos)
10227#define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk
10228#define PWR_CSR2_WUPF3_Pos (2U)
10229#define PWR_CSR2_WUPF3_Msk (0x1UL << PWR_CSR2_WUPF3_Pos)
10230#define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk
10231#define PWR_CSR2_WUPF4_Pos (3U)
10232#define PWR_CSR2_WUPF4_Msk (0x1UL << PWR_CSR2_WUPF4_Pos)
10233#define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk
10234#define PWR_CSR2_WUPF5_Pos (4U)
10235#define PWR_CSR2_WUPF5_Msk (0x1UL << PWR_CSR2_WUPF5_Pos)
10236#define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk
10237#define PWR_CSR2_WUPF6_Pos (5U)
10238#define PWR_CSR2_WUPF6_Msk (0x1UL << PWR_CSR2_WUPF6_Pos)
10239#define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk
10240#define PWR_CSR2_EWUP1_Pos (8U)
10241#define PWR_CSR2_EWUP1_Msk (0x1UL << PWR_CSR2_EWUP1_Pos)
10242#define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk
10243#define PWR_CSR2_EWUP2_Pos (9U)
10244#define PWR_CSR2_EWUP2_Msk (0x1UL << PWR_CSR2_EWUP2_Pos)
10245#define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk
10246#define PWR_CSR2_EWUP3_Pos (10U)
10247#define PWR_CSR2_EWUP3_Msk (0x1UL << PWR_CSR2_EWUP3_Pos)
10248#define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk
10249#define PWR_CSR2_EWUP4_Pos (11U)
10250#define PWR_CSR2_EWUP4_Msk (0x1UL << PWR_CSR2_EWUP4_Pos)
10251#define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk
10252#define PWR_CSR2_EWUP5_Pos (12U)
10253#define PWR_CSR2_EWUP5_Msk (0x1UL << PWR_CSR2_EWUP5_Pos)
10254#define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk
10255#define PWR_CSR2_EWUP6_Pos (13U)
10256#define PWR_CSR2_EWUP6_Msk (0x1UL << PWR_CSR2_EWUP6_Pos)
10257#define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk
10259/******************************************************************************/
10260/* */
10261/* QUADSPI */
10262/* */
10263/******************************************************************************/
10264/* QUADSPI IP version */
10265#define QSPI1_V1_0
10266/***************** Bit definition for QUADSPI_CR register *******************/
10267#define QUADSPI_CR_EN_Pos (0U)
10268#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
10269#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
10270#define QUADSPI_CR_ABORT_Pos (1U)
10271#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
10272#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
10273#define QUADSPI_CR_DMAEN_Pos (2U)
10274#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
10275#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
10276#define QUADSPI_CR_TCEN_Pos (3U)
10277#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
10278#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
10279#define QUADSPI_CR_SSHIFT_Pos (4U)
10280#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
10281#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
10282#define QUADSPI_CR_DFM_Pos (6U)
10283#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
10284#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
10285#define QUADSPI_CR_FSEL_Pos (7U)
10286#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
10287#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
10288#define QUADSPI_CR_FTHRES_Pos (8U)
10289#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
10290#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
10291#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos)
10292#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos)
10293#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos)
10294#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos)
10295#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
10296#define QUADSPI_CR_TEIE_Pos (16U)
10297#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
10298#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
10299#define QUADSPI_CR_TCIE_Pos (17U)
10300#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
10301#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
10302#define QUADSPI_CR_FTIE_Pos (18U)
10303#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
10304#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
10305#define QUADSPI_CR_SMIE_Pos (19U)
10306#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
10307#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
10308#define QUADSPI_CR_TOIE_Pos (20U)
10309#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
10310#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
10311#define QUADSPI_CR_APMS_Pos (22U)
10312#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
10313#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
10314#define QUADSPI_CR_PMM_Pos (23U)
10315#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
10316#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
10317#define QUADSPI_CR_PRESCALER_Pos (24U)
10318#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
10319#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
10320#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
10321#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
10322#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
10323#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
10324#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
10325#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
10326#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
10327#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
10329/***************** Bit definition for QUADSPI_DCR register ******************/
10330#define QUADSPI_DCR_CKMODE_Pos (0U)
10331#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
10332#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
10333#define QUADSPI_DCR_CSHT_Pos (8U)
10334#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
10335#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
10336#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
10337#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
10338#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
10339#define QUADSPI_DCR_FSIZE_Pos (16U)
10340#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
10341#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
10342#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
10343#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
10344#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
10345#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
10346#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
10348/****************** Bit definition for QUADSPI_SR register *******************/
10349#define QUADSPI_SR_TEF_Pos (0U)
10350#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
10351#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
10352#define QUADSPI_SR_TCF_Pos (1U)
10353#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
10354#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
10355#define QUADSPI_SR_FTF_Pos (2U)
10356#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
10357#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
10358#define QUADSPI_SR_SMF_Pos (3U)
10359#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
10360#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
10361#define QUADSPI_SR_TOF_Pos (4U)
10362#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
10363#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
10364#define QUADSPI_SR_BUSY_Pos (5U)
10365#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
10366#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
10367#define QUADSPI_SR_FLEVEL_Pos (8U)
10368#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
10369#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
10370#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
10371#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
10372#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
10373#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
10374#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
10375#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
10377/****************** Bit definition for QUADSPI_FCR register ******************/
10378#define QUADSPI_FCR_CTEF_Pos (0U)
10379#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
10380#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
10381#define QUADSPI_FCR_CTCF_Pos (1U)
10382#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
10383#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
10384#define QUADSPI_FCR_CSMF_Pos (3U)
10385#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
10386#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
10387#define QUADSPI_FCR_CTOF_Pos (4U)
10388#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
10389#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
10391/****************** Bit definition for QUADSPI_DLR register ******************/
10392#define QUADSPI_DLR_DL_Pos (0U)
10393#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
10394#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
10396/****************** Bit definition for QUADSPI_CCR register ******************/
10397#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
10398#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
10399#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
10400#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
10401#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
10402#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
10403#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
10404#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
10405#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
10406#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
10407#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
10408#define QUADSPI_CCR_IMODE_Pos (8U)
10409#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
10410#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
10411#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
10412#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
10413#define QUADSPI_CCR_ADMODE_Pos (10U)
10414#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
10415#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
10416#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
10417#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
10418#define QUADSPI_CCR_ADSIZE_Pos (12U)
10419#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
10420#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
10421#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
10422#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
10423#define QUADSPI_CCR_ABMODE_Pos (14U)
10424#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
10425#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
10426#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
10427#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
10428#define QUADSPI_CCR_ABSIZE_Pos (16U)
10429#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
10430#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
10431#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
10432#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
10433#define QUADSPI_CCR_DCYC_Pos (18U)
10434#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
10435#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
10436#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
10437#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
10438#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
10439#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
10440#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
10441#define QUADSPI_CCR_DMODE_Pos (24U)
10442#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
10443#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
10444#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
10445#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
10446#define QUADSPI_CCR_FMODE_Pos (26U)
10447#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
10448#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
10449#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
10450#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
10451#define QUADSPI_CCR_SIOO_Pos (28U)
10452#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
10453#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
10454#define QUADSPI_CCR_DHHC_Pos (30U)
10455#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
10456#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
10457#define QUADSPI_CCR_DDRM_Pos (31U)
10458#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
10459#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
10460/****************** Bit definition for QUADSPI_AR register *******************/
10461#define QUADSPI_AR_ADDRESS_Pos (0U)
10462#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
10463#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
10465/****************** Bit definition for QUADSPI_ABR register ******************/
10466#define QUADSPI_ABR_ALTERNATE_Pos (0U)
10467#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
10468#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
10470/****************** Bit definition for QUADSPI_DR register *******************/
10471#define QUADSPI_DR_DATA_Pos (0U)
10472#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
10473#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
10475/****************** Bit definition for QUADSPI_PSMKR register ****************/
10476#define QUADSPI_PSMKR_MASK_Pos (0U)
10477#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
10478#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
10480/****************** Bit definition for QUADSPI_PSMAR register ****************/
10481#define QUADSPI_PSMAR_MATCH_Pos (0U)
10482#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
10483#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
10485/****************** Bit definition for QUADSPI_PIR register *****************/
10486#define QUADSPI_PIR_INTERVAL_Pos (0U)
10487#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
10488#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
10490/****************** Bit definition for QUADSPI_LPTR register *****************/
10491#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
10492#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
10493#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
10495/******************************************************************************/
10496/* */
10497/* Reset and Clock Control */
10498/* */
10499/******************************************************************************/
10500/******************** Bit definition for RCC_CR register ********************/
10501#define RCC_CR_HSION_Pos (0U)
10502#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
10503#define RCC_CR_HSION RCC_CR_HSION_Msk
10504#define RCC_CR_HSIRDY_Pos (1U)
10505#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
10506#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10507#define RCC_CR_HSITRIM_Pos (3U)
10508#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
10509#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
10510#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
10511#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
10512#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
10513#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
10514#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
10515#define RCC_CR_HSICAL_Pos (8U)
10516#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
10517#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
10518#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
10519#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
10520#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
10521#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
10522#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
10523#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
10524#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
10525#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
10526#define RCC_CR_HSEON_Pos (16U)
10527#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
10528#define RCC_CR_HSEON RCC_CR_HSEON_Msk
10529#define RCC_CR_HSERDY_Pos (17U)
10530#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
10531#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10532#define RCC_CR_HSEBYP_Pos (18U)
10533#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
10534#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10535#define RCC_CR_CSSON_Pos (19U)
10536#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
10537#define RCC_CR_CSSON RCC_CR_CSSON_Msk
10538#define RCC_CR_PLLON_Pos (24U)
10539#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
10540#define RCC_CR_PLLON RCC_CR_PLLON_Msk
10541#define RCC_CR_PLLRDY_Pos (25U)
10542#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
10543#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10544#define RCC_CR_PLLI2SON_Pos (26U)
10545#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
10546#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
10547#define RCC_CR_PLLI2SRDY_Pos (27U)
10548#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
10549#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
10550#define RCC_CR_PLLSAION_Pos (28U)
10551#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos)
10552#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
10553#define RCC_CR_PLLSAIRDY_Pos (29U)
10554#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos)
10555#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
10556
10557/******************** Bit definition for RCC_PLLCFGR register ***************/
10558#define RCC_PLLCFGR_PLLM_Pos (0U)
10559#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
10560#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10561#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
10562#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
10563#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
10564#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
10565#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
10566#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
10567#define RCC_PLLCFGR_PLLN_Pos (6U)
10568#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
10569#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10570#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
10571#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
10572#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
10573#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
10574#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
10575#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
10576#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
10577#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
10578#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
10579#define RCC_PLLCFGR_PLLP_Pos (16U)
10580#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
10581#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10582#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
10583#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
10584#define RCC_PLLCFGR_PLLSRC_Pos (22U)
10585#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
10586#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10587#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
10588#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
10589#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
10590#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
10591#define RCC_PLLCFGR_PLLQ_Pos (24U)
10592#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
10593#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10594#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
10595#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
10596#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
10597#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
10600/******************** Bit definition for RCC_CFGR register ******************/
10602#define RCC_CFGR_SW_Pos (0U)
10603#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
10604#define RCC_CFGR_SW RCC_CFGR_SW_Msk
10605#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
10606#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
10607#define RCC_CFGR_SW_HSI 0x00000000U
10608#define RCC_CFGR_SW_HSE 0x00000001U
10609#define RCC_CFGR_SW_PLL 0x00000002U
10612#define RCC_CFGR_SWS_Pos (2U)
10613#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
10614#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
10615#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
10616#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
10617#define RCC_CFGR_SWS_HSI 0x00000000U
10618#define RCC_CFGR_SWS_HSE 0x00000004U
10619#define RCC_CFGR_SWS_PLL 0x00000008U
10622#define RCC_CFGR_HPRE_Pos (4U)
10623#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
10624#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
10625#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
10626#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
10627#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
10628#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
10630#define RCC_CFGR_HPRE_DIV1 0x00000000U
10631#define RCC_CFGR_HPRE_DIV2 0x00000080U
10632#define RCC_CFGR_HPRE_DIV4 0x00000090U
10633#define RCC_CFGR_HPRE_DIV8 0x000000A0U
10634#define RCC_CFGR_HPRE_DIV16 0x000000B0U
10635#define RCC_CFGR_HPRE_DIV64 0x000000C0U
10636#define RCC_CFGR_HPRE_DIV128 0x000000D0U
10637#define RCC_CFGR_HPRE_DIV256 0x000000E0U
10638#define RCC_CFGR_HPRE_DIV512 0x000000F0U
10641#define RCC_CFGR_PPRE1_Pos (10U)
10642#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
10643#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
10644#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
10645#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
10646#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
10648#define RCC_CFGR_PPRE1_DIV1 0x00000000U
10649#define RCC_CFGR_PPRE1_DIV2 0x00001000U
10650#define RCC_CFGR_PPRE1_DIV4 0x00001400U
10651#define RCC_CFGR_PPRE1_DIV8 0x00001800U
10652#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
10655#define RCC_CFGR_PPRE2_Pos (13U)
10656#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
10657#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
10658#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
10659#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
10660#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
10662#define RCC_CFGR_PPRE2_DIV1 0x00000000U
10663#define RCC_CFGR_PPRE2_DIV2 0x00008000U
10664#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
10665#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
10666#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
10669#define RCC_CFGR_RTCPRE_Pos (16U)
10670#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
10671#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
10672#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
10673#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
10674#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
10675#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
10676#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
10679#define RCC_CFGR_MCO1_Pos (21U)
10680#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
10681#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
10682#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
10683#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
10685#define RCC_CFGR_I2SSRC_Pos (23U)
10686#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
10687#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
10688
10689#define RCC_CFGR_MCO1PRE_Pos (24U)
10690#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
10691#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
10692#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
10693#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
10694#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
10696#define RCC_CFGR_MCO2PRE_Pos (27U)
10697#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
10698#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
10699#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
10700#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
10701#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
10703#define RCC_CFGR_MCO2_Pos (30U)
10704#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
10705#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
10706#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
10707#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
10709/******************** Bit definition for RCC_CIR register *******************/
10710#define RCC_CIR_LSIRDYF_Pos (0U)
10711#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
10712#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
10713#define RCC_CIR_LSERDYF_Pos (1U)
10714#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
10715#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
10716#define RCC_CIR_HSIRDYF_Pos (2U)
10717#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
10718#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
10719#define RCC_CIR_HSERDYF_Pos (3U)
10720#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
10721#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
10722#define RCC_CIR_PLLRDYF_Pos (4U)
10723#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
10724#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
10725#define RCC_CIR_PLLI2SRDYF_Pos (5U)
10726#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
10727#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
10728#define RCC_CIR_PLLSAIRDYF_Pos (6U)
10729#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)
10730#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
10731#define RCC_CIR_CSSF_Pos (7U)
10732#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
10733#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
10734#define RCC_CIR_LSIRDYIE_Pos (8U)
10735#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
10736#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
10737#define RCC_CIR_LSERDYIE_Pos (9U)
10738#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
10739#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
10740#define RCC_CIR_HSIRDYIE_Pos (10U)
10741#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
10742#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
10743#define RCC_CIR_HSERDYIE_Pos (11U)
10744#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
10745#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
10746#define RCC_CIR_PLLRDYIE_Pos (12U)
10747#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
10748#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
10749#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
10750#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
10751#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
10752#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
10753#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)
10754#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
10755#define RCC_CIR_LSIRDYC_Pos (16U)
10756#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
10757#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
10758#define RCC_CIR_LSERDYC_Pos (17U)
10759#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
10760#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
10761#define RCC_CIR_HSIRDYC_Pos (18U)
10762#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
10763#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
10764#define RCC_CIR_HSERDYC_Pos (19U)
10765#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
10766#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
10767#define RCC_CIR_PLLRDYC_Pos (20U)
10768#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
10769#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
10770#define RCC_CIR_PLLI2SRDYC_Pos (21U)
10771#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
10772#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
10773#define RCC_CIR_PLLSAIRDYC_Pos (22U)
10774#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)
10775#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
10776#define RCC_CIR_CSSC_Pos (23U)
10777#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
10778#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
10779
10780/******************** Bit definition for RCC_AHB1RSTR register **************/
10781#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
10782#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
10783#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
10784#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
10785#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
10786#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
10787#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
10788#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
10789#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
10790#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
10791#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
10792#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
10793#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
10794#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
10795#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
10796#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
10797#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
10798#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
10799#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
10800#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
10801#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
10802#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
10803#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
10804#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
10805#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
10806#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
10807#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
10808#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
10809#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos)
10810#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
10811#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
10812#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos)
10813#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
10814#define RCC_AHB1RSTR_CRCRST_Pos (12U)
10815#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
10816#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10817#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
10818#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
10819#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10820#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
10821#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
10822#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10823#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
10824#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos)
10825#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
10826#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
10827#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
10828#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
10829#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
10830#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
10831#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
10832
10833/******************** Bit definition for RCC_AHB2RSTR register **************/
10834#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
10835#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
10836#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
10837#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
10838#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)
10839#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
10840#define RCC_AHB2RSTR_HASHRST_Pos (5U)
10841#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)
10842#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
10843#define RCC_AHB2RSTR_RNGRST_Pos (6U)
10844#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
10845#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
10846#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
10847#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
10848#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
10849
10850/******************** Bit definition for RCC_AHB3RSTR register **************/
10851
10852#define RCC_AHB3RSTR_FMCRST_Pos (0U)
10853#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
10854#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
10855#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
10856#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
10857#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
10858
10859/******************** Bit definition for RCC_APB1RSTR register **************/
10860#define RCC_APB1RSTR_TIM2RST_Pos (0U)
10861#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
10862#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
10863#define RCC_APB1RSTR_TIM3RST_Pos (1U)
10864#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
10865#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
10866#define RCC_APB1RSTR_TIM4RST_Pos (2U)
10867#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
10868#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
10869#define RCC_APB1RSTR_TIM5RST_Pos (3U)
10870#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
10871#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
10872#define RCC_APB1RSTR_TIM6RST_Pos (4U)
10873#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
10874#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
10875#define RCC_APB1RSTR_TIM7RST_Pos (5U)
10876#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
10877#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
10878#define RCC_APB1RSTR_TIM12RST_Pos (6U)
10879#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
10880#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
10881#define RCC_APB1RSTR_TIM13RST_Pos (7U)
10882#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
10883#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
10884#define RCC_APB1RSTR_TIM14RST_Pos (8U)
10885#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
10886#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
10887#define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
10888#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)
10889#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
10890#define RCC_APB1RSTR_WWDGRST_Pos (11U)
10891#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
10892#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
10893#define RCC_APB1RSTR_SPI2RST_Pos (14U)
10894#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
10895#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
10896#define RCC_APB1RSTR_SPI3RST_Pos (15U)
10897#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
10898#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
10899#define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
10900#define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR_SPDIFRXRST_Pos)
10901#define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
10902#define RCC_APB1RSTR_USART2RST_Pos (17U)
10903#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
10904#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
10905#define RCC_APB1RSTR_USART3RST_Pos (18U)
10906#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
10907#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
10908#define RCC_APB1RSTR_UART4RST_Pos (19U)
10909#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
10910#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
10911#define RCC_APB1RSTR_UART5RST_Pos (20U)
10912#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
10913#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
10914#define RCC_APB1RSTR_I2C1RST_Pos (21U)
10915#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
10916#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
10917#define RCC_APB1RSTR_I2C2RST_Pos (22U)
10918#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
10919#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
10920#define RCC_APB1RSTR_I2C3RST_Pos (23U)
10921#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
10922#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
10923#define RCC_APB1RSTR_I2C4RST_Pos (24U)
10924#define RCC_APB1RSTR_I2C4RST_Msk (0x1UL << RCC_APB1RSTR_I2C4RST_Pos)
10925#define RCC_APB1RSTR_I2C4RST RCC_APB1RSTR_I2C4RST_Msk
10926#define RCC_APB1RSTR_CAN1RST_Pos (25U)
10927#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
10928#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
10929#define RCC_APB1RSTR_CAN2RST_Pos (26U)
10930#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
10931#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
10932#define RCC_APB1RSTR_CECRST_Pos (27U)
10933#define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos)
10934#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
10935#define RCC_APB1RSTR_PWRRST_Pos (28U)
10936#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
10937#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
10938#define RCC_APB1RSTR_DACRST_Pos (29U)
10939#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
10940#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
10941#define RCC_APB1RSTR_UART7RST_Pos (30U)
10942#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos)
10943#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
10944#define RCC_APB1RSTR_UART8RST_Pos (31U)
10945#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos)
10946#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
10947
10948/******************** Bit definition for RCC_APB2RSTR register **************/
10949#define RCC_APB2RSTR_TIM1RST_Pos (0U)
10950#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
10951#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
10952#define RCC_APB2RSTR_TIM8RST_Pos (1U)
10953#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
10954#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
10955#define RCC_APB2RSTR_USART1RST_Pos (4U)
10956#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
10957#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
10958#define RCC_APB2RSTR_USART6RST_Pos (5U)
10959#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
10960#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
10961#define RCC_APB2RSTR_ADCRST_Pos (8U)
10962#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
10963#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
10964#define RCC_APB2RSTR_SDMMC1RST_Pos (11U)
10965#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos)
10966#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
10967#define RCC_APB2RSTR_SPI1RST_Pos (12U)
10968#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
10969#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
10970#define RCC_APB2RSTR_SPI4RST_Pos (13U)
10971#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
10972#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
10973#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
10974#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
10975#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
10976#define RCC_APB2RSTR_TIM9RST_Pos (16U)
10977#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
10978#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
10979#define RCC_APB2RSTR_TIM10RST_Pos (17U)
10980#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
10981#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
10982#define RCC_APB2RSTR_TIM11RST_Pos (18U)
10983#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
10984#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
10985#define RCC_APB2RSTR_SPI5RST_Pos (20U)
10986#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
10987#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
10988#define RCC_APB2RSTR_SPI6RST_Pos (21U)
10989#define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)
10990#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
10991#define RCC_APB2RSTR_SAI1RST_Pos (22U)
10992#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
10993#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
10994#define RCC_APB2RSTR_SAI2RST_Pos (23U)
10995#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
10996#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
10997#define RCC_APB2RSTR_LTDCRST_Pos (26U)
10998#define RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)
10999#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
11000
11001/******************** Bit definition for RCC_AHB1ENR register ***************/
11002#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
11003#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
11004#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
11005#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
11006#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
11007#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
11008#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
11009#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
11010#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
11011#define RCC_AHB1ENR_GPIODEN_Pos (3U)
11012#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
11013#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
11014#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
11015#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
11016#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
11017#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
11018#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
11019#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
11020#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
11021#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
11022#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
11023#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
11024#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
11025#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
11026#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
11027#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
11028#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
11029#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
11030#define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)
11031#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
11032#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
11033#define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)
11034#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
11035#define RCC_AHB1ENR_CRCEN_Pos (12U)
11036#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
11037#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
11038#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
11039#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
11040#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
11041#define RCC_AHB1ENR_DTCMRAMEN_Pos (20U)
11042#define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1UL << RCC_AHB1ENR_DTCMRAMEN_Pos)
11043#define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk
11044#define RCC_AHB1ENR_DMA1EN_Pos (21U)
11045#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
11046#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
11047#define RCC_AHB1ENR_DMA2EN_Pos (22U)
11048#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
11049#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
11050#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
11051#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)
11052#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
11053#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
11054#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
11055#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
11056#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
11057#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
11058#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
11059#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
11060#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
11061#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
11062#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
11063#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
11064#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
11065#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
11066#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
11067#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
11068#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
11069#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
11070#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
11071
11072/******************** Bit definition for RCC_AHB2ENR register ***************/
11073#define RCC_AHB2ENR_DCMIEN_Pos (0U)
11074#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
11075#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
11076#define RCC_AHB2ENR_CRYPEN_Pos (4U)
11077#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)
11078#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
11079#define RCC_AHB2ENR_HASHEN_Pos (5U)
11080#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos)
11081#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
11082#define RCC_AHB2ENR_RNGEN_Pos (6U)
11083#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
11084#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
11085#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
11086#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
11087#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
11088
11089/******************** Bit definition for RCC_AHB3ENR register ***************/
11090#define RCC_AHB3ENR_FMCEN_Pos (0U)
11091#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
11092#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11093#define RCC_AHB3ENR_QSPIEN_Pos (1U)
11094#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
11095#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
11096
11097/******************** Bit definition for RCC_APB1ENR register ***************/
11098#define RCC_APB1ENR_TIM2EN_Pos (0U)
11099#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
11100#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
11101#define RCC_APB1ENR_TIM3EN_Pos (1U)
11102#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
11103#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
11104#define RCC_APB1ENR_TIM4EN_Pos (2U)
11105#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
11106#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
11107#define RCC_APB1ENR_TIM5EN_Pos (3U)
11108#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
11109#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
11110#define RCC_APB1ENR_TIM6EN_Pos (4U)
11111#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
11112#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
11113#define RCC_APB1ENR_TIM7EN_Pos (5U)
11114#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
11115#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
11116#define RCC_APB1ENR_TIM12EN_Pos (6U)
11117#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
11118#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
11119#define RCC_APB1ENR_TIM13EN_Pos (7U)
11120#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
11121#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
11122#define RCC_APB1ENR_TIM14EN_Pos (8U)
11123#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
11124#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
11125#define RCC_APB1ENR_LPTIM1EN_Pos (9U)
11126#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)
11127#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
11128#define RCC_APB1ENR_WWDGEN_Pos (11U)
11129#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
11130#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
11131#define RCC_APB1ENR_SPI2EN_Pos (14U)
11132#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
11133#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
11134#define RCC_APB1ENR_SPI3EN_Pos (15U)
11135#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
11136#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
11137#define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
11138#define RCC_APB1ENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR_SPDIFRXEN_Pos)
11139#define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
11140#define RCC_APB1ENR_USART2EN_Pos (17U)
11141#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
11142#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
11143#define RCC_APB1ENR_USART3EN_Pos (18U)
11144#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
11145#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
11146#define RCC_APB1ENR_UART4EN_Pos (19U)
11147#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
11148#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
11149#define RCC_APB1ENR_UART5EN_Pos (20U)
11150#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
11151#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
11152#define RCC_APB1ENR_I2C1EN_Pos (21U)
11153#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
11154#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
11155#define RCC_APB1ENR_I2C2EN_Pos (22U)
11156#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
11157#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
11158#define RCC_APB1ENR_I2C3EN_Pos (23U)
11159#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
11160#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
11161#define RCC_APB1ENR_I2C4EN_Pos (24U)
11162#define RCC_APB1ENR_I2C4EN_Msk (0x1UL << RCC_APB1ENR_I2C4EN_Pos)
11163#define RCC_APB1ENR_I2C4EN RCC_APB1ENR_I2C4EN_Msk
11164#define RCC_APB1ENR_CAN1EN_Pos (25U)
11165#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
11166#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
11167#define RCC_APB1ENR_CAN2EN_Pos (26U)
11168#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
11169#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
11170#define RCC_APB1ENR_CECEN_Pos (27U)
11171#define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos)
11172#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
11173#define RCC_APB1ENR_PWREN_Pos (28U)
11174#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
11175#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
11176#define RCC_APB1ENR_DACEN_Pos (29U)
11177#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
11178#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
11179#define RCC_APB1ENR_UART7EN_Pos (30U)
11180#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos)
11181#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
11182#define RCC_APB1ENR_UART8EN_Pos (31U)
11183#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos)
11184#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
11185
11186/******************** Bit definition for RCC_APB2ENR register ***************/
11187#define RCC_APB2ENR_TIM1EN_Pos (0U)
11188#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
11189#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11190#define RCC_APB2ENR_TIM8EN_Pos (1U)
11191#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
11192#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11193#define RCC_APB2ENR_USART1EN_Pos (4U)
11194#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
11195#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11196#define RCC_APB2ENR_USART6EN_Pos (5U)
11197#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
11198#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
11199#define RCC_APB2ENR_ADC1EN_Pos (8U)
11200#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
11201#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
11202#define RCC_APB2ENR_ADC2EN_Pos (9U)
11203#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
11204#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
11205#define RCC_APB2ENR_ADC3EN_Pos (10U)
11206#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
11207#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
11208#define RCC_APB2ENR_SDMMC1EN_Pos (11U)
11209#define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos)
11210#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
11211#define RCC_APB2ENR_SPI1EN_Pos (12U)
11212#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
11213#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11214#define RCC_APB2ENR_SPI4EN_Pos (13U)
11215#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
11216#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
11217#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
11218#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
11219#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11220#define RCC_APB2ENR_TIM9EN_Pos (16U)
11221#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
11222#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
11223#define RCC_APB2ENR_TIM10EN_Pos (17U)
11224#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
11225#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
11226#define RCC_APB2ENR_TIM11EN_Pos (18U)
11227#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
11228#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
11229#define RCC_APB2ENR_SPI5EN_Pos (20U)
11230#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
11231#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
11232#define RCC_APB2ENR_SPI6EN_Pos (21U)
11233#define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos)
11234#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
11235#define RCC_APB2ENR_SAI1EN_Pos (22U)
11236#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
11237#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11238#define RCC_APB2ENR_SAI2EN_Pos (23U)
11239#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
11240#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
11241#define RCC_APB2ENR_LTDCEN_Pos (26U)
11242#define RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos)
11243#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
11244
11245/******************** Bit definition for RCC_AHB1LPENR register *************/
11246#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
11247#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
11248#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
11249#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
11250#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
11251#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
11252#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
11253#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
11254#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
11255#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
11256#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
11257#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
11258#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
11259#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
11260#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
11261#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
11262#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
11263#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
11264#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
11265#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
11266#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
11267#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
11268#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
11269#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
11270#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
11271#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
11272#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
11273#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
11274#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos)
11275#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
11276#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
11277#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos)
11278#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
11279#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
11280#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
11281#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
11282#define RCC_AHB1LPENR_AXILPEN_Pos (13U)
11283#define RCC_AHB1LPENR_AXILPEN_Msk (0x1UL << RCC_AHB1LPENR_AXILPEN_Pos)
11284#define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk
11285#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
11286#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
11287#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
11288#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
11289#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
11290#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
11291#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
11292#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
11293#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
11294#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
11295#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
11296#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
11297#define RCC_AHB1LPENR_DTCMLPEN_Pos (20U)
11298#define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1UL << RCC_AHB1LPENR_DTCMLPEN_Pos)
11299#define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk
11300#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
11301#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
11302#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
11303#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
11304#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
11305#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
11306#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
11307#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos)
11308#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
11309#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
11310#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
11311#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
11312#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
11313#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
11314#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
11315#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
11316#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
11317#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
11318#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
11319#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
11320#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
11321#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
11322#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
11323#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
11324#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
11325#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
11326#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
11327
11328/******************** Bit definition for RCC_AHB2LPENR register *************/
11329#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
11330#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
11331#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
11332#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
11333#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos)
11334#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
11335#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
11336#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)
11337#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
11338#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
11339#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
11340#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
11341#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
11342#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
11343#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
11344
11345/******************** Bit definition for RCC_AHB3LPENR register *************/
11346#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
11347#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
11348#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
11349#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
11350#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
11351#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
11352/******************** Bit definition for RCC_APB1LPENR register *************/
11353#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
11354#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
11355#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
11356#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
11357#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
11358#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
11359#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
11360#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
11361#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
11362#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
11363#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
11364#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
11365#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
11366#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
11367#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
11368#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
11369#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
11370#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
11371#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
11372#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
11373#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
11374#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
11375#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
11376#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
11377#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
11378#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
11379#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
11380#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
11381#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos)
11382#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
11383#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
11384#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
11385#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
11386#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
11387#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
11388#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
11389#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
11390#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
11391#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
11392#define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
11393#define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR_SPDIFRXLPEN_Pos)
11394#define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
11395#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
11396#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
11397#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
11398#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
11399#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
11400#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
11401#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
11402#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
11403#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
11404#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
11405#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
11406#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
11407#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
11408#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
11409#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
11410#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
11411#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
11412#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
11413#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
11414#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
11415#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
11416#define RCC_APB1LPENR_I2C4LPEN_Pos (24U)
11417#define RCC_APB1LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C4LPEN_Pos)
11418#define RCC_APB1LPENR_I2C4LPEN RCC_APB1LPENR_I2C4LPEN_Msk
11419#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
11420#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
11421#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
11422#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
11423#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
11424#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
11425#define RCC_APB1LPENR_CECLPEN_Pos (27U)
11426#define RCC_APB1LPENR_CECLPEN_Msk (0x1UL << RCC_APB1LPENR_CECLPEN_Pos)
11427#define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
11428#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
11429#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
11430#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
11431#define RCC_APB1LPENR_DACLPEN_Pos (29U)
11432#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
11433#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
11434#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
11435#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos)
11436#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
11437#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
11438#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos)
11439#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
11440
11441/******************** Bit definition for RCC_APB2LPENR register *************/
11442#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
11443#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
11444#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
11445#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
11446#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
11447#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
11448#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
11449#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
11450#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
11451#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
11452#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
11453#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
11454#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
11455#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
11456#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
11457#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
11458#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
11459#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
11460#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
11461#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
11462#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
11463#define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U)
11464#define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC1LPEN_Pos)
11465#define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk
11466#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
11467#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
11468#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
11469#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
11470#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
11471#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
11472#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
11473#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
11474#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
11475#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
11476#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
11477#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
11478#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
11479#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
11480#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
11481#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
11482#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
11483#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
11484#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
11485#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
11486#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
11487#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
11488#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos)
11489#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
11490#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
11491#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
11492#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
11493#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
11494#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)
11495#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
11496#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
11497#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos)
11498#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
11499
11500/******************** Bit definition for RCC_BDCR register ******************/
11501#define RCC_BDCR_LSEON_Pos (0U)
11502#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
11503#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11504#define RCC_BDCR_LSERDY_Pos (1U)
11505#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
11506#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11507#define RCC_BDCR_LSEBYP_Pos (2U)
11508#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
11509#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11510#define RCC_BDCR_LSEDRV_Pos (3U)
11511#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
11512#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
11513#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
11514#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
11515#define RCC_BDCR_RTCSEL_Pos (8U)
11516#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
11517#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11518#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
11519#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
11520#define RCC_BDCR_RTCEN_Pos (15U)
11521#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
11522#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11523#define RCC_BDCR_BDRST_Pos (16U)
11524#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
11525#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11526
11527/******************** Bit definition for RCC_CSR register *******************/
11528#define RCC_CSR_LSION_Pos (0U)
11529#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
11530#define RCC_CSR_LSION RCC_CSR_LSION_Msk
11531#define RCC_CSR_LSIRDY_Pos (1U)
11532#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
11533#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11534#define RCC_CSR_RMVF_Pos (24U)
11535#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
11536#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11537#define RCC_CSR_BORRSTF_Pos (25U)
11538#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
11539#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
11540#define RCC_CSR_PINRSTF_Pos (26U)
11541#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
11542#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11543#define RCC_CSR_PORRSTF_Pos (27U)
11544#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
11545#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
11546#define RCC_CSR_SFTRSTF_Pos (28U)
11547#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
11548#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11549#define RCC_CSR_IWDGRSTF_Pos (29U)
11550#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
11551#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11552#define RCC_CSR_WWDGRSTF_Pos (30U)
11553#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
11554#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11555#define RCC_CSR_LPWRRSTF_Pos (31U)
11556#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
11557#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11558
11559/******************** Bit definition for RCC_SSCGR register *****************/
11560#define RCC_SSCGR_MODPER_Pos (0U)
11561#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
11562#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
11563#define RCC_SSCGR_INCSTEP_Pos (13U)
11564#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
11565#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
11566#define RCC_SSCGR_SPREADSEL_Pos (30U)
11567#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
11568#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
11569#define RCC_SSCGR_SSCGEN_Pos (31U)
11570#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
11571#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
11572
11573/******************** Bit definition for RCC_PLLI2SCFGR register ************/
11574#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
11575#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11576#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
11577#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11578#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11579#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11580#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11581#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11582#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11583#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11584#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11585#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
11586#define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
11587#define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
11588#define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
11589#define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
11590#define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
11591#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
11592#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11593#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
11594#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11595#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11596#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11597#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
11598#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
11599#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11600#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
11601#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11602#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11603#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
11605/******************** Bit definition for RCC_PLLSAICFGR register ************/
11606#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
11607#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11608#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
11609#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11610#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11611#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11612#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11613#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11614#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11615#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11616#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11617#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
11618#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
11619#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
11620#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
11621#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
11622#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
11623#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
11624#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11625#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
11626#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11627#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11628#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11629#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
11630#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
11631#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11632#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
11633#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11634#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11635#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
11637/******************** Bit definition for RCC_DCKCFGR1 register ***************/
11638#define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U)
11639#define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11640#define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk
11641#define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11642#define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11643#define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11644#define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11645#define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
11647#define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U)
11648#define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11649#define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk
11650#define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11651#define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11652#define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11653#define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11654#define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
11656#define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U)
11657#define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos)
11658#define RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR_Msk
11659#define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos)
11660#define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos)
11662#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
11663#define RCC_DCKCFGR1_SAI1SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI1SEL_Pos)
11664#define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk
11665#define RCC_DCKCFGR1_SAI1SEL_0 (0x1UL << RCC_DCKCFGR1_SAI1SEL_Pos)
11666#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos)
11668#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
11669#define RCC_DCKCFGR1_SAI2SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI2SEL_Pos)
11670#define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk
11671#define RCC_DCKCFGR1_SAI2SEL_0 (0x1UL << RCC_DCKCFGR1_SAI2SEL_Pos)
11672#define RCC_DCKCFGR1_SAI2SEL_1 (0x2UL << RCC_DCKCFGR1_SAI2SEL_Pos)
11674#define RCC_DCKCFGR1_TIMPRE_Pos (24U)
11675#define RCC_DCKCFGR1_TIMPRE_Msk (0x1UL << RCC_DCKCFGR1_TIMPRE_Pos)
11676#define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk
11677
11678/******************** Bit definition for RCC_DCKCFGR2 register ***************/
11679#define RCC_DCKCFGR2_USART1SEL_Pos (0U)
11680#define RCC_DCKCFGR2_USART1SEL_Msk (0x3UL << RCC_DCKCFGR2_USART1SEL_Pos)
11681#define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk
11682#define RCC_DCKCFGR2_USART1SEL_0 (0x1UL << RCC_DCKCFGR2_USART1SEL_Pos)
11683#define RCC_DCKCFGR2_USART1SEL_1 (0x2UL << RCC_DCKCFGR2_USART1SEL_Pos)
11684#define RCC_DCKCFGR2_USART2SEL_Pos (2U)
11685#define RCC_DCKCFGR2_USART2SEL_Msk (0x3UL << RCC_DCKCFGR2_USART2SEL_Pos)
11686#define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk
11687#define RCC_DCKCFGR2_USART2SEL_0 (0x1UL << RCC_DCKCFGR2_USART2SEL_Pos)
11688#define RCC_DCKCFGR2_USART2SEL_1 (0x2UL << RCC_DCKCFGR2_USART2SEL_Pos)
11689#define RCC_DCKCFGR2_USART3SEL_Pos (4U)
11690#define RCC_DCKCFGR2_USART3SEL_Msk (0x3UL << RCC_DCKCFGR2_USART3SEL_Pos)
11691#define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk
11692#define RCC_DCKCFGR2_USART3SEL_0 (0x1UL << RCC_DCKCFGR2_USART3SEL_Pos)
11693#define RCC_DCKCFGR2_USART3SEL_1 (0x2UL << RCC_DCKCFGR2_USART3SEL_Pos)
11694#define RCC_DCKCFGR2_UART4SEL_Pos (6U)
11695#define RCC_DCKCFGR2_UART4SEL_Msk (0x3UL << RCC_DCKCFGR2_UART4SEL_Pos)
11696#define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk
11697#define RCC_DCKCFGR2_UART4SEL_0 (0x1UL << RCC_DCKCFGR2_UART4SEL_Pos)
11698#define RCC_DCKCFGR2_UART4SEL_1 (0x2UL << RCC_DCKCFGR2_UART4SEL_Pos)
11699#define RCC_DCKCFGR2_UART5SEL_Pos (8U)
11700#define RCC_DCKCFGR2_UART5SEL_Msk (0x3UL << RCC_DCKCFGR2_UART5SEL_Pos)
11701#define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk
11702#define RCC_DCKCFGR2_UART5SEL_0 (0x1UL << RCC_DCKCFGR2_UART5SEL_Pos)
11703#define RCC_DCKCFGR2_UART5SEL_1 (0x2UL << RCC_DCKCFGR2_UART5SEL_Pos)
11704#define RCC_DCKCFGR2_USART6SEL_Pos (10U)
11705#define RCC_DCKCFGR2_USART6SEL_Msk (0x3UL << RCC_DCKCFGR2_USART6SEL_Pos)
11706#define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk
11707#define RCC_DCKCFGR2_USART6SEL_0 (0x1UL << RCC_DCKCFGR2_USART6SEL_Pos)
11708#define RCC_DCKCFGR2_USART6SEL_1 (0x2UL << RCC_DCKCFGR2_USART6SEL_Pos)
11709#define RCC_DCKCFGR2_UART7SEL_Pos (12U)
11710#define RCC_DCKCFGR2_UART7SEL_Msk (0x3UL << RCC_DCKCFGR2_UART7SEL_Pos)
11711#define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk
11712#define RCC_DCKCFGR2_UART7SEL_0 (0x1UL << RCC_DCKCFGR2_UART7SEL_Pos)
11713#define RCC_DCKCFGR2_UART7SEL_1 (0x2UL << RCC_DCKCFGR2_UART7SEL_Pos)
11714#define RCC_DCKCFGR2_UART8SEL_Pos (14U)
11715#define RCC_DCKCFGR2_UART8SEL_Msk (0x3UL << RCC_DCKCFGR2_UART8SEL_Pos)
11716#define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk
11717#define RCC_DCKCFGR2_UART8SEL_0 (0x1UL << RCC_DCKCFGR2_UART8SEL_Pos)
11718#define RCC_DCKCFGR2_UART8SEL_1 (0x2UL << RCC_DCKCFGR2_UART8SEL_Pos)
11719#define RCC_DCKCFGR2_I2C1SEL_Pos (16U)
11720#define RCC_DCKCFGR2_I2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C1SEL_Pos)
11721#define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk
11722#define RCC_DCKCFGR2_I2C1SEL_0 (0x1UL << RCC_DCKCFGR2_I2C1SEL_Pos)
11723#define RCC_DCKCFGR2_I2C1SEL_1 (0x2UL << RCC_DCKCFGR2_I2C1SEL_Pos)
11724#define RCC_DCKCFGR2_I2C2SEL_Pos (18U)
11725#define RCC_DCKCFGR2_I2C2SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C2SEL_Pos)
11726#define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk
11727#define RCC_DCKCFGR2_I2C2SEL_0 (0x1UL << RCC_DCKCFGR2_I2C2SEL_Pos)
11728#define RCC_DCKCFGR2_I2C2SEL_1 (0x2UL << RCC_DCKCFGR2_I2C2SEL_Pos)
11729#define RCC_DCKCFGR2_I2C3SEL_Pos (20U)
11730#define RCC_DCKCFGR2_I2C3SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C3SEL_Pos)
11731#define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk
11732#define RCC_DCKCFGR2_I2C3SEL_0 (0x1UL << RCC_DCKCFGR2_I2C3SEL_Pos)
11733#define RCC_DCKCFGR2_I2C3SEL_1 (0x2UL << RCC_DCKCFGR2_I2C3SEL_Pos)
11734#define RCC_DCKCFGR2_I2C4SEL_Pos (22U)
11735#define RCC_DCKCFGR2_I2C4SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C4SEL_Pos)
11736#define RCC_DCKCFGR2_I2C4SEL RCC_DCKCFGR2_I2C4SEL_Msk
11737#define RCC_DCKCFGR2_I2C4SEL_0 (0x1UL << RCC_DCKCFGR2_I2C4SEL_Pos)
11738#define RCC_DCKCFGR2_I2C4SEL_1 (0x2UL << RCC_DCKCFGR2_I2C4SEL_Pos)
11739#define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U)
11740#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
11741#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
11742#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
11743#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
11744#define RCC_DCKCFGR2_CECSEL_Pos (26U)
11745#define RCC_DCKCFGR2_CECSEL_Msk (0x1UL << RCC_DCKCFGR2_CECSEL_Pos)
11746#define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
11747#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
11748#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos)
11749#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
11750#define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U)
11751#define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC1SEL_Pos)
11752#define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk
11753
11754/******************************************************************************/
11755/* */
11756/* RNG */
11757/* */
11758/******************************************************************************/
11759/******************** Bits definition for RNG_CR register *******************/
11760#define RNG_CR_RNGEN_Pos (2U)
11761#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
11762#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
11763#define RNG_CR_IE_Pos (3U)
11764#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
11765#define RNG_CR_IE RNG_CR_IE_Msk
11766
11767/******************** Bits definition for RNG_SR register *******************/
11768#define RNG_SR_DRDY_Pos (0U)
11769#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
11770#define RNG_SR_DRDY RNG_SR_DRDY_Msk
11771#define RNG_SR_CECS_Pos (1U)
11772#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
11773#define RNG_SR_CECS RNG_SR_CECS_Msk
11774#define RNG_SR_SECS_Pos (2U)
11775#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
11776#define RNG_SR_SECS RNG_SR_SECS_Msk
11777#define RNG_SR_CEIS_Pos (5U)
11778#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
11779#define RNG_SR_CEIS RNG_SR_CEIS_Msk
11780#define RNG_SR_SEIS_Pos (6U)
11781#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
11782#define RNG_SR_SEIS RNG_SR_SEIS_Msk
11783
11784/******************************************************************************/
11785/* */
11786/* Real-Time Clock (RTC) */
11787/* */
11788/******************************************************************************/
11789/******************** Bits definition for RTC_TR register *******************/
11790#define RTC_TR_PM_Pos (22U)
11791#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
11792#define RTC_TR_PM RTC_TR_PM_Msk
11793#define RTC_TR_HT_Pos (20U)
11794#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
11795#define RTC_TR_HT RTC_TR_HT_Msk
11796#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
11797#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
11798#define RTC_TR_HU_Pos (16U)
11799#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
11800#define RTC_TR_HU RTC_TR_HU_Msk
11801#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
11802#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
11803#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
11804#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
11805#define RTC_TR_MNT_Pos (12U)
11806#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
11807#define RTC_TR_MNT RTC_TR_MNT_Msk
11808#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
11809#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
11810#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
11811#define RTC_TR_MNU_Pos (8U)
11812#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
11813#define RTC_TR_MNU RTC_TR_MNU_Msk
11814#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
11815#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
11816#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
11817#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
11818#define RTC_TR_ST_Pos (4U)
11819#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
11820#define RTC_TR_ST RTC_TR_ST_Msk
11821#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
11822#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
11823#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
11824#define RTC_TR_SU_Pos (0U)
11825#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
11826#define RTC_TR_SU RTC_TR_SU_Msk
11827#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
11828#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
11829#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
11830#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
11832/******************** Bits definition for RTC_DR register *******************/
11833#define RTC_DR_YT_Pos (20U)
11834#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
11835#define RTC_DR_YT RTC_DR_YT_Msk
11836#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
11837#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
11838#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
11839#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
11840#define RTC_DR_YU_Pos (16U)
11841#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
11842#define RTC_DR_YU RTC_DR_YU_Msk
11843#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
11844#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
11845#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
11846#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
11847#define RTC_DR_WDU_Pos (13U)
11848#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
11849#define RTC_DR_WDU RTC_DR_WDU_Msk
11850#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
11851#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
11852#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
11853#define RTC_DR_MT_Pos (12U)
11854#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
11855#define RTC_DR_MT RTC_DR_MT_Msk
11856#define RTC_DR_MU_Pos (8U)
11857#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
11858#define RTC_DR_MU RTC_DR_MU_Msk
11859#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
11860#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
11861#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
11862#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
11863#define RTC_DR_DT_Pos (4U)
11864#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
11865#define RTC_DR_DT RTC_DR_DT_Msk
11866#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
11867#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
11868#define RTC_DR_DU_Pos (0U)
11869#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
11870#define RTC_DR_DU RTC_DR_DU_Msk
11871#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
11872#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
11873#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
11874#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
11876/******************** Bits definition for RTC_CR register *******************/
11877#define RTC_CR_ITSE_Pos (24U)
11878#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
11879#define RTC_CR_ITSE RTC_CR_ITSE_Msk
11880#define RTC_CR_COE_Pos (23U)
11881#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
11882#define RTC_CR_COE RTC_CR_COE_Msk
11883#define RTC_CR_OSEL_Pos (21U)
11884#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
11885#define RTC_CR_OSEL RTC_CR_OSEL_Msk
11886#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
11887#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
11888#define RTC_CR_POL_Pos (20U)
11889#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
11890#define RTC_CR_POL RTC_CR_POL_Msk
11891#define RTC_CR_COSEL_Pos (19U)
11892#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
11893#define RTC_CR_COSEL RTC_CR_COSEL_Msk
11894#define RTC_CR_BKP_Pos (18U)
11895#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
11896#define RTC_CR_BKP RTC_CR_BKP_Msk
11897#define RTC_CR_SUB1H_Pos (17U)
11898#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
11899#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11900#define RTC_CR_ADD1H_Pos (16U)
11901#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
11902#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11903#define RTC_CR_TSIE_Pos (15U)
11904#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
11905#define RTC_CR_TSIE RTC_CR_TSIE_Msk
11906#define RTC_CR_WUTIE_Pos (14U)
11907#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
11908#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11909#define RTC_CR_ALRBIE_Pos (13U)
11910#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
11911#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11912#define RTC_CR_ALRAIE_Pos (12U)
11913#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
11914#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11915#define RTC_CR_TSE_Pos (11U)
11916#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
11917#define RTC_CR_TSE RTC_CR_TSE_Msk
11918#define RTC_CR_WUTE_Pos (10U)
11919#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
11920#define RTC_CR_WUTE RTC_CR_WUTE_Msk
11921#define RTC_CR_ALRBE_Pos (9U)
11922#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
11923#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11924#define RTC_CR_ALRAE_Pos (8U)
11925#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
11926#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11927#define RTC_CR_FMT_Pos (6U)
11928#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
11929#define RTC_CR_FMT RTC_CR_FMT_Msk
11930#define RTC_CR_BYPSHAD_Pos (5U)
11931#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
11932#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11933#define RTC_CR_REFCKON_Pos (4U)
11934#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
11935#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11936#define RTC_CR_TSEDGE_Pos (3U)
11937#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
11938#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11939#define RTC_CR_WUCKSEL_Pos (0U)
11940#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
11941#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11942#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
11943#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
11944#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
11946/* Legacy define */
11947#define RTC_CR_BCK RTC_CR_BKP
11948
11949/******************** Bits definition for RTC_ISR register ******************/
11950#define RTC_ISR_ITSF_Pos (17U)
11951#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
11952#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
11953#define RTC_ISR_RECALPF_Pos (16U)
11954#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
11955#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11956#define RTC_ISR_TAMP3F_Pos (15U)
11957#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
11958#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
11959#define RTC_ISR_TAMP2F_Pos (14U)
11960#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
11961#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11962#define RTC_ISR_TAMP1F_Pos (13U)
11963#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
11964#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11965#define RTC_ISR_TSOVF_Pos (12U)
11966#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
11967#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11968#define RTC_ISR_TSF_Pos (11U)
11969#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
11970#define RTC_ISR_TSF RTC_ISR_TSF_Msk
11971#define RTC_ISR_WUTF_Pos (10U)
11972#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
11973#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11974#define RTC_ISR_ALRBF_Pos (9U)
11975#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
11976#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11977#define RTC_ISR_ALRAF_Pos (8U)
11978#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
11979#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11980#define RTC_ISR_INIT_Pos (7U)
11981#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
11982#define RTC_ISR_INIT RTC_ISR_INIT_Msk
11983#define RTC_ISR_INITF_Pos (6U)
11984#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
11985#define RTC_ISR_INITF RTC_ISR_INITF_Msk
11986#define RTC_ISR_RSF_Pos (5U)
11987#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
11988#define RTC_ISR_RSF RTC_ISR_RSF_Msk
11989#define RTC_ISR_INITS_Pos (4U)
11990#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
11991#define RTC_ISR_INITS RTC_ISR_INITS_Msk
11992#define RTC_ISR_SHPF_Pos (3U)
11993#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
11994#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11995#define RTC_ISR_WUTWF_Pos (2U)
11996#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
11997#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11998#define RTC_ISR_ALRBWF_Pos (1U)
11999#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
12000#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
12001#define RTC_ISR_ALRAWF_Pos (0U)
12002#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
12003#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
12004
12005/******************** Bits definition for RTC_PRER register *****************/
12006#define RTC_PRER_PREDIV_A_Pos (16U)
12007#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
12008#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
12009#define RTC_PRER_PREDIV_S_Pos (0U)
12010#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
12011#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
12012
12013/******************** Bits definition for RTC_WUTR register *****************/
12014#define RTC_WUTR_WUT_Pos (0U)
12015#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
12016#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
12017
12018/******************** Bits definition for RTC_ALRMAR register ***************/
12019#define RTC_ALRMAR_MSK4_Pos (31U)
12020#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
12021#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
12022#define RTC_ALRMAR_WDSEL_Pos (30U)
12023#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
12024#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
12025#define RTC_ALRMAR_DT_Pos (28U)
12026#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
12027#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
12028#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
12029#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
12030#define RTC_ALRMAR_DU_Pos (24U)
12031#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
12032#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
12033#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
12034#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
12035#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
12036#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
12037#define RTC_ALRMAR_MSK3_Pos (23U)
12038#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
12039#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
12040#define RTC_ALRMAR_PM_Pos (22U)
12041#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
12042#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
12043#define RTC_ALRMAR_HT_Pos (20U)
12044#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
12045#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
12046#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
12047#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
12048#define RTC_ALRMAR_HU_Pos (16U)
12049#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
12050#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
12051#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
12052#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
12053#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
12054#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
12055#define RTC_ALRMAR_MSK2_Pos (15U)
12056#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
12057#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
12058#define RTC_ALRMAR_MNT_Pos (12U)
12059#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
12060#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
12061#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
12062#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
12063#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
12064#define RTC_ALRMAR_MNU_Pos (8U)
12065#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
12066#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
12067#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
12068#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
12069#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
12070#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
12071#define RTC_ALRMAR_MSK1_Pos (7U)
12072#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
12073#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
12074#define RTC_ALRMAR_ST_Pos (4U)
12075#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
12076#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
12077#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
12078#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
12079#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
12080#define RTC_ALRMAR_SU_Pos (0U)
12081#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
12082#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
12083#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
12084#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
12085#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
12086#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
12088/******************** Bits definition for RTC_ALRMBR register ***************/
12089#define RTC_ALRMBR_MSK4_Pos (31U)
12090#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
12091#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
12092#define RTC_ALRMBR_WDSEL_Pos (30U)
12093#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
12094#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
12095#define RTC_ALRMBR_DT_Pos (28U)
12096#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
12097#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
12098#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
12099#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
12100#define RTC_ALRMBR_DU_Pos (24U)
12101#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
12102#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
12103#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
12104#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
12105#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
12106#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
12107#define RTC_ALRMBR_MSK3_Pos (23U)
12108#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
12109#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
12110#define RTC_ALRMBR_PM_Pos (22U)
12111#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
12112#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
12113#define RTC_ALRMBR_HT_Pos (20U)
12114#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
12115#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
12116#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
12117#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
12118#define RTC_ALRMBR_HU_Pos (16U)
12119#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
12120#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
12121#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
12122#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
12123#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
12124#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
12125#define RTC_ALRMBR_MSK2_Pos (15U)
12126#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
12127#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
12128#define RTC_ALRMBR_MNT_Pos (12U)
12129#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
12130#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
12131#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
12132#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
12133#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
12134#define RTC_ALRMBR_MNU_Pos (8U)
12135#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
12136#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
12137#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
12138#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
12139#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
12140#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
12141#define RTC_ALRMBR_MSK1_Pos (7U)
12142#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
12143#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
12144#define RTC_ALRMBR_ST_Pos (4U)
12145#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
12146#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
12147#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
12148#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
12149#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
12150#define RTC_ALRMBR_SU_Pos (0U)
12151#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
12152#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
12153#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
12154#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
12155#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
12156#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
12158/******************** Bits definition for RTC_WPR register ******************/
12159#define RTC_WPR_KEY_Pos (0U)
12160#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
12161#define RTC_WPR_KEY RTC_WPR_KEY_Msk
12162
12163/******************** Bits definition for RTC_SSR register ******************/
12164#define RTC_SSR_SS_Pos (0U)
12165#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
12166#define RTC_SSR_SS RTC_SSR_SS_Msk
12167
12168/******************** Bits definition for RTC_SHIFTR register ***************/
12169#define RTC_SHIFTR_SUBFS_Pos (0U)
12170#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
12171#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
12172#define RTC_SHIFTR_ADD1S_Pos (31U)
12173#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
12174#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
12175
12176/******************** Bits definition for RTC_TSTR register *****************/
12177#define RTC_TSTR_PM_Pos (22U)
12178#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
12179#define RTC_TSTR_PM RTC_TSTR_PM_Msk
12180#define RTC_TSTR_HT_Pos (20U)
12181#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
12182#define RTC_TSTR_HT RTC_TSTR_HT_Msk
12183#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
12184#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
12185#define RTC_TSTR_HU_Pos (16U)
12186#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
12187#define RTC_TSTR_HU RTC_TSTR_HU_Msk
12188#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
12189#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
12190#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
12191#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
12192#define RTC_TSTR_MNT_Pos (12U)
12193#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
12194#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
12195#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
12196#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
12197#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
12198#define RTC_TSTR_MNU_Pos (8U)
12199#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
12200#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
12201#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
12202#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
12203#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
12204#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
12205#define RTC_TSTR_ST_Pos (4U)
12206#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
12207#define RTC_TSTR_ST RTC_TSTR_ST_Msk
12208#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
12209#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
12210#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
12211#define RTC_TSTR_SU_Pos (0U)
12212#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
12213#define RTC_TSTR_SU RTC_TSTR_SU_Msk
12214#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
12215#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
12216#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
12217#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
12219/******************** Bits definition for RTC_TSDR register *****************/
12220#define RTC_TSDR_WDU_Pos (13U)
12221#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
12222#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12223#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
12224#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
12225#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
12226#define RTC_TSDR_MT_Pos (12U)
12227#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
12228#define RTC_TSDR_MT RTC_TSDR_MT_Msk
12229#define RTC_TSDR_MU_Pos (8U)
12230#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
12231#define RTC_TSDR_MU RTC_TSDR_MU_Msk
12232#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
12233#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
12234#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
12235#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
12236#define RTC_TSDR_DT_Pos (4U)
12237#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
12238#define RTC_TSDR_DT RTC_TSDR_DT_Msk
12239#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
12240#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
12241#define RTC_TSDR_DU_Pos (0U)
12242#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
12243#define RTC_TSDR_DU RTC_TSDR_DU_Msk
12244#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
12245#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
12246#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
12247#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
12249/******************** Bits definition for RTC_TSSSR register ****************/
12250#define RTC_TSSSR_SS_Pos (0U)
12251#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
12252#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12253
12254/******************** Bits definition for RTC_CAL register *****************/
12255#define RTC_CALR_CALP_Pos (15U)
12256#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
12257#define RTC_CALR_CALP RTC_CALR_CALP_Msk
12258#define RTC_CALR_CALW8_Pos (14U)
12259#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
12260#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12261#define RTC_CALR_CALW16_Pos (13U)
12262#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
12263#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12264#define RTC_CALR_CALM_Pos (0U)
12265#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
12266#define RTC_CALR_CALM RTC_CALR_CALM_Msk
12267#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
12268#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
12269#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
12270#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
12271#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
12272#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
12273#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
12274#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
12275#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
12277/******************** Bits definition for RTC_TAMPCR register ****************/
12278#define RTC_TAMPCR_TAMP3MF_Pos (24U)
12279#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
12280#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
12281#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
12282#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
12283#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
12284#define RTC_TAMPCR_TAMP3IE_Pos (22U)
12285#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
12286#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
12287#define RTC_TAMPCR_TAMP2MF_Pos (21U)
12288#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
12289#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
12290#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
12291#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
12292#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
12293#define RTC_TAMPCR_TAMP2IE_Pos (19U)
12294#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
12295#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
12296#define RTC_TAMPCR_TAMP1MF_Pos (18U)
12297#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
12298#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
12299#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
12300#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
12301#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
12302#define RTC_TAMPCR_TAMP1IE_Pos (16U)
12303#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
12304#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
12305#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
12306#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
12307#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
12308#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
12309#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
12310#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
12311#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
12312#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
12313#define RTC_TAMPCR_TAMPFLT_Pos (11U)
12314#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
12315#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
12316#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
12317#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
12318#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
12319#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
12320#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
12321#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
12322#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
12323#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
12324#define RTC_TAMPCR_TAMPTS_Pos (7U)
12325#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
12326#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
12327#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
12328#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
12329#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
12330#define RTC_TAMPCR_TAMP3E_Pos (5U)
12331#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
12332#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
12333#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
12334#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
12335#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
12336#define RTC_TAMPCR_TAMP2E_Pos (3U)
12337#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
12338#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
12339#define RTC_TAMPCR_TAMPIE_Pos (2U)
12340#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
12341#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
12342#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
12343#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
12344#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
12345#define RTC_TAMPCR_TAMP1E_Pos (0U)
12346#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
12347#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
12348
12349/* Legacy defines */
12350#define RTC_TAMPCR_TAMP3_TRG RTC_TAMPCR_TAMP3TRG
12351#define RTC_TAMPCR_TAMP2_TRG RTC_TAMPCR_TAMP2TRG
12352#define RTC_TAMPCR_TAMP1_TRG RTC_TAMPCR_TAMP1TRG
12353
12354/******************** Bits definition for RTC_ALRMASSR register *************/
12355#define RTC_ALRMASSR_MASKSS_Pos (24U)
12356#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
12357#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12358#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
12359#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
12360#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
12361#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
12362#define RTC_ALRMASSR_SS_Pos (0U)
12363#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
12364#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12365
12366/******************** Bits definition for RTC_ALRMBSSR register *************/
12367#define RTC_ALRMBSSR_MASKSS_Pos (24U)
12368#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
12369#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12370#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
12371#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
12372#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
12373#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
12374#define RTC_ALRMBSSR_SS_Pos (0U)
12375#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
12376#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12377
12378/******************** Bits definition for RTC_OR register ****************/
12379#define RTC_OR_TSINSEL_Pos (1U)
12380#define RTC_OR_TSINSEL_Msk (0x3UL << RTC_OR_TSINSEL_Pos)
12381#define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk
12382#define RTC_OR_TSINSEL_0 (0x1UL << RTC_OR_TSINSEL_Pos)
12383#define RTC_OR_TSINSEL_1 (0x2UL << RTC_OR_TSINSEL_Pos)
12384#define RTC_OR_ALARMOUTTYPE_Pos (3U)
12385#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
12386#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
12387/* Legacy defines*/
12388#define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE
12389
12390/******************** Bits definition for RTC_BKP0R register ****************/
12391#define RTC_BKP0R_Pos (0U)
12392#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
12393#define RTC_BKP0R RTC_BKP0R_Msk
12394
12395/******************** Bits definition for RTC_BKP1R register ****************/
12396#define RTC_BKP1R_Pos (0U)
12397#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
12398#define RTC_BKP1R RTC_BKP1R_Msk
12399
12400/******************** Bits definition for RTC_BKP2R register ****************/
12401#define RTC_BKP2R_Pos (0U)
12402#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
12403#define RTC_BKP2R RTC_BKP2R_Msk
12404
12405/******************** Bits definition for RTC_BKP3R register ****************/
12406#define RTC_BKP3R_Pos (0U)
12407#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
12408#define RTC_BKP3R RTC_BKP3R_Msk
12409
12410/******************** Bits definition for RTC_BKP4R register ****************/
12411#define RTC_BKP4R_Pos (0U)
12412#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
12413#define RTC_BKP4R RTC_BKP4R_Msk
12414
12415/******************** Bits definition for RTC_BKP5R register ****************/
12416#define RTC_BKP5R_Pos (0U)
12417#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
12418#define RTC_BKP5R RTC_BKP5R_Msk
12419
12420/******************** Bits definition for RTC_BKP6R register ****************/
12421#define RTC_BKP6R_Pos (0U)
12422#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
12423#define RTC_BKP6R RTC_BKP6R_Msk
12424
12425/******************** Bits definition for RTC_BKP7R register ****************/
12426#define RTC_BKP7R_Pos (0U)
12427#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
12428#define RTC_BKP7R RTC_BKP7R_Msk
12429
12430/******************** Bits definition for RTC_BKP8R register ****************/
12431#define RTC_BKP8R_Pos (0U)
12432#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
12433#define RTC_BKP8R RTC_BKP8R_Msk
12434
12435/******************** Bits definition for RTC_BKP9R register ****************/
12436#define RTC_BKP9R_Pos (0U)
12437#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
12438#define RTC_BKP9R RTC_BKP9R_Msk
12439
12440/******************** Bits definition for RTC_BKP10R register ***************/
12441#define RTC_BKP10R_Pos (0U)
12442#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
12443#define RTC_BKP10R RTC_BKP10R_Msk
12444
12445/******************** Bits definition for RTC_BKP11R register ***************/
12446#define RTC_BKP11R_Pos (0U)
12447#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
12448#define RTC_BKP11R RTC_BKP11R_Msk
12449
12450/******************** Bits definition for RTC_BKP12R register ***************/
12451#define RTC_BKP12R_Pos (0U)
12452#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
12453#define RTC_BKP12R RTC_BKP12R_Msk
12454
12455/******************** Bits definition for RTC_BKP13R register ***************/
12456#define RTC_BKP13R_Pos (0U)
12457#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
12458#define RTC_BKP13R RTC_BKP13R_Msk
12459
12460/******************** Bits definition for RTC_BKP14R register ***************/
12461#define RTC_BKP14R_Pos (0U)
12462#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
12463#define RTC_BKP14R RTC_BKP14R_Msk
12464
12465/******************** Bits definition for RTC_BKP15R register ***************/
12466#define RTC_BKP15R_Pos (0U)
12467#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
12468#define RTC_BKP15R RTC_BKP15R_Msk
12469
12470/******************** Bits definition for RTC_BKP16R register ***************/
12471#define RTC_BKP16R_Pos (0U)
12472#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
12473#define RTC_BKP16R RTC_BKP16R_Msk
12474
12475/******************** Bits definition for RTC_BKP17R register ***************/
12476#define RTC_BKP17R_Pos (0U)
12477#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
12478#define RTC_BKP17R RTC_BKP17R_Msk
12479
12480/******************** Bits definition for RTC_BKP18R register ***************/
12481#define RTC_BKP18R_Pos (0U)
12482#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
12483#define RTC_BKP18R RTC_BKP18R_Msk
12484
12485/******************** Bits definition for RTC_BKP19R register ***************/
12486#define RTC_BKP19R_Pos (0U)
12487#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
12488#define RTC_BKP19R RTC_BKP19R_Msk
12489
12490/******************** Bits definition for RTC_BKP20R register ***************/
12491#define RTC_BKP20R_Pos (0U)
12492#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
12493#define RTC_BKP20R RTC_BKP20R_Msk
12494
12495/******************** Bits definition for RTC_BKP21R register ***************/
12496#define RTC_BKP21R_Pos (0U)
12497#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
12498#define RTC_BKP21R RTC_BKP21R_Msk
12499
12500/******************** Bits definition for RTC_BKP22R register ***************/
12501#define RTC_BKP22R_Pos (0U)
12502#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
12503#define RTC_BKP22R RTC_BKP22R_Msk
12504
12505/******************** Bits definition for RTC_BKP23R register ***************/
12506#define RTC_BKP23R_Pos (0U)
12507#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
12508#define RTC_BKP23R RTC_BKP23R_Msk
12509
12510/******************** Bits definition for RTC_BKP24R register ***************/
12511#define RTC_BKP24R_Pos (0U)
12512#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
12513#define RTC_BKP24R RTC_BKP24R_Msk
12514
12515/******************** Bits definition for RTC_BKP25R register ***************/
12516#define RTC_BKP25R_Pos (0U)
12517#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
12518#define RTC_BKP25R RTC_BKP25R_Msk
12519
12520/******************** Bits definition for RTC_BKP26R register ***************/
12521#define RTC_BKP26R_Pos (0U)
12522#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
12523#define RTC_BKP26R RTC_BKP26R_Msk
12524
12525/******************** Bits definition for RTC_BKP27R register ***************/
12526#define RTC_BKP27R_Pos (0U)
12527#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
12528#define RTC_BKP27R RTC_BKP27R_Msk
12529
12530/******************** Bits definition for RTC_BKP28R register ***************/
12531#define RTC_BKP28R_Pos (0U)
12532#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
12533#define RTC_BKP28R RTC_BKP28R_Msk
12534
12535/******************** Bits definition for RTC_BKP29R register ***************/
12536#define RTC_BKP29R_Pos (0U)
12537#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
12538#define RTC_BKP29R RTC_BKP29R_Msk
12539
12540/******************** Bits definition for RTC_BKP30R register ***************/
12541#define RTC_BKP30R_Pos (0U)
12542#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
12543#define RTC_BKP30R RTC_BKP30R_Msk
12544
12545/******************** Bits definition for RTC_BKP31R register ***************/
12546#define RTC_BKP31R_Pos (0U)
12547#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
12548#define RTC_BKP31R RTC_BKP31R_Msk
12549
12550/******************** Number of backup registers ******************************/
12551#define RTC_BKP_NUMBER 0x00000020U
12552
12553/******************************************************************************/
12554/* */
12555/* Serial Audio Interface */
12556/* */
12557/******************************************************************************/
12558/******************** Bit definition for SAI_GCR register *******************/
12559#define SAI_GCR_SYNCIN_Pos (0U)
12560#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
12561#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
12562#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
12563#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
12565#define SAI_GCR_SYNCOUT_Pos (4U)
12566#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
12567#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
12568#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
12569#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
12571/******************* Bit definition for SAI_xCR1 register *******************/
12572#define SAI_xCR1_MODE_Pos (0U)
12573#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
12574#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
12575#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
12576#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
12578#define SAI_xCR1_PRTCFG_Pos (2U)
12579#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
12580#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
12581#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
12582#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
12584#define SAI_xCR1_DS_Pos (5U)
12585#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
12586#define SAI_xCR1_DS SAI_xCR1_DS_Msk
12587#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
12588#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
12589#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
12591#define SAI_xCR1_LSBFIRST_Pos (8U)
12592#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
12593#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
12594#define SAI_xCR1_CKSTR_Pos (9U)
12595#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
12596#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
12598#define SAI_xCR1_SYNCEN_Pos (10U)
12599#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
12600#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
12601#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
12602#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
12604#define SAI_xCR1_MONO_Pos (12U)
12605#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
12606#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
12607#define SAI_xCR1_OUTDRIV_Pos (13U)
12608#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
12609#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
12610#define SAI_xCR1_SAIEN_Pos (16U)
12611#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
12612#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
12613#define SAI_xCR1_DMAEN_Pos (17U)
12614#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
12615#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
12616#define SAI_xCR1_NODIV_Pos (19U)
12617#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
12618#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
12620#define SAI_xCR1_MCKDIV_Pos (20U)
12621#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
12622#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
12623#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
12624#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
12625#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
12626#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
12628/******************* Bit definition for SAI_xCR2 register *******************/
12629#define SAI_xCR2_FTH_Pos (0U)
12630#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
12631#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
12632#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
12633#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
12634#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
12636#define SAI_xCR2_FFLUSH_Pos (3U)
12637#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
12638#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
12639#define SAI_xCR2_TRIS_Pos (4U)
12640#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
12641#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
12642#define SAI_xCR2_MUTE_Pos (5U)
12643#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
12644#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
12645#define SAI_xCR2_MUTEVAL_Pos (6U)
12646#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
12647#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
12649#define SAI_xCR2_MUTECNT_Pos (7U)
12650#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
12651#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
12652#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
12653#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
12654#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
12655#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
12656#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
12657#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
12659#define SAI_xCR2_CPL_Pos (13U)
12660#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
12661#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
12663#define SAI_xCR2_COMP_Pos (14U)
12664#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
12665#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
12666#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
12667#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
12669/****************** Bit definition for SAI_xFRCR register *******************/
12670#define SAI_xFRCR_FRL_Pos (0U)
12671#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
12672#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
12673#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
12674#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
12675#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
12676#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
12677#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
12678#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
12679#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
12680#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
12682#define SAI_xFRCR_FSALL_Pos (8U)
12683#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
12684#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
12685#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
12686#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
12687#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
12688#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
12689#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
12690#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
12691#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
12693#define SAI_xFRCR_FSDEF_Pos (16U)
12694#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
12695#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
12696#define SAI_xFRCR_FSPOL_Pos (17U)
12697#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
12698#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
12699#define SAI_xFRCR_FSOFF_Pos (18U)
12700#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
12701#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
12703/* Legacy define */
12704#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
12705
12706/****************** Bit definition for SAI_xSLOTR register *******************/
12707#define SAI_xSLOTR_FBOFF_Pos (0U)
12708#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
12709#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
12710#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
12711#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
12712#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
12713#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
12714#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
12716#define SAI_xSLOTR_SLOTSZ_Pos (6U)
12717#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
12718#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
12719#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
12720#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
12722#define SAI_xSLOTR_NBSLOT_Pos (8U)
12723#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
12724#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
12725#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
12726#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
12727#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
12728#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
12730#define SAI_xSLOTR_SLOTEN_Pos (16U)
12731#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
12732#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
12734/******************* Bit definition for SAI_xIMR register *******************/
12735#define SAI_xIMR_OVRUDRIE_Pos (0U)
12736#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
12737#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
12738#define SAI_xIMR_MUTEDETIE_Pos (1U)
12739#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
12740#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
12741#define SAI_xIMR_WCKCFGIE_Pos (2U)
12742#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
12743#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
12744#define SAI_xIMR_FREQIE_Pos (3U)
12745#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
12746#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
12747#define SAI_xIMR_CNRDYIE_Pos (4U)
12748#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
12749#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
12750#define SAI_xIMR_AFSDETIE_Pos (5U)
12751#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
12752#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
12753#define SAI_xIMR_LFSDETIE_Pos (6U)
12754#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
12755#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
12757/******************** Bit definition for SAI_xSR register *******************/
12758#define SAI_xSR_OVRUDR_Pos (0U)
12759#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
12760#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
12761#define SAI_xSR_MUTEDET_Pos (1U)
12762#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
12763#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
12764#define SAI_xSR_WCKCFG_Pos (2U)
12765#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
12766#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
12767#define SAI_xSR_FREQ_Pos (3U)
12768#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
12769#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
12770#define SAI_xSR_CNRDY_Pos (4U)
12771#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
12772#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
12773#define SAI_xSR_AFSDET_Pos (5U)
12774#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
12775#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
12776#define SAI_xSR_LFSDET_Pos (6U)
12777#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
12778#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
12780#define SAI_xSR_FLVL_Pos (16U)
12781#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
12782#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
12783#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
12784#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
12785#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
12787/****************** Bit definition for SAI_xCLRFR register ******************/
12788#define SAI_xCLRFR_COVRUDR_Pos (0U)
12789#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
12790#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
12791#define SAI_xCLRFR_CMUTEDET_Pos (1U)
12792#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
12793#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
12794#define SAI_xCLRFR_CWCKCFG_Pos (2U)
12795#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
12796#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
12797#define SAI_xCLRFR_CFREQ_Pos (3U)
12798#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
12799#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
12800#define SAI_xCLRFR_CCNRDY_Pos (4U)
12801#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
12802#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
12803#define SAI_xCLRFR_CAFSDET_Pos (5U)
12804#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
12805#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
12806#define SAI_xCLRFR_CLFSDET_Pos (6U)
12807#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
12808#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
12810/****************** Bit definition for SAI_xDR register *********************/
12811#define SAI_xDR_DATA_Pos (0U)
12812#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
12813#define SAI_xDR_DATA SAI_xDR_DATA_Msk
12814
12815/******************************************************************************/
12816/* */
12817/* SPDIF-RX Interface */
12818/* */
12819/******************************************************************************/
12820/******************** Bit definition for SPDIF_CR register *******************/
12821#define SPDIFRX_CR_SPDIFEN_Pos (0U)
12822#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
12823#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk
12824#define SPDIFRX_CR_RXDMAEN_Pos (2U)
12825#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
12826#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk
12827#define SPDIFRX_CR_RXSTEO_Pos (3U)
12828#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
12829#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk
12830#define SPDIFRX_CR_DRFMT_Pos (4U)
12831#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos)
12832#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk
12833#define SPDIFRX_CR_PMSK_Pos (6U)
12834#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos)
12835#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk
12836#define SPDIFRX_CR_VMSK_Pos (7U)
12837#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos)
12838#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk
12839#define SPDIFRX_CR_CUMSK_Pos (8U)
12840#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos)
12841#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk
12842#define SPDIFRX_CR_PTMSK_Pos (9U)
12843#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos)
12844#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk
12845#define SPDIFRX_CR_CBDMAEN_Pos (10U)
12846#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
12847#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk
12848#define SPDIFRX_CR_CHSEL_Pos (11U)
12849#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos)
12850#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk
12851#define SPDIFRX_CR_NBTR_Pos (12U)
12852#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos)
12853#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk
12854#define SPDIFRX_CR_WFA_Pos (14U)
12855#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos)
12856#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk
12857#define SPDIFRX_CR_INSEL_Pos (16U)
12858#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos)
12859#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk
12861/******************* Bit definition for SPDIFRX_IMR register *******************/
12862#define SPDIFRX_IMR_RXNEIE_Pos (0U)
12863#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
12864#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk
12865#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
12866#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
12867#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk
12868#define SPDIFRX_IMR_PERRIE_Pos (2U)
12869#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
12870#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk
12871#define SPDIFRX_IMR_OVRIE_Pos (3U)
12872#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
12873#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk
12874#define SPDIFRX_IMR_SBLKIE_Pos (4U)
12875#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
12876#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk
12877#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
12878#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
12879#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk
12880#define SPDIFRX_IMR_IFEIE_Pos (6U)
12881#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
12882#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk
12884/******************* Bit definition for SPDIFRX_SR register *******************/
12885#define SPDIFRX_SR_RXNE_Pos (0U)
12886#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos)
12887#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk
12888#define SPDIFRX_SR_CSRNE_Pos (1U)
12889#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos)
12890#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk
12891#define SPDIFRX_SR_PERR_Pos (2U)
12892#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos)
12893#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk
12894#define SPDIFRX_SR_OVR_Pos (3U)
12895#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos)
12896#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk
12897#define SPDIFRX_SR_SBD_Pos (4U)
12898#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos)
12899#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk
12900#define SPDIFRX_SR_SYNCD_Pos (5U)
12901#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos)
12902#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk
12903#define SPDIFRX_SR_FERR_Pos (6U)
12904#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos)
12905#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk
12906#define SPDIFRX_SR_SERR_Pos (7U)
12907#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos)
12908#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk
12909#define SPDIFRX_SR_TERR_Pos (8U)
12910#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos)
12911#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk
12912#define SPDIFRX_SR_WIDTH5_Pos (16U)
12913#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
12914#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk
12916/******************* Bit definition for SPDIFRX_IFCR register *******************/
12917#define SPDIFRX_IFCR_PERRCF_Pos (2U)
12918#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
12919#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk
12920#define SPDIFRX_IFCR_OVRCF_Pos (3U)
12921#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
12922#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk
12923#define SPDIFRX_IFCR_SBDCF_Pos (4U)
12924#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
12925#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk
12926#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
12927#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
12928#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk
12930/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
12931#define SPDIFRX_DR0_DR_Pos (0U)
12932#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
12933#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk
12934#define SPDIFRX_DR0_PE_Pos (24U)
12935#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos)
12936#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk
12937#define SPDIFRX_DR0_V_Pos (25U)
12938#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos)
12939#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk
12940#define SPDIFRX_DR0_U_Pos (26U)
12941#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos)
12942#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk
12943#define SPDIFRX_DR0_C_Pos (27U)
12944#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos)
12945#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk
12946#define SPDIFRX_DR0_PT_Pos (28U)
12947#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos)
12948#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk
12950/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
12951#define SPDIFRX_DR1_DR_Pos (8U)
12952#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
12953#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk
12954#define SPDIFRX_DR1_PT_Pos (4U)
12955#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos)
12956#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk
12957#define SPDIFRX_DR1_C_Pos (3U)
12958#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos)
12959#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk
12960#define SPDIFRX_DR1_U_Pos (2U)
12961#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos)
12962#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk
12963#define SPDIFRX_DR1_V_Pos (1U)
12964#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos)
12965#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk
12966#define SPDIFRX_DR1_PE_Pos (0U)
12967#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos)
12968#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk
12970/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
12971#define SPDIFRX_DR1_DRNL1_Pos (16U)
12972#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
12973#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk
12974#define SPDIFRX_DR1_DRNL2_Pos (0U)
12975#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
12976#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk
12978/******************* Bit definition for SPDIFRX_CSR register *******************/
12979#define SPDIFRX_CSR_USR_Pos (0U)
12980#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
12981#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk
12982#define SPDIFRX_CSR_CS_Pos (16U)
12983#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos)
12984#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk
12985#define SPDIFRX_CSR_SOB_Pos (24U)
12986#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos)
12987#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk
12989/******************* Bit definition for SPDIFRX_DIR register *******************/
12990#define SPDIFRX_DIR_THI_Pos (0U)
12991#define SPDIFRX_DIR_THI_Msk (0x13FFUL << SPDIFRX_DIR_THI_Pos)
12992#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk
12993#define SPDIFRX_DIR_TLO_Pos (16U)
12994#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
12995#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk
12997/******************************************************************************/
12998/* */
12999/* SD host Interface */
13000/* */
13001/******************************************************************************/
13002/****************** Bit definition for SDMMC_POWER register ******************/
13003#define SDMMC_POWER_PWRCTRL_Pos (0U)
13004#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
13005#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
13006#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
13007#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
13009/****************** Bit definition for SDMMC_CLKCR register ******************/
13010#define SDMMC_CLKCR_CLKDIV_Pos (0U)
13011#define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)
13012#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
13013#define SDMMC_CLKCR_CLKEN_Pos (8U)
13014#define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos)
13015#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk
13016#define SDMMC_CLKCR_PWRSAV_Pos (9U)
13017#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
13018#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
13019#define SDMMC_CLKCR_BYPASS_Pos (10U)
13020#define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos)
13021#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk
13023#define SDMMC_CLKCR_WIDBUS_Pos (11U)
13024#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
13025#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
13026#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
13027#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
13029#define SDMMC_CLKCR_NEGEDGE_Pos (13U)
13030#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
13031#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
13032#define SDMMC_CLKCR_HWFC_EN_Pos (14U)
13033#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
13034#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
13036/******************* Bit definition for SDMMC_ARG register *******************/
13037#define SDMMC_ARG_CMDARG_Pos (0U)
13038#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
13039#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
13041/******************* Bit definition for SDMMC_CMD register *******************/
13042#define SDMMC_CMD_CMDINDEX_Pos (0U)
13043#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
13044#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
13046#define SDMMC_CMD_WAITRESP_Pos (6U)
13047#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
13048#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
13049#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
13050#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
13052#define SDMMC_CMD_WAITINT_Pos (8U)
13053#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
13054#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
13055#define SDMMC_CMD_WAITPEND_Pos (9U)
13056#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
13057#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
13058#define SDMMC_CMD_CPSMEN_Pos (10U)
13059#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
13060#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
13061#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
13062#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)
13063#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk
13065/***************** Bit definition for SDMMC_RESPCMD register *****************/
13066#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
13067#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
13068#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
13070/****************** Bit definition for SDMMC_RESP0 register ******************/
13071#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
13072#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
13073#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk
13075/****************** Bit definition for SDMMC_RESP1 register ******************/
13076#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
13077#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
13078#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
13080/****************** Bit definition for SDMMC_RESP2 register ******************/
13081#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
13082#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
13083#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
13085/****************** Bit definition for SDMMC_RESP3 register ******************/
13086#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
13087#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
13088#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
13090/****************** Bit definition for SDMMC_RESP4 register ******************/
13091#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
13092#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
13093#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
13095/****************** Bit definition for SDMMC_DTIMER register *****************/
13096#define SDMMC_DTIMER_DATATIME_Pos (0U)
13097#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
13098#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
13100/****************** Bit definition for SDMMC_DLEN register *******************/
13101#define SDMMC_DLEN_DATALENGTH_Pos (0U)
13102#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
13103#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
13105/****************** Bit definition for SDMMC_DCTRL register ******************/
13106#define SDMMC_DCTRL_DTEN_Pos (0U)
13107#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
13108#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
13109#define SDMMC_DCTRL_DTDIR_Pos (1U)
13110#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
13111#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
13112#define SDMMC_DCTRL_DTMODE_Pos (2U)
13113#define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
13114#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
13115#define SDMMC_DCTRL_DMAEN_Pos (3U)
13116#define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos)
13117#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk
13119#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
13120#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
13121#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
13122#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
13123#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
13124#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
13125#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
13127#define SDMMC_DCTRL_RWSTART_Pos (8U)
13128#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
13129#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
13130#define SDMMC_DCTRL_RWSTOP_Pos (9U)
13131#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
13132#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
13133#define SDMMC_DCTRL_RWMOD_Pos (10U)
13134#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
13135#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
13136#define SDMMC_DCTRL_SDIOEN_Pos (11U)
13137#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
13138#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
13140/****************** Bit definition for SDMMC_DCOUNT register *****************/
13141#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
13142#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
13143#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
13145/****************** Bit definition for SDMMC_STA registe ********************/
13146#define SDMMC_STA_CCRCFAIL_Pos (0U)
13147#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
13148#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
13149#define SDMMC_STA_DCRCFAIL_Pos (1U)
13150#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
13151#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
13152#define SDMMC_STA_CTIMEOUT_Pos (2U)
13153#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
13154#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
13155#define SDMMC_STA_DTIMEOUT_Pos (3U)
13156#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
13157#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
13158#define SDMMC_STA_TXUNDERR_Pos (4U)
13159#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
13160#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
13161#define SDMMC_STA_RXOVERR_Pos (5U)
13162#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
13163#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
13164#define SDMMC_STA_CMDREND_Pos (6U)
13165#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
13166#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
13167#define SDMMC_STA_CMDSENT_Pos (7U)
13168#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
13169#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
13170#define SDMMC_STA_DATAEND_Pos (8U)
13171#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
13172#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
13173#define SDMMC_STA_DBCKEND_Pos (10U)
13174#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
13175#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
13176#define SDMMC_STA_CMDACT_Pos (11U)
13177#define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos)
13178#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk
13179#define SDMMC_STA_TXACT_Pos (12U)
13180#define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos)
13181#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk
13182#define SDMMC_STA_RXACT_Pos (13U)
13183#define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos)
13184#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk
13185#define SDMMC_STA_TXFIFOHE_Pos (14U)
13186#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
13187#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
13188#define SDMMC_STA_RXFIFOHF_Pos (15U)
13189#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
13190#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
13191#define SDMMC_STA_TXFIFOF_Pos (16U)
13192#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
13193#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
13194#define SDMMC_STA_RXFIFOF_Pos (17U)
13195#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
13196#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
13197#define SDMMC_STA_TXFIFOE_Pos (18U)
13198#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
13199#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
13200#define SDMMC_STA_RXFIFOE_Pos (19U)
13201#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
13202#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
13203#define SDMMC_STA_TXDAVL_Pos (20U)
13204#define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos)
13205#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk
13206#define SDMMC_STA_RXDAVL_Pos (21U)
13207#define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos)
13208#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk
13209#define SDMMC_STA_SDIOIT_Pos (22U)
13210#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
13211#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
13213/******************* Bit definition for SDMMC_ICR register *******************/
13214#define SDMMC_ICR_CCRCFAILC_Pos (0U)
13215#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
13216#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
13217#define SDMMC_ICR_DCRCFAILC_Pos (1U)
13218#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
13219#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
13220#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
13221#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
13222#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
13223#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
13224#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
13225#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
13226#define SDMMC_ICR_TXUNDERRC_Pos (4U)
13227#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
13228#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
13229#define SDMMC_ICR_RXOVERRC_Pos (5U)
13230#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
13231#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
13232#define SDMMC_ICR_CMDRENDC_Pos (6U)
13233#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
13234#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
13235#define SDMMC_ICR_CMDSENTC_Pos (7U)
13236#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
13237#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
13238#define SDMMC_ICR_DATAENDC_Pos (8U)
13239#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
13240#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
13241#define SDMMC_ICR_DBCKENDC_Pos (10U)
13242#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
13243#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
13244#define SDMMC_ICR_SDIOITC_Pos (22U)
13245#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
13246#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
13248/****************** Bit definition for SDMMC_MASK register *******************/
13249#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
13250#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
13251#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
13252#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
13253#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
13254#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
13255#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
13256#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
13257#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
13258#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
13259#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
13260#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
13261#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
13262#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
13263#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
13264#define SDMMC_MASK_RXOVERRIE_Pos (5U)
13265#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
13266#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
13267#define SDMMC_MASK_CMDRENDIE_Pos (6U)
13268#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
13269#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
13270#define SDMMC_MASK_CMDSENTIE_Pos (7U)
13271#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
13272#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
13273#define SDMMC_MASK_DATAENDIE_Pos (8U)
13274#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
13275#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
13276#define SDMMC_MASK_DBCKENDIE_Pos (10U)
13277#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
13278#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
13279#define SDMMC_MASK_CMDACTIE_Pos (11U)
13280#define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos)
13281#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk
13282#define SDMMC_MASK_TXACTIE_Pos (12U)
13283#define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos)
13284#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk
13285#define SDMMC_MASK_RXACTIE_Pos (13U)
13286#define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos)
13287#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk
13288#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
13289#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
13290#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
13291#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
13292#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
13293#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
13294#define SDMMC_MASK_TXFIFOFIE_Pos (16U)
13295#define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)
13296#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk
13297#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
13298#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
13299#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
13300#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
13301#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
13302#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
13303#define SDMMC_MASK_RXFIFOEIE_Pos (19U)
13304#define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)
13305#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk
13306#define SDMMC_MASK_TXDAVLIE_Pos (20U)
13307#define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)
13308#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk
13309#define SDMMC_MASK_RXDAVLIE_Pos (21U)
13310#define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)
13311#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk
13312#define SDMMC_MASK_SDIOITIE_Pos (22U)
13313#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
13314#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
13316/***************** Bit definition for SDMMC_FIFOCNT register *****************/
13317#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
13318#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos)
13319#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk
13321/****************** Bit definition for SDMMC_FIFO register *******************/
13322#define SDMMC_FIFO_FIFODATA_Pos (0U)
13323#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
13324#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
13326/******************************************************************************/
13327/* */
13328/* Serial Peripheral Interface (SPI) */
13329/* */
13330/******************************************************************************/
13331/******************* Bit definition for SPI_CR1 register ********************/
13332#define SPI_CR1_CPHA_Pos (0U)
13333#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
13334#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
13335#define SPI_CR1_CPOL_Pos (1U)
13336#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
13337#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
13338#define SPI_CR1_MSTR_Pos (2U)
13339#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
13340#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
13341#define SPI_CR1_BR_Pos (3U)
13342#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
13343#define SPI_CR1_BR SPI_CR1_BR_Msk
13344#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
13345#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
13346#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
13347#define SPI_CR1_SPE_Pos (6U)
13348#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
13349#define SPI_CR1_SPE SPI_CR1_SPE_Msk
13350#define SPI_CR1_LSBFIRST_Pos (7U)
13351#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
13352#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
13353#define SPI_CR1_SSI_Pos (8U)
13354#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
13355#define SPI_CR1_SSI SPI_CR1_SSI_Msk
13356#define SPI_CR1_SSM_Pos (9U)
13357#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
13358#define SPI_CR1_SSM SPI_CR1_SSM_Msk
13359#define SPI_CR1_RXONLY_Pos (10U)
13360#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
13361#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
13362#define SPI_CR1_CRCL_Pos (11U)
13363#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
13364#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
13365#define SPI_CR1_CRCNEXT_Pos (12U)
13366#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
13367#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
13368#define SPI_CR1_CRCEN_Pos (13U)
13369#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
13370#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
13371#define SPI_CR1_BIDIOE_Pos (14U)
13372#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
13373#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
13374#define SPI_CR1_BIDIMODE_Pos (15U)
13375#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
13376#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
13378/******************* Bit definition for SPI_CR2 register ********************/
13379#define SPI_CR2_RXDMAEN_Pos (0U)
13380#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
13381#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
13382#define SPI_CR2_TXDMAEN_Pos (1U)
13383#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
13384#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
13385#define SPI_CR2_SSOE_Pos (2U)
13386#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
13387#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
13388#define SPI_CR2_NSSP_Pos (3U)
13389#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
13390#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
13391#define SPI_CR2_FRF_Pos (4U)
13392#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
13393#define SPI_CR2_FRF SPI_CR2_FRF_Msk
13394#define SPI_CR2_ERRIE_Pos (5U)
13395#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
13396#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
13397#define SPI_CR2_RXNEIE_Pos (6U)
13398#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
13399#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
13400#define SPI_CR2_TXEIE_Pos (7U)
13401#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
13402#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
13403#define SPI_CR2_DS_Pos (8U)
13404#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
13405#define SPI_CR2_DS SPI_CR2_DS_Msk
13406#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
13407#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
13408#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
13409#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
13410#define SPI_CR2_FRXTH_Pos (12U)
13411#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
13412#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
13413#define SPI_CR2_LDMARX_Pos (13U)
13414#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
13415#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
13416#define SPI_CR2_LDMATX_Pos (14U)
13417#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
13418#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
13420/******************** Bit definition for SPI_SR register ********************/
13421#define SPI_SR_RXNE_Pos (0U)
13422#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
13423#define SPI_SR_RXNE SPI_SR_RXNE_Msk
13424#define SPI_SR_TXE_Pos (1U)
13425#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
13426#define SPI_SR_TXE SPI_SR_TXE_Msk
13427#define SPI_SR_CHSIDE_Pos (2U)
13428#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
13429#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
13430#define SPI_SR_UDR_Pos (3U)
13431#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
13432#define SPI_SR_UDR SPI_SR_UDR_Msk
13433#define SPI_SR_CRCERR_Pos (4U)
13434#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
13435#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
13436#define SPI_SR_MODF_Pos (5U)
13437#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
13438#define SPI_SR_MODF SPI_SR_MODF_Msk
13439#define SPI_SR_OVR_Pos (6U)
13440#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
13441#define SPI_SR_OVR SPI_SR_OVR_Msk
13442#define SPI_SR_BSY_Pos (7U)
13443#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
13444#define SPI_SR_BSY SPI_SR_BSY_Msk
13445#define SPI_SR_FRE_Pos (8U)
13446#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
13447#define SPI_SR_FRE SPI_SR_FRE_Msk
13448#define SPI_SR_FRLVL_Pos (9U)
13449#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
13450#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
13451#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
13452#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
13453#define SPI_SR_FTLVL_Pos (11U)
13454#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
13455#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
13456#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
13457#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
13459/******************** Bit definition for SPI_DR register ********************/
13460#define SPI_DR_DR_Pos (0U)
13461#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
13462#define SPI_DR_DR SPI_DR_DR_Msk
13464/******************* Bit definition for SPI_CRCPR register ******************/
13465#define SPI_CRCPR_CRCPOLY_Pos (0U)
13466#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
13467#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
13469/****************** Bit definition for SPI_RXCRCR register ******************/
13470#define SPI_RXCRCR_RXCRC_Pos (0U)
13471#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
13472#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
13474/****************** Bit definition for SPI_TXCRCR register ******************/
13475#define SPI_TXCRCR_TXCRC_Pos (0U)
13476#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
13477#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
13479/****************** Bit definition for SPI_I2SCFGR register *****************/
13480#define SPI_I2SCFGR_CHLEN_Pos (0U)
13481#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
13482#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
13483#define SPI_I2SCFGR_DATLEN_Pos (1U)
13484#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
13485#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
13486#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
13487#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
13488#define SPI_I2SCFGR_CKPOL_Pos (3U)
13489#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
13490#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
13491#define SPI_I2SCFGR_I2SSTD_Pos (4U)
13492#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
13493#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
13494#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
13495#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
13496#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
13497#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
13498#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
13499#define SPI_I2SCFGR_I2SCFG_Pos (8U)
13500#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
13501#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
13502#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
13503#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
13504#define SPI_I2SCFGR_I2SE_Pos (10U)
13505#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
13506#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
13507#define SPI_I2SCFGR_I2SMOD_Pos (11U)
13508#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
13509#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
13510#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
13511#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
13512#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
13514/****************** Bit definition for SPI_I2SPR register *******************/
13515#define SPI_I2SPR_I2SDIV_Pos (0U)
13516#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
13517#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
13518#define SPI_I2SPR_ODD_Pos (8U)
13519#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
13520#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
13521#define SPI_I2SPR_MCKOE_Pos (9U)
13522#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
13523#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
13526/******************************************************************************/
13527/* */
13528/* SYSCFG */
13529/* */
13530/******************************************************************************/
13531/****************** Bit definition for SYSCFG_MEMRMP register ***************/
13532#define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U)
13533#define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1UL << SYSCFG_MEMRMP_MEM_BOOT_Pos)
13534#define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk
13537#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
13538#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
13539#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk
13540#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
13541#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
13543/****************** Bit definition for SYSCFG_PMC register ******************/
13544#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
13545#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos)
13546#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk
13547#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
13548#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos)
13549#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk
13550#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
13551#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos)
13552#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk
13553#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
13554#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos)
13555#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk
13556#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
13557#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos)
13558#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk
13559#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
13560#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos)
13561#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk
13562#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
13563#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos)
13564#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk
13565#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
13566#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos)
13567#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk
13569#define SYSCFG_PMC_ADCxDC2_Pos (16U)
13570#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)
13571#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk
13572#define SYSCFG_PMC_ADC1DC2_Pos (16U)
13573#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
13574#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
13575#define SYSCFG_PMC_ADC2DC2_Pos (17U)
13576#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)
13577#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk
13578#define SYSCFG_PMC_ADC3DC2_Pos (18U)
13579#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)
13580#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk
13582#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
13583#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
13584#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
13586/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
13587#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
13588#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
13589#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
13590#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
13591#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
13592#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
13593#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
13594#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
13595#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
13596#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
13597#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
13598#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
13602#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
13603#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
13604#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
13605#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
13606#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
13607#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
13608#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
13609#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
13610#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
13611#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
13612#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
13617#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
13618#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
13619#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
13620#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
13621#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
13622#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
13623#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
13624#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
13625#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
13626#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
13627#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
13632#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
13633#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
13634#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
13635#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
13636#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
13637#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
13638#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
13639#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
13640#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
13641#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
13642#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
13647#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
13648#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
13649#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
13650#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
13651#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
13652#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
13653#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
13654#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
13655#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
13656#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
13657#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
13659/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
13660#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
13661#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
13662#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
13663#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
13664#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
13665#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
13666#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
13667#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
13668#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
13669#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
13670#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
13671#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
13675#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
13676#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
13677#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
13678#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
13679#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
13680#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
13681#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
13682#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
13683#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
13684#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
13685#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
13690#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
13691#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
13692#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
13693#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
13694#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
13695#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
13696#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
13697#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
13698#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
13699#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
13700#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
13705#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
13706#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
13707#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
13708#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
13709#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
13710#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
13711#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
13712#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
13713#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
13714#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
13715#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
13720#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
13721#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
13722#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
13723#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
13724#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
13725#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
13726#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
13727#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
13728#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
13729#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
13730#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
13732/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
13733#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
13734#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
13735#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
13736#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
13737#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
13738#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
13739#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
13740#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
13741#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
13742#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
13743#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
13744#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
13749#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
13750#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
13751#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
13752#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
13753#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
13754#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
13755#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
13756#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
13757#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
13758#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
13763#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
13764#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
13765#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
13766#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
13767#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
13768#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
13769#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
13770#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
13771#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
13772#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
13777#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
13778#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
13779#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
13780#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
13781#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
13782#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
13783#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
13784#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
13785#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
13786#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
13791#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
13792#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
13793#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
13794#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
13795#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
13796#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
13797#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
13798#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
13799#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
13800#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
13803/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13804#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13805#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
13806#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
13807#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13808#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
13809#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
13810#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13811#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
13812#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
13813#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13814#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
13815#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
13819#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
13820#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
13821#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
13822#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
13823#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
13824#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
13825#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
13826#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
13827#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
13828#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
13833#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
13834#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
13835#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
13836#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
13837#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
13838#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
13839#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
13840#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
13841#define SYSCFG_EXTICR4_EXTI13_PI 0x0080U
13842#define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U
13847#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
13848#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
13849#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
13850#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
13851#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
13852#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
13853#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
13854#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
13855#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
13856#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
13861#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
13862#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
13863#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
13864#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
13865#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
13866#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
13867#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
13868#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
13869#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
13870#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
13873/****************** Bit definition for SYSCFG_CMPCR register ****************/
13874#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
13875#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
13876#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
13877#define SYSCFG_CMPCR_READY_Pos (8U)
13878#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
13879#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
13881/******************************************************************************/
13882/* */
13883/* TIM */
13884/* */
13885/******************************************************************************/
13886/******************* Bit definition for TIM_CR1 register ********************/
13887#define TIM_CR1_CEN_Pos (0U)
13888#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
13889#define TIM_CR1_CEN TIM_CR1_CEN_Msk
13890#define TIM_CR1_UDIS_Pos (1U)
13891#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
13892#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
13893#define TIM_CR1_URS_Pos (2U)
13894#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
13895#define TIM_CR1_URS TIM_CR1_URS_Msk
13896#define TIM_CR1_OPM_Pos (3U)
13897#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
13898#define TIM_CR1_OPM TIM_CR1_OPM_Msk
13899#define TIM_CR1_DIR_Pos (4U)
13900#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
13901#define TIM_CR1_DIR TIM_CR1_DIR_Msk
13903#define TIM_CR1_CMS_Pos (5U)
13904#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
13905#define TIM_CR1_CMS TIM_CR1_CMS_Msk
13906#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
13907#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
13909#define TIM_CR1_ARPE_Pos (7U)
13910#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
13911#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
13913#define TIM_CR1_CKD_Pos (8U)
13914#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
13915#define TIM_CR1_CKD TIM_CR1_CKD_Msk
13916#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
13917#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
13918#define TIM_CR1_UIFREMAP_Pos (11U)
13919#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
13920#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
13922/******************* Bit definition for TIM_CR2 register ********************/
13923#define TIM_CR2_CCPC_Pos (0U)
13924#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
13925#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
13926#define TIM_CR2_CCUS_Pos (2U)
13927#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
13928#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
13929#define TIM_CR2_CCDS_Pos (3U)
13930#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
13931#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
13933#define TIM_CR2_OIS5_Pos (16U)
13934#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
13935#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
13936#define TIM_CR2_OIS6_Pos (18U)
13937#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
13938#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
13940#define TIM_CR2_MMS_Pos (4U)
13941#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
13942#define TIM_CR2_MMS TIM_CR2_MMS_Msk
13943#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
13944#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
13945#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
13947#define TIM_CR2_MMS2_Pos (20U)
13948#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
13949#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
13950#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
13951#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
13952#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
13953#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
13955#define TIM_CR2_TI1S_Pos (7U)
13956#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
13957#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
13958#define TIM_CR2_OIS1_Pos (8U)
13959#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
13960#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
13961#define TIM_CR2_OIS1N_Pos (9U)
13962#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
13963#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
13964#define TIM_CR2_OIS2_Pos (10U)
13965#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
13966#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
13967#define TIM_CR2_OIS2N_Pos (11U)
13968#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
13969#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
13970#define TIM_CR2_OIS3_Pos (12U)
13971#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
13972#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
13973#define TIM_CR2_OIS3N_Pos (13U)
13974#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
13975#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
13976#define TIM_CR2_OIS4_Pos (14U)
13977#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
13978#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
13980/******************* Bit definition for TIM_SMCR register *******************/
13981#define TIM_SMCR_SMS_Pos (0U)
13982#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
13983#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
13984#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
13985#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
13986#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
13987#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
13989#define TIM_SMCR_TS_Pos (4U)
13990#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
13991#define TIM_SMCR_TS TIM_SMCR_TS_Msk
13992#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
13993#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
13994#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
13996#define TIM_SMCR_MSM_Pos (7U)
13997#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
13998#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
14000#define TIM_SMCR_ETF_Pos (8U)
14001#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
14002#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
14003#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
14004#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
14005#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
14006#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
14008#define TIM_SMCR_ETPS_Pos (12U)
14009#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
14010#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
14011#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
14012#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
14014#define TIM_SMCR_ECE_Pos (14U)
14015#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
14016#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
14017#define TIM_SMCR_ETP_Pos (15U)
14018#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
14019#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
14021/******************* Bit definition for TIM_DIER register *******************/
14022#define TIM_DIER_UIE_Pos (0U)
14023#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
14024#define TIM_DIER_UIE TIM_DIER_UIE_Msk
14025#define TIM_DIER_CC1IE_Pos (1U)
14026#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
14027#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
14028#define TIM_DIER_CC2IE_Pos (2U)
14029#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
14030#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
14031#define TIM_DIER_CC3IE_Pos (3U)
14032#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
14033#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
14034#define TIM_DIER_CC4IE_Pos (4U)
14035#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
14036#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
14037#define TIM_DIER_COMIE_Pos (5U)
14038#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
14039#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
14040#define TIM_DIER_TIE_Pos (6U)
14041#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
14042#define TIM_DIER_TIE TIM_DIER_TIE_Msk
14043#define TIM_DIER_BIE_Pos (7U)
14044#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
14045#define TIM_DIER_BIE TIM_DIER_BIE_Msk
14046#define TIM_DIER_UDE_Pos (8U)
14047#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
14048#define TIM_DIER_UDE TIM_DIER_UDE_Msk
14049#define TIM_DIER_CC1DE_Pos (9U)
14050#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
14051#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
14052#define TIM_DIER_CC2DE_Pos (10U)
14053#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
14054#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
14055#define TIM_DIER_CC3DE_Pos (11U)
14056#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
14057#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
14058#define TIM_DIER_CC4DE_Pos (12U)
14059#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
14060#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
14061#define TIM_DIER_COMDE_Pos (13U)
14062#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
14063#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
14064#define TIM_DIER_TDE_Pos (14U)
14065#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
14066#define TIM_DIER_TDE TIM_DIER_TDE_Msk
14068/******************** Bit definition for TIM_SR register ********************/
14069#define TIM_SR_UIF_Pos (0U)
14070#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
14071#define TIM_SR_UIF TIM_SR_UIF_Msk
14072#define TIM_SR_CC1IF_Pos (1U)
14073#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
14074#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
14075#define TIM_SR_CC2IF_Pos (2U)
14076#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
14077#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
14078#define TIM_SR_CC3IF_Pos (3U)
14079#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
14080#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
14081#define TIM_SR_CC4IF_Pos (4U)
14082#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
14083#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
14084#define TIM_SR_COMIF_Pos (5U)
14085#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
14086#define TIM_SR_COMIF TIM_SR_COMIF_Msk
14087#define TIM_SR_TIF_Pos (6U)
14088#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
14089#define TIM_SR_TIF TIM_SR_TIF_Msk
14090#define TIM_SR_BIF_Pos (7U)
14091#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
14092#define TIM_SR_BIF TIM_SR_BIF_Msk
14093#define TIM_SR_B2IF_Pos (8U)
14094#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
14095#define TIM_SR_B2IF TIM_SR_B2IF_Msk
14096#define TIM_SR_CC1OF_Pos (9U)
14097#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
14098#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
14099#define TIM_SR_CC2OF_Pos (10U)
14100#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
14101#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
14102#define TIM_SR_CC3OF_Pos (11U)
14103#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
14104#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
14105#define TIM_SR_CC4OF_Pos (12U)
14106#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
14107#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
14108#define TIM_SR_SBIF_Pos (13U)
14109#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
14110#define TIM_SR_SBIF TIM_SR_SBIF_Msk
14111#define TIM_SR_CC5IF_Pos (16U)
14112#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
14113#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
14114#define TIM_SR_CC6IF_Pos (17U)
14115#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
14116#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
14118/******************* Bit definition for TIM_EGR register ********************/
14119#define TIM_EGR_UG_Pos (0U)
14120#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
14121#define TIM_EGR_UG TIM_EGR_UG_Msk
14122#define TIM_EGR_CC1G_Pos (1U)
14123#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
14124#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
14125#define TIM_EGR_CC2G_Pos (2U)
14126#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
14127#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
14128#define TIM_EGR_CC3G_Pos (3U)
14129#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
14130#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
14131#define TIM_EGR_CC4G_Pos (4U)
14132#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
14133#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
14134#define TIM_EGR_COMG_Pos (5U)
14135#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
14136#define TIM_EGR_COMG TIM_EGR_COMG_Msk
14137#define TIM_EGR_TG_Pos (6U)
14138#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
14139#define TIM_EGR_TG TIM_EGR_TG_Msk
14140#define TIM_EGR_BG_Pos (7U)
14141#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
14142#define TIM_EGR_BG TIM_EGR_BG_Msk
14143#define TIM_EGR_B2G_Pos (8U)
14144#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
14145#define TIM_EGR_B2G TIM_EGR_B2G_Msk
14147/****************** Bit definition for TIM_CCMR1 register *******************/
14148#define TIM_CCMR1_CC1S_Pos (0U)
14149#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
14150#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
14151#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
14152#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
14154#define TIM_CCMR1_OC1FE_Pos (2U)
14155#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
14156#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
14157#define TIM_CCMR1_OC1PE_Pos (3U)
14158#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
14159#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
14161#define TIM_CCMR1_OC1M_Pos (4U)
14162#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
14163#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
14164#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
14165#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
14166#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
14167#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
14169#define TIM_CCMR1_OC1CE_Pos (7U)
14170#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
14171#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
14173#define TIM_CCMR1_CC2S_Pos (8U)
14174#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
14175#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
14176#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
14177#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
14179#define TIM_CCMR1_OC2FE_Pos (10U)
14180#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
14181#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
14182#define TIM_CCMR1_OC2PE_Pos (11U)
14183#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
14184#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
14186#define TIM_CCMR1_OC2M_Pos (12U)
14187#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
14188#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
14189#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
14190#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
14191#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
14192#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
14194#define TIM_CCMR1_OC2CE_Pos (15U)
14195#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
14196#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
14198/*----------------------------------------------------------------------------*/
14199
14200#define TIM_CCMR1_IC1PSC_Pos (2U)
14201#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
14202#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
14203#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
14204#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
14206#define TIM_CCMR1_IC1F_Pos (4U)
14207#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
14208#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
14209#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
14210#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
14211#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
14212#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
14214#define TIM_CCMR1_IC2PSC_Pos (10U)
14215#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
14216#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
14217#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
14218#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
14220#define TIM_CCMR1_IC2F_Pos (12U)
14221#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
14222#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
14223#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
14224#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
14225#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
14226#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
14228/****************** Bit definition for TIM_CCMR2 register *******************/
14229#define TIM_CCMR2_CC3S_Pos (0U)
14230#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
14231#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
14232#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
14233#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
14235#define TIM_CCMR2_OC3FE_Pos (2U)
14236#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
14237#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
14238#define TIM_CCMR2_OC3PE_Pos (3U)
14239#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
14240#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
14242#define TIM_CCMR2_OC3M_Pos (4U)
14243#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
14244#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
14245#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)
14246#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)
14247#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)
14248#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
14252#define TIM_CCMR2_OC3CE_Pos (7U)
14253#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
14254#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
14256#define TIM_CCMR2_CC4S_Pos (8U)
14257#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
14258#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
14259#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
14260#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
14262#define TIM_CCMR2_OC4FE_Pos (10U)
14263#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
14264#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
14265#define TIM_CCMR2_OC4PE_Pos (11U)
14266#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
14267#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
14269#define TIM_CCMR2_OC4M_Pos (12U)
14270#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
14271#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
14272#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)
14273#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)
14274#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)
14275#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
14277#define TIM_CCMR2_OC4CE_Pos (15U)
14278#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
14279#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
14281/*----------------------------------------------------------------------------*/
14282
14283#define TIM_CCMR2_IC3PSC_Pos (2U)
14284#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
14285#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
14286#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
14287#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
14289#define TIM_CCMR2_IC3F_Pos (4U)
14290#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
14291#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
14292#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
14293#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
14294#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
14295#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
14297#define TIM_CCMR2_IC4PSC_Pos (10U)
14298#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
14299#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
14300#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
14301#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
14303#define TIM_CCMR2_IC4F_Pos (12U)
14304#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
14305#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
14306#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
14307#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
14308#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
14309#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
14311/******************* Bit definition for TIM_CCER register *******************/
14312#define TIM_CCER_CC1E_Pos (0U)
14313#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
14314#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
14315#define TIM_CCER_CC1P_Pos (1U)
14316#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
14317#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
14318#define TIM_CCER_CC1NE_Pos (2U)
14319#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
14320#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
14321#define TIM_CCER_CC1NP_Pos (3U)
14322#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
14323#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
14324#define TIM_CCER_CC2E_Pos (4U)
14325#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
14326#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
14327#define TIM_CCER_CC2P_Pos (5U)
14328#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
14329#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
14330#define TIM_CCER_CC2NE_Pos (6U)
14331#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
14332#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
14333#define TIM_CCER_CC2NP_Pos (7U)
14334#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
14335#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
14336#define TIM_CCER_CC3E_Pos (8U)
14337#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
14338#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
14339#define TIM_CCER_CC3P_Pos (9U)
14340#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
14341#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
14342#define TIM_CCER_CC3NE_Pos (10U)
14343#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
14344#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
14345#define TIM_CCER_CC3NP_Pos (11U)
14346#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
14347#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
14348#define TIM_CCER_CC4E_Pos (12U)
14349#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
14350#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
14351#define TIM_CCER_CC4P_Pos (13U)
14352#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
14353#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
14354#define TIM_CCER_CC4NP_Pos (15U)
14355#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
14356#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
14357#define TIM_CCER_CC5E_Pos (16U)
14358#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
14359#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
14360#define TIM_CCER_CC5P_Pos (17U)
14361#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
14362#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
14363#define TIM_CCER_CC6E_Pos (20U)
14364#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
14365#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
14366#define TIM_CCER_CC6P_Pos (21U)
14367#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
14368#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
14371/******************* Bit definition for TIM_CNT register ********************/
14372#define TIM_CNT_CNT_Pos (0U)
14373#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
14374#define TIM_CNT_CNT TIM_CNT_CNT_Msk
14375#define TIM_CNT_UIFCPY_Pos (31U)
14376#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
14377#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
14379/******************* Bit definition for TIM_PSC register ********************/
14380#define TIM_PSC_PSC_Pos (0U)
14381#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
14382#define TIM_PSC_PSC TIM_PSC_PSC_Msk
14384/******************* Bit definition for TIM_ARR register ********************/
14385#define TIM_ARR_ARR_Pos (0U)
14386#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
14387#define TIM_ARR_ARR TIM_ARR_ARR_Msk
14389/******************* Bit definition for TIM_RCR register ********************/
14390#define TIM_RCR_REP_Pos (0U)
14391#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)
14392#define TIM_RCR_REP TIM_RCR_REP_Msk
14394/******************* Bit definition for TIM_CCR1 register *******************/
14395#define TIM_CCR1_CCR1_Pos (0U)
14396#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
14397#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
14399/******************* Bit definition for TIM_CCR2 register *******************/
14400#define TIM_CCR2_CCR2_Pos (0U)
14401#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
14402#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
14404/******************* Bit definition for TIM_CCR3 register *******************/
14405#define TIM_CCR3_CCR3_Pos (0U)
14406#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
14407#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
14409/******************* Bit definition for TIM_CCR4 register *******************/
14410#define TIM_CCR4_CCR4_Pos (0U)
14411#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
14412#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
14414/******************* Bit definition for TIM_BDTR register *******************/
14415#define TIM_BDTR_DTG_Pos (0U)
14416#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
14417#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
14418#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
14419#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
14420#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
14421#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
14422#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
14423#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
14424#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
14425#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
14427#define TIM_BDTR_LOCK_Pos (8U)
14428#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
14429#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
14430#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
14431#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
14433#define TIM_BDTR_OSSI_Pos (10U)
14434#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
14435#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
14436#define TIM_BDTR_OSSR_Pos (11U)
14437#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
14438#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
14439#define TIM_BDTR_BKE_Pos (12U)
14440#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
14441#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
14442#define TIM_BDTR_BKP_Pos (13U)
14443#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
14444#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
14445#define TIM_BDTR_AOE_Pos (14U)
14446#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
14447#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
14448#define TIM_BDTR_MOE_Pos (15U)
14449#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
14450#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
14451#define TIM_BDTR_BKF_Pos (16U)
14452#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
14453#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
14454#define TIM_BDTR_BK2F_Pos (20U)
14455#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
14456#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
14457#define TIM_BDTR_BK2E_Pos (24U)
14458#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
14459#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
14460#define TIM_BDTR_BK2P_Pos (25U)
14461#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
14462#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
14464/******************* Bit definition for TIM_DCR register ********************/
14465#define TIM_DCR_DBA_Pos (0U)
14466#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
14467#define TIM_DCR_DBA TIM_DCR_DBA_Msk
14468#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
14469#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
14470#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
14471#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
14472#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
14474#define TIM_DCR_DBL_Pos (8U)
14475#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
14476#define TIM_DCR_DBL TIM_DCR_DBL_Msk
14477#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
14478#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
14479#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
14480#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
14481#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
14483/******************* Bit definition for TIM_DMAR register *******************/
14484#define TIM_DMAR_DMAB_Pos (0U)
14485#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
14486#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
14488/******************* Bit definition for TIM_OR regiter *********************/
14489#define TIM_OR_TI4_RMP_Pos (6U)
14490#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
14491#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
14492#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
14493#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
14494#define TIM_OR_ITR1_RMP_Pos (10U)
14495#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
14496#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
14497#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
14498#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
14500/******************* Bit definition for TIM2_OR register *******************/
14501#define TIM2_OR_ITR1_RMP_Pos (10U)
14502#define TIM2_OR_ITR1_RMP_Msk (0x3UL << TIM2_OR_ITR1_RMP_Pos)
14503#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk
14504#define TIM2_OR_ITR1_RMP_0 (0x1UL << TIM2_OR_ITR1_RMP_Pos)
14505#define TIM2_OR_ITR1_RMP_1 (0x2UL << TIM2_OR_ITR1_RMP_Pos)
14507/******************* Bit definition for TIM5_OR register *******************/
14508#define TIM5_OR_TI4_RMP_Pos (6U)
14509#define TIM5_OR_TI4_RMP_Msk (0x3UL << TIM5_OR_TI4_RMP_Pos)
14510#define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk
14511#define TIM5_OR_TI4_RMP_0 (0x1UL << TIM5_OR_TI4_RMP_Pos)
14512#define TIM5_OR_TI4_RMP_1 (0x2UL << TIM5_OR_TI4_RMP_Pos)
14514/******************* Bit definition for TIM11_OR register *******************/
14515#define TIM11_OR_TI1_RMP_Pos (0U)
14516#define TIM11_OR_TI1_RMP_Msk (0x3UL << TIM11_OR_TI1_RMP_Pos)
14517#define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk
14518#define TIM11_OR_TI1_RMP_0 (0x1UL << TIM11_OR_TI1_RMP_Pos)
14519#define TIM11_OR_TI1_RMP_1 (0x2UL << TIM11_OR_TI1_RMP_Pos)
14521/****************** Bit definition for TIM_CCMR3 register *******************/
14522#define TIM_CCMR3_OC5FE_Pos (2U)
14523#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
14524#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
14525#define TIM_CCMR3_OC5PE_Pos (3U)
14526#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
14527#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
14529#define TIM_CCMR3_OC5M_Pos (4U)
14530#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
14531#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
14532#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)
14533#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)
14534#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)
14535#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
14537#define TIM_CCMR3_OC5CE_Pos (7U)
14538#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
14539#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
14541#define TIM_CCMR3_OC6FE_Pos (10U)
14542#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
14543#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
14544#define TIM_CCMR3_OC6PE_Pos (11U)
14545#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
14546#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
14548#define TIM_CCMR3_OC6M_Pos (12U)
14549#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
14550#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
14551#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)
14552#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)
14553#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)
14554#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
14556#define TIM_CCMR3_OC6CE_Pos (15U)
14557#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
14558#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
14560/******************* Bit definition for TIM_CCR5 register *******************/
14561#define TIM_CCR5_CCR5_Pos (0U)
14562#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
14563#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
14564#define TIM_CCR5_GC5C1_Pos (29U)
14565#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
14566#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
14567#define TIM_CCR5_GC5C2_Pos (30U)
14568#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
14569#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
14570#define TIM_CCR5_GC5C3_Pos (31U)
14571#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
14572#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
14574/******************* Bit definition for TIM_CCR6 register *******************/
14575#define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU)
14578/******************************************************************************/
14579/* */
14580/* Low Power Timer (LPTIM) */
14581/* */
14582/******************************************************************************/
14583/****************** Bit definition for LPTIM_ISR register *******************/
14584#define LPTIM_ISR_CMPM_Pos (0U)
14585#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
14586#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
14587#define LPTIM_ISR_ARRM_Pos (1U)
14588#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
14589#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
14590#define LPTIM_ISR_EXTTRIG_Pos (2U)
14591#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
14592#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
14593#define LPTIM_ISR_CMPOK_Pos (3U)
14594#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
14595#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
14596#define LPTIM_ISR_ARROK_Pos (4U)
14597#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
14598#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
14599#define LPTIM_ISR_UP_Pos (5U)
14600#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
14601#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
14602#define LPTIM_ISR_DOWN_Pos (6U)
14603#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
14604#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
14606/****************** Bit definition for LPTIM_ICR register *******************/
14607#define LPTIM_ICR_CMPMCF_Pos (0U)
14608#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
14609#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
14610#define LPTIM_ICR_ARRMCF_Pos (1U)
14611#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
14612#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
14613#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
14614#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
14615#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
14616#define LPTIM_ICR_CMPOKCF_Pos (3U)
14617#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
14618#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
14619#define LPTIM_ICR_ARROKCF_Pos (4U)
14620#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
14621#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
14622#define LPTIM_ICR_UPCF_Pos (5U)
14623#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
14624#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
14625#define LPTIM_ICR_DOWNCF_Pos (6U)
14626#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
14627#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
14629/****************** Bit definition for LPTIM_IER register *******************/
14630#define LPTIM_IER_CMPMIE_Pos (0U)
14631#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
14632#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
14633#define LPTIM_IER_ARRMIE_Pos (1U)
14634#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
14635#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
14636#define LPTIM_IER_EXTTRIGIE_Pos (2U)
14637#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
14638#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
14639#define LPTIM_IER_CMPOKIE_Pos (3U)
14640#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
14641#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
14642#define LPTIM_IER_ARROKIE_Pos (4U)
14643#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
14644#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
14645#define LPTIM_IER_UPIE_Pos (5U)
14646#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
14647#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
14648#define LPTIM_IER_DOWNIE_Pos (6U)
14649#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
14650#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
14652/****************** Bit definition for LPTIM_CFGR register*******************/
14653#define LPTIM_CFGR_CKSEL_Pos (0U)
14654#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
14655#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
14657#define LPTIM_CFGR_CKPOL_Pos (1U)
14658#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
14659#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
14660#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
14661#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
14663#define LPTIM_CFGR_CKFLT_Pos (3U)
14664#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
14665#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
14666#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
14667#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
14669#define LPTIM_CFGR_TRGFLT_Pos (6U)
14670#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
14671#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
14672#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
14673#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
14675#define LPTIM_CFGR_PRESC_Pos (9U)
14676#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
14677#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
14678#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
14679#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
14680#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
14682#define LPTIM_CFGR_TRIGSEL_Pos (13U)
14683#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
14684#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
14685#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
14686#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
14687#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
14689#define LPTIM_CFGR_TRIGEN_Pos (17U)
14690#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
14691#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
14692#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
14693#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
14695#define LPTIM_CFGR_TIMOUT_Pos (19U)
14696#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
14697#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
14698#define LPTIM_CFGR_WAVE_Pos (20U)
14699#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
14700#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
14701#define LPTIM_CFGR_WAVPOL_Pos (21U)
14702#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
14703#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
14704#define LPTIM_CFGR_PRELOAD_Pos (22U)
14705#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
14706#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
14707#define LPTIM_CFGR_COUNTMODE_Pos (23U)
14708#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
14709#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
14710#define LPTIM_CFGR_ENC_Pos (24U)
14711#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
14712#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
14714/****************** Bit definition for LPTIM_CR register ********************/
14715#define LPTIM_CR_ENABLE_Pos (0U)
14716#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
14717#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
14718#define LPTIM_CR_SNGSTRT_Pos (1U)
14719#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
14720#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
14721#define LPTIM_CR_CNTSTRT_Pos (2U)
14722#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
14723#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
14725/****************** Bit definition for LPTIM_CMP register *******************/
14726#define LPTIM_CMP_CMP_Pos (0U)
14727#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
14728#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
14730/****************** Bit definition for LPTIM_ARR register *******************/
14731#define LPTIM_ARR_ARR_Pos (0U)
14732#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
14733#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
14735/****************** Bit definition for LPTIM_CNT register *******************/
14736#define LPTIM_CNT_CNT_Pos (0U)
14737#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
14738#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
14739/******************************************************************************/
14740/* */
14741/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
14742/* */
14743/******************************************************************************/
14744/****************** Bit definition for USART_CR1 register *******************/
14745#define USART_CR1_UE_Pos (0U)
14746#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
14747#define USART_CR1_UE USART_CR1_UE_Msk
14748#define USART_CR1_RE_Pos (2U)
14749#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
14750#define USART_CR1_RE USART_CR1_RE_Msk
14751#define USART_CR1_TE_Pos (3U)
14752#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
14753#define USART_CR1_TE USART_CR1_TE_Msk
14754#define USART_CR1_IDLEIE_Pos (4U)
14755#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
14756#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
14757#define USART_CR1_RXNEIE_Pos (5U)
14758#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
14759#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
14760#define USART_CR1_TCIE_Pos (6U)
14761#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
14762#define USART_CR1_TCIE USART_CR1_TCIE_Msk
14763#define USART_CR1_TXEIE_Pos (7U)
14764#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
14765#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
14766#define USART_CR1_PEIE_Pos (8U)
14767#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
14768#define USART_CR1_PEIE USART_CR1_PEIE_Msk
14769#define USART_CR1_PS_Pos (9U)
14770#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
14771#define USART_CR1_PS USART_CR1_PS_Msk
14772#define USART_CR1_PCE_Pos (10U)
14773#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
14774#define USART_CR1_PCE USART_CR1_PCE_Msk
14775#define USART_CR1_WAKE_Pos (11U)
14776#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
14777#define USART_CR1_WAKE USART_CR1_WAKE_Msk
14778#define USART_CR1_M_Pos (12U)
14779#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
14780#define USART_CR1_M USART_CR1_M_Msk
14781#define USART_CR1_M0 (0x00001UL << USART_CR1_M_Pos)
14782#define USART_CR1_MME_Pos (13U)
14783#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
14784#define USART_CR1_MME USART_CR1_MME_Msk
14785#define USART_CR1_CMIE_Pos (14U)
14786#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
14787#define USART_CR1_CMIE USART_CR1_CMIE_Msk
14788#define USART_CR1_OVER8_Pos (15U)
14789#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
14790#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
14791#define USART_CR1_DEDT_Pos (16U)
14792#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
14793#define USART_CR1_DEDT USART_CR1_DEDT_Msk
14794#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
14795#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
14796#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
14797#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
14798#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
14799#define USART_CR1_DEAT_Pos (21U)
14800#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
14801#define USART_CR1_DEAT USART_CR1_DEAT_Msk
14802#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
14803#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
14804#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
14805#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
14806#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
14807#define USART_CR1_RTOIE_Pos (26U)
14808#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
14809#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
14810#define USART_CR1_EOBIE_Pos (27U)
14811#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
14812#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
14813#define USART_CR1_M1 0x10000000U
14815/* Legacy defines */
14816#define USART_CR1_M_0 USART_CR1_M0
14817#define USART_CR1_M_1 USART_CR1_M1
14819/****************** Bit definition for USART_CR2 register *******************/
14820#define USART_CR2_ADDM7_Pos (4U)
14821#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
14822#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
14823#define USART_CR2_LBDL_Pos (5U)
14824#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
14825#define USART_CR2_LBDL USART_CR2_LBDL_Msk
14826#define USART_CR2_LBDIE_Pos (6U)
14827#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
14828#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
14829#define USART_CR2_LBCL_Pos (8U)
14830#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
14831#define USART_CR2_LBCL USART_CR2_LBCL_Msk
14832#define USART_CR2_CPHA_Pos (9U)
14833#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
14834#define USART_CR2_CPHA USART_CR2_CPHA_Msk
14835#define USART_CR2_CPOL_Pos (10U)
14836#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
14837#define USART_CR2_CPOL USART_CR2_CPOL_Msk
14838#define USART_CR2_CLKEN_Pos (11U)
14839#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
14840#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
14841#define USART_CR2_STOP_Pos (12U)
14842#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
14843#define USART_CR2_STOP USART_CR2_STOP_Msk
14844#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
14845#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
14846#define USART_CR2_LINEN_Pos (14U)
14847#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
14848#define USART_CR2_LINEN USART_CR2_LINEN_Msk
14849#define USART_CR2_SWAP_Pos (15U)
14850#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
14851#define USART_CR2_SWAP USART_CR2_SWAP_Msk
14852#define USART_CR2_RXINV_Pos (16U)
14853#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
14854#define USART_CR2_RXINV USART_CR2_RXINV_Msk
14855#define USART_CR2_TXINV_Pos (17U)
14856#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
14857#define USART_CR2_TXINV USART_CR2_TXINV_Msk
14858#define USART_CR2_DATAINV_Pos (18U)
14859#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
14860#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
14861#define USART_CR2_MSBFIRST_Pos (19U)
14862#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
14863#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
14864#define USART_CR2_ABREN_Pos (20U)
14865#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
14866#define USART_CR2_ABREN USART_CR2_ABREN_Msk
14867#define USART_CR2_ABRMODE_Pos (21U)
14868#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
14869#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
14870#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
14871#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
14872#define USART_CR2_RTOEN_Pos (23U)
14873#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
14874#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
14875#define USART_CR2_ADD_Pos (24U)
14876#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
14877#define USART_CR2_ADD USART_CR2_ADD_Msk
14879/****************** Bit definition for USART_CR3 register *******************/
14880#define USART_CR3_EIE_Pos (0U)
14881#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
14882#define USART_CR3_EIE USART_CR3_EIE_Msk
14883#define USART_CR3_IREN_Pos (1U)
14884#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
14885#define USART_CR3_IREN USART_CR3_IREN_Msk
14886#define USART_CR3_IRLP_Pos (2U)
14887#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
14888#define USART_CR3_IRLP USART_CR3_IRLP_Msk
14889#define USART_CR3_HDSEL_Pos (3U)
14890#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
14891#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
14892#define USART_CR3_NACK_Pos (4U)
14893#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
14894#define USART_CR3_NACK USART_CR3_NACK_Msk
14895#define USART_CR3_SCEN_Pos (5U)
14896#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
14897#define USART_CR3_SCEN USART_CR3_SCEN_Msk
14898#define USART_CR3_DMAR_Pos (6U)
14899#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
14900#define USART_CR3_DMAR USART_CR3_DMAR_Msk
14901#define USART_CR3_DMAT_Pos (7U)
14902#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
14903#define USART_CR3_DMAT USART_CR3_DMAT_Msk
14904#define USART_CR3_RTSE_Pos (8U)
14905#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
14906#define USART_CR3_RTSE USART_CR3_RTSE_Msk
14907#define USART_CR3_CTSE_Pos (9U)
14908#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
14909#define USART_CR3_CTSE USART_CR3_CTSE_Msk
14910#define USART_CR3_CTSIE_Pos (10U)
14911#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
14912#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
14913#define USART_CR3_ONEBIT_Pos (11U)
14914#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
14915#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
14916#define USART_CR3_OVRDIS_Pos (12U)
14917#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
14918#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
14919#define USART_CR3_DDRE_Pos (13U)
14920#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
14921#define USART_CR3_DDRE USART_CR3_DDRE_Msk
14922#define USART_CR3_DEM_Pos (14U)
14923#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
14924#define USART_CR3_DEM USART_CR3_DEM_Msk
14925#define USART_CR3_DEP_Pos (15U)
14926#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
14927#define USART_CR3_DEP USART_CR3_DEP_Msk
14928#define USART_CR3_SCARCNT_Pos (17U)
14929#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
14930#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
14931#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
14932#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
14933#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
14935/****************** Bit definition for USART_BRR register *******************/
14936#define USART_BRR_DIV_FRACTION_Pos (0U)
14937#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
14938#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
14939#define USART_BRR_DIV_MANTISSA_Pos (4U)
14940#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
14941#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
14943/****************** Bit definition for USART_GTPR register ******************/
14944#define USART_GTPR_PSC_Pos (0U)
14945#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
14946#define USART_GTPR_PSC USART_GTPR_PSC_Msk
14947#define USART_GTPR_GT_Pos (8U)
14948#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
14949#define USART_GTPR_GT USART_GTPR_GT_Msk
14952/******************* Bit definition for USART_RTOR register *****************/
14953#define USART_RTOR_RTO_Pos (0U)
14954#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
14955#define USART_RTOR_RTO USART_RTOR_RTO_Msk
14956#define USART_RTOR_BLEN_Pos (24U)
14957#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
14958#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
14960/******************* Bit definition for USART_RQR register ******************/
14961#define USART_RQR_ABRRQ_Pos (0U)
14962#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
14963#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
14964#define USART_RQR_SBKRQ_Pos (1U)
14965#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
14966#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
14967#define USART_RQR_MMRQ_Pos (2U)
14968#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
14969#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
14970#define USART_RQR_RXFRQ_Pos (3U)
14971#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
14972#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
14973#define USART_RQR_TXFRQ_Pos (4U)
14974#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
14975#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
14977/******************* Bit definition for USART_ISR register ******************/
14978#define USART_ISR_PE_Pos (0U)
14979#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
14980#define USART_ISR_PE USART_ISR_PE_Msk
14981#define USART_ISR_FE_Pos (1U)
14982#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
14983#define USART_ISR_FE USART_ISR_FE_Msk
14984#define USART_ISR_NE_Pos (2U)
14985#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
14986#define USART_ISR_NE USART_ISR_NE_Msk
14987#define USART_ISR_ORE_Pos (3U)
14988#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
14989#define USART_ISR_ORE USART_ISR_ORE_Msk
14990#define USART_ISR_IDLE_Pos (4U)
14991#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
14992#define USART_ISR_IDLE USART_ISR_IDLE_Msk
14993#define USART_ISR_RXNE_Pos (5U)
14994#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
14995#define USART_ISR_RXNE USART_ISR_RXNE_Msk
14996#define USART_ISR_TC_Pos (6U)
14997#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
14998#define USART_ISR_TC USART_ISR_TC_Msk
14999#define USART_ISR_TXE_Pos (7U)
15000#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
15001#define USART_ISR_TXE USART_ISR_TXE_Msk
15002#define USART_ISR_LBDF_Pos (8U)
15003#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
15004#define USART_ISR_LBDF USART_ISR_LBDF_Msk
15005#define USART_ISR_CTSIF_Pos (9U)
15006#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
15007#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
15008#define USART_ISR_CTS_Pos (10U)
15009#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
15010#define USART_ISR_CTS USART_ISR_CTS_Msk
15011#define USART_ISR_RTOF_Pos (11U)
15012#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
15013#define USART_ISR_RTOF USART_ISR_RTOF_Msk
15014#define USART_ISR_EOBF_Pos (12U)
15015#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
15016#define USART_ISR_EOBF USART_ISR_EOBF_Msk
15017#define USART_ISR_ABRE_Pos (14U)
15018#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
15019#define USART_ISR_ABRE USART_ISR_ABRE_Msk
15020#define USART_ISR_ABRF_Pos (15U)
15021#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
15022#define USART_ISR_ABRF USART_ISR_ABRF_Msk
15023#define USART_ISR_BUSY_Pos (16U)
15024#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
15025#define USART_ISR_BUSY USART_ISR_BUSY_Msk
15026#define USART_ISR_CMF_Pos (17U)
15027#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
15028#define USART_ISR_CMF USART_ISR_CMF_Msk
15029#define USART_ISR_SBKF_Pos (18U)
15030#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
15031#define USART_ISR_SBKF USART_ISR_SBKF_Msk
15032#define USART_ISR_RWU_Pos (19U)
15033#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
15034#define USART_ISR_RWU USART_ISR_RWU_Msk
15035#define USART_ISR_TEACK_Pos (21U)
15036#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
15037#define USART_ISR_TEACK USART_ISR_TEACK_Msk
15038/* Legacy define */
15039#define USART_ISR_LBD USART_ISR_LBDF
15040
15041/******************* Bit definition for USART_ICR register ******************/
15042#define USART_ICR_PECF_Pos (0U)
15043#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
15044#define USART_ICR_PECF USART_ICR_PECF_Msk
15045#define USART_ICR_FECF_Pos (1U)
15046#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
15047#define USART_ICR_FECF USART_ICR_FECF_Msk
15048#define USART_ICR_NCF_Pos (2U)
15049#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)
15050#define USART_ICR_NCF USART_ICR_NCF_Msk
15051#define USART_ICR_ORECF_Pos (3U)
15052#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
15053#define USART_ICR_ORECF USART_ICR_ORECF_Msk
15054#define USART_ICR_IDLECF_Pos (4U)
15055#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
15056#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
15057#define USART_ICR_TCCF_Pos (6U)
15058#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
15059#define USART_ICR_TCCF USART_ICR_TCCF_Msk
15060#define USART_ICR_LBDCF_Pos (8U)
15061#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
15062#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
15063#define USART_ICR_CTSCF_Pos (9U)
15064#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
15065#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
15066#define USART_ICR_RTOCF_Pos (11U)
15067#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
15068#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
15069#define USART_ICR_EOBCF_Pos (12U)
15070#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
15071#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
15072#define USART_ICR_CMCF_Pos (17U)
15073#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
15074#define USART_ICR_CMCF USART_ICR_CMCF_Msk
15076/******************* Bit definition for USART_RDR register ******************/
15077#define USART_RDR_RDR_Pos (0U)
15078#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
15079#define USART_RDR_RDR USART_RDR_RDR_Msk
15081/******************* Bit definition for USART_TDR register ******************/
15082#define USART_TDR_TDR_Pos (0U)
15083#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
15084#define USART_TDR_TDR USART_TDR_TDR_Msk
15086/******************************************************************************/
15087/* */
15088/* Window WATCHDOG */
15089/* */
15090/******************************************************************************/
15091/******************* Bit definition for WWDG_CR register ********************/
15092#define WWDG_CR_T_Pos (0U)
15093#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
15094#define WWDG_CR_T WWDG_CR_T_Msk
15095#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
15096#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
15097#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
15098#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
15099#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
15100#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
15101#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
15103/* Legacy defines */
15104#define WWDG_CR_T0 WWDG_CR_T_0
15105#define WWDG_CR_T1 WWDG_CR_T_1
15106#define WWDG_CR_T2 WWDG_CR_T_2
15107#define WWDG_CR_T3 WWDG_CR_T_3
15108#define WWDG_CR_T4 WWDG_CR_T_4
15109#define WWDG_CR_T5 WWDG_CR_T_5
15110#define WWDG_CR_T6 WWDG_CR_T_6
15112#define WWDG_CR_WDGA_Pos (7U)
15113#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
15114#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
15116/******************* Bit definition for WWDG_CFR register *******************/
15117#define WWDG_CFR_W_Pos (0U)
15118#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
15119#define WWDG_CFR_W WWDG_CFR_W_Msk
15120#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
15121#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
15122#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
15123#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
15124#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
15125#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
15126#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
15128/* Legacy defines */
15129#define WWDG_CFR_W0 WWDG_CFR_W_0
15130#define WWDG_CFR_W1 WWDG_CFR_W_1
15131#define WWDG_CFR_W2 WWDG_CFR_W_2
15132#define WWDG_CFR_W3 WWDG_CFR_W_3
15133#define WWDG_CFR_W4 WWDG_CFR_W_4
15134#define WWDG_CFR_W5 WWDG_CFR_W_5
15135#define WWDG_CFR_W6 WWDG_CFR_W_6
15137#define WWDG_CFR_WDGTB_Pos (7U)
15138#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
15139#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
15140#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
15141#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
15143/* Legacy defines */
15144#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
15145#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
15147#define WWDG_CFR_EWI_Pos (9U)
15148#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
15149#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
15151/******************* Bit definition for WWDG_SR register ********************/
15152#define WWDG_SR_EWIF_Pos (0U)
15153#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
15154#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
15156/******************************************************************************/
15157/* */
15158/* DBG */
15159/* */
15160/******************************************************************************/
15161/******************** Bit definition for DBGMCU_IDCODE register *************/
15162#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
15163#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
15164#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
15165#define DBGMCU_IDCODE_REV_ID_Pos (16U)
15166#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
15167#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
15168
15169/******************** Bit definition for DBGMCU_CR register *****************/
15170#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
15171#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
15172#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
15173#define DBGMCU_CR_DBG_STOP_Pos (1U)
15174#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
15175#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
15176#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
15177#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
15178#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
15179#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
15180#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
15181#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
15182
15183#define DBGMCU_CR_TRACE_MODE_Pos (6U)
15184#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
15185#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
15186#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
15187#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
15189/******************** Bit definition for DBGMCU_APB1_FZ register ************/
15190#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
15191#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
15192#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
15193#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
15194#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
15195#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
15196#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
15197#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
15198#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
15199#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
15200#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
15201#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
15202#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
15203#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
15204#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
15205#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
15206#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
15207#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
15208#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
15209#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
15210#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
15211#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
15212#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
15213#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
15214#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
15215#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
15216#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
15217#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
15218#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos)
15219#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
15220#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
15221#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
15222#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
15223#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
15224#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
15225#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
15226#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
15227#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
15228#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
15229#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
15230#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
15231#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
15232#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
15233#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
15234#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
15235#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
15236#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
15237#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
15238#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
15239#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
15240#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
15241#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
15242#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
15243#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
15244
15245/******************** Bit definition for DBGMCU_APB2_FZ register ************/
15246#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
15247#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
15248#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
15249#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
15250#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
15251#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
15252#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
15253#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
15254#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
15255#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
15256#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
15257#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
15258#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
15259#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
15260#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
15261
15262/******************************************************************************/
15263/* */
15264/* Ethernet MAC Registers bits definitions */
15265/* */
15266/******************************************************************************/
15267/* Bit definition for Ethernet MAC Control Register register */
15268#define ETH_MACCR_WD_Pos (23U)
15269#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
15270#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
15271#define ETH_MACCR_JD_Pos (22U)
15272#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
15273#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
15274#define ETH_MACCR_IFG_Pos (17U)
15275#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
15276#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
15277#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
15278#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
15279#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
15280#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
15281#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
15282#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
15283#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
15284#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
15285#define ETH_MACCR_CSD_Pos (16U)
15286#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
15287#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
15288#define ETH_MACCR_FES_Pos (14U)
15289#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
15290#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
15291#define ETH_MACCR_ROD_Pos (13U)
15292#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
15293#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
15294#define ETH_MACCR_LM_Pos (12U)
15295#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
15296#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
15297#define ETH_MACCR_DM_Pos (11U)
15298#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
15299#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
15300#define ETH_MACCR_IPCO_Pos (10U)
15301#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
15302#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
15303#define ETH_MACCR_RD_Pos (9U)
15304#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
15305#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
15306#define ETH_MACCR_APCS_Pos (7U)
15307#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
15308#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
15309#define ETH_MACCR_BL_Pos (5U)
15310#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
15311#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
15312 a transmission attempt during retries after a collision: 0 =< r <2^k */
15313#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
15314#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
15315#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
15316#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
15317#define ETH_MACCR_DC_Pos (4U)
15318#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
15319#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
15320#define ETH_MACCR_TE_Pos (3U)
15321#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
15322#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
15323#define ETH_MACCR_RE_Pos (2U)
15324#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
15325#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
15326
15327/* Bit definition for Ethernet MAC Frame Filter Register */
15328#define ETH_MACFFR_RA_Pos (31U)
15329#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
15330#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
15331#define ETH_MACFFR_HPF_Pos (10U)
15332#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
15333#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
15334#define ETH_MACFFR_SAF_Pos (9U)
15335#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
15336#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
15337#define ETH_MACFFR_SAIF_Pos (8U)
15338#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
15339#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
15340#define ETH_MACFFR_PCF_Pos (6U)
15341#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
15342#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
15343#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
15344#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
15345#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
15346#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
15347#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
15348#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
15349#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
15350#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
15351#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
15352#define ETH_MACFFR_BFD_Pos (5U)
15353#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
15354#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
15355#define ETH_MACFFR_PAM_Pos (4U)
15356#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
15357#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
15358#define ETH_MACFFR_DAIF_Pos (3U)
15359#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
15360#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
15361#define ETH_MACFFR_HM_Pos (2U)
15362#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
15363#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
15364#define ETH_MACFFR_HU_Pos (1U)
15365#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
15366#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
15367#define ETH_MACFFR_PM_Pos (0U)
15368#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
15369#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
15370
15371/* Bit definition for Ethernet MAC Hash Table High Register */
15372#define ETH_MACHTHR_HTH_Pos (0U)
15373#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
15374#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
15375
15376/* Bit definition for Ethernet MAC Hash Table Low Register */
15377#define ETH_MACHTLR_HTL_Pos (0U)
15378#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
15379#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
15380
15381/* Bit definition for Ethernet MAC MII Address Register */
15382#define ETH_MACMIIAR_PA_Pos (11U)
15383#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
15384#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
15385#define ETH_MACMIIAR_MR_Pos (6U)
15386#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
15387#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
15388#define ETH_MACMIIAR_CR_Pos (2U)
15389#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
15390#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
15391#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
15392#define ETH_MACMIIAR_CR_Div62_Pos (2U)
15393#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
15394#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
15395#define ETH_MACMIIAR_CR_Div16_Pos (3U)
15396#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
15397#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
15398#define ETH_MACMIIAR_CR_Div26_Pos (2U)
15399#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
15400#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
15401#define ETH_MACMIIAR_CR_Div102_Pos (4U)
15402#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
15403#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
15404#define ETH_MACMIIAR_MW_Pos (1U)
15405#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
15406#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
15407#define ETH_MACMIIAR_MB_Pos (0U)
15408#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
15409#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
15410
15411/* Bit definition for Ethernet MAC MII Data Register */
15412#define ETH_MACMIIDR_MD_Pos (0U)
15413#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
15414#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
15415
15416/* Bit definition for Ethernet MAC Flow Control Register */
15417#define ETH_MACFCR_PT_Pos (16U)
15418#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
15419#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
15420#define ETH_MACFCR_ZQPD_Pos (7U)
15421#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
15422#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
15423#define ETH_MACFCR_PLT_Pos (4U)
15424#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
15425#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
15426#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
15427#define ETH_MACFCR_PLT_Minus28_Pos (4U)
15428#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
15429#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
15430#define ETH_MACFCR_PLT_Minus144_Pos (5U)
15431#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
15432#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
15433#define ETH_MACFCR_PLT_Minus256_Pos (4U)
15434#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
15435#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
15436#define ETH_MACFCR_UPFD_Pos (3U)
15437#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
15438#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
15439#define ETH_MACFCR_RFCE_Pos (2U)
15440#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
15441#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
15442#define ETH_MACFCR_TFCE_Pos (1U)
15443#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
15444#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
15445#define ETH_MACFCR_FCBBPA_Pos (0U)
15446#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
15447#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
15448
15449/* Bit definition for Ethernet MAC VLAN Tag Register */
15450#define ETH_MACVLANTR_VLANTC_Pos (16U)
15451#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
15452#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
15453#define ETH_MACVLANTR_VLANTI_Pos (0U)
15454#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
15455#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
15456
15457/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
15458#define ETH_MACRWUFFR_D_Pos (0U)
15459#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
15460#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
15461/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
15462 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
15463/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
15464 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
15465 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
15466 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
15467 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
15468 RSVD - Filter1 Command - RSVD - Filter0 Command
15469 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
15470 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
15471 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
15472
15473/* Bit definition for Ethernet MAC PMT Control and Status Register */
15474#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
15475#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
15476#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
15477#define ETH_MACPMTCSR_GU_Pos (9U)
15478#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
15479#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
15480#define ETH_MACPMTCSR_WFR_Pos (6U)
15481#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
15482#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
15483#define ETH_MACPMTCSR_MPR_Pos (5U)
15484#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
15485#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
15486#define ETH_MACPMTCSR_WFE_Pos (2U)
15487#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
15488#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
15489#define ETH_MACPMTCSR_MPE_Pos (1U)
15490#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
15491#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
15492#define ETH_MACPMTCSR_PD_Pos (0U)
15493#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
15494#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
15495
15496/* Bit definition for Ethernet MAC debug Register */
15497#define ETH_MACDBGR_TFF_Pos (25U)
15498#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
15499#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
15500#define ETH_MACDBGR_TFNE_Pos (24U)
15501#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
15502#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
15503#define ETH_MACDBGR_TPWA_Pos (22U)
15504#define ETH_MACDBGR_TPWA_Msk (0x1UL << ETH_MACDBGR_TPWA_Pos)
15505#define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */
15506#define ETH_MACDBGR_TFRS_Pos (20U)
15507#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
15508#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
15509#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
15510#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
15511#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
15512#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
15513#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
15514#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
15515#define ETH_MACDBGR_TFRS_READ_Pos (20U)
15516#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
15517#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
15518#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
15519#define ETH_MACDBGR_MTP_Pos (19U)
15520#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
15521#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
15522#define ETH_MACDBGR_MTFCS_Pos (17U)
15523#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
15524#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
15525#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
15526#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
15527#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
15528#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
15529#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
15530#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
15531#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
15532#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
15533#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
15534#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
15535#define ETH_MACDBGR_MMTEA_Pos (16U)
15536#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
15537#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
15538#define ETH_MACDBGR_RFFL_Pos (8U)
15539#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
15540#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
15541#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
15542#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
15543#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
15544#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
15545#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
15546#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
15547#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
15548#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
15549#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
15550#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
15551#define ETH_MACDBGR_RFRCS_Pos (5U)
15552#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
15553#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
15554#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
15555#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
15556#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
15557#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
15558#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
15559#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
15560#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
15561#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
15562#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
15563#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
15564#define ETH_MACDBGR_RFWRA_Pos (4U)
15565#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
15566#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
15567#define ETH_MACDBGR_MSFRWCS_Pos (1U)
15568#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
15569#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
15570#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
15571#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
15572#define ETH_MACDBGR_MMRPEA_Pos (0U)
15573#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
15574#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
15575
15576/* Bit definition for Ethernet MAC Status Register */
15577#define ETH_MACSR_TSTS_Pos (9U)
15578#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
15579#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
15580#define ETH_MACSR_MMCTS_Pos (6U)
15581#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
15582#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
15583#define ETH_MACSR_MMMCRS_Pos (5U)
15584#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
15585#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
15586#define ETH_MACSR_MMCS_Pos (4U)
15587#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
15588#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
15589#define ETH_MACSR_PMTS_Pos (3U)
15590#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
15591#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
15592
15593/* Bit definition for Ethernet MAC Interrupt Mask Register */
15594#define ETH_MACIMR_TSTIM_Pos (9U)
15595#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
15596#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
15597#define ETH_MACIMR_PMTIM_Pos (3U)
15598#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
15599#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
15600
15601/* Bit definition for Ethernet MAC Address0 High Register */
15602#define ETH_MACA0HR_MACA0H_Pos (0U)
15603#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
15604#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
15605
15606/* Bit definition for Ethernet MAC Address0 Low Register */
15607#define ETH_MACA0LR_MACA0L_Pos (0U)
15608#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
15609#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
15610
15611/* Bit definition for Ethernet MAC Address1 High Register */
15612#define ETH_MACA1HR_AE_Pos (31U)
15613#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
15614#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
15615#define ETH_MACA1HR_SA_Pos (30U)
15616#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
15617#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
15618#define ETH_MACA1HR_MBC_Pos (24U)
15619#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
15620#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
15621#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
15622#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
15623#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
15624#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
15625#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
15626#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
15627#define ETH_MACA1HR_MACA1H_Pos (0U)
15628#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
15629#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
15630
15631/* Bit definition for Ethernet MAC Address1 Low Register */
15632#define ETH_MACA1LR_MACA1L_Pos (0U)
15633#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
15634#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
15635
15636/* Bit definition for Ethernet MAC Address2 High Register */
15637#define ETH_MACA2HR_AE_Pos (31U)
15638#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
15639#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
15640#define ETH_MACA2HR_SA_Pos (30U)
15641#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
15642#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
15643#define ETH_MACA2HR_MBC_Pos (24U)
15644#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
15645#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
15646#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
15647#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
15648#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
15649#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
15650#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
15651#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
15652#define ETH_MACA2HR_MACA2H_Pos (0U)
15653#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
15654#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
15655
15656/* Bit definition for Ethernet MAC Address2 Low Register */
15657#define ETH_MACA2LR_MACA2L_Pos (0U)
15658#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
15659#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
15660
15661/* Bit definition for Ethernet MAC Address3 High Register */
15662#define ETH_MACA3HR_AE_Pos (31U)
15663#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
15664#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
15665#define ETH_MACA3HR_SA_Pos (30U)
15666#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
15667#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
15668#define ETH_MACA3HR_MBC_Pos (24U)
15669#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
15670#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
15671#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
15672#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
15673#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
15674#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
15675#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
15676#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
15677#define ETH_MACA3HR_MACA3H_Pos (0U)
15678#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
15679#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
15680
15681/* Bit definition for Ethernet MAC Address3 Low Register */
15682#define ETH_MACA3LR_MACA3L_Pos (0U)
15683#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
15684#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
15685
15686/******************************************************************************/
15687/* Ethernet MMC Registers bits definition */
15688/******************************************************************************/
15689
15690/* Bit definition for Ethernet MMC Contol Register */
15691#define ETH_MMCCR_MCFHP_Pos (5U)
15692#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
15693#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
15694#define ETH_MMCCR_MCP_Pos (4U)
15695#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
15696#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
15697#define ETH_MMCCR_MCF_Pos (3U)
15698#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
15699#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
15700#define ETH_MMCCR_ROR_Pos (2U)
15701#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
15702#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
15703#define ETH_MMCCR_CSR_Pos (1U)
15704#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
15705#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
15706#define ETH_MMCCR_CR_Pos (0U)
15707#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
15708#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
15709
15710/* Bit definition for Ethernet MMC Receive Interrupt Register */
15711#define ETH_MMCRIR_RGUFS_Pos (17U)
15712#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
15713#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
15714#define ETH_MMCRIR_RFAES_Pos (6U)
15715#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
15716#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
15717#define ETH_MMCRIR_RFCES_Pos (5U)
15718#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
15719#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
15720
15721/* Bit definition for Ethernet MMC Transmit Interrupt Register */
15722#define ETH_MMCTIR_TGFS_Pos (21U)
15723#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
15724#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
15725#define ETH_MMCTIR_TGFMSCS_Pos (15U)
15726#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
15727#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
15728#define ETH_MMCTIR_TGFSCS_Pos (14U)
15729#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
15730#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
15731
15732/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
15733#define ETH_MMCRIMR_RGUFM_Pos (17U)
15734#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
15735#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
15736#define ETH_MMCRIMR_RFAEM_Pos (6U)
15737#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
15738#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
15739#define ETH_MMCRIMR_RFCEM_Pos (5U)
15740#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
15741#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
15742
15743/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
15744#define ETH_MMCTIMR_TGFM_Pos (21U)
15745#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
15746#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
15747#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
15748#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
15749#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
15750#define ETH_MMCTIMR_TGFSCM_Pos (14U)
15751#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
15752#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
15753
15754/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
15755#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
15756#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
15757#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
15758
15759/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
15760#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
15761#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
15762#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
15763
15764/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
15765#define ETH_MMCTGFCR_TGFC_Pos (0U)
15766#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
15767#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
15768
15769/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
15770#define ETH_MMCRFCECR_RFCEC_Pos (0U)
15771#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
15772#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
15773
15774/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
15775#define ETH_MMCRFAECR_RFAEC_Pos (0U)
15776#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
15777#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
15778
15779/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
15780#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
15781#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
15782#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
15783
15784/******************************************************************************/
15785/* Ethernet PTP Registers bits definition */
15786/******************************************************************************/
15787
15788/* Bit definition for Ethernet PTP Time Stamp Contol Register */
15789#define ETH_PTPTSCR_TSCNT_Pos (16U)
15790#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
15791#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
15792#define ETH_PTPTSSR_TSSMRME_Pos (15U)
15793#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos)
15794#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
15795#define ETH_PTPTSSR_TSSEME_Pos (14U)
15796#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos)
15797#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
15798#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
15799#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos)
15800#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15801#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
15802#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos)
15803#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15804#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
15805#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos)
15806#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15807#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
15808#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos)
15809#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15810#define ETH_PTPTSSR_TSSSR_Pos (9U)
15811#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos)
15812#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
15813#define ETH_PTPTSSR_TSSARFE_Pos (8U)
15814#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos)
15815#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
15816
15817#define ETH_PTPTSCR_TSARU_Pos (5U)
15818#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
15819#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
15820#define ETH_PTPTSCR_TSITE_Pos (4U)
15821#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
15822#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
15823#define ETH_PTPTSCR_TSSTU_Pos (3U)
15824#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
15825#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
15826#define ETH_PTPTSCR_TSSTI_Pos (2U)
15827#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
15828#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
15829#define ETH_PTPTSCR_TSFCU_Pos (1U)
15830#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
15831#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
15832#define ETH_PTPTSCR_TSE_Pos (0U)
15833#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
15834#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
15835
15836/* Bit definition for Ethernet PTP Sub-Second Increment Register */
15837#define ETH_PTPSSIR_STSSI_Pos (0U)
15838#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
15839#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
15840
15841/* Bit definition for Ethernet PTP Time Stamp High Register */
15842#define ETH_PTPTSHR_STS_Pos (0U)
15843#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
15844#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
15845
15846/* Bit definition for Ethernet PTP Time Stamp Low Register */
15847#define ETH_PTPTSLR_STPNS_Pos (31U)
15848#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
15849#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
15850#define ETH_PTPTSLR_STSS_Pos (0U)
15851#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
15852#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
15853
15854/* Bit definition for Ethernet PTP Time Stamp High Update Register */
15855#define ETH_PTPTSHUR_TSUS_Pos (0U)
15856#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
15857#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
15858
15859/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
15860#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
15861#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
15862#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
15863#define ETH_PTPTSLUR_TSUSS_Pos (0U)
15864#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
15865#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
15866
15867/* Bit definition for Ethernet PTP Time Stamp Addend Register */
15868#define ETH_PTPTSAR_TSA_Pos (0U)
15869#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
15870#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
15871
15872/* Bit definition for Ethernet PTP Target Time High Register */
15873#define ETH_PTPTTHR_TTSH_Pos (0U)
15874#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
15875#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
15876
15877/* Bit definition for Ethernet PTP Target Time Low Register */
15878#define ETH_PTPTTLR_TTSL_Pos (0U)
15879#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
15880#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
15881
15882/* Bit definition for Ethernet PTP Time Stamp Status Register */
15883#define ETH_PTPTSSR_TSTTR_Pos (5U)
15884#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
15885#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
15886#define ETH_PTPTSSR_TSSO_Pos (4U)
15887#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
15888#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
15889
15890/* Bit definition for Ethernet PTP PPS Control Register */
15891#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
15892#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos)
15893#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
15894
15895/******************************************************************************/
15896/* Ethernet DMA Registers bits definition */
15897/******************************************************************************/
15898
15899/* Bit definition for Ethernet DMA Bus Mode Register */
15900#define ETH_DMABMR_AAB_Pos (25U)
15901#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
15902#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
15903#define ETH_DMABMR_FPM_Pos (24U)
15904#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
15905#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
15906#define ETH_DMABMR_USP_Pos (23U)
15907#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
15908#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
15909#define ETH_DMABMR_RDP_Pos (17U)
15910#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
15911#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
15912#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
15913#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
15914#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15915#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15916#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15917#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15918#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
15919#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
15920#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
15921#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
15922#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
15923#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
15924#define ETH_DMABMR_FB_Pos (16U)
15925#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
15926#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
15927#define ETH_DMABMR_RTPR_Pos (14U)
15928#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
15929#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
15930#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
15931#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
15932#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
15933#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
15934#define ETH_DMABMR_PBL_Pos (8U)
15935#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
15936#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
15937#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
15938#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
15939#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15940#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15941#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15942#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15943#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
15944#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
15945#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
15946#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
15947#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
15948#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
15949#define ETH_DMABMR_EDE_Pos (7U)
15950#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
15951#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
15952#define ETH_DMABMR_DSL_Pos (2U)
15953#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
15954#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
15955#define ETH_DMABMR_DA_Pos (1U)
15956#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
15957#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
15958#define ETH_DMABMR_SR_Pos (0U)
15959#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
15960#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
15961
15962/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
15963#define ETH_DMATPDR_TPD_Pos (0U)
15964#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
15965#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
15966
15967/* Bit definition for Ethernet DMA Receive Poll Demand Register */
15968#define ETH_DMARPDR_RPD_Pos (0U)
15969#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
15970#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
15971
15972/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
15973#define ETH_DMARDLAR_SRL_Pos (0U)
15974#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
15975#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
15976
15977/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
15978#define ETH_DMATDLAR_STL_Pos (0U)
15979#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
15980#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
15981
15982/* Bit definition for Ethernet DMA Status Register */
15983#define ETH_DMASR_TSTS_Pos (29U)
15984#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
15985#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
15986#define ETH_DMASR_PMTS_Pos (28U)
15987#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
15988#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
15989#define ETH_DMASR_MMCS_Pos (27U)
15990#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
15991#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
15992#define ETH_DMASR_EBS_Pos (23U)
15993#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
15994#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
15995 /* combination with EBS[2:0] for GetFlagStatus function */
15996#define ETH_DMASR_EBS_DescAccess_Pos (25U)
15997#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
15998#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
15999#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
16000#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
16001#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
16002#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
16003#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
16004#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
16005#define ETH_DMASR_TPS_Pos (20U)
16006#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
16007#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
16008#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
16009#define ETH_DMASR_TPS_Fetching_Pos (20U)
16010#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
16011#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
16012#define ETH_DMASR_TPS_Waiting_Pos (21U)
16013#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
16014#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
16015#define ETH_DMASR_TPS_Reading_Pos (20U)
16016#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
16017#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
16018#define ETH_DMASR_TPS_Suspended_Pos (21U)
16019#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
16020#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
16021#define ETH_DMASR_TPS_Closing_Pos (20U)
16022#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
16023#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
16024#define ETH_DMASR_RPS_Pos (17U)
16025#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
16026#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
16027#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
16028#define ETH_DMASR_RPS_Fetching_Pos (17U)
16029#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
16030#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
16031#define ETH_DMASR_RPS_Waiting_Pos (17U)
16032#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
16033#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
16034#define ETH_DMASR_RPS_Suspended_Pos (19U)
16035#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
16036#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
16037#define ETH_DMASR_RPS_Closing_Pos (17U)
16038#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
16039#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
16040#define ETH_DMASR_RPS_Queuing_Pos (17U)
16041#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
16042#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
16043#define ETH_DMASR_NIS_Pos (16U)
16044#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
16045#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
16046#define ETH_DMASR_AIS_Pos (15U)
16047#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
16048#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
16049#define ETH_DMASR_ERS_Pos (14U)
16050#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
16051#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
16052#define ETH_DMASR_FBES_Pos (13U)
16053#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
16054#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
16055#define ETH_DMASR_ETS_Pos (10U)
16056#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
16057#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
16058#define ETH_DMASR_RWTS_Pos (9U)
16059#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
16060#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
16061#define ETH_DMASR_RPSS_Pos (8U)
16062#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
16063#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
16064#define ETH_DMASR_RBUS_Pos (7U)
16065#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
16066#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
16067#define ETH_DMASR_RS_Pos (6U)
16068#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
16069#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
16070#define ETH_DMASR_TUS_Pos (5U)
16071#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
16072#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
16073#define ETH_DMASR_ROS_Pos (4U)
16074#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
16075#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
16076#define ETH_DMASR_TJTS_Pos (3U)
16077#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
16078#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
16079#define ETH_DMASR_TBUS_Pos (2U)
16080#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
16081#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
16082#define ETH_DMASR_TPSS_Pos (1U)
16083#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
16084#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
16085#define ETH_DMASR_TS_Pos (0U)
16086#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
16087#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
16088
16089/* Bit definition for Ethernet DMA Operation Mode Register */
16090#define ETH_DMAOMR_DTCEFD_Pos (26U)
16091#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
16092#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
16093#define ETH_DMAOMR_RSF_Pos (25U)
16094#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
16095#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
16096#define ETH_DMAOMR_DFRF_Pos (24U)
16097#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
16098#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
16099#define ETH_DMAOMR_TSF_Pos (21U)
16100#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
16101#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
16102#define ETH_DMAOMR_FTF_Pos (20U)
16103#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
16104#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
16105#define ETH_DMAOMR_TTC_Pos (14U)
16106#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
16107#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
16108#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
16109#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
16110#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
16111#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
16112#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
16113#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
16114#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
16115#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
16116#define ETH_DMAOMR_ST_Pos (13U)
16117#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
16118#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
16119#define ETH_DMAOMR_FEF_Pos (7U)
16120#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
16121#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
16122#define ETH_DMAOMR_FUGF_Pos (6U)
16123#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
16124#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
16125#define ETH_DMAOMR_RTC_Pos (3U)
16126#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
16127#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
16128#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
16129#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
16130#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
16131#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
16132#define ETH_DMAOMR_OSF_Pos (2U)
16133#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
16134#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
16135#define ETH_DMAOMR_SR_Pos (1U)
16136#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
16137#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
16138
16139/* Bit definition for Ethernet DMA Interrupt Enable Register */
16140#define ETH_DMAIER_NISE_Pos (16U)
16141#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
16142#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
16143#define ETH_DMAIER_AISE_Pos (15U)
16144#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
16145#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
16146#define ETH_DMAIER_ERIE_Pos (14U)
16147#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
16148#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
16149#define ETH_DMAIER_FBEIE_Pos (13U)
16150#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
16151#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
16152#define ETH_DMAIER_ETIE_Pos (10U)
16153#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
16154#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
16155#define ETH_DMAIER_RWTIE_Pos (9U)
16156#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
16157#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
16158#define ETH_DMAIER_RPSIE_Pos (8U)
16159#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
16160#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
16161#define ETH_DMAIER_RBUIE_Pos (7U)
16162#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
16163#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
16164#define ETH_DMAIER_RIE_Pos (6U)
16165#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
16166#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
16167#define ETH_DMAIER_TUIE_Pos (5U)
16168#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
16169#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
16170#define ETH_DMAIER_ROIE_Pos (4U)
16171#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
16172#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
16173#define ETH_DMAIER_TJTIE_Pos (3U)
16174#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
16175#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
16176#define ETH_DMAIER_TBUIE_Pos (2U)
16177#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
16178#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
16179#define ETH_DMAIER_TPSIE_Pos (1U)
16180#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
16181#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
16182#define ETH_DMAIER_TIE_Pos (0U)
16183#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
16184#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
16185
16186/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
16187#define ETH_DMAMFBOCR_OFOC_Pos (28U)
16188#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
16189#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
16190#define ETH_DMAMFBOCR_MFA_Pos (17U)
16191#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
16192#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
16193#define ETH_DMAMFBOCR_OMFC_Pos (16U)
16194#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
16195#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
16196#define ETH_DMAMFBOCR_MFC_Pos (0U)
16197#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
16198#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
16199
16200/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
16201#define ETH_DMACHTDR_HTDAP_Pos (0U)
16202#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
16203#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
16204
16205/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
16206#define ETH_DMACHRDR_HRDAP_Pos (0U)
16207#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
16208#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
16209
16210/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
16211#define ETH_DMACHTBAR_HTBAP_Pos (0U)
16212#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
16213#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
16214
16215/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
16216#define ETH_DMACHRBAR_HRBAP_Pos (0U)
16217#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
16218#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
16219
16220/******************************************************************************/
16221/* */
16222/* USB_OTG */
16223/* */
16224/******************************************************************************/
16225/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
16226#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
16227#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
16228#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
16229#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
16230#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
16231#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
16232#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
16233#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
16234#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
16235#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
16236#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
16237#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
16238#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
16239#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
16240#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
16241#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
16242#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
16243#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
16244#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
16245#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
16246#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
16247#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
16248#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
16249#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
16250#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
16251#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
16252#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
16253#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
16254#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
16255#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
16256#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
16257#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
16258#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
16259#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
16260#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
16261#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
16262#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
16263#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
16264#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
16265#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
16266#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
16267#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
16268#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
16269#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
16270#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
16271#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
16272#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
16273#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
16274#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
16275#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
16276#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
16277#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
16278#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
16279#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
16281/******************** Bit definition for USB_OTG_HCFG register ********************/
16282#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
16283#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
16284#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
16285#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
16286#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
16287#define USB_OTG_HCFG_FSLSS_Pos (2U)
16288#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
16289#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
16291/******************** Bit definition for USB_OTG_DCFG register ********************/
16292#define USB_OTG_DCFG_DSPD_Pos (0U)
16293#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
16294#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
16295#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
16296#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
16297#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
16298#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
16299#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
16301#define USB_OTG_DCFG_DAD_Pos (4U)
16302#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
16303#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
16304#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
16305#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
16306#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
16307#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
16308#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
16309#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
16310#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
16312#define USB_OTG_DCFG_PFIVL_Pos (11U)
16313#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
16314#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
16315#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
16316#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
16318#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
16319#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
16320#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
16321#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
16322#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
16324/******************** Bit definition for USB_OTG_PCGCR register ********************/
16325#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
16326#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
16327#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
16328#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
16329#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
16330#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
16331#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
16332#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
16333#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
16335/******************** Bit definition for USB_OTG_GOTGINT register ********************/
16336#define USB_OTG_GOTGINT_SEDET_Pos (2U)
16337#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
16338#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
16339#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
16340#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
16341#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
16342#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
16343#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
16344#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
16345#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
16346#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
16347#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
16348#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
16349#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
16350#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
16351#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
16352#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
16353#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
16354#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
16355#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos)
16356#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk
16358/******************** Bit definition for USB_OTG_DCTL register ********************/
16359#define USB_OTG_DCTL_RWUSIG_Pos (0U)
16360#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
16361#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
16362#define USB_OTG_DCTL_SDIS_Pos (1U)
16363#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
16364#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
16365#define USB_OTG_DCTL_GINSTS_Pos (2U)
16366#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
16367#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
16368#define USB_OTG_DCTL_GONSTS_Pos (3U)
16369#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
16370#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
16372#define USB_OTG_DCTL_TCTL_Pos (4U)
16373#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
16374#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
16375#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
16376#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
16377#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
16378#define USB_OTG_DCTL_SGINAK_Pos (7U)
16379#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
16380#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
16381#define USB_OTG_DCTL_CGINAK_Pos (8U)
16382#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
16383#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
16384#define USB_OTG_DCTL_SGONAK_Pos (9U)
16385#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
16386#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
16387#define USB_OTG_DCTL_CGONAK_Pos (10U)
16388#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
16389#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
16390#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
16391#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
16392#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
16394/******************** Bit definition for USB_OTG_HFIR register ********************/
16395#define USB_OTG_HFIR_FRIVL_Pos (0U)
16396#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
16397#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
16399/******************** Bit definition for USB_OTG_HFNUM register ********************/
16400#define USB_OTG_HFNUM_FRNUM_Pos (0U)
16401#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
16402#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
16403#define USB_OTG_HFNUM_FTREM_Pos (16U)
16404#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
16405#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
16407/******************** Bit definition for USB_OTG_DSTS register ********************/
16408#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
16409#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
16410#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
16412#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
16413#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
16414#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
16415#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
16416#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
16417#define USB_OTG_DSTS_EERR_Pos (3U)
16418#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
16419#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
16420#define USB_OTG_DSTS_FNSOF_Pos (8U)
16421#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
16422#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
16424/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
16425#define USB_OTG_GAHBCFG_GINT_Pos (0U)
16426#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
16427#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
16428#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
16429#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16430#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
16431#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16432#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16433#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16434#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16435#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
16436#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
16437#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
16438#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
16439#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
16440#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
16441#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
16442#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
16443#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
16444#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
16446/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
16447#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
16448#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
16449#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
16450#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
16451#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
16452#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
16453#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
16454#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
16455#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
16456#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
16457#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
16458#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
16459#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
16460#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
16461#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
16462#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
16463#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
16464#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
16465#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
16466#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
16467#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
16468#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
16469#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
16470#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
16471#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
16472#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
16473#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
16474#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
16475#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
16476#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
16477#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
16478#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
16479#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
16480#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
16481#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
16482#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
16483#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
16484#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
16485#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
16486#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
16487#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
16488#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
16489#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
16490#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
16491#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
16492#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
16493#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
16494#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
16495#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
16496#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
16497#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
16498#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
16499#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
16500#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
16501#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
16502#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
16503#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
16504#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
16505#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
16506#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
16507#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
16509/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
16510#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
16511#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
16512#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
16513#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
16514#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
16515#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
16516#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
16517#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
16518#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
16519#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
16520#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
16521#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
16522#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
16523#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
16524#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
16525#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
16526#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16527#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
16528#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16529#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16530#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16531#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16532#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
16533#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
16534#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
16535#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
16536#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
16537#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
16538#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
16540/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
16541#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
16542#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
16543#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
16544#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
16545#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
16546#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
16547#define USB_OTG_DIEPMSK_TOM_Pos (3U)
16548#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
16549#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
16550#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
16551#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
16552#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
16553#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
16554#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
16555#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
16556#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
16557#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
16558#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
16559#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
16560#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
16561#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
16562#define USB_OTG_DIEPMSK_BIM_Pos (9U)
16563#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
16564#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
16566/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
16567#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
16568#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
16569#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
16570#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
16571#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
16572#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
16573#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
16574#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
16575#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
16576#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
16577#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
16578#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
16579#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
16580#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
16582#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
16583#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
16584#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
16585#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
16586#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
16587#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
16588#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
16589#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
16590#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
16591#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
16592#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
16594/******************** Bit definition for USB_OTG_HAINT register ********************/
16595#define USB_OTG_HAINT_HAINT_Pos (0U)
16596#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
16597#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
16599/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
16600#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
16601#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
16602#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
16603#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
16604#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
16605#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
16606#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
16607#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
16608#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
16609#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
16610#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
16611#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
16612#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
16613#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
16614#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
16615#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
16616#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
16617#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
16618#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
16619#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
16620#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
16621#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
16622#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
16623#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
16624#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
16625#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
16626#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
16627#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
16628#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
16629#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
16630#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
16631#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
16632#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
16633#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
16634#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
16635#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
16637/******************** Bit definition for USB_OTG_GINTSTS register ********************/
16638#define USB_OTG_GINTSTS_CMOD_Pos (0U)
16639#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
16640#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
16641#define USB_OTG_GINTSTS_MMIS_Pos (1U)
16642#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
16643#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
16644#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
16645#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
16646#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
16647#define USB_OTG_GINTSTS_SOF_Pos (3U)
16648#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
16649#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
16650#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
16651#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
16652#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
16653#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
16654#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
16655#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
16656#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
16657#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
16658#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
16659#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
16660#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
16661#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
16662#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
16663#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
16664#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
16665#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
16666#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
16667#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
16668#define USB_OTG_GINTSTS_USBRST_Pos (12U)
16669#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
16670#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
16671#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
16672#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
16673#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
16674#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
16675#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
16676#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
16677#define USB_OTG_GINTSTS_EOPF_Pos (15U)
16678#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
16679#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
16680#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
16681#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
16682#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
16683#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
16684#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
16685#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
16686#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
16687#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
16688#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
16689#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
16690#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
16691#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
16692#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
16693#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
16694#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
16695#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
16696#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
16697#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
16698#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
16699#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
16700#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
16701#define USB_OTG_GINTSTS_HCINT_Pos (25U)
16702#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
16703#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
16704#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
16705#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
16706#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
16707#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
16708#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
16709#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
16710#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
16711#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
16712#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
16713#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
16714#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
16715#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
16716#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
16717#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
16718#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
16719#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
16720#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
16721#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
16723/******************** Bit definition for USB_OTG_GINTMSK register ********************/
16724#define USB_OTG_GINTMSK_MMISM_Pos (1U)
16725#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
16726#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
16727#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
16728#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
16729#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
16730#define USB_OTG_GINTMSK_SOFM_Pos (3U)
16731#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
16732#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
16733#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
16734#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
16735#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
16736#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
16737#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
16738#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
16739#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
16740#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
16741#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
16742#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
16743#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
16744#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
16745#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
16746#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
16747#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
16748#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
16749#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
16750#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
16751#define USB_OTG_GINTMSK_USBRST_Pos (12U)
16752#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
16753#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
16754#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
16755#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
16756#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
16757#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
16758#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
16759#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
16760#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
16761#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
16762#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
16763#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
16764#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
16765#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
16766#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
16767#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
16768#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
16769#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
16770#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
16771#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
16772#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
16773#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
16774#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
16775#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
16776#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
16777#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
16778#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
16779#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
16780#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
16781#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
16782#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
16783#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
16784#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
16785#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
16786#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
16787#define USB_OTG_GINTMSK_HCIM_Pos (25U)
16788#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
16789#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
16790#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
16791#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
16792#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
16793#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
16794#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
16795#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
16796#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
16797#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
16798#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
16799#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
16800#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
16801#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
16802#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
16803#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
16804#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
16805#define USB_OTG_GINTMSK_WUIM_Pos (31U)
16806#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
16807#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
16809/******************** Bit definition for USB_OTG_DAINT register ********************/
16810#define USB_OTG_DAINT_IEPINT_Pos (0U)
16811#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
16812#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
16813#define USB_OTG_DAINT_OEPINT_Pos (16U)
16814#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
16815#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
16817/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
16818#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
16819#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
16820#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
16822/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
16823#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
16824#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
16825#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
16826#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
16827#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
16828#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
16829#define USB_OTG_GRXSTSP_DPID_Pos (15U)
16830#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
16831#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
16832#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
16833#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
16834#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
16836/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
16837#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
16838#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
16839#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
16840#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
16841#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
16842#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
16844/******************** Bit definition for OTG register ********************/
16845
16846#define USB_OTG_CHNUM_Pos (0U)
16847#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
16848#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
16849#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
16850#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
16851#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
16852#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
16853#define USB_OTG_BCNT_Pos (4U)
16854#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
16855#define USB_OTG_BCNT USB_OTG_BCNT_Msk
16857#define USB_OTG_DPID_Pos (15U)
16858#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
16859#define USB_OTG_DPID USB_OTG_DPID_Msk
16860#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
16861#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
16863#define USB_OTG_PKTSTS_Pos (17U)
16864#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
16865#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
16866#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
16867#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
16868#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
16869#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
16871#define USB_OTG_EPNUM_Pos (0U)
16872#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
16873#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
16874#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
16875#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
16876#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
16877#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
16879#define USB_OTG_FRMNUM_Pos (21U)
16880#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
16881#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
16882#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
16883#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
16884#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
16885#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
16887/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
16888#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
16889#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
16890#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
16892/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
16893#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
16894#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
16895#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
16897/******************** Bit definition for OTG register ********************/
16898#define USB_OTG_NPTXFSA_Pos (0U)
16899#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
16900#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
16901#define USB_OTG_NPTXFD_Pos (16U)
16902#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
16903#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
16904#define USB_OTG_TX0FSA_Pos (0U)
16905#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
16906#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
16907#define USB_OTG_TX0FD_Pos (16U)
16908#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
16909#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
16911/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
16912#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
16913#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
16914#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
16916/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
16917#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
16918#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
16919#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
16921#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
16922#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16923#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
16924#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16925#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16926#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16927#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16928#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16929#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16930#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16931#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
16933#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
16934#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16935#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
16936#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16937#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16938#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16939#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16940#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16941#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16942#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
16944/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
16945#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
16946#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
16947#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
16948#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
16949#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
16950#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
16952#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
16953#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16954#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
16955#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16956#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16957#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16958#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16959#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16960#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16961#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16962#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16963#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
16964#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
16965#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
16966#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
16968#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
16969#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16970#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
16971#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16972#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16973#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16974#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16975#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16976#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16977#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16978#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16979#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
16980#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
16981#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
16982#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
16984/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
16985#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
16986#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
16987#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
16989/******************** Bit definition for USB_OTG_DEACHINT register ********************/
16990#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
16991#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
16992#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
16993#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
16994#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
16995#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
16997/******************** Bit definition for USB_OTG_GCCFG register ********************/
16998#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
16999#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
17000#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
17001#define USB_OTG_GCCFG_VBDEN_Pos (21U)
17002#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
17003#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
17005/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
17006#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
17007#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
17008#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
17009#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
17010#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
17011#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
17013/******************** Bit definition for USB_OTG_CID register ********************/
17014#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
17015#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
17016#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
17018/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
17019#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
17020#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
17021#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
17022#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
17023#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
17024#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
17025#define USB_OTG_GLPMCFG_BESL_Pos (2U)
17026#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
17027#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
17028#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
17029#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
17030#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
17031#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
17032#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
17033#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
17034#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
17035#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
17036#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
17037#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
17038#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
17039#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
17040#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
17041#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
17042#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
17043#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
17044#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
17045#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
17046#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
17047#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
17048#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
17049#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
17050#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
17051#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
17052#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
17053#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
17054#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
17055#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
17056#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
17057#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
17058#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
17059#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
17060#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
17061#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
17062#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
17063#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
17065/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
17066#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
17067#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
17068#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
17069#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
17070#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
17071#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
17072#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
17073#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
17074#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
17075#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
17076#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
17077#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
17078#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
17079#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
17080#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
17081#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
17082#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
17083#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
17084#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
17085#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
17086#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
17087#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
17088#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
17089#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
17090#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
17091#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
17092#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
17094/******************** Bit definition for USB_OTG_HPRT register ********************/
17095#define USB_OTG_HPRT_PCSTS_Pos (0U)
17096#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
17097#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
17098#define USB_OTG_HPRT_PCDET_Pos (1U)
17099#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
17100#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
17101#define USB_OTG_HPRT_PENA_Pos (2U)
17102#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
17103#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
17104#define USB_OTG_HPRT_PENCHNG_Pos (3U)
17105#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
17106#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
17107#define USB_OTG_HPRT_POCA_Pos (4U)
17108#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
17109#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
17110#define USB_OTG_HPRT_POCCHNG_Pos (5U)
17111#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
17112#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
17113#define USB_OTG_HPRT_PRES_Pos (6U)
17114#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
17115#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
17116#define USB_OTG_HPRT_PSUSP_Pos (7U)
17117#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
17118#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
17119#define USB_OTG_HPRT_PRST_Pos (8U)
17120#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
17121#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
17123#define USB_OTG_HPRT_PLSTS_Pos (10U)
17124#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
17125#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
17126#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
17127#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
17128#define USB_OTG_HPRT_PPWR_Pos (12U)
17129#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
17130#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
17132#define USB_OTG_HPRT_PTCTL_Pos (13U)
17133#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
17134#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
17135#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
17136#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
17137#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
17138#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
17140#define USB_OTG_HPRT_PSPD_Pos (17U)
17141#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
17142#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
17143#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
17144#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
17146/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
17147#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
17148#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
17149#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
17150#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
17151#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
17152#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
17153#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
17154#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
17155#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
17156#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
17157#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
17158#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
17159#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
17160#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
17161#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
17162#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
17163#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
17164#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
17165#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
17166#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
17167#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
17168#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
17169#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
17170#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
17171#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
17172#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
17173#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
17174#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
17175#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
17176#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
17177#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
17178#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
17179#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
17181/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
17182#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
17183#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
17184#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
17185#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
17186#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
17187#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
17189/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
17190#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
17191#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
17192#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
17193#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
17194#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
17195#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
17196#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
17197#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
17198#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
17199#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
17200#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
17201#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
17203#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
17204#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
17205#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
17206#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
17207#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
17208#define USB_OTG_DIEPCTL_STALL_Pos (21U)
17209#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
17210#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
17212#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
17213#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17214#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
17215#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17216#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17217#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17218#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17219#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
17220#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
17221#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
17222#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
17223#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
17224#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
17225#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
17226#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
17227#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
17228#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
17229#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
17230#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
17231#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
17232#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
17233#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
17234#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
17235#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
17236#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
17238/******************** Bit definition for USB_OTG_HCCHAR register ********************/
17239#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
17240#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
17241#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
17243#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
17244#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
17245#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
17246#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
17247#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
17248#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
17249#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
17250#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
17251#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
17252#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
17253#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
17254#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
17255#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
17257#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
17258#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
17259#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
17260#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
17261#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
17263#define USB_OTG_HCCHAR_MC_Pos (20U)
17264#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
17265#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
17266#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
17267#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
17269#define USB_OTG_HCCHAR_DAD_Pos (22U)
17270#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
17271#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
17272#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
17273#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
17274#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
17275#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
17276#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
17277#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
17278#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
17279#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
17280#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
17281#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
17282#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
17283#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
17284#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
17285#define USB_OTG_HCCHAR_CHENA_Pos (31U)
17286#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
17287#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
17289/******************** Bit definition for USB_OTG_HCSPLT register ********************/
17290
17291#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
17292#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
17293#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
17294#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17295#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17296#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17297#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17298#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17299#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17300#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
17302#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
17303#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
17304#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
17305#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17306#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17307#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17308#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17309#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17310#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17311#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
17313#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
17314#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
17315#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
17316#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
17317#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
17318#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
17319#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
17320#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
17321#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
17322#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
17323#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
17325/******************** Bit definition for USB_OTG_HCINT register ********************/
17326#define USB_OTG_HCINT_XFRC_Pos (0U)
17327#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
17328#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
17329#define USB_OTG_HCINT_CHH_Pos (1U)
17330#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
17331#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
17332#define USB_OTG_HCINT_AHBERR_Pos (2U)
17333#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
17334#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
17335#define USB_OTG_HCINT_STALL_Pos (3U)
17336#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
17337#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
17338#define USB_OTG_HCINT_NAK_Pos (4U)
17339#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
17340#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
17341#define USB_OTG_HCINT_ACK_Pos (5U)
17342#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
17343#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
17344#define USB_OTG_HCINT_NYET_Pos (6U)
17345#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
17346#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
17347#define USB_OTG_HCINT_TXERR_Pos (7U)
17348#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
17349#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
17350#define USB_OTG_HCINT_BBERR_Pos (8U)
17351#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
17352#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
17353#define USB_OTG_HCINT_FRMOR_Pos (9U)
17354#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
17355#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
17356#define USB_OTG_HCINT_DTERR_Pos (10U)
17357#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
17358#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
17360/******************** Bit definition for USB_OTG_DIEPINT register ********************/
17361#define USB_OTG_DIEPINT_XFRC_Pos (0U)
17362#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
17363#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
17364#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
17365#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
17366#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
17367#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
17368#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
17369#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
17370#define USB_OTG_DIEPINT_TOC_Pos (3U)
17371#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
17372#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
17373#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
17374#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
17375#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
17376#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
17377#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
17378#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
17379#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
17380#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
17381#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
17382#define USB_OTG_DIEPINT_TXFE_Pos (7U)
17383#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
17384#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
17385#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
17386#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
17387#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
17388#define USB_OTG_DIEPINT_BNA_Pos (9U)
17389#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
17390#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
17391#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
17392#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
17393#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
17394#define USB_OTG_DIEPINT_BERR_Pos (12U)
17395#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
17396#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
17397#define USB_OTG_DIEPINT_NAK_Pos (13U)
17398#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
17399#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
17401/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
17402#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
17403#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
17404#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
17405#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
17406#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
17407#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
17408#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
17409#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
17410#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
17411#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
17412#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
17413#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
17414#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
17415#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
17416#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
17417#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
17418#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
17419#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
17420#define USB_OTG_HCINTMSK_NYET_Pos (6U)
17421#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
17422#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
17423#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
17424#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
17425#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
17426#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
17427#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
17428#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
17429#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
17430#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
17431#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
17432#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
17433#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
17434#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
17436/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
17437
17438#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
17439#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
17440#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
17441#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
17442#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
17443#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
17444#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
17445#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
17446#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
17447/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
17448#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
17449#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
17450#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
17451#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
17452#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
17453#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
17454#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
17455#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
17456#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
17457#define USB_OTG_HCTSIZ_DPID_Pos (29U)
17458#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
17459#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
17460#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
17461#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
17463/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
17464#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
17465#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
17466#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
17468/******************** Bit definition for USB_OTG_HCDMA register ********************/
17469#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
17470#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
17471#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
17473/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
17474#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
17475#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
17476#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
17478/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
17479#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
17480#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
17481#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
17482#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
17483#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
17484#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
17486/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
17487#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
17488#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
17489#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
17490#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
17491#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
17492#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
17493#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
17494#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
17495#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
17496#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
17497#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
17498#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
17499#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
17500#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
17501#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
17502#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
17503#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
17504#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
17505#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
17506#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
17507#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
17508#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
17509#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
17510#define USB_OTG_DOEPCTL_STALL_Pos (21U)
17511#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
17512#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
17513#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
17514#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
17515#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
17516#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
17517#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
17518#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
17519#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
17520#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
17521#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
17522#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
17523#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
17524#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
17526/******************** Bit definition for USB_OTG_DOEPINT register ********************/
17527#define USB_OTG_DOEPINT_XFRC_Pos (0U)
17528#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
17529#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
17530#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
17531#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
17532#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
17533#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
17534#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
17535#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
17536#define USB_OTG_DOEPINT_STUP_Pos (3U)
17537#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
17538#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
17539#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
17540#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
17541#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
17542#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
17543#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
17544#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
17545#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
17546#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
17547#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
17548#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
17549#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
17550#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
17551#define USB_OTG_DOEPINT_NAK_Pos (13U)
17552#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
17553#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
17554#define USB_OTG_DOEPINT_NYET_Pos (14U)
17555#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
17556#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
17557#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
17558#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
17559#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
17561/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
17562#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
17563#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
17564#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
17565#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
17566#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
17567#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
17569#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
17570#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
17571#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
17572#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
17573#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
17575/******************** Bit definition for PCGCCTL register ********************/
17576#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
17577#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
17578#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
17579#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
17580#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
17581#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
17582#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
17583#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
17584#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
17601/******************************* ADC Instances ********************************/
17602#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
17603 ((__INSTANCE__) == ADC2) || \
17604 ((__INSTANCE__) == ADC3))
17605#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
17606
17607#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
17608
17609/******************************* CAN Instances ********************************/
17610#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
17611 ((__INSTANCE__) == CAN2))
17612/******************************* CRC Instances ********************************/
17613#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
17614
17615/******************************* DAC Instances ********************************/
17616#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)
17617
17618/******************************* DCMI Instances *******************************/
17619#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
17620
17621
17622/******************************* DMA2D Instances *******************************/
17623#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
17624
17625/******************************** DMA Instances *******************************/
17626#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
17627 ((__INSTANCE__) == DMA1_Stream1) || \
17628 ((__INSTANCE__) == DMA1_Stream2) || \
17629 ((__INSTANCE__) == DMA1_Stream3) || \
17630 ((__INSTANCE__) == DMA1_Stream4) || \
17631 ((__INSTANCE__) == DMA1_Stream5) || \
17632 ((__INSTANCE__) == DMA1_Stream6) || \
17633 ((__INSTANCE__) == DMA1_Stream7) || \
17634 ((__INSTANCE__) == DMA2_Stream0) || \
17635 ((__INSTANCE__) == DMA2_Stream1) || \
17636 ((__INSTANCE__) == DMA2_Stream2) || \
17637 ((__INSTANCE__) == DMA2_Stream3) || \
17638 ((__INSTANCE__) == DMA2_Stream4) || \
17639 ((__INSTANCE__) == DMA2_Stream5) || \
17640 ((__INSTANCE__) == DMA2_Stream6) || \
17641 ((__INSTANCE__) == DMA2_Stream7))
17642
17643/******************************* GPIO Instances *******************************/
17644#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
17645 ((__INSTANCE__) == GPIOB) || \
17646 ((__INSTANCE__) == GPIOC) || \
17647 ((__INSTANCE__) == GPIOD) || \
17648 ((__INSTANCE__) == GPIOE) || \
17649 ((__INSTANCE__) == GPIOF) || \
17650 ((__INSTANCE__) == GPIOG) || \
17651 ((__INSTANCE__) == GPIOH) || \
17652 ((__INSTANCE__) == GPIOI) || \
17653 ((__INSTANCE__) == GPIOJ) || \
17654 ((__INSTANCE__) == GPIOK))
17655
17656#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
17657 ((__INSTANCE__) == GPIOB) || \
17658 ((__INSTANCE__) == GPIOC) || \
17659 ((__INSTANCE__) == GPIOD) || \
17660 ((__INSTANCE__) == GPIOE) || \
17661 ((__INSTANCE__) == GPIOF) || \
17662 ((__INSTANCE__) == GPIOG) || \
17663 ((__INSTANCE__) == GPIOH) || \
17664 ((__INSTANCE__) == GPIOI) || \
17665 ((__INSTANCE__) == GPIOJ) || \
17666 ((__INSTANCE__) == GPIOK))
17667
17668/****************************** CEC Instances *********************************/
17669#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
17670
17671/****************************** QSPI Instances *********************************/
17672#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
17673
17674
17675/******************************** I2C Instances *******************************/
17676#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
17677 ((__INSTANCE__) == I2C2) || \
17678 ((__INSTANCE__) == I2C3) || \
17679 ((__INSTANCE__) == I2C4))
17680
17681/****************************** SMBUS Instances *******************************/
17682#define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
17683 ((__INSTANCE__) == I2C2) || \
17684 ((__INSTANCE__) == I2C3) || \
17685 ((__INSTANCE__) == I2C4))
17686
17687
17688/******************************** I2S Instances *******************************/
17689#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
17690 ((__INSTANCE__) == SPI2) || \
17691 ((__INSTANCE__) == SPI3))
17692
17693/******************************* LPTIM Instances ********************************/
17694#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
17695
17696/****************************** LTDC Instances ********************************/
17697#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
17698
17699
17700
17701
17702/******************************* RNG Instances ********************************/
17703#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
17704
17705/****************************** RTC Instances *********************************/
17706#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
17707
17708/******************************* SAI Instances ********************************/
17709#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
17710 ((__PERIPH__) == SAI1_Block_B) || \
17711 ((__PERIPH__) == SAI2_Block_A) || \
17712 ((__PERIPH__) == SAI2_Block_B))
17713/* Legacy define */
17714#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
17715
17716/******************************** SDMMC Instances *******************************/
17717#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
17718
17719/****************************** SPDIFRX Instances *********************************/
17720#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
17721
17722/******************************** SPI Instances *******************************/
17723#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
17724 ((__INSTANCE__) == SPI2) || \
17725 ((__INSTANCE__) == SPI3) || \
17726 ((__INSTANCE__) == SPI4) || \
17727 ((__INSTANCE__) == SPI5) || \
17728 ((__INSTANCE__) == SPI6))
17729
17730/****************** TIM Instances : All supported instances *******************/
17731#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17732 ((__INSTANCE__) == TIM2) || \
17733 ((__INSTANCE__) == TIM3) || \
17734 ((__INSTANCE__) == TIM4) || \
17735 ((__INSTANCE__) == TIM5) || \
17736 ((__INSTANCE__) == TIM6) || \
17737 ((__INSTANCE__) == TIM7) || \
17738 ((__INSTANCE__) == TIM8) || \
17739 ((__INSTANCE__) == TIM9) || \
17740 ((__INSTANCE__) == TIM10) || \
17741 ((__INSTANCE__) == TIM11) || \
17742 ((__INSTANCE__) == TIM12) || \
17743 ((__INSTANCE__) == TIM13) || \
17744 ((__INSTANCE__) == TIM14))
17745
17746/****************** TIM Instances : supporting 32 bits counter ****************/
17747#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
17748 ((__INSTANCE__) == TIM5))
17749
17750/****************** TIM Instances : supporting the break function *************/
17751#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17752 ((INSTANCE) == TIM8))
17753
17754/************** TIM Instances : supporting Break source selection *************/
17755#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17756 ((INSTANCE) == TIM8))
17757
17758/****************** TIM Instances : supporting 2 break inputs *****************/
17759#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
17760 ((INSTANCE) == TIM8))
17761
17762/************* TIM Instances : at least 1 capture/compare channel *************/
17763#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17764 ((__INSTANCE__) == TIM2) || \
17765 ((__INSTANCE__) == TIM3) || \
17766 ((__INSTANCE__) == TIM4) || \
17767 ((__INSTANCE__) == TIM5) || \
17768 ((__INSTANCE__) == TIM8) || \
17769 ((__INSTANCE__) == TIM9) || \
17770 ((__INSTANCE__) == TIM10) || \
17771 ((__INSTANCE__) == TIM11) || \
17772 ((__INSTANCE__) == TIM12) || \
17773 ((__INSTANCE__) == TIM13) || \
17774 ((__INSTANCE__) == TIM14))
17775
17776/************ TIM Instances : at least 2 capture/compare channels *************/
17777#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17778 ((__INSTANCE__) == TIM2) || \
17779 ((__INSTANCE__) == TIM3) || \
17780 ((__INSTANCE__) == TIM4) || \
17781 ((__INSTANCE__) == TIM5) || \
17782 ((__INSTANCE__) == TIM8) || \
17783 ((__INSTANCE__) == TIM9) || \
17784 ((__INSTANCE__) == TIM12))
17785
17786/************ TIM Instances : at least 3 capture/compare channels *************/
17787#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17788 ((__INSTANCE__) == TIM2) || \
17789 ((__INSTANCE__) == TIM3) || \
17790 ((__INSTANCE__) == TIM4) || \
17791 ((__INSTANCE__) == TIM5) || \
17792 ((__INSTANCE__) == TIM8))
17793
17794/************ TIM Instances : at least 4 capture/compare channels *************/
17795#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17796 ((__INSTANCE__) == TIM2) || \
17797 ((__INSTANCE__) == TIM3) || \
17798 ((__INSTANCE__) == TIM4) || \
17799 ((__INSTANCE__) == TIM5) || \
17800 ((__INSTANCE__) == TIM8))
17801
17802/****************** TIM Instances : at least 5 capture/compare channels *******/
17803#define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17804 ((__INSTANCE__) == TIM8))
17805
17806/****************** TIM Instances : at least 6 capture/compare channels *******/
17807#define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17808 ((__INSTANCE__) == TIM8))
17809
17810/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
17811#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17812 ((__INSTANCE__) == TIM8))
17813
17814/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
17815#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17816 ((__INSTANCE__) == TIM8) || \
17817 ((__INSTANCE__) == TIM2) || \
17818 ((__INSTANCE__) == TIM3) || \
17819 ((__INSTANCE__) == TIM4) || \
17820 ((__INSTANCE__) == TIM5) || \
17821 ((__INSTANCE__) == TIM6) || \
17822 ((__INSTANCE__) == TIM7))
17823
17824/************ TIM Instances : DMA requests generation (CCxDE) *****************/
17825#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17826 ((__INSTANCE__) == TIM2) || \
17827 ((__INSTANCE__) == TIM3) || \
17828 ((__INSTANCE__) == TIM4) || \
17829 ((__INSTANCE__) == TIM5) || \
17830 ((__INSTANCE__) == TIM8))
17831
17832/******************** TIM Instances : DMA burst feature ***********************/
17833#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17834 ((__INSTANCE__) == TIM2) || \
17835 ((__INSTANCE__) == TIM3) || \
17836 ((__INSTANCE__) == TIM4) || \
17837 ((__INSTANCE__) == TIM5) || \
17838 ((__INSTANCE__) == TIM8))
17839
17840/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
17841#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
17842 (((__INSTANCE__) == TIM1) || \
17843 ((__INSTANCE__) == TIM8))
17844
17845/****************** TIM Instances : supporting counting mode selection ********/
17846#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17847 ((__INSTANCE__) == TIM2) || \
17848 ((__INSTANCE__) == TIM3) || \
17849 ((__INSTANCE__) == TIM4) || \
17850 ((__INSTANCE__) == TIM5) || \
17851 ((__INSTANCE__) == TIM8))
17852
17853/****************** TIM Instances : supporting encoder interface **************/
17854#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17855 ((__INSTANCE__) == TIM2) || \
17856 ((__INSTANCE__) == TIM3) || \
17857 ((__INSTANCE__) == TIM4) || \
17858 ((__INSTANCE__) == TIM5) || \
17859 ((__INSTANCE__) == TIM8))
17860
17861/****************** TIM Instances : supporting OCxREF clear *******************/
17862#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
17863 (((__INSTANCE__) == TIM2) || \
17864 ((__INSTANCE__) == TIM3) || \
17865 ((__INSTANCE__) == TIM4) || \
17866 ((__INSTANCE__) == TIM5))
17867
17868/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
17869#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
17870 (((__INSTANCE__) == TIM1) || \
17871 ((__INSTANCE__) == TIM2) || \
17872 ((__INSTANCE__) == TIM3) || \
17873 ((__INSTANCE__) == TIM4) || \
17874 ((__INSTANCE__) == TIM5) || \
17875 ((__INSTANCE__) == TIM8))
17876
17877/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
17878#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
17879 (((__INSTANCE__) == TIM1) || \
17880 ((__INSTANCE__) == TIM2) || \
17881 ((__INSTANCE__) == TIM3) || \
17882 ((__INSTANCE__) == TIM4) || \
17883 ((__INSTANCE__) == TIM5) || \
17884 ((__INSTANCE__) == TIM8))
17885
17886/******************** TIM Instances : Advanced-control timers *****************/
17887#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17888 ((__INSTANCE__) == TIM8))
17889
17890/******************* TIM Instances : Timer input XOR function *****************/
17891#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17892 ((__INSTANCE__) == TIM2) || \
17893 ((__INSTANCE__) == TIM3) || \
17894 ((__INSTANCE__) == TIM4) || \
17895 ((__INSTANCE__) == TIM5) || \
17896 ((__INSTANCE__) == TIM8))
17897
17898/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
17899#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17900 ((__INSTANCE__) == TIM2) || \
17901 ((__INSTANCE__) == TIM3) || \
17902 ((__INSTANCE__) == TIM4) || \
17903 ((__INSTANCE__) == TIM5) || \
17904 ((__INSTANCE__) == TIM6) || \
17905 ((__INSTANCE__) == TIM7) || \
17906 ((__INSTANCE__) == TIM8))
17907
17908/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
17909#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17910 ((__INSTANCE__) == TIM2) || \
17911 ((__INSTANCE__) == TIM3) || \
17912 ((__INSTANCE__) == TIM4) || \
17913 ((__INSTANCE__) == TIM5) || \
17914 ((__INSTANCE__) == TIM8) || \
17915 ((__INSTANCE__) == TIM9) || \
17916 ((__INSTANCE__) == TIM12))
17917
17918/***************** TIM Instances : external trigger input available ************/
17919#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
17920 ((__INSTANCE__) == TIM2) || \
17921 ((__INSTANCE__) == TIM3) || \
17922 ((__INSTANCE__) == TIM4) || \
17923 ((__INSTANCE__) == TIM5) || \
17924 ((__INSTANCE__) == TIM8))
17925
17926/****************** TIM Instances : remapping capability **********************/
17927#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
17928 ((__INSTANCE__) == TIM5) || \
17929 ((__INSTANCE__) == TIM11))
17930
17931/******************* TIM Instances : output(s) available **********************/
17932#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
17933 ((((__INSTANCE__) == TIM1) && \
17934 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17935 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17936 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17937 ((__CHANNEL__) == TIM_CHANNEL_4) || \
17938 ((__CHANNEL__) == TIM_CHANNEL_5) || \
17939 ((__CHANNEL__) == TIM_CHANNEL_6))) \
17940 || \
17941 (((__INSTANCE__) == TIM2) && \
17942 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17943 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17944 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17945 ((__CHANNEL__) == TIM_CHANNEL_4))) \
17946 || \
17947 (((__INSTANCE__) == TIM3) && \
17948 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17949 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17950 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17951 ((__CHANNEL__) == TIM_CHANNEL_4))) \
17952 || \
17953 (((__INSTANCE__) == TIM4) && \
17954 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17955 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17956 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17957 ((__CHANNEL__) == TIM_CHANNEL_4))) \
17958 || \
17959 (((__INSTANCE__) == TIM5) && \
17960 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17961 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17962 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17963 ((__CHANNEL__) == TIM_CHANNEL_4))) \
17964 || \
17965 (((__INSTANCE__) == TIM8) && \
17966 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17967 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17968 ((__CHANNEL__) == TIM_CHANNEL_3) || \
17969 ((__CHANNEL__) == TIM_CHANNEL_4) || \
17970 ((__CHANNEL__) == TIM_CHANNEL_5) || \
17971 ((__CHANNEL__) == TIM_CHANNEL_6))) \
17972 || \
17973 (((__INSTANCE__) == TIM9) && \
17974 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17975 ((__CHANNEL__) == TIM_CHANNEL_2))) \
17976 || \
17977 (((__INSTANCE__) == TIM10) && \
17978 (((__CHANNEL__) == TIM_CHANNEL_1))) \
17979 || \
17980 (((__INSTANCE__) == TIM11) && \
17981 (((__CHANNEL__) == TIM_CHANNEL_1))) \
17982 || \
17983 (((__INSTANCE__) == TIM12) && \
17984 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17985 ((__CHANNEL__) == TIM_CHANNEL_2))) \
17986 || \
17987 (((__INSTANCE__) == TIM13) && \
17988 (((__CHANNEL__) == TIM_CHANNEL_1))) \
17989 || \
17990 (((__INSTANCE__) == TIM14) && \
17991 (((__CHANNEL__) == TIM_CHANNEL_1))))
17992
17993/************ TIM Instances : complementary output(s) available ***************/
17994#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
17995 ((((__INSTANCE__) == TIM1) && \
17996 (((__CHANNEL__) == TIM_CHANNEL_1) || \
17997 ((__CHANNEL__) == TIM_CHANNEL_2) || \
17998 ((__CHANNEL__) == TIM_CHANNEL_3))) \
17999 || \
18000 (((__INSTANCE__) == TIM8) && \
18001 (((__CHANNEL__) == TIM_CHANNEL_1) || \
18002 ((__CHANNEL__) == TIM_CHANNEL_2) || \
18003 ((__CHANNEL__) == TIM_CHANNEL_3))))
18004
18005/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
18006#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
18007 (((__INSTANCE__) == TIM1) || \
18008 ((__INSTANCE__) == TIM8) )
18009
18010/****************** TIM Instances : supporting clock division *****************/
18011#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
18012 ((__INSTANCE__) == TIM2) || \
18013 ((__INSTANCE__) == TIM3) || \
18014 ((__INSTANCE__) == TIM4) || \
18015 ((__INSTANCE__) == TIM5) || \
18016 ((__INSTANCE__) == TIM8) || \
18017 ((__INSTANCE__) == TIM9) || \
18018 ((__INSTANCE__) == TIM10) || \
18019 ((__INSTANCE__) == TIM11) || \
18020 ((__INSTANCE__) == TIM12) || \
18021 ((__INSTANCE__) == TIM13) || \
18022 ((__INSTANCE__) == TIM14))
18023
18024/****************** TIM Instances : supporting repetition counter *************/
18025#define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
18026 ((__INSTANCE__) == TIM8))
18027
18028/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
18029#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
18030 ((__INSTANCE__) == TIM2) || \
18031 ((__INSTANCE__) == TIM3) || \
18032 ((__INSTANCE__) == TIM4) || \
18033 ((__INSTANCE__) == TIM5) || \
18034 ((__INSTANCE__) == TIM8) || \
18035 ((__INSTANCE__) == TIM9) || \
18036 ((__INSTANCE__) == TIM12))
18037
18038/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
18039#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
18040 ((__INSTANCE__) == TIM2) || \
18041 ((__INSTANCE__) == TIM3) || \
18042 ((__INSTANCE__) == TIM4) || \
18043 ((__INSTANCE__) == TIM5) || \
18044 ((__INSTANCE__) == TIM8))
18045
18046/****************** TIM Instances : supporting Hall sensor interface **********/
18047#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
18048 ((__INSTANCE__) == TIM2) || \
18049 ((__INSTANCE__) == TIM3) || \
18050 ((__INSTANCE__) == TIM4) || \
18051 ((__INSTANCE__) == TIM5) || \
18052 ((__INSTANCE__) == TIM8))
18053
18054/****************** TIM Instances : supporting commutation event generation ***/
18055#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
18056 ((__INSTANCE__) == TIM8))
18057
18058/******************** USART Instances : Synchronous mode **********************/
18059#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18060 ((__INSTANCE__) == USART2) || \
18061 ((__INSTANCE__) == USART3) || \
18062 ((__INSTANCE__) == USART6))
18063
18064/******************** UART Instances : Asynchronous mode **********************/
18065#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18066 ((__INSTANCE__) == USART2) || \
18067 ((__INSTANCE__) == USART3) || \
18068 ((__INSTANCE__) == UART4) || \
18069 ((__INSTANCE__) == UART5) || \
18070 ((__INSTANCE__) == USART6) || \
18071 ((__INSTANCE__) == UART7) || \
18072 ((__INSTANCE__) == UART8))
18073
18074/****************** UART Instances : Auto Baud Rate detection ****************/
18075#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18076 ((__INSTANCE__) == USART2) || \
18077 ((__INSTANCE__) == USART3) || \
18078 ((__INSTANCE__) == USART6))
18079
18080/****************** UART Instances : Driver Enable *****************/
18081#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18082 ((__INSTANCE__) == USART2) || \
18083 ((__INSTANCE__) == USART3) || \
18084 ((__INSTANCE__) == UART4) || \
18085 ((__INSTANCE__) == UART5) || \
18086 ((__INSTANCE__) == USART6) || \
18087 ((__INSTANCE__) == UART7) || \
18088 ((__INSTANCE__) == UART8))
18089
18090/******************** UART Instances : Half-Duplex mode **********************/
18091#define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18092 ((__INSTANCE__) == USART2) || \
18093 ((__INSTANCE__) == USART3) || \
18094 ((__INSTANCE__) == UART4) || \
18095 ((__INSTANCE__) == UART5) || \
18096 ((__INSTANCE__) == USART6) || \
18097 ((__INSTANCE__) == UART7) || \
18098 ((__INSTANCE__) == UART8))
18099
18100/****************** UART Instances : Hardware Flow control ********************/
18101#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18102 ((__INSTANCE__) == USART2) || \
18103 ((__INSTANCE__) == USART3) || \
18104 ((__INSTANCE__) == UART4) || \
18105 ((__INSTANCE__) == UART5) || \
18106 ((__INSTANCE__) == USART6) || \
18107 ((__INSTANCE__) == UART7) || \
18108 ((__INSTANCE__) == UART8))
18109
18110/******************** UART Instances : LIN mode **********************/
18111#define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18112 ((__INSTANCE__) == USART2) || \
18113 ((__INSTANCE__) == USART3) || \
18114 ((__INSTANCE__) == UART4) || \
18115 ((__INSTANCE__) == UART5) || \
18116 ((__INSTANCE__) == USART6) || \
18117 ((__INSTANCE__) == UART7) || \
18118 ((__INSTANCE__) == UART8))
18119
18120/********************* UART Instances : Smart card mode ***********************/
18121#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18122 ((__INSTANCE__) == USART2) || \
18123 ((__INSTANCE__) == USART3) || \
18124 ((__INSTANCE__) == USART6))
18125
18126/*********************** UART Instances : IRDA mode ***************************/
18127#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
18128 ((__INSTANCE__) == USART2) || \
18129 ((__INSTANCE__) == USART3) || \
18130 ((__INSTANCE__) == UART4) || \
18131 ((__INSTANCE__) == UART5) || \
18132 ((__INSTANCE__) == USART6) || \
18133 ((__INSTANCE__) == UART7) || \
18134 ((__INSTANCE__) == UART8))
18135
18136/****************************** IWDG Instances ********************************/
18137#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
18138
18139/****************************** WWDG Instances ********************************/
18140#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
18141
18142/*********************** PCD Instances ****************************************/
18143#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
18144 ((INSTANCE) == USB_OTG_HS))
18145
18146/*********************** HCD Instances ****************************************/
18147#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
18148 ((INSTANCE) == USB_OTG_HS))
18149
18150/******************************************************************************/
18151/* For a painless codes migration between the STM32F7xx device product */
18152/* lines, the aliases defined below are put in place to overcome the */
18153/* differences in the interrupt handlers and IRQn definitions. */
18154/* No need to update developed interrupt code when moving across */
18155/* product lines within the same STM32F7 Family */
18156/******************************************************************************/
18157
18158/* Aliases for __IRQn */
18159#define RNG_IRQn HASH_RNG_IRQn
18160
18161/* Aliases for __IRQHandler */
18162#define RNG_IRQHandler HASH_RNG_IRQHandler
18163
18176#ifdef __cplusplus
18177}
18178#endif /* __cplusplus */
18179
18180#endif /* __STM32F756xx_H */
18181
18182
18183/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition core_cm3.h:170
__I
#define __I
Definition core_cm3.h:167
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f756xx.h:50
PendSV_IRQn
@ PendSV_IRQn
Definition stm32f756xx.h:58
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition stm32f756xx.h:123
EXTI2_IRQn
@ EXTI2_IRQn
Definition stm32f756xx.h:69
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition stm32f756xx.h:74
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition stm32f756xx.h:83
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition stm32f756xx.h:64
SPDIF_RX_IRQn
@ SPDIF_RX_IRQn
Definition stm32f756xx.h:158
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition stm32f756xx.h:136
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition stm32f756xx.h:117
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition stm32f756xx.h:130
UART7_IRQn
@ UART7_IRQn
Definition stm32f756xx.h:143
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition stm32f756xx.h:93
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition stm32f756xx.h:94
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition stm32f756xx.h:53
SAI1_IRQn
@ SAI1_IRQn
Definition stm32f756xx.h:148
TIM4_IRQn
@ TIM4_IRQn
Definition stm32f756xx.h:91
TIM2_IRQn
@ TIM2_IRQn
Definition stm32f756xx.h:89
LTDC_ER_IRQn
@ LTDC_ER_IRQn
Definition stm32f756xx.h:150
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition stm32f756xx.h:131
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition stm32f756xx.h:104
USART2_IRQn
@ USART2_IRQn
Definition stm32f756xx.h:99
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition stm32f756xx.h:120
SVCall_IRQn
@ SVCall_IRQn
Definition stm32f756xx.h:56
ADC_IRQn
@ ADC_IRQn
Definition stm32f756xx.h:79
SPI3_IRQn
@ SPI3_IRQn
Definition stm32f756xx.h:112
SPI2_IRQn
@ SPI2_IRQn
Definition stm32f756xx.h:97
TIM7_IRQn
@ TIM7_IRQn
Definition stm32f756xx.h:116
UART8_IRQn
@ UART8_IRQn
Definition stm32f756xx.h:144
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition stm32f756xx.h:127
RCC_IRQn
@ RCC_IRQn
Definition stm32f756xx.h:66
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition stm32f756xx.h:115
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition stm32f756xx.h:135
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition stm32f756xx.h:95
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition stm32f756xx.h:153
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition stm32f756xx.h:107
UsageFault_IRQn
@ UsageFault_IRQn
Definition stm32f756xx.h:55
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition stm32f756xx.h:157
SysTick_IRQn
@ SysTick_IRQn
Definition stm32f756xx.h:59
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition stm32f756xx.h:134
CRYP_IRQn
@ CRYP_IRQn
Definition stm32f756xx.h:140
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition stm32f756xx.h:133
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition stm32f756xx.h:125
BusFault_IRQn
@ BusFault_IRQn
Definition stm32f756xx.h:54
HASH_RNG_IRQn
@ HASH_RNG_IRQn
Definition stm32f756xx.h:141
CEC_IRQn
@ CEC_IRQn
Definition stm32f756xx.h:155
SPI5_IRQn
@ SPI5_IRQn
Definition stm32f756xx.h:146
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition stm32f756xx.h:57
FLASH_IRQn
@ FLASH_IRQn
Definition stm32f756xx.h:65
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition stm32f756xx.h:129
WWDG_IRQn
@ WWDG_IRQn
Definition stm32f756xx.h:61
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition stm32f756xx.h:92
TIM3_IRQn
@ TIM3_IRQn
Definition stm32f756xx.h:90
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition stm32f756xx.h:118
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition stm32f756xx.h:80
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition stm32f756xx.h:137
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition stm32f756xx.h:110
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition stm32f756xx.h:72
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition stm32f756xx.h:101
SPI4_IRQn
@ SPI4_IRQn
Definition stm32f756xx.h:145
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f756xx.h:86
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition stm32f756xx.h:84
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition stm32f756xx.h:73
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition stm32f756xx.h:154
SPI6_IRQn
@ SPI6_IRQn
Definition stm32f756xx.h:147
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition stm32f756xx.h:128
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition stm32f756xx.h:103
FPU_IRQn
@ FPU_IRQn
Definition stm32f756xx.h:142
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition stm32f756xx.h:105
USART6_IRQn
@ USART6_IRQn
Definition stm32f756xx.h:132
SPI1_IRQn
@ SPI1_IRQn
Definition stm32f756xx.h:96
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition stm32f756xx.h:138
PVD_IRQn
@ PVD_IRQn
Definition stm32f756xx.h:62
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f756xx.h:87
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition stm32f756xx.h:85
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition stm32f756xx.h:126
FMC_IRQn
@ FMC_IRQn
Definition stm32f756xx.h:109
EXTI0_IRQn
@ EXTI0_IRQn
Definition stm32f756xx.h:67
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition stm32f756xx.h:81
EXTI4_IRQn
@ EXTI4_IRQn
Definition stm32f756xx.h:71
SAI2_IRQn
@ SAI2_IRQn
Definition stm32f756xx.h:152
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition stm32f756xx.h:119
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f756xx.h:63
UART5_IRQn
@ UART5_IRQn
Definition stm32f756xx.h:114
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition stm32f756xx.h:77
DMA2D_IRQn
@ DMA2D_IRQn
Definition stm32f756xx.h:151
DCMI_IRQn
@ DCMI_IRQn
Definition stm32f756xx.h:139
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition stm32f756xx.h:156
ETH_IRQn
@ ETH_IRQn
Definition stm32f756xx.h:122
USART1_IRQn
@ USART1_IRQn
Definition stm32f756xx.h:98
EXTI3_IRQn
@ EXTI3_IRQn
Definition stm32f756xx.h:70
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition stm32f756xx.h:52
UART4_IRQn
@ UART4_IRQn
Definition stm32f756xx.h:113
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition stm32f756xx.h:106
EXTI1_IRQn
@ EXTI1_IRQn
Definition stm32f756xx.h:68
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition stm32f756xx.h:121
TIM5_IRQn
@ TIM5_IRQn
Definition stm32f756xx.h:111
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition stm32f756xx.h:108
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f756xx.h:76
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition stm32f756xx.h:78
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition stm32f756xx.h:88
LTDC_IRQn
@ LTDC_IRQn
Definition stm32f756xx.h:149
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition stm32f756xx.h:124
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition stm32f756xx.h:82
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition stm32f756xx.h:75
USART3_IRQn
@ USART3_IRQn
Definition stm32f756xx.h:100
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition stm32f756xx.h:102
PMC
#define PMC
Definition MK60D10.h:8809
ADC_Common_TypeDef
Definition stm32f107xc.h:187
ADC_TypeDef
Analog to Digital Converter
Definition stm32f107xc.h:163
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition stm32f107xc.h:267
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition stm32f107xc.h:279
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition stm32f107xc.h:255
CAN_TypeDef
Controller Area Network.
Definition stm32f107xc.h:289
CEC_TypeDef
HDMI-CEC.
Definition stm32f745xx.h:287
CRC_TypeDef
CRC calculation unit.
Definition stm32f107xc.h:319
CRYP_TypeDef
Crypto Processor.
Definition stm32f217xx.h:784
DAC_TypeDef
Digital to Analog Converter.
Definition stm32f107xc.h:332
DBGMCU_TypeDef
Debug MCU.
Definition stm32f107xc.h:353
DCMI_TypeDef
DCMI.
Definition stm32f207xx.h:325
DIR
Definition ff_types.h:208
DMA2D_TypeDef
DMA2D Controller.
Definition stm32f427xx.h:373
DMA_Stream_TypeDef
DMA Controller.
Definition stm32f207xx.h:344
DMA_TypeDef
Definition stm32f107xc.h:371
ETH_TypeDef
Ethernet MAC.
Definition stm32f107xc.h:383
EXTI_TypeDef
External Interrupt/Event Controller.
Definition stm32f107xc.h:455
FLASH_TypeDef
FLASH Registers.
Definition stm32f107xc.h:469
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition stm32f427xx.h:517
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition stm32f427xx.h:508
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition stm32f469xx.h:611
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition stm32f427xx.h:560
GPIO_TypeDef
General Purpose I/O.
Definition stm32f107xc.h:502
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition stm32f417xx.h:843
HASH_TypeDef
HASH.
Definition stm32f217xx.h:812
I2C_TypeDef
Inter Integrated Circuit Interface.
Definition stm32f107xc.h:529
IWDG_TypeDef
Independent WATCHDOG.
Definition stm32f107xc.h:546
LPTIM_TypeDef
LPTIMIMER.
Definition stm32f745xx.h:892
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition stm32f429xx.h:660
LTDC_TypeDef
LCD-TFT Display Controller.
Definition stm32f429xx.h:635
PWR_TypeDef
Power Control.
Definition stm32f107xc.h:558
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition stm32f469xx.h:909
RCC_TypeDef
Reset and Clock Control.
Definition stm32f107xc.h:568
RNG_TypeDef
RNG.
Definition stm32f207xx.h:782
RTC_TypeDef
Real-Time Clock.
Definition stm32f107xc.h:590
SAI_Block_TypeDef
Definition stm32f427xx.h:737
SAI_TypeDef
Serial Audio Interface.
Definition stm32f427xx.h:732
SDMMC_TypeDef
SD host Interface.
Definition stm32f745xx.h:794
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition stm32f745xx.h:779
SPI_TypeDef
Serial Peripheral Interface.
Definition stm32f107xc.h:608
SYSCFG_TypeDef
System configuration controller.
Definition stm32f207xx.h:542
TIM_TypeDef
TIM Timers.
Definition stm32f107xc.h:624
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32f107xc.h:654
USB_OTG_DeviceTypeDef
__device_Registers
Definition stm32f107xc.h:696
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition stm32f107xc.h:670
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition stm32f107xc.h:770
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition stm32f107xc.h:755
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition stm32f107xc.h:724
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition stm32f107xc.h:740
WWDG_TypeDef
Window WATCHDOG.
Definition stm32f107xc.h:785
system_stm32f7xx.h
CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.