mikroSDK Reference Manual
stm32f779xx.h
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1
34#ifndef __STM32F779xx_H
35#define __STM32F779xx_H
36
37#ifdef __cplusplus
38 extern "C" {
39#endif /* __cplusplus */
40
49typedef enum
50{
51/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
52 NonMaskableInt_IRQn = -14,
53 MemoryManagement_IRQn = -12,
54 BusFault_IRQn = -11,
55 UsageFault_IRQn = -10,
56 SVCall_IRQn = -5,
57 DebugMonitor_IRQn = -4,
58 PendSV_IRQn = -2,
59 SysTick_IRQn = -1,
60/****** STM32 specific Interrupt Numbers **********************************************************************/
61 WWDG_IRQn = 0,
62 PVD_IRQn = 1,
63 TAMP_STAMP_IRQn = 2,
64 RTC_WKUP_IRQn = 3,
65 FLASH_IRQn = 4,
66 RCC_IRQn = 5,
67 EXTI0_IRQn = 6,
68 EXTI1_IRQn = 7,
69 EXTI2_IRQn = 8,
70 EXTI3_IRQn = 9,
71 EXTI4_IRQn = 10,
72 DMA1_Stream0_IRQn = 11,
73 DMA1_Stream1_IRQn = 12,
74 DMA1_Stream2_IRQn = 13,
75 DMA1_Stream3_IRQn = 14,
76 DMA1_Stream4_IRQn = 15,
77 DMA1_Stream5_IRQn = 16,
78 DMA1_Stream6_IRQn = 17,
79 ADC_IRQn = 18,
80 CAN1_TX_IRQn = 19,
81 CAN1_RX0_IRQn = 20,
82 CAN1_RX1_IRQn = 21,
83 CAN1_SCE_IRQn = 22,
84 EXTI9_5_IRQn = 23,
85 TIM1_BRK_TIM9_IRQn = 24,
86 TIM1_UP_TIM10_IRQn = 25,
87 TIM1_TRG_COM_TIM11_IRQn = 26,
88 TIM1_CC_IRQn = 27,
89 TIM2_IRQn = 28,
90 TIM3_IRQn = 29,
91 TIM4_IRQn = 30,
92 I2C1_EV_IRQn = 31,
93 I2C1_ER_IRQn = 32,
94 I2C2_EV_IRQn = 33,
95 I2C2_ER_IRQn = 34,
96 SPI1_IRQn = 35,
97 SPI2_IRQn = 36,
98 USART1_IRQn = 37,
99 USART2_IRQn = 38,
100 USART3_IRQn = 39,
101 EXTI15_10_IRQn = 40,
102 RTC_Alarm_IRQn = 41,
103 OTG_FS_WKUP_IRQn = 42,
104 TIM8_BRK_TIM12_IRQn = 43,
105 TIM8_UP_TIM13_IRQn = 44,
106 TIM8_TRG_COM_TIM14_IRQn = 45,
107 TIM8_CC_IRQn = 46,
108 DMA1_Stream7_IRQn = 47,
109 FMC_IRQn = 48,
110 SDMMC1_IRQn = 49,
111 TIM5_IRQn = 50,
112 SPI3_IRQn = 51,
113 UART4_IRQn = 52,
114 UART5_IRQn = 53,
115 TIM6_DAC_IRQn = 54,
116 TIM7_IRQn = 55,
117 DMA2_Stream0_IRQn = 56,
118 DMA2_Stream1_IRQn = 57,
119 DMA2_Stream2_IRQn = 58,
120 DMA2_Stream3_IRQn = 59,
121 DMA2_Stream4_IRQn = 60,
122 ETH_IRQn = 61,
123 ETH_WKUP_IRQn = 62,
124 CAN2_TX_IRQn = 63,
125 CAN2_RX0_IRQn = 64,
126 CAN2_RX1_IRQn = 65,
127 CAN2_SCE_IRQn = 66,
128 OTG_FS_IRQn = 67,
129 DMA2_Stream5_IRQn = 68,
130 DMA2_Stream6_IRQn = 69,
131 DMA2_Stream7_IRQn = 70,
132 USART6_IRQn = 71,
133 I2C3_EV_IRQn = 72,
134 I2C3_ER_IRQn = 73,
135 OTG_HS_EP1_OUT_IRQn = 74,
136 OTG_HS_EP1_IN_IRQn = 75,
137 OTG_HS_WKUP_IRQn = 76,
138 OTG_HS_IRQn = 77,
139 DCMI_IRQn = 78,
140 CRYP_IRQn = 79,
141 HASH_RNG_IRQn = 80,
142 FPU_IRQn = 81,
143 UART7_IRQn = 82,
144 UART8_IRQn = 83,
145 SPI4_IRQn = 84,
146 SPI5_IRQn = 85,
147 SPI6_IRQn = 86,
148 SAI1_IRQn = 87,
149 LTDC_IRQn = 88,
150 LTDC_ER_IRQn = 89,
151 DMA2D_IRQn = 90,
152 SAI2_IRQn = 91,
153 QUADSPI_IRQn = 92,
154 LPTIM1_IRQn = 93,
155 CEC_IRQn = 94,
156 I2C4_EV_IRQn = 95,
157 I2C4_ER_IRQn = 96,
158 SPDIF_RX_IRQn = 97,
159 DSI_IRQn = 98,
160 DFSDM1_FLT0_IRQn = 99,
161 DFSDM1_FLT1_IRQn = 100,
162 DFSDM1_FLT2_IRQn = 101,
163 DFSDM1_FLT3_IRQn = 102,
164 SDMMC2_IRQn = 103,
165 CAN3_TX_IRQn = 104,
166 CAN3_RX0_IRQn = 105,
167 CAN3_RX1_IRQn = 106,
168 CAN3_SCE_IRQn = 107,
169 JPEG_IRQn = 108,
170 MDIOS_IRQn = 109
171} IRQn_Type;
172
180#define __CM7_REV 0x0100U
181#define __MPU_PRESENT 1
182#define __NVIC_PRIO_BITS 4
183#define __Vendor_SysTickConfig 0
184#define __FPU_PRESENT 1
185#define __ICACHE_PRESENT 1
186#define __DCACHE_PRESENT 1
187#include "core_cm7.h"
190#include "system_stm32f7xx.h"
191#include <stdint.h>
192
201typedef struct
202{
203 __IO uint32_t SR;
204 __IO uint32_t CR1;
205 __IO uint32_t CR2;
206 __IO uint32_t SMPR1;
207 __IO uint32_t SMPR2;
208 __IO uint32_t JOFR1;
209 __IO uint32_t JOFR2;
210 __IO uint32_t JOFR3;
211 __IO uint32_t JOFR4;
212 __IO uint32_t HTR;
213 __IO uint32_t LTR;
214 __IO uint32_t SQR1;
215 __IO uint32_t SQR2;
216 __IO uint32_t SQR3;
217 __IO uint32_t JSQR;
218 __IO uint32_t JDR1;
219 __IO uint32_t JDR2;
220 __IO uint32_t JDR3;
221 __IO uint32_t JDR4;
222 __IO uint32_t DR;
223} ADC_TypeDef;
224
225typedef struct
226{
227 __IO uint32_t CSR;
228 __IO uint32_t CCR;
229 __IO uint32_t CDR;
231} ADC_Common_TypeDef;
232
233
238typedef struct
239{
240 __IO uint32_t TIR;
241 __IO uint32_t TDTR;
242 __IO uint32_t TDLR;
243 __IO uint32_t TDHR;
244} CAN_TxMailBox_TypeDef;
245
250typedef struct
251{
252 __IO uint32_t RIR;
253 __IO uint32_t RDTR;
254 __IO uint32_t RDLR;
255 __IO uint32_t RDHR;
256} CAN_FIFOMailBox_TypeDef;
257
262typedef struct
263{
264 __IO uint32_t FR1;
265 __IO uint32_t FR2;
266} CAN_FilterRegister_TypeDef;
267
272typedef struct
273{
274 __IO uint32_t MCR;
275 __IO uint32_t MSR;
276 __IO uint32_t TSR;
277 __IO uint32_t RF0R;
278 __IO uint32_t RF1R;
279 __IO uint32_t IER;
280 __IO uint32_t ESR;
281 __IO uint32_t BTR;
282 uint32_t RESERVED0[88];
283 CAN_TxMailBox_TypeDef sTxMailBox[3];
284 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
285 uint32_t RESERVED1[12];
286 __IO uint32_t FMR;
287 __IO uint32_t FM1R;
288 uint32_t RESERVED2;
289 __IO uint32_t FS1R;
290 uint32_t RESERVED3;
291 __IO uint32_t FFA1R;
292 uint32_t RESERVED4;
293 __IO uint32_t FA1R;
294 uint32_t RESERVED5[8];
295 CAN_FilterRegister_TypeDef sFilterRegister[28];
296} CAN_TypeDef;
297
302typedef struct
303{
304 __IO uint32_t CR;
305 __IO uint32_t CFGR;
306 __IO uint32_t TXDR;
307 __IO uint32_t RXDR;
308 __IO uint32_t ISR;
309 __IO uint32_t IER;
310}CEC_TypeDef;
311
316typedef struct
317{
318 __IO uint32_t DR;
319 __IO uint8_t IDR;
320 uint8_t RESERVED0;
321 uint16_t RESERVED1;
322 __IO uint32_t CR;
323 uint32_t RESERVED2;
324 __IO uint32_t INIT;
325 __IO uint32_t POL;
326} CRC_TypeDef;
327
332typedef struct
333{
334 __IO uint32_t CR;
335 __IO uint32_t SWTRIGR;
336 __IO uint32_t DHR12R1;
337 __IO uint32_t DHR12L1;
338 __IO uint32_t DHR8R1;
339 __IO uint32_t DHR12R2;
340 __IO uint32_t DHR12L2;
341 __IO uint32_t DHR8R2;
342 __IO uint32_t DHR12RD;
343 __IO uint32_t DHR12LD;
344 __IO uint32_t DHR8RD;
345 __IO uint32_t DOR1;
346 __IO uint32_t DOR2;
347 __IO uint32_t SR;
348} DAC_TypeDef;
349
353typedef struct
354{
355 __IO uint32_t FLTCR1;
356 __IO uint32_t FLTCR2;
357 __IO uint32_t FLTISR;
358 __IO uint32_t FLTICR;
359 __IO uint32_t FLTJCHGR;
360 __IO uint32_t FLTFCR;
361 __IO uint32_t FLTJDATAR;
362 __IO uint32_t FLTRDATAR;
363 __IO uint32_t FLTAWHTR;
364 __IO uint32_t FLTAWLTR;
365 __IO uint32_t FLTAWSR;
366 __IO uint32_t FLTAWCFR;
367 __IO uint32_t FLTEXMAX;
368 __IO uint32_t FLTEXMIN;
369 __IO uint32_t FLTCNVTIMR;
370} DFSDM_Filter_TypeDef;
371
375typedef struct
376{
377 __IO uint32_t CHCFGR1;
378 __IO uint32_t CHCFGR2;
379 __IO uint32_t CHAWSCDR;
381 __IO uint32_t CHWDATAR;
382 __IO uint32_t CHDATINR;
383} DFSDM_Channel_TypeDef;
384
389typedef struct
390{
391 __IO uint32_t IDCODE;
392 __IO uint32_t CR;
393 __IO uint32_t APB1FZ;
394 __IO uint32_t APB2FZ;
395}DBGMCU_TypeDef;
396
401typedef struct
402{
403 __IO uint32_t CR;
404 __IO uint32_t SR;
405 __IO uint32_t RISR;
406 __IO uint32_t IER;
407 __IO uint32_t MISR;
408 __IO uint32_t ICR;
409 __IO uint32_t ESCR;
410 __IO uint32_t ESUR;
411 __IO uint32_t CWSTRTR;
412 __IO uint32_t CWSIZER;
413 __IO uint32_t DR;
414} DCMI_TypeDef;
415
420typedef struct
421{
422 __IO uint32_t CR;
423 __IO uint32_t NDTR;
424 __IO uint32_t PAR;
425 __IO uint32_t M0AR;
426 __IO uint32_t M1AR;
427 __IO uint32_t FCR;
428} DMA_Stream_TypeDef;
429
430typedef struct
431{
432 __IO uint32_t LISR;
433 __IO uint32_t HISR;
434 __IO uint32_t LIFCR;
435 __IO uint32_t HIFCR;
436} DMA_TypeDef;
437
442typedef struct
443{
444 __IO uint32_t CR;
445 __IO uint32_t ISR;
446 __IO uint32_t IFCR;
447 __IO uint32_t FGMAR;
448 __IO uint32_t FGOR;
449 __IO uint32_t BGMAR;
450 __IO uint32_t BGOR;
451 __IO uint32_t FGPFCCR;
452 __IO uint32_t FGCOLR;
453 __IO uint32_t BGPFCCR;
454 __IO uint32_t BGCOLR;
455 __IO uint32_t FGCMAR;
456 __IO uint32_t BGCMAR;
457 __IO uint32_t OPFCCR;
458 __IO uint32_t OCOLR;
459 __IO uint32_t OMAR;
460 __IO uint32_t OOR;
461 __IO uint32_t NLR;
462 __IO uint32_t LWR;
463 __IO uint32_t AMTCR;
464 uint32_t RESERVED[236];
465 __IO uint32_t FGCLUT[256];
466 __IO uint32_t BGCLUT[256];
467} DMA2D_TypeDef;
468
469
474typedef struct
475{
476 __IO uint32_t MACCR;
477 __IO uint32_t MACFFR;
478 __IO uint32_t MACHTHR;
479 __IO uint32_t MACHTLR;
480 __IO uint32_t MACMIIAR;
481 __IO uint32_t MACMIIDR;
482 __IO uint32_t MACFCR;
483 __IO uint32_t MACVLANTR; /* 8 */
484 uint32_t RESERVED0[2];
485 __IO uint32_t MACRWUFFR; /* 11 */
486 __IO uint32_t MACPMTCSR;
487 uint32_t RESERVED1;
488 __IO uint32_t MACDBGR;
489 __IO uint32_t MACSR; /* 15 */
490 __IO uint32_t MACIMR;
491 __IO uint32_t MACA0HR;
492 __IO uint32_t MACA0LR;
493 __IO uint32_t MACA1HR;
494 __IO uint32_t MACA1LR;
495 __IO uint32_t MACA2HR;
496 __IO uint32_t MACA2LR;
497 __IO uint32_t MACA3HR;
498 __IO uint32_t MACA3LR; /* 24 */
499 uint32_t RESERVED2[40];
500 __IO uint32_t MMCCR; /* 65 */
501 __IO uint32_t MMCRIR;
502 __IO uint32_t MMCTIR;
503 __IO uint32_t MMCRIMR;
504 __IO uint32_t MMCTIMR; /* 69 */
505 uint32_t RESERVED3[14];
506 __IO uint32_t MMCTGFSCCR; /* 84 */
507 __IO uint32_t MMCTGFMSCCR;
508 uint32_t RESERVED4[5];
509 __IO uint32_t MMCTGFCR;
510 uint32_t RESERVED5[10];
511 __IO uint32_t MMCRFCECR;
512 __IO uint32_t MMCRFAECR;
513 uint32_t RESERVED6[10];
514 __IO uint32_t MMCRGUFCR;
515 uint32_t RESERVED7[334];
516 __IO uint32_t PTPTSCR;
517 __IO uint32_t PTPSSIR;
518 __IO uint32_t PTPTSHR;
519 __IO uint32_t PTPTSLR;
520 __IO uint32_t PTPTSHUR;
521 __IO uint32_t PTPTSLUR;
522 __IO uint32_t PTPTSAR;
523 __IO uint32_t PTPTTHR;
524 __IO uint32_t PTPTTLR;
525 __IO uint32_t RESERVED8;
526 __IO uint32_t PTPTSSR;
527 __IO uint32_t PTPPPSCR;
528 uint32_t RESERVED9[564];
529 __IO uint32_t DMABMR;
530 __IO uint32_t DMATPDR;
531 __IO uint32_t DMARPDR;
532 __IO uint32_t DMARDLAR;
533 __IO uint32_t DMATDLAR;
534 __IO uint32_t DMASR;
535 __IO uint32_t DMAOMR;
536 __IO uint32_t DMAIER;
537 __IO uint32_t DMAMFBOCR;
538 __IO uint32_t DMARSWTR;
539 uint32_t RESERVED10[8];
540 __IO uint32_t DMACHTDR;
541 __IO uint32_t DMACHRDR;
542 __IO uint32_t DMACHTBAR;
543 __IO uint32_t DMACHRBAR;
544} ETH_TypeDef;
545
550typedef struct
551{
552 __IO uint32_t IMR;
553 __IO uint32_t EMR;
554 __IO uint32_t RTSR;
555 __IO uint32_t FTSR;
556 __IO uint32_t SWIER;
557 __IO uint32_t PR;
558} EXTI_TypeDef;
559
564typedef struct
565{
566 __IO uint32_t ACR;
567 __IO uint32_t KEYR;
568 __IO uint32_t OPTKEYR;
569 __IO uint32_t SR;
570 __IO uint32_t CR;
571 __IO uint32_t OPTCR;
572 __IO uint32_t OPTCR1;
573} FLASH_TypeDef;
574
575
576
581typedef struct
582{
583 __IO uint32_t BTCR[8];
584} FMC_Bank1_TypeDef;
585
590typedef struct
591{
592 __IO uint32_t BWTR[7];
593} FMC_Bank1E_TypeDef;
594
599typedef struct
600{
601 __IO uint32_t PCR;
602 __IO uint32_t SR;
603 __IO uint32_t PMEM;
604 __IO uint32_t PATT;
605 uint32_t RESERVED0;
606 __IO uint32_t ECCR;
607} FMC_Bank3_TypeDef;
608
613typedef struct
614{
615 __IO uint32_t SDCR[2];
616 __IO uint32_t SDTR[2];
617 __IO uint32_t SDCMR;
618 __IO uint32_t SDRTR;
619 __IO uint32_t SDSR;
620} FMC_Bank5_6_TypeDef;
621
622
627typedef struct
628{
629 __IO uint32_t MODER;
630 __IO uint32_t OTYPER;
631 __IO uint32_t OSPEEDR;
632 __IO uint32_t PUPDR;
633 __IO uint32_t IDR;
634 __IO uint32_t ODR;
635 __IO uint32_t BSRR;
636 __IO uint32_t LCKR;
637 __IO uint32_t AFR[2];
638} GPIO_TypeDef;
639
644typedef struct
645{
646 __IO uint32_t MEMRMP;
647 __IO uint32_t PMC;
648 __IO uint32_t EXTICR[4];
649 uint32_t RESERVED;
650 __IO uint32_t CBR;
651 __IO uint32_t CMPCR;
652} SYSCFG_TypeDef;
653
658typedef struct
659{
660 __IO uint32_t CR1;
661 __IO uint32_t CR2;
662 __IO uint32_t OAR1;
663 __IO uint32_t OAR2;
664 __IO uint32_t TIMINGR;
665 __IO uint32_t TIMEOUTR;
666 __IO uint32_t ISR;
667 __IO uint32_t ICR;
668 __IO uint32_t PECR;
669 __IO uint32_t RXDR;
670 __IO uint32_t TXDR;
671} I2C_TypeDef;
672
677typedef struct
678{
679 __IO uint32_t KR;
680 __IO uint32_t PR;
681 __IO uint32_t RLR;
682 __IO uint32_t SR;
683 __IO uint32_t WINR;
684} IWDG_TypeDef;
685
686
691typedef struct
692{
693 uint32_t RESERVED0[2];
694 __IO uint32_t SSCR;
695 __IO uint32_t BPCR;
696 __IO uint32_t AWCR;
697 __IO uint32_t TWCR;
698 __IO uint32_t GCR;
699 uint32_t RESERVED1[2];
700 __IO uint32_t SRCR;
701 uint32_t RESERVED2[1];
702 __IO uint32_t BCCR;
703 uint32_t RESERVED3[1];
704 __IO uint32_t IER;
705 __IO uint32_t ISR;
706 __IO uint32_t ICR;
707 __IO uint32_t LIPCR;
708 __IO uint32_t CPSR;
709 __IO uint32_t CDSR;
710} LTDC_TypeDef;
711
716typedef struct
717{
718 __IO uint32_t CR;
719 __IO uint32_t WHPCR;
720 __IO uint32_t WVPCR;
721 __IO uint32_t CKCR;
722 __IO uint32_t PFCR;
723 __IO uint32_t CACR;
724 __IO uint32_t DCCR;
725 __IO uint32_t BFCR;
726 uint32_t RESERVED0[2];
727 __IO uint32_t CFBAR;
728 __IO uint32_t CFBLR;
729 __IO uint32_t CFBLNR;
730 uint32_t RESERVED1[3];
731 __IO uint32_t CLUTWR;
733} LTDC_Layer_TypeDef;
734
739typedef struct
740{
741 __IO uint32_t CR1;
742 __IO uint32_t CSR1;
743 __IO uint32_t CR2;
744 __IO uint32_t CSR2;
745} PWR_TypeDef;
746
747
752typedef struct
753{
754 __IO uint32_t CR;
755 __IO uint32_t PLLCFGR;
756 __IO uint32_t CFGR;
757 __IO uint32_t CIR;
758 __IO uint32_t AHB1RSTR;
759 __IO uint32_t AHB2RSTR;
760 __IO uint32_t AHB3RSTR;
761 uint32_t RESERVED0;
762 __IO uint32_t APB1RSTR;
763 __IO uint32_t APB2RSTR;
764 uint32_t RESERVED1[2];
765 __IO uint32_t AHB1ENR;
766 __IO uint32_t AHB2ENR;
767 __IO uint32_t AHB3ENR;
768 uint32_t RESERVED2;
769 __IO uint32_t APB1ENR;
770 __IO uint32_t APB2ENR;
771 uint32_t RESERVED3[2];
772 __IO uint32_t AHB1LPENR;
773 __IO uint32_t AHB2LPENR;
774 __IO uint32_t AHB3LPENR;
775 uint32_t RESERVED4;
776 __IO uint32_t APB1LPENR;
777 __IO uint32_t APB2LPENR;
778 uint32_t RESERVED5[2];
779 __IO uint32_t BDCR;
780 __IO uint32_t CSR;
781 uint32_t RESERVED6[2];
782 __IO uint32_t SSCGR;
783 __IO uint32_t PLLI2SCFGR;
784 __IO uint32_t PLLSAICFGR;
785 __IO uint32_t DCKCFGR1;
786 __IO uint32_t DCKCFGR2;
788} RCC_TypeDef;
789
794typedef struct
795{
796 __IO uint32_t TR;
797 __IO uint32_t DR;
798 __IO uint32_t CR;
799 __IO uint32_t ISR;
800 __IO uint32_t PRER;
801 __IO uint32_t WUTR;
802 uint32_t reserved;
803 __IO uint32_t ALRMAR;
804 __IO uint32_t ALRMBR;
805 __IO uint32_t WPR;
806 __IO uint32_t SSR;
807 __IO uint32_t SHIFTR;
808 __IO uint32_t TSTR;
809 __IO uint32_t TSDR;
810 __IO uint32_t TSSSR;
811 __IO uint32_t CALR;
812 __IO uint32_t TAMPCR;
813 __IO uint32_t ALRMASSR;
814 __IO uint32_t ALRMBSSR;
815 __IO uint32_t OR;
816 __IO uint32_t BKP0R;
817 __IO uint32_t BKP1R;
818 __IO uint32_t BKP2R;
819 __IO uint32_t BKP3R;
820 __IO uint32_t BKP4R;
821 __IO uint32_t BKP5R;
822 __IO uint32_t BKP6R;
823 __IO uint32_t BKP7R;
824 __IO uint32_t BKP8R;
825 __IO uint32_t BKP9R;
826 __IO uint32_t BKP10R;
827 __IO uint32_t BKP11R;
828 __IO uint32_t BKP12R;
829 __IO uint32_t BKP13R;
830 __IO uint32_t BKP14R;
831 __IO uint32_t BKP15R;
832 __IO uint32_t BKP16R;
833 __IO uint32_t BKP17R;
834 __IO uint32_t BKP18R;
835 __IO uint32_t BKP19R;
836 __IO uint32_t BKP20R;
837 __IO uint32_t BKP21R;
838 __IO uint32_t BKP22R;
839 __IO uint32_t BKP23R;
840 __IO uint32_t BKP24R;
841 __IO uint32_t BKP25R;
842 __IO uint32_t BKP26R;
843 __IO uint32_t BKP27R;
844 __IO uint32_t BKP28R;
845 __IO uint32_t BKP29R;
846 __IO uint32_t BKP30R;
847 __IO uint32_t BKP31R;
848} RTC_TypeDef;
849
850
855typedef struct
856{
857 __IO uint32_t GCR;
858} SAI_TypeDef;
859
860typedef struct
861{
862 __IO uint32_t CR1;
863 __IO uint32_t CR2;
864 __IO uint32_t FRCR;
865 __IO uint32_t SLOTR;
866 __IO uint32_t IMR;
867 __IO uint32_t SR;
868 __IO uint32_t CLRFR;
869 __IO uint32_t DR;
870} SAI_Block_TypeDef;
871
876typedef struct
877{
878 __IO uint32_t CR;
879 __IO uint32_t IMR;
880 __IO uint32_t SR;
881 __IO uint32_t IFCR;
882 __IO uint32_t DR;
883 __IO uint32_t CSR;
884 __IO uint32_t DIR;
885} SPDIFRX_TypeDef;
886
891typedef struct
892{
893 __IO uint32_t POWER;
894 __IO uint32_t CLKCR;
895 __IO uint32_t ARG;
896 __IO uint32_t CMD;
897 __I uint32_t RESPCMD;
898 __I uint32_t RESP1;
899 __I uint32_t RESP2;
900 __I uint32_t RESP3;
901 __I uint32_t RESP4;
902 __IO uint32_t DTIMER;
903 __IO uint32_t DLEN;
904 __IO uint32_t DCTRL;
905 __I uint32_t DCOUNT;
906 __I uint32_t STA;
907 __IO uint32_t ICR;
908 __IO uint32_t MASK;
909 uint32_t RESERVED0[2];
910 __I uint32_t FIFOCNT;
911 uint32_t RESERVED1[13];
912 __IO uint32_t FIFO;
913} SDMMC_TypeDef;
914
919typedef struct
920{
921 __IO uint32_t CR1;
922 __IO uint32_t CR2;
923 __IO uint32_t SR;
924 __IO uint32_t DR;
925 __IO uint32_t CRCPR;
926 __IO uint32_t RXCRCR;
927 __IO uint32_t TXCRCR;
928 __IO uint32_t I2SCFGR;
929 __IO uint32_t I2SPR;
930} SPI_TypeDef;
931
936typedef struct
937{
938 __IO uint32_t CR;
939 __IO uint32_t DCR;
940 __IO uint32_t SR;
941 __IO uint32_t FCR;
942 __IO uint32_t DLR;
943 __IO uint32_t CCR;
944 __IO uint32_t AR;
945 __IO uint32_t ABR;
946 __IO uint32_t DR;
947 __IO uint32_t PSMKR;
948 __IO uint32_t PSMAR;
949 __IO uint32_t PIR;
950 __IO uint32_t LPTR;
951} QUADSPI_TypeDef;
952
957typedef struct
958{
959 __IO uint32_t CR1;
960 __IO uint32_t CR2;
961 __IO uint32_t SMCR;
962 __IO uint32_t DIER;
963 __IO uint32_t SR;
964 __IO uint32_t EGR;
965 __IO uint32_t CCMR1;
966 __IO uint32_t CCMR2;
967 __IO uint32_t CCER;
968 __IO uint32_t CNT;
969 __IO uint32_t PSC;
970 __IO uint32_t ARR;
971 __IO uint32_t RCR;
972 __IO uint32_t CCR1;
973 __IO uint32_t CCR2;
974 __IO uint32_t CCR3;
975 __IO uint32_t CCR4;
976 __IO uint32_t BDTR;
977 __IO uint32_t DCR;
978 __IO uint32_t DMAR;
979 __IO uint32_t OR;
980 __IO uint32_t CCMR3;
981 __IO uint32_t CCR5;
982 __IO uint32_t CCR6;
983 __IO uint32_t AF1;
984 __IO uint32_t AF2;
986} TIM_TypeDef;
987
991typedef struct
992{
993 __IO uint32_t ISR;
994 __IO uint32_t ICR;
995 __IO uint32_t IER;
996 __IO uint32_t CFGR;
997 __IO uint32_t CR;
998 __IO uint32_t CMP;
999 __IO uint32_t ARR;
1000 __IO uint32_t CNT;
1001} LPTIM_TypeDef;
1002
1003
1008typedef struct
1009{
1010 __IO uint32_t CR1;
1011 __IO uint32_t CR2;
1012 __IO uint32_t CR3;
1013 __IO uint32_t BRR;
1014 __IO uint32_t GTPR;
1015 __IO uint32_t RTOR;
1016 __IO uint32_t RQR;
1017 __IO uint32_t ISR;
1018 __IO uint32_t ICR;
1019 __IO uint32_t RDR;
1020 __IO uint32_t TDR;
1021} USART_TypeDef;
1022
1023
1028typedef struct
1029{
1030 __IO uint32_t CR;
1031 __IO uint32_t CFR;
1032 __IO uint32_t SR;
1033} WWDG_TypeDef;
1034
1039typedef struct
1040{
1041 __IO uint32_t CR;
1042 __IO uint32_t SR;
1043 __IO uint32_t DIN;
1044 __IO uint32_t DOUT;
1045 __IO uint32_t DMACR;
1046 __IO uint32_t IMSCR;
1047 __IO uint32_t RISR;
1048 __IO uint32_t MISR;
1049 __IO uint32_t K0LR;
1050 __IO uint32_t K0RR;
1051 __IO uint32_t K1LR;
1052 __IO uint32_t K1RR;
1053 __IO uint32_t K2LR;
1054 __IO uint32_t K2RR;
1055 __IO uint32_t K3LR;
1056 __IO uint32_t K3RR;
1057 __IO uint32_t IV0LR;
1058 __IO uint32_t IV0RR;
1059 __IO uint32_t IV1LR;
1060 __IO uint32_t IV1RR;
1061 __IO uint32_t CSGCMCCM0R;
1062 __IO uint32_t CSGCMCCM1R;
1063 __IO uint32_t CSGCMCCM2R;
1064 __IO uint32_t CSGCMCCM3R;
1065 __IO uint32_t CSGCMCCM4R;
1066 __IO uint32_t CSGCMCCM5R;
1067 __IO uint32_t CSGCMCCM6R;
1068 __IO uint32_t CSGCMCCM7R;
1069 __IO uint32_t CSGCM0R;
1070 __IO uint32_t CSGCM1R;
1071 __IO uint32_t CSGCM2R;
1072 __IO uint32_t CSGCM3R;
1073 __IO uint32_t CSGCM4R;
1074 __IO uint32_t CSGCM5R;
1075 __IO uint32_t CSGCM6R;
1076 __IO uint32_t CSGCM7R;
1077} CRYP_TypeDef;
1078
1083typedef struct
1084{
1085 __IO uint32_t CR;
1086 __IO uint32_t DIN;
1087 __IO uint32_t STR;
1088 __IO uint32_t HR[5];
1089 __IO uint32_t IMR;
1090 __IO uint32_t SR;
1091 uint32_t RESERVED[52];
1092 __IO uint32_t CSR[54];
1093} HASH_TypeDef;
1094
1099typedef struct
1100{
1101 __IO uint32_t HR[8];
1102} HASH_DIGEST_TypeDef;
1103
1108typedef struct
1109{
1110 __IO uint32_t CR;
1111 __IO uint32_t SR;
1112 __IO uint32_t DR;
1113} RNG_TypeDef;
1114
1122typedef struct
1123{
1124 __IO uint32_t GOTGCTL;
1125 __IO uint32_t GOTGINT;
1126 __IO uint32_t GAHBCFG;
1127 __IO uint32_t GUSBCFG;
1128 __IO uint32_t GRSTCTL;
1129 __IO uint32_t GINTSTS;
1130 __IO uint32_t GINTMSK;
1131 __IO uint32_t GRXSTSR;
1132 __IO uint32_t GRXSTSP;
1133 __IO uint32_t GRXFSIZ;
1134 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1135 __IO uint32_t HNPTXSTS;
1136 uint32_t Reserved30[2];
1137 __IO uint32_t GCCFG;
1138 __IO uint32_t CID;
1139 uint32_t Reserved5[3];
1140 __IO uint32_t GHWCFG3;
1141 uint32_t Reserved6;
1142 __IO uint32_t GLPMCFG;
1143 uint32_t Reserved7;
1144 __IO uint32_t GDFIFOCFG;
1145 uint32_t Reserved43[40];
1146 __IO uint32_t HPTXFSIZ;
1147 __IO uint32_t DIEPTXF[0x0F];
1148} USB_OTG_GlobalTypeDef;
1149
1150
1154typedef struct
1155{
1156 __IO uint32_t DCFG;
1157 __IO uint32_t DCTL;
1158 __IO uint32_t DSTS;
1159 uint32_t Reserved0C;
1160 __IO uint32_t DIEPMSK;
1161 __IO uint32_t DOEPMSK;
1162 __IO uint32_t DAINT;
1163 __IO uint32_t DAINTMSK;
1164 uint32_t Reserved20;
1165 uint32_t Reserved9;
1166 __IO uint32_t DVBUSDIS;
1167 __IO uint32_t DVBUSPULSE;
1168 __IO uint32_t DTHRCTL;
1169 __IO uint32_t DIEPEMPMSK;
1170 __IO uint32_t DEACHINT;
1171 __IO uint32_t DEACHMSK;
1172 uint32_t Reserved40;
1173 __IO uint32_t DINEP1MSK;
1174 uint32_t Reserved44[15];
1175 __IO uint32_t DOUTEP1MSK;
1176} USB_OTG_DeviceTypeDef;
1177
1178
1182typedef struct
1183{
1184 __IO uint32_t DIEPCTL;
1185 uint32_t Reserved04;
1186 __IO uint32_t DIEPINT;
1187 uint32_t Reserved0C;
1188 __IO uint32_t DIEPTSIZ;
1189 __IO uint32_t DIEPDMA;
1190 __IO uint32_t DTXFSTS;
1191 uint32_t Reserved18;
1192} USB_OTG_INEndpointTypeDef;
1193
1194
1198typedef struct
1199{
1200 __IO uint32_t DOEPCTL;
1201 uint32_t Reserved04;
1202 __IO uint32_t DOEPINT;
1203 uint32_t Reserved0C;
1204 __IO uint32_t DOEPTSIZ;
1205 __IO uint32_t DOEPDMA;
1206 uint32_t Reserved18[2];
1207} USB_OTG_OUTEndpointTypeDef;
1208
1209
1213typedef struct
1214{
1215 __IO uint32_t HCFG;
1216 __IO uint32_t HFIR;
1217 __IO uint32_t HFNUM;
1218 uint32_t Reserved40C;
1219 __IO uint32_t HPTXSTS;
1220 __IO uint32_t HAINT;
1221 __IO uint32_t HAINTMSK;
1222} USB_OTG_HostTypeDef;
1223
1227typedef struct
1228{
1229 __IO uint32_t HCCHAR;
1230 __IO uint32_t HCSPLT;
1231 __IO uint32_t HCINT;
1232 __IO uint32_t HCINTMSK;
1233 __IO uint32_t HCTSIZ;
1234 __IO uint32_t HCDMA;
1235 uint32_t Reserved[2];
1236} USB_OTG_HostChannelTypeDef;
1244typedef struct
1245{
1246 __IO uint32_t CONFR0;
1247 __IO uint32_t CONFR1;
1248 __IO uint32_t CONFR2;
1249 __IO uint32_t CONFR3;
1250 __IO uint32_t CONFR4;
1251 __IO uint32_t CONFR5;
1252 __IO uint32_t CONFR6;
1253 __IO uint32_t CONFR7;
1254 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1255 __IO uint32_t CR;
1256 __IO uint32_t SR;
1257 __IO uint32_t CFR;
1258 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1259 __IO uint32_t DIR;
1260 __IO uint32_t DOR;
1261 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1262 __IO uint32_t QMEM0[16];
1263 __IO uint32_t QMEM1[16];
1264 __IO uint32_t QMEM2[16];
1265 __IO uint32_t QMEM3[16];
1266 __IO uint32_t HUFFMIN[16];
1267 __IO uint32_t HUFFBASE[32];
1268 __IO uint32_t HUFFSYMB[84];
1269 __IO uint32_t DHTMEM[103];
1270 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1271 __IO uint32_t HUFFENC_AC0[88];
1272 __IO uint32_t HUFFENC_AC1[88];
1273 __IO uint32_t HUFFENC_DC0[8];
1274 __IO uint32_t HUFFENC_DC1[8];
1276} JPEG_TypeDef;
1277
1282typedef struct
1283{
1284 __IO uint32_t CR;
1285 __IO uint32_t WRFR;
1286 __IO uint32_t CWRFR;
1287 __IO uint32_t RDFR;
1288 __IO uint32_t CRDFR;
1289 __IO uint32_t SR;
1290 __IO uint32_t CLRFR;
1291 uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
1292 __IO uint32_t DINR0;
1293 __IO uint32_t DINR1;
1294 __IO uint32_t DINR2;
1295 __IO uint32_t DINR3;
1296 __IO uint32_t DINR4;
1297 __IO uint32_t DINR5;
1298 __IO uint32_t DINR6;
1299 __IO uint32_t DINR7;
1300 __IO uint32_t DINR8;
1301 __IO uint32_t DINR9;
1302 __IO uint32_t DINR10;
1303 __IO uint32_t DINR11;
1304 __IO uint32_t DINR12;
1305 __IO uint32_t DINR13;
1306 __IO uint32_t DINR14;
1307 __IO uint32_t DINR15;
1308 __IO uint32_t DINR16;
1309 __IO uint32_t DINR17;
1310 __IO uint32_t DINR18;
1311 __IO uint32_t DINR19;
1312 __IO uint32_t DINR20;
1313 __IO uint32_t DINR21;
1314 __IO uint32_t DINR22;
1315 __IO uint32_t DINR23;
1316 __IO uint32_t DINR24;
1317 __IO uint32_t DINR25;
1318 __IO uint32_t DINR26;
1319 __IO uint32_t DINR27;
1320 __IO uint32_t DINR28;
1321 __IO uint32_t DINR29;
1322 __IO uint32_t DINR30;
1323 __IO uint32_t DINR31;
1324 __IO uint32_t DOUTR0;
1325 __IO uint32_t DOUTR1;
1326 __IO uint32_t DOUTR2;
1327 __IO uint32_t DOUTR3;
1328 __IO uint32_t DOUTR4;
1329 __IO uint32_t DOUTR5;
1330 __IO uint32_t DOUTR6;
1331 __IO uint32_t DOUTR7;
1332 __IO uint32_t DOUTR8;
1333 __IO uint32_t DOUTR9;
1334 __IO uint32_t DOUTR10;
1335 __IO uint32_t DOUTR11;
1336 __IO uint32_t DOUTR12;
1337 __IO uint32_t DOUTR13;
1338 __IO uint32_t DOUTR14;
1339 __IO uint32_t DOUTR15;
1340 __IO uint32_t DOUTR16;
1341 __IO uint32_t DOUTR17;
1342 __IO uint32_t DOUTR18;
1343 __IO uint32_t DOUTR19;
1344 __IO uint32_t DOUTR20;
1345 __IO uint32_t DOUTR21;
1346 __IO uint32_t DOUTR22;
1347 __IO uint32_t DOUTR23;
1348 __IO uint32_t DOUTR24;
1349 __IO uint32_t DOUTR25;
1350 __IO uint32_t DOUTR26;
1351 __IO uint32_t DOUTR27;
1352 __IO uint32_t DOUTR28;
1353 __IO uint32_t DOUTR29;
1354 __IO uint32_t DOUTR30;
1355 __IO uint32_t DOUTR31;
1356} MDIOS_TypeDef;
1357
1362typedef struct
1363{
1364 __IO uint32_t VR;
1365 __IO uint32_t CR;
1366 __IO uint32_t CCR;
1367 __IO uint32_t LVCIDR;
1368 __IO uint32_t LCOLCR;
1369 __IO uint32_t LPCR;
1370 __IO uint32_t LPMCR;
1371 uint32_t RESERVED0[4];
1372 __IO uint32_t PCR;
1373 __IO uint32_t GVCIDR;
1374 __IO uint32_t MCR;
1375 __IO uint32_t VMCR;
1376 __IO uint32_t VPCR;
1377 __IO uint32_t VCCR;
1378 __IO uint32_t VNPCR;
1379 __IO uint32_t VHSACR;
1380 __IO uint32_t VHBPCR;
1381 __IO uint32_t VLCR;
1382 __IO uint32_t VVSACR;
1383 __IO uint32_t VVBPCR;
1384 __IO uint32_t VVFPCR;
1385 __IO uint32_t VVACR;
1386 __IO uint32_t LCCR;
1387 __IO uint32_t CMCR;
1388 __IO uint32_t GHCR;
1389 __IO uint32_t GPDR;
1390 __IO uint32_t GPSR;
1391 __IO uint32_t TCCR[6];
1392 __IO uint32_t TDCR;
1393 __IO uint32_t CLCR;
1394 __IO uint32_t CLTCR;
1395 __IO uint32_t DLTCR;
1396 __IO uint32_t PCTLR;
1397 __IO uint32_t PCONFR;
1398 __IO uint32_t PUCR;
1399 __IO uint32_t PTTCR;
1400 __IO uint32_t PSR;
1401 uint32_t RESERVED1[2];
1402 __IO uint32_t ISR[2];
1403 __IO uint32_t IER[2];
1404 uint32_t RESERVED2[3];
1405 __IO uint32_t FIR[2];
1406 uint32_t RESERVED3[8];
1407 __IO uint32_t VSCR;
1408 uint32_t RESERVED4[2];
1409 __IO uint32_t LCVCIDR;
1410 __IO uint32_t LCCCR;
1411 uint32_t RESERVED5;
1412 __IO uint32_t LPMCCR;
1413 uint32_t RESERVED6[7];
1414 __IO uint32_t VMCCR;
1415 __IO uint32_t VPCCR;
1416 __IO uint32_t VCCCR;
1417 __IO uint32_t VNPCCR;
1418 __IO uint32_t VHSACCR;
1419 __IO uint32_t VHBPCCR;
1420 __IO uint32_t VLCCR;
1421 __IO uint32_t VVSACCR;
1422 __IO uint32_t VVBPCCR;
1423 __IO uint32_t VVFPCCR;
1424 __IO uint32_t VVACCR;
1425 uint32_t RESERVED7[11];
1426 __IO uint32_t TDCCR;
1427 uint32_t RESERVED8[155];
1428 __IO uint32_t WCFGR;
1429 __IO uint32_t WCR;
1430 __IO uint32_t WIER;
1431 __IO uint32_t WISR;
1432 __IO uint32_t WIFCR;
1433 uint32_t RESERVED9;
1434 __IO uint32_t WPCR[5];
1435 uint32_t RESERVED10;
1436 __IO uint32_t WRPCR;
1437} DSI_TypeDef;
1438
1442#define RAMITCM_BASE 0x00000000UL
1443#define FLASHITCM_BASE 0x00200000UL
1444#define FLASHAXI_BASE 0x08000000UL
1445#define RAMDTCM_BASE 0x20000000UL
1446#define PERIPH_BASE 0x40000000UL
1447#define BKPSRAM_BASE 0x40024000UL
1448#define QSPI_BASE 0x90000000UL
1449#define FMC_R_BASE 0xA0000000UL
1450#define QSPI_R_BASE 0xA0001000UL
1451#define SRAM1_BASE 0x20020000UL
1452#define SRAM2_BASE 0x2007C000UL
1453#define FLASH_END 0x081FFFFFUL
1454#define FLASH_OTP_BASE 0x1FF0F000UL
1455#define FLASH_OTP_END 0x1FF0F41FUL
1457/* Legacy define */
1458#define FLASH_BASE FLASHAXI_BASE
1459
1461#define APB1PERIPH_BASE PERIPH_BASE
1462#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1463#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1464#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
1465
1467#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1468#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1469#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1470#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1471#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1472#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1473#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
1474#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
1475#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
1476#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
1477#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1478#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1479#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1480#define CAN3_BASE (APB1PERIPH_BASE + 0x3400UL)
1481#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1482#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1483#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL)
1484#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1485#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1486#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1487#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1488#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1489#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1490#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
1491#define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL)
1492#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1493#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1494#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL)
1495#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1496#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1497#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
1498#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
1499
1501#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
1502#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
1503#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
1504#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
1505#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL)
1506#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
1507#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
1508#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
1509#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)
1510#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)
1511#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1512#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
1513#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
1514#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
1515#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
1516#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
1517#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
1518#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
1519#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
1520#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
1521#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)
1522#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
1523#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
1524#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
1525#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
1526#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
1527#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL)
1528#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL)
1529#define DSI_BASE (APB2PERIPH_BASE + 0x6C00UL)
1530#define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400UL)
1531#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
1532#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
1533#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
1534#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
1535#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
1536#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
1537#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
1538#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
1539#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
1540#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
1541#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
1542#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
1543#define MDIOS_BASE (APB2PERIPH_BASE + 0x7800UL)
1545#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
1546#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1547#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1548#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1549#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1550#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1551#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1552#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1553#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
1554#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
1555#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
1556#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1557#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1558#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1559#define UID_BASE 0x1FF0F420UL
1560#define FLASHSIZE_BASE 0x1FF0F442UL
1561#define PACKAGE_BASE 0x1FF0F7E0UL
1562/* Legacy define */
1563#define PACKAGESIZE_BASE PACKAGE_BASE
1564
1565#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1566#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1567#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1568#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1569#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1570#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1571#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1572#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1573#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1574#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1575#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1576#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1577#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1578#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1579#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1580#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1581#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1582#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1583#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
1584#define ETH_MAC_BASE (ETH_BASE)
1585#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
1586#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
1587#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
1588#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
1590#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1591#define JPEG_BASE (AHB2PERIPH_BASE + 0x51000UL)
1592#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000UL)
1593#define HASH_BASE (AHB2PERIPH_BASE + 0x60400UL)
1594#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710UL)
1595#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1597#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1598#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1599#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1600#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
1601
1602/* Debug MCU registers base address */
1603#define DBGMCU_BASE 0xE0042000UL
1604
1606#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1607#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1608
1609#define USB_OTG_GLOBAL_BASE 0x0000UL
1610#define USB_OTG_DEVICE_BASE 0x0800UL
1611#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL
1612#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL
1613#define USB_OTG_EP_REG_SIZE 0x0020UL
1614#define USB_OTG_HOST_BASE 0x0400UL
1615#define USB_OTG_HOST_PORT_BASE 0x0440UL
1616#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL
1617#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL
1618#define USB_OTG_PCGCCTL_BASE 0x0E00UL
1619#define USB_OTG_FIFO_BASE 0x1000UL
1620#define USB_OTG_FIFO_SIZE 0x1000UL
1621
1629#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1630#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1631#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1632#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1633#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1634#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1635#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1636#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1637#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1638#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1639#define RTC ((RTC_TypeDef *) RTC_BASE)
1640#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1641#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1642#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1643#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1644#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1645#define USART2 ((USART_TypeDef *) USART2_BASE)
1646#define USART3 ((USART_TypeDef *) USART3_BASE)
1647#define UART4 ((USART_TypeDef *) UART4_BASE)
1648#define UART5 ((USART_TypeDef *) UART5_BASE)
1649#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1650#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1651#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1652#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1653#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1654#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1655#define CEC ((CEC_TypeDef *) CEC_BASE)
1656#define PWR ((PWR_TypeDef *) PWR_BASE)
1657#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1658#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1659#define UART7 ((USART_TypeDef *) UART7_BASE)
1660#define UART8 ((USART_TypeDef *) UART8_BASE)
1661#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1662#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1663#define USART1 ((USART_TypeDef *) USART1_BASE)
1664#define USART6 ((USART_TypeDef *) USART6_BASE)
1665#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1666#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1667#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1668#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1669#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
1670#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1671#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1672#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1673#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1674#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1675#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1676#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1677#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1678#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1679#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1680#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1681#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1682#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1683#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1684#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1685#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1686#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1687#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1688#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1689#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1690#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1691#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1692#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1693#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1694#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1695#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1696#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1697#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1698#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1699#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1700#define CRC ((CRC_TypeDef *) CRC_BASE)
1701#define RCC ((RCC_TypeDef *) RCC_BASE)
1702#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1703#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1704#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1705#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1706#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1707#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1708#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1709#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1710#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1711#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1712#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1713#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1714#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1715#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1716#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1717#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1718#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1719#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1720#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1721#define ETH ((ETH_TypeDef *) ETH_BASE)
1722#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1723#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1724#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1725#define HASH ((HASH_TypeDef *) HASH_BASE)
1726#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1727#define RNG ((RNG_TypeDef *) RNG_BASE)
1728#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1729#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1730#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1731#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1732#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1733#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1734#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1735#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1736#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
1737#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
1738#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
1739#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1740#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1741#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1742#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1743#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1744#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1745#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1746#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1747#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1748#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1749#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1750#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1751#define JPEG ((JPEG_TypeDef *) JPEG_BASE)
1752#define DSI ((DSI_TypeDef *)DSI_BASE)
1753
1766/******************************************************************************/
1767/* Peripheral Registers_Bits_Definition */
1768/******************************************************************************/
1769
1770/******************************************************************************/
1771/* */
1772/* Analog to Digital Converter */
1773/* */
1774/******************************************************************************/
1775#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A))
1776#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF0F44C))
1777#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF0F44E))
1779/******************** Bit definition for ADC_SR register ********************/
1780#define ADC_SR_AWD_Pos (0U)
1781#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1782#define ADC_SR_AWD ADC_SR_AWD_Msk
1783#define ADC_SR_EOC_Pos (1U)
1784#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1785#define ADC_SR_EOC ADC_SR_EOC_Msk
1786#define ADC_SR_JEOC_Pos (2U)
1787#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1788#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1789#define ADC_SR_JSTRT_Pos (3U)
1790#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1791#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1792#define ADC_SR_STRT_Pos (4U)
1793#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1794#define ADC_SR_STRT ADC_SR_STRT_Msk
1795#define ADC_SR_OVR_Pos (5U)
1796#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1797#define ADC_SR_OVR ADC_SR_OVR_Msk
1799/******************* Bit definition for ADC_CR1 register ********************/
1800#define ADC_CR1_AWDCH_Pos (0U)
1801#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1802#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1803#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1804#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1805#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1806#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1807#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1808#define ADC_CR1_EOCIE_Pos (5U)
1809#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1810#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1811#define ADC_CR1_AWDIE_Pos (6U)
1812#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1813#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1814#define ADC_CR1_JEOCIE_Pos (7U)
1815#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1816#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1817#define ADC_CR1_SCAN_Pos (8U)
1818#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1819#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1820#define ADC_CR1_AWDSGL_Pos (9U)
1821#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1822#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1823#define ADC_CR1_JAUTO_Pos (10U)
1824#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1825#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1826#define ADC_CR1_DISCEN_Pos (11U)
1827#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1828#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1829#define ADC_CR1_JDISCEN_Pos (12U)
1830#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1831#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1832#define ADC_CR1_DISCNUM_Pos (13U)
1833#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1834#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1835#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1836#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1837#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1838#define ADC_CR1_JAWDEN_Pos (22U)
1839#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1840#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1841#define ADC_CR1_AWDEN_Pos (23U)
1842#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1843#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1844#define ADC_CR1_RES_Pos (24U)
1845#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1846#define ADC_CR1_RES ADC_CR1_RES_Msk
1847#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1848#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1849#define ADC_CR1_OVRIE_Pos (26U)
1850#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1851#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1853/******************* Bit definition for ADC_CR2 register ********************/
1854#define ADC_CR2_ADON_Pos (0U)
1855#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1856#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1857#define ADC_CR2_CONT_Pos (1U)
1858#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1859#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1860#define ADC_CR2_DMA_Pos (8U)
1861#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1862#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1863#define ADC_CR2_DDS_Pos (9U)
1864#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1865#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1866#define ADC_CR2_EOCS_Pos (10U)
1867#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1868#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1869#define ADC_CR2_ALIGN_Pos (11U)
1870#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1871#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1872#define ADC_CR2_JEXTSEL_Pos (16U)
1873#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1874#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1875#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1876#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1877#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1878#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1879#define ADC_CR2_JEXTEN_Pos (20U)
1880#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1881#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1882#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1883#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1884#define ADC_CR2_JSWSTART_Pos (22U)
1885#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1886#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1887#define ADC_CR2_EXTSEL_Pos (24U)
1888#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1889#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1890#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1891#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1892#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1893#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1894#define ADC_CR2_EXTEN_Pos (28U)
1895#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1896#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1897#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1898#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1899#define ADC_CR2_SWSTART_Pos (30U)
1900#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1901#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1903/****************** Bit definition for ADC_SMPR1 register *******************/
1904#define ADC_SMPR1_SMP10_Pos (0U)
1905#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1906#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1907#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1908#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1909#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1910#define ADC_SMPR1_SMP11_Pos (3U)
1911#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1912#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1913#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1914#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1915#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1916#define ADC_SMPR1_SMP12_Pos (6U)
1917#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1918#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1919#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1920#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1921#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1922#define ADC_SMPR1_SMP13_Pos (9U)
1923#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1924#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1925#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1926#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1927#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1928#define ADC_SMPR1_SMP14_Pos (12U)
1929#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1930#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1931#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1932#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1933#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1934#define ADC_SMPR1_SMP15_Pos (15U)
1935#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1936#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1937#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1938#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1939#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1940#define ADC_SMPR1_SMP16_Pos (18U)
1941#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1942#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1943#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1944#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1945#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1946#define ADC_SMPR1_SMP17_Pos (21U)
1947#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1948#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1949#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1950#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1951#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1952#define ADC_SMPR1_SMP18_Pos (24U)
1953#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1954#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1955#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1956#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1957#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1959/****************** Bit definition for ADC_SMPR2 register *******************/
1960#define ADC_SMPR2_SMP0_Pos (0U)
1961#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1962#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1963#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1964#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1965#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1966#define ADC_SMPR2_SMP1_Pos (3U)
1967#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1968#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1969#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1970#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1971#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1972#define ADC_SMPR2_SMP2_Pos (6U)
1973#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1974#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1975#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1976#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1977#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1978#define ADC_SMPR2_SMP3_Pos (9U)
1979#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1980#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1981#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1982#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1983#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1984#define ADC_SMPR2_SMP4_Pos (12U)
1985#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1986#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1987#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1988#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1989#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1990#define ADC_SMPR2_SMP5_Pos (15U)
1991#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1992#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1993#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1994#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1995#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1996#define ADC_SMPR2_SMP6_Pos (18U)
1997#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1998#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1999#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
2000#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
2001#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
2002#define ADC_SMPR2_SMP7_Pos (21U)
2003#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
2004#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
2005#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
2006#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
2007#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
2008#define ADC_SMPR2_SMP8_Pos (24U)
2009#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
2010#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
2011#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
2012#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
2013#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
2014#define ADC_SMPR2_SMP9_Pos (27U)
2015#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
2016#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
2017#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
2018#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
2019#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
2021/****************** Bit definition for ADC_JOFR1 register *******************/
2022#define ADC_JOFR1_JOFFSET1_Pos (0U)
2023#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
2024#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
2026/****************** Bit definition for ADC_JOFR2 register *******************/
2027#define ADC_JOFR2_JOFFSET2_Pos (0U)
2028#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
2029#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
2031/****************** Bit definition for ADC_JOFR3 register *******************/
2032#define ADC_JOFR3_JOFFSET3_Pos (0U)
2033#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
2034#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
2036/****************** Bit definition for ADC_JOFR4 register *******************/
2037#define ADC_JOFR4_JOFFSET4_Pos (0U)
2038#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
2039#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
2041/******************* Bit definition for ADC_HTR register ********************/
2042#define ADC_HTR_HT_Pos (0U)
2043#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
2044#define ADC_HTR_HT ADC_HTR_HT_Msk
2046/******************* Bit definition for ADC_LTR register ********************/
2047#define ADC_LTR_LT_Pos (0U)
2048#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
2049#define ADC_LTR_LT ADC_LTR_LT_Msk
2051/******************* Bit definition for ADC_SQR1 register *******************/
2052#define ADC_SQR1_SQ13_Pos (0U)
2053#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
2054#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
2055#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
2056#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
2057#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
2058#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
2059#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
2060#define ADC_SQR1_SQ14_Pos (5U)
2061#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
2062#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
2063#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
2064#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
2065#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
2066#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
2067#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
2068#define ADC_SQR1_SQ15_Pos (10U)
2069#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
2070#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
2071#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
2072#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
2073#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
2074#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
2075#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
2076#define ADC_SQR1_SQ16_Pos (15U)
2077#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
2078#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
2079#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
2080#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
2081#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
2082#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
2083#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
2084#define ADC_SQR1_L_Pos (20U)
2085#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
2086#define ADC_SQR1_L ADC_SQR1_L_Msk
2087#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
2088#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
2089#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
2090#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
2092/******************* Bit definition for ADC_SQR2 register *******************/
2093#define ADC_SQR2_SQ7_Pos (0U)
2094#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
2095#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
2096#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
2097#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
2098#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
2099#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
2100#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
2101#define ADC_SQR2_SQ8_Pos (5U)
2102#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
2103#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
2104#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
2105#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
2106#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
2107#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
2108#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
2109#define ADC_SQR2_SQ9_Pos (10U)
2110#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
2111#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
2112#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
2113#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
2114#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
2115#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
2116#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
2117#define ADC_SQR2_SQ10_Pos (15U)
2118#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
2119#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
2120#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
2121#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
2122#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
2123#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
2124#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
2125#define ADC_SQR2_SQ11_Pos (20U)
2126#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
2127#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
2128#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
2129#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
2130#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
2131#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
2132#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
2133#define ADC_SQR2_SQ12_Pos (25U)
2134#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
2135#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
2136#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
2137#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
2138#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
2139#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
2140#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
2142/******************* Bit definition for ADC_SQR3 register *******************/
2143#define ADC_SQR3_SQ1_Pos (0U)
2144#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
2145#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
2146#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
2147#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
2148#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
2149#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
2150#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
2151#define ADC_SQR3_SQ2_Pos (5U)
2152#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
2153#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
2154#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
2155#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
2156#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
2157#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
2158#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
2159#define ADC_SQR3_SQ3_Pos (10U)
2160#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
2161#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
2162#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
2163#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
2164#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
2165#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
2166#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
2167#define ADC_SQR3_SQ4_Pos (15U)
2168#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
2169#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
2170#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
2171#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
2172#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
2173#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
2174#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
2175#define ADC_SQR3_SQ5_Pos (20U)
2176#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
2177#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
2178#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
2179#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
2180#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
2181#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
2182#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
2183#define ADC_SQR3_SQ6_Pos (25U)
2184#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
2185#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
2186#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
2187#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
2188#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
2189#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
2190#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
2192/******************* Bit definition for ADC_JSQR register *******************/
2193#define ADC_JSQR_JSQ1_Pos (0U)
2194#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
2195#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
2196#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
2197#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
2198#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
2199#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
2200#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
2201#define ADC_JSQR_JSQ2_Pos (5U)
2202#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
2203#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
2204#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
2205#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
2206#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
2207#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
2208#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
2209#define ADC_JSQR_JSQ3_Pos (10U)
2210#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
2211#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
2212#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
2213#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
2214#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
2215#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
2216#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
2217#define ADC_JSQR_JSQ4_Pos (15U)
2218#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
2219#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
2220#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
2221#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
2222#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
2223#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
2224#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
2225#define ADC_JSQR_JL_Pos (20U)
2226#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
2227#define ADC_JSQR_JL ADC_JSQR_JL_Msk
2228#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
2229#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
2231/******************* Bit definition for ADC_JDR1 register *******************/
2232#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU)
2234/******************* Bit definition for ADC_JDR2 register *******************/
2235#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU)
2237/******************* Bit definition for ADC_JDR3 register *******************/
2238#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU)
2240/******************* Bit definition for ADC_JDR4 register *******************/
2241#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU)
2243/******************** Bit definition for ADC_DR register ********************/
2244#define ADC_DR_DATA_Pos (0U)
2245#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
2246#define ADC_DR_DATA ADC_DR_DATA_Msk
2247#define ADC_DR_ADC2DATA_Pos (16U)
2248#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
2249#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
2251/******************* Bit definition for ADC_CSR register ********************/
2252#define ADC_CSR_AWD1_Pos (0U)
2253#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
2254#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
2255#define ADC_CSR_EOC1_Pos (1U)
2256#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
2257#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
2258#define ADC_CSR_JEOC1_Pos (2U)
2259#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
2260#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
2261#define ADC_CSR_JSTRT1_Pos (3U)
2262#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
2263#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
2264#define ADC_CSR_STRT1_Pos (4U)
2265#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
2266#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
2267#define ADC_CSR_OVR1_Pos (5U)
2268#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
2269#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
2270#define ADC_CSR_AWD2_Pos (8U)
2271#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
2272#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
2273#define ADC_CSR_EOC2_Pos (9U)
2274#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
2275#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
2276#define ADC_CSR_JEOC2_Pos (10U)
2277#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
2278#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
2279#define ADC_CSR_JSTRT2_Pos (11U)
2280#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
2281#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
2282#define ADC_CSR_STRT2_Pos (12U)
2283#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
2284#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
2285#define ADC_CSR_OVR2_Pos (13U)
2286#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
2287#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
2288#define ADC_CSR_AWD3_Pos (16U)
2289#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
2290#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
2291#define ADC_CSR_EOC3_Pos (17U)
2292#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
2293#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
2294#define ADC_CSR_JEOC3_Pos (18U)
2295#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
2296#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
2297#define ADC_CSR_JSTRT3_Pos (19U)
2298#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
2299#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
2300#define ADC_CSR_STRT3_Pos (20U)
2301#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
2302#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
2303#define ADC_CSR_OVR3_Pos (21U)
2304#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
2305#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
2307/* Legacy defines */
2308#define ADC_CSR_DOVR1 ADC_CSR_OVR1
2309#define ADC_CSR_DOVR2 ADC_CSR_OVR2
2310#define ADC_CSR_DOVR3 ADC_CSR_OVR3
2311
2312
2313/******************* Bit definition for ADC_CCR register ********************/
2314#define ADC_CCR_MULTI_Pos (0U)
2315#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
2316#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
2317#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
2318#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
2319#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
2320#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
2321#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
2322#define ADC_CCR_DELAY_Pos (8U)
2323#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
2324#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
2325#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
2326#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
2327#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
2328#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
2329#define ADC_CCR_DDS_Pos (13U)
2330#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
2331#define ADC_CCR_DDS ADC_CCR_DDS_Msk
2332#define ADC_CCR_DMA_Pos (14U)
2333#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
2334#define ADC_CCR_DMA ADC_CCR_DMA_Msk
2335#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
2336#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
2337#define ADC_CCR_ADCPRE_Pos (16U)
2338#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
2339#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
2340#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
2341#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
2342#define ADC_CCR_VBATE_Pos (22U)
2343#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
2344#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
2345#define ADC_CCR_TSVREFE_Pos (23U)
2346#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
2347#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
2349/******************* Bit definition for ADC_CDR register ********************/
2350#define ADC_CDR_DATA1_Pos (0U)
2351#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
2352#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
2353#define ADC_CDR_DATA2_Pos (16U)
2354#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
2355#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
2357/* Legacy defines */
2358#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
2359#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
2360
2361/******************************************************************************/
2362/* */
2363/* Controller Area Network */
2364/* */
2365/******************************************************************************/
2367/******************* Bit definition for CAN_MCR register ********************/
2368#define CAN_MCR_INRQ_Pos (0U)
2369#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
2370#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
2371#define CAN_MCR_SLEEP_Pos (1U)
2372#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
2373#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
2374#define CAN_MCR_TXFP_Pos (2U)
2375#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
2376#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
2377#define CAN_MCR_RFLM_Pos (3U)
2378#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
2379#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
2380#define CAN_MCR_NART_Pos (4U)
2381#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
2382#define CAN_MCR_NART CAN_MCR_NART_Msk
2383#define CAN_MCR_AWUM_Pos (5U)
2384#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
2385#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
2386#define CAN_MCR_ABOM_Pos (6U)
2387#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
2388#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
2389#define CAN_MCR_TTCM_Pos (7U)
2390#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
2391#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
2392#define CAN_MCR_RESET_Pos (15U)
2393#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
2394#define CAN_MCR_RESET CAN_MCR_RESET_Msk
2396/******************* Bit definition for CAN_MSR register ********************/
2397#define CAN_MSR_INAK_Pos (0U)
2398#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
2399#define CAN_MSR_INAK CAN_MSR_INAK_Msk
2400#define CAN_MSR_SLAK_Pos (1U)
2401#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
2402#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
2403#define CAN_MSR_ERRI_Pos (2U)
2404#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
2405#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
2406#define CAN_MSR_WKUI_Pos (3U)
2407#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
2408#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
2409#define CAN_MSR_SLAKI_Pos (4U)
2410#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
2411#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
2412#define CAN_MSR_TXM_Pos (8U)
2413#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
2414#define CAN_MSR_TXM CAN_MSR_TXM_Msk
2415#define CAN_MSR_RXM_Pos (9U)
2416#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
2417#define CAN_MSR_RXM CAN_MSR_RXM_Msk
2418#define CAN_MSR_SAMP_Pos (10U)
2419#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
2420#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
2421#define CAN_MSR_RX_Pos (11U)
2422#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
2423#define CAN_MSR_RX CAN_MSR_RX_Msk
2425/******************* Bit definition for CAN_TSR register ********************/
2426#define CAN_TSR_RQCP0_Pos (0U)
2427#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
2428#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
2429#define CAN_TSR_TXOK0_Pos (1U)
2430#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
2431#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
2432#define CAN_TSR_ALST0_Pos (2U)
2433#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
2434#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
2435#define CAN_TSR_TERR0_Pos (3U)
2436#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
2437#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
2438#define CAN_TSR_ABRQ0_Pos (7U)
2439#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
2440#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
2441#define CAN_TSR_RQCP1_Pos (8U)
2442#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2443#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2444#define CAN_TSR_TXOK1_Pos (9U)
2445#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2446#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2447#define CAN_TSR_ALST1_Pos (10U)
2448#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2449#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2450#define CAN_TSR_TERR1_Pos (11U)
2451#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2452#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2453#define CAN_TSR_ABRQ1_Pos (15U)
2454#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2455#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2456#define CAN_TSR_RQCP2_Pos (16U)
2457#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2458#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2459#define CAN_TSR_TXOK2_Pos (17U)
2460#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2461#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2462#define CAN_TSR_ALST2_Pos (18U)
2463#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2464#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2465#define CAN_TSR_TERR2_Pos (19U)
2466#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2467#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2468#define CAN_TSR_ABRQ2_Pos (23U)
2469#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2470#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2471#define CAN_TSR_CODE_Pos (24U)
2472#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2473#define CAN_TSR_CODE CAN_TSR_CODE_Msk
2475#define CAN_TSR_TME_Pos (26U)
2476#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2477#define CAN_TSR_TME CAN_TSR_TME_Msk
2478#define CAN_TSR_TME0_Pos (26U)
2479#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2480#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2481#define CAN_TSR_TME1_Pos (27U)
2482#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2483#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2484#define CAN_TSR_TME2_Pos (28U)
2485#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2486#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2488#define CAN_TSR_LOW_Pos (29U)
2489#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2490#define CAN_TSR_LOW CAN_TSR_LOW_Msk
2491#define CAN_TSR_LOW0_Pos (29U)
2492#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2493#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2494#define CAN_TSR_LOW1_Pos (30U)
2495#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2496#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2497#define CAN_TSR_LOW2_Pos (31U)
2498#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2499#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2501/******************* Bit definition for CAN_RF0R register *******************/
2502#define CAN_RF0R_FMP0_Pos (0U)
2503#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2504#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2505#define CAN_RF0R_FULL0_Pos (3U)
2506#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2507#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2508#define CAN_RF0R_FOVR0_Pos (4U)
2509#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2510#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2511#define CAN_RF0R_RFOM0_Pos (5U)
2512#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2513#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2515/******************* Bit definition for CAN_RF1R register *******************/
2516#define CAN_RF1R_FMP1_Pos (0U)
2517#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2518#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2519#define CAN_RF1R_FULL1_Pos (3U)
2520#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2521#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2522#define CAN_RF1R_FOVR1_Pos (4U)
2523#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2524#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2525#define CAN_RF1R_RFOM1_Pos (5U)
2526#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2527#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2529/******************** Bit definition for CAN_IER register *******************/
2530#define CAN_IER_TMEIE_Pos (0U)
2531#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2532#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2533#define CAN_IER_FMPIE0_Pos (1U)
2534#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2535#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2536#define CAN_IER_FFIE0_Pos (2U)
2537#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2538#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2539#define CAN_IER_FOVIE0_Pos (3U)
2540#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2541#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2542#define CAN_IER_FMPIE1_Pos (4U)
2543#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2544#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2545#define CAN_IER_FFIE1_Pos (5U)
2546#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2547#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2548#define CAN_IER_FOVIE1_Pos (6U)
2549#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2550#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2551#define CAN_IER_EWGIE_Pos (8U)
2552#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2553#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2554#define CAN_IER_EPVIE_Pos (9U)
2555#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2556#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2557#define CAN_IER_BOFIE_Pos (10U)
2558#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2559#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2560#define CAN_IER_LECIE_Pos (11U)
2561#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2562#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2563#define CAN_IER_ERRIE_Pos (15U)
2564#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2565#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2566#define CAN_IER_WKUIE_Pos (16U)
2567#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2568#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2569#define CAN_IER_SLKIE_Pos (17U)
2570#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2571#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2573/******************** Bit definition for CAN_ESR register *******************/
2574#define CAN_ESR_EWGF_Pos (0U)
2575#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2576#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2577#define CAN_ESR_EPVF_Pos (1U)
2578#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2579#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2580#define CAN_ESR_BOFF_Pos (2U)
2581#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2582#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2584#define CAN_ESR_LEC_Pos (4U)
2585#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2586#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2587#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2588#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2589#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2591#define CAN_ESR_TEC_Pos (16U)
2592#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2593#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2594#define CAN_ESR_REC_Pos (24U)
2595#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2596#define CAN_ESR_REC CAN_ESR_REC_Msk
2598/******************* Bit definition for CAN_BTR register ********************/
2599#define CAN_BTR_BRP_Pos (0U)
2600#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2601#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2602#define CAN_BTR_TS1_Pos (16U)
2603#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2604#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2605#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2606#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2607#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2608#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2609#define CAN_BTR_TS2_Pos (20U)
2610#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2611#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2612#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2613#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2614#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2615#define CAN_BTR_SJW_Pos (24U)
2616#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2617#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2618#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2619#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2620#define CAN_BTR_LBKM_Pos (30U)
2621#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2622#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2623#define CAN_BTR_SILM_Pos (31U)
2624#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2625#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2628/****************** Bit definition for CAN_TI0R register ********************/
2629#define CAN_TI0R_TXRQ_Pos (0U)
2630#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2631#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2632#define CAN_TI0R_RTR_Pos (1U)
2633#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2634#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2635#define CAN_TI0R_IDE_Pos (2U)
2636#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2637#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2638#define CAN_TI0R_EXID_Pos (3U)
2639#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2640#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2641#define CAN_TI0R_STID_Pos (21U)
2642#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2643#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2645/****************** Bit definition for CAN_TDT0R register *******************/
2646#define CAN_TDT0R_DLC_Pos (0U)
2647#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2648#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2649#define CAN_TDT0R_TGT_Pos (8U)
2650#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2651#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2652#define CAN_TDT0R_TIME_Pos (16U)
2653#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2654#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2656/****************** Bit definition for CAN_TDL0R register *******************/
2657#define CAN_TDL0R_DATA0_Pos (0U)
2658#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2659#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2660#define CAN_TDL0R_DATA1_Pos (8U)
2661#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2662#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2663#define CAN_TDL0R_DATA2_Pos (16U)
2664#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2665#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2666#define CAN_TDL0R_DATA3_Pos (24U)
2667#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2668#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2670/****************** Bit definition for CAN_TDH0R register *******************/
2671#define CAN_TDH0R_DATA4_Pos (0U)
2672#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2673#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2674#define CAN_TDH0R_DATA5_Pos (8U)
2675#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2676#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2677#define CAN_TDH0R_DATA6_Pos (16U)
2678#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2679#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2680#define CAN_TDH0R_DATA7_Pos (24U)
2681#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2682#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2684/******************* Bit definition for CAN_TI1R register *******************/
2685#define CAN_TI1R_TXRQ_Pos (0U)
2686#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2687#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2688#define CAN_TI1R_RTR_Pos (1U)
2689#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2690#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2691#define CAN_TI1R_IDE_Pos (2U)
2692#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2693#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2694#define CAN_TI1R_EXID_Pos (3U)
2695#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2696#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2697#define CAN_TI1R_STID_Pos (21U)
2698#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2699#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2701/******************* Bit definition for CAN_TDT1R register ******************/
2702#define CAN_TDT1R_DLC_Pos (0U)
2703#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2704#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2705#define CAN_TDT1R_TGT_Pos (8U)
2706#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2707#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2708#define CAN_TDT1R_TIME_Pos (16U)
2709#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2710#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2712/******************* Bit definition for CAN_TDL1R register ******************/
2713#define CAN_TDL1R_DATA0_Pos (0U)
2714#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2715#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2716#define CAN_TDL1R_DATA1_Pos (8U)
2717#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2718#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2719#define CAN_TDL1R_DATA2_Pos (16U)
2720#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2721#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2722#define CAN_TDL1R_DATA3_Pos (24U)
2723#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2724#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2726/******************* Bit definition for CAN_TDH1R register ******************/
2727#define CAN_TDH1R_DATA4_Pos (0U)
2728#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2729#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2730#define CAN_TDH1R_DATA5_Pos (8U)
2731#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2732#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2733#define CAN_TDH1R_DATA6_Pos (16U)
2734#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2735#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2736#define CAN_TDH1R_DATA7_Pos (24U)
2737#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2738#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2740/******************* Bit definition for CAN_TI2R register *******************/
2741#define CAN_TI2R_TXRQ_Pos (0U)
2742#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2743#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2744#define CAN_TI2R_RTR_Pos (1U)
2745#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2746#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2747#define CAN_TI2R_IDE_Pos (2U)
2748#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2749#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2750#define CAN_TI2R_EXID_Pos (3U)
2751#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2752#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2753#define CAN_TI2R_STID_Pos (21U)
2754#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2755#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2757/******************* Bit definition for CAN_TDT2R register ******************/
2758#define CAN_TDT2R_DLC_Pos (0U)
2759#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2760#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2761#define CAN_TDT2R_TGT_Pos (8U)
2762#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2763#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2764#define CAN_TDT2R_TIME_Pos (16U)
2765#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2766#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2768/******************* Bit definition for CAN_TDL2R register ******************/
2769#define CAN_TDL2R_DATA0_Pos (0U)
2770#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2771#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2772#define CAN_TDL2R_DATA1_Pos (8U)
2773#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2774#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2775#define CAN_TDL2R_DATA2_Pos (16U)
2776#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2777#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2778#define CAN_TDL2R_DATA3_Pos (24U)
2779#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2780#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2782/******************* Bit definition for CAN_TDH2R register ******************/
2783#define CAN_TDH2R_DATA4_Pos (0U)
2784#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2785#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2786#define CAN_TDH2R_DATA5_Pos (8U)
2787#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2788#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2789#define CAN_TDH2R_DATA6_Pos (16U)
2790#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2791#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2792#define CAN_TDH2R_DATA7_Pos (24U)
2793#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2794#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2796/******************* Bit definition for CAN_RI0R register *******************/
2797#define CAN_RI0R_RTR_Pos (1U)
2798#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2799#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2800#define CAN_RI0R_IDE_Pos (2U)
2801#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2802#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2803#define CAN_RI0R_EXID_Pos (3U)
2804#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2805#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2806#define CAN_RI0R_STID_Pos (21U)
2807#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2808#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2810/******************* Bit definition for CAN_RDT0R register ******************/
2811#define CAN_RDT0R_DLC_Pos (0U)
2812#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2813#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2814#define CAN_RDT0R_FMI_Pos (8U)
2815#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2816#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2817#define CAN_RDT0R_TIME_Pos (16U)
2818#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2819#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2821/******************* Bit definition for CAN_RDL0R register ******************/
2822#define CAN_RDL0R_DATA0_Pos (0U)
2823#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2824#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2825#define CAN_RDL0R_DATA1_Pos (8U)
2826#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2827#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2828#define CAN_RDL0R_DATA2_Pos (16U)
2829#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2830#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2831#define CAN_RDL0R_DATA3_Pos (24U)
2832#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2833#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2835/******************* Bit definition for CAN_RDH0R register ******************/
2836#define CAN_RDH0R_DATA4_Pos (0U)
2837#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2838#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2839#define CAN_RDH0R_DATA5_Pos (8U)
2840#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2841#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2842#define CAN_RDH0R_DATA6_Pos (16U)
2843#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2844#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2845#define CAN_RDH0R_DATA7_Pos (24U)
2846#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2847#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2849/******************* Bit definition for CAN_RI1R register *******************/
2850#define CAN_RI1R_RTR_Pos (1U)
2851#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2852#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2853#define CAN_RI1R_IDE_Pos (2U)
2854#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2855#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2856#define CAN_RI1R_EXID_Pos (3U)
2857#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2858#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2859#define CAN_RI1R_STID_Pos (21U)
2860#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2861#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2863/******************* Bit definition for CAN_RDT1R register ******************/
2864#define CAN_RDT1R_DLC_Pos (0U)
2865#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2866#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2867#define CAN_RDT1R_FMI_Pos (8U)
2868#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2869#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2870#define CAN_RDT1R_TIME_Pos (16U)
2871#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2872#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2874/******************* Bit definition for CAN_RDL1R register ******************/
2875#define CAN_RDL1R_DATA0_Pos (0U)
2876#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2877#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2878#define CAN_RDL1R_DATA1_Pos (8U)
2879#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2880#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2881#define CAN_RDL1R_DATA2_Pos (16U)
2882#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2883#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2884#define CAN_RDL1R_DATA3_Pos (24U)
2885#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2886#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2888/******************* Bit definition for CAN_RDH1R register ******************/
2889#define CAN_RDH1R_DATA4_Pos (0U)
2890#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2891#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2892#define CAN_RDH1R_DATA5_Pos (8U)
2893#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2894#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2895#define CAN_RDH1R_DATA6_Pos (16U)
2896#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2897#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2898#define CAN_RDH1R_DATA7_Pos (24U)
2899#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2900#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2903/******************* Bit definition for CAN_FMR register ********************/
2904#define CAN_FMR_FINIT ((uint8_t)0x01U)
2905#define CAN_FMR_CAN2SB_Pos (8U)
2906#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2907#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2909/******************* Bit definition for CAN_FM1R register *******************/
2910#define CAN_FM1R_FBM_Pos (0U)
2911#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
2912#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2913#define CAN_FM1R_FBM0_Pos (0U)
2914#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2915#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2916#define CAN_FM1R_FBM1_Pos (1U)
2917#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2918#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2919#define CAN_FM1R_FBM2_Pos (2U)
2920#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2921#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2922#define CAN_FM1R_FBM3_Pos (3U)
2923#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2924#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2925#define CAN_FM1R_FBM4_Pos (4U)
2926#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2927#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2928#define CAN_FM1R_FBM5_Pos (5U)
2929#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2930#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2931#define CAN_FM1R_FBM6_Pos (6U)
2932#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2933#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2934#define CAN_FM1R_FBM7_Pos (7U)
2935#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2936#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2937#define CAN_FM1R_FBM8_Pos (8U)
2938#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2939#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2940#define CAN_FM1R_FBM9_Pos (9U)
2941#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2942#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2943#define CAN_FM1R_FBM10_Pos (10U)
2944#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2945#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2946#define CAN_FM1R_FBM11_Pos (11U)
2947#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2948#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2949#define CAN_FM1R_FBM12_Pos (12U)
2950#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2951#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2952#define CAN_FM1R_FBM13_Pos (13U)
2953#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2954#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2956/******************* Bit definition for CAN_FS1R register *******************/
2957#define CAN_FS1R_FSC_Pos (0U)
2958#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
2959#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2960#define CAN_FS1R_FSC0_Pos (0U)
2961#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2962#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2963#define CAN_FS1R_FSC1_Pos (1U)
2964#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2965#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2966#define CAN_FS1R_FSC2_Pos (2U)
2967#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2968#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2969#define CAN_FS1R_FSC3_Pos (3U)
2970#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2971#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2972#define CAN_FS1R_FSC4_Pos (4U)
2973#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2974#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2975#define CAN_FS1R_FSC5_Pos (5U)
2976#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2977#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2978#define CAN_FS1R_FSC6_Pos (6U)
2979#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2980#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2981#define CAN_FS1R_FSC7_Pos (7U)
2982#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2983#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2984#define CAN_FS1R_FSC8_Pos (8U)
2985#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2986#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2987#define CAN_FS1R_FSC9_Pos (9U)
2988#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2989#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2990#define CAN_FS1R_FSC10_Pos (10U)
2991#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2992#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2993#define CAN_FS1R_FSC11_Pos (11U)
2994#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2995#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2996#define CAN_FS1R_FSC12_Pos (12U)
2997#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2998#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2999#define CAN_FS1R_FSC13_Pos (13U)
3000#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
3001#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
3003/****************** Bit definition for CAN_FFA1R register *******************/
3004#define CAN_FFA1R_FFA_Pos (0U)
3005#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
3006#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
3007#define CAN_FFA1R_FFA0_Pos (0U)
3008#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
3009#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
3010#define CAN_FFA1R_FFA1_Pos (1U)
3011#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
3012#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
3013#define CAN_FFA1R_FFA2_Pos (2U)
3014#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
3015#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
3016#define CAN_FFA1R_FFA3_Pos (3U)
3017#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
3018#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
3019#define CAN_FFA1R_FFA4_Pos (4U)
3020#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
3021#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
3022#define CAN_FFA1R_FFA5_Pos (5U)
3023#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
3024#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
3025#define CAN_FFA1R_FFA6_Pos (6U)
3026#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
3027#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
3028#define CAN_FFA1R_FFA7_Pos (7U)
3029#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
3030#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
3031#define CAN_FFA1R_FFA8_Pos (8U)
3032#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
3033#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
3034#define CAN_FFA1R_FFA9_Pos (9U)
3035#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
3036#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
3037#define CAN_FFA1R_FFA10_Pos (10U)
3038#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
3039#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
3040#define CAN_FFA1R_FFA11_Pos (11U)
3041#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
3042#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
3043#define CAN_FFA1R_FFA12_Pos (12U)
3044#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
3045#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
3046#define CAN_FFA1R_FFA13_Pos (13U)
3047#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
3048#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
3050/******************* Bit definition for CAN_FA1R register *******************/
3051#define CAN_FA1R_FACT_Pos (0U)
3052#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
3053#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
3054#define CAN_FA1R_FACT0_Pos (0U)
3055#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
3056#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
3057#define CAN_FA1R_FACT1_Pos (1U)
3058#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
3059#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
3060#define CAN_FA1R_FACT2_Pos (2U)
3061#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
3062#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
3063#define CAN_FA1R_FACT3_Pos (3U)
3064#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
3065#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
3066#define CAN_FA1R_FACT4_Pos (4U)
3067#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
3068#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
3069#define CAN_FA1R_FACT5_Pos (5U)
3070#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
3071#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
3072#define CAN_FA1R_FACT6_Pos (6U)
3073#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
3074#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
3075#define CAN_FA1R_FACT7_Pos (7U)
3076#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
3077#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
3078#define CAN_FA1R_FACT8_Pos (8U)
3079#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
3080#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
3081#define CAN_FA1R_FACT9_Pos (9U)
3082#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
3083#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
3084#define CAN_FA1R_FACT10_Pos (10U)
3085#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
3086#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
3087#define CAN_FA1R_FACT11_Pos (11U)
3088#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
3089#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
3090#define CAN_FA1R_FACT12_Pos (12U)
3091#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
3092#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
3093#define CAN_FA1R_FACT13_Pos (13U)
3094#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
3095#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
3097/******************* Bit definition for CAN_F0R1 register *******************/
3098#define CAN_F0R1_FB0_Pos (0U)
3099#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
3100#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
3101#define CAN_F0R1_FB1_Pos (1U)
3102#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
3103#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
3104#define CAN_F0R1_FB2_Pos (2U)
3105#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
3106#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
3107#define CAN_F0R1_FB3_Pos (3U)
3108#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
3109#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
3110#define CAN_F0R1_FB4_Pos (4U)
3111#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
3112#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
3113#define CAN_F0R1_FB5_Pos (5U)
3114#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
3115#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
3116#define CAN_F0R1_FB6_Pos (6U)
3117#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
3118#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
3119#define CAN_F0R1_FB7_Pos (7U)
3120#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
3121#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
3122#define CAN_F0R1_FB8_Pos (8U)
3123#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
3124#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
3125#define CAN_F0R1_FB9_Pos (9U)
3126#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
3127#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
3128#define CAN_F0R1_FB10_Pos (10U)
3129#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
3130#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
3131#define CAN_F0R1_FB11_Pos (11U)
3132#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
3133#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
3134#define CAN_F0R1_FB12_Pos (12U)
3135#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
3136#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
3137#define CAN_F0R1_FB13_Pos (13U)
3138#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
3139#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
3140#define CAN_F0R1_FB14_Pos (14U)
3141#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
3142#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
3143#define CAN_F0R1_FB15_Pos (15U)
3144#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
3145#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
3146#define CAN_F0R1_FB16_Pos (16U)
3147#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
3148#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
3149#define CAN_F0R1_FB17_Pos (17U)
3150#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
3151#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
3152#define CAN_F0R1_FB18_Pos (18U)
3153#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
3154#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
3155#define CAN_F0R1_FB19_Pos (19U)
3156#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
3157#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
3158#define CAN_F0R1_FB20_Pos (20U)
3159#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
3160#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
3161#define CAN_F0R1_FB21_Pos (21U)
3162#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
3163#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
3164#define CAN_F0R1_FB22_Pos (22U)
3165#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
3166#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
3167#define CAN_F0R1_FB23_Pos (23U)
3168#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
3169#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
3170#define CAN_F0R1_FB24_Pos (24U)
3171#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
3172#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
3173#define CAN_F0R1_FB25_Pos (25U)
3174#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
3175#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
3176#define CAN_F0R1_FB26_Pos (26U)
3177#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
3178#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
3179#define CAN_F0R1_FB27_Pos (27U)
3180#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
3181#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
3182#define CAN_F0R1_FB28_Pos (28U)
3183#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
3184#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
3185#define CAN_F0R1_FB29_Pos (29U)
3186#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
3187#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
3188#define CAN_F0R1_FB30_Pos (30U)
3189#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
3190#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
3191#define CAN_F0R1_FB31_Pos (31U)
3192#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
3193#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
3195/******************* Bit definition for CAN_F1R1 register *******************/
3196#define CAN_F1R1_FB0_Pos (0U)
3197#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
3198#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
3199#define CAN_F1R1_FB1_Pos (1U)
3200#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
3201#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
3202#define CAN_F1R1_FB2_Pos (2U)
3203#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
3204#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
3205#define CAN_F1R1_FB3_Pos (3U)
3206#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
3207#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
3208#define CAN_F1R1_FB4_Pos (4U)
3209#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
3210#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
3211#define CAN_F1R1_FB5_Pos (5U)
3212#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
3213#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
3214#define CAN_F1R1_FB6_Pos (6U)
3215#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
3216#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
3217#define CAN_F1R1_FB7_Pos (7U)
3218#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
3219#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
3220#define CAN_F1R1_FB8_Pos (8U)
3221#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
3222#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
3223#define CAN_F1R1_FB9_Pos (9U)
3224#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
3225#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
3226#define CAN_F1R1_FB10_Pos (10U)
3227#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
3228#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
3229#define CAN_F1R1_FB11_Pos (11U)
3230#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
3231#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
3232#define CAN_F1R1_FB12_Pos (12U)
3233#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
3234#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
3235#define CAN_F1R1_FB13_Pos (13U)
3236#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
3237#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
3238#define CAN_F1R1_FB14_Pos (14U)
3239#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
3240#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
3241#define CAN_F1R1_FB15_Pos (15U)
3242#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
3243#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
3244#define CAN_F1R1_FB16_Pos (16U)
3245#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
3246#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
3247#define CAN_F1R1_FB17_Pos (17U)
3248#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
3249#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
3250#define CAN_F1R1_FB18_Pos (18U)
3251#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
3252#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
3253#define CAN_F1R1_FB19_Pos (19U)
3254#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
3255#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
3256#define CAN_F1R1_FB20_Pos (20U)
3257#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
3258#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
3259#define CAN_F1R1_FB21_Pos (21U)
3260#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
3261#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
3262#define CAN_F1R1_FB22_Pos (22U)
3263#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
3264#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
3265#define CAN_F1R1_FB23_Pos (23U)
3266#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
3267#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
3268#define CAN_F1R1_FB24_Pos (24U)
3269#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
3270#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
3271#define CAN_F1R1_FB25_Pos (25U)
3272#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
3273#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
3274#define CAN_F1R1_FB26_Pos (26U)
3275#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
3276#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
3277#define CAN_F1R1_FB27_Pos (27U)
3278#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3279#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3280#define CAN_F1R1_FB28_Pos (28U)
3281#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3282#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3283#define CAN_F1R1_FB29_Pos (29U)
3284#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3285#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3286#define CAN_F1R1_FB30_Pos (30U)
3287#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3288#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3289#define CAN_F1R1_FB31_Pos (31U)
3290#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3291#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3293/******************* Bit definition for CAN_F2R1 register *******************/
3294#define CAN_F2R1_FB0_Pos (0U)
3295#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
3296#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
3297#define CAN_F2R1_FB1_Pos (1U)
3298#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
3299#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
3300#define CAN_F2R1_FB2_Pos (2U)
3301#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
3302#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
3303#define CAN_F2R1_FB3_Pos (3U)
3304#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
3305#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
3306#define CAN_F2R1_FB4_Pos (4U)
3307#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
3308#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
3309#define CAN_F2R1_FB5_Pos (5U)
3310#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
3311#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
3312#define CAN_F2R1_FB6_Pos (6U)
3313#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
3314#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
3315#define CAN_F2R1_FB7_Pos (7U)
3316#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
3317#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
3318#define CAN_F2R1_FB8_Pos (8U)
3319#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
3320#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
3321#define CAN_F2R1_FB9_Pos (9U)
3322#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
3323#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
3324#define CAN_F2R1_FB10_Pos (10U)
3325#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
3326#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
3327#define CAN_F2R1_FB11_Pos (11U)
3328#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
3329#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
3330#define CAN_F2R1_FB12_Pos (12U)
3331#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
3332#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
3333#define CAN_F2R1_FB13_Pos (13U)
3334#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
3335#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
3336#define CAN_F2R1_FB14_Pos (14U)
3337#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
3338#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
3339#define CAN_F2R1_FB15_Pos (15U)
3340#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
3341#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
3342#define CAN_F2R1_FB16_Pos (16U)
3343#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
3344#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
3345#define CAN_F2R1_FB17_Pos (17U)
3346#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
3347#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
3348#define CAN_F2R1_FB18_Pos (18U)
3349#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
3350#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
3351#define CAN_F2R1_FB19_Pos (19U)
3352#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
3353#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
3354#define CAN_F2R1_FB20_Pos (20U)
3355#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
3356#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
3357#define CAN_F2R1_FB21_Pos (21U)
3358#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
3359#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
3360#define CAN_F2R1_FB22_Pos (22U)
3361#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
3362#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
3363#define CAN_F2R1_FB23_Pos (23U)
3364#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
3365#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
3366#define CAN_F2R1_FB24_Pos (24U)
3367#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
3368#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
3369#define CAN_F2R1_FB25_Pos (25U)
3370#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
3371#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
3372#define CAN_F2R1_FB26_Pos (26U)
3373#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
3374#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
3375#define CAN_F2R1_FB27_Pos (27U)
3376#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
3377#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3378#define CAN_F2R1_FB28_Pos (28U)
3379#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3380#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3381#define CAN_F2R1_FB29_Pos (29U)
3382#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3383#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3384#define CAN_F2R1_FB30_Pos (30U)
3385#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3386#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3387#define CAN_F2R1_FB31_Pos (31U)
3388#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3389#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3391/******************* Bit definition for CAN_F3R1 register *******************/
3392#define CAN_F3R1_FB0_Pos (0U)
3393#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3394#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3395#define CAN_F3R1_FB1_Pos (1U)
3396#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3397#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3398#define CAN_F3R1_FB2_Pos (2U)
3399#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3400#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3401#define CAN_F3R1_FB3_Pos (3U)
3402#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3403#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3404#define CAN_F3R1_FB4_Pos (4U)
3405#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3406#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3407#define CAN_F3R1_FB5_Pos (5U)
3408#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3409#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3410#define CAN_F3R1_FB6_Pos (6U)
3411#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3412#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3413#define CAN_F3R1_FB7_Pos (7U)
3414#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3415#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3416#define CAN_F3R1_FB8_Pos (8U)
3417#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3418#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3419#define CAN_F3R1_FB9_Pos (9U)
3420#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3421#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3422#define CAN_F3R1_FB10_Pos (10U)
3423#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3424#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3425#define CAN_F3R1_FB11_Pos (11U)
3426#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3427#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3428#define CAN_F3R1_FB12_Pos (12U)
3429#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3430#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3431#define CAN_F3R1_FB13_Pos (13U)
3432#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3433#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3434#define CAN_F3R1_FB14_Pos (14U)
3435#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3436#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3437#define CAN_F3R1_FB15_Pos (15U)
3438#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3439#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3440#define CAN_F3R1_FB16_Pos (16U)
3441#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3442#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3443#define CAN_F3R1_FB17_Pos (17U)
3444#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3445#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3446#define CAN_F3R1_FB18_Pos (18U)
3447#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3448#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3449#define CAN_F3R1_FB19_Pos (19U)
3450#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3451#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3452#define CAN_F3R1_FB20_Pos (20U)
3453#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3454#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3455#define CAN_F3R1_FB21_Pos (21U)
3456#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3457#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3458#define CAN_F3R1_FB22_Pos (22U)
3459#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3460#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3461#define CAN_F3R1_FB23_Pos (23U)
3462#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3463#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3464#define CAN_F3R1_FB24_Pos (24U)
3465#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3466#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3467#define CAN_F3R1_FB25_Pos (25U)
3468#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3469#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3470#define CAN_F3R1_FB26_Pos (26U)
3471#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3472#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3473#define CAN_F3R1_FB27_Pos (27U)
3474#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3475#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3476#define CAN_F3R1_FB28_Pos (28U)
3477#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3478#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3479#define CAN_F3R1_FB29_Pos (29U)
3480#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3481#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3482#define CAN_F3R1_FB30_Pos (30U)
3483#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3484#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3485#define CAN_F3R1_FB31_Pos (31U)
3486#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3487#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3489/******************* Bit definition for CAN_F4R1 register *******************/
3490#define CAN_F4R1_FB0_Pos (0U)
3491#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3492#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3493#define CAN_F4R1_FB1_Pos (1U)
3494#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3495#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3496#define CAN_F4R1_FB2_Pos (2U)
3497#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3498#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3499#define CAN_F4R1_FB3_Pos (3U)
3500#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3501#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3502#define CAN_F4R1_FB4_Pos (4U)
3503#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3504#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3505#define CAN_F4R1_FB5_Pos (5U)
3506#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3507#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3508#define CAN_F4R1_FB6_Pos (6U)
3509#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3510#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3511#define CAN_F4R1_FB7_Pos (7U)
3512#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3513#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3514#define CAN_F4R1_FB8_Pos (8U)
3515#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3516#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3517#define CAN_F4R1_FB9_Pos (9U)
3518#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3519#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3520#define CAN_F4R1_FB10_Pos (10U)
3521#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3522#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3523#define CAN_F4R1_FB11_Pos (11U)
3524#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3525#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3526#define CAN_F4R1_FB12_Pos (12U)
3527#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3528#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3529#define CAN_F4R1_FB13_Pos (13U)
3530#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3531#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3532#define CAN_F4R1_FB14_Pos (14U)
3533#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3534#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3535#define CAN_F4R1_FB15_Pos (15U)
3536#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3537#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3538#define CAN_F4R1_FB16_Pos (16U)
3539#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3540#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3541#define CAN_F4R1_FB17_Pos (17U)
3542#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3543#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3544#define CAN_F4R1_FB18_Pos (18U)
3545#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3546#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3547#define CAN_F4R1_FB19_Pos (19U)
3548#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3549#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3550#define CAN_F4R1_FB20_Pos (20U)
3551#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3552#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3553#define CAN_F4R1_FB21_Pos (21U)
3554#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3555#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3556#define CAN_F4R1_FB22_Pos (22U)
3557#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3558#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3559#define CAN_F4R1_FB23_Pos (23U)
3560#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3561#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3562#define CAN_F4R1_FB24_Pos (24U)
3563#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3564#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3565#define CAN_F4R1_FB25_Pos (25U)
3566#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3567#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3568#define CAN_F4R1_FB26_Pos (26U)
3569#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3570#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3571#define CAN_F4R1_FB27_Pos (27U)
3572#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3573#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3574#define CAN_F4R1_FB28_Pos (28U)
3575#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3576#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3577#define CAN_F4R1_FB29_Pos (29U)
3578#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3579#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3580#define CAN_F4R1_FB30_Pos (30U)
3581#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3582#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3583#define CAN_F4R1_FB31_Pos (31U)
3584#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3585#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3587/******************* Bit definition for CAN_F5R1 register *******************/
3588#define CAN_F5R1_FB0_Pos (0U)
3589#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3590#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3591#define CAN_F5R1_FB1_Pos (1U)
3592#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3593#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3594#define CAN_F5R1_FB2_Pos (2U)
3595#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3596#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3597#define CAN_F5R1_FB3_Pos (3U)
3598#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3599#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3600#define CAN_F5R1_FB4_Pos (4U)
3601#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3602#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3603#define CAN_F5R1_FB5_Pos (5U)
3604#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3605#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3606#define CAN_F5R1_FB6_Pos (6U)
3607#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3608#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3609#define CAN_F5R1_FB7_Pos (7U)
3610#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3611#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3612#define CAN_F5R1_FB8_Pos (8U)
3613#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3614#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3615#define CAN_F5R1_FB9_Pos (9U)
3616#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3617#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3618#define CAN_F5R1_FB10_Pos (10U)
3619#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3620#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3621#define CAN_F5R1_FB11_Pos (11U)
3622#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3623#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3624#define CAN_F5R1_FB12_Pos (12U)
3625#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3626#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3627#define CAN_F5R1_FB13_Pos (13U)
3628#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3629#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3630#define CAN_F5R1_FB14_Pos (14U)
3631#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3632#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3633#define CAN_F5R1_FB15_Pos (15U)
3634#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3635#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3636#define CAN_F5R1_FB16_Pos (16U)
3637#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3638#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3639#define CAN_F5R1_FB17_Pos (17U)
3640#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3641#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3642#define CAN_F5R1_FB18_Pos (18U)
3643#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3644#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3645#define CAN_F5R1_FB19_Pos (19U)
3646#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3647#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3648#define CAN_F5R1_FB20_Pos (20U)
3649#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3650#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3651#define CAN_F5R1_FB21_Pos (21U)
3652#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3653#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3654#define CAN_F5R1_FB22_Pos (22U)
3655#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3656#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3657#define CAN_F5R1_FB23_Pos (23U)
3658#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3659#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3660#define CAN_F5R1_FB24_Pos (24U)
3661#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3662#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3663#define CAN_F5R1_FB25_Pos (25U)
3664#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3665#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3666#define CAN_F5R1_FB26_Pos (26U)
3667#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3668#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3669#define CAN_F5R1_FB27_Pos (27U)
3670#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3671#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3672#define CAN_F5R1_FB28_Pos (28U)
3673#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3674#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3675#define CAN_F5R1_FB29_Pos (29U)
3676#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3677#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3678#define CAN_F5R1_FB30_Pos (30U)
3679#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3680#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3681#define CAN_F5R1_FB31_Pos (31U)
3682#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3683#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3685/******************* Bit definition for CAN_F6R1 register *******************/
3686#define CAN_F6R1_FB0_Pos (0U)
3687#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3688#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3689#define CAN_F6R1_FB1_Pos (1U)
3690#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3691#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3692#define CAN_F6R1_FB2_Pos (2U)
3693#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3694#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3695#define CAN_F6R1_FB3_Pos (3U)
3696#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3697#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3698#define CAN_F6R1_FB4_Pos (4U)
3699#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3700#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3701#define CAN_F6R1_FB5_Pos (5U)
3702#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3703#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3704#define CAN_F6R1_FB6_Pos (6U)
3705#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3706#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3707#define CAN_F6R1_FB7_Pos (7U)
3708#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3709#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3710#define CAN_F6R1_FB8_Pos (8U)
3711#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3712#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3713#define CAN_F6R1_FB9_Pos (9U)
3714#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3715#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3716#define CAN_F6R1_FB10_Pos (10U)
3717#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3718#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3719#define CAN_F6R1_FB11_Pos (11U)
3720#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3721#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3722#define CAN_F6R1_FB12_Pos (12U)
3723#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3724#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3725#define CAN_F6R1_FB13_Pos (13U)
3726#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3727#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3728#define CAN_F6R1_FB14_Pos (14U)
3729#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3730#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3731#define CAN_F6R1_FB15_Pos (15U)
3732#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3733#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3734#define CAN_F6R1_FB16_Pos (16U)
3735#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3736#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3737#define CAN_F6R1_FB17_Pos (17U)
3738#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3739#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3740#define CAN_F6R1_FB18_Pos (18U)
3741#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3742#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3743#define CAN_F6R1_FB19_Pos (19U)
3744#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3745#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3746#define CAN_F6R1_FB20_Pos (20U)
3747#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3748#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3749#define CAN_F6R1_FB21_Pos (21U)
3750#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3751#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3752#define CAN_F6R1_FB22_Pos (22U)
3753#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3754#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3755#define CAN_F6R1_FB23_Pos (23U)
3756#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3757#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3758#define CAN_F6R1_FB24_Pos (24U)
3759#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3760#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3761#define CAN_F6R1_FB25_Pos (25U)
3762#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3763#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3764#define CAN_F6R1_FB26_Pos (26U)
3765#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3766#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3767#define CAN_F6R1_FB27_Pos (27U)
3768#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3769#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3770#define CAN_F6R1_FB28_Pos (28U)
3771#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3772#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3773#define CAN_F6R1_FB29_Pos (29U)
3774#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3775#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3776#define CAN_F6R1_FB30_Pos (30U)
3777#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3778#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3779#define CAN_F6R1_FB31_Pos (31U)
3780#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3781#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3783/******************* Bit definition for CAN_F7R1 register *******************/
3784#define CAN_F7R1_FB0_Pos (0U)
3785#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3786#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3787#define CAN_F7R1_FB1_Pos (1U)
3788#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3789#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3790#define CAN_F7R1_FB2_Pos (2U)
3791#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3792#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3793#define CAN_F7R1_FB3_Pos (3U)
3794#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3795#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3796#define CAN_F7R1_FB4_Pos (4U)
3797#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3798#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3799#define CAN_F7R1_FB5_Pos (5U)
3800#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3801#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3802#define CAN_F7R1_FB6_Pos (6U)
3803#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3804#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3805#define CAN_F7R1_FB7_Pos (7U)
3806#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3807#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3808#define CAN_F7R1_FB8_Pos (8U)
3809#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3810#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3811#define CAN_F7R1_FB9_Pos (9U)
3812#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3813#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3814#define CAN_F7R1_FB10_Pos (10U)
3815#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3816#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3817#define CAN_F7R1_FB11_Pos (11U)
3818#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3819#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3820#define CAN_F7R1_FB12_Pos (12U)
3821#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3822#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3823#define CAN_F7R1_FB13_Pos (13U)
3824#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3825#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3826#define CAN_F7R1_FB14_Pos (14U)
3827#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3828#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3829#define CAN_F7R1_FB15_Pos (15U)
3830#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3831#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3832#define CAN_F7R1_FB16_Pos (16U)
3833#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3834#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3835#define CAN_F7R1_FB17_Pos (17U)
3836#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3837#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3838#define CAN_F7R1_FB18_Pos (18U)
3839#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3840#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3841#define CAN_F7R1_FB19_Pos (19U)
3842#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3843#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3844#define CAN_F7R1_FB20_Pos (20U)
3845#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3846#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3847#define CAN_F7R1_FB21_Pos (21U)
3848#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3849#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3850#define CAN_F7R1_FB22_Pos (22U)
3851#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3852#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3853#define CAN_F7R1_FB23_Pos (23U)
3854#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3855#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3856#define CAN_F7R1_FB24_Pos (24U)
3857#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3858#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3859#define CAN_F7R1_FB25_Pos (25U)
3860#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3861#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3862#define CAN_F7R1_FB26_Pos (26U)
3863#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3864#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3865#define CAN_F7R1_FB27_Pos (27U)
3866#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3867#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3868#define CAN_F7R1_FB28_Pos (28U)
3869#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3870#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3871#define CAN_F7R1_FB29_Pos (29U)
3872#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3873#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3874#define CAN_F7R1_FB30_Pos (30U)
3875#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3876#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3877#define CAN_F7R1_FB31_Pos (31U)
3878#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3879#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3881/******************* Bit definition for CAN_F8R1 register *******************/
3882#define CAN_F8R1_FB0_Pos (0U)
3883#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3884#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3885#define CAN_F8R1_FB1_Pos (1U)
3886#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3887#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3888#define CAN_F8R1_FB2_Pos (2U)
3889#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3890#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3891#define CAN_F8R1_FB3_Pos (3U)
3892#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3893#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3894#define CAN_F8R1_FB4_Pos (4U)
3895#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3896#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3897#define CAN_F8R1_FB5_Pos (5U)
3898#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3899#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3900#define CAN_F8R1_FB6_Pos (6U)
3901#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3902#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3903#define CAN_F8R1_FB7_Pos (7U)
3904#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3905#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3906#define CAN_F8R1_FB8_Pos (8U)
3907#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3908#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3909#define CAN_F8R1_FB9_Pos (9U)
3910#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3911#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3912#define CAN_F8R1_FB10_Pos (10U)
3913#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3914#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3915#define CAN_F8R1_FB11_Pos (11U)
3916#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3917#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3918#define CAN_F8R1_FB12_Pos (12U)
3919#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3920#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3921#define CAN_F8R1_FB13_Pos (13U)
3922#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3923#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3924#define CAN_F8R1_FB14_Pos (14U)
3925#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3926#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3927#define CAN_F8R1_FB15_Pos (15U)
3928#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3929#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3930#define CAN_F8R1_FB16_Pos (16U)
3931#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3932#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3933#define CAN_F8R1_FB17_Pos (17U)
3934#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3935#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3936#define CAN_F8R1_FB18_Pos (18U)
3937#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3938#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3939#define CAN_F8R1_FB19_Pos (19U)
3940#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3941#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3942#define CAN_F8R1_FB20_Pos (20U)
3943#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3944#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3945#define CAN_F8R1_FB21_Pos (21U)
3946#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3947#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3948#define CAN_F8R1_FB22_Pos (22U)
3949#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3950#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3951#define CAN_F8R1_FB23_Pos (23U)
3952#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3953#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3954#define CAN_F8R1_FB24_Pos (24U)
3955#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3956#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3957#define CAN_F8R1_FB25_Pos (25U)
3958#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3959#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3960#define CAN_F8R1_FB26_Pos (26U)
3961#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3962#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3963#define CAN_F8R1_FB27_Pos (27U)
3964#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3965#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3966#define CAN_F8R1_FB28_Pos (28U)
3967#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3968#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3969#define CAN_F8R1_FB29_Pos (29U)
3970#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3971#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3972#define CAN_F8R1_FB30_Pos (30U)
3973#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3974#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3975#define CAN_F8R1_FB31_Pos (31U)
3976#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3977#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3979/******************* Bit definition for CAN_F9R1 register *******************/
3980#define CAN_F9R1_FB0_Pos (0U)
3981#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3982#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3983#define CAN_F9R1_FB1_Pos (1U)
3984#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3985#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3986#define CAN_F9R1_FB2_Pos (2U)
3987#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3988#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3989#define CAN_F9R1_FB3_Pos (3U)
3990#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3991#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3992#define CAN_F9R1_FB4_Pos (4U)
3993#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3994#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3995#define CAN_F9R1_FB5_Pos (5U)
3996#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3997#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3998#define CAN_F9R1_FB6_Pos (6U)
3999#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
4000#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
4001#define CAN_F9R1_FB7_Pos (7U)
4002#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
4003#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
4004#define CAN_F9R1_FB8_Pos (8U)
4005#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
4006#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
4007#define CAN_F9R1_FB9_Pos (9U)
4008#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
4009#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
4010#define CAN_F9R1_FB10_Pos (10U)
4011#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
4012#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
4013#define CAN_F9R1_FB11_Pos (11U)
4014#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
4015#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
4016#define CAN_F9R1_FB12_Pos (12U)
4017#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
4018#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
4019#define CAN_F9R1_FB13_Pos (13U)
4020#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
4021#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
4022#define CAN_F9R1_FB14_Pos (14U)
4023#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
4024#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
4025#define CAN_F9R1_FB15_Pos (15U)
4026#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
4027#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
4028#define CAN_F9R1_FB16_Pos (16U)
4029#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
4030#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
4031#define CAN_F9R1_FB17_Pos (17U)
4032#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
4033#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
4034#define CAN_F9R1_FB18_Pos (18U)
4035#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
4036#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
4037#define CAN_F9R1_FB19_Pos (19U)
4038#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
4039#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
4040#define CAN_F9R1_FB20_Pos (20U)
4041#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
4042#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
4043#define CAN_F9R1_FB21_Pos (21U)
4044#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
4045#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
4046#define CAN_F9R1_FB22_Pos (22U)
4047#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
4048#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
4049#define CAN_F9R1_FB23_Pos (23U)
4050#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
4051#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
4052#define CAN_F9R1_FB24_Pos (24U)
4053#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
4054#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
4055#define CAN_F9R1_FB25_Pos (25U)
4056#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
4057#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
4058#define CAN_F9R1_FB26_Pos (26U)
4059#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
4060#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
4061#define CAN_F9R1_FB27_Pos (27U)
4062#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
4063#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
4064#define CAN_F9R1_FB28_Pos (28U)
4065#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
4066#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
4067#define CAN_F9R1_FB29_Pos (29U)
4068#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
4069#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
4070#define CAN_F9R1_FB30_Pos (30U)
4071#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
4072#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
4073#define CAN_F9R1_FB31_Pos (31U)
4074#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
4075#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
4077/******************* Bit definition for CAN_F10R1 register ******************/
4078#define CAN_F10R1_FB0_Pos (0U)
4079#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
4080#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
4081#define CAN_F10R1_FB1_Pos (1U)
4082#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
4083#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
4084#define CAN_F10R1_FB2_Pos (2U)
4085#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
4086#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
4087#define CAN_F10R1_FB3_Pos (3U)
4088#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
4089#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
4090#define CAN_F10R1_FB4_Pos (4U)
4091#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
4092#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
4093#define CAN_F10R1_FB5_Pos (5U)
4094#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
4095#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
4096#define CAN_F10R1_FB6_Pos (6U)
4097#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
4098#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
4099#define CAN_F10R1_FB7_Pos (7U)
4100#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
4101#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
4102#define CAN_F10R1_FB8_Pos (8U)
4103#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
4104#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
4105#define CAN_F10R1_FB9_Pos (9U)
4106#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
4107#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
4108#define CAN_F10R1_FB10_Pos (10U)
4109#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
4110#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
4111#define CAN_F10R1_FB11_Pos (11U)
4112#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
4113#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
4114#define CAN_F10R1_FB12_Pos (12U)
4115#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
4116#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
4117#define CAN_F10R1_FB13_Pos (13U)
4118#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
4119#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
4120#define CAN_F10R1_FB14_Pos (14U)
4121#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
4122#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
4123#define CAN_F10R1_FB15_Pos (15U)
4124#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
4125#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
4126#define CAN_F10R1_FB16_Pos (16U)
4127#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
4128#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
4129#define CAN_F10R1_FB17_Pos (17U)
4130#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
4131#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
4132#define CAN_F10R1_FB18_Pos (18U)
4133#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
4134#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
4135#define CAN_F10R1_FB19_Pos (19U)
4136#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
4137#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
4138#define CAN_F10R1_FB20_Pos (20U)
4139#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
4140#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
4141#define CAN_F10R1_FB21_Pos (21U)
4142#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
4143#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
4144#define CAN_F10R1_FB22_Pos (22U)
4145#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
4146#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
4147#define CAN_F10R1_FB23_Pos (23U)
4148#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
4149#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
4150#define CAN_F10R1_FB24_Pos (24U)
4151#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
4152#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
4153#define CAN_F10R1_FB25_Pos (25U)
4154#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
4155#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
4156#define CAN_F10R1_FB26_Pos (26U)
4157#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
4158#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
4159#define CAN_F10R1_FB27_Pos (27U)
4160#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
4161#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
4162#define CAN_F10R1_FB28_Pos (28U)
4163#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
4164#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
4165#define CAN_F10R1_FB29_Pos (29U)
4166#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
4167#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
4168#define CAN_F10R1_FB30_Pos (30U)
4169#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
4170#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
4171#define CAN_F10R1_FB31_Pos (31U)
4172#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
4173#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
4175/******************* Bit definition for CAN_F11R1 register ******************/
4176#define CAN_F11R1_FB0_Pos (0U)
4177#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
4178#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
4179#define CAN_F11R1_FB1_Pos (1U)
4180#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
4181#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
4182#define CAN_F11R1_FB2_Pos (2U)
4183#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
4184#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
4185#define CAN_F11R1_FB3_Pos (3U)
4186#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
4187#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
4188#define CAN_F11R1_FB4_Pos (4U)
4189#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
4190#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
4191#define CAN_F11R1_FB5_Pos (5U)
4192#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
4193#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
4194#define CAN_F11R1_FB6_Pos (6U)
4195#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
4196#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
4197#define CAN_F11R1_FB7_Pos (7U)
4198#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
4199#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
4200#define CAN_F11R1_FB8_Pos (8U)
4201#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
4202#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
4203#define CAN_F11R1_FB9_Pos (9U)
4204#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
4205#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
4206#define CAN_F11R1_FB10_Pos (10U)
4207#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
4208#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
4209#define CAN_F11R1_FB11_Pos (11U)
4210#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
4211#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
4212#define CAN_F11R1_FB12_Pos (12U)
4213#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
4214#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
4215#define CAN_F11R1_FB13_Pos (13U)
4216#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
4217#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
4218#define CAN_F11R1_FB14_Pos (14U)
4219#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
4220#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
4221#define CAN_F11R1_FB15_Pos (15U)
4222#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
4223#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
4224#define CAN_F11R1_FB16_Pos (16U)
4225#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
4226#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
4227#define CAN_F11R1_FB17_Pos (17U)
4228#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
4229#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
4230#define CAN_F11R1_FB18_Pos (18U)
4231#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
4232#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
4233#define CAN_F11R1_FB19_Pos (19U)
4234#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
4235#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
4236#define CAN_F11R1_FB20_Pos (20U)
4237#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
4238#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
4239#define CAN_F11R1_FB21_Pos (21U)
4240#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
4241#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
4242#define CAN_F11R1_FB22_Pos (22U)
4243#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
4244#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
4245#define CAN_F11R1_FB23_Pos (23U)
4246#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
4247#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
4248#define CAN_F11R1_FB24_Pos (24U)
4249#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
4250#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
4251#define CAN_F11R1_FB25_Pos (25U)
4252#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
4253#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
4254#define CAN_F11R1_FB26_Pos (26U)
4255#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
4256#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
4257#define CAN_F11R1_FB27_Pos (27U)
4258#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
4259#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
4260#define CAN_F11R1_FB28_Pos (28U)
4261#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
4262#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
4263#define CAN_F11R1_FB29_Pos (29U)
4264#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
4265#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
4266#define CAN_F11R1_FB30_Pos (30U)
4267#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
4268#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
4269#define CAN_F11R1_FB31_Pos (31U)
4270#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
4271#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
4273/******************* Bit definition for CAN_F12R1 register ******************/
4274#define CAN_F12R1_FB0_Pos (0U)
4275#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
4276#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
4277#define CAN_F12R1_FB1_Pos (1U)
4278#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4279#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4280#define CAN_F12R1_FB2_Pos (2U)
4281#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4282#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4283#define CAN_F12R1_FB3_Pos (3U)
4284#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4285#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4286#define CAN_F12R1_FB4_Pos (4U)
4287#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4288#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4289#define CAN_F12R1_FB5_Pos (5U)
4290#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4291#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4292#define CAN_F12R1_FB6_Pos (6U)
4293#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4294#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
4295#define CAN_F12R1_FB7_Pos (7U)
4296#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
4297#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
4298#define CAN_F12R1_FB8_Pos (8U)
4299#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
4300#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
4301#define CAN_F12R1_FB9_Pos (9U)
4302#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
4303#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
4304#define CAN_F12R1_FB10_Pos (10U)
4305#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
4306#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
4307#define CAN_F12R1_FB11_Pos (11U)
4308#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
4309#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
4310#define CAN_F12R1_FB12_Pos (12U)
4311#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
4312#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
4313#define CAN_F12R1_FB13_Pos (13U)
4314#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
4315#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
4316#define CAN_F12R1_FB14_Pos (14U)
4317#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
4318#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
4319#define CAN_F12R1_FB15_Pos (15U)
4320#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
4321#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
4322#define CAN_F12R1_FB16_Pos (16U)
4323#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
4324#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
4325#define CAN_F12R1_FB17_Pos (17U)
4326#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
4327#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
4328#define CAN_F12R1_FB18_Pos (18U)
4329#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
4330#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
4331#define CAN_F12R1_FB19_Pos (19U)
4332#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
4333#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
4334#define CAN_F12R1_FB20_Pos (20U)
4335#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
4336#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
4337#define CAN_F12R1_FB21_Pos (21U)
4338#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
4339#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
4340#define CAN_F12R1_FB22_Pos (22U)
4341#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
4342#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
4343#define CAN_F12R1_FB23_Pos (23U)
4344#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
4345#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
4346#define CAN_F12R1_FB24_Pos (24U)
4347#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
4348#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
4349#define CAN_F12R1_FB25_Pos (25U)
4350#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
4351#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
4352#define CAN_F12R1_FB26_Pos (26U)
4353#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
4354#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
4355#define CAN_F12R1_FB27_Pos (27U)
4356#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
4357#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
4358#define CAN_F12R1_FB28_Pos (28U)
4359#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
4360#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
4361#define CAN_F12R1_FB29_Pos (29U)
4362#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
4363#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
4364#define CAN_F12R1_FB30_Pos (30U)
4365#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
4366#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
4367#define CAN_F12R1_FB31_Pos (31U)
4368#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
4369#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
4371/******************* Bit definition for CAN_F13R1 register ******************/
4372#define CAN_F13R1_FB0_Pos (0U)
4373#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
4374#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
4375#define CAN_F13R1_FB1_Pos (1U)
4376#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
4377#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4378#define CAN_F13R1_FB2_Pos (2U)
4379#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4380#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4381#define CAN_F13R1_FB3_Pos (3U)
4382#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4383#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4384#define CAN_F13R1_FB4_Pos (4U)
4385#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4386#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4387#define CAN_F13R1_FB5_Pos (5U)
4388#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4389#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4390#define CAN_F13R1_FB6_Pos (6U)
4391#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4392#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4393#define CAN_F13R1_FB7_Pos (7U)
4394#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4395#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4396#define CAN_F13R1_FB8_Pos (8U)
4397#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4398#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4399#define CAN_F13R1_FB9_Pos (9U)
4400#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4401#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4402#define CAN_F13R1_FB10_Pos (10U)
4403#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4404#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4405#define CAN_F13R1_FB11_Pos (11U)
4406#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4407#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4408#define CAN_F13R1_FB12_Pos (12U)
4409#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4410#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4411#define CAN_F13R1_FB13_Pos (13U)
4412#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4413#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4414#define CAN_F13R1_FB14_Pos (14U)
4415#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4416#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4417#define CAN_F13R1_FB15_Pos (15U)
4418#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4419#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4420#define CAN_F13R1_FB16_Pos (16U)
4421#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4422#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4423#define CAN_F13R1_FB17_Pos (17U)
4424#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4425#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4426#define CAN_F13R1_FB18_Pos (18U)
4427#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4428#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4429#define CAN_F13R1_FB19_Pos (19U)
4430#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4431#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4432#define CAN_F13R1_FB20_Pos (20U)
4433#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4434#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4435#define CAN_F13R1_FB21_Pos (21U)
4436#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4437#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4438#define CAN_F13R1_FB22_Pos (22U)
4439#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4440#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4441#define CAN_F13R1_FB23_Pos (23U)
4442#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4443#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4444#define CAN_F13R1_FB24_Pos (24U)
4445#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4446#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4447#define CAN_F13R1_FB25_Pos (25U)
4448#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4449#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4450#define CAN_F13R1_FB26_Pos (26U)
4451#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4452#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4453#define CAN_F13R1_FB27_Pos (27U)
4454#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4455#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4456#define CAN_F13R1_FB28_Pos (28U)
4457#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4458#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4459#define CAN_F13R1_FB29_Pos (29U)
4460#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4461#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4462#define CAN_F13R1_FB30_Pos (30U)
4463#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4464#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4465#define CAN_F13R1_FB31_Pos (31U)
4466#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4467#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4469/******************* Bit definition for CAN_F0R2 register *******************/
4470#define CAN_F0R2_FB0_Pos (0U)
4471#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4472#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4473#define CAN_F0R2_FB1_Pos (1U)
4474#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4475#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4476#define CAN_F0R2_FB2_Pos (2U)
4477#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4478#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4479#define CAN_F0R2_FB3_Pos (3U)
4480#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4481#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4482#define CAN_F0R2_FB4_Pos (4U)
4483#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4484#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4485#define CAN_F0R2_FB5_Pos (5U)
4486#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4487#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4488#define CAN_F0R2_FB6_Pos (6U)
4489#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4490#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4491#define CAN_F0R2_FB7_Pos (7U)
4492#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4493#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4494#define CAN_F0R2_FB8_Pos (8U)
4495#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4496#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4497#define CAN_F0R2_FB9_Pos (9U)
4498#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4499#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4500#define CAN_F0R2_FB10_Pos (10U)
4501#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4502#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4503#define CAN_F0R2_FB11_Pos (11U)
4504#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4505#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4506#define CAN_F0R2_FB12_Pos (12U)
4507#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4508#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4509#define CAN_F0R2_FB13_Pos (13U)
4510#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4511#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4512#define CAN_F0R2_FB14_Pos (14U)
4513#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4514#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4515#define CAN_F0R2_FB15_Pos (15U)
4516#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4517#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4518#define CAN_F0R2_FB16_Pos (16U)
4519#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4520#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4521#define CAN_F0R2_FB17_Pos (17U)
4522#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4523#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4524#define CAN_F0R2_FB18_Pos (18U)
4525#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4526#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4527#define CAN_F0R2_FB19_Pos (19U)
4528#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4529#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4530#define CAN_F0R2_FB20_Pos (20U)
4531#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4532#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4533#define CAN_F0R2_FB21_Pos (21U)
4534#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4535#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4536#define CAN_F0R2_FB22_Pos (22U)
4537#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4538#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4539#define CAN_F0R2_FB23_Pos (23U)
4540#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4541#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4542#define CAN_F0R2_FB24_Pos (24U)
4543#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4544#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4545#define CAN_F0R2_FB25_Pos (25U)
4546#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4547#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4548#define CAN_F0R2_FB26_Pos (26U)
4549#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4550#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4551#define CAN_F0R2_FB27_Pos (27U)
4552#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4553#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4554#define CAN_F0R2_FB28_Pos (28U)
4555#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4556#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4557#define CAN_F0R2_FB29_Pos (29U)
4558#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4559#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4560#define CAN_F0R2_FB30_Pos (30U)
4561#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4562#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4563#define CAN_F0R2_FB31_Pos (31U)
4564#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4565#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4567/******************* Bit definition for CAN_F1R2 register *******************/
4568#define CAN_F1R2_FB0_Pos (0U)
4569#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4570#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4571#define CAN_F1R2_FB1_Pos (1U)
4572#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4573#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4574#define CAN_F1R2_FB2_Pos (2U)
4575#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4576#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4577#define CAN_F1R2_FB3_Pos (3U)
4578#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4579#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4580#define CAN_F1R2_FB4_Pos (4U)
4581#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4582#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4583#define CAN_F1R2_FB5_Pos (5U)
4584#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4585#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4586#define CAN_F1R2_FB6_Pos (6U)
4587#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4588#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4589#define CAN_F1R2_FB7_Pos (7U)
4590#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4591#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4592#define CAN_F1R2_FB8_Pos (8U)
4593#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4594#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4595#define CAN_F1R2_FB9_Pos (9U)
4596#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4597#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4598#define CAN_F1R2_FB10_Pos (10U)
4599#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4600#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4601#define CAN_F1R2_FB11_Pos (11U)
4602#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4603#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4604#define CAN_F1R2_FB12_Pos (12U)
4605#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4606#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4607#define CAN_F1R2_FB13_Pos (13U)
4608#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4609#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4610#define CAN_F1R2_FB14_Pos (14U)
4611#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4612#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4613#define CAN_F1R2_FB15_Pos (15U)
4614#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4615#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4616#define CAN_F1R2_FB16_Pos (16U)
4617#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4618#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4619#define CAN_F1R2_FB17_Pos (17U)
4620#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4621#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4622#define CAN_F1R2_FB18_Pos (18U)
4623#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4624#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4625#define CAN_F1R2_FB19_Pos (19U)
4626#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4627#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4628#define CAN_F1R2_FB20_Pos (20U)
4629#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4630#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4631#define CAN_F1R2_FB21_Pos (21U)
4632#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4633#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4634#define CAN_F1R2_FB22_Pos (22U)
4635#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4636#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4637#define CAN_F1R2_FB23_Pos (23U)
4638#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4639#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4640#define CAN_F1R2_FB24_Pos (24U)
4641#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4642#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4643#define CAN_F1R2_FB25_Pos (25U)
4644#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4645#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4646#define CAN_F1R2_FB26_Pos (26U)
4647#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4648#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4649#define CAN_F1R2_FB27_Pos (27U)
4650#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4651#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4652#define CAN_F1R2_FB28_Pos (28U)
4653#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4654#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4655#define CAN_F1R2_FB29_Pos (29U)
4656#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4657#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4658#define CAN_F1R2_FB30_Pos (30U)
4659#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4660#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4661#define CAN_F1R2_FB31_Pos (31U)
4662#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4663#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4665/******************* Bit definition for CAN_F2R2 register *******************/
4666#define CAN_F2R2_FB0_Pos (0U)
4667#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4668#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4669#define CAN_F2R2_FB1_Pos (1U)
4670#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4671#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4672#define CAN_F2R2_FB2_Pos (2U)
4673#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4674#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4675#define CAN_F2R2_FB3_Pos (3U)
4676#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4677#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4678#define CAN_F2R2_FB4_Pos (4U)
4679#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4680#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4681#define CAN_F2R2_FB5_Pos (5U)
4682#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4683#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4684#define CAN_F2R2_FB6_Pos (6U)
4685#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4686#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4687#define CAN_F2R2_FB7_Pos (7U)
4688#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4689#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4690#define CAN_F2R2_FB8_Pos (8U)
4691#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4692#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4693#define CAN_F2R2_FB9_Pos (9U)
4694#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4695#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4696#define CAN_F2R2_FB10_Pos (10U)
4697#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4698#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4699#define CAN_F2R2_FB11_Pos (11U)
4700#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4701#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4702#define CAN_F2R2_FB12_Pos (12U)
4703#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4704#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4705#define CAN_F2R2_FB13_Pos (13U)
4706#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4707#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4708#define CAN_F2R2_FB14_Pos (14U)
4709#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4710#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4711#define CAN_F2R2_FB15_Pos (15U)
4712#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4713#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4714#define CAN_F2R2_FB16_Pos (16U)
4715#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4716#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4717#define CAN_F2R2_FB17_Pos (17U)
4718#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4719#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4720#define CAN_F2R2_FB18_Pos (18U)
4721#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4722#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4723#define CAN_F2R2_FB19_Pos (19U)
4724#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4725#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4726#define CAN_F2R2_FB20_Pos (20U)
4727#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4728#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4729#define CAN_F2R2_FB21_Pos (21U)
4730#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4731#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4732#define CAN_F2R2_FB22_Pos (22U)
4733#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4734#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4735#define CAN_F2R2_FB23_Pos (23U)
4736#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4737#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4738#define CAN_F2R2_FB24_Pos (24U)
4739#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4740#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4741#define CAN_F2R2_FB25_Pos (25U)
4742#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4743#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4744#define CAN_F2R2_FB26_Pos (26U)
4745#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4746#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4747#define CAN_F2R2_FB27_Pos (27U)
4748#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4749#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4750#define CAN_F2R2_FB28_Pos (28U)
4751#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4752#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4753#define CAN_F2R2_FB29_Pos (29U)
4754#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4755#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4756#define CAN_F2R2_FB30_Pos (30U)
4757#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4758#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4759#define CAN_F2R2_FB31_Pos (31U)
4760#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4761#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4763/******************* Bit definition for CAN_F3R2 register *******************/
4764#define CAN_F3R2_FB0_Pos (0U)
4765#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4766#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4767#define CAN_F3R2_FB1_Pos (1U)
4768#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4769#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4770#define CAN_F3R2_FB2_Pos (2U)
4771#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4772#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4773#define CAN_F3R2_FB3_Pos (3U)
4774#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4775#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4776#define CAN_F3R2_FB4_Pos (4U)
4777#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4778#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4779#define CAN_F3R2_FB5_Pos (5U)
4780#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4781#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4782#define CAN_F3R2_FB6_Pos (6U)
4783#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4784#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4785#define CAN_F3R2_FB7_Pos (7U)
4786#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4787#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4788#define CAN_F3R2_FB8_Pos (8U)
4789#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4790#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4791#define CAN_F3R2_FB9_Pos (9U)
4792#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4793#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4794#define CAN_F3R2_FB10_Pos (10U)
4795#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4796#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4797#define CAN_F3R2_FB11_Pos (11U)
4798#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4799#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4800#define CAN_F3R2_FB12_Pos (12U)
4801#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4802#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4803#define CAN_F3R2_FB13_Pos (13U)
4804#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4805#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4806#define CAN_F3R2_FB14_Pos (14U)
4807#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4808#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4809#define CAN_F3R2_FB15_Pos (15U)
4810#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4811#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4812#define CAN_F3R2_FB16_Pos (16U)
4813#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4814#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4815#define CAN_F3R2_FB17_Pos (17U)
4816#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4817#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4818#define CAN_F3R2_FB18_Pos (18U)
4819#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4820#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4821#define CAN_F3R2_FB19_Pos (19U)
4822#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4823#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4824#define CAN_F3R2_FB20_Pos (20U)
4825#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4826#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4827#define CAN_F3R2_FB21_Pos (21U)
4828#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4829#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4830#define CAN_F3R2_FB22_Pos (22U)
4831#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4832#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4833#define CAN_F3R2_FB23_Pos (23U)
4834#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4835#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4836#define CAN_F3R2_FB24_Pos (24U)
4837#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4838#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4839#define CAN_F3R2_FB25_Pos (25U)
4840#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4841#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4842#define CAN_F3R2_FB26_Pos (26U)
4843#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4844#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4845#define CAN_F3R2_FB27_Pos (27U)
4846#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4847#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4848#define CAN_F3R2_FB28_Pos (28U)
4849#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4850#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4851#define CAN_F3R2_FB29_Pos (29U)
4852#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4853#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4854#define CAN_F3R2_FB30_Pos (30U)
4855#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4856#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4857#define CAN_F3R2_FB31_Pos (31U)
4858#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4859#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4861/******************* Bit definition for CAN_F4R2 register *******************/
4862#define CAN_F4R2_FB0_Pos (0U)
4863#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4864#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4865#define CAN_F4R2_FB1_Pos (1U)
4866#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4867#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4868#define CAN_F4R2_FB2_Pos (2U)
4869#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4870#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4871#define CAN_F4R2_FB3_Pos (3U)
4872#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4873#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4874#define CAN_F4R2_FB4_Pos (4U)
4875#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4876#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4877#define CAN_F4R2_FB5_Pos (5U)
4878#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4879#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4880#define CAN_F4R2_FB6_Pos (6U)
4881#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4882#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4883#define CAN_F4R2_FB7_Pos (7U)
4884#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4885#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4886#define CAN_F4R2_FB8_Pos (8U)
4887#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4888#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4889#define CAN_F4R2_FB9_Pos (9U)
4890#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4891#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4892#define CAN_F4R2_FB10_Pos (10U)
4893#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4894#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4895#define CAN_F4R2_FB11_Pos (11U)
4896#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4897#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4898#define CAN_F4R2_FB12_Pos (12U)
4899#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4900#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4901#define CAN_F4R2_FB13_Pos (13U)
4902#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4903#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4904#define CAN_F4R2_FB14_Pos (14U)
4905#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4906#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4907#define CAN_F4R2_FB15_Pos (15U)
4908#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4909#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4910#define CAN_F4R2_FB16_Pos (16U)
4911#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4912#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4913#define CAN_F4R2_FB17_Pos (17U)
4914#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4915#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4916#define CAN_F4R2_FB18_Pos (18U)
4917#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4918#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4919#define CAN_F4R2_FB19_Pos (19U)
4920#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4921#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4922#define CAN_F4R2_FB20_Pos (20U)
4923#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4924#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4925#define CAN_F4R2_FB21_Pos (21U)
4926#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4927#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4928#define CAN_F4R2_FB22_Pos (22U)
4929#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4930#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4931#define CAN_F4R2_FB23_Pos (23U)
4932#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4933#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4934#define CAN_F4R2_FB24_Pos (24U)
4935#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4936#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4937#define CAN_F4R2_FB25_Pos (25U)
4938#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4939#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4940#define CAN_F4R2_FB26_Pos (26U)
4941#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4942#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4943#define CAN_F4R2_FB27_Pos (27U)
4944#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4945#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4946#define CAN_F4R2_FB28_Pos (28U)
4947#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4948#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4949#define CAN_F4R2_FB29_Pos (29U)
4950#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4951#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4952#define CAN_F4R2_FB30_Pos (30U)
4953#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4954#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4955#define CAN_F4R2_FB31_Pos (31U)
4956#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4957#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4959/******************* Bit definition for CAN_F5R2 register *******************/
4960#define CAN_F5R2_FB0_Pos (0U)
4961#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4962#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4963#define CAN_F5R2_FB1_Pos (1U)
4964#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4965#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4966#define CAN_F5R2_FB2_Pos (2U)
4967#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4968#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4969#define CAN_F5R2_FB3_Pos (3U)
4970#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4971#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4972#define CAN_F5R2_FB4_Pos (4U)
4973#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4974#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4975#define CAN_F5R2_FB5_Pos (5U)
4976#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4977#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4978#define CAN_F5R2_FB6_Pos (6U)
4979#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4980#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4981#define CAN_F5R2_FB7_Pos (7U)
4982#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4983#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4984#define CAN_F5R2_FB8_Pos (8U)
4985#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4986#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4987#define CAN_F5R2_FB9_Pos (9U)
4988#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4989#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4990#define CAN_F5R2_FB10_Pos (10U)
4991#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4992#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4993#define CAN_F5R2_FB11_Pos (11U)
4994#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4995#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4996#define CAN_F5R2_FB12_Pos (12U)
4997#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4998#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4999#define CAN_F5R2_FB13_Pos (13U)
5000#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
5001#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
5002#define CAN_F5R2_FB14_Pos (14U)
5003#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
5004#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
5005#define CAN_F5R2_FB15_Pos (15U)
5006#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
5007#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
5008#define CAN_F5R2_FB16_Pos (16U)
5009#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
5010#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
5011#define CAN_F5R2_FB17_Pos (17U)
5012#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
5013#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
5014#define CAN_F5R2_FB18_Pos (18U)
5015#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
5016#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
5017#define CAN_F5R2_FB19_Pos (19U)
5018#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
5019#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
5020#define CAN_F5R2_FB20_Pos (20U)
5021#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
5022#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
5023#define CAN_F5R2_FB21_Pos (21U)
5024#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
5025#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
5026#define CAN_F5R2_FB22_Pos (22U)
5027#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
5028#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
5029#define CAN_F5R2_FB23_Pos (23U)
5030#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
5031#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
5032#define CAN_F5R2_FB24_Pos (24U)
5033#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
5034#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
5035#define CAN_F5R2_FB25_Pos (25U)
5036#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
5037#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
5038#define CAN_F5R2_FB26_Pos (26U)
5039#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
5040#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
5041#define CAN_F5R2_FB27_Pos (27U)
5042#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
5043#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
5044#define CAN_F5R2_FB28_Pos (28U)
5045#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
5046#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
5047#define CAN_F5R2_FB29_Pos (29U)
5048#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
5049#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
5050#define CAN_F5R2_FB30_Pos (30U)
5051#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
5052#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
5053#define CAN_F5R2_FB31_Pos (31U)
5054#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
5055#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
5057/******************* Bit definition for CAN_F6R2 register *******************/
5058#define CAN_F6R2_FB0_Pos (0U)
5059#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
5060#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
5061#define CAN_F6R2_FB1_Pos (1U)
5062#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
5063#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
5064#define CAN_F6R2_FB2_Pos (2U)
5065#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
5066#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
5067#define CAN_F6R2_FB3_Pos (3U)
5068#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
5069#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
5070#define CAN_F6R2_FB4_Pos (4U)
5071#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
5072#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
5073#define CAN_F6R2_FB5_Pos (5U)
5074#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
5075#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
5076#define CAN_F6R2_FB6_Pos (6U)
5077#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
5078#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
5079#define CAN_F6R2_FB7_Pos (7U)
5080#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
5081#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
5082#define CAN_F6R2_FB8_Pos (8U)
5083#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
5084#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
5085#define CAN_F6R2_FB9_Pos (9U)
5086#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
5087#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
5088#define CAN_F6R2_FB10_Pos (10U)
5089#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
5090#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
5091#define CAN_F6R2_FB11_Pos (11U)
5092#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
5093#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
5094#define CAN_F6R2_FB12_Pos (12U)
5095#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
5096#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
5097#define CAN_F6R2_FB13_Pos (13U)
5098#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
5099#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
5100#define CAN_F6R2_FB14_Pos (14U)
5101#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
5102#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
5103#define CAN_F6R2_FB15_Pos (15U)
5104#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
5105#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
5106#define CAN_F6R2_FB16_Pos (16U)
5107#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
5108#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
5109#define CAN_F6R2_FB17_Pos (17U)
5110#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
5111#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
5112#define CAN_F6R2_FB18_Pos (18U)
5113#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
5114#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
5115#define CAN_F6R2_FB19_Pos (19U)
5116#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
5117#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
5118#define CAN_F6R2_FB20_Pos (20U)
5119#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
5120#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
5121#define CAN_F6R2_FB21_Pos (21U)
5122#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
5123#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
5124#define CAN_F6R2_FB22_Pos (22U)
5125#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
5126#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
5127#define CAN_F6R2_FB23_Pos (23U)
5128#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
5129#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
5130#define CAN_F6R2_FB24_Pos (24U)
5131#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
5132#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
5133#define CAN_F6R2_FB25_Pos (25U)
5134#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
5135#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
5136#define CAN_F6R2_FB26_Pos (26U)
5137#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
5138#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
5139#define CAN_F6R2_FB27_Pos (27U)
5140#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
5141#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
5142#define CAN_F6R2_FB28_Pos (28U)
5143#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
5144#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
5145#define CAN_F6R2_FB29_Pos (29U)
5146#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
5147#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
5148#define CAN_F6R2_FB30_Pos (30U)
5149#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
5150#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
5151#define CAN_F6R2_FB31_Pos (31U)
5152#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
5153#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
5155/******************* Bit definition for CAN_F7R2 register *******************/
5156#define CAN_F7R2_FB0_Pos (0U)
5157#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
5158#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
5159#define CAN_F7R2_FB1_Pos (1U)
5160#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
5161#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
5162#define CAN_F7R2_FB2_Pos (2U)
5163#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
5164#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
5165#define CAN_F7R2_FB3_Pos (3U)
5166#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
5167#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
5168#define CAN_F7R2_FB4_Pos (4U)
5169#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
5170#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
5171#define CAN_F7R2_FB5_Pos (5U)
5172#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
5173#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
5174#define CAN_F7R2_FB6_Pos (6U)
5175#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
5176#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
5177#define CAN_F7R2_FB7_Pos (7U)
5178#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
5179#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
5180#define CAN_F7R2_FB8_Pos (8U)
5181#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
5182#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
5183#define CAN_F7R2_FB9_Pos (9U)
5184#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
5185#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
5186#define CAN_F7R2_FB10_Pos (10U)
5187#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
5188#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
5189#define CAN_F7R2_FB11_Pos (11U)
5190#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
5191#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
5192#define CAN_F7R2_FB12_Pos (12U)
5193#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
5194#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
5195#define CAN_F7R2_FB13_Pos (13U)
5196#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
5197#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
5198#define CAN_F7R2_FB14_Pos (14U)
5199#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
5200#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
5201#define CAN_F7R2_FB15_Pos (15U)
5202#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
5203#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
5204#define CAN_F7R2_FB16_Pos (16U)
5205#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
5206#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
5207#define CAN_F7R2_FB17_Pos (17U)
5208#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
5209#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
5210#define CAN_F7R2_FB18_Pos (18U)
5211#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
5212#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
5213#define CAN_F7R2_FB19_Pos (19U)
5214#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
5215#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
5216#define CAN_F7R2_FB20_Pos (20U)
5217#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
5218#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
5219#define CAN_F7R2_FB21_Pos (21U)
5220#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
5221#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
5222#define CAN_F7R2_FB22_Pos (22U)
5223#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
5224#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
5225#define CAN_F7R2_FB23_Pos (23U)
5226#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
5227#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
5228#define CAN_F7R2_FB24_Pos (24U)
5229#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
5230#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
5231#define CAN_F7R2_FB25_Pos (25U)
5232#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
5233#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
5234#define CAN_F7R2_FB26_Pos (26U)
5235#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
5236#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
5237#define CAN_F7R2_FB27_Pos (27U)
5238#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
5239#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
5240#define CAN_F7R2_FB28_Pos (28U)
5241#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
5242#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
5243#define CAN_F7R2_FB29_Pos (29U)
5244#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
5245#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
5246#define CAN_F7R2_FB30_Pos (30U)
5247#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
5248#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
5249#define CAN_F7R2_FB31_Pos (31U)
5250#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
5251#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
5253/******************* Bit definition for CAN_F8R2 register *******************/
5254#define CAN_F8R2_FB0_Pos (0U)
5255#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
5256#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
5257#define CAN_F8R2_FB1_Pos (1U)
5258#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
5259#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
5260#define CAN_F8R2_FB2_Pos (2U)
5261#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
5262#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
5263#define CAN_F8R2_FB3_Pos (3U)
5264#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
5265#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
5266#define CAN_F8R2_FB4_Pos (4U)
5267#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
5268#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
5269#define CAN_F8R2_FB5_Pos (5U)
5270#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
5271#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
5272#define CAN_F8R2_FB6_Pos (6U)
5273#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
5274#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
5275#define CAN_F8R2_FB7_Pos (7U)
5276#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
5277#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
5278#define CAN_F8R2_FB8_Pos (8U)
5279#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5280#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5281#define CAN_F8R2_FB9_Pos (9U)
5282#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5283#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5284#define CAN_F8R2_FB10_Pos (10U)
5285#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5286#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5287#define CAN_F8R2_FB11_Pos (11U)
5288#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5289#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5290#define CAN_F8R2_FB12_Pos (12U)
5291#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5292#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5293#define CAN_F8R2_FB13_Pos (13U)
5294#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
5295#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
5296#define CAN_F8R2_FB14_Pos (14U)
5297#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
5298#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
5299#define CAN_F8R2_FB15_Pos (15U)
5300#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
5301#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
5302#define CAN_F8R2_FB16_Pos (16U)
5303#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
5304#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
5305#define CAN_F8R2_FB17_Pos (17U)
5306#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
5307#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
5308#define CAN_F8R2_FB18_Pos (18U)
5309#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
5310#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
5311#define CAN_F8R2_FB19_Pos (19U)
5312#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
5313#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
5314#define CAN_F8R2_FB20_Pos (20U)
5315#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
5316#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
5317#define CAN_F8R2_FB21_Pos (21U)
5318#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
5319#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
5320#define CAN_F8R2_FB22_Pos (22U)
5321#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
5322#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
5323#define CAN_F8R2_FB23_Pos (23U)
5324#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
5325#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
5326#define CAN_F8R2_FB24_Pos (24U)
5327#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
5328#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
5329#define CAN_F8R2_FB25_Pos (25U)
5330#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
5331#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
5332#define CAN_F8R2_FB26_Pos (26U)
5333#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
5334#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
5335#define CAN_F8R2_FB27_Pos (27U)
5336#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
5337#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
5338#define CAN_F8R2_FB28_Pos (28U)
5339#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
5340#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
5341#define CAN_F8R2_FB29_Pos (29U)
5342#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
5343#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
5344#define CAN_F8R2_FB30_Pos (30U)
5345#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
5346#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
5347#define CAN_F8R2_FB31_Pos (31U)
5348#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
5349#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
5351/******************* Bit definition for CAN_F9R2 register *******************/
5352#define CAN_F9R2_FB0_Pos (0U)
5353#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
5354#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
5355#define CAN_F9R2_FB1_Pos (1U)
5356#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
5357#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
5358#define CAN_F9R2_FB2_Pos (2U)
5359#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
5360#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
5361#define CAN_F9R2_FB3_Pos (3U)
5362#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
5363#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
5364#define CAN_F9R2_FB4_Pos (4U)
5365#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
5366#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
5367#define CAN_F9R2_FB5_Pos (5U)
5368#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
5369#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
5370#define CAN_F9R2_FB6_Pos (6U)
5371#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
5372#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
5373#define CAN_F9R2_FB7_Pos (7U)
5374#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
5375#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
5376#define CAN_F9R2_FB8_Pos (8U)
5377#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5378#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5379#define CAN_F9R2_FB9_Pos (9U)
5380#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5381#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5382#define CAN_F9R2_FB10_Pos (10U)
5383#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5384#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5385#define CAN_F9R2_FB11_Pos (11U)
5386#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5387#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5388#define CAN_F9R2_FB12_Pos (12U)
5389#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5390#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5391#define CAN_F9R2_FB13_Pos (13U)
5392#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5393#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5394#define CAN_F9R2_FB14_Pos (14U)
5395#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5396#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5397#define CAN_F9R2_FB15_Pos (15U)
5398#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5399#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5400#define CAN_F9R2_FB16_Pos (16U)
5401#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5402#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5403#define CAN_F9R2_FB17_Pos (17U)
5404#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5405#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5406#define CAN_F9R2_FB18_Pos (18U)
5407#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5408#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5409#define CAN_F9R2_FB19_Pos (19U)
5410#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5411#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5412#define CAN_F9R2_FB20_Pos (20U)
5413#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5414#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5415#define CAN_F9R2_FB21_Pos (21U)
5416#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5417#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5418#define CAN_F9R2_FB22_Pos (22U)
5419#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5420#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5421#define CAN_F9R2_FB23_Pos (23U)
5422#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5423#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5424#define CAN_F9R2_FB24_Pos (24U)
5425#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5426#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5427#define CAN_F9R2_FB25_Pos (25U)
5428#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5429#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5430#define CAN_F9R2_FB26_Pos (26U)
5431#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5432#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5433#define CAN_F9R2_FB27_Pos (27U)
5434#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5435#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5436#define CAN_F9R2_FB28_Pos (28U)
5437#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5438#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5439#define CAN_F9R2_FB29_Pos (29U)
5440#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5441#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5442#define CAN_F9R2_FB30_Pos (30U)
5443#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5444#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5445#define CAN_F9R2_FB31_Pos (31U)
5446#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5447#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5449/******************* Bit definition for CAN_F10R2 register ******************/
5450#define CAN_F10R2_FB0_Pos (0U)
5451#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5452#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5453#define CAN_F10R2_FB1_Pos (1U)
5454#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5455#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5456#define CAN_F10R2_FB2_Pos (2U)
5457#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5458#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5459#define CAN_F10R2_FB3_Pos (3U)
5460#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5461#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5462#define CAN_F10R2_FB4_Pos (4U)
5463#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5464#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5465#define CAN_F10R2_FB5_Pos (5U)
5466#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5467#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5468#define CAN_F10R2_FB6_Pos (6U)
5469#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5470#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5471#define CAN_F10R2_FB7_Pos (7U)
5472#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5473#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5474#define CAN_F10R2_FB8_Pos (8U)
5475#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5476#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5477#define CAN_F10R2_FB9_Pos (9U)
5478#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5479#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5480#define CAN_F10R2_FB10_Pos (10U)
5481#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5482#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5483#define CAN_F10R2_FB11_Pos (11U)
5484#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5485#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5486#define CAN_F10R2_FB12_Pos (12U)
5487#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5488#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5489#define CAN_F10R2_FB13_Pos (13U)
5490#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5491#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5492#define CAN_F10R2_FB14_Pos (14U)
5493#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5494#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5495#define CAN_F10R2_FB15_Pos (15U)
5496#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5497#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5498#define CAN_F10R2_FB16_Pos (16U)
5499#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5500#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5501#define CAN_F10R2_FB17_Pos (17U)
5502#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5503#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5504#define CAN_F10R2_FB18_Pos (18U)
5505#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5506#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5507#define CAN_F10R2_FB19_Pos (19U)
5508#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5509#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5510#define CAN_F10R2_FB20_Pos (20U)
5511#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5512#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5513#define CAN_F10R2_FB21_Pos (21U)
5514#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5515#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5516#define CAN_F10R2_FB22_Pos (22U)
5517#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5518#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5519#define CAN_F10R2_FB23_Pos (23U)
5520#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5521#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5522#define CAN_F10R2_FB24_Pos (24U)
5523#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5524#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5525#define CAN_F10R2_FB25_Pos (25U)
5526#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5527#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5528#define CAN_F10R2_FB26_Pos (26U)
5529#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5530#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5531#define CAN_F10R2_FB27_Pos (27U)
5532#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5533#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5534#define CAN_F10R2_FB28_Pos (28U)
5535#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5536#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5537#define CAN_F10R2_FB29_Pos (29U)
5538#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5539#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5540#define CAN_F10R2_FB30_Pos (30U)
5541#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5542#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5543#define CAN_F10R2_FB31_Pos (31U)
5544#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5545#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5547/******************* Bit definition for CAN_F11R2 register ******************/
5548#define CAN_F11R2_FB0_Pos (0U)
5549#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5550#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5551#define CAN_F11R2_FB1_Pos (1U)
5552#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5553#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5554#define CAN_F11R2_FB2_Pos (2U)
5555#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5556#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5557#define CAN_F11R2_FB3_Pos (3U)
5558#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5559#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5560#define CAN_F11R2_FB4_Pos (4U)
5561#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5562#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5563#define CAN_F11R2_FB5_Pos (5U)
5564#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5565#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5566#define CAN_F11R2_FB6_Pos (6U)
5567#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5568#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5569#define CAN_F11R2_FB7_Pos (7U)
5570#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5571#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5572#define CAN_F11R2_FB8_Pos (8U)
5573#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5574#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5575#define CAN_F11R2_FB9_Pos (9U)
5576#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5577#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5578#define CAN_F11R2_FB10_Pos (10U)
5579#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5580#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5581#define CAN_F11R2_FB11_Pos (11U)
5582#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5583#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5584#define CAN_F11R2_FB12_Pos (12U)
5585#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5586#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5587#define CAN_F11R2_FB13_Pos (13U)
5588#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5589#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5590#define CAN_F11R2_FB14_Pos (14U)
5591#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5592#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5593#define CAN_F11R2_FB15_Pos (15U)
5594#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5595#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5596#define CAN_F11R2_FB16_Pos (16U)
5597#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5598#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5599#define CAN_F11R2_FB17_Pos (17U)
5600#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5601#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5602#define CAN_F11R2_FB18_Pos (18U)
5603#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5604#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5605#define CAN_F11R2_FB19_Pos (19U)
5606#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5607#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5608#define CAN_F11R2_FB20_Pos (20U)
5609#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5610#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5611#define CAN_F11R2_FB21_Pos (21U)
5612#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5613#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5614#define CAN_F11R2_FB22_Pos (22U)
5615#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5616#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5617#define CAN_F11R2_FB23_Pos (23U)
5618#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5619#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5620#define CAN_F11R2_FB24_Pos (24U)
5621#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5622#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5623#define CAN_F11R2_FB25_Pos (25U)
5624#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5625#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5626#define CAN_F11R2_FB26_Pos (26U)
5627#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5628#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5629#define CAN_F11R2_FB27_Pos (27U)
5630#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5631#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5632#define CAN_F11R2_FB28_Pos (28U)
5633#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5634#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5635#define CAN_F11R2_FB29_Pos (29U)
5636#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5637#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5638#define CAN_F11R2_FB30_Pos (30U)
5639#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5640#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5641#define CAN_F11R2_FB31_Pos (31U)
5642#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5643#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5645/******************* Bit definition for CAN_F12R2 register ******************/
5646#define CAN_F12R2_FB0_Pos (0U)
5647#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5648#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5649#define CAN_F12R2_FB1_Pos (1U)
5650#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5651#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5652#define CAN_F12R2_FB2_Pos (2U)
5653#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5654#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5655#define CAN_F12R2_FB3_Pos (3U)
5656#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5657#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5658#define CAN_F12R2_FB4_Pos (4U)
5659#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5660#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5661#define CAN_F12R2_FB5_Pos (5U)
5662#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5663#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5664#define CAN_F12R2_FB6_Pos (6U)
5665#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5666#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5667#define CAN_F12R2_FB7_Pos (7U)
5668#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5669#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5670#define CAN_F12R2_FB8_Pos (8U)
5671#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5672#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5673#define CAN_F12R2_FB9_Pos (9U)
5674#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5675#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5676#define CAN_F12R2_FB10_Pos (10U)
5677#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5678#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5679#define CAN_F12R2_FB11_Pos (11U)
5680#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5681#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5682#define CAN_F12R2_FB12_Pos (12U)
5683#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5684#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5685#define CAN_F12R2_FB13_Pos (13U)
5686#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5687#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5688#define CAN_F12R2_FB14_Pos (14U)
5689#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5690#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5691#define CAN_F12R2_FB15_Pos (15U)
5692#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5693#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5694#define CAN_F12R2_FB16_Pos (16U)
5695#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5696#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5697#define CAN_F12R2_FB17_Pos (17U)
5698#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5699#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5700#define CAN_F12R2_FB18_Pos (18U)
5701#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5702#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5703#define CAN_F12R2_FB19_Pos (19U)
5704#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5705#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5706#define CAN_F12R2_FB20_Pos (20U)
5707#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5708#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5709#define CAN_F12R2_FB21_Pos (21U)
5710#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5711#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5712#define CAN_F12R2_FB22_Pos (22U)
5713#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5714#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5715#define CAN_F12R2_FB23_Pos (23U)
5716#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5717#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5718#define CAN_F12R2_FB24_Pos (24U)
5719#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5720#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5721#define CAN_F12R2_FB25_Pos (25U)
5722#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5723#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5724#define CAN_F12R2_FB26_Pos (26U)
5725#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5726#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5727#define CAN_F12R2_FB27_Pos (27U)
5728#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5729#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5730#define CAN_F12R2_FB28_Pos (28U)
5731#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5732#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5733#define CAN_F12R2_FB29_Pos (29U)
5734#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5735#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5736#define CAN_F12R2_FB30_Pos (30U)
5737#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5738#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5739#define CAN_F12R2_FB31_Pos (31U)
5740#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5741#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5743/******************* Bit definition for CAN_F13R2 register ******************/
5744#define CAN_F13R2_FB0_Pos (0U)
5745#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5746#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5747#define CAN_F13R2_FB1_Pos (1U)
5748#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5749#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5750#define CAN_F13R2_FB2_Pos (2U)
5751#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5752#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5753#define CAN_F13R2_FB3_Pos (3U)
5754#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5755#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5756#define CAN_F13R2_FB4_Pos (4U)
5757#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5758#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5759#define CAN_F13R2_FB5_Pos (5U)
5760#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5761#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5762#define CAN_F13R2_FB6_Pos (6U)
5763#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5764#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5765#define CAN_F13R2_FB7_Pos (7U)
5766#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5767#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5768#define CAN_F13R2_FB8_Pos (8U)
5769#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5770#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5771#define CAN_F13R2_FB9_Pos (9U)
5772#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5773#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5774#define CAN_F13R2_FB10_Pos (10U)
5775#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5776#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5777#define CAN_F13R2_FB11_Pos (11U)
5778#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5779#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5780#define CAN_F13R2_FB12_Pos (12U)
5781#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5782#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5783#define CAN_F13R2_FB13_Pos (13U)
5784#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5785#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5786#define CAN_F13R2_FB14_Pos (14U)
5787#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5788#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5789#define CAN_F13R2_FB15_Pos (15U)
5790#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5791#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5792#define CAN_F13R2_FB16_Pos (16U)
5793#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5794#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5795#define CAN_F13R2_FB17_Pos (17U)
5796#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5797#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5798#define CAN_F13R2_FB18_Pos (18U)
5799#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5800#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5801#define CAN_F13R2_FB19_Pos (19U)
5802#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5803#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5804#define CAN_F13R2_FB20_Pos (20U)
5805#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5806#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5807#define CAN_F13R2_FB21_Pos (21U)
5808#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5809#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5810#define CAN_F13R2_FB22_Pos (22U)
5811#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5812#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5813#define CAN_F13R2_FB23_Pos (23U)
5814#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5815#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5816#define CAN_F13R2_FB24_Pos (24U)
5817#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5818#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5819#define CAN_F13R2_FB25_Pos (25U)
5820#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5821#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5822#define CAN_F13R2_FB26_Pos (26U)
5823#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5824#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5825#define CAN_F13R2_FB27_Pos (27U)
5826#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5827#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5828#define CAN_F13R2_FB28_Pos (28U)
5829#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5830#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5831#define CAN_F13R2_FB29_Pos (29U)
5832#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5833#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5834#define CAN_F13R2_FB30_Pos (30U)
5835#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5836#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5837#define CAN_F13R2_FB31_Pos (31U)
5838#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5839#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5841/******************************************************************************/
5842/* */
5843/* HDMI-CEC (CEC) */
5844/* */
5845/******************************************************************************/
5846
5847/******************* Bit definition for CEC_CR register *********************/
5848#define CEC_CR_CECEN_Pos (0U)
5849#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos)
5850#define CEC_CR_CECEN CEC_CR_CECEN_Msk
5851#define CEC_CR_TXSOM_Pos (1U)
5852#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos)
5853#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk
5854#define CEC_CR_TXEOM_Pos (2U)
5855#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos)
5856#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk
5858/******************* Bit definition for CEC_CFGR register *******************/
5859#define CEC_CFGR_SFT_Pos (0U)
5860#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos)
5861#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk
5862#define CEC_CFGR_RXTOL_Pos (3U)
5863#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos)
5864#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk
5865#define CEC_CFGR_BRESTP_Pos (4U)
5866#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos)
5867#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk
5868#define CEC_CFGR_BREGEN_Pos (5U)
5869#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos)
5870#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk
5871#define CEC_CFGR_LBPEGEN_Pos (6U)
5872#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos)
5873#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk
5874#define CEC_CFGR_BRDNOGEN_Pos (7U)
5875#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
5876#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk
5877#define CEC_CFGR_SFTOPT_Pos (8U)
5878#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos)
5879#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk
5880#define CEC_CFGR_OAR_Pos (16U)
5881#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos)
5882#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk
5883#define CEC_CFGR_LSTN_Pos (31U)
5884#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos)
5885#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk
5887/******************* Bit definition for CEC_TXDR register *******************/
5888#define CEC_TXDR_TXD_Pos (0U)
5889#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos)
5890#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk
5892/******************* Bit definition for CEC_RXDR register *******************/
5893#define CEC_RXDR_RXD_Pos (0U)
5894#define CEC_RXDR_RXD_Msk (0xFFU << CEC_RXDR_RXD_Pos)
5895#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk
5897/******************* Bit definition for CEC_ISR register ********************/
5898#define CEC_ISR_RXBR_Pos (0U)
5899#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos)
5900#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk
5901#define CEC_ISR_RXEND_Pos (1U)
5902#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos)
5903#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk
5904#define CEC_ISR_RXOVR_Pos (2U)
5905#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
5906#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk
5907#define CEC_ISR_BRE_Pos (3U)
5908#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos)
5909#define CEC_ISR_BRE CEC_ISR_BRE_Msk
5910#define CEC_ISR_SBPE_Pos (4U)
5911#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos)
5912#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk
5913#define CEC_ISR_LBPE_Pos (5U)
5914#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos)
5915#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk
5916#define CEC_ISR_RXACKE_Pos (6U)
5917#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos)
5918#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk
5919#define CEC_ISR_ARBLST_Pos (7U)
5920#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos)
5921#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk
5922#define CEC_ISR_TXBR_Pos (8U)
5923#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos)
5924#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk
5925#define CEC_ISR_TXEND_Pos (9U)
5926#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos)
5927#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk
5928#define CEC_ISR_TXUDR_Pos (10U)
5929#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos)
5930#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk
5931#define CEC_ISR_TXERR_Pos (11U)
5932#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos)
5933#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk
5934#define CEC_ISR_TXACKE_Pos (12U)
5935#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos)
5936#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk
5938/******************* Bit definition for CEC_IER register ********************/
5939#define CEC_IER_RXBRIE_Pos (0U)
5940#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos)
5941#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk
5942#define CEC_IER_RXENDIE_Pos (1U)
5943#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos)
5944#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk
5945#define CEC_IER_RXOVRIE_Pos (2U)
5946#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos)
5947#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk
5948#define CEC_IER_BREIE_Pos (3U)
5949#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos)
5950#define CEC_IER_BREIE CEC_IER_BREIE_Msk
5951#define CEC_IER_SBPEIE_Pos (4U)
5952#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos)
5953#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk
5954#define CEC_IER_LBPEIE_Pos (5U)
5955#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos)
5956#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk
5957#define CEC_IER_RXACKEIE_Pos (6U)
5958#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos)
5959#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk
5960#define CEC_IER_ARBLSTIE_Pos (7U)
5961#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos)
5962#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk
5963#define CEC_IER_TXBRIE_Pos (8U)
5964#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos)
5965#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk
5966#define CEC_IER_TXENDIE_Pos (9U)
5967#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos)
5968#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk
5969#define CEC_IER_TXUDRIE_Pos (10U)
5970#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos)
5971#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk
5972#define CEC_IER_TXERRIE_Pos (11U)
5973#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos)
5974#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk
5975#define CEC_IER_TXACKEIE_Pos (12U)
5976#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos)
5977#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk
5979/******************************************************************************/
5980/* */
5981/* CRC calculation unit */
5982/* */
5983/******************************************************************************/
5984/******************* Bit definition for CRC_DR register *********************/
5985#define CRC_DR_DR_Pos (0U)
5986#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5987#define CRC_DR_DR CRC_DR_DR_Msk
5989/******************* Bit definition for CRC_IDR register ********************/
5990#define CRC_IDR_IDR_Pos (0U)
5991#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5992#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5994/******************** Bit definition for CRC_CR register ********************/
5995#define CRC_CR_RESET_Pos (0U)
5996#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5997#define CRC_CR_RESET CRC_CR_RESET_Msk
5998#define CRC_CR_POLYSIZE_Pos (3U)
5999#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
6000#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
6001#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
6002#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
6003#define CRC_CR_REV_IN_Pos (5U)
6004#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
6005#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
6006#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
6007#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
6008#define CRC_CR_REV_OUT_Pos (7U)
6009#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
6010#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
6012/******************* Bit definition for CRC_INIT register *******************/
6013#define CRC_INIT_INIT_Pos (0U)
6014#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
6015#define CRC_INIT_INIT CRC_INIT_INIT_Msk
6017/******************* Bit definition for CRC_POL register ********************/
6018#define CRC_POL_POL_Pos (0U)
6019#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
6020#define CRC_POL_POL CRC_POL_POL_Msk
6022/******************************************************************************/
6023/* */
6024/* Crypto Processor */
6025/* */
6026/******************************************************************************/
6027/******************* Bits definition for CRYP_CR register ********************/
6028#define CRYP_CR_ALGODIR_Pos (2U)
6029#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos)
6030#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
6031
6032#define CRYP_CR_ALGOMODE_Pos (3U)
6033#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos)
6034#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
6035#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos)
6036#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos)
6037#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos)
6038#define CRYP_CR_ALGOMODE_TDES_ECB 0x00000000U
6039#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
6040#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos)
6041#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
6042#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
6043#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos)
6044#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
6045#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
6046#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos)
6047#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
6048#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
6049#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)
6050#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
6051#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
6052#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)
6053#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
6054#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
6055#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)
6056#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
6057#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
6058#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)
6059#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
6060#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
6061#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)
6062#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
6063#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
6064#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos)
6065#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
6066
6067#define CRYP_CR_DATATYPE_Pos (6U)
6068#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos)
6069#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
6070#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos)
6071#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos)
6072#define CRYP_CR_KEYSIZE_Pos (8U)
6073#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos)
6074#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
6075#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos)
6076#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos)
6077#define CRYP_CR_FFLUSH_Pos (14U)
6078#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos)
6079#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
6080#define CRYP_CR_CRYPEN_Pos (15U)
6081#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos)
6082#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
6083
6084#define CRYP_CR_GCM_CCMPH_Pos (16U)
6085#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos)
6086#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
6087#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos)
6088#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos)
6089#define CRYP_CR_ALGOMODE_3 0x00080000U
6090
6091/****************** Bits definition for CRYP_SR register *********************/
6092#define CRYP_SR_IFEM_Pos (0U)
6093#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos)
6094#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
6095#define CRYP_SR_IFNF_Pos (1U)
6096#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos)
6097#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
6098#define CRYP_SR_OFNE_Pos (2U)
6099#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos)
6100#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
6101#define CRYP_SR_OFFU_Pos (3U)
6102#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos)
6103#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
6104#define CRYP_SR_BUSY_Pos (4U)
6105#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos)
6106#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
6107/****************** Bits definition for CRYP_DMACR register ******************/
6108#define CRYP_DMACR_DIEN_Pos (0U)
6109#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos)
6110#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
6111#define CRYP_DMACR_DOEN_Pos (1U)
6112#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos)
6113#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
6114/***************** Bits definition for CRYP_IMSCR register ******************/
6115#define CRYP_IMSCR_INIM_Pos (0U)
6116#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos)
6117#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
6118#define CRYP_IMSCR_OUTIM_Pos (1U)
6119#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos)
6120#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
6121/****************** Bits definition for CRYP_RISR register *******************/
6122#define CRYP_RISR_OUTRIS_Pos (0U)
6123#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos)
6124#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
6125#define CRYP_RISR_INRIS_Pos (1U)
6126#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos)
6127#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
6128/****************** Bits definition for CRYP_MISR register *******************/
6129#define CRYP_MISR_INMIS_Pos (0U)
6130#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos)
6131#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
6132#define CRYP_MISR_OUTMIS_Pos (1U)
6133#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos)
6134#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
6135
6136/******************************************************************************/
6137/* */
6138/* Digital to Analog Converter */
6139/* */
6140/******************************************************************************/
6141/******************** Bit definition for DAC_CR register ********************/
6142#define DAC_CR_EN1_Pos (0U)
6143#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
6144#define DAC_CR_EN1 DAC_CR_EN1_Msk
6145#define DAC_CR_BOFF1_Pos (1U)
6146#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
6147#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
6148#define DAC_CR_TEN1_Pos (2U)
6149#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
6150#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
6151#define DAC_CR_TSEL1_Pos (3U)
6152#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
6153#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
6154#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
6155#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
6156#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
6157#define DAC_CR_WAVE1_Pos (6U)
6158#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
6159#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
6160#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
6161#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
6162#define DAC_CR_MAMP1_Pos (8U)
6163#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
6164#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
6165#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
6166#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
6167#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
6168#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
6169#define DAC_CR_DMAEN1_Pos (12U)
6170#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
6171#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
6172#define DAC_CR_DMAUDRIE1_Pos (13U)
6173#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
6174#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
6175#define DAC_CR_EN2_Pos (16U)
6176#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
6177#define DAC_CR_EN2 DAC_CR_EN2_Msk
6178#define DAC_CR_BOFF2_Pos (17U)
6179#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
6180#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
6181#define DAC_CR_TEN2_Pos (18U)
6182#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
6183#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
6184#define DAC_CR_TSEL2_Pos (19U)
6185#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
6186#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
6187#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
6188#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
6189#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
6190#define DAC_CR_WAVE2_Pos (22U)
6191#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
6192#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
6193#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
6194#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
6195#define DAC_CR_MAMP2_Pos (24U)
6196#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
6197#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
6198#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
6199#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
6200#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
6201#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
6202#define DAC_CR_DMAEN2_Pos (28U)
6203#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
6204#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
6205#define DAC_CR_DMAUDRIE2_Pos (29U)
6206#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
6207#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
6209/***************** Bit definition for DAC_SWTRIGR register ******************/
6210#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6211#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
6212#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
6213#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6214#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
6215#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
6217/***************** Bit definition for DAC_DHR12R1 register ******************/
6218#define DAC_DHR12R1_DACC1DHR_Pos (0U)
6219#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
6220#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
6222/***************** Bit definition for DAC_DHR12L1 register ******************/
6223#define DAC_DHR12L1_DACC1DHR_Pos (4U)
6224#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
6225#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
6227/****************** Bit definition for DAC_DHR8R1 register ******************/
6228#define DAC_DHR8R1_DACC1DHR_Pos (0U)
6229#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
6230#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
6232/***************** Bit definition for DAC_DHR12R2 register ******************/
6233#define DAC_DHR12R2_DACC2DHR_Pos (0U)
6234#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
6235#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
6237/***************** Bit definition for DAC_DHR12L2 register ******************/
6238#define DAC_DHR12L2_DACC2DHR_Pos (4U)
6239#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
6240#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
6242/****************** Bit definition for DAC_DHR8R2 register ******************/
6243#define DAC_DHR8R2_DACC2DHR_Pos (0U)
6244#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
6245#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
6247/***************** Bit definition for DAC_DHR12RD register ******************/
6248#define DAC_DHR12RD_DACC1DHR_Pos (0U)
6249#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
6250#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
6251#define DAC_DHR12RD_DACC2DHR_Pos (16U)
6252#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
6253#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
6255/***************** Bit definition for DAC_DHR12LD register ******************/
6256#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6257#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
6258#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
6259#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6260#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
6261#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
6263/****************** Bit definition for DAC_DHR8RD register ******************/
6264#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6265#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
6266#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
6267#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6268#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
6269#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
6271/******************* Bit definition for DAC_DOR1 register *******************/
6272#define DAC_DOR1_DACC1DOR_Pos (0U)
6273#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
6274#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
6276/******************* Bit definition for DAC_DOR2 register *******************/
6277#define DAC_DOR2_DACC2DOR_Pos (0U)
6278#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6279#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6281/******************** Bit definition for DAC_SR register ********************/
6282#define DAC_SR_DMAUDR1_Pos (13U)
6283#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6284#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6285#define DAC_SR_DMAUDR2_Pos (29U)
6286#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6287#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6289/******************************************************************************/
6290/* */
6291/* Digital Filter for Sigma Delta Modulators */
6292/* */
6293/******************************************************************************/
6294
6295/**************** DFSDM channel configuration registers ********************/
6296
6297/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6298#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6299#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
6300#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
6301#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6302#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
6303#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
6304#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6305#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
6306#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
6307#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6308#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
6309#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
6310#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
6311#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
6312#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6313#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
6314#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
6315#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
6316#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
6317#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6318#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
6319#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
6320#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6321#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
6322#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
6323#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6324#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
6325#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
6326#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6327#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
6328#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
6329#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6330#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6331#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
6332#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6333#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6334#define DFSDM_CHCFGR1_SITP_Pos (0U)
6335#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
6336#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
6337#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
6338#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
6340/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6341#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6342#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
6343#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
6344#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6345#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
6346#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
6348/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6349#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6350#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6351#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
6352#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6353#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6354#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6355#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
6356#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
6357#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6358#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
6359#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
6360#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6361#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
6362#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
6364/**************** Bit definition for DFSDM_CHWDATR register *******************/
6365#define DFSDM_CHWDATR_WDATA_Pos (0U)
6366#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
6367#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
6369/**************** Bit definition for DFSDM_CHDATINR register *****************/
6370#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6371#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
6372#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
6373#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6374#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
6375#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
6377/************************ DFSDM module registers ****************************/
6378
6379/******************** Bit definition for DFSDM_FLTCR1 register *******************/
6380#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6381#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
6382#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
6383#define DFSDM_FLTCR1_FAST_Pos (29U)
6384#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
6385#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
6386#define DFSDM_FLTCR1_RCH_Pos (24U)
6387#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
6388#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
6389#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6390#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
6391#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
6392#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6393#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
6394#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
6395#define DFSDM_FLTCR1_RCONT_Pos (18U)
6396#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
6397#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
6398#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6399#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
6400#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
6401#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6402#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
6403#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
6404#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
6405#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
6406#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6407#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)
6408#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
6409#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6410#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6411#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6412#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6413#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6414#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6415#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
6416#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
6417#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6418#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
6419#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
6420#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6421#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
6422#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
6423#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6424#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
6425#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
6426#define DFSDM_FLTCR1_DFEN_Pos (0U)
6427#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
6428#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
6430/******************** Bit definition for DFSDM_FLTCR2 register *******************/
6431#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6432#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
6433#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
6434#define DFSDM_FLTCR2_EXCH_Pos (8U)
6435#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
6436#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
6437#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6438#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
6439#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
6440#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6441#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
6442#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
6443#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6444#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
6445#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
6446#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6447#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
6448#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
6449#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6450#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
6451#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
6452#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6453#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
6454#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
6455#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6456#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
6457#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
6459/******************** Bit definition for DFSDM_FLTISR register *******************/
6460#define DFSDM_FLTISR_SCDF_Pos (24U)
6461#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
6462#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
6463#define DFSDM_FLTISR_CKABF_Pos (16U)
6464#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
6465#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
6466#define DFSDM_FLTISR_RCIP_Pos (14U)
6467#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
6468#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
6469#define DFSDM_FLTISR_JCIP_Pos (13U)
6470#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
6471#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
6472#define DFSDM_FLTISR_AWDF_Pos (4U)
6473#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
6474#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
6475#define DFSDM_FLTISR_ROVRF_Pos (3U)
6476#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
6477#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
6478#define DFSDM_FLTISR_JOVRF_Pos (2U)
6479#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
6480#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
6481#define DFSDM_FLTISR_REOCF_Pos (1U)
6482#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
6483#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
6484#define DFSDM_FLTISR_JEOCF_Pos (0U)
6485#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
6486#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
6488/******************** Bit definition for DFSDM_FLTICR register *******************/
6489#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6490#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
6491#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
6492#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6493#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
6494#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
6495#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6496#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
6497#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
6498#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6499#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
6500#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
6502/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6503#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6504#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
6505#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
6507/******************** Bit definition for DFSDM_FLTFCR register *******************/
6508#define DFSDM_FLTFCR_FORD_Pos (29U)
6509#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
6510#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
6511#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
6512#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
6513#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
6514#define DFSDM_FLTFCR_FOSR_Pos (16U)
6515#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
6516#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
6517#define DFSDM_FLTFCR_IOSR_Pos (0U)
6518#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
6519#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
6521/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6522#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6523#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
6524#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
6525#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6526#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
6527#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
6529/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6530#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6531#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
6532#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
6533#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6534#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
6535#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
6536#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6537#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
6538#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
6540/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6541#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6542#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
6543#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
6544#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6545#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
6546#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
6548/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6549#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6550#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
6551#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
6552#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6553#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
6554#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
6556/****************** Bit definition for DFSDM_FLTAWSR register ******************/
6557#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6558#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
6559#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
6560#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6561#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
6562#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
6564/****************** Bit definition for DFSDM_FLTAWCFR register *****************/
6565#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6566#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
6567#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
6568#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6569#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
6570#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
6572/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6573#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6574#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
6575#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
6576#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6577#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
6578#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
6580/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6581#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6582#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
6583#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
6584#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6585#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
6586#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
6588/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6589#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6590#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
6591#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
6593/* Legacy Defines */
6594#define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
6595#define DFSDM_FLTICR_CLRSCSDF_Msk DFSDM_FLTICR_CLRSCDF_Msk
6596#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCDF
6597
6598/******************************************************************************/
6599/* */
6600/* Debug MCU */
6601/* */
6602/******************************************************************************/
6603
6604/******************************************************************************/
6605/* */
6606/* DCMI */
6607/* */
6608/******************************************************************************/
6609/******************** Bits definition for DCMI_CR register ******************/
6610#define DCMI_CR_CAPTURE_Pos (0U)
6611#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
6612#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6613#define DCMI_CR_CM_Pos (1U)
6614#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
6615#define DCMI_CR_CM DCMI_CR_CM_Msk
6616#define DCMI_CR_CROP_Pos (2U)
6617#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
6618#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6619#define DCMI_CR_JPEG_Pos (3U)
6620#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
6621#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6622#define DCMI_CR_ESS_Pos (4U)
6623#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
6624#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6625#define DCMI_CR_PCKPOL_Pos (5U)
6626#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
6627#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6628#define DCMI_CR_HSPOL_Pos (6U)
6629#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
6630#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6631#define DCMI_CR_VSPOL_Pos (7U)
6632#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
6633#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6634#define DCMI_CR_FCRC_0 0x00000100U
6635#define DCMI_CR_FCRC_1 0x00000200U
6636#define DCMI_CR_EDM_0 0x00000400U
6637#define DCMI_CR_EDM_1 0x00000800U
6638#define DCMI_CR_CRE_Pos (12U)
6639#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
6640#define DCMI_CR_CRE DCMI_CR_CRE_Msk
6641#define DCMI_CR_ENABLE_Pos (14U)
6642#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
6643#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6644#define DCMI_CR_BSM_Pos (16U)
6645#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos)
6646#define DCMI_CR_BSM DCMI_CR_BSM_Msk
6647#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos)
6648#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos)
6649#define DCMI_CR_OEBS_Pos (18U)
6650#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
6651#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6652#define DCMI_CR_LSM_Pos (19U)
6653#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
6654#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6655#define DCMI_CR_OELS_Pos (20U)
6656#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
6657#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6658
6659/******************** Bits definition for DCMI_SR register ******************/
6660#define DCMI_SR_HSYNC_Pos (0U)
6661#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
6662#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6663#define DCMI_SR_VSYNC_Pos (1U)
6664#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
6665#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6666#define DCMI_SR_FNE_Pos (2U)
6667#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
6668#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6669
6670/******************** Bits definition for DCMI_RIS register ****************/
6671#define DCMI_RIS_FRAME_RIS_Pos (0U)
6672#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
6673#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6674#define DCMI_RIS_OVR_RIS_Pos (1U)
6675#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
6676#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6677#define DCMI_RIS_ERR_RIS_Pos (2U)
6678#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
6679#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6680#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6681#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
6682#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6683#define DCMI_RIS_LINE_RIS_Pos (4U)
6684#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
6685#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6686
6687/* Legacy defines */
6688#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
6689#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
6690#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
6691#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
6692#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
6693
6694/******************** Bits definition for DCMI_IER register *****************/
6695#define DCMI_IER_FRAME_IE_Pos (0U)
6696#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
6697#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6698#define DCMI_IER_OVR_IE_Pos (1U)
6699#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
6700#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6701#define DCMI_IER_ERR_IE_Pos (2U)
6702#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
6703#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6704#define DCMI_IER_VSYNC_IE_Pos (3U)
6705#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
6706#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6707#define DCMI_IER_LINE_IE_Pos (4U)
6708#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
6709#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6710
6711
6712/******************** Bits definition for DCMI_MIS register *****************/
6713#define DCMI_MIS_FRAME_MIS_Pos (0U)
6714#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
6715#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6716#define DCMI_MIS_OVR_MIS_Pos (1U)
6717#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
6718#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6719#define DCMI_MIS_ERR_MIS_Pos (2U)
6720#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
6721#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6722#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6723#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
6724#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6725#define DCMI_MIS_LINE_MIS_Pos (4U)
6726#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
6727#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6728
6729
6730/******************** Bits definition for DCMI_ICR register *****************/
6731#define DCMI_ICR_FRAME_ISC_Pos (0U)
6732#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
6733#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6734#define DCMI_ICR_OVR_ISC_Pos (1U)
6735#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
6736#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6737#define DCMI_ICR_ERR_ISC_Pos (2U)
6738#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
6739#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6740#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6741#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
6742#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6743#define DCMI_ICR_LINE_ISC_Pos (4U)
6744#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
6745#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6746
6747
6748/******************** Bits definition for DCMI_ESCR register ******************/
6749#define DCMI_ESCR_FSC_Pos (0U)
6750#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6751#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6752#define DCMI_ESCR_LSC_Pos (8U)
6753#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6754#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6755#define DCMI_ESCR_LEC_Pos (16U)
6756#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6757#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6758#define DCMI_ESCR_FEC_Pos (24U)
6759#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6760#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6761
6762/******************** Bits definition for DCMI_ESUR register ******************/
6763#define DCMI_ESUR_FSU_Pos (0U)
6764#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6765#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6766#define DCMI_ESUR_LSU_Pos (8U)
6767#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6768#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6769#define DCMI_ESUR_LEU_Pos (16U)
6770#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6771#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6772#define DCMI_ESUR_FEU_Pos (24U)
6773#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6774#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6775
6776/******************** Bits definition for DCMI_CWSTRT register ******************/
6777#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6778#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6779#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6780#define DCMI_CWSTRT_VST_Pos (16U)
6781#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6782#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6783
6784/******************** Bits definition for DCMI_CWSIZE register ******************/
6785#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6786#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6787#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6788#define DCMI_CWSIZE_VLINE_Pos (16U)
6789#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6790#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6791
6792/******************** Bits definition for DCMI_DR register ******************/
6793#define DCMI_DR_BYTE0_Pos (0U)
6794#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6795#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6796#define DCMI_DR_BYTE1_Pos (8U)
6797#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6798#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6799#define DCMI_DR_BYTE2_Pos (16U)
6800#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6801#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6802#define DCMI_DR_BYTE3_Pos (24U)
6803#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6804#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6805
6806/******************************************************************************/
6807/* */
6808/* DMA Controller */
6809/* */
6810/******************************************************************************/
6811/******************** Bits definition for DMA_SxCR register *****************/
6812#define DMA_SxCR_CHSEL_Pos (25U)
6813#define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos)
6814#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6815#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
6816#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
6817#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
6818#define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos)
6819#define DMA_SxCR_MBURST_Pos (23U)
6820#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
6821#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6822#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
6823#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
6824#define DMA_SxCR_PBURST_Pos (21U)
6825#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
6826#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6827#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
6828#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
6829#define DMA_SxCR_CT_Pos (19U)
6830#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
6831#define DMA_SxCR_CT DMA_SxCR_CT_Msk
6832#define DMA_SxCR_DBM_Pos (18U)
6833#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
6834#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6835#define DMA_SxCR_PL_Pos (16U)
6836#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
6837#define DMA_SxCR_PL DMA_SxCR_PL_Msk
6838#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
6839#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
6840#define DMA_SxCR_PINCOS_Pos (15U)
6841#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
6842#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6843#define DMA_SxCR_MSIZE_Pos (13U)
6844#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
6845#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6846#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
6847#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
6848#define DMA_SxCR_PSIZE_Pos (11U)
6849#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
6850#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6851#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
6852#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
6853#define DMA_SxCR_MINC_Pos (10U)
6854#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
6855#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6856#define DMA_SxCR_PINC_Pos (9U)
6857#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
6858#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6859#define DMA_SxCR_CIRC_Pos (8U)
6860#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
6861#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6862#define DMA_SxCR_DIR_Pos (6U)
6863#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
6864#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6865#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
6866#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
6867#define DMA_SxCR_PFCTRL_Pos (5U)
6868#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
6869#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6870#define DMA_SxCR_TCIE_Pos (4U)
6871#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
6872#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6873#define DMA_SxCR_HTIE_Pos (3U)
6874#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
6875#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6876#define DMA_SxCR_TEIE_Pos (2U)
6877#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
6878#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6879#define DMA_SxCR_DMEIE_Pos (1U)
6880#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
6881#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6882#define DMA_SxCR_EN_Pos (0U)
6883#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6884#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6885
6886/******************** Bits definition for DMA_SxCNDTR register **************/
6887#define DMA_SxNDT_Pos (0U)
6888#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6889#define DMA_SxNDT DMA_SxNDT_Msk
6890#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6891#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6892#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6893#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6894#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6895#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6896#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6897#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6898#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6899#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6900#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6901#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6902#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6903#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6904#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6905#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6907/******************** Bits definition for DMA_SxFCR register ****************/
6908#define DMA_SxFCR_FEIE_Pos (7U)
6909#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6910#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6911#define DMA_SxFCR_FS_Pos (3U)
6912#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6913#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6914#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6915#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6916#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6917#define DMA_SxFCR_DMDIS_Pos (2U)
6918#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6919#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6920#define DMA_SxFCR_FTH_Pos (0U)
6921#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6922#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6923#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6924#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6926/******************** Bits definition for DMA_LISR register *****************/
6927#define DMA_LISR_TCIF3_Pos (27U)
6928#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6929#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6930#define DMA_LISR_HTIF3_Pos (26U)
6931#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6932#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6933#define DMA_LISR_TEIF3_Pos (25U)
6934#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6935#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6936#define DMA_LISR_DMEIF3_Pos (24U)
6937#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6938#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6939#define DMA_LISR_FEIF3_Pos (22U)
6940#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
6941#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6942#define DMA_LISR_TCIF2_Pos (21U)
6943#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
6944#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6945#define DMA_LISR_HTIF2_Pos (20U)
6946#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
6947#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6948#define DMA_LISR_TEIF2_Pos (19U)
6949#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
6950#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6951#define DMA_LISR_DMEIF2_Pos (18U)
6952#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
6953#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6954#define DMA_LISR_FEIF2_Pos (16U)
6955#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
6956#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6957#define DMA_LISR_TCIF1_Pos (11U)
6958#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
6959#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6960#define DMA_LISR_HTIF1_Pos (10U)
6961#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
6962#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6963#define DMA_LISR_TEIF1_Pos (9U)
6964#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
6965#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6966#define DMA_LISR_DMEIF1_Pos (8U)
6967#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
6968#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6969#define DMA_LISR_FEIF1_Pos (6U)
6970#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
6971#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6972#define DMA_LISR_TCIF0_Pos (5U)
6973#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
6974#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6975#define DMA_LISR_HTIF0_Pos (4U)
6976#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
6977#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6978#define DMA_LISR_TEIF0_Pos (3U)
6979#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
6980#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6981#define DMA_LISR_DMEIF0_Pos (2U)
6982#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
6983#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6984#define DMA_LISR_FEIF0_Pos (0U)
6985#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
6986#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6987
6988/******************** Bits definition for DMA_HISR register *****************/
6989#define DMA_HISR_TCIF7_Pos (27U)
6990#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
6991#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6992#define DMA_HISR_HTIF7_Pos (26U)
6993#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
6994#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6995#define DMA_HISR_TEIF7_Pos (25U)
6996#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6997#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6998#define DMA_HISR_DMEIF7_Pos (24U)
6999#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
7000#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
7001#define DMA_HISR_FEIF7_Pos (22U)
7002#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
7003#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
7004#define DMA_HISR_TCIF6_Pos (21U)
7005#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
7006#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
7007#define DMA_HISR_HTIF6_Pos (20U)
7008#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
7009#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
7010#define DMA_HISR_TEIF6_Pos (19U)
7011#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
7012#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
7013#define DMA_HISR_DMEIF6_Pos (18U)
7014#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
7015#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
7016#define DMA_HISR_FEIF6_Pos (16U)
7017#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
7018#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
7019#define DMA_HISR_TCIF5_Pos (11U)
7020#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
7021#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
7022#define DMA_HISR_HTIF5_Pos (10U)
7023#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
7024#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
7025#define DMA_HISR_TEIF5_Pos (9U)
7026#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
7027#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
7028#define DMA_HISR_DMEIF5_Pos (8U)
7029#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
7030#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
7031#define DMA_HISR_FEIF5_Pos (6U)
7032#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
7033#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
7034#define DMA_HISR_TCIF4_Pos (5U)
7035#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
7036#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
7037#define DMA_HISR_HTIF4_Pos (4U)
7038#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
7039#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
7040#define DMA_HISR_TEIF4_Pos (3U)
7041#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
7042#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
7043#define DMA_HISR_DMEIF4_Pos (2U)
7044#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
7045#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
7046#define DMA_HISR_FEIF4_Pos (0U)
7047#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
7048#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
7049
7050/******************** Bits definition for DMA_LIFCR register ****************/
7051#define DMA_LIFCR_CTCIF3_Pos (27U)
7052#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
7053#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
7054#define DMA_LIFCR_CHTIF3_Pos (26U)
7055#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
7056#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
7057#define DMA_LIFCR_CTEIF3_Pos (25U)
7058#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
7059#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
7060#define DMA_LIFCR_CDMEIF3_Pos (24U)
7061#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
7062#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
7063#define DMA_LIFCR_CFEIF3_Pos (22U)
7064#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
7065#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
7066#define DMA_LIFCR_CTCIF2_Pos (21U)
7067#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
7068#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
7069#define DMA_LIFCR_CHTIF2_Pos (20U)
7070#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
7071#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
7072#define DMA_LIFCR_CTEIF2_Pos (19U)
7073#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
7074#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
7075#define DMA_LIFCR_CDMEIF2_Pos (18U)
7076#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
7077#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
7078#define DMA_LIFCR_CFEIF2_Pos (16U)
7079#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
7080#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
7081#define DMA_LIFCR_CTCIF1_Pos (11U)
7082#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
7083#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
7084#define DMA_LIFCR_CHTIF1_Pos (10U)
7085#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
7086#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
7087#define DMA_LIFCR_CTEIF1_Pos (9U)
7088#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
7089#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
7090#define DMA_LIFCR_CDMEIF1_Pos (8U)
7091#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
7092#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
7093#define DMA_LIFCR_CFEIF1_Pos (6U)
7094#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
7095#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
7096#define DMA_LIFCR_CTCIF0_Pos (5U)
7097#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
7098#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
7099#define DMA_LIFCR_CHTIF0_Pos (4U)
7100#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
7101#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
7102#define DMA_LIFCR_CTEIF0_Pos (3U)
7103#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
7104#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
7105#define DMA_LIFCR_CDMEIF0_Pos (2U)
7106#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
7107#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
7108#define DMA_LIFCR_CFEIF0_Pos (0U)
7109#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
7110#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
7111
7112/******************** Bits definition for DMA_HIFCR register ****************/
7113#define DMA_HIFCR_CTCIF7_Pos (27U)
7114#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
7115#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
7116#define DMA_HIFCR_CHTIF7_Pos (26U)
7117#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
7118#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
7119#define DMA_HIFCR_CTEIF7_Pos (25U)
7120#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
7121#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
7122#define DMA_HIFCR_CDMEIF7_Pos (24U)
7123#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
7124#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
7125#define DMA_HIFCR_CFEIF7_Pos (22U)
7126#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
7127#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
7128#define DMA_HIFCR_CTCIF6_Pos (21U)
7129#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
7130#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
7131#define DMA_HIFCR_CHTIF6_Pos (20U)
7132#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
7133#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
7134#define DMA_HIFCR_CTEIF6_Pos (19U)
7135#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
7136#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
7137#define DMA_HIFCR_CDMEIF6_Pos (18U)
7138#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
7139#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
7140#define DMA_HIFCR_CFEIF6_Pos (16U)
7141#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
7142#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
7143#define DMA_HIFCR_CTCIF5_Pos (11U)
7144#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
7145#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
7146#define DMA_HIFCR_CHTIF5_Pos (10U)
7147#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
7148#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
7149#define DMA_HIFCR_CTEIF5_Pos (9U)
7150#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
7151#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
7152#define DMA_HIFCR_CDMEIF5_Pos (8U)
7153#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
7154#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
7155#define DMA_HIFCR_CFEIF5_Pos (6U)
7156#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
7157#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
7158#define DMA_HIFCR_CTCIF4_Pos (5U)
7159#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
7160#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
7161#define DMA_HIFCR_CHTIF4_Pos (4U)
7162#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
7163#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
7164#define DMA_HIFCR_CTEIF4_Pos (3U)
7165#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
7166#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
7167#define DMA_HIFCR_CDMEIF4_Pos (2U)
7168#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
7169#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
7170#define DMA_HIFCR_CFEIF4_Pos (0U)
7171#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
7172#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
7173
7174/****************** Bit definition for DMA_SxPAR register ********************/
7175#define DMA_SxPAR_PA_Pos (0U)
7176#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
7177#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
7179/****************** Bit definition for DMA_SxM0AR register ********************/
7180#define DMA_SxM0AR_M0A_Pos (0U)
7181#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
7182#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
7184/****************** Bit definition for DMA_SxM1AR register ********************/
7185#define DMA_SxM1AR_M1A_Pos (0U)
7186#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
7187#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
7189/******************************************************************************/
7190/* */
7191/* AHB Master DMA2D Controller (DMA2D) */
7192/* */
7193/******************************************************************************/
7194/*
7195 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
7196 */
7197#define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT
7198/******************** Bit definition for DMA2D_CR register ******************/
7199
7200#define DMA2D_CR_START_Pos (0U)
7201#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
7202#define DMA2D_CR_START DMA2D_CR_START_Msk
7203#define DMA2D_CR_SUSP_Pos (1U)
7204#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
7205#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
7206#define DMA2D_CR_ABORT_Pos (2U)
7207#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
7208#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
7209#define DMA2D_CR_TEIE_Pos (8U)
7210#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
7211#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
7212#define DMA2D_CR_TCIE_Pos (9U)
7213#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
7214#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
7215#define DMA2D_CR_TWIE_Pos (10U)
7216#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
7217#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
7218#define DMA2D_CR_CAEIE_Pos (11U)
7219#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
7220#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
7221#define DMA2D_CR_CTCIE_Pos (12U)
7222#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
7223#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
7224#define DMA2D_CR_CEIE_Pos (13U)
7225#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
7226#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
7227#define DMA2D_CR_MODE_Pos (16U)
7228#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos)
7229#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
7230#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
7231#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
7233/******************** Bit definition for DMA2D_ISR register *****************/
7234
7235#define DMA2D_ISR_TEIF_Pos (0U)
7236#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
7237#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
7238#define DMA2D_ISR_TCIF_Pos (1U)
7239#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
7240#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
7241#define DMA2D_ISR_TWIF_Pos (2U)
7242#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
7243#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
7244#define DMA2D_ISR_CAEIF_Pos (3U)
7245#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
7246#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
7247#define DMA2D_ISR_CTCIF_Pos (4U)
7248#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
7249#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
7250#define DMA2D_ISR_CEIF_Pos (5U)
7251#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
7252#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
7254/******************** Bit definition for DMA2D_IFCR register ****************/
7255
7256#define DMA2D_IFCR_CTEIF_Pos (0U)
7257#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
7258#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
7259#define DMA2D_IFCR_CTCIF_Pos (1U)
7260#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
7261#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
7262#define DMA2D_IFCR_CTWIF_Pos (2U)
7263#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
7264#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
7265#define DMA2D_IFCR_CAECIF_Pos (3U)
7266#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
7267#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
7268#define DMA2D_IFCR_CCTCIF_Pos (4U)
7269#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
7270#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
7271#define DMA2D_IFCR_CCEIF_Pos (5U)
7272#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
7273#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
7275/* Legacy defines */
7276#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
7277#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
7278#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
7279#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
7280#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
7281#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
7283/******************** Bit definition for DMA2D_FGMAR register ***************/
7284
7285#define DMA2D_FGMAR_MA_Pos (0U)
7286#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
7287#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
7289/******************** Bit definition for DMA2D_FGOR register ****************/
7290
7291#define DMA2D_FGOR_LO_Pos (0U)
7292#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos)
7293#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
7295/******************** Bit definition for DMA2D_BGMAR register ***************/
7296
7297#define DMA2D_BGMAR_MA_Pos (0U)
7298#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
7299#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
7301/******************** Bit definition for DMA2D_BGOR register ****************/
7302
7303#define DMA2D_BGOR_LO_Pos (0U)
7304#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos)
7305#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
7307/******************** Bit definition for DMA2D_FGPFCCR register *************/
7308
7309#define DMA2D_FGPFCCR_CM_Pos (0U)
7310#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
7311#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
7312#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
7313#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
7314#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
7315#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
7316#define DMA2D_FGPFCCR_CCM_Pos (4U)
7317#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
7318#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
7319#define DMA2D_FGPFCCR_START_Pos (5U)
7320#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
7321#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
7322#define DMA2D_FGPFCCR_CS_Pos (8U)
7323#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
7324#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
7325#define DMA2D_FGPFCCR_AM_Pos (16U)
7326#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
7327#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
7328#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
7329#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
7330#define DMA2D_FGPFCCR_AI_Pos (20U)
7331#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos)
7332#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk
7333#define DMA2D_FGPFCCR_RBS_Pos (21U)
7334#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos)
7335#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk
7336#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
7337#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
7338#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
7340/******************** Bit definition for DMA2D_FGCOLR register **************/
7341
7342#define DMA2D_FGCOLR_BLUE_Pos (0U)
7343#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
7344#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
7345#define DMA2D_FGCOLR_GREEN_Pos (8U)
7346#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
7347#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
7348#define DMA2D_FGCOLR_RED_Pos (16U)
7349#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
7350#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
7352/******************** Bit definition for DMA2D_BGPFCCR register *************/
7353
7354#define DMA2D_BGPFCCR_CM_Pos (0U)
7355#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
7356#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
7357#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
7358#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
7359#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
7360#define DMA2D_BGPFCCR_CM_3 0x00000008U
7361#define DMA2D_BGPFCCR_CCM_Pos (4U)
7362#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
7363#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
7364#define DMA2D_BGPFCCR_START_Pos (5U)
7365#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
7366#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
7367#define DMA2D_BGPFCCR_CS_Pos (8U)
7368#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
7369#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
7370#define DMA2D_BGPFCCR_AM_Pos (16U)
7371#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
7372#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
7373#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
7374#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
7375#define DMA2D_BGPFCCR_AI_Pos (20U)
7376#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos)
7377#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk
7378#define DMA2D_BGPFCCR_RBS_Pos (21U)
7379#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos)
7380#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk
7381#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
7382#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
7383#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
7385/******************** Bit definition for DMA2D_BGCOLR register **************/
7386
7387#define DMA2D_BGCOLR_BLUE_Pos (0U)
7388#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
7389#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
7390#define DMA2D_BGCOLR_GREEN_Pos (8U)
7391#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
7392#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
7393#define DMA2D_BGCOLR_RED_Pos (16U)
7394#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
7395#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
7397/******************** Bit definition for DMA2D_FGCMAR register **************/
7398
7399#define DMA2D_FGCMAR_MA_Pos (0U)
7400#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
7401#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
7403/******************** Bit definition for DMA2D_BGCMAR register **************/
7404
7405#define DMA2D_BGCMAR_MA_Pos (0U)
7406#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
7407#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
7409/******************** Bit definition for DMA2D_OPFCCR register **************/
7410
7411#define DMA2D_OPFCCR_CM_Pos (0U)
7412#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
7413#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
7414#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
7415#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
7416#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
7417#define DMA2D_OPFCCR_AI_Pos (20U)
7418#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos)
7419#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk
7420#define DMA2D_OPFCCR_RBS_Pos (21U)
7421#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos)
7422#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk
7424/******************** Bit definition for DMA2D_OCOLR register ***************/
7425
7428#define DMA2D_OCOLR_BLUE_1 0x000000FFU
7429#define DMA2D_OCOLR_GREEN_1 0x0000FF00U
7430#define DMA2D_OCOLR_RED_1 0x00FF0000U
7431#define DMA2D_OCOLR_ALPHA_1 0xFF000000U
7434#define DMA2D_OCOLR_BLUE_2 0x0000001FU
7435#define DMA2D_OCOLR_GREEN_2 0x000007E0U
7436#define DMA2D_OCOLR_RED_2 0x0000F800U
7439#define DMA2D_OCOLR_BLUE_3 0x0000001FU
7440#define DMA2D_OCOLR_GREEN_3 0x000003E0U
7441#define DMA2D_OCOLR_RED_3 0x00007C00U
7442#define DMA2D_OCOLR_ALPHA_3 0x00008000U
7445#define DMA2D_OCOLR_BLUE_4 0x0000000FU
7446#define DMA2D_OCOLR_GREEN_4 0x000000F0U
7447#define DMA2D_OCOLR_RED_4 0x00000F00U
7448#define DMA2D_OCOLR_ALPHA_4 0x0000F000U
7450/******************** Bit definition for DMA2D_OMAR register ****************/
7451
7452#define DMA2D_OMAR_MA_Pos (0U)
7453#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
7454#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
7456/******************** Bit definition for DMA2D_OOR register *****************/
7457
7458#define DMA2D_OOR_LO_Pos (0U)
7459#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos)
7460#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
7462/******************** Bit definition for DMA2D_NLR register *****************/
7463
7464#define DMA2D_NLR_NL_Pos (0U)
7465#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
7466#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
7467#define DMA2D_NLR_PL_Pos (16U)
7468#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
7469#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
7471/******************** Bit definition for DMA2D_LWR register *****************/
7472
7473#define DMA2D_LWR_LW_Pos (0U)
7474#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
7475#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
7477/******************** Bit definition for DMA2D_AMTCR register ***************/
7478
7479#define DMA2D_AMTCR_EN_Pos (0U)
7480#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
7481#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
7482#define DMA2D_AMTCR_DT_Pos (8U)
7483#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
7484#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
7487/******************** Bit definition for DMA2D_FGCLUT register **************/
7488
7489/******************** Bit definition for DMA2D_BGCLUT register **************/
7490
7491/******************************************************************************/
7492/* */
7493/* External Interrupt/Event Controller */
7494/* */
7495/******************************************************************************/
7496/******************* Bit definition for EXTI_IMR register *******************/
7497#define EXTI_IMR_MR0_Pos (0U)
7498#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
7499#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
7500#define EXTI_IMR_MR1_Pos (1U)
7501#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
7502#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
7503#define EXTI_IMR_MR2_Pos (2U)
7504#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
7505#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
7506#define EXTI_IMR_MR3_Pos (3U)
7507#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
7508#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
7509#define EXTI_IMR_MR4_Pos (4U)
7510#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
7511#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
7512#define EXTI_IMR_MR5_Pos (5U)
7513#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
7514#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
7515#define EXTI_IMR_MR6_Pos (6U)
7516#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
7517#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
7518#define EXTI_IMR_MR7_Pos (7U)
7519#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
7520#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
7521#define EXTI_IMR_MR8_Pos (8U)
7522#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
7523#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
7524#define EXTI_IMR_MR9_Pos (9U)
7525#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
7526#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
7527#define EXTI_IMR_MR10_Pos (10U)
7528#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
7529#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
7530#define EXTI_IMR_MR11_Pos (11U)
7531#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
7532#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
7533#define EXTI_IMR_MR12_Pos (12U)
7534#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
7535#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
7536#define EXTI_IMR_MR13_Pos (13U)
7537#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
7538#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
7539#define EXTI_IMR_MR14_Pos (14U)
7540#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
7541#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
7542#define EXTI_IMR_MR15_Pos (15U)
7543#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
7544#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
7545#define EXTI_IMR_MR16_Pos (16U)
7546#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
7547#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
7548#define EXTI_IMR_MR17_Pos (17U)
7549#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
7550#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
7551#define EXTI_IMR_MR18_Pos (18U)
7552#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
7553#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
7554#define EXTI_IMR_MR19_Pos (19U)
7555#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
7556#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
7557#define EXTI_IMR_MR20_Pos (20U)
7558#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
7559#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
7560#define EXTI_IMR_MR21_Pos (21U)
7561#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
7562#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
7563#define EXTI_IMR_MR22_Pos (22U)
7564#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
7565#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
7566#define EXTI_IMR_MR23_Pos (23U)
7567#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos)
7568#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk
7569#define EXTI_IMR_MR24_Pos (24U)
7570#define EXTI_IMR_MR24_Msk (0x1UL << EXTI_IMR_MR24_Pos)
7571#define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk
7573/* Reference Defines */
7574#define EXTI_IMR_IM0 EXTI_IMR_MR0
7575#define EXTI_IMR_IM1 EXTI_IMR_MR1
7576#define EXTI_IMR_IM2 EXTI_IMR_MR2
7577#define EXTI_IMR_IM3 EXTI_IMR_MR3
7578#define EXTI_IMR_IM4 EXTI_IMR_MR4
7579#define EXTI_IMR_IM5 EXTI_IMR_MR5
7580#define EXTI_IMR_IM6 EXTI_IMR_MR6
7581#define EXTI_IMR_IM7 EXTI_IMR_MR7
7582#define EXTI_IMR_IM8 EXTI_IMR_MR8
7583#define EXTI_IMR_IM9 EXTI_IMR_MR9
7584#define EXTI_IMR_IM10 EXTI_IMR_MR10
7585#define EXTI_IMR_IM11 EXTI_IMR_MR11
7586#define EXTI_IMR_IM12 EXTI_IMR_MR12
7587#define EXTI_IMR_IM13 EXTI_IMR_MR13
7588#define EXTI_IMR_IM14 EXTI_IMR_MR14
7589#define EXTI_IMR_IM15 EXTI_IMR_MR15
7590#define EXTI_IMR_IM16 EXTI_IMR_MR16
7591#define EXTI_IMR_IM17 EXTI_IMR_MR17
7592#define EXTI_IMR_IM18 EXTI_IMR_MR18
7593#define EXTI_IMR_IM19 EXTI_IMR_MR19
7594#define EXTI_IMR_IM20 EXTI_IMR_MR20
7595#define EXTI_IMR_IM21 EXTI_IMR_MR21
7596#define EXTI_IMR_IM22 EXTI_IMR_MR22
7597#define EXTI_IMR_IM23 EXTI_IMR_MR23
7598#define EXTI_IMR_IM24 EXTI_IMR_MR24
7599
7600#define EXTI_IMR_IM_Pos (0U)
7601#define EXTI_IMR_IM_Msk (0x1FFFFFFUL << EXTI_IMR_IM_Pos)
7602#define EXTI_IMR_IM EXTI_IMR_IM_Msk
7604/******************* Bit definition for EXTI_EMR register *******************/
7605#define EXTI_EMR_MR0_Pos (0U)
7606#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
7607#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
7608#define EXTI_EMR_MR1_Pos (1U)
7609#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
7610#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
7611#define EXTI_EMR_MR2_Pos (2U)
7612#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
7613#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
7614#define EXTI_EMR_MR3_Pos (3U)
7615#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
7616#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
7617#define EXTI_EMR_MR4_Pos (4U)
7618#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
7619#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
7620#define EXTI_EMR_MR5_Pos (5U)
7621#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
7622#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
7623#define EXTI_EMR_MR6_Pos (6U)
7624#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
7625#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
7626#define EXTI_EMR_MR7_Pos (7U)
7627#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
7628#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
7629#define EXTI_EMR_MR8_Pos (8U)
7630#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
7631#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
7632#define EXTI_EMR_MR9_Pos (9U)
7633#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
7634#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
7635#define EXTI_EMR_MR10_Pos (10U)
7636#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
7637#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
7638#define EXTI_EMR_MR11_Pos (11U)
7639#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
7640#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
7641#define EXTI_EMR_MR12_Pos (12U)
7642#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
7643#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
7644#define EXTI_EMR_MR13_Pos (13U)
7645#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
7646#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
7647#define EXTI_EMR_MR14_Pos (14U)
7648#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
7649#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
7650#define EXTI_EMR_MR15_Pos (15U)
7651#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
7652#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
7653#define EXTI_EMR_MR16_Pos (16U)
7654#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
7655#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
7656#define EXTI_EMR_MR17_Pos (17U)
7657#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
7658#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
7659#define EXTI_EMR_MR18_Pos (18U)
7660#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
7661#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
7662#define EXTI_EMR_MR19_Pos (19U)
7663#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
7664#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
7665#define EXTI_EMR_MR20_Pos (20U)
7666#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
7667#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
7668#define EXTI_EMR_MR21_Pos (21U)
7669#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
7670#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
7671#define EXTI_EMR_MR22_Pos (22U)
7672#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
7673#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
7674#define EXTI_EMR_MR23_Pos (23U)
7675#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos)
7676#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk
7677#define EXTI_EMR_MR24_Pos (24U)
7678#define EXTI_EMR_MR24_Msk (0x1UL << EXTI_EMR_MR24_Pos)
7679#define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk
7681/* Reference Defines */
7682#define EXTI_EMR_EM0 EXTI_EMR_MR0
7683#define EXTI_EMR_EM1 EXTI_EMR_MR1
7684#define EXTI_EMR_EM2 EXTI_EMR_MR2
7685#define EXTI_EMR_EM3 EXTI_EMR_MR3
7686#define EXTI_EMR_EM4 EXTI_EMR_MR4
7687#define EXTI_EMR_EM5 EXTI_EMR_MR5
7688#define EXTI_EMR_EM6 EXTI_EMR_MR6
7689#define EXTI_EMR_EM7 EXTI_EMR_MR7
7690#define EXTI_EMR_EM8 EXTI_EMR_MR8
7691#define EXTI_EMR_EM9 EXTI_EMR_MR9
7692#define EXTI_EMR_EM10 EXTI_EMR_MR10
7693#define EXTI_EMR_EM11 EXTI_EMR_MR11
7694#define EXTI_EMR_EM12 EXTI_EMR_MR12
7695#define EXTI_EMR_EM13 EXTI_EMR_MR13
7696#define EXTI_EMR_EM14 EXTI_EMR_MR14
7697#define EXTI_EMR_EM15 EXTI_EMR_MR15
7698#define EXTI_EMR_EM16 EXTI_EMR_MR16
7699#define EXTI_EMR_EM17 EXTI_EMR_MR17
7700#define EXTI_EMR_EM18 EXTI_EMR_MR18
7701#define EXTI_EMR_EM19 EXTI_EMR_MR19
7702#define EXTI_EMR_EM20 EXTI_EMR_MR20
7703#define EXTI_EMR_EM21 EXTI_EMR_MR21
7704#define EXTI_EMR_EM22 EXTI_EMR_MR22
7705#define EXTI_EMR_EM23 EXTI_EMR_MR23
7706#define EXTI_EMR_EM24 EXTI_EMR_MR24
7707
7708
7709/****************** Bit definition for EXTI_RTSR register *******************/
7710#define EXTI_RTSR_TR0_Pos (0U)
7711#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
7712#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
7713#define EXTI_RTSR_TR1_Pos (1U)
7714#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
7715#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
7716#define EXTI_RTSR_TR2_Pos (2U)
7717#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
7718#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
7719#define EXTI_RTSR_TR3_Pos (3U)
7720#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
7721#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
7722#define EXTI_RTSR_TR4_Pos (4U)
7723#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
7724#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
7725#define EXTI_RTSR_TR5_Pos (5U)
7726#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
7727#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
7728#define EXTI_RTSR_TR6_Pos (6U)
7729#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
7730#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
7731#define EXTI_RTSR_TR7_Pos (7U)
7732#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
7733#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
7734#define EXTI_RTSR_TR8_Pos (8U)
7735#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
7736#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
7737#define EXTI_RTSR_TR9_Pos (9U)
7738#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
7739#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
7740#define EXTI_RTSR_TR10_Pos (10U)
7741#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
7742#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
7743#define EXTI_RTSR_TR11_Pos (11U)
7744#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
7745#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
7746#define EXTI_RTSR_TR12_Pos (12U)
7747#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
7748#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
7749#define EXTI_RTSR_TR13_Pos (13U)
7750#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
7751#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
7752#define EXTI_RTSR_TR14_Pos (14U)
7753#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
7754#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
7755#define EXTI_RTSR_TR15_Pos (15U)
7756#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
7757#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
7758#define EXTI_RTSR_TR16_Pos (16U)
7759#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
7760#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
7761#define EXTI_RTSR_TR17_Pos (17U)
7762#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
7763#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
7764#define EXTI_RTSR_TR18_Pos (18U)
7765#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
7766#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
7767#define EXTI_RTSR_TR19_Pos (19U)
7768#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
7769#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
7770#define EXTI_RTSR_TR20_Pos (20U)
7771#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
7772#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
7773#define EXTI_RTSR_TR21_Pos (21U)
7774#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
7775#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
7776#define EXTI_RTSR_TR22_Pos (22U)
7777#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
7778#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
7779#define EXTI_RTSR_TR23_Pos (23U)
7780#define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos)
7781#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk
7782#define EXTI_RTSR_TR24_Pos (24U)
7783#define EXTI_RTSR_TR24_Msk (0x1UL << EXTI_RTSR_TR24_Pos)
7784#define EXTI_RTSR_TR24 EXTI_RTSR_TR24_Msk
7786/****************** Bit definition for EXTI_FTSR register *******************/
7787#define EXTI_FTSR_TR0_Pos (0U)
7788#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
7789#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
7790#define EXTI_FTSR_TR1_Pos (1U)
7791#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
7792#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
7793#define EXTI_FTSR_TR2_Pos (2U)
7794#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
7795#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
7796#define EXTI_FTSR_TR3_Pos (3U)
7797#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
7798#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
7799#define EXTI_FTSR_TR4_Pos (4U)
7800#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
7801#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
7802#define EXTI_FTSR_TR5_Pos (5U)
7803#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
7804#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
7805#define EXTI_FTSR_TR6_Pos (6U)
7806#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
7807#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
7808#define EXTI_FTSR_TR7_Pos (7U)
7809#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
7810#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
7811#define EXTI_FTSR_TR8_Pos (8U)
7812#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
7813#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
7814#define EXTI_FTSR_TR9_Pos (9U)
7815#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
7816#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
7817#define EXTI_FTSR_TR10_Pos (10U)
7818#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
7819#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
7820#define EXTI_FTSR_TR11_Pos (11U)
7821#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
7822#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
7823#define EXTI_FTSR_TR12_Pos (12U)
7824#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
7825#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
7826#define EXTI_FTSR_TR13_Pos (13U)
7827#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
7828#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
7829#define EXTI_FTSR_TR14_Pos (14U)
7830#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
7831#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
7832#define EXTI_FTSR_TR15_Pos (15U)
7833#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
7834#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
7835#define EXTI_FTSR_TR16_Pos (16U)
7836#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
7837#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
7838#define EXTI_FTSR_TR17_Pos (17U)
7839#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
7840#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
7841#define EXTI_FTSR_TR18_Pos (18U)
7842#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
7843#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
7844#define EXTI_FTSR_TR19_Pos (19U)
7845#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
7846#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
7847#define EXTI_FTSR_TR20_Pos (20U)
7848#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
7849#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
7850#define EXTI_FTSR_TR21_Pos (21U)
7851#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
7852#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
7853#define EXTI_FTSR_TR22_Pos (22U)
7854#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
7855#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
7856#define EXTI_FTSR_TR23_Pos (23U)
7857#define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos)
7858#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk
7859#define EXTI_FTSR_TR24_Pos (24U)
7860#define EXTI_FTSR_TR24_Msk (0x1UL << EXTI_FTSR_TR24_Pos)
7861#define EXTI_FTSR_TR24 EXTI_FTSR_TR24_Msk
7863/****************** Bit definition for EXTI_SWIER register ******************/
7864#define EXTI_SWIER_SWIER0_Pos (0U)
7865#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
7866#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
7867#define EXTI_SWIER_SWIER1_Pos (1U)
7868#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
7869#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
7870#define EXTI_SWIER_SWIER2_Pos (2U)
7871#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
7872#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
7873#define EXTI_SWIER_SWIER3_Pos (3U)
7874#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
7875#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
7876#define EXTI_SWIER_SWIER4_Pos (4U)
7877#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
7878#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
7879#define EXTI_SWIER_SWIER5_Pos (5U)
7880#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
7881#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
7882#define EXTI_SWIER_SWIER6_Pos (6U)
7883#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
7884#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
7885#define EXTI_SWIER_SWIER7_Pos (7U)
7886#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
7887#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
7888#define EXTI_SWIER_SWIER8_Pos (8U)
7889#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
7890#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
7891#define EXTI_SWIER_SWIER9_Pos (9U)
7892#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
7893#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
7894#define EXTI_SWIER_SWIER10_Pos (10U)
7895#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
7896#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
7897#define EXTI_SWIER_SWIER11_Pos (11U)
7898#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
7899#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
7900#define EXTI_SWIER_SWIER12_Pos (12U)
7901#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
7902#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
7903#define EXTI_SWIER_SWIER13_Pos (13U)
7904#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
7905#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
7906#define EXTI_SWIER_SWIER14_Pos (14U)
7907#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
7908#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
7909#define EXTI_SWIER_SWIER15_Pos (15U)
7910#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
7911#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
7912#define EXTI_SWIER_SWIER16_Pos (16U)
7913#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
7914#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
7915#define EXTI_SWIER_SWIER17_Pos (17U)
7916#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
7917#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
7918#define EXTI_SWIER_SWIER18_Pos (18U)
7919#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
7920#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
7921#define EXTI_SWIER_SWIER19_Pos (19U)
7922#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
7923#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
7924#define EXTI_SWIER_SWIER20_Pos (20U)
7925#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
7926#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
7927#define EXTI_SWIER_SWIER21_Pos (21U)
7928#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
7929#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
7930#define EXTI_SWIER_SWIER22_Pos (22U)
7931#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
7932#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
7933#define EXTI_SWIER_SWIER23_Pos (23U)
7934#define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos)
7935#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk
7936#define EXTI_SWIER_SWIER24_Pos (24U)
7937#define EXTI_SWIER_SWIER24_Msk (0x1UL << EXTI_SWIER_SWIER24_Pos)
7938#define EXTI_SWIER_SWIER24 EXTI_SWIER_SWIER24_Msk
7940/******************* Bit definition for EXTI_PR register ********************/
7941#define EXTI_PR_PR0_Pos (0U)
7942#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
7943#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
7944#define EXTI_PR_PR1_Pos (1U)
7945#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
7946#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
7947#define EXTI_PR_PR2_Pos (2U)
7948#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
7949#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
7950#define EXTI_PR_PR3_Pos (3U)
7951#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
7952#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
7953#define EXTI_PR_PR4_Pos (4U)
7954#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
7955#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
7956#define EXTI_PR_PR5_Pos (5U)
7957#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
7958#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
7959#define EXTI_PR_PR6_Pos (6U)
7960#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
7961#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
7962#define EXTI_PR_PR7_Pos (7U)
7963#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
7964#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
7965#define EXTI_PR_PR8_Pos (8U)
7966#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
7967#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
7968#define EXTI_PR_PR9_Pos (9U)
7969#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
7970#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
7971#define EXTI_PR_PR10_Pos (10U)
7972#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
7973#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
7974#define EXTI_PR_PR11_Pos (11U)
7975#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
7976#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
7977#define EXTI_PR_PR12_Pos (12U)
7978#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
7979#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
7980#define EXTI_PR_PR13_Pos (13U)
7981#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
7982#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
7983#define EXTI_PR_PR14_Pos (14U)
7984#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
7985#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
7986#define EXTI_PR_PR15_Pos (15U)
7987#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
7988#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
7989#define EXTI_PR_PR16_Pos (16U)
7990#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
7991#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
7992#define EXTI_PR_PR17_Pos (17U)
7993#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
7994#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
7995#define EXTI_PR_PR18_Pos (18U)
7996#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
7997#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
7998#define EXTI_PR_PR19_Pos (19U)
7999#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
8000#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
8001#define EXTI_PR_PR20_Pos (20U)
8002#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
8003#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
8004#define EXTI_PR_PR21_Pos (21U)
8005#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
8006#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
8007#define EXTI_PR_PR22_Pos (22U)
8008#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
8009#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
8010#define EXTI_PR_PR23_Pos (23U)
8011#define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos)
8012#define EXTI_PR_PR23 EXTI_PR_PR23_Msk
8013#define EXTI_PR_PR24_Pos (24U)
8014#define EXTI_PR_PR24_Msk (0x1UL << EXTI_PR_PR24_Pos)
8015#define EXTI_PR_PR24 EXTI_PR_PR24_Msk
8017/******************************************************************************/
8018/* */
8019/* FLASH */
8020/* */
8021/******************************************************************************/
8022/*
8023* @brief FLASH Total Sectors Number
8024*/
8025#define FLASH_SECTOR_TOTAL 24
8026
8027/******************* Bits definition for FLASH_ACR register *****************/
8028#define FLASH_ACR_LATENCY_Pos (0U)
8029#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
8030#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
8031#define FLASH_ACR_LATENCY_0WS 0x00000000U
8032#define FLASH_ACR_LATENCY_1WS 0x00000001U
8033#define FLASH_ACR_LATENCY_2WS 0x00000002U
8034#define FLASH_ACR_LATENCY_3WS 0x00000003U
8035#define FLASH_ACR_LATENCY_4WS 0x00000004U
8036#define FLASH_ACR_LATENCY_5WS 0x00000005U
8037#define FLASH_ACR_LATENCY_6WS 0x00000006U
8038#define FLASH_ACR_LATENCY_7WS 0x00000007U
8039#define FLASH_ACR_LATENCY_8WS 0x00000008U
8040#define FLASH_ACR_LATENCY_9WS 0x00000009U
8041#define FLASH_ACR_LATENCY_10WS 0x0000000AU
8042#define FLASH_ACR_LATENCY_11WS 0x0000000BU
8043#define FLASH_ACR_LATENCY_12WS 0x0000000CU
8044#define FLASH_ACR_LATENCY_13WS 0x0000000DU
8045#define FLASH_ACR_LATENCY_14WS 0x0000000EU
8046#define FLASH_ACR_LATENCY_15WS 0x0000000FU
8047#define FLASH_ACR_PRFTEN_Pos (8U)
8048#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
8049#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
8050#define FLASH_ACR_ARTEN_Pos (9U)
8051#define FLASH_ACR_ARTEN_Msk (0x1UL << FLASH_ACR_ARTEN_Pos)
8052#define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk
8053#define FLASH_ACR_ARTRST_Pos (11U)
8054#define FLASH_ACR_ARTRST_Msk (0x1UL << FLASH_ACR_ARTRST_Pos)
8055#define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk
8056
8057/******************* Bits definition for FLASH_SR register ******************/
8058#define FLASH_SR_EOP_Pos (0U)
8059#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
8060#define FLASH_SR_EOP FLASH_SR_EOP_Msk
8061#define FLASH_SR_OPERR_Pos (1U)
8062#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
8063#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
8064#define FLASH_SR_WRPERR_Pos (4U)
8065#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
8066#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
8067#define FLASH_SR_PGAERR_Pos (5U)
8068#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
8069#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
8070#define FLASH_SR_PGPERR_Pos (6U)
8071#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
8072#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
8073#define FLASH_SR_ERSERR_Pos (7U)
8074#define FLASH_SR_ERSERR_Msk (0x1UL << FLASH_SR_ERSERR_Pos)
8075#define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk
8076#define FLASH_SR_BSY_Pos (16U)
8077#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
8078#define FLASH_SR_BSY FLASH_SR_BSY_Msk
8079
8080/******************* Bits definition for FLASH_CR register ******************/
8081#define FLASH_CR_PG_Pos (0U)
8082#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
8083#define FLASH_CR_PG FLASH_CR_PG_Msk
8084#define FLASH_CR_SER_Pos (1U)
8085#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
8086#define FLASH_CR_SER FLASH_CR_SER_Msk
8087#define FLASH_CR_MER_Pos (2U)
8088#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
8089#define FLASH_CR_MER FLASH_CR_MER_Msk
8090#define FLASH_CR_MER1 FLASH_CR_MER
8091#define FLASH_CR_SNB_Pos (3U)
8092#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
8093#define FLASH_CR_SNB FLASH_CR_SNB_Msk
8094#define FLASH_CR_SNB_0 0x00000008U
8095#define FLASH_CR_SNB_1 0x00000010U
8096#define FLASH_CR_SNB_2 0x00000020U
8097#define FLASH_CR_SNB_3 0x00000040U
8098#define FLASH_CR_SNB_4 0x00000080U
8099#define FLASH_CR_PSIZE_Pos (8U)
8100#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
8101#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
8102#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
8103#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
8104#define FLASH_CR_MER2_Pos (15U)
8105#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos)
8106#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
8107#define FLASH_CR_STRT_Pos (16U)
8108#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
8109#define FLASH_CR_STRT FLASH_CR_STRT_Msk
8110#define FLASH_CR_EOPIE_Pos (24U)
8111#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
8112#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
8113#define FLASH_CR_ERRIE_Pos (25U)
8114#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
8115#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
8116#define FLASH_CR_LOCK_Pos (31U)
8117#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
8118#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
8119
8120/******************* Bits definition for FLASH_OPTCR register ***************/
8121#define FLASH_OPTCR_OPTLOCK_Pos (0U)
8122#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
8123#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
8124#define FLASH_OPTCR_OPTSTRT_Pos (1U)
8125#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
8126#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
8127#define FLASH_OPTCR_BOR_LEV_Pos (2U)
8128#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
8129#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
8130#define FLASH_OPTCR_BOR_LEV_0 (0x1UL << FLASH_OPTCR_BOR_LEV_Pos)
8131#define FLASH_OPTCR_BOR_LEV_1 (0x2UL << FLASH_OPTCR_BOR_LEV_Pos)
8132#define FLASH_OPTCR_WWDG_SW_Pos (4U)
8133#define FLASH_OPTCR_WWDG_SW_Msk (0x1UL << FLASH_OPTCR_WWDG_SW_Pos)
8134#define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk
8135#define FLASH_OPTCR_IWDG_SW_Pos (5U)
8136#define FLASH_OPTCR_IWDG_SW_Msk (0x1UL << FLASH_OPTCR_IWDG_SW_Pos)
8137#define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk
8138#define FLASH_OPTCR_nRST_STOP_Pos (6U)
8139#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
8140#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
8141#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
8142#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
8143#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
8144#define FLASH_OPTCR_RDP_Pos (8U)
8145#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
8146#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
8147#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
8148#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
8149#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
8150#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
8151#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
8152#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
8153#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
8154#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
8155#define FLASH_OPTCR_nWRP_Pos (16U)
8156#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
8157#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
8158#define FLASH_OPTCR_nWRP_0 0x00010000U
8159#define FLASH_OPTCR_nWRP_1 0x00020000U
8160#define FLASH_OPTCR_nWRP_2 0x00040000U
8161#define FLASH_OPTCR_nWRP_3 0x00080000U
8162#define FLASH_OPTCR_nWRP_4 0x00100000U
8163#define FLASH_OPTCR_nWRP_5 0x00200000U
8164#define FLASH_OPTCR_nWRP_6 0x00400000U
8165#define FLASH_OPTCR_nWRP_7 0x00800000U
8166#define FLASH_OPTCR_nWRP_8 0x01000000U
8167#define FLASH_OPTCR_nWRP_9 0x02000000U
8168#define FLASH_OPTCR_nWRP_10 0x04000000U
8169#define FLASH_OPTCR_nWRP_11 0x08000000U
8170#define FLASH_OPTCR_nDBOOT_Pos (28U)
8171#define FLASH_OPTCR_nDBOOT_Msk (0x1UL << FLASH_OPTCR_nDBOOT_Pos)
8172#define FLASH_OPTCR_nDBOOT FLASH_OPTCR_nDBOOT_Msk
8173#define FLASH_OPTCR_nDBANK_Pos (29U)
8174#define FLASH_OPTCR_nDBANK_Msk (0x1UL << FLASH_OPTCR_nDBANK_Pos)
8175#define FLASH_OPTCR_nDBANK FLASH_OPTCR_nDBANK_Msk
8176#define FLASH_OPTCR_IWDG_STDBY_Pos (30U)
8177#define FLASH_OPTCR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTCR_IWDG_STDBY_Pos)
8178#define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk
8179#define FLASH_OPTCR_IWDG_STOP_Pos (31U)
8180#define FLASH_OPTCR_IWDG_STOP_Msk (0x1UL << FLASH_OPTCR_IWDG_STOP_Pos)
8181#define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk
8182
8183/******************* Bits definition for FLASH_OPTCR1 register ***************/
8184#define FLASH_OPTCR1_BOOT_ADD0_Pos (0U)
8185#define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD0_Pos)
8186#define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk
8187#define FLASH_OPTCR1_BOOT_ADD1_Pos (16U)
8188#define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD1_Pos)
8189#define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk
8190
8191
8192/******************************************************************************/
8193/* */
8194/* Flexible Memory Controller */
8195/* */
8196/******************************************************************************/
8197/****************** Bit definition for FMC_BCR1 register *******************/
8198#define FMC_BCR1_MBKEN_Pos (0U)
8199#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)
8200#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk
8201#define FMC_BCR1_MUXEN_Pos (1U)
8202#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)
8203#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk
8204#define FMC_BCR1_MTYP_Pos (2U)
8205#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)
8206#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk
8207#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)
8208#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)
8209#define FMC_BCR1_MWID_Pos (4U)
8210#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)
8211#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk
8212#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)
8213#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)
8214#define FMC_BCR1_FACCEN_Pos (6U)
8215#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)
8216#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk
8217#define FMC_BCR1_BURSTEN_Pos (8U)
8218#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)
8219#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk
8220#define FMC_BCR1_WAITPOL_Pos (9U)
8221#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)
8222#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk
8223#define FMC_BCR1_WRAPMOD_Pos (10U)
8224#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos)
8225#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk
8226#define FMC_BCR1_WAITCFG_Pos (11U)
8227#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)
8228#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk
8229#define FMC_BCR1_WREN_Pos (12U)
8230#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)
8231#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk
8232#define FMC_BCR1_WAITEN_Pos (13U)
8233#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)
8234#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk
8235#define FMC_BCR1_EXTMOD_Pos (14U)
8236#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)
8237#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk
8238#define FMC_BCR1_ASYNCWAIT_Pos (15U)
8239#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)
8240#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk
8241#define FMC_BCR1_CPSIZE_Pos (16U)
8242#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos)
8243#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk
8244#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos)
8245#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos)
8246#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos)
8247#define FMC_BCR1_CBURSTRW_Pos (19U)
8248#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)
8249#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk
8250#define FMC_BCR1_CCLKEN_Pos (20U)
8251#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
8252#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
8253#define FMC_BCR1_WFDIS_Pos (21U)
8254#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
8255#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
8257/****************** Bit definition for FMC_BCR2 register *******************/
8258#define FMC_BCR2_MBKEN_Pos (0U)
8259#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)
8260#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk
8261#define FMC_BCR2_MUXEN_Pos (1U)
8262#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)
8263#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk
8264#define FMC_BCR2_MTYP_Pos (2U)
8265#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)
8266#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk
8267#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)
8268#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)
8269#define FMC_BCR2_MWID_Pos (4U)
8270#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)
8271#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk
8272#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)
8273#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)
8274#define FMC_BCR2_FACCEN_Pos (6U)
8275#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)
8276#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk
8277#define FMC_BCR2_BURSTEN_Pos (8U)
8278#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)
8279#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk
8280#define FMC_BCR2_WAITPOL_Pos (9U)
8281#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)
8282#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk
8283#define FMC_BCR2_WRAPMOD_Pos (10U)
8284#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos)
8285#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk
8286#define FMC_BCR2_WAITCFG_Pos (11U)
8287#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)
8288#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk
8289#define FMC_BCR2_WREN_Pos (12U)
8290#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)
8291#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk
8292#define FMC_BCR2_WAITEN_Pos (13U)
8293#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)
8294#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk
8295#define FMC_BCR2_EXTMOD_Pos (14U)
8296#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)
8297#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk
8298#define FMC_BCR2_ASYNCWAIT_Pos (15U)
8299#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)
8300#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk
8301#define FMC_BCR2_CPSIZE_Pos (16U)
8302#define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos)
8303#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk
8304#define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos)
8305#define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos)
8306#define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos)
8307#define FMC_BCR2_CBURSTRW_Pos (19U)
8308#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)
8309#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk
8311/****************** Bit definition for FMC_BCR3 register *******************/
8312#define FMC_BCR3_MBKEN_Pos (0U)
8313#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)
8314#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk
8315#define FMC_BCR3_MUXEN_Pos (1U)
8316#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)
8317#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk
8318#define FMC_BCR3_MTYP_Pos (2U)
8319#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)
8320#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk
8321#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)
8322#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)
8323#define FMC_BCR3_MWID_Pos (4U)
8324#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)
8325#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk
8326#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)
8327#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)
8328#define FMC_BCR3_FACCEN_Pos (6U)
8329#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)
8330#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk
8331#define FMC_BCR3_BURSTEN_Pos (8U)
8332#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)
8333#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk
8334#define FMC_BCR3_WAITPOL_Pos (9U)
8335#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)
8336#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk
8337#define FMC_BCR3_WRAPMOD_Pos (10U)
8338#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos)
8339#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk
8340#define FMC_BCR3_WAITCFG_Pos (11U)
8341#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)
8342#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk
8343#define FMC_BCR3_WREN_Pos (12U)
8344#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)
8345#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk
8346#define FMC_BCR3_WAITEN_Pos (13U)
8347#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)
8348#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk
8349#define FMC_BCR3_EXTMOD_Pos (14U)
8350#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)
8351#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk
8352#define FMC_BCR3_ASYNCWAIT_Pos (15U)
8353#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)
8354#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk
8355#define FMC_BCR3_CPSIZE_Pos (16U)
8356#define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos)
8357#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk
8358#define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos)
8359#define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos)
8360#define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos)
8361#define FMC_BCR3_CBURSTRW_Pos (19U)
8362#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)
8363#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk
8365/****************** Bit definition for FMC_BCR4 register *******************/
8366#define FMC_BCR4_MBKEN_Pos (0U)
8367#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)
8368#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk
8369#define FMC_BCR4_MUXEN_Pos (1U)
8370#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)
8371#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk
8372#define FMC_BCR4_MTYP_Pos (2U)
8373#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)
8374#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk
8375#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)
8376#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)
8377#define FMC_BCR4_MWID_Pos (4U)
8378#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)
8379#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk
8380#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)
8381#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)
8382#define FMC_BCR4_FACCEN_Pos (6U)
8383#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)
8384#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk
8385#define FMC_BCR4_BURSTEN_Pos (8U)
8386#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)
8387#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk
8388#define FMC_BCR4_WAITPOL_Pos (9U)
8389#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)
8390#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk
8391#define FMC_BCR4_WRAPMOD_Pos (10U)
8392#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos)
8393#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk
8394#define FMC_BCR4_WAITCFG_Pos (11U)
8395#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)
8396#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk
8397#define FMC_BCR4_WREN_Pos (12U)
8398#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)
8399#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk
8400#define FMC_BCR4_WAITEN_Pos (13U)
8401#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)
8402#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk
8403#define FMC_BCR4_EXTMOD_Pos (14U)
8404#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)
8405#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk
8406#define FMC_BCR4_ASYNCWAIT_Pos (15U)
8407#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)
8408#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk
8409#define FMC_BCR4_CPSIZE_Pos (16U)
8410#define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos)
8411#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk
8412#define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos)
8413#define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos)
8414#define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos)
8415#define FMC_BCR4_CBURSTRW_Pos (19U)
8416#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)
8417#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk
8419/****************** Bit definition for FMC_BTR1 register ******************/
8420#define FMC_BTR1_ADDSET_Pos (0U)
8421#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)
8422#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk
8423#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)
8424#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)
8425#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)
8426#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)
8427#define FMC_BTR1_ADDHLD_Pos (4U)
8428#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)
8429#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk
8430#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)
8431#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)
8432#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)
8433#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)
8434#define FMC_BTR1_DATAST_Pos (8U)
8435#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)
8436#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk
8437#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)
8438#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)
8439#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)
8440#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)
8441#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)
8442#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)
8443#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)
8444#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)
8445#define FMC_BTR1_BUSTURN_Pos (16U)
8446#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)
8447#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk
8448#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)
8449#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)
8450#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)
8451#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)
8452#define FMC_BTR1_CLKDIV_Pos (20U)
8453#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)
8454#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk
8455#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)
8456#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)
8457#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)
8458#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)
8459#define FMC_BTR1_DATLAT_Pos (24U)
8460#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)
8461#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk
8462#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)
8463#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)
8464#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)
8465#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)
8466#define FMC_BTR1_ACCMOD_Pos (28U)
8467#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)
8468#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk
8469#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)
8470#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)
8472/****************** Bit definition for FMC_BTR2 register *******************/
8473#define FMC_BTR2_ADDSET_Pos (0U)
8474#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)
8475#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk
8476#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)
8477#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)
8478#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)
8479#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)
8480#define FMC_BTR2_ADDHLD_Pos (4U)
8481#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)
8482#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk
8483#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)
8484#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)
8485#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)
8486#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)
8487#define FMC_BTR2_DATAST_Pos (8U)
8488#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)
8489#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk
8490#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)
8491#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)
8492#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)
8493#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)
8494#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)
8495#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)
8496#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)
8497#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)
8498#define FMC_BTR2_BUSTURN_Pos (16U)
8499#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)
8500#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk
8501#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)
8502#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)
8503#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)
8504#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)
8505#define FMC_BTR2_CLKDIV_Pos (20U)
8506#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)
8507#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk
8508#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)
8509#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)
8510#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)
8511#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)
8512#define FMC_BTR2_DATLAT_Pos (24U)
8513#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)
8514#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk
8515#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)
8516#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)
8517#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)
8518#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)
8519#define FMC_BTR2_ACCMOD_Pos (28U)
8520#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)
8521#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk
8522#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)
8523#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)
8525/******************* Bit definition for FMC_BTR3 register *******************/
8526#define FMC_BTR3_ADDSET_Pos (0U)
8527#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)
8528#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk
8529#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)
8530#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)
8531#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)
8532#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)
8533#define FMC_BTR3_ADDHLD_Pos (4U)
8534#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)
8535#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk
8536#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)
8537#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)
8538#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)
8539#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)
8540#define FMC_BTR3_DATAST_Pos (8U)
8541#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)
8542#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk
8543#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)
8544#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)
8545#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)
8546#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)
8547#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)
8548#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)
8549#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)
8550#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)
8551#define FMC_BTR3_BUSTURN_Pos (16U)
8552#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)
8553#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk
8554#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)
8555#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)
8556#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)
8557#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)
8558#define FMC_BTR3_CLKDIV_Pos (20U)
8559#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)
8560#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk
8561#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)
8562#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)
8563#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)
8564#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)
8565#define FMC_BTR3_DATLAT_Pos (24U)
8566#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)
8567#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk
8568#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)
8569#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)
8570#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)
8571#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)
8572#define FMC_BTR3_ACCMOD_Pos (28U)
8573#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)
8574#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk
8575#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)
8576#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)
8578/****************** Bit definition for FMC_BTR4 register *******************/
8579#define FMC_BTR4_ADDSET_Pos (0U)
8580#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)
8581#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk
8582#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)
8583#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)
8584#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)
8585#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)
8586#define FMC_BTR4_ADDHLD_Pos (4U)
8587#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)
8588#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk
8589#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)
8590#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)
8591#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)
8592#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)
8593#define FMC_BTR4_DATAST_Pos (8U)
8594#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)
8595#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk
8596#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)
8597#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)
8598#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)
8599#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)
8600#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)
8601#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)
8602#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)
8603#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)
8604#define FMC_BTR4_BUSTURN_Pos (16U)
8605#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)
8606#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk
8607#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)
8608#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)
8609#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)
8610#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)
8611#define FMC_BTR4_CLKDIV_Pos (20U)
8612#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)
8613#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk
8614#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)
8615#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)
8616#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)
8617#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)
8618#define FMC_BTR4_DATLAT_Pos (24U)
8619#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)
8620#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk
8621#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)
8622#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)
8623#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)
8624#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)
8625#define FMC_BTR4_ACCMOD_Pos (28U)
8626#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)
8627#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk
8628#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)
8629#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)
8631/****************** Bit definition for FMC_BWTR1 register ******************/
8632#define FMC_BWTR1_ADDSET_Pos (0U)
8633#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)
8634#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk
8635#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)
8636#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)
8637#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)
8638#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)
8639#define FMC_BWTR1_ADDHLD_Pos (4U)
8640#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)
8641#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk
8642#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)
8643#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)
8644#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)
8645#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)
8646#define FMC_BWTR1_DATAST_Pos (8U)
8647#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)
8648#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk
8649#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)
8650#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)
8651#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)
8652#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)
8653#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)
8654#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)
8655#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)
8656#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)
8657#define FMC_BWTR1_BUSTURN_Pos (16U)
8658#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos)
8659#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk
8660#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos)
8661#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos)
8662#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos)
8663#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos)
8664#define FMC_BWTR1_ACCMOD_Pos (28U)
8665#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)
8666#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk
8667#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)
8668#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)
8670/****************** Bit definition for FMC_BWTR2 register ******************/
8671#define FMC_BWTR2_ADDSET_Pos (0U)
8672#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)
8673#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk
8674#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)
8675#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)
8676#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)
8677#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)
8678#define FMC_BWTR2_ADDHLD_Pos (4U)
8679#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)
8680#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk
8681#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)
8682#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)
8683#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)
8684#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)
8685#define FMC_BWTR2_DATAST_Pos (8U)
8686#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)
8687#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk
8688#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)
8689#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)
8690#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)
8691#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)
8692#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)
8693#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)
8694#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)
8695#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)
8696#define FMC_BWTR2_BUSTURN_Pos (16U)
8697#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos)
8698#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk
8699#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos)
8700#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos)
8701#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos)
8702#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos)
8703#define FMC_BWTR2_ACCMOD_Pos (28U)
8704#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)
8705#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk
8706#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)
8707#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)
8709/****************** Bit definition for FMC_BWTR3 register ******************/
8710#define FMC_BWTR3_ADDSET_Pos (0U)
8711#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)
8712#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk
8713#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)
8714#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)
8715#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)
8716#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)
8717#define FMC_BWTR3_ADDHLD_Pos (4U)
8718#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)
8719#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk
8720#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)
8721#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)
8722#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)
8723#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)
8724#define FMC_BWTR3_DATAST_Pos (8U)
8725#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)
8726#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk
8727#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)
8728#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)
8729#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)
8730#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)
8731#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)
8732#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)
8733#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)
8734#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)
8735#define FMC_BWTR3_BUSTURN_Pos (16U)
8736#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos)
8737#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk
8738#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos)
8739#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos)
8740#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos)
8741#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos)
8742#define FMC_BWTR3_ACCMOD_Pos (28U)
8743#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)
8744#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk
8745#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)
8746#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)
8748/****************** Bit definition for FMC_BWTR4 register ******************/
8749#define FMC_BWTR4_ADDSET_Pos (0U)
8750#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)
8751#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk
8752#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)
8753#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)
8754#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)
8755#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)
8756#define FMC_BWTR4_ADDHLD_Pos (4U)
8757#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)
8758#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk
8759#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)
8760#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)
8761#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)
8762#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)
8763#define FMC_BWTR4_DATAST_Pos (8U)
8764#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)
8765#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk
8766#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)
8767#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)
8768#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)
8769#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)
8770#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)
8771#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)
8772#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)
8773#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)
8774#define FMC_BWTR4_BUSTURN_Pos (16U)
8775#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos)
8776#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk
8777#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos)
8778#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos)
8779#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos)
8780#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos)
8781#define FMC_BWTR4_ACCMOD_Pos (28U)
8782#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)
8783#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk
8784#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)
8785#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)
8787/****************** Bit definition for FMC_PCR register *******************/
8788#define FMC_PCR_PWAITEN_Pos (1U)
8789#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
8790#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
8791#define FMC_PCR_PBKEN_Pos (2U)
8792#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
8793#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
8794#define FMC_PCR_PTYP_Pos (3U)
8795#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
8796#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
8797#define FMC_PCR_PWID_Pos (4U)
8798#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
8799#define FMC_PCR_PWID FMC_PCR_PWID_Msk
8800#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
8801#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
8802#define FMC_PCR_ECCEN_Pos (6U)
8803#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
8804#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
8805#define FMC_PCR_TCLR_Pos (9U)
8806#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
8807#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
8808#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
8809#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
8810#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
8811#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
8812#define FMC_PCR_TAR_Pos (13U)
8813#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
8814#define FMC_PCR_TAR FMC_PCR_TAR_Msk
8815#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
8816#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
8817#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
8818#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
8819#define FMC_PCR_ECCPS_Pos (17U)
8820#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
8821#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
8822#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
8823#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
8824#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
8826/******************* Bit definition for FMC_SR register *******************/
8827#define FMC_SR_IRS_Pos (0U)
8828#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
8829#define FMC_SR_IRS FMC_SR_IRS_Msk
8830#define FMC_SR_ILS_Pos (1U)
8831#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
8832#define FMC_SR_ILS FMC_SR_ILS_Msk
8833#define FMC_SR_IFS_Pos (2U)
8834#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
8835#define FMC_SR_IFS FMC_SR_IFS_Msk
8836#define FMC_SR_IREN_Pos (3U)
8837#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
8838#define FMC_SR_IREN FMC_SR_IREN_Msk
8839#define FMC_SR_ILEN_Pos (4U)
8840#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
8841#define FMC_SR_ILEN FMC_SR_ILEN_Msk
8842#define FMC_SR_IFEN_Pos (5U)
8843#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
8844#define FMC_SR_IFEN FMC_SR_IFEN_Msk
8845#define FMC_SR_FEMPT_Pos (6U)
8846#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
8847#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
8849/****************** Bit definition for FMC_PMEM register ******************/
8850#define FMC_PMEM_MEMSET3_Pos (0U)
8851#define FMC_PMEM_MEMSET3_Msk (0xFFUL << FMC_PMEM_MEMSET3_Pos)
8852#define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk
8853#define FMC_PMEM_MEMSET3_0 (0x01UL << FMC_PMEM_MEMSET3_Pos)
8854#define FMC_PMEM_MEMSET3_1 (0x02UL << FMC_PMEM_MEMSET3_Pos)
8855#define FMC_PMEM_MEMSET3_2 (0x04UL << FMC_PMEM_MEMSET3_Pos)
8856#define FMC_PMEM_MEMSET3_3 (0x08UL << FMC_PMEM_MEMSET3_Pos)
8857#define FMC_PMEM_MEMSET3_4 (0x10UL << FMC_PMEM_MEMSET3_Pos)
8858#define FMC_PMEM_MEMSET3_5 (0x20UL << FMC_PMEM_MEMSET3_Pos)
8859#define FMC_PMEM_MEMSET3_6 (0x40UL << FMC_PMEM_MEMSET3_Pos)
8860#define FMC_PMEM_MEMSET3_7 (0x80UL << FMC_PMEM_MEMSET3_Pos)
8861#define FMC_PMEM_MEMWAIT3_Pos (8U)
8862#define FMC_PMEM_MEMWAIT3_Msk (0xFFUL << FMC_PMEM_MEMWAIT3_Pos)
8863#define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk
8864#define FMC_PMEM_MEMWAIT3_0 (0x01UL << FMC_PMEM_MEMWAIT3_Pos)
8865#define FMC_PMEM_MEMWAIT3_1 (0x02UL << FMC_PMEM_MEMWAIT3_Pos)
8866#define FMC_PMEM_MEMWAIT3_2 (0x04UL << FMC_PMEM_MEMWAIT3_Pos)
8867#define FMC_PMEM_MEMWAIT3_3 (0x08UL << FMC_PMEM_MEMWAIT3_Pos)
8868#define FMC_PMEM_MEMWAIT3_4 (0x10UL << FMC_PMEM_MEMWAIT3_Pos)
8869#define FMC_PMEM_MEMWAIT3_5 (0x20UL << FMC_PMEM_MEMWAIT3_Pos)
8870#define FMC_PMEM_MEMWAIT3_6 (0x40UL << FMC_PMEM_MEMWAIT3_Pos)
8871#define FMC_PMEM_MEMWAIT3_7 (0x80UL << FMC_PMEM_MEMWAIT3_Pos)
8872#define FMC_PMEM_MEMHOLD3_Pos (16U)
8873#define FMC_PMEM_MEMHOLD3_Msk (0xFFUL << FMC_PMEM_MEMHOLD3_Pos)
8874#define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk
8875#define FMC_PMEM_MEMHOLD3_0 (0x01UL << FMC_PMEM_MEMHOLD3_Pos)
8876#define FMC_PMEM_MEMHOLD3_1 (0x02UL << FMC_PMEM_MEMHOLD3_Pos)
8877#define FMC_PMEM_MEMHOLD3_2 (0x04UL << FMC_PMEM_MEMHOLD3_Pos)
8878#define FMC_PMEM_MEMHOLD3_3 (0x08UL << FMC_PMEM_MEMHOLD3_Pos)
8879#define FMC_PMEM_MEMHOLD3_4 (0x10UL << FMC_PMEM_MEMHOLD3_Pos)
8880#define FMC_PMEM_MEMHOLD3_5 (0x20UL << FMC_PMEM_MEMHOLD3_Pos)
8881#define FMC_PMEM_MEMHOLD3_6 (0x40UL << FMC_PMEM_MEMHOLD3_Pos)
8882#define FMC_PMEM_MEMHOLD3_7 (0x80UL << FMC_PMEM_MEMHOLD3_Pos)
8883#define FMC_PMEM_MEMHIZ3_Pos (24U)
8884#define FMC_PMEM_MEMHIZ3_Msk (0xFFUL << FMC_PMEM_MEMHIZ3_Pos)
8885#define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk
8886#define FMC_PMEM_MEMHIZ3_0 (0x01UL << FMC_PMEM_MEMHIZ3_Pos)
8887#define FMC_PMEM_MEMHIZ3_1 (0x02UL << FMC_PMEM_MEMHIZ3_Pos)
8888#define FMC_PMEM_MEMHIZ3_2 (0x04UL << FMC_PMEM_MEMHIZ3_Pos)
8889#define FMC_PMEM_MEMHIZ3_3 (0x08UL << FMC_PMEM_MEMHIZ3_Pos)
8890#define FMC_PMEM_MEMHIZ3_4 (0x10UL << FMC_PMEM_MEMHIZ3_Pos)
8891#define FMC_PMEM_MEMHIZ3_5 (0x20UL << FMC_PMEM_MEMHIZ3_Pos)
8892#define FMC_PMEM_MEMHIZ3_6 (0x40UL << FMC_PMEM_MEMHIZ3_Pos)
8893#define FMC_PMEM_MEMHIZ3_7 (0x80UL << FMC_PMEM_MEMHIZ3_Pos)
8895/****************** Bit definition for FMC_PATT register ******************/
8896#define FMC_PATT_ATTSET3_Pos (0U)
8897#define FMC_PATT_ATTSET3_Msk (0xFFUL << FMC_PATT_ATTSET3_Pos)
8898#define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk
8899#define FMC_PATT_ATTSET3_0 (0x01UL << FMC_PATT_ATTSET3_Pos)
8900#define FMC_PATT_ATTSET3_1 (0x02UL << FMC_PATT_ATTSET3_Pos)
8901#define FMC_PATT_ATTSET3_2 (0x04UL << FMC_PATT_ATTSET3_Pos)
8902#define FMC_PATT_ATTSET3_3 (0x08UL << FMC_PATT_ATTSET3_Pos)
8903#define FMC_PATT_ATTSET3_4 (0x10UL << FMC_PATT_ATTSET3_Pos)
8904#define FMC_PATT_ATTSET3_5 (0x20UL << FMC_PATT_ATTSET3_Pos)
8905#define FMC_PATT_ATTSET3_6 (0x40UL << FMC_PATT_ATTSET3_Pos)
8906#define FMC_PATT_ATTSET3_7 (0x80UL << FMC_PATT_ATTSET3_Pos)
8907#define FMC_PATT_ATTWAIT3_Pos (8U)
8908#define FMC_PATT_ATTWAIT3_Msk (0xFFUL << FMC_PATT_ATTWAIT3_Pos)
8909#define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk
8910#define FMC_PATT_ATTWAIT3_0 (0x01UL << FMC_PATT_ATTWAIT3_Pos)
8911#define FMC_PATT_ATTWAIT3_1 (0x02UL << FMC_PATT_ATTWAIT3_Pos)
8912#define FMC_PATT_ATTWAIT3_2 (0x04UL << FMC_PATT_ATTWAIT3_Pos)
8913#define FMC_PATT_ATTWAIT3_3 (0x08UL << FMC_PATT_ATTWAIT3_Pos)
8914#define FMC_PATT_ATTWAIT3_4 (0x10UL << FMC_PATT_ATTWAIT3_Pos)
8915#define FMC_PATT_ATTWAIT3_5 (0x20UL << FMC_PATT_ATTWAIT3_Pos)
8916#define FMC_PATT_ATTWAIT3_6 (0x40UL << FMC_PATT_ATTWAIT3_Pos)
8917#define FMC_PATT_ATTWAIT3_7 (0x80UL << FMC_PATT_ATTWAIT3_Pos)
8918#define FMC_PATT_ATTHOLD3_Pos (16U)
8919#define FMC_PATT_ATTHOLD3_Msk (0xFFUL << FMC_PATT_ATTHOLD3_Pos)
8920#define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk
8921#define FMC_PATT_ATTHOLD3_0 (0x01UL << FMC_PATT_ATTHOLD3_Pos)
8922#define FMC_PATT_ATTHOLD3_1 (0x02UL << FMC_PATT_ATTHOLD3_Pos)
8923#define FMC_PATT_ATTHOLD3_2 (0x04UL << FMC_PATT_ATTHOLD3_Pos)
8924#define FMC_PATT_ATTHOLD3_3 (0x08UL << FMC_PATT_ATTHOLD3_Pos)
8925#define FMC_PATT_ATTHOLD3_4 (0x10UL << FMC_PATT_ATTHOLD3_Pos)
8926#define FMC_PATT_ATTHOLD3_5 (0x20UL << FMC_PATT_ATTHOLD3_Pos)
8927#define FMC_PATT_ATTHOLD3_6 (0x40UL << FMC_PATT_ATTHOLD3_Pos)
8928#define FMC_PATT_ATTHOLD3_7 (0x80UL << FMC_PATT_ATTHOLD3_Pos)
8929#define FMC_PATT_ATTHIZ3_Pos (24U)
8930#define FMC_PATT_ATTHIZ3_Msk (0xFFUL << FMC_PATT_ATTHIZ3_Pos)
8931#define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk
8932#define FMC_PATT_ATTHIZ3_0 (0x01UL << FMC_PATT_ATTHIZ3_Pos)
8933#define FMC_PATT_ATTHIZ3_1 (0x02UL << FMC_PATT_ATTHIZ3_Pos)
8934#define FMC_PATT_ATTHIZ3_2 (0x04UL << FMC_PATT_ATTHIZ3_Pos)
8935#define FMC_PATT_ATTHIZ3_3 (0x08UL << FMC_PATT_ATTHIZ3_Pos)
8936#define FMC_PATT_ATTHIZ3_4 (0x10UL << FMC_PATT_ATTHIZ3_Pos)
8937#define FMC_PATT_ATTHIZ3_5 (0x20UL << FMC_PATT_ATTHIZ3_Pos)
8938#define FMC_PATT_ATTHIZ3_6 (0x40UL << FMC_PATT_ATTHIZ3_Pos)
8939#define FMC_PATT_ATTHIZ3_7 (0x80UL << FMC_PATT_ATTHIZ3_Pos)
8941/****************** Bit definition for FMC_ECCR register ******************/
8942#define FMC_ECCR_ECC3_Pos (0U)
8943#define FMC_ECCR_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC3_Pos)
8944#define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk
8946/****************** Bit definition for FMC_SDCR1 register ******************/
8947#define FMC_SDCR1_NC_Pos (0U)
8948#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos)
8949#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk
8950#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos)
8951#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos)
8952#define FMC_SDCR1_NR_Pos (2U)
8953#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos)
8954#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk
8955#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos)
8956#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos)
8957#define FMC_SDCR1_MWID_Pos (4U)
8958#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos)
8959#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk
8960#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos)
8961#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos)
8962#define FMC_SDCR1_NB_Pos (6U)
8963#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos)
8964#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk
8965#define FMC_SDCR1_CAS_Pos (7U)
8966#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos)
8967#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk
8968#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos)
8969#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos)
8970#define FMC_SDCR1_WP_Pos (9U)
8971#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos)
8972#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk
8973#define FMC_SDCR1_SDCLK_Pos (10U)
8974#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos)
8975#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk
8976#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos)
8977#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos)
8978#define FMC_SDCR1_RBURST_Pos (12U)
8979#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos)
8980#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk
8981#define FMC_SDCR1_RPIPE_Pos (13U)
8982#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos)
8983#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk
8984#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos)
8985#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos)
8987/****************** Bit definition for FMC_SDCR2 register ******************/
8988#define FMC_SDCR2_NC_Pos (0U)
8989#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos)
8990#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk
8991#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos)
8992#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos)
8993#define FMC_SDCR2_NR_Pos (2U)
8994#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos)
8995#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk
8996#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos)
8997#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos)
8998#define FMC_SDCR2_MWID_Pos (4U)
8999#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos)
9000#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk
9001#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos)
9002#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos)
9003#define FMC_SDCR2_NB_Pos (6U)
9004#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos)
9005#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk
9006#define FMC_SDCR2_CAS_Pos (7U)
9007#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos)
9008#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk
9009#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos)
9010#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos)
9011#define FMC_SDCR2_WP_Pos (9U)
9012#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos)
9013#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk
9014#define FMC_SDCR2_SDCLK_Pos (10U)
9015#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos)
9016#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk
9017#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos)
9018#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos)
9019#define FMC_SDCR2_RBURST_Pos (12U)
9020#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos)
9021#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk
9022#define FMC_SDCR2_RPIPE_Pos (13U)
9023#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos)
9024#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk
9025#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos)
9026#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos)
9028/****************** Bit definition for FMC_SDTR1 register ******************/
9029#define FMC_SDTR1_TMRD_Pos (0U)
9030#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos)
9031#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk
9032#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos)
9033#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos)
9034#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos)
9035#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos)
9036#define FMC_SDTR1_TXSR_Pos (4U)
9037#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos)
9038#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk
9039#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos)
9040#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos)
9041#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos)
9042#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos)
9043#define FMC_SDTR1_TRAS_Pos (8U)
9044#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos)
9045#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk
9046#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos)
9047#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos)
9048#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos)
9049#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos)
9050#define FMC_SDTR1_TRC_Pos (12U)
9051#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos)
9052#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk
9053#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos)
9054#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos)
9055#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos)
9056#define FMC_SDTR1_TWR_Pos (16U)
9057#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos)
9058#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk
9059#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos)
9060#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos)
9061#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos)
9062#define FMC_SDTR1_TRP_Pos (20U)
9063#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos)
9064#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk
9065#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos)
9066#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos)
9067#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos)
9068#define FMC_SDTR1_TRCD_Pos (24U)
9069#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos)
9070#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk
9071#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos)
9072#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos)
9073#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos)
9075/****************** Bit definition for FMC_SDTR2 register ******************/
9076#define FMC_SDTR2_TMRD_Pos (0U)
9077#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos)
9078#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk
9079#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos)
9080#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos)
9081#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos)
9082#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos)
9083#define FMC_SDTR2_TXSR_Pos (4U)
9084#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos)
9085#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk
9086#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos)
9087#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos)
9088#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos)
9089#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos)
9090#define FMC_SDTR2_TRAS_Pos (8U)
9091#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos)
9092#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk
9093#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos)
9094#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos)
9095#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos)
9096#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos)
9097#define FMC_SDTR2_TRC_Pos (12U)
9098#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos)
9099#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk
9100#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos)
9101#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos)
9102#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos)
9103#define FMC_SDTR2_TWR_Pos (16U)
9104#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos)
9105#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk
9106#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos)
9107#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos)
9108#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos)
9109#define FMC_SDTR2_TRP_Pos (20U)
9110#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos)
9111#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk
9112#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos)
9113#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos)
9114#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos)
9115#define FMC_SDTR2_TRCD_Pos (24U)
9116#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos)
9117#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk
9118#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos)
9119#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos)
9120#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos)
9122/****************** Bit definition for FMC_SDCMR register ******************/
9123#define FMC_SDCMR_MODE_Pos (0U)
9124#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
9125#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
9126#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
9127#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
9128#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos)
9129#define FMC_SDCMR_CTB2_Pos (3U)
9130#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
9131#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
9132#define FMC_SDCMR_CTB1_Pos (4U)
9133#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
9134#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
9135#define FMC_SDCMR_NRFS_Pos (5U)
9136#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
9137#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
9138#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
9139#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
9140#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
9141#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
9142#define FMC_SDCMR_MRD_Pos (9U)
9143#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
9144#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
9146/****************** Bit definition for FMC_SDRTR register ******************/
9147#define FMC_SDRTR_CRE_Pos (0U)
9148#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
9149#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
9150#define FMC_SDRTR_COUNT_Pos (1U)
9151#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
9152#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
9153#define FMC_SDRTR_REIE_Pos (14U)
9154#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
9155#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
9157/****************** Bit definition for FMC_SDSR register ******************/
9158#define FMC_SDSR_RE_Pos (0U)
9159#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
9160#define FMC_SDSR_RE FMC_SDSR_RE_Msk
9161#define FMC_SDSR_MODES1_Pos (1U)
9162#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
9163#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
9164#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
9165#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
9166#define FMC_SDSR_MODES2_Pos (3U)
9167#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
9168#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
9169#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
9170#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
9171#define FMC_SDSR_BUSY_Pos (5U)
9172#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos)
9173#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk
9175/******************************************************************************/
9176/* */
9177/* General Purpose I/O */
9178/* */
9179/******************************************************************************/
9180/****************** Bits definition for GPIO_MODER register *****************/
9181#define GPIO_MODER_MODER0_Pos (0U)
9182#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
9183#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
9184#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
9185#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
9186#define GPIO_MODER_MODER1_Pos (2U)
9187#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
9188#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
9189#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
9190#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
9191#define GPIO_MODER_MODER2_Pos (4U)
9192#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
9193#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
9194#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
9195#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
9196#define GPIO_MODER_MODER3_Pos (6U)
9197#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
9198#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
9199#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
9200#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
9201#define GPIO_MODER_MODER4_Pos (8U)
9202#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
9203#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
9204#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
9205#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
9206#define GPIO_MODER_MODER5_Pos (10U)
9207#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
9208#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
9209#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
9210#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
9211#define GPIO_MODER_MODER6_Pos (12U)
9212#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
9213#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
9214#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
9215#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
9216#define GPIO_MODER_MODER7_Pos (14U)
9217#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
9218#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
9219#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
9220#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
9221#define GPIO_MODER_MODER8_Pos (16U)
9222#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
9223#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
9224#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
9225#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
9226#define GPIO_MODER_MODER9_Pos (18U)
9227#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
9228#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
9229#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
9230#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
9231#define GPIO_MODER_MODER10_Pos (20U)
9232#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
9233#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
9234#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
9235#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
9236#define GPIO_MODER_MODER11_Pos (22U)
9237#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
9238#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
9239#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
9240#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
9241#define GPIO_MODER_MODER12_Pos (24U)
9242#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
9243#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
9244#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
9245#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
9246#define GPIO_MODER_MODER13_Pos (26U)
9247#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
9248#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
9249#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
9250#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
9251#define GPIO_MODER_MODER14_Pos (28U)
9252#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
9253#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
9254#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
9255#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
9256#define GPIO_MODER_MODER15_Pos (30U)
9257#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
9258#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
9259#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
9260#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
9262/****************** Bits definition for GPIO_OTYPER register ****************/
9263#define GPIO_OTYPER_OT0_Pos (0U)
9264#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
9265#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
9266#define GPIO_OTYPER_OT1_Pos (1U)
9267#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
9268#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
9269#define GPIO_OTYPER_OT2_Pos (2U)
9270#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
9271#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
9272#define GPIO_OTYPER_OT3_Pos (3U)
9273#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
9274#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
9275#define GPIO_OTYPER_OT4_Pos (4U)
9276#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
9277#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
9278#define GPIO_OTYPER_OT5_Pos (5U)
9279#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
9280#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
9281#define GPIO_OTYPER_OT6_Pos (6U)
9282#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
9283#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
9284#define GPIO_OTYPER_OT7_Pos (7U)
9285#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
9286#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
9287#define GPIO_OTYPER_OT8_Pos (8U)
9288#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
9289#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
9290#define GPIO_OTYPER_OT9_Pos (9U)
9291#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
9292#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
9293#define GPIO_OTYPER_OT10_Pos (10U)
9294#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
9295#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
9296#define GPIO_OTYPER_OT11_Pos (11U)
9297#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
9298#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
9299#define GPIO_OTYPER_OT12_Pos (12U)
9300#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
9301#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
9302#define GPIO_OTYPER_OT13_Pos (13U)
9303#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
9304#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
9305#define GPIO_OTYPER_OT14_Pos (14U)
9306#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
9307#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
9308#define GPIO_OTYPER_OT15_Pos (15U)
9309#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
9310#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
9311
9312/* Legacy defines */
9313#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
9314#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
9315#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
9316#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
9317#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
9318#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
9319#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
9320#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
9321#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
9322#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
9323#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
9324#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
9325#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
9326#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
9327#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
9328#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
9329
9330/****************** Bits definition for GPIO_OSPEEDR register ***************/
9331#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
9332#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
9333#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
9334#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
9335#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
9336#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
9337#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
9338#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
9339#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
9340#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
9341#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
9342#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
9343#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
9344#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
9345#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
9346#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
9347#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
9348#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
9349#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
9350#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
9351#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
9352#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
9353#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
9354#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
9355#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
9356#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
9357#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
9358#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
9359#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
9360#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
9361#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
9362#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
9363#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
9364#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
9365#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
9366#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
9367#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
9368#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
9369#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
9370#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
9371#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
9372#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
9373#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
9374#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
9375#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
9376#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
9377#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
9378#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
9379#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
9380#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
9381#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
9382#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
9383#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
9384#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
9385#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
9386#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
9387#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
9388#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
9389#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
9390#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
9391#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
9392#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
9393#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
9394#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
9395#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
9396#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
9397#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
9398#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
9399#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
9400#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
9401#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
9402#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
9403#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
9404#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
9405#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
9406#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
9407#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
9408#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
9409#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
9410#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
9412/* legacy defines */
9413#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
9414#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
9415#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
9416#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
9417#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
9418#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
9419#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
9420#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
9421#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
9422#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
9423#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
9424#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
9425#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
9426#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
9427#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
9428#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
9429#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
9430#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
9431#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
9432#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
9433#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
9434#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
9435#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
9436#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
9437#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
9438#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
9439#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
9440#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
9441#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
9442#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
9443#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
9444#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
9445#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
9446#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
9447#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
9448#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
9449#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
9450#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
9451#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
9452#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
9453#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
9454#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
9455#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
9456#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
9457#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
9458#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
9459#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
9460#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
9461#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
9462#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
9463#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
9464#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
9465#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
9466#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
9467#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
9468#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
9469#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
9470#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
9471#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
9472#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
9473#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
9474#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
9475#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
9476#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
9477#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
9478#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
9479#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
9480#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
9481#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
9482#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
9483#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
9484#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
9485#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
9486#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
9487#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
9488#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
9489#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
9490#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
9491#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
9492#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
9493
9494/****************** Bits definition for GPIO_PUPDR register *****************/
9495#define GPIO_PUPDR_PUPDR0_Pos (0U)
9496#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos)
9497#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
9498#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos)
9499#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos)
9500#define GPIO_PUPDR_PUPDR1_Pos (2U)
9501#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos)
9502#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
9503#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos)
9504#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos)
9505#define GPIO_PUPDR_PUPDR2_Pos (4U)
9506#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos)
9507#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
9508#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos)
9509#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos)
9510#define GPIO_PUPDR_PUPDR3_Pos (6U)
9511#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos)
9512#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
9513#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos)
9514#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos)
9515#define GPIO_PUPDR_PUPDR4_Pos (8U)
9516#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos)
9517#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
9518#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos)
9519#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos)
9520#define GPIO_PUPDR_PUPDR5_Pos (10U)
9521#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos)
9522#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
9523#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos)
9524#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos)
9525#define GPIO_PUPDR_PUPDR6_Pos (12U)
9526#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos)
9527#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
9528#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos)
9529#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos)
9530#define GPIO_PUPDR_PUPDR7_Pos (14U)
9531#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos)
9532#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
9533#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos)
9534#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos)
9535#define GPIO_PUPDR_PUPDR8_Pos (16U)
9536#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos)
9537#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
9538#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos)
9539#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos)
9540#define GPIO_PUPDR_PUPDR9_Pos (18U)
9541#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos)
9542#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
9543#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos)
9544#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos)
9545#define GPIO_PUPDR_PUPDR10_Pos (20U)
9546#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos)
9547#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
9548#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)
9549#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)
9550#define GPIO_PUPDR_PUPDR11_Pos (22U)
9551#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos)
9552#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
9553#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)
9554#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)
9555#define GPIO_PUPDR_PUPDR12_Pos (24U)
9556#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos)
9557#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
9558#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)
9559#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)
9560#define GPIO_PUPDR_PUPDR13_Pos (26U)
9561#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos)
9562#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
9563#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)
9564#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)
9565#define GPIO_PUPDR_PUPDR14_Pos (28U)
9566#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos)
9567#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
9568#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)
9569#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)
9570#define GPIO_PUPDR_PUPDR15_Pos (30U)
9571#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos)
9572#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
9573#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)
9574#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)
9576/****************** Bits definition for GPIO_IDR register *******************/
9577#define GPIO_IDR_ID0_Pos (0U)
9578#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
9579#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
9580#define GPIO_IDR_ID1_Pos (1U)
9581#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
9582#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
9583#define GPIO_IDR_ID2_Pos (2U)
9584#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
9585#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
9586#define GPIO_IDR_ID3_Pos (3U)
9587#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
9588#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
9589#define GPIO_IDR_ID4_Pos (4U)
9590#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
9591#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
9592#define GPIO_IDR_ID5_Pos (5U)
9593#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
9594#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
9595#define GPIO_IDR_ID6_Pos (6U)
9596#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
9597#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
9598#define GPIO_IDR_ID7_Pos (7U)
9599#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
9600#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
9601#define GPIO_IDR_ID8_Pos (8U)
9602#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
9603#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
9604#define GPIO_IDR_ID9_Pos (9U)
9605#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
9606#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
9607#define GPIO_IDR_ID10_Pos (10U)
9608#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
9609#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
9610#define GPIO_IDR_ID11_Pos (11U)
9611#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
9612#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
9613#define GPIO_IDR_ID12_Pos (12U)
9614#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
9615#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
9616#define GPIO_IDR_ID13_Pos (13U)
9617#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
9618#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
9619#define GPIO_IDR_ID14_Pos (14U)
9620#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
9621#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
9622#define GPIO_IDR_ID15_Pos (15U)
9623#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
9624#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
9625
9626/* Legacy defines */
9627#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
9628#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
9629#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
9630#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
9631#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
9632#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
9633#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
9634#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
9635#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
9636#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
9637#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
9638#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
9639#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
9640#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
9641#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
9642#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
9643
9644/****************** Bits definition for GPIO_ODR register *******************/
9645#define GPIO_ODR_OD0_Pos (0U)
9646#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
9647#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
9648#define GPIO_ODR_OD1_Pos (1U)
9649#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
9650#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
9651#define GPIO_ODR_OD2_Pos (2U)
9652#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
9653#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
9654#define GPIO_ODR_OD3_Pos (3U)
9655#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
9656#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
9657#define GPIO_ODR_OD4_Pos (4U)
9658#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
9659#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
9660#define GPIO_ODR_OD5_Pos (5U)
9661#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
9662#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
9663#define GPIO_ODR_OD6_Pos (6U)
9664#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
9665#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
9666#define GPIO_ODR_OD7_Pos (7U)
9667#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
9668#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
9669#define GPIO_ODR_OD8_Pos (8U)
9670#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
9671#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
9672#define GPIO_ODR_OD9_Pos (9U)
9673#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
9674#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
9675#define GPIO_ODR_OD10_Pos (10U)
9676#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
9677#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
9678#define GPIO_ODR_OD11_Pos (11U)
9679#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
9680#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
9681#define GPIO_ODR_OD12_Pos (12U)
9682#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
9683#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
9684#define GPIO_ODR_OD13_Pos (13U)
9685#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
9686#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
9687#define GPIO_ODR_OD14_Pos (14U)
9688#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
9689#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
9690#define GPIO_ODR_OD15_Pos (15U)
9691#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
9692#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
9693
9694/* Legacy defines */
9695#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
9696#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
9697#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
9698#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
9699#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
9700#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
9701#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
9702#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
9703#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
9704#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
9705#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
9706#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
9707#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
9708#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
9709#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
9710#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
9711
9712/****************** Bits definition for GPIO_BSRR register ******************/
9713#define GPIO_BSRR_BS0_Pos (0U)
9714#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
9715#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
9716#define GPIO_BSRR_BS1_Pos (1U)
9717#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
9718#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
9719#define GPIO_BSRR_BS2_Pos (2U)
9720#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
9721#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
9722#define GPIO_BSRR_BS3_Pos (3U)
9723#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
9724#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
9725#define GPIO_BSRR_BS4_Pos (4U)
9726#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
9727#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
9728#define GPIO_BSRR_BS5_Pos (5U)
9729#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
9730#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
9731#define GPIO_BSRR_BS6_Pos (6U)
9732#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
9733#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
9734#define GPIO_BSRR_BS7_Pos (7U)
9735#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
9736#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
9737#define GPIO_BSRR_BS8_Pos (8U)
9738#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
9739#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
9740#define GPIO_BSRR_BS9_Pos (9U)
9741#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
9742#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
9743#define GPIO_BSRR_BS10_Pos (10U)
9744#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
9745#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
9746#define GPIO_BSRR_BS11_Pos (11U)
9747#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
9748#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
9749#define GPIO_BSRR_BS12_Pos (12U)
9750#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
9751#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
9752#define GPIO_BSRR_BS13_Pos (13U)
9753#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
9754#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
9755#define GPIO_BSRR_BS14_Pos (14U)
9756#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
9757#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
9758#define GPIO_BSRR_BS15_Pos (15U)
9759#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
9760#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
9761#define GPIO_BSRR_BR0_Pos (16U)
9762#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
9763#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
9764#define GPIO_BSRR_BR1_Pos (17U)
9765#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
9766#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
9767#define GPIO_BSRR_BR2_Pos (18U)
9768#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
9769#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
9770#define GPIO_BSRR_BR3_Pos (19U)
9771#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
9772#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
9773#define GPIO_BSRR_BR4_Pos (20U)
9774#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
9775#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
9776#define GPIO_BSRR_BR5_Pos (21U)
9777#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
9778#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
9779#define GPIO_BSRR_BR6_Pos (22U)
9780#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
9781#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
9782#define GPIO_BSRR_BR7_Pos (23U)
9783#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
9784#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
9785#define GPIO_BSRR_BR8_Pos (24U)
9786#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
9787#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
9788#define GPIO_BSRR_BR9_Pos (25U)
9789#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
9790#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
9791#define GPIO_BSRR_BR10_Pos (26U)
9792#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
9793#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
9794#define GPIO_BSRR_BR11_Pos (27U)
9795#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
9796#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
9797#define GPIO_BSRR_BR12_Pos (28U)
9798#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
9799#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
9800#define GPIO_BSRR_BR13_Pos (29U)
9801#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
9802#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
9803#define GPIO_BSRR_BR14_Pos (30U)
9804#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
9805#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
9806#define GPIO_BSRR_BR15_Pos (31U)
9807#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
9808#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
9809
9810/* Legacy defines */
9811#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
9812#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
9813#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
9814#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
9815#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
9816#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
9817#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
9818#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
9819#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
9820#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
9821#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
9822#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
9823#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
9824#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
9825#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
9826#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
9827#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
9828#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
9829#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
9830#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
9831#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
9832#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
9833#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
9834#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
9835#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
9836#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
9837#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
9838#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
9839#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
9840#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
9841#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
9842#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
9843
9844/****************** Bit definition for GPIO_LCKR register *********************/
9845#define GPIO_LCKR_LCK0_Pos (0U)
9846#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
9847#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
9848#define GPIO_LCKR_LCK1_Pos (1U)
9849#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
9850#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
9851#define GPIO_LCKR_LCK2_Pos (2U)
9852#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
9853#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
9854#define GPIO_LCKR_LCK3_Pos (3U)
9855#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
9856#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
9857#define GPIO_LCKR_LCK4_Pos (4U)
9858#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
9859#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
9860#define GPIO_LCKR_LCK5_Pos (5U)
9861#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
9862#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
9863#define GPIO_LCKR_LCK6_Pos (6U)
9864#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
9865#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
9866#define GPIO_LCKR_LCK7_Pos (7U)
9867#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
9868#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
9869#define GPIO_LCKR_LCK8_Pos (8U)
9870#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
9871#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
9872#define GPIO_LCKR_LCK9_Pos (9U)
9873#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
9874#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
9875#define GPIO_LCKR_LCK10_Pos (10U)
9876#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
9877#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
9878#define GPIO_LCKR_LCK11_Pos (11U)
9879#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
9880#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
9881#define GPIO_LCKR_LCK12_Pos (12U)
9882#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
9883#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
9884#define GPIO_LCKR_LCK13_Pos (13U)
9885#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
9886#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
9887#define GPIO_LCKR_LCK14_Pos (14U)
9888#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
9889#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
9890#define GPIO_LCKR_LCK15_Pos (15U)
9891#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
9892#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
9893#define GPIO_LCKR_LCKK_Pos (16U)
9894#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
9895#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
9896
9897/****************** Bit definition for GPIO_AFRL register *********************/
9898#define GPIO_AFRL_AFRL0_Pos (0U)
9899#define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos)
9900#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
9901#define GPIO_AFRL_AFRL0_0 (0x1UL << GPIO_AFRL_AFRL0_Pos)
9902#define GPIO_AFRL_AFRL0_1 (0x2UL << GPIO_AFRL_AFRL0_Pos)
9903#define GPIO_AFRL_AFRL0_2 (0x4UL << GPIO_AFRL_AFRL0_Pos)
9904#define GPIO_AFRL_AFRL0_3 (0x8UL << GPIO_AFRL_AFRL0_Pos)
9905#define GPIO_AFRL_AFRL1_Pos (4U)
9906#define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos)
9907#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
9908#define GPIO_AFRL_AFRL1_0 (0x1UL << GPIO_AFRL_AFRL1_Pos)
9909#define GPIO_AFRL_AFRL1_1 (0x2UL << GPIO_AFRL_AFRL1_Pos)
9910#define GPIO_AFRL_AFRL1_2 (0x4UL << GPIO_AFRL_AFRL1_Pos)
9911#define GPIO_AFRL_AFRL1_3 (0x8UL << GPIO_AFRL_AFRL1_Pos)
9912#define GPIO_AFRL_AFRL2_Pos (8U)
9913#define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos)
9914#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
9915#define GPIO_AFRL_AFRL2_0 (0x1UL << GPIO_AFRL_AFRL2_Pos)
9916#define GPIO_AFRL_AFRL2_1 (0x2UL << GPIO_AFRL_AFRL2_Pos)
9917#define GPIO_AFRL_AFRL2_2 (0x4UL << GPIO_AFRL_AFRL2_Pos)
9918#define GPIO_AFRL_AFRL2_3 (0x8UL << GPIO_AFRL_AFRL2_Pos)
9919#define GPIO_AFRL_AFRL3_Pos (12U)
9920#define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos)
9921#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
9922#define GPIO_AFRL_AFRL3_0 (0x1UL << GPIO_AFRL_AFRL3_Pos)
9923#define GPIO_AFRL_AFRL3_1 (0x2UL << GPIO_AFRL_AFRL3_Pos)
9924#define GPIO_AFRL_AFRL3_2 (0x4UL << GPIO_AFRL_AFRL3_Pos)
9925#define GPIO_AFRL_AFRL3_3 (0x8UL << GPIO_AFRL_AFRL3_Pos)
9926#define GPIO_AFRL_AFRL4_Pos (16U)
9927#define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos)
9928#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
9929#define GPIO_AFRL_AFRL4_0 (0x1UL << GPIO_AFRL_AFRL4_Pos)
9930#define GPIO_AFRL_AFRL4_1 (0x2UL << GPIO_AFRL_AFRL4_Pos)
9931#define GPIO_AFRL_AFRL4_2 (0x4UL << GPIO_AFRL_AFRL4_Pos)
9932#define GPIO_AFRL_AFRL4_3 (0x8UL << GPIO_AFRL_AFRL4_Pos)
9933#define GPIO_AFRL_AFRL5_Pos (20U)
9934#define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos)
9935#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
9936#define GPIO_AFRL_AFRL5_0 (0x1UL << GPIO_AFRL_AFRL5_Pos)
9937#define GPIO_AFRL_AFRL5_1 (0x2UL << GPIO_AFRL_AFRL5_Pos)
9938#define GPIO_AFRL_AFRL5_2 (0x4UL << GPIO_AFRL_AFRL5_Pos)
9939#define GPIO_AFRL_AFRL5_3 (0x8UL << GPIO_AFRL_AFRL5_Pos)
9940#define GPIO_AFRL_AFRL6_Pos (24U)
9941#define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos)
9942#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
9943#define GPIO_AFRL_AFRL6_0 (0x1UL << GPIO_AFRL_AFRL6_Pos)
9944#define GPIO_AFRL_AFRL6_1 (0x2UL << GPIO_AFRL_AFRL6_Pos)
9945#define GPIO_AFRL_AFRL6_2 (0x4UL << GPIO_AFRL_AFRL6_Pos)
9946#define GPIO_AFRL_AFRL6_3 (0x8UL << GPIO_AFRL_AFRL6_Pos)
9947#define GPIO_AFRL_AFRL7_Pos (28U)
9948#define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos)
9949#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
9950#define GPIO_AFRL_AFRL7_0 (0x1UL << GPIO_AFRL_AFRL7_Pos)
9951#define GPIO_AFRL_AFRL7_1 (0x2UL << GPIO_AFRL_AFRL7_Pos)
9952#define GPIO_AFRL_AFRL7_2 (0x4UL << GPIO_AFRL_AFRL7_Pos)
9953#define GPIO_AFRL_AFRL7_3 (0x8UL << GPIO_AFRL_AFRL7_Pos)
9955/****************** Bit definition for GPIO_AFRH register *********************/
9956#define GPIO_AFRH_AFRH0_Pos (0U)
9957#define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos)
9958#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
9959#define GPIO_AFRH_AFRH0_0 (0x1UL << GPIO_AFRH_AFRH0_Pos)
9960#define GPIO_AFRH_AFRH0_1 (0x2UL << GPIO_AFRH_AFRH0_Pos)
9961#define GPIO_AFRH_AFRH0_2 (0x4UL << GPIO_AFRH_AFRH0_Pos)
9962#define GPIO_AFRH_AFRH0_3 (0x8UL << GPIO_AFRH_AFRH0_Pos)
9963#define GPIO_AFRH_AFRH1_Pos (4U)
9964#define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos)
9965#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
9966#define GPIO_AFRH_AFRH1_0 (0x1UL << GPIO_AFRH_AFRH1_Pos)
9967#define GPIO_AFRH_AFRH1_1 (0x2UL << GPIO_AFRH_AFRH1_Pos)
9968#define GPIO_AFRH_AFRH1_2 (0x4UL << GPIO_AFRH_AFRH1_Pos)
9969#define GPIO_AFRH_AFRH1_3 (0x8UL << GPIO_AFRH_AFRH1_Pos)
9970#define GPIO_AFRH_AFRH2_Pos (8U)
9971#define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos)
9972#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
9973#define GPIO_AFRH_AFRH2_0 (0x1UL << GPIO_AFRH_AFRH2_Pos)
9974#define GPIO_AFRH_AFRH2_1 (0x2UL << GPIO_AFRH_AFRH2_Pos)
9975#define GPIO_AFRH_AFRH2_2 (0x4UL << GPIO_AFRH_AFRH2_Pos)
9976#define GPIO_AFRH_AFRH2_3 (0x8UL << GPIO_AFRH_AFRH2_Pos)
9977#define GPIO_AFRH_AFRH3_Pos (12U)
9978#define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos)
9979#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
9980#define GPIO_AFRH_AFRH3_0 (0x1UL << GPIO_AFRH_AFRH3_Pos)
9981#define GPIO_AFRH_AFRH3_1 (0x2UL << GPIO_AFRH_AFRH3_Pos)
9982#define GPIO_AFRH_AFRH3_2 (0x4UL << GPIO_AFRH_AFRH3_Pos)
9983#define GPIO_AFRH_AFRH3_3 (0x8UL << GPIO_AFRH_AFRH3_Pos)
9984#define GPIO_AFRH_AFRH4_Pos (16U)
9985#define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos)
9986#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
9987#define GPIO_AFRH_AFRH4_0 (0x1UL << GPIO_AFRH_AFRH4_Pos)
9988#define GPIO_AFRH_AFRH4_1 (0x2UL << GPIO_AFRH_AFRH4_Pos)
9989#define GPIO_AFRH_AFRH4_2 (0x4UL << GPIO_AFRH_AFRH4_Pos)
9990#define GPIO_AFRH_AFRH4_3 (0x8UL << GPIO_AFRH_AFRH4_Pos)
9991#define GPIO_AFRH_AFRH5_Pos (20U)
9992#define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos)
9993#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
9994#define GPIO_AFRH_AFRH5_0 (0x1UL << GPIO_AFRH_AFRH5_Pos)
9995#define GPIO_AFRH_AFRH5_1 (0x2UL << GPIO_AFRH_AFRH5_Pos)
9996#define GPIO_AFRH_AFRH5_2 (0x4UL << GPIO_AFRH_AFRH5_Pos)
9997#define GPIO_AFRH_AFRH5_3 (0x8UL << GPIO_AFRH_AFRH5_Pos)
9998#define GPIO_AFRH_AFRH6_Pos (24U)
9999#define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos)
10000#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
10001#define GPIO_AFRH_AFRH6_0 (0x1UL << GPIO_AFRH_AFRH6_Pos)
10002#define GPIO_AFRH_AFRH6_1 (0x2UL << GPIO_AFRH_AFRH6_Pos)
10003#define GPIO_AFRH_AFRH6_2 (0x4UL << GPIO_AFRH_AFRH6_Pos)
10004#define GPIO_AFRH_AFRH6_3 (0x8UL << GPIO_AFRH_AFRH6_Pos)
10005#define GPIO_AFRH_AFRH7_Pos (28U)
10006#define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos)
10007#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
10008#define GPIO_AFRH_AFRH7_0 (0x1UL << GPIO_AFRH_AFRH7_Pos)
10009#define GPIO_AFRH_AFRH7_1 (0x2UL << GPIO_AFRH_AFRH7_Pos)
10010#define GPIO_AFRH_AFRH7_2 (0x4UL << GPIO_AFRH_AFRH7_Pos)
10011#define GPIO_AFRH_AFRH7_3 (0x8UL << GPIO_AFRH_AFRH7_Pos)
10013/******************************************************************************/
10014/* */
10015/* HASH */
10016/* */
10017/******************************************************************************/
10018/****************** Bits definition for HASH_CR register ********************/
10019#define HASH_CR_INIT_Pos (2U)
10020#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos)
10021#define HASH_CR_INIT HASH_CR_INIT_Msk
10022#define HASH_CR_DMAE_Pos (3U)
10023#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos)
10024#define HASH_CR_DMAE HASH_CR_DMAE_Msk
10025#define HASH_CR_DATATYPE_Pos (4U)
10026#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos)
10027#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
10028#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos)
10029#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos)
10030#define HASH_CR_MODE_Pos (6U)
10031#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos)
10032#define HASH_CR_MODE HASH_CR_MODE_Msk
10033#define HASH_CR_ALGO_Pos (7U)
10034#define HASH_CR_ALGO_Msk (0x801UL << HASH_CR_ALGO_Pos)
10035#define HASH_CR_ALGO HASH_CR_ALGO_Msk
10036#define HASH_CR_ALGO_0 (0x001UL << HASH_CR_ALGO_Pos)
10037#define HASH_CR_ALGO_1 (0x800UL << HASH_CR_ALGO_Pos)
10038#define HASH_CR_NBW_Pos (8U)
10039#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos)
10040#define HASH_CR_NBW HASH_CR_NBW_Msk
10041#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos)
10042#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos)
10043#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos)
10044#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos)
10045#define HASH_CR_DINNE_Pos (12U)
10046#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos)
10047#define HASH_CR_DINNE HASH_CR_DINNE_Msk
10048#define HASH_CR_MDMAT_Pos (13U)
10049#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos)
10050#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
10051#define HASH_CR_LKEY_Pos (16U)
10052#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos)
10053#define HASH_CR_LKEY HASH_CR_LKEY_Msk
10054
10055/****************** Bits definition for HASH_STR register *******************/
10056#define HASH_STR_NBLW_Pos (0U)
10057#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos)
10058#define HASH_STR_NBLW HASH_STR_NBLW_Msk
10059#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos)
10060#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos)
10061#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos)
10062#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos)
10063#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos)
10064#define HASH_STR_DCAL_Pos (8U)
10065#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos)
10066#define HASH_STR_DCAL HASH_STR_DCAL_Msk
10067
10068/* legacy defines */
10069#define HASH_STR_NBW HASH_STR_NBLW
10070#define HASH_STR_NBW_0 HASH_STR_NBLW_0
10071#define HASH_STR_NBW_1 HASH_STR_NBLW_1
10072#define HASH_STR_NBW_2 HASH_STR_NBLW_2
10073#define HASH_STR_NBW_3 HASH_STR_NBLW_3
10074#define HASH_STR_NBW_4 HASH_STR_NBLW_4
10075
10076/****************** Bits definition for HASH_IMR register *******************/
10077#define HASH_IMR_DINIE_Pos (0U)
10078#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos)
10079#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
10080#define HASH_IMR_DCIE_Pos (1U)
10081#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos)
10082#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
10083
10084/* legacy defines */
10085#define HASH_IMR_DINIM HASH_IMR_DINIE
10086#define HASH_IMR_DCIM HASH_IMR_DCIE
10087/****************** Bits definition for HASH_SR register ********************/
10088#define HASH_SR_DINIS_Pos (0U)
10089#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos)
10090#define HASH_SR_DINIS HASH_SR_DINIS_Msk
10091#define HASH_SR_DCIS_Pos (1U)
10092#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos)
10093#define HASH_SR_DCIS HASH_SR_DCIS_Msk
10094#define HASH_SR_DMAS_Pos (2U)
10095#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos)
10096#define HASH_SR_DMAS HASH_SR_DMAS_Msk
10097#define HASH_SR_BUSY_Pos (3U)
10098#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos)
10099#define HASH_SR_BUSY HASH_SR_BUSY_Msk
10100
10101/******************************************************************************/
10102/* */
10103/* Inter-integrated Circuit Interface (I2C) */
10104/* */
10105/******************************************************************************/
10106/******************* Bit definition for I2C_CR1 register *******************/
10107#define I2C_CR1_PE_Pos (0U)
10108#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
10109#define I2C_CR1_PE I2C_CR1_PE_Msk
10110#define I2C_CR1_TXIE_Pos (1U)
10111#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
10112#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
10113#define I2C_CR1_RXIE_Pos (2U)
10114#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
10115#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
10116#define I2C_CR1_ADDRIE_Pos (3U)
10117#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
10118#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
10119#define I2C_CR1_NACKIE_Pos (4U)
10120#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
10121#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
10122#define I2C_CR1_STOPIE_Pos (5U)
10123#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
10124#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
10125#define I2C_CR1_TCIE_Pos (6U)
10126#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
10127#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
10128#define I2C_CR1_ERRIE_Pos (7U)
10129#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
10130#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
10131#define I2C_CR1_DNF_Pos (8U)
10132#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
10133#define I2C_CR1_DNF I2C_CR1_DNF_Msk
10134#define I2C_CR1_ANFOFF_Pos (12U)
10135#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
10136#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
10137#define I2C_CR1_TXDMAEN_Pos (14U)
10138#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
10139#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
10140#define I2C_CR1_RXDMAEN_Pos (15U)
10141#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
10142#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
10143#define I2C_CR1_SBC_Pos (16U)
10144#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
10145#define I2C_CR1_SBC I2C_CR1_SBC_Msk
10146#define I2C_CR1_NOSTRETCH_Pos (17U)
10147#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
10148#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
10149#define I2C_CR1_GCEN_Pos (19U)
10150#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
10151#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
10152#define I2C_CR1_SMBHEN_Pos (20U)
10153#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
10154#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
10155#define I2C_CR1_SMBDEN_Pos (21U)
10156#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
10157#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
10158#define I2C_CR1_ALERTEN_Pos (22U)
10159#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
10160#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
10161#define I2C_CR1_PECEN_Pos (23U)
10162#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
10163#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
10166/****************** Bit definition for I2C_CR2 register ********************/
10167#define I2C_CR2_SADD_Pos (0U)
10168#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
10169#define I2C_CR2_SADD I2C_CR2_SADD_Msk
10170#define I2C_CR2_RD_WRN_Pos (10U)
10171#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
10172#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
10173#define I2C_CR2_ADD10_Pos (11U)
10174#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
10175#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
10176#define I2C_CR2_HEAD10R_Pos (12U)
10177#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
10178#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
10179#define I2C_CR2_START_Pos (13U)
10180#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
10181#define I2C_CR2_START I2C_CR2_START_Msk
10182#define I2C_CR2_STOP_Pos (14U)
10183#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
10184#define I2C_CR2_STOP I2C_CR2_STOP_Msk
10185#define I2C_CR2_NACK_Pos (15U)
10186#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
10187#define I2C_CR2_NACK I2C_CR2_NACK_Msk
10188#define I2C_CR2_NBYTES_Pos (16U)
10189#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
10190#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
10191#define I2C_CR2_RELOAD_Pos (24U)
10192#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
10193#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
10194#define I2C_CR2_AUTOEND_Pos (25U)
10195#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
10196#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
10197#define I2C_CR2_PECBYTE_Pos (26U)
10198#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
10199#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
10201/******************* Bit definition for I2C_OAR1 register ******************/
10202#define I2C_OAR1_OA1_Pos (0U)
10203#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
10204#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
10205#define I2C_OAR1_OA1MODE_Pos (10U)
10206#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
10207#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
10208#define I2C_OAR1_OA1EN_Pos (15U)
10209#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
10210#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
10212/******************* Bit definition for I2C_OAR2 register ******************/
10213#define I2C_OAR2_OA2_Pos (1U)
10214#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
10215#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
10216#define I2C_OAR2_OA2MSK_Pos (8U)
10217#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
10218#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
10219#define I2C_OAR2_OA2NOMASK 0x00000000U
10220#define I2C_OAR2_OA2MASK01_Pos (8U)
10221#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
10222#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
10223#define I2C_OAR2_OA2MASK02_Pos (9U)
10224#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
10225#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
10226#define I2C_OAR2_OA2MASK03_Pos (8U)
10227#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
10228#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
10229#define I2C_OAR2_OA2MASK04_Pos (10U)
10230#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
10231#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
10232#define I2C_OAR2_OA2MASK05_Pos (8U)
10233#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
10234#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
10235#define I2C_OAR2_OA2MASK06_Pos (9U)
10236#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
10237#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
10238#define I2C_OAR2_OA2MASK07_Pos (8U)
10239#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
10240#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
10241#define I2C_OAR2_OA2EN_Pos (15U)
10242#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
10243#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
10245/******************* Bit definition for I2C_TIMINGR register *******************/
10246#define I2C_TIMINGR_SCLL_Pos (0U)
10247#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
10248#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
10249#define I2C_TIMINGR_SCLH_Pos (8U)
10250#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
10251#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
10252#define I2C_TIMINGR_SDADEL_Pos (16U)
10253#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
10254#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
10255#define I2C_TIMINGR_SCLDEL_Pos (20U)
10256#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
10257#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
10258#define I2C_TIMINGR_PRESC_Pos (28U)
10259#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
10260#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
10262/******************* Bit definition for I2C_TIMEOUTR register *******************/
10263#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
10264#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
10265#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
10266#define I2C_TIMEOUTR_TIDLE_Pos (12U)
10267#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
10268#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
10269#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
10270#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
10271#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
10272#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
10273#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
10274#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
10275#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
10276#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
10277#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
10279/****************** Bit definition for I2C_ISR register *********************/
10280#define I2C_ISR_TXE_Pos (0U)
10281#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
10282#define I2C_ISR_TXE I2C_ISR_TXE_Msk
10283#define I2C_ISR_TXIS_Pos (1U)
10284#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
10285#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
10286#define I2C_ISR_RXNE_Pos (2U)
10287#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
10288#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
10289#define I2C_ISR_ADDR_Pos (3U)
10290#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
10291#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
10292#define I2C_ISR_NACKF_Pos (4U)
10293#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
10294#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
10295#define I2C_ISR_STOPF_Pos (5U)
10296#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
10297#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
10298#define I2C_ISR_TC_Pos (6U)
10299#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
10300#define I2C_ISR_TC I2C_ISR_TC_Msk
10301#define I2C_ISR_TCR_Pos (7U)
10302#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
10303#define I2C_ISR_TCR I2C_ISR_TCR_Msk
10304#define I2C_ISR_BERR_Pos (8U)
10305#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
10306#define I2C_ISR_BERR I2C_ISR_BERR_Msk
10307#define I2C_ISR_ARLO_Pos (9U)
10308#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
10309#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
10310#define I2C_ISR_OVR_Pos (10U)
10311#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
10312#define I2C_ISR_OVR I2C_ISR_OVR_Msk
10313#define I2C_ISR_PECERR_Pos (11U)
10314#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
10315#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
10316#define I2C_ISR_TIMEOUT_Pos (12U)
10317#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
10318#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
10319#define I2C_ISR_ALERT_Pos (13U)
10320#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
10321#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
10322#define I2C_ISR_BUSY_Pos (15U)
10323#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
10324#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
10325#define I2C_ISR_DIR_Pos (16U)
10326#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
10327#define I2C_ISR_DIR I2C_ISR_DIR_Msk
10328#define I2C_ISR_ADDCODE_Pos (17U)
10329#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
10330#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
10332/****************** Bit definition for I2C_ICR register *********************/
10333#define I2C_ICR_ADDRCF_Pos (3U)
10334#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
10335#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
10336#define I2C_ICR_NACKCF_Pos (4U)
10337#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
10338#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
10339#define I2C_ICR_STOPCF_Pos (5U)
10340#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
10341#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
10342#define I2C_ICR_BERRCF_Pos (8U)
10343#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
10344#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
10345#define I2C_ICR_ARLOCF_Pos (9U)
10346#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
10347#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
10348#define I2C_ICR_OVRCF_Pos (10U)
10349#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
10350#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
10351#define I2C_ICR_PECCF_Pos (11U)
10352#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
10353#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
10354#define I2C_ICR_TIMOUTCF_Pos (12U)
10355#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
10356#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
10357#define I2C_ICR_ALERTCF_Pos (13U)
10358#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
10359#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
10361/****************** Bit definition for I2C_PECR register *********************/
10362#define I2C_PECR_PEC_Pos (0U)
10363#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
10364#define I2C_PECR_PEC I2C_PECR_PEC_Msk
10366/****************** Bit definition for I2C_RXDR register *********************/
10367#define I2C_RXDR_RXDATA_Pos (0U)
10368#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
10369#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
10371/****************** Bit definition for I2C_TXDR register *********************/
10372#define I2C_TXDR_TXDATA_Pos (0U)
10373#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
10374#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
10377/******************************************************************************/
10378/* */
10379/* Independent WATCHDOG */
10380/* */
10381/******************************************************************************/
10382/******************* Bit definition for IWDG_KR register ********************/
10383#define IWDG_KR_KEY_Pos (0U)
10384#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
10385#define IWDG_KR_KEY IWDG_KR_KEY_Msk
10387/******************* Bit definition for IWDG_PR register ********************/
10388#define IWDG_PR_PR_Pos (0U)
10389#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
10390#define IWDG_PR_PR IWDG_PR_PR_Msk
10391#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
10392#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
10393#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
10395/******************* Bit definition for IWDG_RLR register *******************/
10396#define IWDG_RLR_RL_Pos (0U)
10397#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
10398#define IWDG_RLR_RL IWDG_RLR_RL_Msk
10400/******************* Bit definition for IWDG_SR register ********************/
10401#define IWDG_SR_PVU_Pos (0U)
10402#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
10403#define IWDG_SR_PVU IWDG_SR_PVU_Msk
10404#define IWDG_SR_RVU_Pos (1U)
10405#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
10406#define IWDG_SR_RVU IWDG_SR_RVU_Msk
10407#define IWDG_SR_WVU_Pos (2U)
10408#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
10409#define IWDG_SR_WVU IWDG_SR_WVU_Msk
10411/******************* Bit definition for IWDG_KR register ********************/
10412#define IWDG_WINR_WIN_Pos (0U)
10413#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
10414#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
10416/******************************************************************************/
10417/* */
10418/* LCD-TFT Display Controller (LTDC) */
10419/* */
10420/******************************************************************************/
10421
10422/******************** Bit definition for LTDC_SSCR register *****************/
10423
10424#define LTDC_SSCR_VSH_Pos (0U)
10425#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
10426#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
10427#define LTDC_SSCR_HSW_Pos (16U)
10428#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
10429#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
10431/******************** Bit definition for LTDC_BPCR register *****************/
10432
10433#define LTDC_BPCR_AVBP_Pos (0U)
10434#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
10435#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
10436#define LTDC_BPCR_AHBP_Pos (16U)
10437#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
10438#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
10440/******************** Bit definition for LTDC_AWCR register *****************/
10441
10442#define LTDC_AWCR_AAH_Pos (0U)
10443#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
10444#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
10445#define LTDC_AWCR_AAW_Pos (16U)
10446#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
10447#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
10449/******************** Bit definition for LTDC_TWCR register *****************/
10450
10451#define LTDC_TWCR_TOTALH_Pos (0U)
10452#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
10453#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
10454#define LTDC_TWCR_TOTALW_Pos (16U)
10455#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
10456#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
10458/******************** Bit definition for LTDC_GCR register ******************/
10459
10460#define LTDC_GCR_LTDCEN_Pos (0U)
10461#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
10462#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
10463#define LTDC_GCR_DBW_Pos (4U)
10464#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
10465#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
10466#define LTDC_GCR_DGW_Pos (8U)
10467#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
10468#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
10469#define LTDC_GCR_DRW_Pos (12U)
10470#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
10471#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
10472#define LTDC_GCR_DEN_Pos (16U)
10473#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
10474#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
10475#define LTDC_GCR_PCPOL_Pos (28U)
10476#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
10477#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
10478#define LTDC_GCR_DEPOL_Pos (29U)
10479#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
10480#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
10481#define LTDC_GCR_VSPOL_Pos (30U)
10482#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
10483#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
10484#define LTDC_GCR_HSPOL_Pos (31U)
10485#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
10486#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
10489/******************** Bit definition for LTDC_SRCR register *****************/
10490
10491#define LTDC_SRCR_IMR_Pos (0U)
10492#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
10493#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
10494#define LTDC_SRCR_VBR_Pos (1U)
10495#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
10496#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
10498/******************** Bit definition for LTDC_BCCR register *****************/
10499
10500#define LTDC_BCCR_BCBLUE_Pos (0U)
10501#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
10502#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
10503#define LTDC_BCCR_BCGREEN_Pos (8U)
10504#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
10505#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
10506#define LTDC_BCCR_BCRED_Pos (16U)
10507#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
10508#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
10510/******************** Bit definition for LTDC_IER register ******************/
10511
10512#define LTDC_IER_LIE_Pos (0U)
10513#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
10514#define LTDC_IER_LIE LTDC_IER_LIE_Msk
10515#define LTDC_IER_FUIE_Pos (1U)
10516#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
10517#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
10518#define LTDC_IER_TERRIE_Pos (2U)
10519#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
10520#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
10521#define LTDC_IER_RRIE_Pos (3U)
10522#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
10523#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
10525/******************** Bit definition for LTDC_ISR register ******************/
10526
10527#define LTDC_ISR_LIF_Pos (0U)
10528#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
10529#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
10530#define LTDC_ISR_FUIF_Pos (1U)
10531#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
10532#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
10533#define LTDC_ISR_TERRIF_Pos (2U)
10534#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
10535#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
10536#define LTDC_ISR_RRIF_Pos (3U)
10537#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
10538#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
10540/******************** Bit definition for LTDC_ICR register ******************/
10541
10542#define LTDC_ICR_CLIF_Pos (0U)
10543#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
10544#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
10545#define LTDC_ICR_CFUIF_Pos (1U)
10546#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
10547#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
10548#define LTDC_ICR_CTERRIF_Pos (2U)
10549#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
10550#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
10551#define LTDC_ICR_CRRIF_Pos (3U)
10552#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
10553#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
10555/******************** Bit definition for LTDC_LIPCR register ****************/
10556
10557#define LTDC_LIPCR_LIPOS_Pos (0U)
10558#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
10559#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
10561/******************** Bit definition for LTDC_CPSR register *****************/
10562
10563#define LTDC_CPSR_CYPOS_Pos (0U)
10564#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
10565#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
10566#define LTDC_CPSR_CXPOS_Pos (16U)
10567#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
10568#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
10570/******************** Bit definition for LTDC_CDSR register *****************/
10571
10572#define LTDC_CDSR_VDES_Pos (0U)
10573#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
10574#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
10575#define LTDC_CDSR_HDES_Pos (1U)
10576#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
10577#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
10578#define LTDC_CDSR_VSYNCS_Pos (2U)
10579#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
10580#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
10581#define LTDC_CDSR_HSYNCS_Pos (3U)
10582#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
10583#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
10585/******************** Bit definition for LTDC_LxCR register *****************/
10586
10587#define LTDC_LxCR_LEN_Pos (0U)
10588#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
10589#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
10590#define LTDC_LxCR_COLKEN_Pos (1U)
10591#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
10592#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
10593#define LTDC_LxCR_CLUTEN_Pos (4U)
10594#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
10595#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
10597/******************** Bit definition for LTDC_LxWHPCR register **************/
10598
10599#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
10600#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
10601#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
10602#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
10603#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
10604#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
10606/******************** Bit definition for LTDC_LxWVPCR register **************/
10607
10608#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
10609#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
10610#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
10611#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
10612#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
10613#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
10615/******************** Bit definition for LTDC_LxCKCR register ***************/
10616
10617#define LTDC_LxCKCR_CKBLUE_Pos (0U)
10618#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
10619#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
10620#define LTDC_LxCKCR_CKGREEN_Pos (8U)
10621#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
10622#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
10623#define LTDC_LxCKCR_CKRED_Pos (16U)
10624#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
10625#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
10627/******************** Bit definition for LTDC_LxPFCR register ***************/
10628
10629#define LTDC_LxPFCR_PF_Pos (0U)
10630#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
10631#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
10633/******************** Bit definition for LTDC_LxCACR register ***************/
10634
10635#define LTDC_LxCACR_CONSTA_Pos (0U)
10636#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
10637#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
10639/******************** Bit definition for LTDC_LxDCCR register ***************/
10640
10641#define LTDC_LxDCCR_DCBLUE_Pos (0U)
10642#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
10643#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
10644#define LTDC_LxDCCR_DCGREEN_Pos (8U)
10645#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
10646#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
10647#define LTDC_LxDCCR_DCRED_Pos (16U)
10648#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
10649#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
10650#define LTDC_LxDCCR_DCALPHA_Pos (24U)
10651#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
10652#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
10654/******************** Bit definition for LTDC_LxBFCR register ***************/
10655
10656#define LTDC_LxBFCR_BF2_Pos (0U)
10657#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
10658#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
10659#define LTDC_LxBFCR_BF1_Pos (8U)
10660#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
10661#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
10663/******************** Bit definition for LTDC_LxCFBAR register **************/
10664
10665#define LTDC_LxCFBAR_CFBADD_Pos (0U)
10666#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
10667#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
10669/******************** Bit definition for LTDC_LxCFBLR register **************/
10670
10671#define LTDC_LxCFBLR_CFBLL_Pos (0U)
10672#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
10673#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
10674#define LTDC_LxCFBLR_CFBP_Pos (16U)
10675#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
10676#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
10678/******************** Bit definition for LTDC_LxCFBLNR register *************/
10679
10680#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
10681#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
10682#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
10684/******************** Bit definition for LTDC_LxCLUTWR register *************/
10685
10686#define LTDC_LxCLUTWR_BLUE_Pos (0U)
10687#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
10688#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
10689#define LTDC_LxCLUTWR_GREEN_Pos (8U)
10690#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
10691#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
10692#define LTDC_LxCLUTWR_RED_Pos (16U)
10693#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
10694#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
10695#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
10696#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
10697#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
10699/******************************************************************************/
10700/* */
10701/* Power Control */
10702/* */
10703/******************************************************************************/
10704/******************** Bit definition for PWR_CR1 register ********************/
10705#define PWR_CR1_LPDS_Pos (0U)
10706#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos)
10707#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk
10708#define PWR_CR1_PDDS_Pos (1U)
10709#define PWR_CR1_PDDS_Msk (0x1UL << PWR_CR1_PDDS_Pos)
10710#define PWR_CR1_PDDS PWR_CR1_PDDS_Msk
10711#define PWR_CR1_CSBF_Pos (3U)
10712#define PWR_CR1_CSBF_Msk (0x1UL << PWR_CR1_CSBF_Pos)
10713#define PWR_CR1_CSBF PWR_CR1_CSBF_Msk
10714#define PWR_CR1_PVDE_Pos (4U)
10715#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos)
10716#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk
10717#define PWR_CR1_PLS_Pos (5U)
10718#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos)
10719#define PWR_CR1_PLS PWR_CR1_PLS_Msk
10720#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos)
10721#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos)
10722#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos)
10725#define PWR_CR1_PLS_LEV0 0x00000000U
10726#define PWR_CR1_PLS_LEV1_Pos (5U)
10727#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos)
10728#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk
10729#define PWR_CR1_PLS_LEV2_Pos (6U)
10730#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos)
10731#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk
10732#define PWR_CR1_PLS_LEV3_Pos (5U)
10733#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos)
10734#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk
10735#define PWR_CR1_PLS_LEV4_Pos (7U)
10736#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos)
10737#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk
10738#define PWR_CR1_PLS_LEV5_Pos (5U)
10739#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos)
10740#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk
10741#define PWR_CR1_PLS_LEV6_Pos (6U)
10742#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos)
10743#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk
10744#define PWR_CR1_PLS_LEV7_Pos (5U)
10745#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos)
10746#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk
10747#define PWR_CR1_DBP_Pos (8U)
10748#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
10749#define PWR_CR1_DBP PWR_CR1_DBP_Msk
10750#define PWR_CR1_FPDS_Pos (9U)
10751#define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos)
10752#define PWR_CR1_FPDS PWR_CR1_FPDS_Msk
10753#define PWR_CR1_LPUDS_Pos (10U)
10754#define PWR_CR1_LPUDS_Msk (0x1UL << PWR_CR1_LPUDS_Pos)
10755#define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk
10756#define PWR_CR1_MRUDS_Pos (11U)
10757#define PWR_CR1_MRUDS_Msk (0x1UL << PWR_CR1_MRUDS_Pos)
10758#define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk
10759#define PWR_CR1_ADCDC1_Pos (13U)
10760#define PWR_CR1_ADCDC1_Msk (0x1UL << PWR_CR1_ADCDC1_Pos)
10761#define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk
10762#define PWR_CR1_VOS_Pos (14U)
10763#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)
10764#define PWR_CR1_VOS PWR_CR1_VOS_Msk
10765#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)
10766#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)
10767#define PWR_CR1_ODEN_Pos (16U)
10768#define PWR_CR1_ODEN_Msk (0x1UL << PWR_CR1_ODEN_Pos)
10769#define PWR_CR1_ODEN PWR_CR1_ODEN_Msk
10770#define PWR_CR1_ODSWEN_Pos (17U)
10771#define PWR_CR1_ODSWEN_Msk (0x1UL << PWR_CR1_ODSWEN_Pos)
10772#define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk
10773#define PWR_CR1_UDEN_Pos (18U)
10774#define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos)
10775#define PWR_CR1_UDEN PWR_CR1_UDEN_Msk
10776#define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos)
10777#define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos)
10779/******************* Bit definition for PWR_CSR1 register ********************/
10780#define PWR_CSR1_WUIF_Pos (0U)
10781#define PWR_CSR1_WUIF_Msk (0x1UL << PWR_CSR1_WUIF_Pos)
10782#define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk
10783#define PWR_CSR1_SBF_Pos (1U)
10784#define PWR_CSR1_SBF_Msk (0x1UL << PWR_CSR1_SBF_Pos)
10785#define PWR_CSR1_SBF PWR_CSR1_SBF_Msk
10786#define PWR_CSR1_PVDO_Pos (2U)
10787#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos)
10788#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk
10789#define PWR_CSR1_BRR_Pos (3U)
10790#define PWR_CSR1_BRR_Msk (0x1UL << PWR_CSR1_BRR_Pos)
10791#define PWR_CSR1_BRR PWR_CSR1_BRR_Msk
10792#define PWR_CSR1_EIWUP_Pos (8U)
10793#define PWR_CSR1_EIWUP_Msk (0x1UL << PWR_CSR1_EIWUP_Pos)
10794#define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk
10795#define PWR_CSR1_BRE_Pos (9U)
10796#define PWR_CSR1_BRE_Msk (0x1UL << PWR_CSR1_BRE_Pos)
10797#define PWR_CSR1_BRE PWR_CSR1_BRE_Msk
10798#define PWR_CSR1_VOSRDY_Pos (14U)
10799#define PWR_CSR1_VOSRDY_Msk (0x1UL << PWR_CSR1_VOSRDY_Pos)
10800#define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk
10801#define PWR_CSR1_ODRDY_Pos (16U)
10802#define PWR_CSR1_ODRDY_Msk (0x1UL << PWR_CSR1_ODRDY_Pos)
10803#define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk
10804#define PWR_CSR1_ODSWRDY_Pos (17U)
10805#define PWR_CSR1_ODSWRDY_Msk (0x1UL << PWR_CSR1_ODSWRDY_Pos)
10806#define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk
10807#define PWR_CSR1_UDRDY_Pos (18U)
10808#define PWR_CSR1_UDRDY_Msk (0x3UL << PWR_CSR1_UDRDY_Pos)
10809#define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk
10812/******************** Bit definition for PWR_CR2 register ********************/
10813#define PWR_CR2_CWUPF1_Pos (0U)
10814#define PWR_CR2_CWUPF1_Msk (0x1UL << PWR_CR2_CWUPF1_Pos)
10815#define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk
10816#define PWR_CR2_CWUPF2_Pos (1U)
10817#define PWR_CR2_CWUPF2_Msk (0x1UL << PWR_CR2_CWUPF2_Pos)
10818#define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk
10819#define PWR_CR2_CWUPF3_Pos (2U)
10820#define PWR_CR2_CWUPF3_Msk (0x1UL << PWR_CR2_CWUPF3_Pos)
10821#define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk
10822#define PWR_CR2_CWUPF4_Pos (3U)
10823#define PWR_CR2_CWUPF4_Msk (0x1UL << PWR_CR2_CWUPF4_Pos)
10824#define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk
10825#define PWR_CR2_CWUPF5_Pos (4U)
10826#define PWR_CR2_CWUPF5_Msk (0x1UL << PWR_CR2_CWUPF5_Pos)
10827#define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk
10828#define PWR_CR2_CWUPF6_Pos (5U)
10829#define PWR_CR2_CWUPF6_Msk (0x1UL << PWR_CR2_CWUPF6_Pos)
10830#define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk
10831#define PWR_CR2_WUPP1_Pos (8U)
10832#define PWR_CR2_WUPP1_Msk (0x1UL << PWR_CR2_WUPP1_Pos)
10833#define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk
10834#define PWR_CR2_WUPP2_Pos (9U)
10835#define PWR_CR2_WUPP2_Msk (0x1UL << PWR_CR2_WUPP2_Pos)
10836#define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk
10837#define PWR_CR2_WUPP3_Pos (10U)
10838#define PWR_CR2_WUPP3_Msk (0x1UL << PWR_CR2_WUPP3_Pos)
10839#define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk
10840#define PWR_CR2_WUPP4_Pos (11U)
10841#define PWR_CR2_WUPP4_Msk (0x1UL << PWR_CR2_WUPP4_Pos)
10842#define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk
10843#define PWR_CR2_WUPP5_Pos (12U)
10844#define PWR_CR2_WUPP5_Msk (0x1UL << PWR_CR2_WUPP5_Pos)
10845#define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk
10846#define PWR_CR2_WUPP6_Pos (13U)
10847#define PWR_CR2_WUPP6_Msk (0x1UL << PWR_CR2_WUPP6_Pos)
10848#define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk
10850/******************* Bit definition for PWR_CSR2 register ********************/
10851#define PWR_CSR2_WUPF1_Pos (0U)
10852#define PWR_CSR2_WUPF1_Msk (0x1UL << PWR_CSR2_WUPF1_Pos)
10853#define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk
10854#define PWR_CSR2_WUPF2_Pos (1U)
10855#define PWR_CSR2_WUPF2_Msk (0x1UL << PWR_CSR2_WUPF2_Pos)
10856#define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk
10857#define PWR_CSR2_WUPF3_Pos (2U)
10858#define PWR_CSR2_WUPF3_Msk (0x1UL << PWR_CSR2_WUPF3_Pos)
10859#define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk
10860#define PWR_CSR2_WUPF4_Pos (3U)
10861#define PWR_CSR2_WUPF4_Msk (0x1UL << PWR_CSR2_WUPF4_Pos)
10862#define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk
10863#define PWR_CSR2_WUPF5_Pos (4U)
10864#define PWR_CSR2_WUPF5_Msk (0x1UL << PWR_CSR2_WUPF5_Pos)
10865#define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk
10866#define PWR_CSR2_WUPF6_Pos (5U)
10867#define PWR_CSR2_WUPF6_Msk (0x1UL << PWR_CSR2_WUPF6_Pos)
10868#define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk
10869#define PWR_CSR2_EWUP1_Pos (8U)
10870#define PWR_CSR2_EWUP1_Msk (0x1UL << PWR_CSR2_EWUP1_Pos)
10871#define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk
10872#define PWR_CSR2_EWUP2_Pos (9U)
10873#define PWR_CSR2_EWUP2_Msk (0x1UL << PWR_CSR2_EWUP2_Pos)
10874#define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk
10875#define PWR_CSR2_EWUP3_Pos (10U)
10876#define PWR_CSR2_EWUP3_Msk (0x1UL << PWR_CSR2_EWUP3_Pos)
10877#define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk
10878#define PWR_CSR2_EWUP4_Pos (11U)
10879#define PWR_CSR2_EWUP4_Msk (0x1UL << PWR_CSR2_EWUP4_Pos)
10880#define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk
10881#define PWR_CSR2_EWUP5_Pos (12U)
10882#define PWR_CSR2_EWUP5_Msk (0x1UL << PWR_CSR2_EWUP5_Pos)
10883#define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk
10884#define PWR_CSR2_EWUP6_Pos (13U)
10885#define PWR_CSR2_EWUP6_Msk (0x1UL << PWR_CSR2_EWUP6_Pos)
10886#define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk
10888/******************************************************************************/
10889/* */
10890/* QUADSPI */
10891/* */
10892/******************************************************************************/
10893/***************** Bit definition for QUADSPI_CR register *******************/
10894#define QUADSPI_CR_EN_Pos (0U)
10895#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
10896#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
10897#define QUADSPI_CR_ABORT_Pos (1U)
10898#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
10899#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
10900#define QUADSPI_CR_DMAEN_Pos (2U)
10901#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
10902#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
10903#define QUADSPI_CR_TCEN_Pos (3U)
10904#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
10905#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
10906#define QUADSPI_CR_SSHIFT_Pos (4U)
10907#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
10908#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
10909#define QUADSPI_CR_DFM_Pos (6U)
10910#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
10911#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
10912#define QUADSPI_CR_FSEL_Pos (7U)
10913#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
10914#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
10915#define QUADSPI_CR_FTHRES_Pos (8U)
10916#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
10917#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
10918#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos)
10919#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos)
10920#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos)
10921#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos)
10922#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
10923#define QUADSPI_CR_TEIE_Pos (16U)
10924#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
10925#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
10926#define QUADSPI_CR_TCIE_Pos (17U)
10927#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
10928#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
10929#define QUADSPI_CR_FTIE_Pos (18U)
10930#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
10931#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
10932#define QUADSPI_CR_SMIE_Pos (19U)
10933#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
10934#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
10935#define QUADSPI_CR_TOIE_Pos (20U)
10936#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
10937#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
10938#define QUADSPI_CR_APMS_Pos (22U)
10939#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
10940#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
10941#define QUADSPI_CR_PMM_Pos (23U)
10942#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
10943#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
10944#define QUADSPI_CR_PRESCALER_Pos (24U)
10945#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
10946#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
10947#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
10948#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
10949#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
10950#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
10951#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
10952#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
10953#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
10954#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
10956/***************** Bit definition for QUADSPI_DCR register ******************/
10957#define QUADSPI_DCR_CKMODE_Pos (0U)
10958#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
10959#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
10960#define QUADSPI_DCR_CSHT_Pos (8U)
10961#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
10962#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
10963#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
10964#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
10965#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
10966#define QUADSPI_DCR_FSIZE_Pos (16U)
10967#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
10968#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
10969#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
10970#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
10971#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
10972#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
10973#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
10975/****************** Bit definition for QUADSPI_SR register *******************/
10976#define QUADSPI_SR_TEF_Pos (0U)
10977#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
10978#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
10979#define QUADSPI_SR_TCF_Pos (1U)
10980#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
10981#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
10982#define QUADSPI_SR_FTF_Pos (2U)
10983#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
10984#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
10985#define QUADSPI_SR_SMF_Pos (3U)
10986#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
10987#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
10988#define QUADSPI_SR_TOF_Pos (4U)
10989#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
10990#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
10991#define QUADSPI_SR_BUSY_Pos (5U)
10992#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
10993#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
10994#define QUADSPI_SR_FLEVEL_Pos (8U)
10995#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
10996#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
10997#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
10998#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
10999#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
11000#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
11001#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
11002#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
11004/****************** Bit definition for QUADSPI_FCR register ******************/
11005#define QUADSPI_FCR_CTEF_Pos (0U)
11006#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
11007#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
11008#define QUADSPI_FCR_CTCF_Pos (1U)
11009#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
11010#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
11011#define QUADSPI_FCR_CSMF_Pos (3U)
11012#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
11013#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
11014#define QUADSPI_FCR_CTOF_Pos (4U)
11015#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
11016#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
11018/****************** Bit definition for QUADSPI_DLR register ******************/
11019#define QUADSPI_DLR_DL_Pos (0U)
11020#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
11021#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
11023/****************** Bit definition for QUADSPI_CCR register ******************/
11024#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
11025#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
11026#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
11027#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
11028#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
11029#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
11030#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
11031#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
11032#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
11033#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
11034#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
11035#define QUADSPI_CCR_IMODE_Pos (8U)
11036#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
11037#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
11038#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
11039#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
11040#define QUADSPI_CCR_ADMODE_Pos (10U)
11041#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
11042#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
11043#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
11044#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
11045#define QUADSPI_CCR_ADSIZE_Pos (12U)
11046#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
11047#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
11048#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
11049#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
11050#define QUADSPI_CCR_ABMODE_Pos (14U)
11051#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
11052#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
11053#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
11054#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
11055#define QUADSPI_CCR_ABSIZE_Pos (16U)
11056#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
11057#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
11058#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
11059#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
11060#define QUADSPI_CCR_DCYC_Pos (18U)
11061#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
11062#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
11063#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
11064#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
11065#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
11066#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
11067#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
11068#define QUADSPI_CCR_DMODE_Pos (24U)
11069#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
11070#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
11071#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
11072#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
11073#define QUADSPI_CCR_FMODE_Pos (26U)
11074#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
11075#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
11076#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
11077#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
11078#define QUADSPI_CCR_SIOO_Pos (28U)
11079#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
11080#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
11081#define QUADSPI_CCR_DHHC_Pos (30U)
11082#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
11083#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
11084#define QUADSPI_CCR_DDRM_Pos (31U)
11085#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
11086#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
11087/****************** Bit definition for QUADSPI_AR register *******************/
11088#define QUADSPI_AR_ADDRESS_Pos (0U)
11089#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
11090#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
11092/****************** Bit definition for QUADSPI_ABR register ******************/
11093#define QUADSPI_ABR_ALTERNATE_Pos (0U)
11094#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
11095#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
11097/****************** Bit definition for QUADSPI_DR register *******************/
11098#define QUADSPI_DR_DATA_Pos (0U)
11099#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
11100#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
11102/****************** Bit definition for QUADSPI_PSMKR register ****************/
11103#define QUADSPI_PSMKR_MASK_Pos (0U)
11104#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
11105#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
11107/****************** Bit definition for QUADSPI_PSMAR register ****************/
11108#define QUADSPI_PSMAR_MATCH_Pos (0U)
11109#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
11110#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
11112/****************** Bit definition for QUADSPI_PIR register *****************/
11113#define QUADSPI_PIR_INTERVAL_Pos (0U)
11114#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
11115#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
11117/****************** Bit definition for QUADSPI_LPTR register *****************/
11118#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
11119#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
11120#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
11122/******************************************************************************/
11123/* */
11124/* Reset and Clock Control */
11125/* */
11126/******************************************************************************/
11127/******************** Bit definition for RCC_CR register ********************/
11128#define RCC_CR_HSION_Pos (0U)
11129#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
11130#define RCC_CR_HSION RCC_CR_HSION_Msk
11131#define RCC_CR_HSIRDY_Pos (1U)
11132#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
11133#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
11134#define RCC_CR_HSITRIM_Pos (3U)
11135#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
11136#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
11137#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
11138#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
11139#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
11140#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
11141#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
11142#define RCC_CR_HSICAL_Pos (8U)
11143#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
11144#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
11145#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
11146#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
11147#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
11148#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
11149#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
11150#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
11151#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
11152#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
11153#define RCC_CR_HSEON_Pos (16U)
11154#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
11155#define RCC_CR_HSEON RCC_CR_HSEON_Msk
11156#define RCC_CR_HSERDY_Pos (17U)
11157#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
11158#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
11159#define RCC_CR_HSEBYP_Pos (18U)
11160#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
11161#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
11162#define RCC_CR_CSSON_Pos (19U)
11163#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
11164#define RCC_CR_CSSON RCC_CR_CSSON_Msk
11165#define RCC_CR_PLLON_Pos (24U)
11166#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
11167#define RCC_CR_PLLON RCC_CR_PLLON_Msk
11168#define RCC_CR_PLLRDY_Pos (25U)
11169#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
11170#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
11171#define RCC_CR_PLLI2SON_Pos (26U)
11172#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
11173#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
11174#define RCC_CR_PLLI2SRDY_Pos (27U)
11175#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
11176#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
11177#define RCC_CR_PLLSAION_Pos (28U)
11178#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos)
11179#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
11180#define RCC_CR_PLLSAIRDY_Pos (29U)
11181#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos)
11182#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
11183
11184/******************** Bit definition for RCC_PLLCFGR register ***************/
11185#define RCC_PLLCFGR_PLLM_Pos (0U)
11186#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
11187#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
11188#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
11189#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
11190#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
11191#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
11192#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
11193#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
11194#define RCC_PLLCFGR_PLLN_Pos (6U)
11195#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
11196#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
11197#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
11198#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
11199#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
11200#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
11201#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
11202#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
11203#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
11204#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
11205#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
11206#define RCC_PLLCFGR_PLLP_Pos (16U)
11207#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
11208#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
11209#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
11210#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
11211#define RCC_PLLCFGR_PLLSRC_Pos (22U)
11212#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
11213#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
11214#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
11215#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
11216#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
11217#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
11218#define RCC_PLLCFGR_PLLQ_Pos (24U)
11219#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
11220#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
11221#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
11222#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
11223#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
11224#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
11226#define RCC_PLLCFGR_PLLR_Pos (28U)
11227#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)
11228#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
11229#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
11230#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
11231#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)
11233/******************** Bit definition for RCC_CFGR register ******************/
11235#define RCC_CFGR_SW_Pos (0U)
11236#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
11237#define RCC_CFGR_SW RCC_CFGR_SW_Msk
11238#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
11239#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
11240#define RCC_CFGR_SW_HSI 0x00000000U
11241#define RCC_CFGR_SW_HSE 0x00000001U
11242#define RCC_CFGR_SW_PLL 0x00000002U
11245#define RCC_CFGR_SWS_Pos (2U)
11246#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
11247#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
11248#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
11249#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
11250#define RCC_CFGR_SWS_HSI 0x00000000U
11251#define RCC_CFGR_SWS_HSE 0x00000004U
11252#define RCC_CFGR_SWS_PLL 0x00000008U
11255#define RCC_CFGR_HPRE_Pos (4U)
11256#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
11257#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
11258#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
11259#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
11260#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
11261#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
11263#define RCC_CFGR_HPRE_DIV1 0x00000000U
11264#define RCC_CFGR_HPRE_DIV2 0x00000080U
11265#define RCC_CFGR_HPRE_DIV4 0x00000090U
11266#define RCC_CFGR_HPRE_DIV8 0x000000A0U
11267#define RCC_CFGR_HPRE_DIV16 0x000000B0U
11268#define RCC_CFGR_HPRE_DIV64 0x000000C0U
11269#define RCC_CFGR_HPRE_DIV128 0x000000D0U
11270#define RCC_CFGR_HPRE_DIV256 0x000000E0U
11271#define RCC_CFGR_HPRE_DIV512 0x000000F0U
11274#define RCC_CFGR_PPRE1_Pos (10U)
11275#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
11276#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
11277#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
11278#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
11279#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
11281#define RCC_CFGR_PPRE1_DIV1 0x00000000U
11282#define RCC_CFGR_PPRE1_DIV2 0x00001000U
11283#define RCC_CFGR_PPRE1_DIV4 0x00001400U
11284#define RCC_CFGR_PPRE1_DIV8 0x00001800U
11285#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
11288#define RCC_CFGR_PPRE2_Pos (13U)
11289#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
11290#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
11291#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
11292#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
11293#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
11295#define RCC_CFGR_PPRE2_DIV1 0x00000000U
11296#define RCC_CFGR_PPRE2_DIV2 0x00008000U
11297#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
11298#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
11299#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
11302#define RCC_CFGR_RTCPRE_Pos (16U)
11303#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
11304#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
11305#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
11306#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
11307#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
11308#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
11309#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
11312#define RCC_CFGR_MCO1_Pos (21U)
11313#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
11314#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
11315#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
11316#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
11318#define RCC_CFGR_I2SSRC_Pos (23U)
11319#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
11320#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
11321
11322#define RCC_CFGR_MCO1PRE_Pos (24U)
11323#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
11324#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
11325#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
11326#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
11327#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
11329#define RCC_CFGR_MCO2PRE_Pos (27U)
11330#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
11331#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
11332#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
11333#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
11334#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
11336#define RCC_CFGR_MCO2_Pos (30U)
11337#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
11338#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
11339#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
11340#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
11342/******************** Bit definition for RCC_CIR register *******************/
11343#define RCC_CIR_LSIRDYF_Pos (0U)
11344#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
11345#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
11346#define RCC_CIR_LSERDYF_Pos (1U)
11347#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
11348#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
11349#define RCC_CIR_HSIRDYF_Pos (2U)
11350#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
11351#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
11352#define RCC_CIR_HSERDYF_Pos (3U)
11353#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
11354#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
11355#define RCC_CIR_PLLRDYF_Pos (4U)
11356#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
11357#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
11358#define RCC_CIR_PLLI2SRDYF_Pos (5U)
11359#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
11360#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
11361#define RCC_CIR_PLLSAIRDYF_Pos (6U)
11362#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)
11363#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
11364#define RCC_CIR_CSSF_Pos (7U)
11365#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
11366#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
11367#define RCC_CIR_LSIRDYIE_Pos (8U)
11368#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
11369#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
11370#define RCC_CIR_LSERDYIE_Pos (9U)
11371#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
11372#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
11373#define RCC_CIR_HSIRDYIE_Pos (10U)
11374#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
11375#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
11376#define RCC_CIR_HSERDYIE_Pos (11U)
11377#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
11378#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
11379#define RCC_CIR_PLLRDYIE_Pos (12U)
11380#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
11381#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
11382#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
11383#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
11384#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
11385#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
11386#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)
11387#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
11388#define RCC_CIR_LSIRDYC_Pos (16U)
11389#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
11390#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
11391#define RCC_CIR_LSERDYC_Pos (17U)
11392#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
11393#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
11394#define RCC_CIR_HSIRDYC_Pos (18U)
11395#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
11396#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
11397#define RCC_CIR_HSERDYC_Pos (19U)
11398#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
11399#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
11400#define RCC_CIR_PLLRDYC_Pos (20U)
11401#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
11402#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
11403#define RCC_CIR_PLLI2SRDYC_Pos (21U)
11404#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
11405#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
11406#define RCC_CIR_PLLSAIRDYC_Pos (22U)
11407#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)
11408#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
11409#define RCC_CIR_CSSC_Pos (23U)
11410#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
11411#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
11412
11413/******************** Bit definition for RCC_AHB1RSTR register **************/
11414#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
11415#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
11416#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
11417#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
11418#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
11419#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
11420#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
11421#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
11422#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
11423#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
11424#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
11425#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
11426#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
11427#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
11428#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
11429#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
11430#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
11431#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
11432#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
11433#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
11434#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
11435#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
11436#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
11437#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
11438#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
11439#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
11440#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
11441#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
11442#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos)
11443#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
11444#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
11445#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos)
11446#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
11447#define RCC_AHB1RSTR_CRCRST_Pos (12U)
11448#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
11449#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
11450#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
11451#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
11452#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
11453#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
11454#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
11455#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
11456#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
11457#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos)
11458#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
11459#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
11460#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
11461#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
11462#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
11463#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
11464#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
11465
11466/******************** Bit definition for RCC_AHB2RSTR register **************/
11467#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
11468#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
11469#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
11470#define RCC_AHB2RSTR_JPEGRST_Pos (1U)
11471#define RCC_AHB2RSTR_JPEGRST_Msk (0x1UL << RCC_AHB2RSTR_JPEGRST_Pos)
11472#define RCC_AHB2RSTR_JPEGRST RCC_AHB2RSTR_JPEGRST_Msk
11473#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
11474#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)
11475#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
11476#define RCC_AHB2RSTR_HASHRST_Pos (5U)
11477#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)
11478#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
11479#define RCC_AHB2RSTR_RNGRST_Pos (6U)
11480#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
11481#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
11482#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
11483#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
11484#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
11485
11486/******************** Bit definition for RCC_AHB3RSTR register **************/
11487
11488#define RCC_AHB3RSTR_FMCRST_Pos (0U)
11489#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
11490#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
11491#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
11492#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
11493#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
11494
11495/******************** Bit definition for RCC_APB1RSTR register **************/
11496#define RCC_APB1RSTR_TIM2RST_Pos (0U)
11497#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
11498#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
11499#define RCC_APB1RSTR_TIM3RST_Pos (1U)
11500#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
11501#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
11502#define RCC_APB1RSTR_TIM4RST_Pos (2U)
11503#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
11504#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
11505#define RCC_APB1RSTR_TIM5RST_Pos (3U)
11506#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
11507#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
11508#define RCC_APB1RSTR_TIM6RST_Pos (4U)
11509#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
11510#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
11511#define RCC_APB1RSTR_TIM7RST_Pos (5U)
11512#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
11513#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
11514#define RCC_APB1RSTR_TIM12RST_Pos (6U)
11515#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
11516#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
11517#define RCC_APB1RSTR_TIM13RST_Pos (7U)
11518#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
11519#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
11520#define RCC_APB1RSTR_TIM14RST_Pos (8U)
11521#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
11522#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
11523#define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
11524#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)
11525#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
11526#define RCC_APB1RSTR_WWDGRST_Pos (11U)
11527#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
11528#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
11529#define RCC_APB1RSTR_CAN3RST_Pos (13U)
11530#define RCC_APB1RSTR_CAN3RST_Msk (0x1UL << RCC_APB1RSTR_CAN3RST_Pos)
11531#define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
11532#define RCC_APB1RSTR_SPI2RST_Pos (14U)
11533#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
11534#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
11535#define RCC_APB1RSTR_SPI3RST_Pos (15U)
11536#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
11537#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
11538#define RCC_APB1RSTR_SPDIFRXRST_Pos (16U)
11539#define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR_SPDIFRXRST_Pos)
11540#define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk
11541#define RCC_APB1RSTR_USART2RST_Pos (17U)
11542#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
11543#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
11544#define RCC_APB1RSTR_USART3RST_Pos (18U)
11545#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
11546#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
11547#define RCC_APB1RSTR_UART4RST_Pos (19U)
11548#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
11549#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
11550#define RCC_APB1RSTR_UART5RST_Pos (20U)
11551#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
11552#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
11553#define RCC_APB1RSTR_I2C1RST_Pos (21U)
11554#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
11555#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
11556#define RCC_APB1RSTR_I2C2RST_Pos (22U)
11557#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
11558#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
11559#define RCC_APB1RSTR_I2C3RST_Pos (23U)
11560#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
11561#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
11562#define RCC_APB1RSTR_I2C4RST_Pos (24U)
11563#define RCC_APB1RSTR_I2C4RST_Msk (0x1UL << RCC_APB1RSTR_I2C4RST_Pos)
11564#define RCC_APB1RSTR_I2C4RST RCC_APB1RSTR_I2C4RST_Msk
11565#define RCC_APB1RSTR_CAN1RST_Pos (25U)
11566#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
11567#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
11568#define RCC_APB1RSTR_CAN2RST_Pos (26U)
11569#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
11570#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
11571#define RCC_APB1RSTR_CECRST_Pos (27U)
11572#define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos)
11573#define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk
11574#define RCC_APB1RSTR_PWRRST_Pos (28U)
11575#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
11576#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
11577#define RCC_APB1RSTR_DACRST_Pos (29U)
11578#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
11579#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
11580#define RCC_APB1RSTR_UART7RST_Pos (30U)
11581#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos)
11582#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
11583#define RCC_APB1RSTR_UART8RST_Pos (31U)
11584#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos)
11585#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
11586
11587/******************** Bit definition for RCC_APB2RSTR register **************/
11588#define RCC_APB2RSTR_TIM1RST_Pos (0U)
11589#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
11590#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
11591#define RCC_APB2RSTR_TIM8RST_Pos (1U)
11592#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
11593#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
11594#define RCC_APB2RSTR_USART1RST_Pos (4U)
11595#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
11596#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
11597#define RCC_APB2RSTR_USART6RST_Pos (5U)
11598#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
11599#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
11600#define RCC_APB2RSTR_SDMMC2RST_Pos (7U)
11601#define RCC_APB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC2RST_Pos)
11602#define RCC_APB2RSTR_SDMMC2RST RCC_APB2RSTR_SDMMC2RST_Msk
11603#define RCC_APB2RSTR_ADCRST_Pos (8U)
11604#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
11605#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
11606#define RCC_APB2RSTR_SDMMC1RST_Pos (11U)
11607#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos)
11608#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
11609#define RCC_APB2RSTR_SPI1RST_Pos (12U)
11610#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
11611#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
11612#define RCC_APB2RSTR_SPI4RST_Pos (13U)
11613#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
11614#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
11615#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
11616#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
11617#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
11618#define RCC_APB2RSTR_TIM9RST_Pos (16U)
11619#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
11620#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
11621#define RCC_APB2RSTR_TIM10RST_Pos (17U)
11622#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
11623#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
11624#define RCC_APB2RSTR_TIM11RST_Pos (18U)
11625#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
11626#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
11627#define RCC_APB2RSTR_SPI5RST_Pos (20U)
11628#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
11629#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
11630#define RCC_APB2RSTR_SPI6RST_Pos (21U)
11631#define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)
11632#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
11633#define RCC_APB2RSTR_SAI1RST_Pos (22U)
11634#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
11635#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
11636#define RCC_APB2RSTR_SAI2RST_Pos (23U)
11637#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
11638#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
11639#define RCC_APB2RSTR_LTDCRST_Pos (26U)
11640#define RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)
11641#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
11642#define RCC_APB2RSTR_DSIRST_Pos (27U)
11643#define RCC_APB2RSTR_DSIRST_Msk (0x1UL << RCC_APB2RSTR_DSIRST_Pos)
11644#define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk
11645#define RCC_APB2RSTR_DFSDM1RST_Pos (29U)
11646#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
11647#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
11648#define RCC_APB2RSTR_MDIORST_Pos (30U)
11649#define RCC_APB2RSTR_MDIORST_Msk (0x1UL << RCC_APB2RSTR_MDIORST_Pos)
11650#define RCC_APB2RSTR_MDIORST RCC_APB2RSTR_MDIORST_Msk
11651
11652/******************** Bit definition for RCC_AHB1ENR register ***************/
11653#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
11654#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
11655#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
11656#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
11657#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
11658#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
11659#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
11660#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
11661#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
11662#define RCC_AHB1ENR_GPIODEN_Pos (3U)
11663#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
11664#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
11665#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
11666#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
11667#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
11668#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
11669#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
11670#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
11671#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
11672#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
11673#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
11674#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
11675#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
11676#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
11677#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
11678#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
11679#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
11680#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
11681#define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)
11682#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
11683#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
11684#define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)
11685#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
11686#define RCC_AHB1ENR_CRCEN_Pos (12U)
11687#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
11688#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
11689#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
11690#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
11691#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
11692#define RCC_AHB1ENR_DTCMRAMEN_Pos (20U)
11693#define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1UL << RCC_AHB1ENR_DTCMRAMEN_Pos)
11694#define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk
11695#define RCC_AHB1ENR_DMA1EN_Pos (21U)
11696#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
11697#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
11698#define RCC_AHB1ENR_DMA2EN_Pos (22U)
11699#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
11700#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
11701#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
11702#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)
11703#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
11704#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
11705#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
11706#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
11707#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
11708#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
11709#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
11710#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
11711#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
11712#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
11713#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
11714#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
11715#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
11716#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
11717#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
11718#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
11719#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
11720#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
11721#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
11722
11723/******************** Bit definition for RCC_AHB2ENR register ***************/
11724#define RCC_AHB2ENR_DCMIEN_Pos (0U)
11725#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
11726#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
11727#define RCC_AHB2ENR_JPEGEN_Pos (1U)
11728#define RCC_AHB2ENR_JPEGEN_Msk (0x1UL << RCC_AHB2ENR_JPEGEN_Pos)
11729#define RCC_AHB2ENR_JPEGEN RCC_AHB2ENR_JPEGEN_Msk
11730#define RCC_AHB2ENR_CRYPEN_Pos (4U)
11731#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)
11732#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
11733#define RCC_AHB2ENR_HASHEN_Pos (5U)
11734#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos)
11735#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
11736#define RCC_AHB2ENR_RNGEN_Pos (6U)
11737#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
11738#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
11739#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
11740#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
11741#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
11742
11743/******************** Bit definition for RCC_AHB3ENR register ***************/
11744#define RCC_AHB3ENR_FMCEN_Pos (0U)
11745#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
11746#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11747#define RCC_AHB3ENR_QSPIEN_Pos (1U)
11748#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
11749#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
11750
11751/******************** Bit definition for RCC_APB1ENR register ***************/
11752#define RCC_APB1ENR_TIM2EN_Pos (0U)
11753#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
11754#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
11755#define RCC_APB1ENR_TIM3EN_Pos (1U)
11756#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
11757#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
11758#define RCC_APB1ENR_TIM4EN_Pos (2U)
11759#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
11760#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
11761#define RCC_APB1ENR_TIM5EN_Pos (3U)
11762#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
11763#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
11764#define RCC_APB1ENR_TIM6EN_Pos (4U)
11765#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
11766#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
11767#define RCC_APB1ENR_TIM7EN_Pos (5U)
11768#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
11769#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
11770#define RCC_APB1ENR_TIM12EN_Pos (6U)
11771#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
11772#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
11773#define RCC_APB1ENR_TIM13EN_Pos (7U)
11774#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
11775#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
11776#define RCC_APB1ENR_TIM14EN_Pos (8U)
11777#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
11778#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
11779#define RCC_APB1ENR_LPTIM1EN_Pos (9U)
11780#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)
11781#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
11782#define RCC_APB1ENR_RTCEN_Pos (10U)
11783#define RCC_APB1ENR_RTCEN_Msk (0x1UL << RCC_APB1ENR_RTCEN_Pos)
11784#define RCC_APB1ENR_RTCEN RCC_APB1ENR_RTCEN_Msk
11785#define RCC_APB1ENR_WWDGEN_Pos (11U)
11786#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
11787#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
11788#define RCC_APB1ENR_CAN3EN_Pos (13U)
11789#define RCC_APB1ENR_CAN3EN_Msk (0x1UL << RCC_APB1ENR_CAN3EN_Pos)
11790#define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
11791#define RCC_APB1ENR_SPI2EN_Pos (14U)
11792#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
11793#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
11794#define RCC_APB1ENR_SPI3EN_Pos (15U)
11795#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
11796#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
11797#define RCC_APB1ENR_SPDIFRXEN_Pos (16U)
11798#define RCC_APB1ENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR_SPDIFRXEN_Pos)
11799#define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk
11800#define RCC_APB1ENR_USART2EN_Pos (17U)
11801#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
11802#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
11803#define RCC_APB1ENR_USART3EN_Pos (18U)
11804#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
11805#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
11806#define RCC_APB1ENR_UART4EN_Pos (19U)
11807#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
11808#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
11809#define RCC_APB1ENR_UART5EN_Pos (20U)
11810#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
11811#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
11812#define RCC_APB1ENR_I2C1EN_Pos (21U)
11813#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
11814#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
11815#define RCC_APB1ENR_I2C2EN_Pos (22U)
11816#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
11817#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
11818#define RCC_APB1ENR_I2C3EN_Pos (23U)
11819#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
11820#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
11821#define RCC_APB1ENR_I2C4EN_Pos (24U)
11822#define RCC_APB1ENR_I2C4EN_Msk (0x1UL << RCC_APB1ENR_I2C4EN_Pos)
11823#define RCC_APB1ENR_I2C4EN RCC_APB1ENR_I2C4EN_Msk
11824#define RCC_APB1ENR_CAN1EN_Pos (25U)
11825#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
11826#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
11827#define RCC_APB1ENR_CAN2EN_Pos (26U)
11828#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
11829#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
11830#define RCC_APB1ENR_CECEN_Pos (27U)
11831#define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos)
11832#define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk
11833#define RCC_APB1ENR_PWREN_Pos (28U)
11834#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
11835#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
11836#define RCC_APB1ENR_DACEN_Pos (29U)
11837#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
11838#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
11839#define RCC_APB1ENR_UART7EN_Pos (30U)
11840#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos)
11841#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
11842#define RCC_APB1ENR_UART8EN_Pos (31U)
11843#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos)
11844#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
11845
11846/******************** Bit definition for RCC_APB2ENR register ***************/
11847#define RCC_APB2ENR_TIM1EN_Pos (0U)
11848#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
11849#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11850#define RCC_APB2ENR_TIM8EN_Pos (1U)
11851#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
11852#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11853#define RCC_APB2ENR_USART1EN_Pos (4U)
11854#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
11855#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11856#define RCC_APB2ENR_USART6EN_Pos (5U)
11857#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
11858#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
11859#define RCC_APB2ENR_SDMMC2EN_Pos (7U)
11860#define RCC_APB2ENR_SDMMC2EN_Msk (0x1UL << RCC_APB2ENR_SDMMC2EN_Pos)
11861#define RCC_APB2ENR_SDMMC2EN RCC_APB2ENR_SDMMC2EN_Msk
11862#define RCC_APB2ENR_ADC1EN_Pos (8U)
11863#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
11864#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
11865#define RCC_APB2ENR_ADC2EN_Pos (9U)
11866#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
11867#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
11868#define RCC_APB2ENR_ADC3EN_Pos (10U)
11869#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
11870#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
11871#define RCC_APB2ENR_SDMMC1EN_Pos (11U)
11872#define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos)
11873#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
11874#define RCC_APB2ENR_SPI1EN_Pos (12U)
11875#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
11876#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11877#define RCC_APB2ENR_SPI4EN_Pos (13U)
11878#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
11879#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
11880#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
11881#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
11882#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11883#define RCC_APB2ENR_TIM9EN_Pos (16U)
11884#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
11885#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
11886#define RCC_APB2ENR_TIM10EN_Pos (17U)
11887#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
11888#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
11889#define RCC_APB2ENR_TIM11EN_Pos (18U)
11890#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
11891#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
11892#define RCC_APB2ENR_SPI5EN_Pos (20U)
11893#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
11894#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
11895#define RCC_APB2ENR_SPI6EN_Pos (21U)
11896#define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos)
11897#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
11898#define RCC_APB2ENR_SAI1EN_Pos (22U)
11899#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
11900#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11901#define RCC_APB2ENR_SAI2EN_Pos (23U)
11902#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
11903#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
11904#define RCC_APB2ENR_LTDCEN_Pos (26U)
11905#define RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos)
11906#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
11907#define RCC_APB2ENR_DSIEN_Pos (27U)
11908#define RCC_APB2ENR_DSIEN_Msk (0x1UL << RCC_APB2ENR_DSIEN_Pos)
11909#define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk
11910#define RCC_APB2ENR_DFSDM1EN_Pos (29U)
11911#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
11912#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
11913#define RCC_APB2ENR_MDIOEN_Pos (30U)
11914#define RCC_APB2ENR_MDIOEN_Msk (0x1UL << RCC_APB2ENR_MDIOEN_Pos)
11915#define RCC_APB2ENR_MDIOEN RCC_APB2ENR_MDIOEN_Msk
11916
11917/******************** Bit definition for RCC_AHB1LPENR register *************/
11918#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
11919#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
11920#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
11921#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
11922#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
11923#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
11924#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
11925#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
11926#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
11927#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
11928#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
11929#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
11930#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
11931#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
11932#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
11933#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
11934#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
11935#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
11936#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
11937#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
11938#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
11939#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
11940#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
11941#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
11942#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
11943#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
11944#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
11945#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
11946#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos)
11947#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
11948#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
11949#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos)
11950#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
11951#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
11952#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
11953#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
11954#define RCC_AHB1LPENR_AXILPEN_Pos (13U)
11955#define RCC_AHB1LPENR_AXILPEN_Msk (0x1UL << RCC_AHB1LPENR_AXILPEN_Pos)
11956#define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk
11957#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
11958#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
11959#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
11960#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
11961#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
11962#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
11963#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
11964#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
11965#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
11966#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
11967#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
11968#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
11969#define RCC_AHB1LPENR_DTCMLPEN_Pos (20U)
11970#define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1UL << RCC_AHB1LPENR_DTCMLPEN_Pos)
11971#define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk
11972#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
11973#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
11974#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
11975#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
11976#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
11977#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
11978#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
11979#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos)
11980#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
11981#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
11982#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
11983#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
11984#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
11985#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
11986#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
11987#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
11988#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
11989#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
11990#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
11991#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
11992#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
11993#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
11994#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
11995#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
11996#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
11997#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
11998#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
11999
12000/******************** Bit definition for RCC_AHB2LPENR register *************/
12001#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
12002#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
12003#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
12004#define RCC_AHB2LPENR_JPEGLPEN_Pos (1U)
12005#define RCC_AHB2LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB2LPENR_JPEGLPEN_Pos)
12006#define RCC_AHB2LPENR_JPEGLPEN RCC_AHB2LPENR_JPEGLPEN_Msk
12007#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
12008#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos)
12009#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
12010#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
12011#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)
12012#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
12013#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
12014#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
12015#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
12016#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
12017#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
12018#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
12019
12020/******************** Bit definition for RCC_AHB3LPENR register *************/
12021#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
12022#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
12023#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
12024#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
12025#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
12026#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
12027/******************** Bit definition for RCC_APB1LPENR register *************/
12028#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
12029#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
12030#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
12031#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
12032#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
12033#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
12034#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
12035#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
12036#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
12037#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
12038#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
12039#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
12040#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
12041#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
12042#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
12043#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
12044#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
12045#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
12046#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
12047#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
12048#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
12049#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
12050#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
12051#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
12052#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
12053#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
12054#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
12055#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
12056#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos)
12057#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
12058#define RCC_APB1LPENR_RTCLPEN_Pos (10U)
12059#define RCC_APB1LPENR_RTCLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCLPEN_Pos)
12060#define RCC_APB1LPENR_RTCLPEN RCC_APB1LPENR_RTCLPEN_Msk
12061#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
12062#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
12063#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
12064#define RCC_APB1LPENR_CAN3LPEN_Pos (13U)
12065#define RCC_APB1LPENR_CAN3LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN3LPEN_Pos)
12066#define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
12067#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
12068#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
12069#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
12070#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
12071#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
12072#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
12073#define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U)
12074#define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR_SPDIFRXLPEN_Pos)
12075#define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk
12076#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
12077#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
12078#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
12079#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
12080#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
12081#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
12082#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
12083#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
12084#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
12085#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
12086#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
12087#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
12088#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
12089#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
12090#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
12091#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
12092#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
12093#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
12094#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
12095#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
12096#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
12097#define RCC_APB1LPENR_I2C4LPEN_Pos (24U)
12098#define RCC_APB1LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C4LPEN_Pos)
12099#define RCC_APB1LPENR_I2C4LPEN RCC_APB1LPENR_I2C4LPEN_Msk
12100#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
12101#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
12102#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
12103#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
12104#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
12105#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
12106#define RCC_APB1LPENR_CECLPEN_Pos (27U)
12107#define RCC_APB1LPENR_CECLPEN_Msk (0x1UL << RCC_APB1LPENR_CECLPEN_Pos)
12108#define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk
12109#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
12110#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
12111#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
12112#define RCC_APB1LPENR_DACLPEN_Pos (29U)
12113#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
12114#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
12115#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
12116#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos)
12117#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
12118#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
12119#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos)
12120#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
12121
12122/******************** Bit definition for RCC_APB2LPENR register *************/
12123#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
12124#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
12125#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
12126#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
12127#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
12128#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
12129#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
12130#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
12131#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
12132#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
12133#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
12134#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
12135#define RCC_APB2LPENR_SDMMC2LPEN_Pos (7U)
12136#define RCC_APB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC2LPEN_Pos)
12137#define RCC_APB2LPENR_SDMMC2LPEN RCC_APB2LPENR_SDMMC2LPEN_Msk
12138#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
12139#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
12140#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
12141#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
12142#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
12143#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
12144#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
12145#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
12146#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
12147#define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U)
12148#define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC1LPEN_Pos)
12149#define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk
12150#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
12151#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
12152#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
12153#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
12154#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
12155#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
12156#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
12157#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
12158#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
12159#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
12160#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
12161#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
12162#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
12163#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
12164#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
12165#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
12166#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
12167#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
12168#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
12169#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
12170#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
12171#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
12172#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos)
12173#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
12174#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
12175#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
12176#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
12177#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
12178#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)
12179#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
12180#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
12181#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos)
12182#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
12183#define RCC_APB2LPENR_DSILPEN_Pos (27U)
12184#define RCC_APB2LPENR_DSILPEN_Msk (0x1UL << RCC_APB2LPENR_DSILPEN_Pos)
12185#define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk
12186#define RCC_APB2LPENR_DFSDM1LPEN_Pos (29U)
12187#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
12188#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
12189#define RCC_APB2LPENR_MDIOLPEN_Pos (30U)
12190#define RCC_APB2LPENR_MDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_MDIOLPEN_Pos)
12191#define RCC_APB2LPENR_MDIOLPEN RCC_APB2LPENR_MDIOLPEN_Msk
12192
12193/******************** Bit definition for RCC_BDCR register ******************/
12194#define RCC_BDCR_LSEON_Pos (0U)
12195#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
12196#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
12197#define RCC_BDCR_LSERDY_Pos (1U)
12198#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
12199#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
12200#define RCC_BDCR_LSEBYP_Pos (2U)
12201#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
12202#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
12203#define RCC_BDCR_LSEDRV_Pos (3U)
12204#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
12205#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
12206#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
12207#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
12208#define RCC_BDCR_RTCSEL_Pos (8U)
12209#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
12210#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
12211#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
12212#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
12213#define RCC_BDCR_RTCEN_Pos (15U)
12214#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
12215#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
12216#define RCC_BDCR_BDRST_Pos (16U)
12217#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
12218#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
12219
12220/******************** Bit definition for RCC_CSR register *******************/
12221#define RCC_CSR_LSION_Pos (0U)
12222#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
12223#define RCC_CSR_LSION RCC_CSR_LSION_Msk
12224#define RCC_CSR_LSIRDY_Pos (1U)
12225#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
12226#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
12227#define RCC_CSR_RMVF_Pos (24U)
12228#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
12229#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
12230#define RCC_CSR_BORRSTF_Pos (25U)
12231#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
12232#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
12233#define RCC_CSR_PINRSTF_Pos (26U)
12234#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
12235#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
12236#define RCC_CSR_PORRSTF_Pos (27U)
12237#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
12238#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
12239#define RCC_CSR_SFTRSTF_Pos (28U)
12240#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
12241#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
12242#define RCC_CSR_IWDGRSTF_Pos (29U)
12243#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
12244#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
12245#define RCC_CSR_WWDGRSTF_Pos (30U)
12246#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
12247#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
12248#define RCC_CSR_LPWRRSTF_Pos (31U)
12249#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
12250#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
12251
12252/******************** Bit definition for RCC_SSCGR register *****************/
12253#define RCC_SSCGR_MODPER_Pos (0U)
12254#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
12255#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
12256#define RCC_SSCGR_INCSTEP_Pos (13U)
12257#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
12258#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
12259#define RCC_SSCGR_SPREADSEL_Pos (30U)
12260#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
12261#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
12262#define RCC_SSCGR_SSCGEN_Pos (31U)
12263#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
12264#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
12265
12266/******************** Bit definition for RCC_PLLI2SCFGR register ************/
12267#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
12268#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
12269#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
12270#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
12271#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
12272#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
12273#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
12274#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
12275#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
12276#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
12277#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
12278#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
12279#define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U)
12280#define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
12281#define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk
12282#define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
12283#define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SP_Pos)
12284#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
12285#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
12286#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
12287#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
12288#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
12289#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
12290#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
12291#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
12292#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
12293#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
12294#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
12295#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
12296#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
12298/******************** Bit definition for RCC_PLLSAICFGR register ************/
12299#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
12300#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos)
12301#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
12302#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
12303#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
12304#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
12305#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
12306#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
12307#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
12308#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
12309#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
12310#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
12311#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
12312#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
12313#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
12314#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
12315#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
12316#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
12317#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
12318#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
12319#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
12320#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
12321#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
12322#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
12323#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
12324#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
12325#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
12326#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
12327#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
12328#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
12330/******************** Bit definition for RCC_DCKCFGR1 register ***************/
12331#define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U)
12332#define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
12333#define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk
12334#define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
12335#define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
12336#define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
12337#define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
12338#define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
12340#define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U)
12341#define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
12342#define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk
12343#define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
12344#define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
12345#define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
12346#define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
12347#define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
12349#define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U)
12350#define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos)
12351#define RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR_Msk
12352#define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos)
12353#define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR1_PLLSAIDIVR_Pos)
12355/*
12356 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
12357 */
12358#define RCC_SAI1SEL_PLLSRC_SUPPORT
12359#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
12360#define RCC_DCKCFGR1_SAI1SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI1SEL_Pos)
12361#define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk
12362#define RCC_DCKCFGR1_SAI1SEL_0 (0x1UL << RCC_DCKCFGR1_SAI1SEL_Pos)
12363#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos)
12365/*
12366 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
12367 */
12368#define RCC_SAI2SEL_PLLSRC_SUPPORT
12369#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
12370#define RCC_DCKCFGR1_SAI2SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI2SEL_Pos)
12371#define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk
12372#define RCC_DCKCFGR1_SAI2SEL_0 (0x1UL << RCC_DCKCFGR1_SAI2SEL_Pos)
12373#define RCC_DCKCFGR1_SAI2SEL_1 (0x2UL << RCC_DCKCFGR1_SAI2SEL_Pos)
12375#define RCC_DCKCFGR1_TIMPRE_Pos (24U)
12376#define RCC_DCKCFGR1_TIMPRE_Msk (0x1UL << RCC_DCKCFGR1_TIMPRE_Pos)
12377#define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk
12378#define RCC_DCKCFGR1_DFSDM1SEL_Pos (25U)
12379#define RCC_DCKCFGR1_DFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR1_DFSDM1SEL_Pos)
12380#define RCC_DCKCFGR1_DFSDM1SEL RCC_DCKCFGR1_DFSDM1SEL_Msk
12381#define RCC_DCKCFGR1_ADFSDM1SEL_Pos (26U)
12382#define RCC_DCKCFGR1_ADFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR1_ADFSDM1SEL_Pos)
12383#define RCC_DCKCFGR1_ADFSDM1SEL RCC_DCKCFGR1_ADFSDM1SEL_Msk
12384
12385/******************** Bit definition for RCC_DCKCFGR2 register ***************/
12386#define RCC_DCKCFGR2_USART1SEL_Pos (0U)
12387#define RCC_DCKCFGR2_USART1SEL_Msk (0x3UL << RCC_DCKCFGR2_USART1SEL_Pos)
12388#define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk
12389#define RCC_DCKCFGR2_USART1SEL_0 (0x1UL << RCC_DCKCFGR2_USART1SEL_Pos)
12390#define RCC_DCKCFGR2_USART1SEL_1 (0x2UL << RCC_DCKCFGR2_USART1SEL_Pos)
12391#define RCC_DCKCFGR2_USART2SEL_Pos (2U)
12392#define RCC_DCKCFGR2_USART2SEL_Msk (0x3UL << RCC_DCKCFGR2_USART2SEL_Pos)
12393#define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk
12394#define RCC_DCKCFGR2_USART2SEL_0 (0x1UL << RCC_DCKCFGR2_USART2SEL_Pos)
12395#define RCC_DCKCFGR2_USART2SEL_1 (0x2UL << RCC_DCKCFGR2_USART2SEL_Pos)
12396#define RCC_DCKCFGR2_USART3SEL_Pos (4U)
12397#define RCC_DCKCFGR2_USART3SEL_Msk (0x3UL << RCC_DCKCFGR2_USART3SEL_Pos)
12398#define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk
12399#define RCC_DCKCFGR2_USART3SEL_0 (0x1UL << RCC_DCKCFGR2_USART3SEL_Pos)
12400#define RCC_DCKCFGR2_USART3SEL_1 (0x2UL << RCC_DCKCFGR2_USART3SEL_Pos)
12401#define RCC_DCKCFGR2_UART4SEL_Pos (6U)
12402#define RCC_DCKCFGR2_UART4SEL_Msk (0x3UL << RCC_DCKCFGR2_UART4SEL_Pos)
12403#define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk
12404#define RCC_DCKCFGR2_UART4SEL_0 (0x1UL << RCC_DCKCFGR2_UART4SEL_Pos)
12405#define RCC_DCKCFGR2_UART4SEL_1 (0x2UL << RCC_DCKCFGR2_UART4SEL_Pos)
12406#define RCC_DCKCFGR2_UART5SEL_Pos (8U)
12407#define RCC_DCKCFGR2_UART5SEL_Msk (0x3UL << RCC_DCKCFGR2_UART5SEL_Pos)
12408#define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk
12409#define RCC_DCKCFGR2_UART5SEL_0 (0x1UL << RCC_DCKCFGR2_UART5SEL_Pos)
12410#define RCC_DCKCFGR2_UART5SEL_1 (0x2UL << RCC_DCKCFGR2_UART5SEL_Pos)
12411#define RCC_DCKCFGR2_USART6SEL_Pos (10U)
12412#define RCC_DCKCFGR2_USART6SEL_Msk (0x3UL << RCC_DCKCFGR2_USART6SEL_Pos)
12413#define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk
12414#define RCC_DCKCFGR2_USART6SEL_0 (0x1UL << RCC_DCKCFGR2_USART6SEL_Pos)
12415#define RCC_DCKCFGR2_USART6SEL_1 (0x2UL << RCC_DCKCFGR2_USART6SEL_Pos)
12416#define RCC_DCKCFGR2_UART7SEL_Pos (12U)
12417#define RCC_DCKCFGR2_UART7SEL_Msk (0x3UL << RCC_DCKCFGR2_UART7SEL_Pos)
12418#define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk
12419#define RCC_DCKCFGR2_UART7SEL_0 (0x1UL << RCC_DCKCFGR2_UART7SEL_Pos)
12420#define RCC_DCKCFGR2_UART7SEL_1 (0x2UL << RCC_DCKCFGR2_UART7SEL_Pos)
12421#define RCC_DCKCFGR2_UART8SEL_Pos (14U)
12422#define RCC_DCKCFGR2_UART8SEL_Msk (0x3UL << RCC_DCKCFGR2_UART8SEL_Pos)
12423#define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk
12424#define RCC_DCKCFGR2_UART8SEL_0 (0x1UL << RCC_DCKCFGR2_UART8SEL_Pos)
12425#define RCC_DCKCFGR2_UART8SEL_1 (0x2UL << RCC_DCKCFGR2_UART8SEL_Pos)
12426#define RCC_DCKCFGR2_I2C1SEL_Pos (16U)
12427#define RCC_DCKCFGR2_I2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C1SEL_Pos)
12428#define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk
12429#define RCC_DCKCFGR2_I2C1SEL_0 (0x1UL << RCC_DCKCFGR2_I2C1SEL_Pos)
12430#define RCC_DCKCFGR2_I2C1SEL_1 (0x2UL << RCC_DCKCFGR2_I2C1SEL_Pos)
12431#define RCC_DCKCFGR2_I2C2SEL_Pos (18U)
12432#define RCC_DCKCFGR2_I2C2SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C2SEL_Pos)
12433#define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk
12434#define RCC_DCKCFGR2_I2C2SEL_0 (0x1UL << RCC_DCKCFGR2_I2C2SEL_Pos)
12435#define RCC_DCKCFGR2_I2C2SEL_1 (0x2UL << RCC_DCKCFGR2_I2C2SEL_Pos)
12436#define RCC_DCKCFGR2_I2C3SEL_Pos (20U)
12437#define RCC_DCKCFGR2_I2C3SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C3SEL_Pos)
12438#define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk
12439#define RCC_DCKCFGR2_I2C3SEL_0 (0x1UL << RCC_DCKCFGR2_I2C3SEL_Pos)
12440#define RCC_DCKCFGR2_I2C3SEL_1 (0x2UL << RCC_DCKCFGR2_I2C3SEL_Pos)
12441#define RCC_DCKCFGR2_I2C4SEL_Pos (22U)
12442#define RCC_DCKCFGR2_I2C4SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C4SEL_Pos)
12443#define RCC_DCKCFGR2_I2C4SEL RCC_DCKCFGR2_I2C4SEL_Msk
12444#define RCC_DCKCFGR2_I2C4SEL_0 (0x1UL << RCC_DCKCFGR2_I2C4SEL_Pos)
12445#define RCC_DCKCFGR2_I2C4SEL_1 (0x2UL << RCC_DCKCFGR2_I2C4SEL_Pos)
12446#define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U)
12447#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
12448#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
12449#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
12450#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
12451#define RCC_DCKCFGR2_CECSEL_Pos (26U)
12452#define RCC_DCKCFGR2_CECSEL_Msk (0x1UL << RCC_DCKCFGR2_CECSEL_Pos)
12453#define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk
12454#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
12455#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos)
12456#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
12457#define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U)
12458#define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC1SEL_Pos)
12459#define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk
12460#define RCC_DCKCFGR2_SDMMC2SEL_Pos (29U)
12461#define RCC_DCKCFGR2_SDMMC2SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC2SEL_Pos)
12462#define RCC_DCKCFGR2_SDMMC2SEL RCC_DCKCFGR2_SDMMC2SEL_Msk
12463#define RCC_DCKCFGR2_DSISEL_Pos (30U)
12464#define RCC_DCKCFGR2_DSISEL_Msk (0x1UL << RCC_DCKCFGR2_DSISEL_Pos)
12465#define RCC_DCKCFGR2_DSISEL RCC_DCKCFGR2_DSISEL_Msk
12466
12467/******************************************************************************/
12468/* */
12469/* RNG */
12470/* */
12471/******************************************************************************/
12472/******************** Bits definition for RNG_CR register *******************/
12473#define RNG_CR_RNGEN_Pos (2U)
12474#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
12475#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
12476#define RNG_CR_IE_Pos (3U)
12477#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
12478#define RNG_CR_IE RNG_CR_IE_Msk
12479
12480/******************** Bits definition for RNG_SR register *******************/
12481#define RNG_SR_DRDY_Pos (0U)
12482#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
12483#define RNG_SR_DRDY RNG_SR_DRDY_Msk
12484#define RNG_SR_CECS_Pos (1U)
12485#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
12486#define RNG_SR_CECS RNG_SR_CECS_Msk
12487#define RNG_SR_SECS_Pos (2U)
12488#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
12489#define RNG_SR_SECS RNG_SR_SECS_Msk
12490#define RNG_SR_CEIS_Pos (5U)
12491#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
12492#define RNG_SR_CEIS RNG_SR_CEIS_Msk
12493#define RNG_SR_SEIS_Pos (6U)
12494#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
12495#define RNG_SR_SEIS RNG_SR_SEIS_Msk
12496
12497/******************************************************************************/
12498/* */
12499/* Real-Time Clock (RTC) */
12500/* */
12501/******************************************************************************/
12502/******************** Bits definition for RTC_TR register *******************/
12503#define RTC_TR_PM_Pos (22U)
12504#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
12505#define RTC_TR_PM RTC_TR_PM_Msk
12506#define RTC_TR_HT_Pos (20U)
12507#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
12508#define RTC_TR_HT RTC_TR_HT_Msk
12509#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
12510#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
12511#define RTC_TR_HU_Pos (16U)
12512#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
12513#define RTC_TR_HU RTC_TR_HU_Msk
12514#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
12515#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
12516#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
12517#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
12518#define RTC_TR_MNT_Pos (12U)
12519#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
12520#define RTC_TR_MNT RTC_TR_MNT_Msk
12521#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
12522#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
12523#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
12524#define RTC_TR_MNU_Pos (8U)
12525#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
12526#define RTC_TR_MNU RTC_TR_MNU_Msk
12527#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
12528#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
12529#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
12530#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
12531#define RTC_TR_ST_Pos (4U)
12532#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
12533#define RTC_TR_ST RTC_TR_ST_Msk
12534#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
12535#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
12536#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
12537#define RTC_TR_SU_Pos (0U)
12538#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
12539#define RTC_TR_SU RTC_TR_SU_Msk
12540#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
12541#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
12542#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
12543#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
12545/******************** Bits definition for RTC_DR register *******************/
12546#define RTC_DR_YT_Pos (20U)
12547#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
12548#define RTC_DR_YT RTC_DR_YT_Msk
12549#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
12550#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
12551#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
12552#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
12553#define RTC_DR_YU_Pos (16U)
12554#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
12555#define RTC_DR_YU RTC_DR_YU_Msk
12556#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
12557#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
12558#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
12559#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
12560#define RTC_DR_WDU_Pos (13U)
12561#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
12562#define RTC_DR_WDU RTC_DR_WDU_Msk
12563#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
12564#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
12565#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
12566#define RTC_DR_MT_Pos (12U)
12567#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
12568#define RTC_DR_MT RTC_DR_MT_Msk
12569#define RTC_DR_MU_Pos (8U)
12570#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
12571#define RTC_DR_MU RTC_DR_MU_Msk
12572#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
12573#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
12574#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
12575#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
12576#define RTC_DR_DT_Pos (4U)
12577#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
12578#define RTC_DR_DT RTC_DR_DT_Msk
12579#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
12580#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
12581#define RTC_DR_DU_Pos (0U)
12582#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
12583#define RTC_DR_DU RTC_DR_DU_Msk
12584#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
12585#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
12586#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
12587#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
12589/******************** Bits definition for RTC_CR register *******************/
12590#define RTC_CR_ITSE_Pos (24U)
12591#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
12592#define RTC_CR_ITSE RTC_CR_ITSE_Msk
12593#define RTC_CR_COE_Pos (23U)
12594#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
12595#define RTC_CR_COE RTC_CR_COE_Msk
12596#define RTC_CR_OSEL_Pos (21U)
12597#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
12598#define RTC_CR_OSEL RTC_CR_OSEL_Msk
12599#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
12600#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
12601#define RTC_CR_POL_Pos (20U)
12602#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
12603#define RTC_CR_POL RTC_CR_POL_Msk
12604#define RTC_CR_COSEL_Pos (19U)
12605#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
12606#define RTC_CR_COSEL RTC_CR_COSEL_Msk
12607#define RTC_CR_BKP_Pos (18U)
12608#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
12609#define RTC_CR_BKP RTC_CR_BKP_Msk
12610#define RTC_CR_SUB1H_Pos (17U)
12611#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
12612#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
12613#define RTC_CR_ADD1H_Pos (16U)
12614#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
12615#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
12616#define RTC_CR_TSIE_Pos (15U)
12617#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
12618#define RTC_CR_TSIE RTC_CR_TSIE_Msk
12619#define RTC_CR_WUTIE_Pos (14U)
12620#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
12621#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
12622#define RTC_CR_ALRBIE_Pos (13U)
12623#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
12624#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
12625#define RTC_CR_ALRAIE_Pos (12U)
12626#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
12627#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
12628#define RTC_CR_TSE_Pos (11U)
12629#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
12630#define RTC_CR_TSE RTC_CR_TSE_Msk
12631#define RTC_CR_WUTE_Pos (10U)
12632#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
12633#define RTC_CR_WUTE RTC_CR_WUTE_Msk
12634#define RTC_CR_ALRBE_Pos (9U)
12635#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
12636#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
12637#define RTC_CR_ALRAE_Pos (8U)
12638#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
12639#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
12640#define RTC_CR_FMT_Pos (6U)
12641#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
12642#define RTC_CR_FMT RTC_CR_FMT_Msk
12643#define RTC_CR_BYPSHAD_Pos (5U)
12644#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
12645#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
12646#define RTC_CR_REFCKON_Pos (4U)
12647#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
12648#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
12649#define RTC_CR_TSEDGE_Pos (3U)
12650#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
12651#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
12652#define RTC_CR_WUCKSEL_Pos (0U)
12653#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
12654#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
12655#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
12656#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
12657#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
12659/* Legacy define */
12660#define RTC_CR_BCK RTC_CR_BKP
12661
12662/******************** Bits definition for RTC_ISR register ******************/
12663#define RTC_ISR_ITSF_Pos (17U)
12664#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
12665#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
12666#define RTC_ISR_RECALPF_Pos (16U)
12667#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
12668#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
12669#define RTC_ISR_TAMP3F_Pos (15U)
12670#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
12671#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
12672#define RTC_ISR_TAMP2F_Pos (14U)
12673#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
12674#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
12675#define RTC_ISR_TAMP1F_Pos (13U)
12676#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
12677#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
12678#define RTC_ISR_TSOVF_Pos (12U)
12679#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
12680#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
12681#define RTC_ISR_TSF_Pos (11U)
12682#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
12683#define RTC_ISR_TSF RTC_ISR_TSF_Msk
12684#define RTC_ISR_WUTF_Pos (10U)
12685#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
12686#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
12687#define RTC_ISR_ALRBF_Pos (9U)
12688#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
12689#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
12690#define RTC_ISR_ALRAF_Pos (8U)
12691#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
12692#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
12693#define RTC_ISR_INIT_Pos (7U)
12694#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
12695#define RTC_ISR_INIT RTC_ISR_INIT_Msk
12696#define RTC_ISR_INITF_Pos (6U)
12697#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
12698#define RTC_ISR_INITF RTC_ISR_INITF_Msk
12699#define RTC_ISR_RSF_Pos (5U)
12700#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
12701#define RTC_ISR_RSF RTC_ISR_RSF_Msk
12702#define RTC_ISR_INITS_Pos (4U)
12703#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
12704#define RTC_ISR_INITS RTC_ISR_INITS_Msk
12705#define RTC_ISR_SHPF_Pos (3U)
12706#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
12707#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
12708#define RTC_ISR_WUTWF_Pos (2U)
12709#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
12710#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
12711#define RTC_ISR_ALRBWF_Pos (1U)
12712#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
12713#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
12714#define RTC_ISR_ALRAWF_Pos (0U)
12715#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
12716#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
12717
12718/******************** Bits definition for RTC_PRER register *****************/
12719#define RTC_PRER_PREDIV_A_Pos (16U)
12720#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
12721#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
12722#define RTC_PRER_PREDIV_S_Pos (0U)
12723#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
12724#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
12725
12726/******************** Bits definition for RTC_WUTR register *****************/
12727#define RTC_WUTR_WUT_Pos (0U)
12728#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
12729#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
12730
12731/******************** Bits definition for RTC_ALRMAR register ***************/
12732#define RTC_ALRMAR_MSK4_Pos (31U)
12733#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
12734#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
12735#define RTC_ALRMAR_WDSEL_Pos (30U)
12736#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
12737#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
12738#define RTC_ALRMAR_DT_Pos (28U)
12739#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
12740#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
12741#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
12742#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
12743#define RTC_ALRMAR_DU_Pos (24U)
12744#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
12745#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
12746#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
12747#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
12748#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
12749#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
12750#define RTC_ALRMAR_MSK3_Pos (23U)
12751#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
12752#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
12753#define RTC_ALRMAR_PM_Pos (22U)
12754#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
12755#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
12756#define RTC_ALRMAR_HT_Pos (20U)
12757#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
12758#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
12759#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
12760#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
12761#define RTC_ALRMAR_HU_Pos (16U)
12762#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
12763#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
12764#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
12765#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
12766#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
12767#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
12768#define RTC_ALRMAR_MSK2_Pos (15U)
12769#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
12770#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
12771#define RTC_ALRMAR_MNT_Pos (12U)
12772#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
12773#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
12774#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
12775#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
12776#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
12777#define RTC_ALRMAR_MNU_Pos (8U)
12778#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
12779#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
12780#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
12781#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
12782#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
12783#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
12784#define RTC_ALRMAR_MSK1_Pos (7U)
12785#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
12786#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
12787#define RTC_ALRMAR_ST_Pos (4U)
12788#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
12789#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
12790#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
12791#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
12792#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
12793#define RTC_ALRMAR_SU_Pos (0U)
12794#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
12795#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
12796#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
12797#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
12798#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
12799#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
12801/******************** Bits definition for RTC_ALRMBR register ***************/
12802#define RTC_ALRMBR_MSK4_Pos (31U)
12803#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
12804#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
12805#define RTC_ALRMBR_WDSEL_Pos (30U)
12806#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
12807#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
12808#define RTC_ALRMBR_DT_Pos (28U)
12809#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
12810#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
12811#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
12812#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
12813#define RTC_ALRMBR_DU_Pos (24U)
12814#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
12815#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
12816#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
12817#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
12818#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
12819#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
12820#define RTC_ALRMBR_MSK3_Pos (23U)
12821#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
12822#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
12823#define RTC_ALRMBR_PM_Pos (22U)
12824#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
12825#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
12826#define RTC_ALRMBR_HT_Pos (20U)
12827#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
12828#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
12829#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
12830#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
12831#define RTC_ALRMBR_HU_Pos (16U)
12832#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
12833#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
12834#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
12835#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
12836#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
12837#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
12838#define RTC_ALRMBR_MSK2_Pos (15U)
12839#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
12840#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
12841#define RTC_ALRMBR_MNT_Pos (12U)
12842#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
12843#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
12844#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
12845#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
12846#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
12847#define RTC_ALRMBR_MNU_Pos (8U)
12848#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
12849#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
12850#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
12851#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
12852#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
12853#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
12854#define RTC_ALRMBR_MSK1_Pos (7U)
12855#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
12856#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
12857#define RTC_ALRMBR_ST_Pos (4U)
12858#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
12859#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
12860#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
12861#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
12862#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
12863#define RTC_ALRMBR_SU_Pos (0U)
12864#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
12865#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
12866#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
12867#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
12868#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
12869#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
12871/******************** Bits definition for RTC_WPR register ******************/
12872#define RTC_WPR_KEY_Pos (0U)
12873#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
12874#define RTC_WPR_KEY RTC_WPR_KEY_Msk
12875
12876/******************** Bits definition for RTC_SSR register ******************/
12877#define RTC_SSR_SS_Pos (0U)
12878#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
12879#define RTC_SSR_SS RTC_SSR_SS_Msk
12880
12881/******************** Bits definition for RTC_SHIFTR register ***************/
12882#define RTC_SHIFTR_SUBFS_Pos (0U)
12883#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
12884#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
12885#define RTC_SHIFTR_ADD1S_Pos (31U)
12886#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
12887#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
12888
12889/******************** Bits definition for RTC_TSTR register *****************/
12890#define RTC_TSTR_PM_Pos (22U)
12891#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
12892#define RTC_TSTR_PM RTC_TSTR_PM_Msk
12893#define RTC_TSTR_HT_Pos (20U)
12894#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
12895#define RTC_TSTR_HT RTC_TSTR_HT_Msk
12896#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
12897#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
12898#define RTC_TSTR_HU_Pos (16U)
12899#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
12900#define RTC_TSTR_HU RTC_TSTR_HU_Msk
12901#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
12902#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
12903#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
12904#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
12905#define RTC_TSTR_MNT_Pos (12U)
12906#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
12907#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
12908#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
12909#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
12910#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
12911#define RTC_TSTR_MNU_Pos (8U)
12912#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
12913#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
12914#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
12915#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
12916#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
12917#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
12918#define RTC_TSTR_ST_Pos (4U)
12919#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
12920#define RTC_TSTR_ST RTC_TSTR_ST_Msk
12921#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
12922#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
12923#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
12924#define RTC_TSTR_SU_Pos (0U)
12925#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
12926#define RTC_TSTR_SU RTC_TSTR_SU_Msk
12927#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
12928#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
12929#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
12930#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
12932/******************** Bits definition for RTC_TSDR register *****************/
12933#define RTC_TSDR_WDU_Pos (13U)
12934#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
12935#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
12936#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
12937#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
12938#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
12939#define RTC_TSDR_MT_Pos (12U)
12940#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
12941#define RTC_TSDR_MT RTC_TSDR_MT_Msk
12942#define RTC_TSDR_MU_Pos (8U)
12943#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
12944#define RTC_TSDR_MU RTC_TSDR_MU_Msk
12945#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
12946#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
12947#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
12948#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
12949#define RTC_TSDR_DT_Pos (4U)
12950#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
12951#define RTC_TSDR_DT RTC_TSDR_DT_Msk
12952#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
12953#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
12954#define RTC_TSDR_DU_Pos (0U)
12955#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
12956#define RTC_TSDR_DU RTC_TSDR_DU_Msk
12957#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
12958#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
12959#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
12960#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
12962/******************** Bits definition for RTC_TSSSR register ****************/
12963#define RTC_TSSSR_SS_Pos (0U)
12964#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
12965#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12966
12967/******************** Bits definition for RTC_CAL register *****************/
12968#define RTC_CALR_CALP_Pos (15U)
12969#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
12970#define RTC_CALR_CALP RTC_CALR_CALP_Msk
12971#define RTC_CALR_CALW8_Pos (14U)
12972#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
12973#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12974#define RTC_CALR_CALW16_Pos (13U)
12975#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
12976#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12977#define RTC_CALR_CALM_Pos (0U)
12978#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
12979#define RTC_CALR_CALM RTC_CALR_CALM_Msk
12980#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
12981#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
12982#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
12983#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
12984#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
12985#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
12986#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
12987#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
12988#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
12990/******************** Bits definition for RTC_TAMPCR register ****************/
12991#define RTC_TAMPCR_TAMP3MF_Pos (24U)
12992#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
12993#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
12994#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
12995#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
12996#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
12997#define RTC_TAMPCR_TAMP3IE_Pos (22U)
12998#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
12999#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
13000#define RTC_TAMPCR_TAMP2MF_Pos (21U)
13001#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
13002#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
13003#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
13004#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
13005#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
13006#define RTC_TAMPCR_TAMP2IE_Pos (19U)
13007#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
13008#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
13009#define RTC_TAMPCR_TAMP1MF_Pos (18U)
13010#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
13011#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
13012#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
13013#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
13014#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
13015#define RTC_TAMPCR_TAMP1IE_Pos (16U)
13016#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
13017#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
13018#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
13019#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
13020#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
13021#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
13022#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
13023#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
13024#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
13025#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
13026#define RTC_TAMPCR_TAMPFLT_Pos (11U)
13027#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
13028#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
13029#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
13030#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
13031#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
13032#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
13033#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
13034#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
13035#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
13036#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
13037#define RTC_TAMPCR_TAMPTS_Pos (7U)
13038#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
13039#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
13040#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
13041#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
13042#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
13043#define RTC_TAMPCR_TAMP3E_Pos (5U)
13044#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
13045#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
13046#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
13047#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
13048#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
13049#define RTC_TAMPCR_TAMP2E_Pos (3U)
13050#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
13051#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
13052#define RTC_TAMPCR_TAMPIE_Pos (2U)
13053#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
13054#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
13055#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
13056#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
13057#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
13058#define RTC_TAMPCR_TAMP1E_Pos (0U)
13059#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
13060#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
13061
13062
13063/******************** Bits definition for RTC_ALRMASSR register *************/
13064#define RTC_ALRMASSR_MASKSS_Pos (24U)
13065#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
13066#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
13067#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
13068#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
13069#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
13070#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
13071#define RTC_ALRMASSR_SS_Pos (0U)
13072#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
13073#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
13074
13075/******************** Bits definition for RTC_ALRMBSSR register *************/
13076#define RTC_ALRMBSSR_MASKSS_Pos (24U)
13077#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
13078#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
13079#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
13080#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
13081#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
13082#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
13083#define RTC_ALRMBSSR_SS_Pos (0U)
13084#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
13085#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
13086
13087/******************** Bits definition for RTC_OR register ****************/
13088#define RTC_OR_TSINSEL_Pos (1U)
13089#define RTC_OR_TSINSEL_Msk (0x3UL << RTC_OR_TSINSEL_Pos)
13090#define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk
13091#define RTC_OR_TSINSEL_0 (0x1UL << RTC_OR_TSINSEL_Pos)
13092#define RTC_OR_TSINSEL_1 (0x2UL << RTC_OR_TSINSEL_Pos)
13093#define RTC_OR_ALARMOUTTYPE_Pos (3U)
13094#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
13095#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
13096/* Legacy defines*/
13097#define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE
13098
13099/******************** Bits definition for RTC_BKP0R register ****************/
13100#define RTC_BKP0R_Pos (0U)
13101#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
13102#define RTC_BKP0R RTC_BKP0R_Msk
13103
13104/******************** Bits definition for RTC_BKP1R register ****************/
13105#define RTC_BKP1R_Pos (0U)
13106#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
13107#define RTC_BKP1R RTC_BKP1R_Msk
13108
13109/******************** Bits definition for RTC_BKP2R register ****************/
13110#define RTC_BKP2R_Pos (0U)
13111#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
13112#define RTC_BKP2R RTC_BKP2R_Msk
13113
13114/******************** Bits definition for RTC_BKP3R register ****************/
13115#define RTC_BKP3R_Pos (0U)
13116#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
13117#define RTC_BKP3R RTC_BKP3R_Msk
13118
13119/******************** Bits definition for RTC_BKP4R register ****************/
13120#define RTC_BKP4R_Pos (0U)
13121#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
13122#define RTC_BKP4R RTC_BKP4R_Msk
13123
13124/******************** Bits definition for RTC_BKP5R register ****************/
13125#define RTC_BKP5R_Pos (0U)
13126#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
13127#define RTC_BKP5R RTC_BKP5R_Msk
13128
13129/******************** Bits definition for RTC_BKP6R register ****************/
13130#define RTC_BKP6R_Pos (0U)
13131#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
13132#define RTC_BKP6R RTC_BKP6R_Msk
13133
13134/******************** Bits definition for RTC_BKP7R register ****************/
13135#define RTC_BKP7R_Pos (0U)
13136#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
13137#define RTC_BKP7R RTC_BKP7R_Msk
13138
13139/******************** Bits definition for RTC_BKP8R register ****************/
13140#define RTC_BKP8R_Pos (0U)
13141#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
13142#define RTC_BKP8R RTC_BKP8R_Msk
13143
13144/******************** Bits definition for RTC_BKP9R register ****************/
13145#define RTC_BKP9R_Pos (0U)
13146#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
13147#define RTC_BKP9R RTC_BKP9R_Msk
13148
13149/******************** Bits definition for RTC_BKP10R register ***************/
13150#define RTC_BKP10R_Pos (0U)
13151#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
13152#define RTC_BKP10R RTC_BKP10R_Msk
13153
13154/******************** Bits definition for RTC_BKP11R register ***************/
13155#define RTC_BKP11R_Pos (0U)
13156#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
13157#define RTC_BKP11R RTC_BKP11R_Msk
13158
13159/******************** Bits definition for RTC_BKP12R register ***************/
13160#define RTC_BKP12R_Pos (0U)
13161#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
13162#define RTC_BKP12R RTC_BKP12R_Msk
13163
13164/******************** Bits definition for RTC_BKP13R register ***************/
13165#define RTC_BKP13R_Pos (0U)
13166#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
13167#define RTC_BKP13R RTC_BKP13R_Msk
13168
13169/******************** Bits definition for RTC_BKP14R register ***************/
13170#define RTC_BKP14R_Pos (0U)
13171#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
13172#define RTC_BKP14R RTC_BKP14R_Msk
13173
13174/******************** Bits definition for RTC_BKP15R register ***************/
13175#define RTC_BKP15R_Pos (0U)
13176#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
13177#define RTC_BKP15R RTC_BKP15R_Msk
13178
13179/******************** Bits definition for RTC_BKP16R register ***************/
13180#define RTC_BKP16R_Pos (0U)
13181#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
13182#define RTC_BKP16R RTC_BKP16R_Msk
13183
13184/******************** Bits definition for RTC_BKP17R register ***************/
13185#define RTC_BKP17R_Pos (0U)
13186#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
13187#define RTC_BKP17R RTC_BKP17R_Msk
13188
13189/******************** Bits definition for RTC_BKP18R register ***************/
13190#define RTC_BKP18R_Pos (0U)
13191#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
13192#define RTC_BKP18R RTC_BKP18R_Msk
13193
13194/******************** Bits definition for RTC_BKP19R register ***************/
13195#define RTC_BKP19R_Pos (0U)
13196#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
13197#define RTC_BKP19R RTC_BKP19R_Msk
13198
13199/******************** Bits definition for RTC_BKP20R register ***************/
13200#define RTC_BKP20R_Pos (0U)
13201#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
13202#define RTC_BKP20R RTC_BKP20R_Msk
13203
13204/******************** Bits definition for RTC_BKP21R register ***************/
13205#define RTC_BKP21R_Pos (0U)
13206#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
13207#define RTC_BKP21R RTC_BKP21R_Msk
13208
13209/******************** Bits definition for RTC_BKP22R register ***************/
13210#define RTC_BKP22R_Pos (0U)
13211#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
13212#define RTC_BKP22R RTC_BKP22R_Msk
13213
13214/******************** Bits definition for RTC_BKP23R register ***************/
13215#define RTC_BKP23R_Pos (0U)
13216#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
13217#define RTC_BKP23R RTC_BKP23R_Msk
13218
13219/******************** Bits definition for RTC_BKP24R register ***************/
13220#define RTC_BKP24R_Pos (0U)
13221#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
13222#define RTC_BKP24R RTC_BKP24R_Msk
13223
13224/******************** Bits definition for RTC_BKP25R register ***************/
13225#define RTC_BKP25R_Pos (0U)
13226#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
13227#define RTC_BKP25R RTC_BKP25R_Msk
13228
13229/******************** Bits definition for RTC_BKP26R register ***************/
13230#define RTC_BKP26R_Pos (0U)
13231#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
13232#define RTC_BKP26R RTC_BKP26R_Msk
13233
13234/******************** Bits definition for RTC_BKP27R register ***************/
13235#define RTC_BKP27R_Pos (0U)
13236#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
13237#define RTC_BKP27R RTC_BKP27R_Msk
13238
13239/******************** Bits definition for RTC_BKP28R register ***************/
13240#define RTC_BKP28R_Pos (0U)
13241#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
13242#define RTC_BKP28R RTC_BKP28R_Msk
13243
13244/******************** Bits definition for RTC_BKP29R register ***************/
13245#define RTC_BKP29R_Pos (0U)
13246#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
13247#define RTC_BKP29R RTC_BKP29R_Msk
13248
13249/******************** Bits definition for RTC_BKP30R register ***************/
13250#define RTC_BKP30R_Pos (0U)
13251#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
13252#define RTC_BKP30R RTC_BKP30R_Msk
13253
13254/******************** Bits definition for RTC_BKP31R register ***************/
13255#define RTC_BKP31R_Pos (0U)
13256#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
13257#define RTC_BKP31R RTC_BKP31R_Msk
13258
13259/******************** Number of backup registers ******************************/
13260#define RTC_BKP_NUMBER 0x00000020U
13261
13262/******************************************************************************/
13263/* */
13264/* Serial Audio Interface */
13265/* */
13266/******************************************************************************/
13267/******************** Bit definition for SAI_GCR register *******************/
13268#define SAI_GCR_SYNCIN_Pos (0U)
13269#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
13270#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
13271#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
13272#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
13274#define SAI_GCR_SYNCOUT_Pos (4U)
13275#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
13276#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
13277#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
13278#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
13280/******************* Bit definition for SAI_xCR1 register *******************/
13281#define SAI_xCR1_MODE_Pos (0U)
13282#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
13283#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
13284#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
13285#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
13287#define SAI_xCR1_PRTCFG_Pos (2U)
13288#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
13289#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
13290#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
13291#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
13293#define SAI_xCR1_DS_Pos (5U)
13294#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
13295#define SAI_xCR1_DS SAI_xCR1_DS_Msk
13296#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
13297#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
13298#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
13300#define SAI_xCR1_LSBFIRST_Pos (8U)
13301#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
13302#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
13303#define SAI_xCR1_CKSTR_Pos (9U)
13304#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
13305#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
13307#define SAI_xCR1_SYNCEN_Pos (10U)
13308#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
13309#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
13310#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
13311#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
13313#define SAI_xCR1_MONO_Pos (12U)
13314#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
13315#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
13316#define SAI_xCR1_OUTDRIV_Pos (13U)
13317#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
13318#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
13319#define SAI_xCR1_SAIEN_Pos (16U)
13320#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
13321#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
13322#define SAI_xCR1_DMAEN_Pos (17U)
13323#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
13324#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
13325#define SAI_xCR1_NODIV_Pos (19U)
13326#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
13327#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
13329#define SAI_xCR1_MCKDIV_Pos (20U)
13330#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
13331#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
13332#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
13333#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
13334#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
13335#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
13337/******************* Bit definition for SAI_xCR2 register *******************/
13338#define SAI_xCR2_FTH_Pos (0U)
13339#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
13340#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
13341#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
13342#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
13343#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
13345#define SAI_xCR2_FFLUSH_Pos (3U)
13346#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
13347#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
13348#define SAI_xCR2_TRIS_Pos (4U)
13349#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
13350#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
13351#define SAI_xCR2_MUTE_Pos (5U)
13352#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
13353#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
13354#define SAI_xCR2_MUTEVAL_Pos (6U)
13355#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
13356#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
13358#define SAI_xCR2_MUTECNT_Pos (7U)
13359#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
13360#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
13361#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
13362#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
13363#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
13364#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
13365#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
13366#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
13368#define SAI_xCR2_CPL_Pos (13U)
13369#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
13370#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
13372#define SAI_xCR2_COMP_Pos (14U)
13373#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
13374#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
13375#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
13376#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
13378/****************** Bit definition for SAI_xFRCR register *******************/
13379#define SAI_xFRCR_FRL_Pos (0U)
13380#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
13381#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
13382#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
13383#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
13384#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
13385#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
13386#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
13387#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
13388#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
13389#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
13391#define SAI_xFRCR_FSALL_Pos (8U)
13392#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
13393#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
13394#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
13395#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
13396#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
13397#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
13398#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
13399#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
13400#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
13402#define SAI_xFRCR_FSDEF_Pos (16U)
13403#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
13404#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
13405#define SAI_xFRCR_FSPOL_Pos (17U)
13406#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
13407#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
13408#define SAI_xFRCR_FSOFF_Pos (18U)
13409#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
13410#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
13412/* Legacy define */
13413#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
13414
13415/****************** Bit definition for SAI_xSLOTR register *******************/
13416#define SAI_xSLOTR_FBOFF_Pos (0U)
13417#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
13418#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
13419#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
13420#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
13421#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
13422#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
13423#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
13425#define SAI_xSLOTR_SLOTSZ_Pos (6U)
13426#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
13427#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
13428#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
13429#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
13431#define SAI_xSLOTR_NBSLOT_Pos (8U)
13432#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
13433#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
13434#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
13435#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
13436#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
13437#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
13439#define SAI_xSLOTR_SLOTEN_Pos (16U)
13440#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
13441#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
13443/******************* Bit definition for SAI_xIMR register *******************/
13444#define SAI_xIMR_OVRUDRIE_Pos (0U)
13445#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
13446#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
13447#define SAI_xIMR_MUTEDETIE_Pos (1U)
13448#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
13449#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
13450#define SAI_xIMR_WCKCFGIE_Pos (2U)
13451#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
13452#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
13453#define SAI_xIMR_FREQIE_Pos (3U)
13454#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
13455#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
13456#define SAI_xIMR_CNRDYIE_Pos (4U)
13457#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
13458#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
13459#define SAI_xIMR_AFSDETIE_Pos (5U)
13460#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
13461#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
13462#define SAI_xIMR_LFSDETIE_Pos (6U)
13463#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
13464#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
13466/******************** Bit definition for SAI_xSR register *******************/
13467#define SAI_xSR_OVRUDR_Pos (0U)
13468#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
13469#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
13470#define SAI_xSR_MUTEDET_Pos (1U)
13471#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
13472#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
13473#define SAI_xSR_WCKCFG_Pos (2U)
13474#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
13475#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
13476#define SAI_xSR_FREQ_Pos (3U)
13477#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
13478#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
13479#define SAI_xSR_CNRDY_Pos (4U)
13480#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
13481#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
13482#define SAI_xSR_AFSDET_Pos (5U)
13483#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
13484#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
13485#define SAI_xSR_LFSDET_Pos (6U)
13486#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
13487#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
13489#define SAI_xSR_FLVL_Pos (16U)
13490#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
13491#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
13492#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
13493#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
13494#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
13496/****************** Bit definition for SAI_xCLRFR register ******************/
13497#define SAI_xCLRFR_COVRUDR_Pos (0U)
13498#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
13499#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
13500#define SAI_xCLRFR_CMUTEDET_Pos (1U)
13501#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
13502#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
13503#define SAI_xCLRFR_CWCKCFG_Pos (2U)
13504#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
13505#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
13506#define SAI_xCLRFR_CFREQ_Pos (3U)
13507#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
13508#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
13509#define SAI_xCLRFR_CCNRDY_Pos (4U)
13510#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
13511#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
13512#define SAI_xCLRFR_CAFSDET_Pos (5U)
13513#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
13514#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
13515#define SAI_xCLRFR_CLFSDET_Pos (6U)
13516#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
13517#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
13519/****************** Bit definition for SAI_xDR register *********************/
13520#define SAI_xDR_DATA_Pos (0U)
13521#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
13522#define SAI_xDR_DATA SAI_xDR_DATA_Msk
13523
13524/******************************************************************************/
13525/* */
13526/* SPDIF-RX Interface */
13527/* */
13528/******************************************************************************/
13529/******************** Bit definition for SPDIF_CR register *******************/
13530#define SPDIFRX_CR_SPDIFEN_Pos (0U)
13531#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
13532#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk
13533#define SPDIFRX_CR_RXDMAEN_Pos (2U)
13534#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
13535#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk
13536#define SPDIFRX_CR_RXSTEO_Pos (3U)
13537#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
13538#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk
13539#define SPDIFRX_CR_DRFMT_Pos (4U)
13540#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos)
13541#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk
13542#define SPDIFRX_CR_PMSK_Pos (6U)
13543#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos)
13544#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk
13545#define SPDIFRX_CR_VMSK_Pos (7U)
13546#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos)
13547#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk
13548#define SPDIFRX_CR_CUMSK_Pos (8U)
13549#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos)
13550#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk
13551#define SPDIFRX_CR_PTMSK_Pos (9U)
13552#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos)
13553#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk
13554#define SPDIFRX_CR_CBDMAEN_Pos (10U)
13555#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
13556#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk
13557#define SPDIFRX_CR_CHSEL_Pos (11U)
13558#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos)
13559#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk
13560#define SPDIFRX_CR_NBTR_Pos (12U)
13561#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos)
13562#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk
13563#define SPDIFRX_CR_WFA_Pos (14U)
13564#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos)
13565#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk
13566#define SPDIFRX_CR_INSEL_Pos (16U)
13567#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos)
13568#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk
13570/******************* Bit definition for SPDIFRX_IMR register *******************/
13571#define SPDIFRX_IMR_RXNEIE_Pos (0U)
13572#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
13573#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk
13574#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
13575#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
13576#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk
13577#define SPDIFRX_IMR_PERRIE_Pos (2U)
13578#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
13579#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk
13580#define SPDIFRX_IMR_OVRIE_Pos (3U)
13581#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
13582#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk
13583#define SPDIFRX_IMR_SBLKIE_Pos (4U)
13584#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
13585#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk
13586#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
13587#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
13588#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk
13589#define SPDIFRX_IMR_IFEIE_Pos (6U)
13590#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
13591#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk
13593/******************* Bit definition for SPDIFRX_SR register *******************/
13594#define SPDIFRX_SR_RXNE_Pos (0U)
13595#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos)
13596#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk
13597#define SPDIFRX_SR_CSRNE_Pos (1U)
13598#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos)
13599#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk
13600#define SPDIFRX_SR_PERR_Pos (2U)
13601#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos)
13602#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk
13603#define SPDIFRX_SR_OVR_Pos (3U)
13604#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos)
13605#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk
13606#define SPDIFRX_SR_SBD_Pos (4U)
13607#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos)
13608#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk
13609#define SPDIFRX_SR_SYNCD_Pos (5U)
13610#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos)
13611#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk
13612#define SPDIFRX_SR_FERR_Pos (6U)
13613#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos)
13614#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk
13615#define SPDIFRX_SR_SERR_Pos (7U)
13616#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos)
13617#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk
13618#define SPDIFRX_SR_TERR_Pos (8U)
13619#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos)
13620#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk
13621#define SPDIFRX_SR_WIDTH5_Pos (16U)
13622#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
13623#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk
13625/******************* Bit definition for SPDIFRX_IFCR register *******************/
13626#define SPDIFRX_IFCR_PERRCF_Pos (2U)
13627#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
13628#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk
13629#define SPDIFRX_IFCR_OVRCF_Pos (3U)
13630#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
13631#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk
13632#define SPDIFRX_IFCR_SBDCF_Pos (4U)
13633#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
13634#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk
13635#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
13636#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
13637#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk
13639/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
13640#define SPDIFRX_DR0_DR_Pos (0U)
13641#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
13642#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk
13643#define SPDIFRX_DR0_PE_Pos (24U)
13644#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos)
13645#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk
13646#define SPDIFRX_DR0_V_Pos (25U)
13647#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos)
13648#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk
13649#define SPDIFRX_DR0_U_Pos (26U)
13650#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos)
13651#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk
13652#define SPDIFRX_DR0_C_Pos (27U)
13653#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos)
13654#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk
13655#define SPDIFRX_DR0_PT_Pos (28U)
13656#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos)
13657#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk
13659/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
13660#define SPDIFRX_DR1_DR_Pos (8U)
13661#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
13662#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk
13663#define SPDIFRX_DR1_PT_Pos (4U)
13664#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos)
13665#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk
13666#define SPDIFRX_DR1_C_Pos (3U)
13667#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos)
13668#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk
13669#define SPDIFRX_DR1_U_Pos (2U)
13670#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos)
13671#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk
13672#define SPDIFRX_DR1_V_Pos (1U)
13673#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos)
13674#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk
13675#define SPDIFRX_DR1_PE_Pos (0U)
13676#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos)
13677#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk
13679/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
13680#define SPDIFRX_DR1_DRNL1_Pos (16U)
13681#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
13682#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk
13683#define SPDIFRX_DR1_DRNL2_Pos (0U)
13684#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
13685#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk
13687/******************* Bit definition for SPDIFRX_CSR register *******************/
13688#define SPDIFRX_CSR_USR_Pos (0U)
13689#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
13690#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk
13691#define SPDIFRX_CSR_CS_Pos (16U)
13692#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos)
13693#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk
13694#define SPDIFRX_CSR_SOB_Pos (24U)
13695#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos)
13696#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk
13698/******************* Bit definition for SPDIFRX_DIR register *******************/
13699#define SPDIFRX_DIR_THI_Pos (0U)
13700#define SPDIFRX_DIR_THI_Msk (0x13FFUL << SPDIFRX_DIR_THI_Pos)
13701#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk
13702#define SPDIFRX_DIR_TLO_Pos (16U)
13703#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
13704#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk
13706/******************************************************************************/
13707/* */
13708/* SD host Interface */
13709/* */
13710/******************************************************************************/
13711/****************** Bit definition for SDMMC_POWER register ******************/
13712#define SDMMC_POWER_PWRCTRL_Pos (0U)
13713#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
13714#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
13715#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
13716#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
13718/****************** Bit definition for SDMMC_CLKCR register ******************/
13719#define SDMMC_CLKCR_CLKDIV_Pos (0U)
13720#define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)
13721#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
13722#define SDMMC_CLKCR_CLKEN_Pos (8U)
13723#define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos)
13724#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk
13725#define SDMMC_CLKCR_PWRSAV_Pos (9U)
13726#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
13727#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
13728#define SDMMC_CLKCR_BYPASS_Pos (10U)
13729#define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos)
13730#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk
13732#define SDMMC_CLKCR_WIDBUS_Pos (11U)
13733#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
13734#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
13735#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
13736#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
13738#define SDMMC_CLKCR_NEGEDGE_Pos (13U)
13739#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
13740#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
13741#define SDMMC_CLKCR_HWFC_EN_Pos (14U)
13742#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
13743#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
13745/******************* Bit definition for SDMMC_ARG register *******************/
13746#define SDMMC_ARG_CMDARG_Pos (0U)
13747#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
13748#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
13750/******************* Bit definition for SDMMC_CMD register *******************/
13751#define SDMMC_CMD_CMDINDEX_Pos (0U)
13752#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
13753#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
13755#define SDMMC_CMD_WAITRESP_Pos (6U)
13756#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
13757#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
13758#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
13759#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
13761#define SDMMC_CMD_WAITINT_Pos (8U)
13762#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
13763#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
13764#define SDMMC_CMD_WAITPEND_Pos (9U)
13765#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
13766#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
13767#define SDMMC_CMD_CPSMEN_Pos (10U)
13768#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
13769#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
13770#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
13771#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)
13772#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk
13774/***************** Bit definition for SDMMC_RESPCMD register *****************/
13775#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
13776#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
13777#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
13779/****************** Bit definition for SDMMC_RESP0 register ******************/
13780#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
13781#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
13782#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk
13784/****************** Bit definition for SDMMC_RESP1 register ******************/
13785#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
13786#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
13787#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
13789/****************** Bit definition for SDMMC_RESP2 register ******************/
13790#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
13791#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
13792#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
13794/****************** Bit definition for SDMMC_RESP3 register ******************/
13795#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
13796#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
13797#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
13799/****************** Bit definition for SDMMC_RESP4 register ******************/
13800#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
13801#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
13802#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
13804/****************** Bit definition for SDMMC_DTIMER register *****************/
13805#define SDMMC_DTIMER_DATATIME_Pos (0U)
13806#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
13807#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
13809/****************** Bit definition for SDMMC_DLEN register *******************/
13810#define SDMMC_DLEN_DATALENGTH_Pos (0U)
13811#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
13812#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
13814/****************** Bit definition for SDMMC_DCTRL register ******************/
13815#define SDMMC_DCTRL_DTEN_Pos (0U)
13816#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
13817#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
13818#define SDMMC_DCTRL_DTDIR_Pos (1U)
13819#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
13820#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
13821#define SDMMC_DCTRL_DTMODE_Pos (2U)
13822#define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
13823#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
13824#define SDMMC_DCTRL_DMAEN_Pos (3U)
13825#define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos)
13826#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk
13828#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
13829#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
13830#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
13831#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
13832#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
13833#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
13834#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
13836#define SDMMC_DCTRL_RWSTART_Pos (8U)
13837#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
13838#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
13839#define SDMMC_DCTRL_RWSTOP_Pos (9U)
13840#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
13841#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
13842#define SDMMC_DCTRL_RWMOD_Pos (10U)
13843#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
13844#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
13845#define SDMMC_DCTRL_SDIOEN_Pos (11U)
13846#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
13847#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
13849/****************** Bit definition for SDMMC_DCOUNT register *****************/
13850#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
13851#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
13852#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
13854/****************** Bit definition for SDMMC_STA registe ********************/
13855#define SDMMC_STA_CCRCFAIL_Pos (0U)
13856#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
13857#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
13858#define SDMMC_STA_DCRCFAIL_Pos (1U)
13859#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
13860#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
13861#define SDMMC_STA_CTIMEOUT_Pos (2U)
13862#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
13863#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
13864#define SDMMC_STA_DTIMEOUT_Pos (3U)
13865#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
13866#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
13867#define SDMMC_STA_TXUNDERR_Pos (4U)
13868#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
13869#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
13870#define SDMMC_STA_RXOVERR_Pos (5U)
13871#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
13872#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
13873#define SDMMC_STA_CMDREND_Pos (6U)
13874#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
13875#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
13876#define SDMMC_STA_CMDSENT_Pos (7U)
13877#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
13878#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
13879#define SDMMC_STA_DATAEND_Pos (8U)
13880#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
13881#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
13882#define SDMMC_STA_DBCKEND_Pos (10U)
13883#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
13884#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
13885#define SDMMC_STA_CMDACT_Pos (11U)
13886#define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos)
13887#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk
13888#define SDMMC_STA_TXACT_Pos (12U)
13889#define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos)
13890#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk
13891#define SDMMC_STA_RXACT_Pos (13U)
13892#define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos)
13893#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk
13894#define SDMMC_STA_TXFIFOHE_Pos (14U)
13895#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
13896#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
13897#define SDMMC_STA_RXFIFOHF_Pos (15U)
13898#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
13899#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
13900#define SDMMC_STA_TXFIFOF_Pos (16U)
13901#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
13902#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
13903#define SDMMC_STA_RXFIFOF_Pos (17U)
13904#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
13905#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
13906#define SDMMC_STA_TXFIFOE_Pos (18U)
13907#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
13908#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
13909#define SDMMC_STA_RXFIFOE_Pos (19U)
13910#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
13911#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
13912#define SDMMC_STA_TXDAVL_Pos (20U)
13913#define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos)
13914#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk
13915#define SDMMC_STA_RXDAVL_Pos (21U)
13916#define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos)
13917#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk
13918#define SDMMC_STA_SDIOIT_Pos (22U)
13919#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
13920#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
13922/******************* Bit definition for SDMMC_ICR register *******************/
13923#define SDMMC_ICR_CCRCFAILC_Pos (0U)
13924#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
13925#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
13926#define SDMMC_ICR_DCRCFAILC_Pos (1U)
13927#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
13928#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
13929#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
13930#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
13931#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
13932#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
13933#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
13934#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
13935#define SDMMC_ICR_TXUNDERRC_Pos (4U)
13936#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
13937#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
13938#define SDMMC_ICR_RXOVERRC_Pos (5U)
13939#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
13940#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
13941#define SDMMC_ICR_CMDRENDC_Pos (6U)
13942#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
13943#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
13944#define SDMMC_ICR_CMDSENTC_Pos (7U)
13945#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
13946#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
13947#define SDMMC_ICR_DATAENDC_Pos (8U)
13948#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
13949#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
13950#define SDMMC_ICR_DBCKENDC_Pos (10U)
13951#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
13952#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
13953#define SDMMC_ICR_SDIOITC_Pos (22U)
13954#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
13955#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
13957/****************** Bit definition for SDMMC_MASK register *******************/
13958#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
13959#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
13960#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
13961#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
13962#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
13963#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
13964#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
13965#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
13966#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
13967#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
13968#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
13969#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
13970#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
13971#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
13972#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
13973#define SDMMC_MASK_RXOVERRIE_Pos (5U)
13974#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
13975#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
13976#define SDMMC_MASK_CMDRENDIE_Pos (6U)
13977#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
13978#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
13979#define SDMMC_MASK_CMDSENTIE_Pos (7U)
13980#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
13981#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
13982#define SDMMC_MASK_DATAENDIE_Pos (8U)
13983#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
13984#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
13985#define SDMMC_MASK_DBCKENDIE_Pos (10U)
13986#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
13987#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
13988#define SDMMC_MASK_CMDACTIE_Pos (11U)
13989#define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos)
13990#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk
13991#define SDMMC_MASK_TXACTIE_Pos (12U)
13992#define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos)
13993#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk
13994#define SDMMC_MASK_RXACTIE_Pos (13U)
13995#define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos)
13996#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk
13997#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
13998#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
13999#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
14000#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
14001#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
14002#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
14003#define SDMMC_MASK_TXFIFOFIE_Pos (16U)
14004#define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)
14005#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk
14006#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
14007#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
14008#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
14009#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
14010#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
14011#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
14012#define SDMMC_MASK_RXFIFOEIE_Pos (19U)
14013#define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)
14014#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk
14015#define SDMMC_MASK_TXDAVLIE_Pos (20U)
14016#define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)
14017#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk
14018#define SDMMC_MASK_RXDAVLIE_Pos (21U)
14019#define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)
14020#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk
14021#define SDMMC_MASK_SDIOITIE_Pos (22U)
14022#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
14023#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
14025/***************** Bit definition for SDMMC_FIFOCNT register *****************/
14026#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
14027#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos)
14028#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk
14030/****************** Bit definition for SDMMC_FIFO register *******************/
14031#define SDMMC_FIFO_FIFODATA_Pos (0U)
14032#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
14033#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
14035/******************************************************************************/
14036/* */
14037/* Serial Peripheral Interface (SPI) */
14038/* */
14039/******************************************************************************/
14040/******************* Bit definition for SPI_CR1 register ********************/
14041#define SPI_CR1_CPHA_Pos (0U)
14042#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
14043#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
14044#define SPI_CR1_CPOL_Pos (1U)
14045#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
14046#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
14047#define SPI_CR1_MSTR_Pos (2U)
14048#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
14049#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
14050#define SPI_CR1_BR_Pos (3U)
14051#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
14052#define SPI_CR1_BR SPI_CR1_BR_Msk
14053#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
14054#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
14055#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
14056#define SPI_CR1_SPE_Pos (6U)
14057#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
14058#define SPI_CR1_SPE SPI_CR1_SPE_Msk
14059#define SPI_CR1_LSBFIRST_Pos (7U)
14060#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
14061#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
14062#define SPI_CR1_SSI_Pos (8U)
14063#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
14064#define SPI_CR1_SSI SPI_CR1_SSI_Msk
14065#define SPI_CR1_SSM_Pos (9U)
14066#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
14067#define SPI_CR1_SSM SPI_CR1_SSM_Msk
14068#define SPI_CR1_RXONLY_Pos (10U)
14069#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
14070#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
14071#define SPI_CR1_CRCL_Pos (11U)
14072#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
14073#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
14074#define SPI_CR1_CRCNEXT_Pos (12U)
14075#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
14076#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
14077#define SPI_CR1_CRCEN_Pos (13U)
14078#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
14079#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
14080#define SPI_CR1_BIDIOE_Pos (14U)
14081#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
14082#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
14083#define SPI_CR1_BIDIMODE_Pos (15U)
14084#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
14085#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
14087/******************* Bit definition for SPI_CR2 register ********************/
14088#define SPI_CR2_RXDMAEN_Pos (0U)
14089#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
14090#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
14091#define SPI_CR2_TXDMAEN_Pos (1U)
14092#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
14093#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
14094#define SPI_CR2_SSOE_Pos (2U)
14095#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
14096#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
14097#define SPI_CR2_NSSP_Pos (3U)
14098#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
14099#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
14100#define SPI_CR2_FRF_Pos (4U)
14101#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
14102#define SPI_CR2_FRF SPI_CR2_FRF_Msk
14103#define SPI_CR2_ERRIE_Pos (5U)
14104#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
14105#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
14106#define SPI_CR2_RXNEIE_Pos (6U)
14107#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
14108#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
14109#define SPI_CR2_TXEIE_Pos (7U)
14110#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
14111#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
14112#define SPI_CR2_DS_Pos (8U)
14113#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
14114#define SPI_CR2_DS SPI_CR2_DS_Msk
14115#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
14116#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
14117#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
14118#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
14119#define SPI_CR2_FRXTH_Pos (12U)
14120#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
14121#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
14122#define SPI_CR2_LDMARX_Pos (13U)
14123#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
14124#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
14125#define SPI_CR2_LDMATX_Pos (14U)
14126#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
14127#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
14129/******************** Bit definition for SPI_SR register ********************/
14130#define SPI_SR_RXNE_Pos (0U)
14131#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
14132#define SPI_SR_RXNE SPI_SR_RXNE_Msk
14133#define SPI_SR_TXE_Pos (1U)
14134#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
14135#define SPI_SR_TXE SPI_SR_TXE_Msk
14136#define SPI_SR_CHSIDE_Pos (2U)
14137#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
14138#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
14139#define SPI_SR_UDR_Pos (3U)
14140#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
14141#define SPI_SR_UDR SPI_SR_UDR_Msk
14142#define SPI_SR_CRCERR_Pos (4U)
14143#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
14144#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
14145#define SPI_SR_MODF_Pos (5U)
14146#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
14147#define SPI_SR_MODF SPI_SR_MODF_Msk
14148#define SPI_SR_OVR_Pos (6U)
14149#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
14150#define SPI_SR_OVR SPI_SR_OVR_Msk
14151#define SPI_SR_BSY_Pos (7U)
14152#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
14153#define SPI_SR_BSY SPI_SR_BSY_Msk
14154#define SPI_SR_FRE_Pos (8U)
14155#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
14156#define SPI_SR_FRE SPI_SR_FRE_Msk
14157#define SPI_SR_FRLVL_Pos (9U)
14158#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
14159#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
14160#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
14161#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
14162#define SPI_SR_FTLVL_Pos (11U)
14163#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
14164#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
14165#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
14166#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
14168/******************** Bit definition for SPI_DR register ********************/
14169#define SPI_DR_DR_Pos (0U)
14170#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
14171#define SPI_DR_DR SPI_DR_DR_Msk
14173/******************* Bit definition for SPI_CRCPR register ******************/
14174#define SPI_CRCPR_CRCPOLY_Pos (0U)
14175#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
14176#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
14178/****************** Bit definition for SPI_RXCRCR register ******************/
14179#define SPI_RXCRCR_RXCRC_Pos (0U)
14180#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
14181#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
14183/****************** Bit definition for SPI_TXCRCR register ******************/
14184#define SPI_TXCRCR_TXCRC_Pos (0U)
14185#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
14186#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
14188/****************** Bit definition for SPI_I2SCFGR register *****************/
14189#define SPI_I2SCFGR_CHLEN_Pos (0U)
14190#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
14191#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
14192#define SPI_I2SCFGR_DATLEN_Pos (1U)
14193#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
14194#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
14195#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
14196#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
14197#define SPI_I2SCFGR_CKPOL_Pos (3U)
14198#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
14199#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
14200#define SPI_I2SCFGR_I2SSTD_Pos (4U)
14201#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
14202#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
14203#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
14204#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
14205#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
14206#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
14207#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
14208#define SPI_I2SCFGR_I2SCFG_Pos (8U)
14209#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
14210#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
14211#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
14212#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
14213#define SPI_I2SCFGR_I2SE_Pos (10U)
14214#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
14215#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
14216#define SPI_I2SCFGR_I2SMOD_Pos (11U)
14217#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
14218#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
14219#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
14220#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
14221#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
14223/****************** Bit definition for SPI_I2SPR register *******************/
14224#define SPI_I2SPR_I2SDIV_Pos (0U)
14225#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
14226#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
14227#define SPI_I2SPR_ODD_Pos (8U)
14228#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
14229#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
14230#define SPI_I2SPR_MCKOE_Pos (9U)
14231#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
14232#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
14235/******************************************************************************/
14236/* */
14237/* SYSCFG */
14238/* */
14239/******************************************************************************/
14240/****************** Bit definition for SYSCFG_MEMRMP register ***************/
14241#define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U)
14242#define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1UL << SYSCFG_MEMRMP_MEM_BOOT_Pos)
14243#define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk
14245#define SYSCFG_MEMRMP_SWP_FB_Pos (8U)
14246#define SYSCFG_MEMRMP_SWP_FB_Msk (0x1UL << SYSCFG_MEMRMP_SWP_FB_Pos)
14247#define SYSCFG_MEMRMP_SWP_FB SYSCFG_MEMRMP_SWP_FB_Msk
14249#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
14250#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
14251#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk
14252#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
14253#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
14255/****************** Bit definition for SYSCFG_PMC register ******************/
14256#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
14257#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos)
14258#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk
14259#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
14260#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos)
14261#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk
14262#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
14263#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos)
14264#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk
14265#define SYSCFG_PMC_I2C4_FMP_Pos (3U)
14266#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos)
14267#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk
14268#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
14269#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos)
14270#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk
14271#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
14272#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos)
14273#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk
14274#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
14275#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos)
14276#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk
14277#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
14278#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos)
14279#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk
14281#define SYSCFG_PMC_ADCxDC2_Pos (16U)
14282#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)
14283#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk
14284#define SYSCFG_PMC_ADC1DC2_Pos (16U)
14285#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
14286#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
14287#define SYSCFG_PMC_ADC2DC2_Pos (17U)
14288#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)
14289#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk
14290#define SYSCFG_PMC_ADC3DC2_Pos (18U)
14291#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)
14292#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk
14294#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
14295#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
14296#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
14298/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
14299#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
14300#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
14301#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
14302#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
14303#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
14304#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
14305#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
14306#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
14307#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
14308#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
14309#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
14310#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
14314#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
14315#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
14316#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
14317#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
14318#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
14319#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
14320#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
14321#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
14322#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
14323#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
14324#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
14329#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
14330#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
14331#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
14332#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
14333#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
14334#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
14335#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
14336#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
14337#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
14338#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
14339#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
14344#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
14345#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
14346#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
14347#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
14348#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
14349#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
14350#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
14351#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
14352#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
14353#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
14354#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
14359#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
14360#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
14361#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
14362#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
14363#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
14364#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
14365#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
14366#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
14367#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
14368#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
14369#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
14371/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
14372#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
14373#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
14374#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
14375#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
14376#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
14377#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
14378#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
14379#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
14380#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
14381#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
14382#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
14383#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
14387#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
14388#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
14389#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
14390#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
14391#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
14392#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
14393#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
14394#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
14395#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
14396#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
14397#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
14402#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
14403#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
14404#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
14405#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
14406#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
14407#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
14408#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
14409#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
14410#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
14411#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
14412#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
14417#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
14418#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
14419#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
14420#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
14421#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
14422#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
14423#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
14424#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
14425#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
14426#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
14427#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
14432#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
14433#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
14434#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
14435#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
14436#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
14437#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
14438#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
14439#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
14440#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
14441#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
14442#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
14444/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
14445#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
14446#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
14447#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
14448#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
14449#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
14450#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
14451#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
14452#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
14453#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
14454#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
14455#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
14456#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
14461#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
14462#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
14463#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
14464#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
14465#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
14466#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
14467#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
14468#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
14469#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
14470#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
14475#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
14476#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
14477#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
14478#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
14479#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
14480#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
14481#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
14482#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
14483#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
14484#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
14489#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
14490#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
14491#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
14492#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
14493#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
14494#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
14495#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
14496#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
14497#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
14498#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
14503#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
14504#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
14505#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
14506#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
14507#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
14508#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
14509#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
14510#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
14511#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
14512#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
14515/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
14516#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
14517#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
14518#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
14519#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
14520#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
14521#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
14522#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
14523#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
14524#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
14525#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
14526#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
14527#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
14531#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
14532#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
14533#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
14534#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
14535#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
14536#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
14537#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
14538#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
14539#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
14540#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
14545#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
14546#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
14547#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
14548#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
14549#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
14550#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
14551#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
14552#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
14553#define SYSCFG_EXTICR4_EXTI13_PI 0x0080U
14554#define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U
14559#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
14560#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
14561#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
14562#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
14563#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
14564#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
14565#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
14566#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
14567#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
14568#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
14573#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
14574#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
14575#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
14576#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
14577#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
14578#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
14579#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
14580#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
14581#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
14582#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
14584/****************** Bit definition for SYSCFG_CBR register ******************/
14585#define SYSCFG_CBR_CLL_Pos (0U)
14586#define SYSCFG_CBR_CLL_Msk (0x1UL << SYSCFG_CBR_CLL_Pos)
14587#define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk
14588#define SYSCFG_CBR_PVDL_Pos (2U)
14589#define SYSCFG_CBR_PVDL_Msk (0x1UL << SYSCFG_CBR_PVDL_Pos)
14590#define SYSCFG_CBR_PVDL SYSCFG_CBR_PVDL_Msk
14592/****************** Bit definition for SYSCFG_CMPCR register ****************/
14593#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
14594#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
14595#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
14596#define SYSCFG_CMPCR_READY_Pos (8U)
14597#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
14598#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
14600/******************************************************************************/
14601/* */
14602/* TIM */
14603/* */
14604/******************************************************************************/
14605/*
14606 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
14607 */
14608#define TIM_BREAK_INPUT_SUPPORT
14609/******************* Bit definition for TIM_CR1 register ********************/
14610#define TIM_CR1_CEN_Pos (0U)
14611#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
14612#define TIM_CR1_CEN TIM_CR1_CEN_Msk
14613#define TIM_CR1_UDIS_Pos (1U)
14614#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
14615#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
14616#define TIM_CR1_URS_Pos (2U)
14617#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
14618#define TIM_CR1_URS TIM_CR1_URS_Msk
14619#define TIM_CR1_OPM_Pos (3U)
14620#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
14621#define TIM_CR1_OPM TIM_CR1_OPM_Msk
14622#define TIM_CR1_DIR_Pos (4U)
14623#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
14624#define TIM_CR1_DIR TIM_CR1_DIR_Msk
14626#define TIM_CR1_CMS_Pos (5U)
14627#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
14628#define TIM_CR1_CMS TIM_CR1_CMS_Msk
14629#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
14630#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
14632#define TIM_CR1_ARPE_Pos (7U)
14633#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
14634#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
14636#define TIM_CR1_CKD_Pos (8U)
14637#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
14638#define TIM_CR1_CKD TIM_CR1_CKD_Msk
14639#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
14640#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
14641#define TIM_CR1_UIFREMAP_Pos (11U)
14642#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
14643#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
14645/******************* Bit definition for TIM_CR2 register ********************/
14646#define TIM_CR2_CCPC_Pos (0U)
14647#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
14648#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
14649#define TIM_CR2_CCUS_Pos (2U)
14650#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
14651#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
14652#define TIM_CR2_CCDS_Pos (3U)
14653#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
14654#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
14656#define TIM_CR2_OIS5_Pos (16U)
14657#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
14658#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
14659#define TIM_CR2_OIS6_Pos (18U)
14660#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
14661#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
14663#define TIM_CR2_MMS_Pos (4U)
14664#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
14665#define TIM_CR2_MMS TIM_CR2_MMS_Msk
14666#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
14667#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
14668#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
14670#define TIM_CR2_MMS2_Pos (20U)
14671#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
14672#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
14673#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
14674#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
14675#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
14676#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
14678#define TIM_CR2_TI1S_Pos (7U)
14679#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
14680#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
14681#define TIM_CR2_OIS1_Pos (8U)
14682#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
14683#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
14684#define TIM_CR2_OIS1N_Pos (9U)
14685#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
14686#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
14687#define TIM_CR2_OIS2_Pos (10U)
14688#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
14689#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
14690#define TIM_CR2_OIS2N_Pos (11U)
14691#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
14692#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
14693#define TIM_CR2_OIS3_Pos (12U)
14694#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
14695#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
14696#define TIM_CR2_OIS3N_Pos (13U)
14697#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
14698#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
14699#define TIM_CR2_OIS4_Pos (14U)
14700#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
14701#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
14703/******************* Bit definition for TIM_SMCR register *******************/
14704#define TIM_SMCR_SMS_Pos (0U)
14705#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
14706#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
14707#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
14708#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
14709#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
14710#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
14712#define TIM_SMCR_TS_Pos (4U)
14713#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
14714#define TIM_SMCR_TS TIM_SMCR_TS_Msk
14715#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
14716#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
14717#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
14719#define TIM_SMCR_MSM_Pos (7U)
14720#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
14721#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
14723#define TIM_SMCR_ETF_Pos (8U)
14724#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
14725#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
14726#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
14727#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
14728#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
14729#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
14731#define TIM_SMCR_ETPS_Pos (12U)
14732#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
14733#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
14734#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
14735#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
14737#define TIM_SMCR_ECE_Pos (14U)
14738#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
14739#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
14740#define TIM_SMCR_ETP_Pos (15U)
14741#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
14742#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
14744/******************* Bit definition for TIM_DIER register *******************/
14745#define TIM_DIER_UIE_Pos (0U)
14746#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
14747#define TIM_DIER_UIE TIM_DIER_UIE_Msk
14748#define TIM_DIER_CC1IE_Pos (1U)
14749#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
14750#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
14751#define TIM_DIER_CC2IE_Pos (2U)
14752#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
14753#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
14754#define TIM_DIER_CC3IE_Pos (3U)
14755#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
14756#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
14757#define TIM_DIER_CC4IE_Pos (4U)
14758#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
14759#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
14760#define TIM_DIER_COMIE_Pos (5U)
14761#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
14762#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
14763#define TIM_DIER_TIE_Pos (6U)
14764#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
14765#define TIM_DIER_TIE TIM_DIER_TIE_Msk
14766#define TIM_DIER_BIE_Pos (7U)
14767#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
14768#define TIM_DIER_BIE TIM_DIER_BIE_Msk
14769#define TIM_DIER_UDE_Pos (8U)
14770#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
14771#define TIM_DIER_UDE TIM_DIER_UDE_Msk
14772#define TIM_DIER_CC1DE_Pos (9U)
14773#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
14774#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
14775#define TIM_DIER_CC2DE_Pos (10U)
14776#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
14777#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
14778#define TIM_DIER_CC3DE_Pos (11U)
14779#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
14780#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
14781#define TIM_DIER_CC4DE_Pos (12U)
14782#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
14783#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
14784#define TIM_DIER_COMDE_Pos (13U)
14785#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
14786#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
14787#define TIM_DIER_TDE_Pos (14U)
14788#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
14789#define TIM_DIER_TDE TIM_DIER_TDE_Msk
14791/******************** Bit definition for TIM_SR register ********************/
14792#define TIM_SR_UIF_Pos (0U)
14793#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
14794#define TIM_SR_UIF TIM_SR_UIF_Msk
14795#define TIM_SR_CC1IF_Pos (1U)
14796#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
14797#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
14798#define TIM_SR_CC2IF_Pos (2U)
14799#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
14800#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
14801#define TIM_SR_CC3IF_Pos (3U)
14802#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
14803#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
14804#define TIM_SR_CC4IF_Pos (4U)
14805#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
14806#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
14807#define TIM_SR_COMIF_Pos (5U)
14808#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
14809#define TIM_SR_COMIF TIM_SR_COMIF_Msk
14810#define TIM_SR_TIF_Pos (6U)
14811#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
14812#define TIM_SR_TIF TIM_SR_TIF_Msk
14813#define TIM_SR_BIF_Pos (7U)
14814#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
14815#define TIM_SR_BIF TIM_SR_BIF_Msk
14816#define TIM_SR_B2IF_Pos (8U)
14817#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
14818#define TIM_SR_B2IF TIM_SR_B2IF_Msk
14819#define TIM_SR_CC1OF_Pos (9U)
14820#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
14821#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
14822#define TIM_SR_CC2OF_Pos (10U)
14823#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
14824#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
14825#define TIM_SR_CC3OF_Pos (11U)
14826#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
14827#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
14828#define TIM_SR_CC4OF_Pos (12U)
14829#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
14830#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
14831#define TIM_SR_SBIF_Pos (13U)
14832#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
14833#define TIM_SR_SBIF TIM_SR_SBIF_Msk
14834#define TIM_SR_CC5IF_Pos (16U)
14835#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
14836#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
14837#define TIM_SR_CC6IF_Pos (17U)
14838#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
14839#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
14841/******************* Bit definition for TIM_EGR register ********************/
14842#define TIM_EGR_UG_Pos (0U)
14843#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
14844#define TIM_EGR_UG TIM_EGR_UG_Msk
14845#define TIM_EGR_CC1G_Pos (1U)
14846#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
14847#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
14848#define TIM_EGR_CC2G_Pos (2U)
14849#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
14850#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
14851#define TIM_EGR_CC3G_Pos (3U)
14852#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
14853#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
14854#define TIM_EGR_CC4G_Pos (4U)
14855#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
14856#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
14857#define TIM_EGR_COMG_Pos (5U)
14858#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
14859#define TIM_EGR_COMG TIM_EGR_COMG_Msk
14860#define TIM_EGR_TG_Pos (6U)
14861#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
14862#define TIM_EGR_TG TIM_EGR_TG_Msk
14863#define TIM_EGR_BG_Pos (7U)
14864#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
14865#define TIM_EGR_BG TIM_EGR_BG_Msk
14866#define TIM_EGR_B2G_Pos (8U)
14867#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
14868#define TIM_EGR_B2G TIM_EGR_B2G_Msk
14870/****************** Bit definition for TIM_CCMR1 register *******************/
14871#define TIM_CCMR1_CC1S_Pos (0U)
14872#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
14873#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
14874#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
14875#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
14877#define TIM_CCMR1_OC1FE_Pos (2U)
14878#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
14879#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
14880#define TIM_CCMR1_OC1PE_Pos (3U)
14881#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
14882#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
14884#define TIM_CCMR1_OC1M_Pos (4U)
14885#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
14886#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
14887#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
14888#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
14889#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
14890#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
14892#define TIM_CCMR1_OC1CE_Pos (7U)
14893#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
14894#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
14896#define TIM_CCMR1_CC2S_Pos (8U)
14897#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
14898#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
14899#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
14900#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
14902#define TIM_CCMR1_OC2FE_Pos (10U)
14903#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
14904#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
14905#define TIM_CCMR1_OC2PE_Pos (11U)
14906#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
14907#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
14909#define TIM_CCMR1_OC2M_Pos (12U)
14910#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
14911#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
14912#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
14913#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
14914#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
14915#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
14917#define TIM_CCMR1_OC2CE_Pos (15U)
14918#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
14919#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
14921/*----------------------------------------------------------------------------*/
14922
14923#define TIM_CCMR1_IC1PSC_Pos (2U)
14924#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
14925#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
14926#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
14927#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
14929#define TIM_CCMR1_IC1F_Pos (4U)
14930#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
14931#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
14932#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
14933#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
14934#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
14935#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
14937#define TIM_CCMR1_IC2PSC_Pos (10U)
14938#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
14939#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
14940#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
14941#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
14943#define TIM_CCMR1_IC2F_Pos (12U)
14944#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
14945#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
14946#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
14947#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
14948#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
14949#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
14951/****************** Bit definition for TIM_CCMR2 register *******************/
14952#define TIM_CCMR2_CC3S_Pos (0U)
14953#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
14954#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
14955#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
14956#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
14958#define TIM_CCMR2_OC3FE_Pos (2U)
14959#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
14960#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
14961#define TIM_CCMR2_OC3PE_Pos (3U)
14962#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
14963#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
14965#define TIM_CCMR2_OC3M_Pos (4U)
14966#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
14967#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
14968#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)
14969#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)
14970#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)
14971#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
14975#define TIM_CCMR2_OC3CE_Pos (7U)
14976#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
14977#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
14979#define TIM_CCMR2_CC4S_Pos (8U)
14980#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
14981#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
14982#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
14983#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
14985#define TIM_CCMR2_OC4FE_Pos (10U)
14986#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
14987#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
14988#define TIM_CCMR2_OC4PE_Pos (11U)
14989#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
14990#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
14992#define TIM_CCMR2_OC4M_Pos (12U)
14993#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
14994#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
14995#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)
14996#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)
14997#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)
14998#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
15000#define TIM_CCMR2_OC4CE_Pos (15U)
15001#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
15002#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
15004/*----------------------------------------------------------------------------*/
15005
15006#define TIM_CCMR2_IC3PSC_Pos (2U)
15007#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
15008#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
15009#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
15010#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
15012#define TIM_CCMR2_IC3F_Pos (4U)
15013#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
15014#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
15015#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
15016#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
15017#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
15018#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
15020#define TIM_CCMR2_IC4PSC_Pos (10U)
15021#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
15022#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
15023#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
15024#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
15026#define TIM_CCMR2_IC4F_Pos (12U)
15027#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
15028#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
15029#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
15030#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
15031#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
15032#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
15034/******************* Bit definition for TIM_CCER register *******************/
15035#define TIM_CCER_CC1E_Pos (0U)
15036#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
15037#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
15038#define TIM_CCER_CC1P_Pos (1U)
15039#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
15040#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
15041#define TIM_CCER_CC1NE_Pos (2U)
15042#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
15043#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
15044#define TIM_CCER_CC1NP_Pos (3U)
15045#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
15046#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
15047#define TIM_CCER_CC2E_Pos (4U)
15048#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
15049#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
15050#define TIM_CCER_CC2P_Pos (5U)
15051#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
15052#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
15053#define TIM_CCER_CC2NE_Pos (6U)
15054#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
15055#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
15056#define TIM_CCER_CC2NP_Pos (7U)
15057#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
15058#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
15059#define TIM_CCER_CC3E_Pos (8U)
15060#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
15061#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
15062#define TIM_CCER_CC3P_Pos (9U)
15063#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
15064#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
15065#define TIM_CCER_CC3NE_Pos (10U)
15066#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
15067#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
15068#define TIM_CCER_CC3NP_Pos (11U)
15069#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
15070#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
15071#define TIM_CCER_CC4E_Pos (12U)
15072#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
15073#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
15074#define TIM_CCER_CC4P_Pos (13U)
15075#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
15076#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
15077#define TIM_CCER_CC4NP_Pos (15U)
15078#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
15079#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
15080#define TIM_CCER_CC5E_Pos (16U)
15081#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
15082#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
15083#define TIM_CCER_CC5P_Pos (17U)
15084#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
15085#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
15086#define TIM_CCER_CC6E_Pos (20U)
15087#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
15088#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
15089#define TIM_CCER_CC6P_Pos (21U)
15090#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
15091#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
15094/******************* Bit definition for TIM_CNT register ********************/
15095#define TIM_CNT_CNT_Pos (0U)
15096#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
15097#define TIM_CNT_CNT TIM_CNT_CNT_Msk
15098#define TIM_CNT_UIFCPY_Pos (31U)
15099#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
15100#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
15102/******************* Bit definition for TIM_PSC register ********************/
15103#define TIM_PSC_PSC_Pos (0U)
15104#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
15105#define TIM_PSC_PSC TIM_PSC_PSC_Msk
15107/******************* Bit definition for TIM_ARR register ********************/
15108#define TIM_ARR_ARR_Pos (0U)
15109#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
15110#define TIM_ARR_ARR TIM_ARR_ARR_Msk
15112/******************* Bit definition for TIM_RCR register ********************/
15113#define TIM_RCR_REP_Pos (0U)
15114#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)
15115#define TIM_RCR_REP TIM_RCR_REP_Msk
15117/******************* Bit definition for TIM_CCR1 register *******************/
15118#define TIM_CCR1_CCR1_Pos (0U)
15119#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
15120#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
15122/******************* Bit definition for TIM_CCR2 register *******************/
15123#define TIM_CCR2_CCR2_Pos (0U)
15124#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
15125#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
15127/******************* Bit definition for TIM_CCR3 register *******************/
15128#define TIM_CCR3_CCR3_Pos (0U)
15129#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
15130#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
15132/******************* Bit definition for TIM_CCR4 register *******************/
15133#define TIM_CCR4_CCR4_Pos (0U)
15134#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
15135#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
15137/******************* Bit definition for TIM_BDTR register *******************/
15138#define TIM_BDTR_DTG_Pos (0U)
15139#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
15140#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
15141#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
15142#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
15143#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
15144#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
15145#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
15146#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
15147#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
15148#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
15150#define TIM_BDTR_LOCK_Pos (8U)
15151#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
15152#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
15153#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
15154#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
15156#define TIM_BDTR_OSSI_Pos (10U)
15157#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
15158#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
15159#define TIM_BDTR_OSSR_Pos (11U)
15160#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
15161#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
15162#define TIM_BDTR_BKE_Pos (12U)
15163#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
15164#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
15165#define TIM_BDTR_BKP_Pos (13U)
15166#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
15167#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
15168#define TIM_BDTR_AOE_Pos (14U)
15169#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
15170#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
15171#define TIM_BDTR_MOE_Pos (15U)
15172#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
15173#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
15174#define TIM_BDTR_BKF_Pos (16U)
15175#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
15176#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
15177#define TIM_BDTR_BK2F_Pos (20U)
15178#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
15179#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
15180#define TIM_BDTR_BK2E_Pos (24U)
15181#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
15182#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
15183#define TIM_BDTR_BK2P_Pos (25U)
15184#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
15185#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
15187/******************* Bit definition for TIM_DCR register ********************/
15188#define TIM_DCR_DBA_Pos (0U)
15189#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
15190#define TIM_DCR_DBA TIM_DCR_DBA_Msk
15191#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
15192#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
15193#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
15194#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
15195#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
15197#define TIM_DCR_DBL_Pos (8U)
15198#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
15199#define TIM_DCR_DBL TIM_DCR_DBL_Msk
15200#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
15201#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
15202#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
15203#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
15204#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
15206/******************* Bit definition for TIM_DMAR register *******************/
15207#define TIM_DMAR_DMAB_Pos (0U)
15208#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
15209#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
15211/******************* Bit definition for TIM_OR regiter *********************/
15212#define TIM_OR_TI4_RMP_Pos (6U)
15213#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
15214#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
15215#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
15216#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
15217#define TIM_OR_ITR1_RMP_Pos (10U)
15218#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
15219#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
15220#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
15221#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
15223/******************* Bit definition for TIM2_OR register *******************/
15224#define TIM2_OR_ITR1_RMP_Pos (10U)
15225#define TIM2_OR_ITR1_RMP_Msk (0x3UL << TIM2_OR_ITR1_RMP_Pos)
15226#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk
15227#define TIM2_OR_ITR1_RMP_0 (0x1UL << TIM2_OR_ITR1_RMP_Pos)
15228#define TIM2_OR_ITR1_RMP_1 (0x2UL << TIM2_OR_ITR1_RMP_Pos)
15230/******************* Bit definition for TIM5_OR register *******************/
15231#define TIM5_OR_TI4_RMP_Pos (6U)
15232#define TIM5_OR_TI4_RMP_Msk (0x3UL << TIM5_OR_TI4_RMP_Pos)
15233#define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk
15234#define TIM5_OR_TI4_RMP_0 (0x1UL << TIM5_OR_TI4_RMP_Pos)
15235#define TIM5_OR_TI4_RMP_1 (0x2UL << TIM5_OR_TI4_RMP_Pos)
15237/******************* Bit definition for TIM11_OR register *******************/
15238#define TIM11_OR_TI1_RMP_Pos (0U)
15239#define TIM11_OR_TI1_RMP_Msk (0x3UL << TIM11_OR_TI1_RMP_Pos)
15240#define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk
15241#define TIM11_OR_TI1_RMP_0 (0x1UL << TIM11_OR_TI1_RMP_Pos)
15242#define TIM11_OR_TI1_RMP_1 (0x2UL << TIM11_OR_TI1_RMP_Pos)
15244/****************** Bit definition for TIM_CCMR3 register *******************/
15245#define TIM_CCMR3_OC5FE_Pos (2U)
15246#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
15247#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
15248#define TIM_CCMR3_OC5PE_Pos (3U)
15249#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
15250#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
15252#define TIM_CCMR3_OC5M_Pos (4U)
15253#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
15254#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
15255#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)
15256#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)
15257#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)
15258#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
15260#define TIM_CCMR3_OC5CE_Pos (7U)
15261#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
15262#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
15264#define TIM_CCMR3_OC6FE_Pos (10U)
15265#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
15266#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
15267#define TIM_CCMR3_OC6PE_Pos (11U)
15268#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
15269#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
15271#define TIM_CCMR3_OC6M_Pos (12U)
15272#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
15273#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
15274#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)
15275#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)
15276#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)
15277#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
15279#define TIM_CCMR3_OC6CE_Pos (15U)
15280#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
15281#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
15283/******************* Bit definition for TIM_CCR5 register *******************/
15284#define TIM_CCR5_CCR5_Pos (0U)
15285#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
15286#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
15287#define TIM_CCR5_GC5C1_Pos (29U)
15288#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
15289#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
15290#define TIM_CCR5_GC5C2_Pos (30U)
15291#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
15292#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
15293#define TIM_CCR5_GC5C3_Pos (31U)
15294#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
15295#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
15297/******************* Bit definition for TIM_CCR6 register *******************/
15298#define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU)
15300/******************* Bit definition for TIM1_AF1 register *******************/
15301#define TIM1_AF1_BKINE_Pos (0U)
15302#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)
15303#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk
15304#define TIM1_AF1_BKDF1BKE_Pos (8U)
15305#define TIM1_AF1_BKDF1BKE_Msk (0x1UL << TIM1_AF1_BKDF1BKE_Pos)
15306#define TIM1_AF1_BKDF1BKE TIM1_AF1_BKDF1BKE_Msk
15307#define TIM1_AF1_BKINP_Pos (9U)
15308#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)
15309#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk
15311/******************* Bit definition for TIM1_AF2 register *******************/
15312#define TIM1_AF2_BK2INE_Pos (0U)
15313#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)
15314#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk
15315#define TIM1_AF2_BK2DF1BKE_Pos (8U)
15316#define TIM1_AF2_BK2DF1BKE_Msk (0x1UL << TIM1_AF2_BK2DF1BKE_Pos)
15317#define TIM1_AF2_BK2DF1BKE TIM1_AF2_BK2DF1BKE_Msk
15318#define TIM1_AF2_BK2INP_Pos (9U)
15319#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)
15320#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk
15322/******************* Bit definition for TIM8_AF1 register *******************/
15323#define TIM8_AF1_BKINE_Pos (0U)
15324#define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos)
15325#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk
15326#define TIM8_AF1_BKDF1BKE_Pos (8U)
15327#define TIM8_AF1_BKDF1BKE_Msk (0x1UL << TIM8_AF1_BKDF1BKE_Pos)
15328#define TIM8_AF1_BKDF1BKE TIM8_AF1_BKDF1BKE_Msk
15329#define TIM8_AF1_BKINP_Pos (9U)
15330#define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos)
15331#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk
15333/******************* Bit definition for TIM8_AF2 register *******************/
15334#define TIM8_AF2_BK2INE_Pos (0U)
15335#define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos)
15336#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk
15337#define TIM8_AF2_BK2DF1BKE_Pos (8U)
15338#define TIM8_AF2_BK2DF1BKE_Msk (0x1UL << TIM8_AF2_BK2DF1BKE_Pos)
15339#define TIM8_AF2_BK2DF1BKE TIM8_AF2_BK2DF1BKE_Msk
15340#define TIM8_AF2_BK2INP_Pos (9U)
15341#define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos)
15342#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk
15345/******************************************************************************/
15346/* */
15347/* Low Power Timer (LPTIM) */
15348/* */
15349/******************************************************************************/
15350/****************** Bit definition for LPTIM_ISR register *******************/
15351#define LPTIM_ISR_CMPM_Pos (0U)
15352#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
15353#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
15354#define LPTIM_ISR_ARRM_Pos (1U)
15355#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
15356#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
15357#define LPTIM_ISR_EXTTRIG_Pos (2U)
15358#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
15359#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
15360#define LPTIM_ISR_CMPOK_Pos (3U)
15361#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
15362#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
15363#define LPTIM_ISR_ARROK_Pos (4U)
15364#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
15365#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
15366#define LPTIM_ISR_UP_Pos (5U)
15367#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
15368#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
15369#define LPTIM_ISR_DOWN_Pos (6U)
15370#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
15371#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
15373/****************** Bit definition for LPTIM_ICR register *******************/
15374#define LPTIM_ICR_CMPMCF_Pos (0U)
15375#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
15376#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
15377#define LPTIM_ICR_ARRMCF_Pos (1U)
15378#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
15379#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
15380#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
15381#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
15382#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
15383#define LPTIM_ICR_CMPOKCF_Pos (3U)
15384#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
15385#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
15386#define LPTIM_ICR_ARROKCF_Pos (4U)
15387#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
15388#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
15389#define LPTIM_ICR_UPCF_Pos (5U)
15390#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
15391#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
15392#define LPTIM_ICR_DOWNCF_Pos (6U)
15393#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
15394#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
15396/****************** Bit definition for LPTIM_IER register *******************/
15397#define LPTIM_IER_CMPMIE_Pos (0U)
15398#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
15399#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
15400#define LPTIM_IER_ARRMIE_Pos (1U)
15401#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
15402#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
15403#define LPTIM_IER_EXTTRIGIE_Pos (2U)
15404#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
15405#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
15406#define LPTIM_IER_CMPOKIE_Pos (3U)
15407#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
15408#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
15409#define LPTIM_IER_ARROKIE_Pos (4U)
15410#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
15411#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
15412#define LPTIM_IER_UPIE_Pos (5U)
15413#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
15414#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
15415#define LPTIM_IER_DOWNIE_Pos (6U)
15416#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
15417#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
15419/****************** Bit definition for LPTIM_CFGR register*******************/
15420#define LPTIM_CFGR_CKSEL_Pos (0U)
15421#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
15422#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
15424#define LPTIM_CFGR_CKPOL_Pos (1U)
15425#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
15426#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
15427#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
15428#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
15430#define LPTIM_CFGR_CKFLT_Pos (3U)
15431#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
15432#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
15433#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
15434#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
15436#define LPTIM_CFGR_TRGFLT_Pos (6U)
15437#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
15438#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
15439#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
15440#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
15442#define LPTIM_CFGR_PRESC_Pos (9U)
15443#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
15444#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
15445#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
15446#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
15447#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
15449#define LPTIM_CFGR_TRIGSEL_Pos (13U)
15450#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
15451#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
15452#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
15453#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
15454#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
15456#define LPTIM_CFGR_TRIGEN_Pos (17U)
15457#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
15458#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
15459#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
15460#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
15462#define LPTIM_CFGR_TIMOUT_Pos (19U)
15463#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
15464#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
15465#define LPTIM_CFGR_WAVE_Pos (20U)
15466#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
15467#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
15468#define LPTIM_CFGR_WAVPOL_Pos (21U)
15469#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
15470#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
15471#define LPTIM_CFGR_PRELOAD_Pos (22U)
15472#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
15473#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
15474#define LPTIM_CFGR_COUNTMODE_Pos (23U)
15475#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
15476#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
15477#define LPTIM_CFGR_ENC_Pos (24U)
15478#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
15479#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
15481/****************** Bit definition for LPTIM_CR register ********************/
15482#define LPTIM_CR_ENABLE_Pos (0U)
15483#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
15484#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
15485#define LPTIM_CR_SNGSTRT_Pos (1U)
15486#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
15487#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
15488#define LPTIM_CR_CNTSTRT_Pos (2U)
15489#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
15490#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
15492/****************** Bit definition for LPTIM_CMP register *******************/
15493#define LPTIM_CMP_CMP_Pos (0U)
15494#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
15495#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
15497/****************** Bit definition for LPTIM_ARR register *******************/
15498#define LPTIM_ARR_ARR_Pos (0U)
15499#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
15500#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
15502/****************** Bit definition for LPTIM_CNT register *******************/
15503#define LPTIM_CNT_CNT_Pos (0U)
15504#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
15505#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
15506/******************************************************************************/
15507/* */
15508/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
15509/* */
15510/******************************************************************************/
15511/****************** Bit definition for USART_CR1 register *******************/
15512#define USART_CR1_UE_Pos (0U)
15513#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
15514#define USART_CR1_UE USART_CR1_UE_Msk
15515#define USART_CR1_UESM_Pos (1U)
15516#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
15517#define USART_CR1_UESM USART_CR1_UESM_Msk
15518#define USART_CR1_RE_Pos (2U)
15519#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
15520#define USART_CR1_RE USART_CR1_RE_Msk
15521#define USART_CR1_TE_Pos (3U)
15522#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
15523#define USART_CR1_TE USART_CR1_TE_Msk
15524#define USART_CR1_IDLEIE_Pos (4U)
15525#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
15526#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
15527#define USART_CR1_RXNEIE_Pos (5U)
15528#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
15529#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
15530#define USART_CR1_TCIE_Pos (6U)
15531#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
15532#define USART_CR1_TCIE USART_CR1_TCIE_Msk
15533#define USART_CR1_TXEIE_Pos (7U)
15534#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
15535#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
15536#define USART_CR1_PEIE_Pos (8U)
15537#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
15538#define USART_CR1_PEIE USART_CR1_PEIE_Msk
15539#define USART_CR1_PS_Pos (9U)
15540#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
15541#define USART_CR1_PS USART_CR1_PS_Msk
15542#define USART_CR1_PCE_Pos (10U)
15543#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
15544#define USART_CR1_PCE USART_CR1_PCE_Msk
15545#define USART_CR1_WAKE_Pos (11U)
15546#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
15547#define USART_CR1_WAKE USART_CR1_WAKE_Msk
15548#define USART_CR1_M_Pos (12U)
15549#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
15550#define USART_CR1_M USART_CR1_M_Msk
15551#define USART_CR1_M0 (0x00001UL << USART_CR1_M_Pos)
15552#define USART_CR1_MME_Pos (13U)
15553#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
15554#define USART_CR1_MME USART_CR1_MME_Msk
15555#define USART_CR1_CMIE_Pos (14U)
15556#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
15557#define USART_CR1_CMIE USART_CR1_CMIE_Msk
15558#define USART_CR1_OVER8_Pos (15U)
15559#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
15560#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
15561#define USART_CR1_DEDT_Pos (16U)
15562#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
15563#define USART_CR1_DEDT USART_CR1_DEDT_Msk
15564#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
15565#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
15566#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
15567#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
15568#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
15569#define USART_CR1_DEAT_Pos (21U)
15570#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
15571#define USART_CR1_DEAT USART_CR1_DEAT_Msk
15572#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
15573#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
15574#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
15575#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
15576#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
15577#define USART_CR1_RTOIE_Pos (26U)
15578#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
15579#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
15580#define USART_CR1_EOBIE_Pos (27U)
15581#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
15582#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
15583#define USART_CR1_M1 0x10000000U
15585/* Legacy defines */
15586#define USART_CR1_M_0 USART_CR1_M0
15587#define USART_CR1_M_1 USART_CR1_M1
15589/****************** Bit definition for USART_CR2 register *******************/
15590#define USART_CR2_ADDM7_Pos (4U)
15591#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
15592#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
15593#define USART_CR2_LBDL_Pos (5U)
15594#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
15595#define USART_CR2_LBDL USART_CR2_LBDL_Msk
15596#define USART_CR2_LBDIE_Pos (6U)
15597#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
15598#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
15599#define USART_CR2_LBCL_Pos (8U)
15600#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
15601#define USART_CR2_LBCL USART_CR2_LBCL_Msk
15602#define USART_CR2_CPHA_Pos (9U)
15603#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
15604#define USART_CR2_CPHA USART_CR2_CPHA_Msk
15605#define USART_CR2_CPOL_Pos (10U)
15606#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
15607#define USART_CR2_CPOL USART_CR2_CPOL_Msk
15608#define USART_CR2_CLKEN_Pos (11U)
15609#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
15610#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
15611#define USART_CR2_STOP_Pos (12U)
15612#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
15613#define USART_CR2_STOP USART_CR2_STOP_Msk
15614#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
15615#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
15616#define USART_CR2_LINEN_Pos (14U)
15617#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
15618#define USART_CR2_LINEN USART_CR2_LINEN_Msk
15619#define USART_CR2_SWAP_Pos (15U)
15620#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
15621#define USART_CR2_SWAP USART_CR2_SWAP_Msk
15622#define USART_CR2_RXINV_Pos (16U)
15623#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
15624#define USART_CR2_RXINV USART_CR2_RXINV_Msk
15625#define USART_CR2_TXINV_Pos (17U)
15626#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
15627#define USART_CR2_TXINV USART_CR2_TXINV_Msk
15628#define USART_CR2_DATAINV_Pos (18U)
15629#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
15630#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
15631#define USART_CR2_MSBFIRST_Pos (19U)
15632#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
15633#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
15634#define USART_CR2_ABREN_Pos (20U)
15635#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
15636#define USART_CR2_ABREN USART_CR2_ABREN_Msk
15637#define USART_CR2_ABRMODE_Pos (21U)
15638#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
15639#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
15640#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
15641#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
15642#define USART_CR2_RTOEN_Pos (23U)
15643#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
15644#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
15645#define USART_CR2_ADD_Pos (24U)
15646#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
15647#define USART_CR2_ADD USART_CR2_ADD_Msk
15649/****************** Bit definition for USART_CR3 register *******************/
15650#define USART_CR3_EIE_Pos (0U)
15651#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
15652#define USART_CR3_EIE USART_CR3_EIE_Msk
15653#define USART_CR3_IREN_Pos (1U)
15654#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
15655#define USART_CR3_IREN USART_CR3_IREN_Msk
15656#define USART_CR3_IRLP_Pos (2U)
15657#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
15658#define USART_CR3_IRLP USART_CR3_IRLP_Msk
15659#define USART_CR3_HDSEL_Pos (3U)
15660#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
15661#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
15662#define USART_CR3_NACK_Pos (4U)
15663#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
15664#define USART_CR3_NACK USART_CR3_NACK_Msk
15665#define USART_CR3_SCEN_Pos (5U)
15666#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
15667#define USART_CR3_SCEN USART_CR3_SCEN_Msk
15668#define USART_CR3_DMAR_Pos (6U)
15669#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
15670#define USART_CR3_DMAR USART_CR3_DMAR_Msk
15671#define USART_CR3_DMAT_Pos (7U)
15672#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
15673#define USART_CR3_DMAT USART_CR3_DMAT_Msk
15674#define USART_CR3_RTSE_Pos (8U)
15675#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
15676#define USART_CR3_RTSE USART_CR3_RTSE_Msk
15677#define USART_CR3_CTSE_Pos (9U)
15678#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
15679#define USART_CR3_CTSE USART_CR3_CTSE_Msk
15680#define USART_CR3_CTSIE_Pos (10U)
15681#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
15682#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
15683#define USART_CR3_ONEBIT_Pos (11U)
15684#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
15685#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
15686#define USART_CR3_OVRDIS_Pos (12U)
15687#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
15688#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
15689#define USART_CR3_DDRE_Pos (13U)
15690#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
15691#define USART_CR3_DDRE USART_CR3_DDRE_Msk
15692#define USART_CR3_DEM_Pos (14U)
15693#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
15694#define USART_CR3_DEM USART_CR3_DEM_Msk
15695#define USART_CR3_DEP_Pos (15U)
15696#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
15697#define USART_CR3_DEP USART_CR3_DEP_Msk
15698#define USART_CR3_SCARCNT_Pos (17U)
15699#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
15700#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
15701#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
15702#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
15703#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
15704#define USART_CR3_WUS_Pos (20U)
15705#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
15706#define USART_CR3_WUS USART_CR3_WUS_Msk
15707#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
15708#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
15709#define USART_CR3_WUFIE_Pos (22U)
15710#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
15711#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
15712#define USART_CR3_UCESM_Pos (23U)
15713#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos)
15714#define USART_CR3_UCESM USART_CR3_UCESM_Msk
15716/****************** Bit definition for USART_BRR register *******************/
15717#define USART_BRR_DIV_FRACTION_Pos (0U)
15718#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
15719#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
15720#define USART_BRR_DIV_MANTISSA_Pos (4U)
15721#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
15722#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
15724/****************** Bit definition for USART_GTPR register ******************/
15725#define USART_GTPR_PSC_Pos (0U)
15726#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
15727#define USART_GTPR_PSC USART_GTPR_PSC_Msk
15728#define USART_GTPR_GT_Pos (8U)
15729#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
15730#define USART_GTPR_GT USART_GTPR_GT_Msk
15733/******************* Bit definition for USART_RTOR register *****************/
15734#define USART_RTOR_RTO_Pos (0U)
15735#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
15736#define USART_RTOR_RTO USART_RTOR_RTO_Msk
15737#define USART_RTOR_BLEN_Pos (24U)
15738#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
15739#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
15741/******************* Bit definition for USART_RQR register ******************/
15742#define USART_RQR_ABRRQ_Pos (0U)
15743#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
15744#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
15745#define USART_RQR_SBKRQ_Pos (1U)
15746#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
15747#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
15748#define USART_RQR_MMRQ_Pos (2U)
15749#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
15750#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
15751#define USART_RQR_RXFRQ_Pos (3U)
15752#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
15753#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
15754#define USART_RQR_TXFRQ_Pos (4U)
15755#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
15756#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
15758/******************* Bit definition for USART_ISR register ******************/
15759#define USART_ISR_PE_Pos (0U)
15760#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
15761#define USART_ISR_PE USART_ISR_PE_Msk
15762#define USART_ISR_FE_Pos (1U)
15763#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
15764#define USART_ISR_FE USART_ISR_FE_Msk
15765#define USART_ISR_NE_Pos (2U)
15766#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
15767#define USART_ISR_NE USART_ISR_NE_Msk
15768#define USART_ISR_ORE_Pos (3U)
15769#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
15770#define USART_ISR_ORE USART_ISR_ORE_Msk
15771#define USART_ISR_IDLE_Pos (4U)
15772#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
15773#define USART_ISR_IDLE USART_ISR_IDLE_Msk
15774#define USART_ISR_RXNE_Pos (5U)
15775#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
15776#define USART_ISR_RXNE USART_ISR_RXNE_Msk
15777#define USART_ISR_TC_Pos (6U)
15778#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
15779#define USART_ISR_TC USART_ISR_TC_Msk
15780#define USART_ISR_TXE_Pos (7U)
15781#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
15782#define USART_ISR_TXE USART_ISR_TXE_Msk
15783#define USART_ISR_LBDF_Pos (8U)
15784#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
15785#define USART_ISR_LBDF USART_ISR_LBDF_Msk
15786#define USART_ISR_CTSIF_Pos (9U)
15787#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
15788#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
15789#define USART_ISR_CTS_Pos (10U)
15790#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
15791#define USART_ISR_CTS USART_ISR_CTS_Msk
15792#define USART_ISR_RTOF_Pos (11U)
15793#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
15794#define USART_ISR_RTOF USART_ISR_RTOF_Msk
15795#define USART_ISR_EOBF_Pos (12U)
15796#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
15797#define USART_ISR_EOBF USART_ISR_EOBF_Msk
15798#define USART_ISR_ABRE_Pos (14U)
15799#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
15800#define USART_ISR_ABRE USART_ISR_ABRE_Msk
15801#define USART_ISR_ABRF_Pos (15U)
15802#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
15803#define USART_ISR_ABRF USART_ISR_ABRF_Msk
15804#define USART_ISR_BUSY_Pos (16U)
15805#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
15806#define USART_ISR_BUSY USART_ISR_BUSY_Msk
15807#define USART_ISR_CMF_Pos (17U)
15808#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
15809#define USART_ISR_CMF USART_ISR_CMF_Msk
15810#define USART_ISR_SBKF_Pos (18U)
15811#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
15812#define USART_ISR_SBKF USART_ISR_SBKF_Msk
15813#define USART_ISR_RWU_Pos (19U)
15814#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
15815#define USART_ISR_RWU USART_ISR_RWU_Msk
15816#define USART_ISR_WUF_Pos (20U)
15817#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
15818#define USART_ISR_WUF USART_ISR_WUF_Msk
15819#define USART_ISR_TEACK_Pos (21U)
15820#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
15821#define USART_ISR_TEACK USART_ISR_TEACK_Msk
15822#define USART_ISR_REACK_Pos (22U)
15823#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
15824#define USART_ISR_REACK USART_ISR_REACK_Msk
15826/******************* Bit definition for USART_ICR register ******************/
15827#define USART_ICR_PECF_Pos (0U)
15828#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
15829#define USART_ICR_PECF USART_ICR_PECF_Msk
15830#define USART_ICR_FECF_Pos (1U)
15831#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
15832#define USART_ICR_FECF USART_ICR_FECF_Msk
15833#define USART_ICR_NCF_Pos (2U)
15834#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)
15835#define USART_ICR_NCF USART_ICR_NCF_Msk
15836#define USART_ICR_ORECF_Pos (3U)
15837#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
15838#define USART_ICR_ORECF USART_ICR_ORECF_Msk
15839#define USART_ICR_IDLECF_Pos (4U)
15840#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
15841#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
15842#define USART_ICR_TCCF_Pos (6U)
15843#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
15844#define USART_ICR_TCCF USART_ICR_TCCF_Msk
15845#define USART_ICR_LBDCF_Pos (8U)
15846#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
15847#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
15848#define USART_ICR_CTSCF_Pos (9U)
15849#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
15850#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
15851#define USART_ICR_RTOCF_Pos (11U)
15852#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
15853#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
15854#define USART_ICR_EOBCF_Pos (12U)
15855#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
15856#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
15857#define USART_ICR_CMCF_Pos (17U)
15858#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
15859#define USART_ICR_CMCF USART_ICR_CMCF_Msk
15860#define USART_ICR_WUCF_Pos (20U)
15861#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
15862#define USART_ICR_WUCF USART_ICR_WUCF_Msk
15864/******************* Bit definition for USART_RDR register ******************/
15865#define USART_RDR_RDR_Pos (0U)
15866#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
15867#define USART_RDR_RDR USART_RDR_RDR_Msk
15869/******************* Bit definition for USART_TDR register ******************/
15870#define USART_TDR_TDR_Pos (0U)
15871#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
15872#define USART_TDR_TDR USART_TDR_TDR_Msk
15874/******************************************************************************/
15875/* */
15876/* Window WATCHDOG */
15877/* */
15878/******************************************************************************/
15879/******************* Bit definition for WWDG_CR register ********************/
15880#define WWDG_CR_T_Pos (0U)
15881#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
15882#define WWDG_CR_T WWDG_CR_T_Msk
15883#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
15884#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
15885#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
15886#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
15887#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
15888#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
15889#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
15892#define WWDG_CR_WDGA_Pos (7U)
15893#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
15894#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
15896/******************* Bit definition for WWDG_CFR register *******************/
15897#define WWDG_CFR_W_Pos (0U)
15898#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
15899#define WWDG_CFR_W WWDG_CFR_W_Msk
15900#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
15901#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
15902#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
15903#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
15904#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
15905#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
15906#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
15909#define WWDG_CFR_WDGTB_Pos (7U)
15910#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
15911#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
15912#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
15913#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
15916#define WWDG_CFR_EWI_Pos (9U)
15917#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
15918#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
15920/******************* Bit definition for WWDG_SR register ********************/
15921#define WWDG_SR_EWIF_Pos (0U)
15922#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
15923#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
15925/******************************************************************************/
15926/* */
15927/* DBG */
15928/* */
15929/******************************************************************************/
15930/******************** Bit definition for DBGMCU_IDCODE register *************/
15931#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
15932#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
15933#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
15934#define DBGMCU_IDCODE_REV_ID_Pos (16U)
15935#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
15936#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
15937
15938/******************** Bit definition for DBGMCU_CR register *****************/
15939#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
15940#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
15941#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
15942#define DBGMCU_CR_DBG_STOP_Pos (1U)
15943#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
15944#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
15945#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
15946#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
15947#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
15948#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
15949#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
15950#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
15951
15952#define DBGMCU_CR_TRACE_MODE_Pos (6U)
15953#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
15954#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
15955#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
15956#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
15958/******************** Bit definition for DBGMCU_APB1_FZ register ************/
15959#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
15960#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
15961#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
15962#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
15963#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
15964#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
15965#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
15966#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
15967#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
15968#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
15969#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
15970#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
15971#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
15972#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
15973#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
15974#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
15975#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
15976#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
15977#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
15978#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
15979#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
15980#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
15981#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
15982#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
15983#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
15984#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
15985#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
15986#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
15987#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos)
15988#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
15989#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
15990#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
15991#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
15992#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
15993#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
15994#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
15995#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
15996#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
15997#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
15998#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (13U)
15999#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos)
16000#define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
16001#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
16002#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
16003#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
16004#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
16005#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
16006#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
16007#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
16008#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
16009#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
16010#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
16011#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos)
16012#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
16013#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
16014#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
16015#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
16016#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
16017#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
16018#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
16019
16020/******************** Bit definition for DBGMCU_APB2_FZ register ************/
16021#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
16022#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
16023#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
16024#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
16025#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
16026#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
16027#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
16028#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
16029#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
16030#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
16031#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
16032#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
16033#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
16034#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
16035#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
16036
16037/******************************************************************************/
16038/* */
16039/* Ethernet MAC Registers bits definitions */
16040/* */
16041/******************************************************************************/
16042/* Bit definition for Ethernet MAC Control Register register */
16043#define ETH_MACCR_WD_Pos (23U)
16044#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
16045#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
16046#define ETH_MACCR_JD_Pos (22U)
16047#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
16048#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
16049#define ETH_MACCR_IFG_Pos (17U)
16050#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
16051#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
16052#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
16053#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
16054#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
16055#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
16056#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
16057#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
16058#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
16059#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
16060#define ETH_MACCR_CSD_Pos (16U)
16061#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
16062#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
16063#define ETH_MACCR_FES_Pos (14U)
16064#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
16065#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
16066#define ETH_MACCR_ROD_Pos (13U)
16067#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
16068#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
16069#define ETH_MACCR_LM_Pos (12U)
16070#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
16071#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
16072#define ETH_MACCR_DM_Pos (11U)
16073#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
16074#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
16075#define ETH_MACCR_IPCO_Pos (10U)
16076#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
16077#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
16078#define ETH_MACCR_RD_Pos (9U)
16079#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
16080#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
16081#define ETH_MACCR_APCS_Pos (7U)
16082#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
16083#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
16084#define ETH_MACCR_BL_Pos (5U)
16085#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
16086#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
16087 a transmission attempt during retries after a collision: 0 =< r <2^k */
16088#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
16089#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
16090#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
16091#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
16092#define ETH_MACCR_DC_Pos (4U)
16093#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
16094#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
16095#define ETH_MACCR_TE_Pos (3U)
16096#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
16097#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
16098#define ETH_MACCR_RE_Pos (2U)
16099#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
16100#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
16101
16102/* Bit definition for Ethernet MAC Frame Filter Register */
16103#define ETH_MACFFR_RA_Pos (31U)
16104#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
16105#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
16106#define ETH_MACFFR_HPF_Pos (10U)
16107#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
16108#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
16109#define ETH_MACFFR_SAF_Pos (9U)
16110#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
16111#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
16112#define ETH_MACFFR_SAIF_Pos (8U)
16113#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
16114#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
16115#define ETH_MACFFR_PCF_Pos (6U)
16116#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
16117#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
16118#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
16119#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
16120#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
16121#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
16122#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
16123#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
16124#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
16125#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
16126#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
16127#define ETH_MACFFR_BFD_Pos (5U)
16128#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
16129#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
16130#define ETH_MACFFR_PAM_Pos (4U)
16131#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
16132#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
16133#define ETH_MACFFR_DAIF_Pos (3U)
16134#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
16135#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
16136#define ETH_MACFFR_HM_Pos (2U)
16137#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
16138#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
16139#define ETH_MACFFR_HU_Pos (1U)
16140#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
16141#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
16142#define ETH_MACFFR_PM_Pos (0U)
16143#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
16144#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
16145
16146/* Bit definition for Ethernet MAC Hash Table High Register */
16147#define ETH_MACHTHR_HTH_Pos (0U)
16148#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
16149#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
16150
16151/* Bit definition for Ethernet MAC Hash Table Low Register */
16152#define ETH_MACHTLR_HTL_Pos (0U)
16153#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
16154#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
16155
16156/* Bit definition for Ethernet MAC MII Address Register */
16157#define ETH_MACMIIAR_PA_Pos (11U)
16158#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
16159#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
16160#define ETH_MACMIIAR_MR_Pos (6U)
16161#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
16162#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
16163#define ETH_MACMIIAR_CR_Pos (2U)
16164#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
16165#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
16166#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
16167#define ETH_MACMIIAR_CR_Div62_Pos (2U)
16168#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
16169#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
16170#define ETH_MACMIIAR_CR_Div16_Pos (3U)
16171#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
16172#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
16173#define ETH_MACMIIAR_CR_Div26_Pos (2U)
16174#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
16175#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
16176#define ETH_MACMIIAR_CR_Div102_Pos (4U)
16177#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
16178#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
16179#define ETH_MACMIIAR_MW_Pos (1U)
16180#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
16181#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
16182#define ETH_MACMIIAR_MB_Pos (0U)
16183#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
16184#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
16185
16186/* Bit definition for Ethernet MAC MII Data Register */
16187#define ETH_MACMIIDR_MD_Pos (0U)
16188#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
16189#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
16190
16191/* Bit definition for Ethernet MAC Flow Control Register */
16192#define ETH_MACFCR_PT_Pos (16U)
16193#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
16194#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
16195#define ETH_MACFCR_ZQPD_Pos (7U)
16196#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
16197#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
16198#define ETH_MACFCR_PLT_Pos (4U)
16199#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
16200#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
16201#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
16202#define ETH_MACFCR_PLT_Minus28_Pos (4U)
16203#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
16204#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
16205#define ETH_MACFCR_PLT_Minus144_Pos (5U)
16206#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
16207#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
16208#define ETH_MACFCR_PLT_Minus256_Pos (4U)
16209#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
16210#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
16211#define ETH_MACFCR_UPFD_Pos (3U)
16212#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
16213#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
16214#define ETH_MACFCR_RFCE_Pos (2U)
16215#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
16216#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
16217#define ETH_MACFCR_TFCE_Pos (1U)
16218#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
16219#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
16220#define ETH_MACFCR_FCBBPA_Pos (0U)
16221#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
16222#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
16223
16224/* Bit definition for Ethernet MAC VLAN Tag Register */
16225#define ETH_MACVLANTR_VLANTC_Pos (16U)
16226#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
16227#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
16228#define ETH_MACVLANTR_VLANTI_Pos (0U)
16229#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
16230#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
16231
16232/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
16233#define ETH_MACRWUFFR_D_Pos (0U)
16234#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
16235#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
16236/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
16237 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
16238/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
16239 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
16240 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
16241 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
16242 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
16243 RSVD - Filter1 Command - RSVD - Filter0 Command
16244 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
16245 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
16246 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
16247
16248/* Bit definition for Ethernet MAC PMT Control and Status Register */
16249#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
16250#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
16251#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
16252#define ETH_MACPMTCSR_GU_Pos (9U)
16253#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
16254#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
16255#define ETH_MACPMTCSR_WFR_Pos (6U)
16256#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
16257#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
16258#define ETH_MACPMTCSR_MPR_Pos (5U)
16259#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
16260#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
16261#define ETH_MACPMTCSR_WFE_Pos (2U)
16262#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
16263#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
16264#define ETH_MACPMTCSR_MPE_Pos (1U)
16265#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
16266#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
16267#define ETH_MACPMTCSR_PD_Pos (0U)
16268#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
16269#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
16270
16271/* Bit definition for Ethernet MAC debug Register */
16272#define ETH_MACDBGR_TFF_Pos (25U)
16273#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
16274#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
16275#define ETH_MACDBGR_TFNE_Pos (24U)
16276#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
16277#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
16278#define ETH_MACDBGR_TPWA_Pos (22U)
16279#define ETH_MACDBGR_TPWA_Msk (0x1UL << ETH_MACDBGR_TPWA_Pos)
16280#define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk /* Tx FIFO write active */
16281#define ETH_MACDBGR_TFRS_Pos (20U)
16282#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
16283#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
16284#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
16285#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
16286#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
16287#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
16288#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
16289#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
16290#define ETH_MACDBGR_TFRS_READ_Pos (20U)
16291#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
16292#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
16293#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
16294#define ETH_MACDBGR_MTP_Pos (19U)
16295#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
16296#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
16297#define ETH_MACDBGR_MTFCS_Pos (17U)
16298#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
16299#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
16300#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
16301#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
16302#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
16303#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
16304#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
16305#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
16306#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
16307#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
16308#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
16309#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
16310#define ETH_MACDBGR_MMTEA_Pos (16U)
16311#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
16312#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
16313#define ETH_MACDBGR_RFFL_Pos (8U)
16314#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
16315#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
16316#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
16317#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
16318#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
16319#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
16320#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
16321#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
16322#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
16323#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
16324#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
16325#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
16326#define ETH_MACDBGR_RFRCS_Pos (5U)
16327#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
16328#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
16329#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
16330#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
16331#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
16332#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
16333#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
16334#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
16335#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
16336#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
16337#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
16338#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
16339#define ETH_MACDBGR_RFWRA_Pos (4U)
16340#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
16341#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
16342#define ETH_MACDBGR_MSFRWCS_Pos (1U)
16343#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
16344#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
16345#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
16346#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
16347#define ETH_MACDBGR_MMRPEA_Pos (0U)
16348#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
16349#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
16350
16351/* Bit definition for Ethernet MAC Status Register */
16352#define ETH_MACSR_TSTS_Pos (9U)
16353#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
16354#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
16355#define ETH_MACSR_MMCTS_Pos (6U)
16356#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
16357#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
16358#define ETH_MACSR_MMMCRS_Pos (5U)
16359#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
16360#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
16361#define ETH_MACSR_MMCS_Pos (4U)
16362#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
16363#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
16364#define ETH_MACSR_PMTS_Pos (3U)
16365#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
16366#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
16367
16368/* Bit definition for Ethernet MAC Interrupt Mask Register */
16369#define ETH_MACIMR_TSTIM_Pos (9U)
16370#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
16371#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
16372#define ETH_MACIMR_PMTIM_Pos (3U)
16373#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
16374#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
16375
16376/* Bit definition for Ethernet MAC Address0 High Register */
16377#define ETH_MACA0HR_MACA0H_Pos (0U)
16378#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
16379#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
16380
16381/* Bit definition for Ethernet MAC Address0 Low Register */
16382#define ETH_MACA0LR_MACA0L_Pos (0U)
16383#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
16384#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
16385
16386/* Bit definition for Ethernet MAC Address1 High Register */
16387#define ETH_MACA1HR_AE_Pos (31U)
16388#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
16389#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
16390#define ETH_MACA1HR_SA_Pos (30U)
16391#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
16392#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
16393#define ETH_MACA1HR_MBC_Pos (24U)
16394#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
16395#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
16396#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
16397#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
16398#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
16399#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
16400#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
16401#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
16402#define ETH_MACA1HR_MACA1H_Pos (0U)
16403#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
16404#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
16405
16406/* Bit definition for Ethernet MAC Address1 Low Register */
16407#define ETH_MACA1LR_MACA1L_Pos (0U)
16408#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
16409#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
16410
16411/* Bit definition for Ethernet MAC Address2 High Register */
16412#define ETH_MACA2HR_AE_Pos (31U)
16413#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
16414#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
16415#define ETH_MACA2HR_SA_Pos (30U)
16416#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
16417#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
16418#define ETH_MACA2HR_MBC_Pos (24U)
16419#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
16420#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
16421#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
16422#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
16423#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
16424#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
16425#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
16426#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
16427#define ETH_MACA2HR_MACA2H_Pos (0U)
16428#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
16429#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
16430
16431/* Bit definition for Ethernet MAC Address2 Low Register */
16432#define ETH_MACA2LR_MACA2L_Pos (0U)
16433#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
16434#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
16435
16436/* Bit definition for Ethernet MAC Address3 High Register */
16437#define ETH_MACA3HR_AE_Pos (31U)
16438#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
16439#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
16440#define ETH_MACA3HR_SA_Pos (30U)
16441#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
16442#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
16443#define ETH_MACA3HR_MBC_Pos (24U)
16444#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
16445#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
16446#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
16447#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
16448#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
16449#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
16450#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
16451#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
16452#define ETH_MACA3HR_MACA3H_Pos (0U)
16453#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
16454#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
16455
16456/* Bit definition for Ethernet MAC Address3 Low Register */
16457#define ETH_MACA3LR_MACA3L_Pos (0U)
16458#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
16459#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
16460
16461/******************************************************************************/
16462/* Ethernet MMC Registers bits definition */
16463/******************************************************************************/
16464
16465/* Bit definition for Ethernet MMC Contol Register */
16466#define ETH_MMCCR_MCFHP_Pos (5U)
16467#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
16468#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
16469#define ETH_MMCCR_MCP_Pos (4U)
16470#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
16471#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
16472#define ETH_MMCCR_MCF_Pos (3U)
16473#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
16474#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
16475#define ETH_MMCCR_ROR_Pos (2U)
16476#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
16477#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
16478#define ETH_MMCCR_CSR_Pos (1U)
16479#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
16480#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
16481#define ETH_MMCCR_CR_Pos (0U)
16482#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
16483#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
16484
16485/* Bit definition for Ethernet MMC Receive Interrupt Register */
16486#define ETH_MMCRIR_RGUFS_Pos (17U)
16487#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
16488#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
16489#define ETH_MMCRIR_RFAES_Pos (6U)
16490#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
16491#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
16492#define ETH_MMCRIR_RFCES_Pos (5U)
16493#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
16494#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
16495
16496/* Bit definition for Ethernet MMC Transmit Interrupt Register */
16497#define ETH_MMCTIR_TGFS_Pos (21U)
16498#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
16499#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
16500#define ETH_MMCTIR_TGFMSCS_Pos (15U)
16501#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
16502#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
16503#define ETH_MMCTIR_TGFSCS_Pos (14U)
16504#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
16505#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
16506
16507/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
16508#define ETH_MMCRIMR_RGUFM_Pos (17U)
16509#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
16510#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
16511#define ETH_MMCRIMR_RFAEM_Pos (6U)
16512#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
16513#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
16514#define ETH_MMCRIMR_RFCEM_Pos (5U)
16515#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
16516#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
16517
16518/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
16519#define ETH_MMCTIMR_TGFM_Pos (21U)
16520#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
16521#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
16522#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
16523#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
16524#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
16525#define ETH_MMCTIMR_TGFSCM_Pos (14U)
16526#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
16527#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
16528
16529/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
16530#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
16531#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
16532#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
16533
16534/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
16535#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
16536#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
16537#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
16538
16539/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
16540#define ETH_MMCTGFCR_TGFC_Pos (0U)
16541#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
16542#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
16543
16544/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
16545#define ETH_MMCRFCECR_RFCEC_Pos (0U)
16546#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
16547#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
16548
16549/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
16550#define ETH_MMCRFAECR_RFAEC_Pos (0U)
16551#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
16552#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
16553
16554/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
16555#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
16556#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
16557#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
16558
16559/******************************************************************************/
16560/* Ethernet PTP Registers bits definition */
16561/******************************************************************************/
16562
16563/* Bit definition for Ethernet PTP Time Stamp Contol Register */
16564#define ETH_PTPTSCR_TSCNT_Pos (16U)
16565#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
16566#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
16567#define ETH_PTPTSSR_TSSMRME_Pos (15U)
16568#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos)
16569#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
16570#define ETH_PTPTSSR_TSSEME_Pos (14U)
16571#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos)
16572#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
16573#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
16574#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos)
16575#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
16576#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
16577#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos)
16578#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
16579#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
16580#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos)
16581#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
16582#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
16583#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos)
16584#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
16585#define ETH_PTPTSSR_TSSSR_Pos (9U)
16586#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos)
16587#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
16588#define ETH_PTPTSSR_TSSARFE_Pos (8U)
16589#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos)
16590#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
16591
16592#define ETH_PTPTSCR_TSARU_Pos (5U)
16593#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
16594#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
16595#define ETH_PTPTSCR_TSITE_Pos (4U)
16596#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
16597#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
16598#define ETH_PTPTSCR_TSSTU_Pos (3U)
16599#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
16600#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
16601#define ETH_PTPTSCR_TSSTI_Pos (2U)
16602#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
16603#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
16604#define ETH_PTPTSCR_TSFCU_Pos (1U)
16605#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
16606#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
16607#define ETH_PTPTSCR_TSE_Pos (0U)
16608#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
16609#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
16610
16611/* Bit definition for Ethernet PTP Sub-Second Increment Register */
16612#define ETH_PTPSSIR_STSSI_Pos (0U)
16613#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
16614#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
16615
16616/* Bit definition for Ethernet PTP Time Stamp High Register */
16617#define ETH_PTPTSHR_STS_Pos (0U)
16618#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
16619#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
16620
16621/* Bit definition for Ethernet PTP Time Stamp Low Register */
16622#define ETH_PTPTSLR_STPNS_Pos (31U)
16623#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
16624#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
16625#define ETH_PTPTSLR_STSS_Pos (0U)
16626#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
16627#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
16628
16629/* Bit definition for Ethernet PTP Time Stamp High Update Register */
16630#define ETH_PTPTSHUR_TSUS_Pos (0U)
16631#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
16632#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
16633
16634/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
16635#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
16636#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
16637#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
16638#define ETH_PTPTSLUR_TSUSS_Pos (0U)
16639#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
16640#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
16641
16642/* Bit definition for Ethernet PTP Time Stamp Addend Register */
16643#define ETH_PTPTSAR_TSA_Pos (0U)
16644#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
16645#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
16646
16647/* Bit definition for Ethernet PTP Target Time High Register */
16648#define ETH_PTPTTHR_TTSH_Pos (0U)
16649#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
16650#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
16651
16652/* Bit definition for Ethernet PTP Target Time Low Register */
16653#define ETH_PTPTTLR_TTSL_Pos (0U)
16654#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
16655#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
16656
16657/* Bit definition for Ethernet PTP Time Stamp Status Register */
16658#define ETH_PTPTSSR_TSTTR_Pos (5U)
16659#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
16660#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
16661#define ETH_PTPTSSR_TSSO_Pos (4U)
16662#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
16663#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
16664
16665/* Bit definition for Ethernet PTP PPS Control Register */
16666#define ETH_PTPPPSCR_PPSFREQ_Pos (0U)
16667#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos)
16668#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */
16669
16670/******************************************************************************/
16671/* Ethernet DMA Registers bits definition */
16672/******************************************************************************/
16673
16674/* Bit definition for Ethernet DMA Bus Mode Register */
16675#define ETH_DMABMR_AAB_Pos (25U)
16676#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
16677#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
16678#define ETH_DMABMR_FPM_Pos (24U)
16679#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
16680#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
16681#define ETH_DMABMR_USP_Pos (23U)
16682#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
16683#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
16684#define ETH_DMABMR_RDP_Pos (17U)
16685#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
16686#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
16687#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
16688#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
16689#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
16690#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
16691#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
16692#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
16693#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
16694#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
16695#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
16696#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
16697#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
16698#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
16699#define ETH_DMABMR_FB_Pos (16U)
16700#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
16701#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
16702#define ETH_DMABMR_RTPR_Pos (14U)
16703#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
16704#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
16705#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
16706#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
16707#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
16708#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
16709#define ETH_DMABMR_PBL_Pos (8U)
16710#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
16711#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
16712#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
16713#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
16714#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
16715#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
16716#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
16717#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
16718#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
16719#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
16720#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
16721#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
16722#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
16723#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
16724#define ETH_DMABMR_EDE_Pos (7U)
16725#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
16726#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
16727#define ETH_DMABMR_DSL_Pos (2U)
16728#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
16729#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
16730#define ETH_DMABMR_DA_Pos (1U)
16731#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
16732#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
16733#define ETH_DMABMR_SR_Pos (0U)
16734#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
16735#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
16736
16737/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
16738#define ETH_DMATPDR_TPD_Pos (0U)
16739#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
16740#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
16741
16742/* Bit definition for Ethernet DMA Receive Poll Demand Register */
16743#define ETH_DMARPDR_RPD_Pos (0U)
16744#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
16745#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
16746
16747/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
16748#define ETH_DMARDLAR_SRL_Pos (0U)
16749#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
16750#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
16751
16752/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
16753#define ETH_DMATDLAR_STL_Pos (0U)
16754#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
16755#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
16756
16757/* Bit definition for Ethernet DMA Status Register */
16758#define ETH_DMASR_TSTS_Pos (29U)
16759#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
16760#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
16761#define ETH_DMASR_PMTS_Pos (28U)
16762#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
16763#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
16764#define ETH_DMASR_MMCS_Pos (27U)
16765#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
16766#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
16767#define ETH_DMASR_EBS_Pos (23U)
16768#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
16769#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
16770 /* combination with EBS[2:0] for GetFlagStatus function */
16771#define ETH_DMASR_EBS_DescAccess_Pos (25U)
16772#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
16773#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
16774#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
16775#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
16776#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
16777#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
16778#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
16779#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
16780#define ETH_DMASR_TPS_Pos (20U)
16781#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
16782#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
16783#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
16784#define ETH_DMASR_TPS_Fetching_Pos (20U)
16785#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
16786#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
16787#define ETH_DMASR_TPS_Waiting_Pos (21U)
16788#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
16789#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
16790#define ETH_DMASR_TPS_Reading_Pos (20U)
16791#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
16792#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
16793#define ETH_DMASR_TPS_Suspended_Pos (21U)
16794#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
16795#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
16796#define ETH_DMASR_TPS_Closing_Pos (20U)
16797#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
16798#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
16799#define ETH_DMASR_RPS_Pos (17U)
16800#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
16801#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
16802#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
16803#define ETH_DMASR_RPS_Fetching_Pos (17U)
16804#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
16805#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
16806#define ETH_DMASR_RPS_Waiting_Pos (17U)
16807#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
16808#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
16809#define ETH_DMASR_RPS_Suspended_Pos (19U)
16810#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
16811#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
16812#define ETH_DMASR_RPS_Closing_Pos (17U)
16813#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
16814#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
16815#define ETH_DMASR_RPS_Queuing_Pos (17U)
16816#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
16817#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
16818#define ETH_DMASR_NIS_Pos (16U)
16819#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
16820#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
16821#define ETH_DMASR_AIS_Pos (15U)
16822#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
16823#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
16824#define ETH_DMASR_ERS_Pos (14U)
16825#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
16826#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
16827#define ETH_DMASR_FBES_Pos (13U)
16828#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
16829#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
16830#define ETH_DMASR_ETS_Pos (10U)
16831#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
16832#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
16833#define ETH_DMASR_RWTS_Pos (9U)
16834#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
16835#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
16836#define ETH_DMASR_RPSS_Pos (8U)
16837#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
16838#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
16839#define ETH_DMASR_RBUS_Pos (7U)
16840#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
16841#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
16842#define ETH_DMASR_RS_Pos (6U)
16843#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
16844#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
16845#define ETH_DMASR_TUS_Pos (5U)
16846#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
16847#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
16848#define ETH_DMASR_ROS_Pos (4U)
16849#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
16850#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
16851#define ETH_DMASR_TJTS_Pos (3U)
16852#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
16853#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
16854#define ETH_DMASR_TBUS_Pos (2U)
16855#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
16856#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
16857#define ETH_DMASR_TPSS_Pos (1U)
16858#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
16859#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
16860#define ETH_DMASR_TS_Pos (0U)
16861#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
16862#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
16863
16864/* Bit definition for Ethernet DMA Operation Mode Register */
16865#define ETH_DMAOMR_DTCEFD_Pos (26U)
16866#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
16867#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
16868#define ETH_DMAOMR_RSF_Pos (25U)
16869#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
16870#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
16871#define ETH_DMAOMR_DFRF_Pos (24U)
16872#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
16873#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
16874#define ETH_DMAOMR_TSF_Pos (21U)
16875#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
16876#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
16877#define ETH_DMAOMR_FTF_Pos (20U)
16878#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
16879#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
16880#define ETH_DMAOMR_TTC_Pos (14U)
16881#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
16882#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
16883#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
16884#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
16885#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
16886#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
16887#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
16888#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
16889#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
16890#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
16891#define ETH_DMAOMR_ST_Pos (13U)
16892#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
16893#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
16894#define ETH_DMAOMR_FEF_Pos (7U)
16895#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
16896#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
16897#define ETH_DMAOMR_FUGF_Pos (6U)
16898#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
16899#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
16900#define ETH_DMAOMR_RTC_Pos (3U)
16901#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
16902#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
16903#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
16904#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
16905#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
16906#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
16907#define ETH_DMAOMR_OSF_Pos (2U)
16908#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
16909#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
16910#define ETH_DMAOMR_SR_Pos (1U)
16911#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
16912#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
16913
16914/* Bit definition for Ethernet DMA Interrupt Enable Register */
16915#define ETH_DMAIER_NISE_Pos (16U)
16916#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
16917#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
16918#define ETH_DMAIER_AISE_Pos (15U)
16919#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
16920#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
16921#define ETH_DMAIER_ERIE_Pos (14U)
16922#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
16923#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
16924#define ETH_DMAIER_FBEIE_Pos (13U)
16925#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
16926#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
16927#define ETH_DMAIER_ETIE_Pos (10U)
16928#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
16929#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
16930#define ETH_DMAIER_RWTIE_Pos (9U)
16931#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
16932#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
16933#define ETH_DMAIER_RPSIE_Pos (8U)
16934#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
16935#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
16936#define ETH_DMAIER_RBUIE_Pos (7U)
16937#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
16938#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
16939#define ETH_DMAIER_RIE_Pos (6U)
16940#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
16941#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
16942#define ETH_DMAIER_TUIE_Pos (5U)
16943#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
16944#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
16945#define ETH_DMAIER_ROIE_Pos (4U)
16946#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
16947#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
16948#define ETH_DMAIER_TJTIE_Pos (3U)
16949#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
16950#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
16951#define ETH_DMAIER_TBUIE_Pos (2U)
16952#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
16953#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
16954#define ETH_DMAIER_TPSIE_Pos (1U)
16955#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
16956#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
16957#define ETH_DMAIER_TIE_Pos (0U)
16958#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
16959#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
16960
16961/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
16962#define ETH_DMAMFBOCR_OFOC_Pos (28U)
16963#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
16964#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
16965#define ETH_DMAMFBOCR_MFA_Pos (17U)
16966#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
16967#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
16968#define ETH_DMAMFBOCR_OMFC_Pos (16U)
16969#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
16970#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
16971#define ETH_DMAMFBOCR_MFC_Pos (0U)
16972#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
16973#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
16974
16975/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
16976#define ETH_DMACHTDR_HTDAP_Pos (0U)
16977#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
16978#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
16979
16980/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
16981#define ETH_DMACHRDR_HRDAP_Pos (0U)
16982#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
16983#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
16984
16985/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
16986#define ETH_DMACHTBAR_HTBAP_Pos (0U)
16987#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
16988#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
16989
16990/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
16991#define ETH_DMACHRBAR_HRBAP_Pos (0U)
16992#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
16993#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
16994
16995/******************************************************************************/
16996/* */
16997/* USB_OTG */
16998/* */
16999/******************************************************************************/
17000/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
17001#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
17002#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
17003#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
17004#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
17005#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
17006#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
17007#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
17008#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
17009#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
17010#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
17011#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
17012#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
17013#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
17014#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
17015#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
17016#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
17017#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
17018#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
17019#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
17020#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
17021#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
17022#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
17023#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
17024#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
17025#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
17026#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
17027#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
17028#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
17029#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
17030#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
17031#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
17032#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
17033#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
17034#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
17035#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
17036#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
17037#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
17038#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
17039#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
17040#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
17041#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
17042#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
17043#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
17044#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
17045#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
17046#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
17047#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
17048#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
17049#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
17050#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
17051#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
17052#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
17053#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
17054#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
17056/******************** Bit definition for USB_OTG_HCFG register ********************/
17057#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
17058#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
17059#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
17060#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
17061#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
17062#define USB_OTG_HCFG_FSLSS_Pos (2U)
17063#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
17064#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
17066/******************** Bit definition for USB_OTG_DCFG register ********************/
17067#define USB_OTG_DCFG_DSPD_Pos (0U)
17068#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
17069#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
17070#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
17071#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
17072#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
17073#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
17074#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
17076#define USB_OTG_DCFG_DAD_Pos (4U)
17077#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
17078#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
17079#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
17080#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
17081#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
17082#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
17083#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
17084#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
17085#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
17087#define USB_OTG_DCFG_PFIVL_Pos (11U)
17088#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
17089#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
17090#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
17091#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
17093#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
17094#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
17095#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
17096#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
17097#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
17099/******************** Bit definition for USB_OTG_PCGCR register ********************/
17100#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
17101#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
17102#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
17103#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
17104#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
17105#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
17106#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
17107#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
17108#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
17110/******************** Bit definition for USB_OTG_GOTGINT register ********************/
17111#define USB_OTG_GOTGINT_SEDET_Pos (2U)
17112#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
17113#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
17114#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
17115#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
17116#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
17117#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
17118#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
17119#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
17120#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
17121#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
17122#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
17123#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
17124#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
17125#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
17126#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
17127#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
17128#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
17129#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
17130#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos)
17131#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk
17133/******************** Bit definition for USB_OTG_DCTL register ********************/
17134#define USB_OTG_DCTL_RWUSIG_Pos (0U)
17135#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
17136#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
17137#define USB_OTG_DCTL_SDIS_Pos (1U)
17138#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
17139#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
17140#define USB_OTG_DCTL_GINSTS_Pos (2U)
17141#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
17142#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
17143#define USB_OTG_DCTL_GONSTS_Pos (3U)
17144#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
17145#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
17147#define USB_OTG_DCTL_TCTL_Pos (4U)
17148#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
17149#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
17150#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
17151#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
17152#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
17153#define USB_OTG_DCTL_SGINAK_Pos (7U)
17154#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
17155#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
17156#define USB_OTG_DCTL_CGINAK_Pos (8U)
17157#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
17158#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
17159#define USB_OTG_DCTL_SGONAK_Pos (9U)
17160#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
17161#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
17162#define USB_OTG_DCTL_CGONAK_Pos (10U)
17163#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
17164#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
17165#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
17166#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
17167#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
17169/******************** Bit definition for USB_OTG_HFIR register ********************/
17170#define USB_OTG_HFIR_FRIVL_Pos (0U)
17171#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
17172#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
17174/******************** Bit definition for USB_OTG_HFNUM register ********************/
17175#define USB_OTG_HFNUM_FRNUM_Pos (0U)
17176#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
17177#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
17178#define USB_OTG_HFNUM_FTREM_Pos (16U)
17179#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
17180#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
17182/******************** Bit definition for USB_OTG_DSTS register ********************/
17183#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
17184#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
17185#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
17187#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
17188#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
17189#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
17190#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
17191#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
17192#define USB_OTG_DSTS_EERR_Pos (3U)
17193#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
17194#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
17195#define USB_OTG_DSTS_FNSOF_Pos (8U)
17196#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
17197#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
17199/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
17200#define USB_OTG_GAHBCFG_GINT_Pos (0U)
17201#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
17202#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
17203#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
17204#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
17205#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
17206#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
17207#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
17208#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
17209#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
17210#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
17211#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
17212#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
17213#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
17214#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
17215#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
17216#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
17217#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
17218#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
17219#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
17221/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
17222#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
17223#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
17224#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
17225#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
17226#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
17227#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
17228#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
17229#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
17230#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
17231#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
17232#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
17233#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
17234#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
17235#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
17236#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
17237#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
17238#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
17239#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
17240#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
17241#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
17242#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
17243#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
17244#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
17245#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
17246#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
17247#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
17248#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
17249#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
17250#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
17251#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
17252#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
17253#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
17254#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
17255#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
17256#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
17257#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
17258#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
17259#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
17260#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
17261#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
17262#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
17263#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
17264#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
17265#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
17266#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
17267#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
17268#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
17269#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
17270#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
17271#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
17272#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
17273#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
17274#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
17275#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
17276#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
17277#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
17278#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
17279#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
17280#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
17281#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
17282#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
17284/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
17285#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
17286#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
17287#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
17288#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
17289#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
17290#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
17291#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
17292#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
17293#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
17294#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
17295#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
17296#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
17297#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
17298#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
17299#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
17300#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
17301#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
17302#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
17303#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
17304#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
17305#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
17306#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
17307#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
17308#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
17309#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
17310#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
17311#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
17312#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
17313#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
17315/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
17316#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
17317#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
17318#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
17319#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
17320#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
17321#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
17322#define USB_OTG_DIEPMSK_TOM_Pos (3U)
17323#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
17324#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
17325#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
17326#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
17327#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
17328#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
17329#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
17330#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
17331#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
17332#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
17333#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
17334#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
17335#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
17336#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
17337#define USB_OTG_DIEPMSK_BIM_Pos (9U)
17338#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
17339#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
17341/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
17342#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
17343#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
17344#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
17345#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
17346#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17347#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
17348#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17349#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17350#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17351#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17352#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17353#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17354#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17355#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
17357#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
17358#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17359#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
17360#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17361#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17362#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17363#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17364#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17365#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17366#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17367#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
17369/******************** Bit definition for USB_OTG_HAINT register ********************/
17370#define USB_OTG_HAINT_HAINT_Pos (0U)
17371#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
17372#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
17374/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
17375#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
17376#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
17377#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
17378#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
17379#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
17380#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
17381#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
17382#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
17383#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
17384#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
17385#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
17386#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
17387#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
17388#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
17389#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
17390#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
17391#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
17392#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
17393#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
17394#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
17395#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
17396#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
17397#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
17398#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
17399#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
17400#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
17401#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
17402#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
17403#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
17404#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
17405#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
17406#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
17407#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
17408#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
17409#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
17410#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
17412/******************** Bit definition for USB_OTG_GINTSTS register ********************/
17413#define USB_OTG_GINTSTS_CMOD_Pos (0U)
17414#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
17415#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
17416#define USB_OTG_GINTSTS_MMIS_Pos (1U)
17417#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
17418#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
17419#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
17420#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
17421#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
17422#define USB_OTG_GINTSTS_SOF_Pos (3U)
17423#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
17424#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
17425#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
17426#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
17427#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
17428#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
17429#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
17430#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
17431#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
17432#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
17433#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
17434#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
17435#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
17436#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
17437#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
17438#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
17439#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
17440#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
17441#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
17442#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
17443#define USB_OTG_GINTSTS_USBRST_Pos (12U)
17444#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
17445#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
17446#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
17447#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
17448#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
17449#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
17450#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
17451#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
17452#define USB_OTG_GINTSTS_EOPF_Pos (15U)
17453#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
17454#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
17455#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
17456#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
17457#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
17458#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
17459#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
17460#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
17461#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
17462#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
17463#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
17464#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
17465#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
17466#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
17467#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
17468#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
17469#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
17470#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
17471#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
17472#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
17473#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
17474#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
17475#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
17476#define USB_OTG_GINTSTS_HCINT_Pos (25U)
17477#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
17478#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
17479#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
17480#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
17481#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
17482#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
17483#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
17484#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
17485#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
17486#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
17487#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
17488#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
17489#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
17490#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
17491#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
17492#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
17493#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
17494#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
17495#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
17496#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
17498/******************** Bit definition for USB_OTG_GINTMSK register ********************/
17499#define USB_OTG_GINTMSK_MMISM_Pos (1U)
17500#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
17501#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
17502#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
17503#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
17504#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
17505#define USB_OTG_GINTMSK_SOFM_Pos (3U)
17506#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
17507#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
17508#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
17509#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
17510#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
17511#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
17512#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
17513#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
17514#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
17515#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
17516#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
17517#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
17518#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
17519#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
17520#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
17521#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
17522#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
17523#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
17524#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
17525#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
17526#define USB_OTG_GINTMSK_USBRST_Pos (12U)
17527#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
17528#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
17529#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
17530#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
17531#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
17532#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
17533#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
17534#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
17535#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
17536#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
17537#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
17538#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
17539#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
17540#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
17541#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
17542#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
17543#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
17544#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
17545#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
17546#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
17547#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
17548#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
17549#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
17550#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
17551#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
17552#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
17553#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
17554#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
17555#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
17556#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
17557#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
17558#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
17559#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
17560#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
17561#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
17562#define USB_OTG_GINTMSK_HCIM_Pos (25U)
17563#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
17564#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
17565#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
17566#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
17567#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
17568#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
17569#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
17570#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
17571#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
17572#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
17573#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
17574#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
17575#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
17576#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
17577#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
17578#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
17579#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
17580#define USB_OTG_GINTMSK_WUIM_Pos (31U)
17581#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
17582#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
17584/******************** Bit definition for USB_OTG_DAINT register ********************/
17585#define USB_OTG_DAINT_IEPINT_Pos (0U)
17586#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
17587#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
17588#define USB_OTG_DAINT_OEPINT_Pos (16U)
17589#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
17590#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
17592/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
17593#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
17594#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
17595#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
17597/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
17598#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
17599#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
17600#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
17601#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
17602#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
17603#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
17604#define USB_OTG_GRXSTSP_DPID_Pos (15U)
17605#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
17606#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
17607#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
17608#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
17609#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
17611/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
17612#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
17613#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
17614#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
17615#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
17616#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
17617#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
17619/******************** Bit definition for OTG register ********************/
17620
17621#define USB_OTG_CHNUM_Pos (0U)
17622#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
17623#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
17624#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
17625#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
17626#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
17627#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
17628#define USB_OTG_BCNT_Pos (4U)
17629#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
17630#define USB_OTG_BCNT USB_OTG_BCNT_Msk
17632#define USB_OTG_DPID_Pos (15U)
17633#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
17634#define USB_OTG_DPID USB_OTG_DPID_Msk
17635#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
17636#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
17638#define USB_OTG_PKTSTS_Pos (17U)
17639#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
17640#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
17641#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
17642#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
17643#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
17644#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
17646#define USB_OTG_EPNUM_Pos (0U)
17647#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
17648#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
17649#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
17650#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
17651#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
17652#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
17654#define USB_OTG_FRMNUM_Pos (21U)
17655#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
17656#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
17657#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
17658#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
17659#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
17660#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
17662/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
17663#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
17664#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
17665#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
17667/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
17668#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
17669#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
17670#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
17672/******************** Bit definition for OTG register ********************/
17673#define USB_OTG_NPTXFSA_Pos (0U)
17674#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
17675#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
17676#define USB_OTG_NPTXFD_Pos (16U)
17677#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
17678#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
17679#define USB_OTG_TX0FSA_Pos (0U)
17680#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
17681#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
17682#define USB_OTG_TX0FD_Pos (16U)
17683#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
17684#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
17686/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
17687#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
17688#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
17689#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
17691/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
17692#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
17693#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
17694#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
17696#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
17697#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
17698#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
17699#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
17700#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
17701#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
17702#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
17703#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
17704#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
17705#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
17706#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
17708#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
17709#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
17710#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
17711#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
17712#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
17713#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
17714#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
17715#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
17716#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
17717#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
17719/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
17720#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
17721#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
17722#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
17723#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
17724#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
17725#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
17727#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
17728#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17729#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
17730#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17731#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17732#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17733#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17734#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17735#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17736#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17737#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17738#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
17739#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
17740#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
17741#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
17743#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
17744#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17745#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
17746#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17747#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17748#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17749#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17750#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17751#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17752#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17753#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17754#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
17755#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
17756#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
17757#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
17759/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
17760#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
17761#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
17762#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
17764/******************** Bit definition for USB_OTG_DEACHINT register ********************/
17765#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
17766#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
17767#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
17768#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
17769#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
17770#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
17772/******************** Bit definition for USB_OTG_GCCFG register ********************/
17773#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
17774#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
17775#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
17776#define USB_OTG_GCCFG_VBDEN_Pos (21U)
17777#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
17778#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
17780/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
17781#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
17782#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
17783#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
17784#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
17785#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
17786#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
17788/******************** Bit definition for USB_OTG_CID register ********************/
17789#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
17790#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
17791#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
17793/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
17794#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
17795#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
17796#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
17797#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
17798#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
17799#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
17800#define USB_OTG_GLPMCFG_BESL_Pos (2U)
17801#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
17802#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
17803#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
17804#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
17805#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
17806#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
17807#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
17808#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
17809#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
17810#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
17811#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
17812#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
17813#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
17814#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
17815#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
17816#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
17817#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
17818#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
17819#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
17820#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
17821#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
17822#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
17823#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
17824#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
17825#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
17826#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
17827#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
17828#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
17829#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
17830#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
17831#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
17832#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
17833#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
17834#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
17835#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
17836#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
17837#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
17838#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
17840/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
17841#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
17842#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
17843#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
17844#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
17845#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
17846#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
17847#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
17848#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
17849#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
17850#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
17851#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
17852#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
17853#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
17854#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
17855#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
17856#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
17857#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
17858#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
17859#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
17860#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
17861#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
17862#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
17863#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
17864#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
17865#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
17866#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
17867#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
17869/******************** Bit definition for USB_OTG_HPRT register ********************/
17870#define USB_OTG_HPRT_PCSTS_Pos (0U)
17871#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
17872#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
17873#define USB_OTG_HPRT_PCDET_Pos (1U)
17874#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
17875#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
17876#define USB_OTG_HPRT_PENA_Pos (2U)
17877#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
17878#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
17879#define USB_OTG_HPRT_PENCHNG_Pos (3U)
17880#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
17881#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
17882#define USB_OTG_HPRT_POCA_Pos (4U)
17883#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
17884#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
17885#define USB_OTG_HPRT_POCCHNG_Pos (5U)
17886#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
17887#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
17888#define USB_OTG_HPRT_PRES_Pos (6U)
17889#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
17890#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
17891#define USB_OTG_HPRT_PSUSP_Pos (7U)
17892#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
17893#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
17894#define USB_OTG_HPRT_PRST_Pos (8U)
17895#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
17896#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
17898#define USB_OTG_HPRT_PLSTS_Pos (10U)
17899#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
17900#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
17901#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
17902#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
17903#define USB_OTG_HPRT_PPWR_Pos (12U)
17904#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
17905#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
17907#define USB_OTG_HPRT_PTCTL_Pos (13U)
17908#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
17909#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
17910#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
17911#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
17912#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
17913#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
17915#define USB_OTG_HPRT_PSPD_Pos (17U)
17916#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
17917#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
17918#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
17919#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
17921/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
17922#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
17923#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
17924#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
17925#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
17926#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
17927#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
17928#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
17929#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
17930#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
17931#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
17932#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
17933#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
17934#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
17935#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
17936#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
17937#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
17938#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
17939#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
17940#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
17941#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
17942#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
17943#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
17944#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
17945#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
17946#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
17947#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
17948#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
17949#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
17950#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
17951#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
17952#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
17953#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
17954#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
17956/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
17957#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
17958#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
17959#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
17960#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
17961#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
17962#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
17964/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
17965#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
17966#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
17967#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
17968#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
17969#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
17970#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
17971#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
17972#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
17973#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
17974#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
17975#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
17976#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
17978#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
17979#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
17980#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
17981#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
17982#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
17983#define USB_OTG_DIEPCTL_STALL_Pos (21U)
17984#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
17985#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
17987#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
17988#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17989#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
17990#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17991#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17992#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17993#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
17994#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
17995#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
17996#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
17997#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
17998#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
17999#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
18000#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
18001#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
18002#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
18003#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
18004#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
18005#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
18006#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
18007#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
18008#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
18009#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
18010#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
18011#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
18013/******************** Bit definition for USB_OTG_HCCHAR register ********************/
18014#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
18015#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
18016#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
18018#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
18019#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
18020#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
18021#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
18022#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
18023#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
18024#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
18025#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
18026#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
18027#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
18028#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
18029#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
18030#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
18032#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
18033#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
18034#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
18035#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
18036#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
18038#define USB_OTG_HCCHAR_MC_Pos (20U)
18039#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
18040#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
18041#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
18042#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
18044#define USB_OTG_HCCHAR_DAD_Pos (22U)
18045#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
18046#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
18047#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
18048#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
18049#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
18050#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
18051#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
18052#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
18053#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
18054#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
18055#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
18056#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
18057#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
18058#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
18059#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
18060#define USB_OTG_HCCHAR_CHENA_Pos (31U)
18061#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
18062#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
18064/******************** Bit definition for USB_OTG_HCSPLT register ********************/
18065
18066#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
18067#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
18068#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
18069#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
18070#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
18071#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
18072#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
18073#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
18074#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
18075#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
18077#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
18078#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
18079#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
18080#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
18081#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
18082#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
18083#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
18084#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
18085#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
18086#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
18088#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
18089#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
18090#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
18091#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
18092#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
18093#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
18094#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
18095#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
18096#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
18097#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
18098#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
18100/******************** Bit definition for USB_OTG_HCINT register ********************/
18101#define USB_OTG_HCINT_XFRC_Pos (0U)
18102#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
18103#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
18104#define USB_OTG_HCINT_CHH_Pos (1U)
18105#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
18106#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
18107#define USB_OTG_HCINT_AHBERR_Pos (2U)
18108#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
18109#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
18110#define USB_OTG_HCINT_STALL_Pos (3U)
18111#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
18112#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
18113#define USB_OTG_HCINT_NAK_Pos (4U)
18114#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
18115#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
18116#define USB_OTG_HCINT_ACK_Pos (5U)
18117#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
18118#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
18119#define USB_OTG_HCINT_NYET_Pos (6U)
18120#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
18121#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
18122#define USB_OTG_HCINT_TXERR_Pos (7U)
18123#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
18124#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
18125#define USB_OTG_HCINT_BBERR_Pos (8U)
18126#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
18127#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
18128#define USB_OTG_HCINT_FRMOR_Pos (9U)
18129#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
18130#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
18131#define USB_OTG_HCINT_DTERR_Pos (10U)
18132#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
18133#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
18135/******************** Bit definition for USB_OTG_DIEPINT register ********************/
18136#define USB_OTG_DIEPINT_XFRC_Pos (0U)
18137#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
18138#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
18139#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
18140#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
18141#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
18142#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
18143#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
18144#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
18145#define USB_OTG_DIEPINT_TOC_Pos (3U)
18146#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
18147#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
18148#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
18149#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
18150#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
18151#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
18152#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
18153#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
18154#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
18155#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
18156#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
18157#define USB_OTG_DIEPINT_TXFE_Pos (7U)
18158#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
18159#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
18160#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
18161#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
18162#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
18163#define USB_OTG_DIEPINT_BNA_Pos (9U)
18164#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
18165#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
18166#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
18167#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
18168#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
18169#define USB_OTG_DIEPINT_BERR_Pos (12U)
18170#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
18171#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
18172#define USB_OTG_DIEPINT_NAK_Pos (13U)
18173#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
18174#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
18176/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
18177#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
18178#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
18179#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
18180#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
18181#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
18182#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
18183#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
18184#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
18185#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
18186#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
18187#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
18188#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
18189#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
18190#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
18191#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
18192#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
18193#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
18194#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
18195#define USB_OTG_HCINTMSK_NYET_Pos (6U)
18196#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
18197#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
18198#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
18199#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
18200#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
18201#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
18202#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
18203#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
18204#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
18205#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
18206#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
18207#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
18208#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
18209#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
18211/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
18212
18213#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
18214#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
18215#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
18216#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
18217#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
18218#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
18219#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
18220#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
18221#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
18222/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
18223#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
18224#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
18225#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
18226#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
18227#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
18228#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
18229#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
18230#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
18231#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
18232#define USB_OTG_HCTSIZ_DPID_Pos (29U)
18233#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
18234#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
18235#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
18236#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
18238/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
18239#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
18240#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
18241#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
18243/******************** Bit definition for USB_OTG_HCDMA register ********************/
18244#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
18245#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
18246#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
18248/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
18249#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
18250#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
18251#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
18253/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
18254#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
18255#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
18256#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
18257#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
18258#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
18259#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
18261/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
18262#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
18263#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
18264#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
18265#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
18266#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
18267#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
18268#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
18269#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
18270#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
18271#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
18272#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
18273#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
18274#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
18275#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
18276#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
18277#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
18278#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
18279#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
18280#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
18281#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
18282#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
18283#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
18284#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
18285#define USB_OTG_DOEPCTL_STALL_Pos (21U)
18286#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
18287#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
18288#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
18289#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
18290#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
18291#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
18292#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
18293#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
18294#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
18295#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
18296#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
18297#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
18298#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
18299#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
18301/******************** Bit definition for USB_OTG_DOEPINT register ********************/
18302#define USB_OTG_DOEPINT_XFRC_Pos (0U)
18303#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
18304#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
18305#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
18306#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
18307#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
18308#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
18309#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
18310#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
18311#define USB_OTG_DOEPINT_STUP_Pos (3U)
18312#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
18313#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
18314#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
18315#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
18316#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
18317#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
18318#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
18319#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
18320#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
18321#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
18322#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
18323#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
18324#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
18325#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
18326#define USB_OTG_DOEPINT_NAK_Pos (13U)
18327#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
18328#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
18329#define USB_OTG_DOEPINT_NYET_Pos (14U)
18330#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
18331#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
18332#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
18333#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
18334#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
18336/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
18337#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
18338#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
18339#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
18340#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
18341#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
18342#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
18344#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
18345#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
18346#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
18347#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
18348#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
18350/******************** Bit definition for PCGCCTL register ********************/
18351#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
18352#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
18353#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
18354#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
18355#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
18356#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
18357#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
18358#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
18359#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
18362/******************************************************************************/
18363/* */
18364/* JPEG Encoder/Decoder */
18365/* */
18366/******************************************************************************/
18367/******************** Bit definition for CONFR0 register ********************/
18368#define JPEG_CONFR0_START_Pos (0U)
18369#define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos)
18370#define JPEG_CONFR0_START JPEG_CONFR0_START_Msk
18372/******************** Bit definition for CONFR1 register *******************/
18373#define JPEG_CONFR1_NF_Pos (0U)
18374#define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos)
18375#define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk
18376#define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos)
18377#define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos)
18378#define JPEG_CONFR1_RE_Pos (2U)
18379#define JPEG_CONFR1_RE_Msk (0x1UL << JPEG_CONFR1_RE_Pos)
18380#define JPEG_CONFR1_RE JPEG_CONFR1_RE_Msk
18381#define JPEG_CONFR1_DE_Pos (3U)
18382#define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos)
18383#define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk
18384#define JPEG_CONFR1_COLORSPACE_Pos (4U)
18385#define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)
18386#define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk
18387#define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)
18388#define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)
18389#define JPEG_CONFR1_NS_Pos (6U)
18390#define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos)
18391#define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk
18392#define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos)
18393#define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos)
18394#define JPEG_CONFR1_HDR_Pos (8U)
18395#define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos)
18396#define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk
18397#define JPEG_CONFR1_YSIZE_Pos (16U)
18398#define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)
18399#define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk
18401/******************** Bit definition for CONFR2 register *******************/
18402#define JPEG_CONFR2_NMCU_Pos (0U)
18403#define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)
18404#define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk
18406/******************** Bit definition for CONFR3 register *******************/
18407#define JPEG_CONFR3_NRST_Pos (0U)
18408#define JPEG_CONFR3_NRST_Msk (0xFFFFUL << JPEG_CONFR3_NRST_Pos)
18409#define JPEG_CONFR3_NRST JPEG_CONFR3_NRST_Msk
18410#define JPEG_CONFR3_XSIZE_Pos (16U)
18411#define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)
18412#define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk
18414/******************** Bit definition for CONFR4 register *******************/
18415#define JPEG_CONFR4_HD_Pos (0U)
18416#define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos)
18417#define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk
18418#define JPEG_CONFR4_HA_Pos (1U)
18419#define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos)
18420#define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk
18421#define JPEG_CONFR4_QT_Pos (2U)
18422#define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos)
18423#define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk
18424#define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos)
18425#define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos)
18426#define JPEG_CONFR4_NB_Pos (4U)
18427#define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos)
18428#define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk
18429#define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos)
18430#define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos)
18431#define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos)
18432#define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos)
18433#define JPEG_CONFR4_VSF_Pos (8U)
18434#define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos)
18435#define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk
18436#define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos)
18437#define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos)
18438#define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos)
18439#define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos)
18440#define JPEG_CONFR4_HSF_Pos (12U)
18441#define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos)
18442#define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk
18443#define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos)
18444#define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos)
18445#define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos)
18446#define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos)
18448/******************** Bit definition for CONFR5 register *******************/
18449#define JPEG_CONFR5_HD_Pos (0U)
18450#define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos)
18451#define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk
18452#define JPEG_CONFR5_HA_Pos (1U)
18453#define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos)
18454#define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk
18455#define JPEG_CONFR5_QT_Pos (2U)
18456#define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos)
18457#define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk
18458#define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos)
18459#define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos)
18460#define JPEG_CONFR5_NB_Pos (4U)
18461#define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos)
18462#define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk
18463#define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos)
18464#define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos)
18465#define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos)
18466#define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos)
18467#define JPEG_CONFR5_VSF_Pos (8U)
18468#define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos)
18469#define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk
18470#define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos)
18471#define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos)
18472#define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos)
18473#define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos)
18474#define JPEG_CONFR5_HSF_Pos (12U)
18475#define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos)
18476#define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk
18477#define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos)
18478#define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos)
18479#define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos)
18480#define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos)
18482/******************** Bit definition for CONFR6 register *******************/
18483#define JPEG_CONFR6_HD_Pos (0U)
18484#define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos)
18485#define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk
18486#define JPEG_CONFR6_HA_Pos (1U)
18487#define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos)
18488#define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk
18489#define JPEG_CONFR6_QT_Pos (2U)
18490#define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos)
18491#define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk
18492#define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos)
18493#define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos)
18494#define JPEG_CONFR6_NB_Pos (4U)
18495#define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos)
18496#define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk
18497#define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos)
18498#define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos)
18499#define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos)
18500#define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos)
18501#define JPEG_CONFR6_VSF_Pos (8U)
18502#define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos)
18503#define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk
18504#define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos)
18505#define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos)
18506#define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos)
18507#define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos)
18508#define JPEG_CONFR6_HSF_Pos (12U)
18509#define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos)
18510#define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk
18511#define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos)
18512#define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos)
18513#define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos)
18514#define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos)
18516/******************** Bit definition for CONFR7 register *******************/
18517#define JPEG_CONFR7_HD_Pos (0U)
18518#define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos)
18519#define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk
18520#define JPEG_CONFR7_HA_Pos (1U)
18521#define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos)
18522#define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk
18523#define JPEG_CONFR7_QT_Pos (2U)
18524#define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos)
18525#define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk
18526#define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos)
18527#define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos)
18528#define JPEG_CONFR7_NB_Pos (4U)
18529#define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos)
18530#define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk
18531#define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos)
18532#define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos)
18533#define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos)
18534#define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos)
18535#define JPEG_CONFR7_VSF_Pos (8U)
18536#define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos)
18537#define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk
18538#define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos)
18539#define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos)
18540#define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos)
18541#define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos)
18542#define JPEG_CONFR7_HSF_Pos (12U)
18543#define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos)
18544#define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk
18545#define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos)
18546#define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos)
18547#define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos)
18548#define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos)
18550/******************** Bit definition for CR register *******************/
18551#define JPEG_CR_JCEN_Pos (0U)
18552#define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos)
18553#define JPEG_CR_JCEN JPEG_CR_JCEN_Msk
18554#define JPEG_CR_IFTIE_Pos (1U)
18555#define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos)
18556#define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk
18557#define JPEG_CR_IFNFIE_Pos (2U)
18558#define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos)
18559#define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk
18560#define JPEG_CR_OFTIE_Pos (3U)
18561#define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos)
18562#define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk
18563#define JPEG_CR_OFNEIE_Pos (4U)
18564#define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos)
18565#define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk
18566#define JPEG_CR_EOCIE_Pos (5U)
18567#define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos)
18568#define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk
18569#define JPEG_CR_HPDIE_Pos (6U)
18570#define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos)
18571#define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk
18572#define JPEG_CR_IDMAEN_Pos (11U)
18573#define JPEG_CR_IDMAEN_Msk (0x1UL << JPEG_CR_IDMAEN_Pos)
18574#define JPEG_CR_IDMAEN JPEG_CR_IDMAEN_Msk
18575#define JPEG_CR_ODMAEN_Pos (12U)
18576#define JPEG_CR_ODMAEN_Msk (0x1UL << JPEG_CR_ODMAEN_Pos)
18577#define JPEG_CR_ODMAEN JPEG_CR_ODMAEN_Msk
18578#define JPEG_CR_IFF_Pos (13U)
18579#define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos)
18580#define JPEG_CR_IFF JPEG_CR_IFF_Msk
18581#define JPEG_CR_OFF_Pos (14U)
18582#define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos)
18583#define JPEG_CR_OFF JPEG_CR_OFF_Msk
18585/******************** Bit definition for SR register *******************/
18586#define JPEG_SR_IFTF_Pos (1U)
18587#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos)
18588#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk
18589#define JPEG_SR_IFNFF_Pos (2U)
18590#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos)
18591#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk
18592#define JPEG_SR_OFTF_Pos (3U)
18593#define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos)
18594#define JPEG_SR_OFTF JPEG_SR_OFTF_Msk
18595#define JPEG_SR_OFNEF_Pos (4U)
18596#define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos)
18597#define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk
18598#define JPEG_SR_EOCF_Pos (5U)
18599#define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos)
18600#define JPEG_SR_EOCF JPEG_SR_EOCF_Msk
18601#define JPEG_SR_HPDF_Pos (6U)
18602#define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos)
18603#define JPEG_SR_HPDF JPEG_SR_HPDF_Msk
18604#define JPEG_SR_COF_Pos (7U)
18605#define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos)
18606#define JPEG_SR_COF JPEG_SR_COF_Msk
18608/******************** Bit definition for CFR register *******************/
18609#define JPEG_CFR_CEOCF_Pos (5U)
18610#define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos)
18611#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk
18612#define JPEG_CFR_CHPDF_Pos (6U)
18613#define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos)
18614#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk
18616/******************** Bit definition for DIR register ********************/
18617#define JPEG_DIR_DATAIN_Pos (0U)
18618#define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)
18619#define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk
18621/******************** Bit definition for DOR register ********************/
18622#define JPEG_DOR_DATAOUT_Pos (0U)
18623#define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos)
18624#define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk
18626/******************************************************************************/
18627/* */
18628/* MDIOS */
18629/* */
18630/******************************************************************************/
18631/******************** Bit definition for MDIOS_CR register *******************/
18632#define MDIOS_CR_EN_Pos (0U)
18633#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos)
18634#define MDIOS_CR_EN MDIOS_CR_EN_Msk
18635#define MDIOS_CR_WRIE_Pos (1U)
18636#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos)
18637#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk
18638#define MDIOS_CR_RDIE_Pos (2U)
18639#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos)
18640#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk
18641#define MDIOS_CR_EIE_Pos (3U)
18642#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos)
18643#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk
18644#define MDIOS_CR_DPC_Pos (7U)
18645#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos)
18646#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk
18647#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
18648#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)
18649#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk
18650#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)
18651#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)
18652#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)
18653#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)
18654#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)
18656/******************** Bit definition for MDIOS_WRFR register *******************/
18657#define MDIOS_WRFR_WRF_Pos (0U)
18658#define MDIOS_WRFR_WRF_Msk (0xFFFFFFFFUL << MDIOS_WRFR_WRF_Pos)
18659#define MDIOS_WRFR_WRF MDIOS_WRFR_WRF_Msk
18661/******************** Bit definition for MDIOS_CWRFR register *******************/
18662#define MDIOS_CWRFR_CWRF_Pos (0U)
18663#define MDIOS_CWRFR_CWRF_Msk (0xFFFFFFFFUL << MDIOS_CWRFR_CWRF_Pos)
18664#define MDIOS_CWRFR_CWRF MDIOS_CWRFR_CWRF_Msk
18666/******************** Bit definition for MDIOS_RDFR register *******************/
18667#define MDIOS_RDFR_RDF_Pos (0U)
18668#define MDIOS_RDFR_RDF_Msk (0xFFFFFFFFUL << MDIOS_RDFR_RDF_Pos)
18669#define MDIOS_RDFR_RDF MDIOS_RDFR_RDF_Msk
18671/******************** Bit definition for MDIOS_CRDFR register *******************/
18672#define MDIOS_CRDFR_CRDF_Pos (0U)
18673#define MDIOS_CRDFR_CRDF_Msk (0xFFFFFFFFUL << MDIOS_CRDFR_CRDF_Pos)
18674#define MDIOS_CRDFR_CRDF MDIOS_CRDFR_CRDF_Msk
18676/******************** Bit definition for MDIOS_SR register *******************/
18677#define MDIOS_SR_PERF_Pos (0U)
18678#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos)
18679#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk
18680#define MDIOS_SR_SERF_Pos (1U)
18681#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos)
18682#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk
18683#define MDIOS_SR_TERF_Pos (2U)
18684#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos)
18685#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk
18687/******************** Bit definition for MDIOS_CLRFR register *******************/
18688#define MDIOS_CLRFR_CPERF_Pos (0U)
18689#define MDIOS_CLRFR_CPERF_Msk (0x1UL << MDIOS_CLRFR_CPERF_Pos)
18690#define MDIOS_CLRFR_CPERF MDIOS_CLRFR_CPERF_Msk
18691#define MDIOS_CLRFR_CSERF_Pos (1U)
18692#define MDIOS_CLRFR_CSERF_Msk (0x1UL << MDIOS_CLRFR_CSERF_Pos)
18693#define MDIOS_CLRFR_CSERF MDIOS_CLRFR_CSERF_Msk
18694#define MDIOS_CLRFR_CTERF_Pos (2U)
18695#define MDIOS_CLRFR_CTERF_Msk (0x1UL << MDIOS_CLRFR_CTERF_Pos)
18696#define MDIOS_CLRFR_CTERF MDIOS_CLRFR_CTERF_Msk
18698/******************************************************************************/
18699/* */
18700/* Display Serial Interface (DSI) */
18701/* */
18702/******************************************************************************/
18703/******************* Bit definition for DSI_VR register *****************/
18704#define DSI_VR_Pos (1U)
18705#define DSI_VR_Msk (0x18999815UL << DSI_VR_Pos)
18706#define DSI_VR DSI_VR_Msk
18708/******************* Bit definition for DSI_CR register *****************/
18709#define DSI_CR_EN_Pos (0U)
18710#define DSI_CR_EN_Msk (0x1UL << DSI_CR_EN_Pos)
18711#define DSI_CR_EN DSI_CR_EN_Msk
18713/******************* Bit definition for DSI_CCR register ****************/
18714#define DSI_CCR_TXECKDIV_Pos (0U)
18715#define DSI_CCR_TXECKDIV_Msk (0xFFUL << DSI_CCR_TXECKDIV_Pos)
18716#define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk
18717#define DSI_CCR_TXECKDIV0_Pos (0U)
18718#define DSI_CCR_TXECKDIV0_Msk (0x1UL << DSI_CCR_TXECKDIV0_Pos)
18719#define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
18720#define DSI_CCR_TXECKDIV1_Pos (1U)
18721#define DSI_CCR_TXECKDIV1_Msk (0x1UL << DSI_CCR_TXECKDIV1_Pos)
18722#define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
18723#define DSI_CCR_TXECKDIV2_Pos (2U)
18724#define DSI_CCR_TXECKDIV2_Msk (0x1UL << DSI_CCR_TXECKDIV2_Pos)
18725#define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
18726#define DSI_CCR_TXECKDIV3_Pos (3U)
18727#define DSI_CCR_TXECKDIV3_Msk (0x1UL << DSI_CCR_TXECKDIV3_Pos)
18728#define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
18729#define DSI_CCR_TXECKDIV4_Pos (4U)
18730#define DSI_CCR_TXECKDIV4_Msk (0x1UL << DSI_CCR_TXECKDIV4_Pos)
18731#define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
18732#define DSI_CCR_TXECKDIV5_Pos (5U)
18733#define DSI_CCR_TXECKDIV5_Msk (0x1UL << DSI_CCR_TXECKDIV5_Pos)
18734#define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
18735#define DSI_CCR_TXECKDIV6_Pos (6U)
18736#define DSI_CCR_TXECKDIV6_Msk (0x1UL << DSI_CCR_TXECKDIV6_Pos)
18737#define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
18738#define DSI_CCR_TXECKDIV7_Pos (7U)
18739#define DSI_CCR_TXECKDIV7_Msk (0x1UL << DSI_CCR_TXECKDIV7_Pos)
18740#define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
18741
18742#define DSI_CCR_TOCKDIV_Pos (8U)
18743#define DSI_CCR_TOCKDIV_Msk (0xFFUL << DSI_CCR_TOCKDIV_Pos)
18744#define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk
18745#define DSI_CCR_TOCKDIV0_Pos (8U)
18746#define DSI_CCR_TOCKDIV0_Msk (0x1UL << DSI_CCR_TOCKDIV0_Pos)
18747#define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
18748#define DSI_CCR_TOCKDIV1_Pos (9U)
18749#define DSI_CCR_TOCKDIV1_Msk (0x1UL << DSI_CCR_TOCKDIV1_Pos)
18750#define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
18751#define DSI_CCR_TOCKDIV2_Pos (10U)
18752#define DSI_CCR_TOCKDIV2_Msk (0x1UL << DSI_CCR_TOCKDIV2_Pos)
18753#define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
18754#define DSI_CCR_TOCKDIV3_Pos (11U)
18755#define DSI_CCR_TOCKDIV3_Msk (0x1UL << DSI_CCR_TOCKDIV3_Pos)
18756#define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
18757#define DSI_CCR_TOCKDIV4_Pos (12U)
18758#define DSI_CCR_TOCKDIV4_Msk (0x1UL << DSI_CCR_TOCKDIV4_Pos)
18759#define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
18760#define DSI_CCR_TOCKDIV5_Pos (13U)
18761#define DSI_CCR_TOCKDIV5_Msk (0x1UL << DSI_CCR_TOCKDIV5_Pos)
18762#define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
18763#define DSI_CCR_TOCKDIV6_Pos (14U)
18764#define DSI_CCR_TOCKDIV6_Msk (0x1UL << DSI_CCR_TOCKDIV6_Pos)
18765#define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
18766#define DSI_CCR_TOCKDIV7_Pos (15U)
18767#define DSI_CCR_TOCKDIV7_Msk (0x1UL << DSI_CCR_TOCKDIV7_Pos)
18768#define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
18769
18770/******************* Bit definition for DSI_LVCIDR register *************/
18771#define DSI_LVCIDR_VCID_Pos (0U)
18772#define DSI_LVCIDR_VCID_Msk (0x3UL << DSI_LVCIDR_VCID_Pos)
18773#define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk
18774#define DSI_LVCIDR_VCID0_Pos (0U)
18775#define DSI_LVCIDR_VCID0_Msk (0x1UL << DSI_LVCIDR_VCID0_Pos)
18776#define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
18777#define DSI_LVCIDR_VCID1_Pos (1U)
18778#define DSI_LVCIDR_VCID1_Msk (0x1UL << DSI_LVCIDR_VCID1_Pos)
18779#define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
18780
18781/******************* Bit definition for DSI_LCOLCR register *************/
18782#define DSI_LCOLCR_COLC_Pos (0U)
18783#define DSI_LCOLCR_COLC_Msk (0xFUL << DSI_LCOLCR_COLC_Pos)
18784#define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk
18785#define DSI_LCOLCR_COLC0_Pos (0U)
18786#define DSI_LCOLCR_COLC0_Msk (0x1UL << DSI_LCOLCR_COLC0_Pos)
18787#define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
18788#define DSI_LCOLCR_COLC1_Pos (5U)
18789#define DSI_LCOLCR_COLC1_Msk (0x1UL << DSI_LCOLCR_COLC1_Pos)
18790#define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
18791#define DSI_LCOLCR_COLC2_Pos (6U)
18792#define DSI_LCOLCR_COLC2_Msk (0x1UL << DSI_LCOLCR_COLC2_Pos)
18793#define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
18794#define DSI_LCOLCR_COLC3_Pos (7U)
18795#define DSI_LCOLCR_COLC3_Msk (0x1UL << DSI_LCOLCR_COLC3_Pos)
18796#define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
18797
18798#define DSI_LCOLCR_LPE_Pos (8U)
18799#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos)
18800#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk
18802/******************* Bit definition for DSI_LPCR register ***************/
18803#define DSI_LPCR_DEP_Pos (0U)
18804#define DSI_LPCR_DEP_Msk (0x1UL << DSI_LPCR_DEP_Pos)
18805#define DSI_LPCR_DEP DSI_LPCR_DEP_Msk
18806#define DSI_LPCR_VSP_Pos (1U)
18807#define DSI_LPCR_VSP_Msk (0x1UL << DSI_LPCR_VSP_Pos)
18808#define DSI_LPCR_VSP DSI_LPCR_VSP_Msk
18809#define DSI_LPCR_HSP_Pos (2U)
18810#define DSI_LPCR_HSP_Msk (0x1UL << DSI_LPCR_HSP_Pos)
18811#define DSI_LPCR_HSP DSI_LPCR_HSP_Msk
18813/******************* Bit definition for DSI_LPMCR register **************/
18814#define DSI_LPMCR_VLPSIZE_Pos (0U)
18815#define DSI_LPMCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCR_VLPSIZE_Pos)
18816#define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk
18817#define DSI_LPMCR_VLPSIZE0_Pos (0U)
18818#define DSI_LPMCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCR_VLPSIZE0_Pos)
18819#define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
18820#define DSI_LPMCR_VLPSIZE1_Pos (1U)
18821#define DSI_LPMCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCR_VLPSIZE1_Pos)
18822#define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
18823#define DSI_LPMCR_VLPSIZE2_Pos (2U)
18824#define DSI_LPMCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCR_VLPSIZE2_Pos)
18825#define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
18826#define DSI_LPMCR_VLPSIZE3_Pos (3U)
18827#define DSI_LPMCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCR_VLPSIZE3_Pos)
18828#define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
18829#define DSI_LPMCR_VLPSIZE4_Pos (4U)
18830#define DSI_LPMCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCR_VLPSIZE4_Pos)
18831#define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
18832#define DSI_LPMCR_VLPSIZE5_Pos (5U)
18833#define DSI_LPMCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCR_VLPSIZE5_Pos)
18834#define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
18835#define DSI_LPMCR_VLPSIZE6_Pos (6U)
18836#define DSI_LPMCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCR_VLPSIZE6_Pos)
18837#define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
18838#define DSI_LPMCR_VLPSIZE7_Pos (7U)
18839#define DSI_LPMCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCR_VLPSIZE7_Pos)
18840#define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
18841
18842#define DSI_LPMCR_LPSIZE_Pos (16U)
18843#define DSI_LPMCR_LPSIZE_Msk (0xFFUL << DSI_LPMCR_LPSIZE_Pos)
18844#define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk
18845#define DSI_LPMCR_LPSIZE0_Pos (16U)
18846#define DSI_LPMCR_LPSIZE0_Msk (0x1UL << DSI_LPMCR_LPSIZE0_Pos)
18847#define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
18848#define DSI_LPMCR_LPSIZE1_Pos (17U)
18849#define DSI_LPMCR_LPSIZE1_Msk (0x1UL << DSI_LPMCR_LPSIZE1_Pos)
18850#define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
18851#define DSI_LPMCR_LPSIZE2_Pos (18U)
18852#define DSI_LPMCR_LPSIZE2_Msk (0x1UL << DSI_LPMCR_LPSIZE2_Pos)
18853#define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
18854#define DSI_LPMCR_LPSIZE3_Pos (19U)
18855#define DSI_LPMCR_LPSIZE3_Msk (0x1UL << DSI_LPMCR_LPSIZE3_Pos)
18856#define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
18857#define DSI_LPMCR_LPSIZE4_Pos (20U)
18858#define DSI_LPMCR_LPSIZE4_Msk (0x1UL << DSI_LPMCR_LPSIZE4_Pos)
18859#define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
18860#define DSI_LPMCR_LPSIZE5_Pos (21U)
18861#define DSI_LPMCR_LPSIZE5_Msk (0x1UL << DSI_LPMCR_LPSIZE5_Pos)
18862#define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
18863#define DSI_LPMCR_LPSIZE6_Pos (22U)
18864#define DSI_LPMCR_LPSIZE6_Msk (0x1UL << DSI_LPMCR_LPSIZE6_Pos)
18865#define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
18866#define DSI_LPMCR_LPSIZE7_Pos (23U)
18867#define DSI_LPMCR_LPSIZE7_Msk (0x1UL << DSI_LPMCR_LPSIZE7_Pos)
18868#define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
18869
18870/******************* Bit definition for DSI_PCR register ****************/
18871#define DSI_PCR_ETTXE_Pos (0U)
18872#define DSI_PCR_ETTXE_Msk (0x1UL << DSI_PCR_ETTXE_Pos)
18873#define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk
18874#define DSI_PCR_ETRXE_Pos (1U)
18875#define DSI_PCR_ETRXE_Msk (0x1UL << DSI_PCR_ETRXE_Pos)
18876#define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk
18877#define DSI_PCR_BTAE_Pos (2U)
18878#define DSI_PCR_BTAE_Msk (0x1UL << DSI_PCR_BTAE_Pos)
18879#define DSI_PCR_BTAE DSI_PCR_BTAE_Msk
18880#define DSI_PCR_ECCRXE_Pos (3U)
18881#define DSI_PCR_ECCRXE_Msk (0x1UL << DSI_PCR_ECCRXE_Pos)
18882#define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk
18883#define DSI_PCR_CRCRXE_Pos (4U)
18884#define DSI_PCR_CRCRXE_Msk (0x1UL << DSI_PCR_CRCRXE_Pos)
18885#define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk
18887/******************* Bit definition for DSI_GVCIDR register *************/
18888#define DSI_GVCIDR_VCID_Pos (0U)
18889#define DSI_GVCIDR_VCID_Msk (0x3UL << DSI_GVCIDR_VCID_Pos)
18890#define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk
18891#define DSI_GVCIDR_VCID0_Pos (0U)
18892#define DSI_GVCIDR_VCID0_Msk (0x1UL << DSI_GVCIDR_VCID0_Pos)
18893#define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
18894#define DSI_GVCIDR_VCID1_Pos (1U)
18895#define DSI_GVCIDR_VCID1_Msk (0x1UL << DSI_GVCIDR_VCID1_Pos)
18896#define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
18897
18898/******************* Bit definition for DSI_MCR register ****************/
18899#define DSI_MCR_CMDM_Pos (0U)
18900#define DSI_MCR_CMDM_Msk (0x1UL << DSI_MCR_CMDM_Pos)
18901#define DSI_MCR_CMDM DSI_MCR_CMDM_Msk
18903/******************* Bit definition for DSI_VMCR register ***************/
18904#define DSI_VMCR_VMT_Pos (0U)
18905#define DSI_VMCR_VMT_Msk (0x3UL << DSI_VMCR_VMT_Pos)
18906#define DSI_VMCR_VMT DSI_VMCR_VMT_Msk
18907#define DSI_VMCR_VMT0_Pos (0U)
18908#define DSI_VMCR_VMT0_Msk (0x1UL << DSI_VMCR_VMT0_Pos)
18909#define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
18910#define DSI_VMCR_VMT1_Pos (1U)
18911#define DSI_VMCR_VMT1_Msk (0x1UL << DSI_VMCR_VMT1_Pos)
18912#define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
18913
18914#define DSI_VMCR_LPVSAE_Pos (8U)
18915#define DSI_VMCR_LPVSAE_Msk (0x1UL << DSI_VMCR_LPVSAE_Pos)
18916#define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk
18917#define DSI_VMCR_LPVBPE_Pos (9U)
18918#define DSI_VMCR_LPVBPE_Msk (0x1UL << DSI_VMCR_LPVBPE_Pos)
18919#define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk
18920#define DSI_VMCR_LPVFPE_Pos (10U)
18921#define DSI_VMCR_LPVFPE_Msk (0x1UL << DSI_VMCR_LPVFPE_Pos)
18922#define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk
18923#define DSI_VMCR_LPVAE_Pos (11U)
18924#define DSI_VMCR_LPVAE_Msk (0x1UL << DSI_VMCR_LPVAE_Pos)
18925#define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk
18926#define DSI_VMCR_LPHBPE_Pos (12U)
18927#define DSI_VMCR_LPHBPE_Msk (0x1UL << DSI_VMCR_LPHBPE_Pos)
18928#define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk
18929#define DSI_VMCR_LPHFPE_Pos (13U)
18930#define DSI_VMCR_LPHFPE_Msk (0x1UL << DSI_VMCR_LPHFPE_Pos)
18931#define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk
18932#define DSI_VMCR_FBTAAE_Pos (14U)
18933#define DSI_VMCR_FBTAAE_Msk (0x1UL << DSI_VMCR_FBTAAE_Pos)
18934#define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk
18935#define DSI_VMCR_LPCE_Pos (15U)
18936#define DSI_VMCR_LPCE_Msk (0x1UL << DSI_VMCR_LPCE_Pos)
18937#define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk
18938#define DSI_VMCR_PGE_Pos (16U)
18939#define DSI_VMCR_PGE_Msk (0x1UL << DSI_VMCR_PGE_Pos)
18940#define DSI_VMCR_PGE DSI_VMCR_PGE_Msk
18941#define DSI_VMCR_PGM_Pos (20U)
18942#define DSI_VMCR_PGM_Msk (0x1UL << DSI_VMCR_PGM_Pos)
18943#define DSI_VMCR_PGM DSI_VMCR_PGM_Msk
18944#define DSI_VMCR_PGO_Pos (24U)
18945#define DSI_VMCR_PGO_Msk (0x1UL << DSI_VMCR_PGO_Pos)
18946#define DSI_VMCR_PGO DSI_VMCR_PGO_Msk
18948/******************* Bit definition for DSI_VPCR register ***************/
18949#define DSI_VPCR_VPSIZE_Pos (0U)
18950#define DSI_VPCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCR_VPSIZE_Pos)
18951#define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk
18952#define DSI_VPCR_VPSIZE0_Pos (0U)
18953#define DSI_VPCR_VPSIZE0_Msk (0x1UL << DSI_VPCR_VPSIZE0_Pos)
18954#define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
18955#define DSI_VPCR_VPSIZE1_Pos (1U)
18956#define DSI_VPCR_VPSIZE1_Msk (0x1UL << DSI_VPCR_VPSIZE1_Pos)
18957#define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
18958#define DSI_VPCR_VPSIZE2_Pos (2U)
18959#define DSI_VPCR_VPSIZE2_Msk (0x1UL << DSI_VPCR_VPSIZE2_Pos)
18960#define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
18961#define DSI_VPCR_VPSIZE3_Pos (3U)
18962#define DSI_VPCR_VPSIZE3_Msk (0x1UL << DSI_VPCR_VPSIZE3_Pos)
18963#define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
18964#define DSI_VPCR_VPSIZE4_Pos (4U)
18965#define DSI_VPCR_VPSIZE4_Msk (0x1UL << DSI_VPCR_VPSIZE4_Pos)
18966#define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
18967#define DSI_VPCR_VPSIZE5_Pos (5U)
18968#define DSI_VPCR_VPSIZE5_Msk (0x1UL << DSI_VPCR_VPSIZE5_Pos)
18969#define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
18970#define DSI_VPCR_VPSIZE6_Pos (6U)
18971#define DSI_VPCR_VPSIZE6_Msk (0x1UL << DSI_VPCR_VPSIZE6_Pos)
18972#define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
18973#define DSI_VPCR_VPSIZE7_Pos (7U)
18974#define DSI_VPCR_VPSIZE7_Msk (0x1UL << DSI_VPCR_VPSIZE7_Pos)
18975#define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
18976#define DSI_VPCR_VPSIZE8_Pos (8U)
18977#define DSI_VPCR_VPSIZE8_Msk (0x1UL << DSI_VPCR_VPSIZE8_Pos)
18978#define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
18979#define DSI_VPCR_VPSIZE9_Pos (9U)
18980#define DSI_VPCR_VPSIZE9_Msk (0x1UL << DSI_VPCR_VPSIZE9_Pos)
18981#define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
18982#define DSI_VPCR_VPSIZE10_Pos (10U)
18983#define DSI_VPCR_VPSIZE10_Msk (0x1UL << DSI_VPCR_VPSIZE10_Pos)
18984#define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
18985#define DSI_VPCR_VPSIZE11_Pos (11U)
18986#define DSI_VPCR_VPSIZE11_Msk (0x1UL << DSI_VPCR_VPSIZE11_Pos)
18987#define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
18988#define DSI_VPCR_VPSIZE12_Pos (12U)
18989#define DSI_VPCR_VPSIZE12_Msk (0x1UL << DSI_VPCR_VPSIZE12_Pos)
18990#define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
18991#define DSI_VPCR_VPSIZE13_Pos (13U)
18992#define DSI_VPCR_VPSIZE13_Msk (0x1UL << DSI_VPCR_VPSIZE13_Pos)
18993#define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
18994
18995/******************* Bit definition for DSI_VCCR register ***************/
18996#define DSI_VCCR_NUMC_Pos (0U)
18997#define DSI_VCCR_NUMC_Msk (0x1FFFUL << DSI_VCCR_NUMC_Pos)
18998#define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk
18999#define DSI_VCCR_NUMC0_Pos (0U)
19000#define DSI_VCCR_NUMC0_Msk (0x1UL << DSI_VCCR_NUMC0_Pos)
19001#define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
19002#define DSI_VCCR_NUMC1_Pos (1U)
19003#define DSI_VCCR_NUMC1_Msk (0x1UL << DSI_VCCR_NUMC1_Pos)
19004#define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
19005#define DSI_VCCR_NUMC2_Pos (2U)
19006#define DSI_VCCR_NUMC2_Msk (0x1UL << DSI_VCCR_NUMC2_Pos)
19007#define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
19008#define DSI_VCCR_NUMC3_Pos (3U)
19009#define DSI_VCCR_NUMC3_Msk (0x1UL << DSI_VCCR_NUMC3_Pos)
19010#define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
19011#define DSI_VCCR_NUMC4_Pos (4U)
19012#define DSI_VCCR_NUMC4_Msk (0x1UL << DSI_VCCR_NUMC4_Pos)
19013#define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
19014#define DSI_VCCR_NUMC5_Pos (5U)
19015#define DSI_VCCR_NUMC5_Msk (0x1UL << DSI_VCCR_NUMC5_Pos)
19016#define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
19017#define DSI_VCCR_NUMC6_Pos (6U)
19018#define DSI_VCCR_NUMC6_Msk (0x1UL << DSI_VCCR_NUMC6_Pos)
19019#define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
19020#define DSI_VCCR_NUMC7_Pos (7U)
19021#define DSI_VCCR_NUMC7_Msk (0x1UL << DSI_VCCR_NUMC7_Pos)
19022#define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
19023#define DSI_VCCR_NUMC8_Pos (8U)
19024#define DSI_VCCR_NUMC8_Msk (0x1UL << DSI_VCCR_NUMC8_Pos)
19025#define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
19026#define DSI_VCCR_NUMC9_Pos (9U)
19027#define DSI_VCCR_NUMC9_Msk (0x1UL << DSI_VCCR_NUMC9_Pos)
19028#define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
19029#define DSI_VCCR_NUMC10_Pos (10U)
19030#define DSI_VCCR_NUMC10_Msk (0x1UL << DSI_VCCR_NUMC10_Pos)
19031#define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
19032#define DSI_VCCR_NUMC11_Pos (11U)
19033#define DSI_VCCR_NUMC11_Msk (0x1UL << DSI_VCCR_NUMC11_Pos)
19034#define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
19035#define DSI_VCCR_NUMC12_Pos (12U)
19036#define DSI_VCCR_NUMC12_Msk (0x1UL << DSI_VCCR_NUMC12_Pos)
19037#define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
19038
19039/******************* Bit definition for DSI_VNPCR register **************/
19040#define DSI_VNPCR_NPSIZE_Pos (0U)
19041#define DSI_VNPCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos)
19042#define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk
19043#define DSI_VNPCR_NPSIZE0_Pos (0U)
19044#define DSI_VNPCR_NPSIZE0_Msk (0x1UL << DSI_VNPCR_NPSIZE0_Pos)
19045#define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
19046#define DSI_VNPCR_NPSIZE1_Pos (1U)
19047#define DSI_VNPCR_NPSIZE1_Msk (0x1UL << DSI_VNPCR_NPSIZE1_Pos)
19048#define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
19049#define DSI_VNPCR_NPSIZE2_Pos (2U)
19050#define DSI_VNPCR_NPSIZE2_Msk (0x1UL << DSI_VNPCR_NPSIZE2_Pos)
19051#define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
19052#define DSI_VNPCR_NPSIZE3_Pos (3U)
19053#define DSI_VNPCR_NPSIZE3_Msk (0x1UL << DSI_VNPCR_NPSIZE3_Pos)
19054#define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
19055#define DSI_VNPCR_NPSIZE4_Pos (4U)
19056#define DSI_VNPCR_NPSIZE4_Msk (0x1UL << DSI_VNPCR_NPSIZE4_Pos)
19057#define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
19058#define DSI_VNPCR_NPSIZE5_Pos (5U)
19059#define DSI_VNPCR_NPSIZE5_Msk (0x1UL << DSI_VNPCR_NPSIZE5_Pos)
19060#define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
19061#define DSI_VNPCR_NPSIZE6_Pos (6U)
19062#define DSI_VNPCR_NPSIZE6_Msk (0x1UL << DSI_VNPCR_NPSIZE6_Pos)
19063#define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
19064#define DSI_VNPCR_NPSIZE7_Pos (7U)
19065#define DSI_VNPCR_NPSIZE7_Msk (0x1UL << DSI_VNPCR_NPSIZE7_Pos)
19066#define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
19067#define DSI_VNPCR_NPSIZE8_Pos (8U)
19068#define DSI_VNPCR_NPSIZE8_Msk (0x1UL << DSI_VNPCR_NPSIZE8_Pos)
19069#define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
19070#define DSI_VNPCR_NPSIZE9_Pos (9U)
19071#define DSI_VNPCR_NPSIZE9_Msk (0x1UL << DSI_VNPCR_NPSIZE9_Pos)
19072#define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
19073#define DSI_VNPCR_NPSIZE10_Pos (10U)
19074#define DSI_VNPCR_NPSIZE10_Msk (0x1UL << DSI_VNPCR_NPSIZE10_Pos)
19075#define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
19076#define DSI_VNPCR_NPSIZE11_Pos (11U)
19077#define DSI_VNPCR_NPSIZE11_Msk (0x1UL << DSI_VNPCR_NPSIZE11_Pos)
19078#define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
19079#define DSI_VNPCR_NPSIZE12_Pos (12U)
19080#define DSI_VNPCR_NPSIZE12_Msk (0x1UL << DSI_VNPCR_NPSIZE12_Pos)
19081#define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
19082
19083/******************* Bit definition for DSI_VHSACR register *************/
19084#define DSI_VHSACR_HSA_Pos (0U)
19085#define DSI_VHSACR_HSA_Msk (0xFFFUL << DSI_VHSACR_HSA_Pos)
19086#define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk
19087#define DSI_VHSACR_HSA0_Pos (0U)
19088#define DSI_VHSACR_HSA0_Msk (0x1UL << DSI_VHSACR_HSA0_Pos)
19089#define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
19090#define DSI_VHSACR_HSA1_Pos (1U)
19091#define DSI_VHSACR_HSA1_Msk (0x1UL << DSI_VHSACR_HSA1_Pos)
19092#define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
19093#define DSI_VHSACR_HSA2_Pos (2U)
19094#define DSI_VHSACR_HSA2_Msk (0x1UL << DSI_VHSACR_HSA2_Pos)
19095#define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
19096#define DSI_VHSACR_HSA3_Pos (3U)
19097#define DSI_VHSACR_HSA3_Msk (0x1UL << DSI_VHSACR_HSA3_Pos)
19098#define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
19099#define DSI_VHSACR_HSA4_Pos (4U)
19100#define DSI_VHSACR_HSA4_Msk (0x1UL << DSI_VHSACR_HSA4_Pos)
19101#define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
19102#define DSI_VHSACR_HSA5_Pos (5U)
19103#define DSI_VHSACR_HSA5_Msk (0x1UL << DSI_VHSACR_HSA5_Pos)
19104#define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
19105#define DSI_VHSACR_HSA6_Pos (6U)
19106#define DSI_VHSACR_HSA6_Msk (0x1UL << DSI_VHSACR_HSA6_Pos)
19107#define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
19108#define DSI_VHSACR_HSA7_Pos (7U)
19109#define DSI_VHSACR_HSA7_Msk (0x1UL << DSI_VHSACR_HSA7_Pos)
19110#define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
19111#define DSI_VHSACR_HSA8_Pos (8U)
19112#define DSI_VHSACR_HSA8_Msk (0x1UL << DSI_VHSACR_HSA8_Pos)
19113#define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
19114#define DSI_VHSACR_HSA9_Pos (9U)
19115#define DSI_VHSACR_HSA9_Msk (0x1UL << DSI_VHSACR_HSA9_Pos)
19116#define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
19117#define DSI_VHSACR_HSA10_Pos (10U)
19118#define DSI_VHSACR_HSA10_Msk (0x1UL << DSI_VHSACR_HSA10_Pos)
19119#define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
19120#define DSI_VHSACR_HSA11_Pos (11U)
19121#define DSI_VHSACR_HSA11_Msk (0x1UL << DSI_VHSACR_HSA11_Pos)
19122#define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
19123
19124/******************* Bit definition for DSI_VHBPCR register *************/
19125#define DSI_VHBPCR_HBP_Pos (0U)
19126#define DSI_VHBPCR_HBP_Msk (0xFFFUL << DSI_VHBPCR_HBP_Pos)
19127#define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk
19128#define DSI_VHBPCR_HBP0_Pos (0U)
19129#define DSI_VHBPCR_HBP0_Msk (0x1UL << DSI_VHBPCR_HBP0_Pos)
19130#define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
19131#define DSI_VHBPCR_HBP1_Pos (1U)
19132#define DSI_VHBPCR_HBP1_Msk (0x1UL << DSI_VHBPCR_HBP1_Pos)
19133#define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
19134#define DSI_VHBPCR_HBP2_Pos (2U)
19135#define DSI_VHBPCR_HBP2_Msk (0x1UL << DSI_VHBPCR_HBP2_Pos)
19136#define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
19137#define DSI_VHBPCR_HBP3_Pos (3U)
19138#define DSI_VHBPCR_HBP3_Msk (0x1UL << DSI_VHBPCR_HBP3_Pos)
19139#define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
19140#define DSI_VHBPCR_HBP4_Pos (4U)
19141#define DSI_VHBPCR_HBP4_Msk (0x1UL << DSI_VHBPCR_HBP4_Pos)
19142#define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
19143#define DSI_VHBPCR_HBP5_Pos (5U)
19144#define DSI_VHBPCR_HBP5_Msk (0x1UL << DSI_VHBPCR_HBP5_Pos)
19145#define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
19146#define DSI_VHBPCR_HBP6_Pos (6U)
19147#define DSI_VHBPCR_HBP6_Msk (0x1UL << DSI_VHBPCR_HBP6_Pos)
19148#define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
19149#define DSI_VHBPCR_HBP7_Pos (7U)
19150#define DSI_VHBPCR_HBP7_Msk (0x1UL << DSI_VHBPCR_HBP7_Pos)
19151#define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
19152#define DSI_VHBPCR_HBP8_Pos (8U)
19153#define DSI_VHBPCR_HBP8_Msk (0x1UL << DSI_VHBPCR_HBP8_Pos)
19154#define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
19155#define DSI_VHBPCR_HBP9_Pos (9U)
19156#define DSI_VHBPCR_HBP9_Msk (0x1UL << DSI_VHBPCR_HBP9_Pos)
19157#define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
19158#define DSI_VHBPCR_HBP10_Pos (10U)
19159#define DSI_VHBPCR_HBP10_Msk (0x1UL << DSI_VHBPCR_HBP10_Pos)
19160#define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
19161#define DSI_VHBPCR_HBP11_Pos (11U)
19162#define DSI_VHBPCR_HBP11_Msk (0x1UL << DSI_VHBPCR_HBP11_Pos)
19163#define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
19164
19165/******************* Bit definition for DSI_VLCR register ***************/
19166#define DSI_VLCR_HLINE_Pos (0U)
19167#define DSI_VLCR_HLINE_Msk (0x7FFFUL << DSI_VLCR_HLINE_Pos)
19168#define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk
19169#define DSI_VLCR_HLINE0_Pos (0U)
19170#define DSI_VLCR_HLINE0_Msk (0x1UL << DSI_VLCR_HLINE0_Pos)
19171#define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
19172#define DSI_VLCR_HLINE1_Pos (1U)
19173#define DSI_VLCR_HLINE1_Msk (0x1UL << DSI_VLCR_HLINE1_Pos)
19174#define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
19175#define DSI_VLCR_HLINE2_Pos (2U)
19176#define DSI_VLCR_HLINE2_Msk (0x1UL << DSI_VLCR_HLINE2_Pos)
19177#define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
19178#define DSI_VLCR_HLINE3_Pos (3U)
19179#define DSI_VLCR_HLINE3_Msk (0x1UL << DSI_VLCR_HLINE3_Pos)
19180#define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
19181#define DSI_VLCR_HLINE4_Pos (4U)
19182#define DSI_VLCR_HLINE4_Msk (0x1UL << DSI_VLCR_HLINE4_Pos)
19183#define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
19184#define DSI_VLCR_HLINE5_Pos (5U)
19185#define DSI_VLCR_HLINE5_Msk (0x1UL << DSI_VLCR_HLINE5_Pos)
19186#define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
19187#define DSI_VLCR_HLINE6_Pos (6U)
19188#define DSI_VLCR_HLINE6_Msk (0x1UL << DSI_VLCR_HLINE6_Pos)
19189#define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
19190#define DSI_VLCR_HLINE7_Pos (7U)
19191#define DSI_VLCR_HLINE7_Msk (0x1UL << DSI_VLCR_HLINE7_Pos)
19192#define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
19193#define DSI_VLCR_HLINE8_Pos (8U)
19194#define DSI_VLCR_HLINE8_Msk (0x1UL << DSI_VLCR_HLINE8_Pos)
19195#define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
19196#define DSI_VLCR_HLINE9_Pos (9U)
19197#define DSI_VLCR_HLINE9_Msk (0x1UL << DSI_VLCR_HLINE9_Pos)
19198#define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
19199#define DSI_VLCR_HLINE10_Pos (10U)
19200#define DSI_VLCR_HLINE10_Msk (0x1UL << DSI_VLCR_HLINE10_Pos)
19201#define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
19202#define DSI_VLCR_HLINE11_Pos (11U)
19203#define DSI_VLCR_HLINE11_Msk (0x1UL << DSI_VLCR_HLINE11_Pos)
19204#define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
19205#define DSI_VLCR_HLINE12_Pos (12U)
19206#define DSI_VLCR_HLINE12_Msk (0x1UL << DSI_VLCR_HLINE12_Pos)
19207#define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
19208#define DSI_VLCR_HLINE13_Pos (13U)
19209#define DSI_VLCR_HLINE13_Msk (0x1UL << DSI_VLCR_HLINE13_Pos)
19210#define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
19211#define DSI_VLCR_HLINE14_Pos (14U)
19212#define DSI_VLCR_HLINE14_Msk (0x1UL << DSI_VLCR_HLINE14_Pos)
19213#define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
19214
19215/******************* Bit definition for DSI_VVSACR register *************/
19216#define DSI_VVSACR_VSA_Pos (0U)
19217#define DSI_VVSACR_VSA_Msk (0x3FFUL << DSI_VVSACR_VSA_Pos)
19218#define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk
19219#define DSI_VVSACR_VSA0_Pos (0U)
19220#define DSI_VVSACR_VSA0_Msk (0x1UL << DSI_VVSACR_VSA0_Pos)
19221#define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
19222#define DSI_VVSACR_VSA1_Pos (1U)
19223#define DSI_VVSACR_VSA1_Msk (0x1UL << DSI_VVSACR_VSA1_Pos)
19224#define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
19225#define DSI_VVSACR_VSA2_Pos (2U)
19226#define DSI_VVSACR_VSA2_Msk (0x1UL << DSI_VVSACR_VSA2_Pos)
19227#define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
19228#define DSI_VVSACR_VSA3_Pos (3U)
19229#define DSI_VVSACR_VSA3_Msk (0x1UL << DSI_VVSACR_VSA3_Pos)
19230#define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
19231#define DSI_VVSACR_VSA4_Pos (4U)
19232#define DSI_VVSACR_VSA4_Msk (0x1UL << DSI_VVSACR_VSA4_Pos)
19233#define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
19234#define DSI_VVSACR_VSA5_Pos (5U)
19235#define DSI_VVSACR_VSA5_Msk (0x1UL << DSI_VVSACR_VSA5_Pos)
19236#define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
19237#define DSI_VVSACR_VSA6_Pos (6U)
19238#define DSI_VVSACR_VSA6_Msk (0x1UL << DSI_VVSACR_VSA6_Pos)
19239#define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
19240#define DSI_VVSACR_VSA7_Pos (7U)
19241#define DSI_VVSACR_VSA7_Msk (0x1UL << DSI_VVSACR_VSA7_Pos)
19242#define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
19243#define DSI_VVSACR_VSA8_Pos (8U)
19244#define DSI_VVSACR_VSA8_Msk (0x1UL << DSI_VVSACR_VSA8_Pos)
19245#define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
19246#define DSI_VVSACR_VSA9_Pos (9U)
19247#define DSI_VVSACR_VSA9_Msk (0x1UL << DSI_VVSACR_VSA9_Pos)
19248#define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
19249
19250/******************* Bit definition for DSI_VVBPCR register *************/
19251#define DSI_VVBPCR_VBP_Pos (0U)
19252#define DSI_VVBPCR_VBP_Msk (0x3FFUL << DSI_VVBPCR_VBP_Pos)
19253#define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk
19254#define DSI_VVBPCR_VBP0_Pos (0U)
19255#define DSI_VVBPCR_VBP0_Msk (0x1UL << DSI_VVBPCR_VBP0_Pos)
19256#define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
19257#define DSI_VVBPCR_VBP1_Pos (1U)
19258#define DSI_VVBPCR_VBP1_Msk (0x1UL << DSI_VVBPCR_VBP1_Pos)
19259#define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
19260#define DSI_VVBPCR_VBP2_Pos (2U)
19261#define DSI_VVBPCR_VBP2_Msk (0x1UL << DSI_VVBPCR_VBP2_Pos)
19262#define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
19263#define DSI_VVBPCR_VBP3_Pos (3U)
19264#define DSI_VVBPCR_VBP3_Msk (0x1UL << DSI_VVBPCR_VBP3_Pos)
19265#define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
19266#define DSI_VVBPCR_VBP4_Pos (4U)
19267#define DSI_VVBPCR_VBP4_Msk (0x1UL << DSI_VVBPCR_VBP4_Pos)
19268#define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
19269#define DSI_VVBPCR_VBP5_Pos (5U)
19270#define DSI_VVBPCR_VBP5_Msk (0x1UL << DSI_VVBPCR_VBP5_Pos)
19271#define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
19272#define DSI_VVBPCR_VBP6_Pos (6U)
19273#define DSI_VVBPCR_VBP6_Msk (0x1UL << DSI_VVBPCR_VBP6_Pos)
19274#define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
19275#define DSI_VVBPCR_VBP7_Pos (7U)
19276#define DSI_VVBPCR_VBP7_Msk (0x1UL << DSI_VVBPCR_VBP7_Pos)
19277#define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
19278#define DSI_VVBPCR_VBP8_Pos (8U)
19279#define DSI_VVBPCR_VBP8_Msk (0x1UL << DSI_VVBPCR_VBP8_Pos)
19280#define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
19281#define DSI_VVBPCR_VBP9_Pos (9U)
19282#define DSI_VVBPCR_VBP9_Msk (0x1UL << DSI_VVBPCR_VBP9_Pos)
19283#define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
19284
19285/******************* Bit definition for DSI_VVFPCR register *************/
19286#define DSI_VVFPCR_VFP_Pos (0U)
19287#define DSI_VVFPCR_VFP_Msk (0x3FFUL << DSI_VVFPCR_VFP_Pos)
19288#define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk
19289#define DSI_VVFPCR_VFP0_Pos (0U)
19290#define DSI_VVFPCR_VFP0_Msk (0x1UL << DSI_VVFPCR_VFP0_Pos)
19291#define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
19292#define DSI_VVFPCR_VFP1_Pos (1U)
19293#define DSI_VVFPCR_VFP1_Msk (0x1UL << DSI_VVFPCR_VFP1_Pos)
19294#define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
19295#define DSI_VVFPCR_VFP2_Pos (2U)
19296#define DSI_VVFPCR_VFP2_Msk (0x1UL << DSI_VVFPCR_VFP2_Pos)
19297#define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
19298#define DSI_VVFPCR_VFP3_Pos (3U)
19299#define DSI_VVFPCR_VFP3_Msk (0x1UL << DSI_VVFPCR_VFP3_Pos)
19300#define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
19301#define DSI_VVFPCR_VFP4_Pos (4U)
19302#define DSI_VVFPCR_VFP4_Msk (0x1UL << DSI_VVFPCR_VFP4_Pos)
19303#define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
19304#define DSI_VVFPCR_VFP5_Pos (5U)
19305#define DSI_VVFPCR_VFP5_Msk (0x1UL << DSI_VVFPCR_VFP5_Pos)
19306#define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
19307#define DSI_VVFPCR_VFP6_Pos (6U)
19308#define DSI_VVFPCR_VFP6_Msk (0x1UL << DSI_VVFPCR_VFP6_Pos)
19309#define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
19310#define DSI_VVFPCR_VFP7_Pos (7U)
19311#define DSI_VVFPCR_VFP7_Msk (0x1UL << DSI_VVFPCR_VFP7_Pos)
19312#define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
19313#define DSI_VVFPCR_VFP8_Pos (8U)
19314#define DSI_VVFPCR_VFP8_Msk (0x1UL << DSI_VVFPCR_VFP8_Pos)
19315#define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
19316#define DSI_VVFPCR_VFP9_Pos (9U)
19317#define DSI_VVFPCR_VFP9_Msk (0x1UL << DSI_VVFPCR_VFP9_Pos)
19318#define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
19319
19320/******************* Bit definition for DSI_VVACR register **************/
19321#define DSI_VVACR_VA_Pos (0U)
19322#define DSI_VVACR_VA_Msk (0x3FFFUL << DSI_VVACR_VA_Pos)
19323#define DSI_VVACR_VA DSI_VVACR_VA_Msk
19324#define DSI_VVACR_VA0_Pos (0U)
19325#define DSI_VVACR_VA0_Msk (0x1UL << DSI_VVACR_VA0_Pos)
19326#define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
19327#define DSI_VVACR_VA1_Pos (1U)
19328#define DSI_VVACR_VA1_Msk (0x1UL << DSI_VVACR_VA1_Pos)
19329#define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
19330#define DSI_VVACR_VA2_Pos (2U)
19331#define DSI_VVACR_VA2_Msk (0x1UL << DSI_VVACR_VA2_Pos)
19332#define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
19333#define DSI_VVACR_VA3_Pos (3U)
19334#define DSI_VVACR_VA3_Msk (0x1UL << DSI_VVACR_VA3_Pos)
19335#define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
19336#define DSI_VVACR_VA4_Pos (4U)
19337#define DSI_VVACR_VA4_Msk (0x1UL << DSI_VVACR_VA4_Pos)
19338#define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
19339#define DSI_VVACR_VA5_Pos (5U)
19340#define DSI_VVACR_VA5_Msk (0x1UL << DSI_VVACR_VA5_Pos)
19341#define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
19342#define DSI_VVACR_VA6_Pos (6U)
19343#define DSI_VVACR_VA6_Msk (0x1UL << DSI_VVACR_VA6_Pos)
19344#define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
19345#define DSI_VVACR_VA7_Pos (7U)
19346#define DSI_VVACR_VA7_Msk (0x1UL << DSI_VVACR_VA7_Pos)
19347#define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
19348#define DSI_VVACR_VA8_Pos (8U)
19349#define DSI_VVACR_VA8_Msk (0x1UL << DSI_VVACR_VA8_Pos)
19350#define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
19351#define DSI_VVACR_VA9_Pos (9U)
19352#define DSI_VVACR_VA9_Msk (0x1UL << DSI_VVACR_VA9_Pos)
19353#define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
19354#define DSI_VVACR_VA10_Pos (10U)
19355#define DSI_VVACR_VA10_Msk (0x1UL << DSI_VVACR_VA10_Pos)
19356#define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
19357#define DSI_VVACR_VA11_Pos (11U)
19358#define DSI_VVACR_VA11_Msk (0x1UL << DSI_VVACR_VA11_Pos)
19359#define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
19360#define DSI_VVACR_VA12_Pos (12U)
19361#define DSI_VVACR_VA12_Msk (0x1UL << DSI_VVACR_VA12_Pos)
19362#define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
19363#define DSI_VVACR_VA13_Pos (13U)
19364#define DSI_VVACR_VA13_Msk (0x1UL << DSI_VVACR_VA13_Pos)
19365#define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
19366
19367/******************* Bit definition for DSI_LCCR register ***************/
19368#define DSI_LCCR_CMDSIZE_Pos (0U)
19369#define DSI_LCCR_CMDSIZE_Msk (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos)
19370#define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk
19371#define DSI_LCCR_CMDSIZE0_Pos (0U)
19372#define DSI_LCCR_CMDSIZE0_Msk (0x1UL << DSI_LCCR_CMDSIZE0_Pos)
19373#define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
19374#define DSI_LCCR_CMDSIZE1_Pos (1U)
19375#define DSI_LCCR_CMDSIZE1_Msk (0x1UL << DSI_LCCR_CMDSIZE1_Pos)
19376#define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
19377#define DSI_LCCR_CMDSIZE2_Pos (2U)
19378#define DSI_LCCR_CMDSIZE2_Msk (0x1UL << DSI_LCCR_CMDSIZE2_Pos)
19379#define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
19380#define DSI_LCCR_CMDSIZE3_Pos (3U)
19381#define DSI_LCCR_CMDSIZE3_Msk (0x1UL << DSI_LCCR_CMDSIZE3_Pos)
19382#define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
19383#define DSI_LCCR_CMDSIZE4_Pos (4U)
19384#define DSI_LCCR_CMDSIZE4_Msk (0x1UL << DSI_LCCR_CMDSIZE4_Pos)
19385#define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
19386#define DSI_LCCR_CMDSIZE5_Pos (5U)
19387#define DSI_LCCR_CMDSIZE5_Msk (0x1UL << DSI_LCCR_CMDSIZE5_Pos)
19388#define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
19389#define DSI_LCCR_CMDSIZE6_Pos (6U)
19390#define DSI_LCCR_CMDSIZE6_Msk (0x1UL << DSI_LCCR_CMDSIZE6_Pos)
19391#define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
19392#define DSI_LCCR_CMDSIZE7_Pos (7U)
19393#define DSI_LCCR_CMDSIZE7_Msk (0x1UL << DSI_LCCR_CMDSIZE7_Pos)
19394#define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
19395#define DSI_LCCR_CMDSIZE8_Pos (8U)
19396#define DSI_LCCR_CMDSIZE8_Msk (0x1UL << DSI_LCCR_CMDSIZE8_Pos)
19397#define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
19398#define DSI_LCCR_CMDSIZE9_Pos (9U)
19399#define DSI_LCCR_CMDSIZE9_Msk (0x1UL << DSI_LCCR_CMDSIZE9_Pos)
19400#define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
19401#define DSI_LCCR_CMDSIZE10_Pos (10U)
19402#define DSI_LCCR_CMDSIZE10_Msk (0x1UL << DSI_LCCR_CMDSIZE10_Pos)
19403#define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
19404#define DSI_LCCR_CMDSIZE11_Pos (11U)
19405#define DSI_LCCR_CMDSIZE11_Msk (0x1UL << DSI_LCCR_CMDSIZE11_Pos)
19406#define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
19407#define DSI_LCCR_CMDSIZE12_Pos (12U)
19408#define DSI_LCCR_CMDSIZE12_Msk (0x1UL << DSI_LCCR_CMDSIZE12_Pos)
19409#define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
19410#define DSI_LCCR_CMDSIZE13_Pos (13U)
19411#define DSI_LCCR_CMDSIZE13_Msk (0x1UL << DSI_LCCR_CMDSIZE13_Pos)
19412#define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
19413#define DSI_LCCR_CMDSIZE14_Pos (14U)
19414#define DSI_LCCR_CMDSIZE14_Msk (0x1UL << DSI_LCCR_CMDSIZE14_Pos)
19415#define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
19416#define DSI_LCCR_CMDSIZE15_Pos (15U)
19417#define DSI_LCCR_CMDSIZE15_Msk (0x1UL << DSI_LCCR_CMDSIZE15_Pos)
19418#define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
19419
19420/******************* Bit definition for DSI_CMCR register ***************/
19421#define DSI_CMCR_TEARE_Pos (0U)
19422#define DSI_CMCR_TEARE_Msk (0x1UL << DSI_CMCR_TEARE_Pos)
19423#define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk
19424#define DSI_CMCR_ARE_Pos (1U)
19425#define DSI_CMCR_ARE_Msk (0x1UL << DSI_CMCR_ARE_Pos)
19426#define DSI_CMCR_ARE DSI_CMCR_ARE_Msk
19427#define DSI_CMCR_GSW0TX_Pos (8U)
19428#define DSI_CMCR_GSW0TX_Msk (0x1UL << DSI_CMCR_GSW0TX_Pos)
19429#define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk
19430#define DSI_CMCR_GSW1TX_Pos (9U)
19431#define DSI_CMCR_GSW1TX_Msk (0x1UL << DSI_CMCR_GSW1TX_Pos)
19432#define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk
19433#define DSI_CMCR_GSW2TX_Pos (10U)
19434#define DSI_CMCR_GSW2TX_Msk (0x1UL << DSI_CMCR_GSW2TX_Pos)
19435#define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk
19436#define DSI_CMCR_GSR0TX_Pos (11U)
19437#define DSI_CMCR_GSR0TX_Msk (0x1UL << DSI_CMCR_GSR0TX_Pos)
19438#define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk
19439#define DSI_CMCR_GSR1TX_Pos (12U)
19440#define DSI_CMCR_GSR1TX_Msk (0x1UL << DSI_CMCR_GSR1TX_Pos)
19441#define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk
19442#define DSI_CMCR_GSR2TX_Pos (13U)
19443#define DSI_CMCR_GSR2TX_Msk (0x1UL << DSI_CMCR_GSR2TX_Pos)
19444#define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk
19445#define DSI_CMCR_GLWTX_Pos (14U)
19446#define DSI_CMCR_GLWTX_Msk (0x1UL << DSI_CMCR_GLWTX_Pos)
19447#define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk
19448#define DSI_CMCR_DSW0TX_Pos (16U)
19449#define DSI_CMCR_DSW0TX_Msk (0x1UL << DSI_CMCR_DSW0TX_Pos)
19450#define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk
19451#define DSI_CMCR_DSW1TX_Pos (17U)
19452#define DSI_CMCR_DSW1TX_Msk (0x1UL << DSI_CMCR_DSW1TX_Pos)
19453#define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk
19454#define DSI_CMCR_DSR0TX_Pos (18U)
19455#define DSI_CMCR_DSR0TX_Msk (0x1UL << DSI_CMCR_DSR0TX_Pos)
19456#define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk
19457#define DSI_CMCR_DLWTX_Pos (19U)
19458#define DSI_CMCR_DLWTX_Msk (0x1UL << DSI_CMCR_DLWTX_Pos)
19459#define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk
19460#define DSI_CMCR_MRDPS_Pos (24U)
19461#define DSI_CMCR_MRDPS_Msk (0x1UL << DSI_CMCR_MRDPS_Pos)
19462#define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk
19464/******************* Bit definition for DSI_GHCR register ***************/
19465#define DSI_GHCR_DT_Pos (0U)
19466#define DSI_GHCR_DT_Msk (0x3FUL << DSI_GHCR_DT_Pos)
19467#define DSI_GHCR_DT DSI_GHCR_DT_Msk
19468#define DSI_GHCR_DT0_Pos (0U)
19469#define DSI_GHCR_DT0_Msk (0x1UL << DSI_GHCR_DT0_Pos)
19470#define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
19471#define DSI_GHCR_DT1_Pos (1U)
19472#define DSI_GHCR_DT1_Msk (0x1UL << DSI_GHCR_DT1_Pos)
19473#define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
19474#define DSI_GHCR_DT2_Pos (2U)
19475#define DSI_GHCR_DT2_Msk (0x1UL << DSI_GHCR_DT2_Pos)
19476#define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
19477#define DSI_GHCR_DT3_Pos (3U)
19478#define DSI_GHCR_DT3_Msk (0x1UL << DSI_GHCR_DT3_Pos)
19479#define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
19480#define DSI_GHCR_DT4_Pos (4U)
19481#define DSI_GHCR_DT4_Msk (0x1UL << DSI_GHCR_DT4_Pos)
19482#define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
19483#define DSI_GHCR_DT5_Pos (5U)
19484#define DSI_GHCR_DT5_Msk (0x1UL << DSI_GHCR_DT5_Pos)
19485#define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
19486
19487#define DSI_GHCR_VCID_Pos (6U)
19488#define DSI_GHCR_VCID_Msk (0x3UL << DSI_GHCR_VCID_Pos)
19489#define DSI_GHCR_VCID DSI_GHCR_VCID_Msk
19490#define DSI_GHCR_VCID0_Pos (6U)
19491#define DSI_GHCR_VCID0_Msk (0x1UL << DSI_GHCR_VCID0_Pos)
19492#define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
19493#define DSI_GHCR_VCID1_Pos (7U)
19494#define DSI_GHCR_VCID1_Msk (0x1UL << DSI_GHCR_VCID1_Pos)
19495#define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
19496
19497#define DSI_GHCR_WCLSB_Pos (8U)
19498#define DSI_GHCR_WCLSB_Msk (0xFFUL << DSI_GHCR_WCLSB_Pos)
19499#define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk
19500#define DSI_GHCR_WCLSB0_Pos (8U)
19501#define DSI_GHCR_WCLSB0_Msk (0x1UL << DSI_GHCR_WCLSB0_Pos)
19502#define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
19503#define DSI_GHCR_WCLSB1_Pos (9U)
19504#define DSI_GHCR_WCLSB1_Msk (0x1UL << DSI_GHCR_WCLSB1_Pos)
19505#define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
19506#define DSI_GHCR_WCLSB2_Pos (10U)
19507#define DSI_GHCR_WCLSB2_Msk (0x1UL << DSI_GHCR_WCLSB2_Pos)
19508#define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
19509#define DSI_GHCR_WCLSB3_Pos (11U)
19510#define DSI_GHCR_WCLSB3_Msk (0x1UL << DSI_GHCR_WCLSB3_Pos)
19511#define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
19512#define DSI_GHCR_WCLSB4_Pos (12U)
19513#define DSI_GHCR_WCLSB4_Msk (0x1UL << DSI_GHCR_WCLSB4_Pos)
19514#define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
19515#define DSI_GHCR_WCLSB5_Pos (13U)
19516#define DSI_GHCR_WCLSB5_Msk (0x1UL << DSI_GHCR_WCLSB5_Pos)
19517#define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
19518#define DSI_GHCR_WCLSB6_Pos (14U)
19519#define DSI_GHCR_WCLSB6_Msk (0x1UL << DSI_GHCR_WCLSB6_Pos)
19520#define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
19521#define DSI_GHCR_WCLSB7_Pos (15U)
19522#define DSI_GHCR_WCLSB7_Msk (0x1UL << DSI_GHCR_WCLSB7_Pos)
19523#define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
19524
19525#define DSI_GHCR_WCMSB_Pos (16U)
19526#define DSI_GHCR_WCMSB_Msk (0xFFUL << DSI_GHCR_WCMSB_Pos)
19527#define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk
19528#define DSI_GHCR_WCMSB0_Pos (16U)
19529#define DSI_GHCR_WCMSB0_Msk (0x1UL << DSI_GHCR_WCMSB0_Pos)
19530#define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
19531#define DSI_GHCR_WCMSB1_Pos (17U)
19532#define DSI_GHCR_WCMSB1_Msk (0x1UL << DSI_GHCR_WCMSB1_Pos)
19533#define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
19534#define DSI_GHCR_WCMSB2_Pos (18U)
19535#define DSI_GHCR_WCMSB2_Msk (0x1UL << DSI_GHCR_WCMSB2_Pos)
19536#define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
19537#define DSI_GHCR_WCMSB3_Pos (19U)
19538#define DSI_GHCR_WCMSB3_Msk (0x1UL << DSI_GHCR_WCMSB3_Pos)
19539#define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
19540#define DSI_GHCR_WCMSB4_Pos (20U)
19541#define DSI_GHCR_WCMSB4_Msk (0x1UL << DSI_GHCR_WCMSB4_Pos)
19542#define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
19543#define DSI_GHCR_WCMSB5_Pos (21U)
19544#define DSI_GHCR_WCMSB5_Msk (0x1UL << DSI_GHCR_WCMSB5_Pos)
19545#define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
19546#define DSI_GHCR_WCMSB6_Pos (22U)
19547#define DSI_GHCR_WCMSB6_Msk (0x1UL << DSI_GHCR_WCMSB6_Pos)
19548#define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
19549#define DSI_GHCR_WCMSB7_Pos (23U)
19550#define DSI_GHCR_WCMSB7_Msk (0x1UL << DSI_GHCR_WCMSB7_Pos)
19551#define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
19552
19553/******************* Bit definition for DSI_GPDR register ***************/
19554#define DSI_GPDR_DATA1_Pos (0U)
19555#define DSI_GPDR_DATA1_Msk (0xFFUL << DSI_GPDR_DATA1_Pos)
19556#define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk
19557#define DSI_GPDR_DATA1_0 (0x01UL << DSI_GPDR_DATA1_Pos)
19558#define DSI_GPDR_DATA1_1 (0x02UL << DSI_GPDR_DATA1_Pos)
19559#define DSI_GPDR_DATA1_2 (0x04UL << DSI_GPDR_DATA1_Pos)
19560#define DSI_GPDR_DATA1_3 (0x08UL << DSI_GPDR_DATA1_Pos)
19561#define DSI_GPDR_DATA1_4 (0x10UL << DSI_GPDR_DATA1_Pos)
19562#define DSI_GPDR_DATA1_5 (0x20UL << DSI_GPDR_DATA1_Pos)
19563#define DSI_GPDR_DATA1_6 (0x40UL << DSI_GPDR_DATA1_Pos)
19564#define DSI_GPDR_DATA1_7 (0x80UL << DSI_GPDR_DATA1_Pos)
19566#define DSI_GPDR_DATA2_Pos (8U)
19567#define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos)
19568#define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk
19569#define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos)
19570#define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos)
19571#define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos)
19572#define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos)
19573#define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos)
19574#define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos)
19575#define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos)
19576#define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos)
19578#define DSI_GPDR_DATA3_Pos (16U)
19579#define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos)
19580#define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk
19581#define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos)
19582#define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos)
19583#define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos)
19584#define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos)
19585#define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos)
19586#define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos)
19587#define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos)
19588#define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos)
19590#define DSI_GPDR_DATA4_Pos (24U)
19591#define DSI_GPDR_DATA4_Msk (0xFFUL << DSI_GPDR_DATA4_Pos)
19592#define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk
19593#define DSI_GPDR_DATA4_0 (0x01UL << DSI_GPDR_DATA4_Pos)
19594#define DSI_GPDR_DATA4_1 (0x02UL << DSI_GPDR_DATA4_Pos)
19595#define DSI_GPDR_DATA4_2 (0x04UL << DSI_GPDR_DATA4_Pos)
19596#define DSI_GPDR_DATA4_3 (0x08UL << DSI_GPDR_DATA4_Pos)
19597#define DSI_GPDR_DATA4_4 (0x10UL << DSI_GPDR_DATA4_Pos)
19598#define DSI_GPDR_DATA4_5 (0x20UL << DSI_GPDR_DATA4_Pos)
19599#define DSI_GPDR_DATA4_6 (0x40UL << DSI_GPDR_DATA4_Pos)
19600#define DSI_GPDR_DATA4_7 (0x80UL << DSI_GPDR_DATA4_Pos)
19602/******************* Bit definition for DSI_GPSR register ***************/
19603#define DSI_GPSR_CMDFE_Pos (0U)
19604#define DSI_GPSR_CMDFE_Msk (0x1UL << DSI_GPSR_CMDFE_Pos)
19605#define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk
19606#define DSI_GPSR_CMDFF_Pos (1U)
19607#define DSI_GPSR_CMDFF_Msk (0x1UL << DSI_GPSR_CMDFF_Pos)
19608#define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk
19609#define DSI_GPSR_PWRFE_Pos (2U)
19610#define DSI_GPSR_PWRFE_Msk (0x1UL << DSI_GPSR_PWRFE_Pos)
19611#define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk
19612#define DSI_GPSR_PWRFF_Pos (3U)
19613#define DSI_GPSR_PWRFF_Msk (0x1UL << DSI_GPSR_PWRFF_Pos)
19614#define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk
19615#define DSI_GPSR_PRDFE_Pos (4U)
19616#define DSI_GPSR_PRDFE_Msk (0x1UL << DSI_GPSR_PRDFE_Pos)
19617#define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk
19618#define DSI_GPSR_PRDFF_Pos (5U)
19619#define DSI_GPSR_PRDFF_Msk (0x1UL << DSI_GPSR_PRDFF_Pos)
19620#define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk
19621#define DSI_GPSR_RCB_Pos (6U)
19622#define DSI_GPSR_RCB_Msk (0x1UL << DSI_GPSR_RCB_Pos)
19623#define DSI_GPSR_RCB DSI_GPSR_RCB_Msk
19625/******************* Bit definition for DSI_TCCR0register **************/
19626#define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
19627#define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos)
19628#define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk
19629#define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
19630#define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos)
19631#define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
19632#define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
19633#define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos)
19634#define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
19635#define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
19636#define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos)
19637#define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
19638#define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
19639#define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos)
19640#define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
19641#define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
19642#define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos)
19643#define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
19644#define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
19645#define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos)
19646#define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
19647#define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
19648#define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos)
19649#define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
19650#define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
19651#define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos)
19652#define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
19653#define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
19654#define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos)
19655#define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
19656#define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
19657#define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos)
19658#define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
19659#define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
19660#define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos)
19661#define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
19662#define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
19663#define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos)
19664#define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
19665#define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
19666#define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos)
19667#define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
19668#define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
19669#define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos)
19670#define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
19671#define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
19672#define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos)
19673#define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
19674#define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
19675#define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos)
19676#define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
19677
19678#define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
19679#define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos)
19680#define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk
19681#define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
19682#define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos)
19683#define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
19684#define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
19685#define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos)
19686#define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
19687#define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
19688#define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos)
19689#define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
19690#define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
19691#define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos)
19692#define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
19693#define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
19694#define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos)
19695#define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
19696#define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
19697#define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos)
19698#define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
19699#define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
19700#define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos)
19701#define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
19702#define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
19703#define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos)
19704#define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
19705#define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
19706#define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos)
19707#define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
19708#define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
19709#define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos)
19710#define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
19711#define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
19712#define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos)
19713#define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
19714#define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
19715#define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos)
19716#define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
19717#define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
19718#define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos)
19719#define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
19720#define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
19721#define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos)
19722#define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
19723#define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
19724#define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos)
19725#define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
19726#define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
19727#define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos)
19728#define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
19729
19730/******************* Bit definition for DSI_TCCR1register **************/
19731#define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
19732#define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos)
19733#define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk
19734#define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
19735#define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos)
19736#define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
19737#define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
19738#define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos)
19739#define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
19740#define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
19741#define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos)
19742#define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
19743#define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
19744#define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos)
19745#define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
19746#define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
19747#define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos)
19748#define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
19749#define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
19750#define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos)
19751#define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
19752#define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
19753#define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos)
19754#define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
19755#define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
19756#define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos)
19757#define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
19758#define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
19759#define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos)
19760#define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
19761#define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
19762#define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos)
19763#define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
19764#define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
19765#define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos)
19766#define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
19767#define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
19768#define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos)
19769#define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
19770#define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
19771#define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos)
19772#define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
19773#define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
19774#define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos)
19775#define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
19776#define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
19777#define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos)
19778#define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
19779#define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
19780#define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos)
19781#define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
19782
19783/******************* Bit definition for DSI_TCCR2 register **************/
19784#define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
19785#define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos)
19786#define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk
19787#define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
19788#define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos)
19789#define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
19790#define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
19791#define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos)
19792#define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
19793#define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
19794#define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos)
19795#define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
19796#define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
19797#define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos)
19798#define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
19799#define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
19800#define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos)
19801#define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
19802#define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
19803#define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos)
19804#define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
19805#define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
19806#define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos)
19807#define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
19808#define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
19809#define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos)
19810#define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
19811#define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
19812#define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos)
19813#define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
19814#define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
19815#define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos)
19816#define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
19817#define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
19818#define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos)
19819#define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
19820#define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
19821#define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos)
19822#define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
19823#define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
19824#define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos)
19825#define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
19826#define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
19827#define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos)
19828#define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
19829#define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
19830#define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos)
19831#define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
19832#define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
19833#define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos)
19834#define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
19835
19836/******************* Bit definition for DSI_TCCR3 register **************/
19837#define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
19838#define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos)
19839#define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk
19840#define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
19841#define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos)
19842#define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
19843#define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
19844#define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos)
19845#define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
19846#define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
19847#define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos)
19848#define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
19849#define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
19850#define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos)
19851#define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
19852#define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
19853#define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos)
19854#define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
19855#define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
19856#define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos)
19857#define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
19858#define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
19859#define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos)
19860#define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
19861#define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
19862#define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos)
19863#define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
19864#define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
19865#define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos)
19866#define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
19867#define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
19868#define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos)
19869#define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
19870#define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
19871#define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos)
19872#define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
19873#define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
19874#define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos)
19875#define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
19876#define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
19877#define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos)
19878#define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
19879#define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
19880#define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos)
19881#define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
19882#define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
19883#define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos)
19884#define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
19885#define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
19886#define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos)
19887#define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
19888
19889#define DSI_TCCR3_PM_Pos (24U)
19890#define DSI_TCCR3_PM_Msk (0x1UL << DSI_TCCR3_PM_Pos)
19891#define DSI_TCCR3_PM DSI_TCCR3_PM_Msk
19893/******************* Bit definition for DSI_TCCR4 register **************/
19894#define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
19895#define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos)
19896#define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk
19897#define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
19898#define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos)
19899#define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
19900#define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
19901#define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos)
19902#define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
19903#define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
19904#define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos)
19905#define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
19906#define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
19907#define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos)
19908#define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
19909#define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
19910#define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos)
19911#define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
19912#define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
19913#define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos)
19914#define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
19915#define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
19916#define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos)
19917#define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
19918#define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
19919#define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos)
19920#define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
19921#define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
19922#define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos)
19923#define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
19924#define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
19925#define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos)
19926#define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
19927#define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
19928#define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos)
19929#define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
19930#define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
19931#define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos)
19932#define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
19933#define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
19934#define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos)
19935#define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
19936#define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
19937#define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos)
19938#define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
19939#define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
19940#define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos)
19941#define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
19942#define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
19943#define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos)
19944#define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
19945
19946/******************* Bit definition for DSI_TCCR5register **************/
19947#define DSI_TCCR5_BTA_TOCNT_Pos (0U)
19948#define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos)
19949#define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk
19950#define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
19951#define DSI_TCCR5_BTA_TOCNT0_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos)
19952#define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
19953#define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
19954#define DSI_TCCR5_BTA_TOCNT1_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos)
19955#define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
19956#define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
19957#define DSI_TCCR5_BTA_TOCNT2_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos)
19958#define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
19959#define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
19960#define DSI_TCCR5_BTA_TOCNT3_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos)
19961#define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
19962#define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
19963#define DSI_TCCR5_BTA_TOCNT4_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos)
19964#define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
19965#define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
19966#define DSI_TCCR5_BTA_TOCNT5_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos)
19967#define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
19968#define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
19969#define DSI_TCCR5_BTA_TOCNT6_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos)
19970#define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
19971#define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
19972#define DSI_TCCR5_BTA_TOCNT7_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos)
19973#define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
19974#define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
19975#define DSI_TCCR5_BTA_TOCNT8_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos)
19976#define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
19977#define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
19978#define DSI_TCCR5_BTA_TOCNT9_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos)
19979#define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
19980#define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
19981#define DSI_TCCR5_BTA_TOCNT10_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos)
19982#define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
19983#define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
19984#define DSI_TCCR5_BTA_TOCNT11_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos)
19985#define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
19986#define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
19987#define DSI_TCCR5_BTA_TOCNT12_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos)
19988#define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
19989#define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
19990#define DSI_TCCR5_BTA_TOCNT13_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos)
19991#define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
19992#define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
19993#define DSI_TCCR5_BTA_TOCNT14_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos)
19994#define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
19995#define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
19996#define DSI_TCCR5_BTA_TOCNT15_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos)
19997#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
19998
19999/******************* Bit definition for DSI_TDCR register ***************/
20000#define DSI_TDCR_3DM 0x00000003U
20001#define DSI_TDCR_3DM0 0x00000001U
20002#define DSI_TDCR_3DM1 0x00000002U
20003
20004#define DSI_TDCR_3DF 0x0000000CU
20005#define DSI_TDCR_3DF0 0x00000004U
20006#define DSI_TDCR_3DF1 0x00000008U
20007
20008#define DSI_TDCR_SVS_Pos (4U)
20009#define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos)
20010#define DSI_TDCR_SVS DSI_TDCR_SVS_Msk
20011#define DSI_TDCR_RF_Pos (5U)
20012#define DSI_TDCR_RF_Msk (0x1UL << DSI_TDCR_RF_Pos)
20013#define DSI_TDCR_RF DSI_TDCR_RF_Msk
20014#define DSI_TDCR_S3DC_Pos (16U)
20015#define DSI_TDCR_S3DC_Msk (0x1UL << DSI_TDCR_S3DC_Pos)
20016#define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk
20018/******************* Bit definition for DSI_CLCR register ***************/
20019#define DSI_CLCR_DPCC_Pos (0U)
20020#define DSI_CLCR_DPCC_Msk (0x1UL << DSI_CLCR_DPCC_Pos)
20021#define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk
20022#define DSI_CLCR_ACR_Pos (1U)
20023#define DSI_CLCR_ACR_Msk (0x1UL << DSI_CLCR_ACR_Pos)
20024#define DSI_CLCR_ACR DSI_CLCR_ACR_Msk
20026/******************* Bit definition for DSI_CLTCR register **************/
20027#define DSI_CLTCR_LP2HS_TIME_Pos (0U)
20028#define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos)
20029#define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk
20030#define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
20031#define DSI_CLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos)
20032#define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
20033#define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
20034#define DSI_CLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos)
20035#define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
20036#define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
20037#define DSI_CLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos)
20038#define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
20039#define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
20040#define DSI_CLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos)
20041#define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
20042#define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
20043#define DSI_CLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos)
20044#define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
20045#define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
20046#define DSI_CLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos)
20047#define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
20048#define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
20049#define DSI_CLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos)
20050#define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
20051#define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
20052#define DSI_CLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos)
20053#define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
20054#define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
20055#define DSI_CLTCR_LP2HS_TIME8_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos)
20056#define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
20057#define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
20058#define DSI_CLTCR_LP2HS_TIME9_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos)
20059#define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
20060
20061#define DSI_CLTCR_HS2LP_TIME_Pos (16U)
20062#define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos)
20063#define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk
20064#define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
20065#define DSI_CLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos)
20066#define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
20067#define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
20068#define DSI_CLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos)
20069#define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
20070#define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
20071#define DSI_CLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos)
20072#define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
20073#define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
20074#define DSI_CLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos)
20075#define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
20076#define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
20077#define DSI_CLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos)
20078#define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
20079#define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
20080#define DSI_CLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos)
20081#define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
20082#define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
20083#define DSI_CLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos)
20084#define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
20085#define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
20086#define DSI_CLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos)
20087#define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
20088#define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
20089#define DSI_CLTCR_HS2LP_TIME8_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos)
20090#define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
20091#define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
20092#define DSI_CLTCR_HS2LP_TIME9_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos)
20093#define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
20094
20095/******************* Bit definition for DSI_DLTCR register **************/
20096#define DSI_DLTCR_MRD_TIME_Pos (0U)
20097#define DSI_DLTCR_MRD_TIME_Msk (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos)
20098#define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk
20099#define DSI_DLTCR_MRD_TIME0_Pos (0U)
20100#define DSI_DLTCR_MRD_TIME0_Msk (0x1UL << DSI_DLTCR_MRD_TIME0_Pos)
20101#define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
20102#define DSI_DLTCR_MRD_TIME1_Pos (1U)
20103#define DSI_DLTCR_MRD_TIME1_Msk (0x1UL << DSI_DLTCR_MRD_TIME1_Pos)
20104#define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
20105#define DSI_DLTCR_MRD_TIME2_Pos (2U)
20106#define DSI_DLTCR_MRD_TIME2_Msk (0x1UL << DSI_DLTCR_MRD_TIME2_Pos)
20107#define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
20108#define DSI_DLTCR_MRD_TIME3_Pos (3U)
20109#define DSI_DLTCR_MRD_TIME3_Msk (0x1UL << DSI_DLTCR_MRD_TIME3_Pos)
20110#define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
20111#define DSI_DLTCR_MRD_TIME4_Pos (4U)
20112#define DSI_DLTCR_MRD_TIME4_Msk (0x1UL << DSI_DLTCR_MRD_TIME4_Pos)
20113#define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
20114#define DSI_DLTCR_MRD_TIME5_Pos (5U)
20115#define DSI_DLTCR_MRD_TIME5_Msk (0x1UL << DSI_DLTCR_MRD_TIME5_Pos)
20116#define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
20117#define DSI_DLTCR_MRD_TIME6_Pos (6U)
20118#define DSI_DLTCR_MRD_TIME6_Msk (0x1UL << DSI_DLTCR_MRD_TIME6_Pos)
20119#define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
20120#define DSI_DLTCR_MRD_TIME7_Pos (7U)
20121#define DSI_DLTCR_MRD_TIME7_Msk (0x1UL << DSI_DLTCR_MRD_TIME7_Pos)
20122#define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
20123#define DSI_DLTCR_MRD_TIME8_Pos (8U)
20124#define DSI_DLTCR_MRD_TIME8_Msk (0x1UL << DSI_DLTCR_MRD_TIME8_Pos)
20125#define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
20126#define DSI_DLTCR_MRD_TIME9_Pos (9U)
20127#define DSI_DLTCR_MRD_TIME9_Msk (0x1UL << DSI_DLTCR_MRD_TIME9_Pos)
20128#define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
20129#define DSI_DLTCR_MRD_TIME10_Pos (10U)
20130#define DSI_DLTCR_MRD_TIME10_Msk (0x1UL << DSI_DLTCR_MRD_TIME10_Pos)
20131#define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
20132#define DSI_DLTCR_MRD_TIME11_Pos (11U)
20133#define DSI_DLTCR_MRD_TIME11_Msk (0x1UL << DSI_DLTCR_MRD_TIME11_Pos)
20134#define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
20135#define DSI_DLTCR_MRD_TIME12_Pos (12U)
20136#define DSI_DLTCR_MRD_TIME12_Msk (0x1UL << DSI_DLTCR_MRD_TIME12_Pos)
20137#define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
20138#define DSI_DLTCR_MRD_TIME13_Pos (13U)
20139#define DSI_DLTCR_MRD_TIME13_Msk (0x1UL << DSI_DLTCR_MRD_TIME13_Pos)
20140#define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
20141#define DSI_DLTCR_MRD_TIME14_Pos (14U)
20142#define DSI_DLTCR_MRD_TIME14_Msk (0x1UL << DSI_DLTCR_MRD_TIME14_Pos)
20143#define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
20144
20145#define DSI_DLTCR_LP2HS_TIME_Pos (16U)
20146#define DSI_DLTCR_LP2HS_TIME_Msk (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos)
20147#define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk
20148#define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
20149#define DSI_DLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos)
20150#define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
20151#define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
20152#define DSI_DLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos)
20153#define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
20154#define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
20155#define DSI_DLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos)
20156#define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
20157#define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
20158#define DSI_DLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos)
20159#define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
20160#define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
20161#define DSI_DLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos)
20162#define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
20163#define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
20164#define DSI_DLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos)
20165#define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
20166#define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
20167#define DSI_DLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos)
20168#define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
20169#define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
20170#define DSI_DLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos)
20171#define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
20172
20173#define DSI_DLTCR_HS2LP_TIME_Pos (24U)
20174#define DSI_DLTCR_HS2LP_TIME_Msk (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos)
20175#define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk
20176#define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
20177#define DSI_DLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos)
20178#define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
20179#define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
20180#define DSI_DLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos)
20181#define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
20182#define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
20183#define DSI_DLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos)
20184#define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
20185#define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
20186#define DSI_DLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos)
20187#define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
20188#define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
20189#define DSI_DLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos)
20190#define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
20191#define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
20192#define DSI_DLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos)
20193#define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
20194#define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
20195#define DSI_DLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos)
20196#define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
20197#define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
20198#define DSI_DLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos)
20199#define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
20200
20201/******************* Bit definition for DSI_PCTLRregister **************/
20202#define DSI_PCTLR_DEN_Pos (1U)
20203#define DSI_PCTLR_DEN_Msk (0x1UL << DSI_PCTLR_DEN_Pos)
20204#define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk
20205#define DSI_PCTLR_CKE_Pos (2U)
20206#define DSI_PCTLR_CKE_Msk (0x1UL << DSI_PCTLR_CKE_Pos)
20207#define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk
20209/******************* Bit definition for DSI_PCONFR register *************/
20210#define DSI_PCONFR_NL_Pos (0U)
20211#define DSI_PCONFR_NL_Msk (0x3UL << DSI_PCONFR_NL_Pos)
20212#define DSI_PCONFR_NL DSI_PCONFR_NL_Msk
20213#define DSI_PCONFR_NL0_Pos (0U)
20214#define DSI_PCONFR_NL0_Msk (0x1UL << DSI_PCONFR_NL0_Pos)
20215#define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
20216#define DSI_PCONFR_NL1_Pos (1U)
20217#define DSI_PCONFR_NL1_Msk (0x1UL << DSI_PCONFR_NL1_Pos)
20218#define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
20219
20220#define DSI_PCONFR_SW_TIME_Pos (8U)
20221#define DSI_PCONFR_SW_TIME_Msk (0xFFUL << DSI_PCONFR_SW_TIME_Pos)
20222#define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk
20223#define DSI_PCONFR_SW_TIME0_Pos (8U)
20224#define DSI_PCONFR_SW_TIME0_Msk (0x1UL << DSI_PCONFR_SW_TIME0_Pos)
20225#define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
20226#define DSI_PCONFR_SW_TIME1_Pos (9U)
20227#define DSI_PCONFR_SW_TIME1_Msk (0x1UL << DSI_PCONFR_SW_TIME1_Pos)
20228#define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
20229#define DSI_PCONFR_SW_TIME2_Pos (10U)
20230#define DSI_PCONFR_SW_TIME2_Msk (0x1UL << DSI_PCONFR_SW_TIME2_Pos)
20231#define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
20232#define DSI_PCONFR_SW_TIME3_Pos (11U)
20233#define DSI_PCONFR_SW_TIME3_Msk (0x1UL << DSI_PCONFR_SW_TIME3_Pos)
20234#define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
20235#define DSI_PCONFR_SW_TIME4_Pos (12U)
20236#define DSI_PCONFR_SW_TIME4_Msk (0x1UL << DSI_PCONFR_SW_TIME4_Pos)
20237#define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
20238#define DSI_PCONFR_SW_TIME5_Pos (13U)
20239#define DSI_PCONFR_SW_TIME5_Msk (0x1UL << DSI_PCONFR_SW_TIME5_Pos)
20240#define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
20241#define DSI_PCONFR_SW_TIME6_Pos (14U)
20242#define DSI_PCONFR_SW_TIME6_Msk (0x1UL << DSI_PCONFR_SW_TIME6_Pos)
20243#define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
20244#define DSI_PCONFR_SW_TIME7_Pos (15U)
20245#define DSI_PCONFR_SW_TIME7_Msk (0x1UL << DSI_PCONFR_SW_TIME7_Pos)
20246#define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
20247
20248/******************* Bit definition for DSI_PUCR register ***************/
20249#define DSI_PUCR_URCL_Pos (0U)
20250#define DSI_PUCR_URCL_Msk (0x1UL << DSI_PUCR_URCL_Pos)
20251#define DSI_PUCR_URCL DSI_PUCR_URCL_Msk
20252#define DSI_PUCR_UECL_Pos (1U)
20253#define DSI_PUCR_UECL_Msk (0x1UL << DSI_PUCR_UECL_Pos)
20254#define DSI_PUCR_UECL DSI_PUCR_UECL_Msk
20255#define DSI_PUCR_URDL_Pos (2U)
20256#define DSI_PUCR_URDL_Msk (0x1UL << DSI_PUCR_URDL_Pos)
20257#define DSI_PUCR_URDL DSI_PUCR_URDL_Msk
20258#define DSI_PUCR_UEDL_Pos (3U)
20259#define DSI_PUCR_UEDL_Msk (0x1UL << DSI_PUCR_UEDL_Pos)
20260#define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk
20262/******************* Bit definition for DSI_PTTCRregister **************/
20263#define DSI_PTTCR_TX_TRIG_Pos (0U)
20264#define DSI_PTTCR_TX_TRIG_Msk (0xFUL << DSI_PTTCR_TX_TRIG_Pos)
20265#define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk
20266#define DSI_PTTCR_TX_TRIG0_Pos (0U)
20267#define DSI_PTTCR_TX_TRIG0_Msk (0x1UL << DSI_PTTCR_TX_TRIG0_Pos)
20268#define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
20269#define DSI_PTTCR_TX_TRIG1_Pos (1U)
20270#define DSI_PTTCR_TX_TRIG1_Msk (0x1UL << DSI_PTTCR_TX_TRIG1_Pos)
20271#define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
20272#define DSI_PTTCR_TX_TRIG2_Pos (2U)
20273#define DSI_PTTCR_TX_TRIG2_Msk (0x1UL << DSI_PTTCR_TX_TRIG2_Pos)
20274#define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
20275#define DSI_PTTCR_TX_TRIG3_Pos (3U)
20276#define DSI_PTTCR_TX_TRIG3_Msk (0x1UL << DSI_PTTCR_TX_TRIG3_Pos)
20277#define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
20278
20279/******************* Bit definition for DSI_PSR register ****************/
20280#define DSI_PSR_PD_Pos (1U)
20281#define DSI_PSR_PD_Msk (0x1UL << DSI_PSR_PD_Pos)
20282#define DSI_PSR_PD DSI_PSR_PD_Msk
20283#define DSI_PSR_PSSC_Pos (2U)
20284#define DSI_PSR_PSSC_Msk (0x1UL << DSI_PSR_PSSC_Pos)
20285#define DSI_PSR_PSSC DSI_PSR_PSSC_Msk
20286#define DSI_PSR_UANC_Pos (3U)
20287#define DSI_PSR_UANC_Msk (0x1UL << DSI_PSR_UANC_Pos)
20288#define DSI_PSR_UANC DSI_PSR_UANC_Msk
20289#define DSI_PSR_PSS0_Pos (4U)
20290#define DSI_PSR_PSS0_Msk (0x1UL << DSI_PSR_PSS0_Pos)
20291#define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk
20292#define DSI_PSR_UAN0_Pos (5U)
20293#define DSI_PSR_UAN0_Msk (0x1UL << DSI_PSR_UAN0_Pos)
20294#define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk
20295#define DSI_PSR_RUE0_Pos (6U)
20296#define DSI_PSR_RUE0_Msk (0x1UL << DSI_PSR_RUE0_Pos)
20297#define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk
20298#define DSI_PSR_PSS1_Pos (7U)
20299#define DSI_PSR_PSS1_Msk (0x1UL << DSI_PSR_PSS1_Pos)
20300#define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk
20301#define DSI_PSR_UAN1_Pos (8U)
20302#define DSI_PSR_UAN1_Msk (0x1UL << DSI_PSR_UAN1_Pos)
20303#define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk
20305/******************* Bit definition for DSI_ISR0 register ***************/
20306#define DSI_ISR0_AE0_Pos (0U)
20307#define DSI_ISR0_AE0_Msk (0x1UL << DSI_ISR0_AE0_Pos)
20308#define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk
20309#define DSI_ISR0_AE1_Pos (1U)
20310#define DSI_ISR0_AE1_Msk (0x1UL << DSI_ISR0_AE1_Pos)
20311#define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk
20312#define DSI_ISR0_AE2_Pos (2U)
20313#define DSI_ISR0_AE2_Msk (0x1UL << DSI_ISR0_AE2_Pos)
20314#define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk
20315#define DSI_ISR0_AE3_Pos (3U)
20316#define DSI_ISR0_AE3_Msk (0x1UL << DSI_ISR0_AE3_Pos)
20317#define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk
20318#define DSI_ISR0_AE4_Pos (4U)
20319#define DSI_ISR0_AE4_Msk (0x1UL << DSI_ISR0_AE4_Pos)
20320#define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk
20321#define DSI_ISR0_AE5_Pos (5U)
20322#define DSI_ISR0_AE5_Msk (0x1UL << DSI_ISR0_AE5_Pos)
20323#define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk
20324#define DSI_ISR0_AE6_Pos (6U)
20325#define DSI_ISR0_AE6_Msk (0x1UL << DSI_ISR0_AE6_Pos)
20326#define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk
20327#define DSI_ISR0_AE7_Pos (7U)
20328#define DSI_ISR0_AE7_Msk (0x1UL << DSI_ISR0_AE7_Pos)
20329#define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk
20330#define DSI_ISR0_AE8_Pos (8U)
20331#define DSI_ISR0_AE8_Msk (0x1UL << DSI_ISR0_AE8_Pos)
20332#define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk
20333#define DSI_ISR0_AE9_Pos (9U)
20334#define DSI_ISR0_AE9_Msk (0x1UL << DSI_ISR0_AE9_Pos)
20335#define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk
20336#define DSI_ISR0_AE10_Pos (10U)
20337#define DSI_ISR0_AE10_Msk (0x1UL << DSI_ISR0_AE10_Pos)
20338#define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk
20339#define DSI_ISR0_AE11_Pos (11U)
20340#define DSI_ISR0_AE11_Msk (0x1UL << DSI_ISR0_AE11_Pos)
20341#define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk
20342#define DSI_ISR0_AE12_Pos (12U)
20343#define DSI_ISR0_AE12_Msk (0x1UL << DSI_ISR0_AE12_Pos)
20344#define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk
20345#define DSI_ISR0_AE13_Pos (13U)
20346#define DSI_ISR0_AE13_Msk (0x1UL << DSI_ISR0_AE13_Pos)
20347#define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk
20348#define DSI_ISR0_AE14_Pos (14U)
20349#define DSI_ISR0_AE14_Msk (0x1UL << DSI_ISR0_AE14_Pos)
20350#define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk
20351#define DSI_ISR0_AE15_Pos (15U)
20352#define DSI_ISR0_AE15_Msk (0x1UL << DSI_ISR0_AE15_Pos)
20353#define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk
20354#define DSI_ISR0_PE0_Pos (16U)
20355#define DSI_ISR0_PE0_Msk (0x1UL << DSI_ISR0_PE0_Pos)
20356#define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk
20357#define DSI_ISR0_PE1_Pos (17U)
20358#define DSI_ISR0_PE1_Msk (0x1UL << DSI_ISR0_PE1_Pos)
20359#define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk
20360#define DSI_ISR0_PE2_Pos (18U)
20361#define DSI_ISR0_PE2_Msk (0x1UL << DSI_ISR0_PE2_Pos)
20362#define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk
20363#define DSI_ISR0_PE3_Pos (19U)
20364#define DSI_ISR0_PE3_Msk (0x1UL << DSI_ISR0_PE3_Pos)
20365#define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk
20366#define DSI_ISR0_PE4_Pos (20U)
20367#define DSI_ISR0_PE4_Msk (0x1UL << DSI_ISR0_PE4_Pos)
20368#define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk
20370/******************* Bit definition for DSI_ISR1 register ***************/
20371#define DSI_ISR1_TOHSTX_Pos (0U)
20372#define DSI_ISR1_TOHSTX_Msk (0x1UL << DSI_ISR1_TOHSTX_Pos)
20373#define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk
20374#define DSI_ISR1_TOLPRX_Pos (1U)
20375#define DSI_ISR1_TOLPRX_Msk (0x1UL << DSI_ISR1_TOLPRX_Pos)
20376#define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk
20377#define DSI_ISR1_ECCSE_Pos (2U)
20378#define DSI_ISR1_ECCSE_Msk (0x1UL << DSI_ISR1_ECCSE_Pos)
20379#define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk
20380#define DSI_ISR1_ECCME_Pos (3U)
20381#define DSI_ISR1_ECCME_Msk (0x1UL << DSI_ISR1_ECCME_Pos)
20382#define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk
20383#define DSI_ISR1_CRCE_Pos (4U)
20384#define DSI_ISR1_CRCE_Msk (0x1UL << DSI_ISR1_CRCE_Pos)
20385#define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk
20386#define DSI_ISR1_PSE_Pos (5U)
20387#define DSI_ISR1_PSE_Msk (0x1UL << DSI_ISR1_PSE_Pos)
20388#define DSI_ISR1_PSE DSI_ISR1_PSE_Msk
20389#define DSI_ISR1_EOTPE_Pos (6U)
20390#define DSI_ISR1_EOTPE_Msk (0x1UL << DSI_ISR1_EOTPE_Pos)
20391#define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk
20392#define DSI_ISR1_LPWRE_Pos (7U)
20393#define DSI_ISR1_LPWRE_Msk (0x1UL << DSI_ISR1_LPWRE_Pos)
20394#define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk
20395#define DSI_ISR1_GCWRE_Pos (8U)
20396#define DSI_ISR1_GCWRE_Msk (0x1UL << DSI_ISR1_GCWRE_Pos)
20397#define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk
20398#define DSI_ISR1_GPWRE_Pos (9U)
20399#define DSI_ISR1_GPWRE_Msk (0x1UL << DSI_ISR1_GPWRE_Pos)
20400#define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk
20401#define DSI_ISR1_GPTXE_Pos (10U)
20402#define DSI_ISR1_GPTXE_Msk (0x1UL << DSI_ISR1_GPTXE_Pos)
20403#define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk
20404#define DSI_ISR1_GPRDE_Pos (11U)
20405#define DSI_ISR1_GPRDE_Msk (0x1UL << DSI_ISR1_GPRDE_Pos)
20406#define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk
20407#define DSI_ISR1_GPRXE_Pos (12U)
20408#define DSI_ISR1_GPRXE_Msk (0x1UL << DSI_ISR1_GPRXE_Pos)
20409#define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk
20411/******************* Bit definition for DSI_IER0 register ***************/
20412#define DSI_IER0_AE0IE_Pos (0U)
20413#define DSI_IER0_AE0IE_Msk (0x1UL << DSI_IER0_AE0IE_Pos)
20414#define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk
20415#define DSI_IER0_AE1IE_Pos (1U)
20416#define DSI_IER0_AE1IE_Msk (0x1UL << DSI_IER0_AE1IE_Pos)
20417#define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk
20418#define DSI_IER0_AE2IE_Pos (2U)
20419#define DSI_IER0_AE2IE_Msk (0x1UL << DSI_IER0_AE2IE_Pos)
20420#define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk
20421#define DSI_IER0_AE3IE_Pos (3U)
20422#define DSI_IER0_AE3IE_Msk (0x1UL << DSI_IER0_AE3IE_Pos)
20423#define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk
20424#define DSI_IER0_AE4IE_Pos (4U)
20425#define DSI_IER0_AE4IE_Msk (0x1UL << DSI_IER0_AE4IE_Pos)
20426#define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk
20427#define DSI_IER0_AE5IE_Pos (5U)
20428#define DSI_IER0_AE5IE_Msk (0x1UL << DSI_IER0_AE5IE_Pos)
20429#define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk
20430#define DSI_IER0_AE6IE_Pos (6U)
20431#define DSI_IER0_AE6IE_Msk (0x1UL << DSI_IER0_AE6IE_Pos)
20432#define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk
20433#define DSI_IER0_AE7IE_Pos (7U)
20434#define DSI_IER0_AE7IE_Msk (0x1UL << DSI_IER0_AE7IE_Pos)
20435#define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk
20436#define DSI_IER0_AE8IE_Pos (8U)
20437#define DSI_IER0_AE8IE_Msk (0x1UL << DSI_IER0_AE8IE_Pos)
20438#define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk
20439#define DSI_IER0_AE9IE_Pos (9U)
20440#define DSI_IER0_AE9IE_Msk (0x1UL << DSI_IER0_AE9IE_Pos)
20441#define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk
20442#define DSI_IER0_AE10IE_Pos (10U)
20443#define DSI_IER0_AE10IE_Msk (0x1UL << DSI_IER0_AE10IE_Pos)
20444#define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk
20445#define DSI_IER0_AE11IE_Pos (11U)
20446#define DSI_IER0_AE11IE_Msk (0x1UL << DSI_IER0_AE11IE_Pos)
20447#define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk
20448#define DSI_IER0_AE12IE_Pos (12U)
20449#define DSI_IER0_AE12IE_Msk (0x1UL << DSI_IER0_AE12IE_Pos)
20450#define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk
20451#define DSI_IER0_AE13IE_Pos (13U)
20452#define DSI_IER0_AE13IE_Msk (0x1UL << DSI_IER0_AE13IE_Pos)
20453#define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk
20454#define DSI_IER0_AE14IE_Pos (14U)
20455#define DSI_IER0_AE14IE_Msk (0x1UL << DSI_IER0_AE14IE_Pos)
20456#define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk
20457#define DSI_IER0_AE15IE_Pos (15U)
20458#define DSI_IER0_AE15IE_Msk (0x1UL << DSI_IER0_AE15IE_Pos)
20459#define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk
20460#define DSI_IER0_PE0IE_Pos (16U)
20461#define DSI_IER0_PE0IE_Msk (0x1UL << DSI_IER0_PE0IE_Pos)
20462#define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk
20463#define DSI_IER0_PE1IE_Pos (17U)
20464#define DSI_IER0_PE1IE_Msk (0x1UL << DSI_IER0_PE1IE_Pos)
20465#define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk
20466#define DSI_IER0_PE2IE_Pos (18U)
20467#define DSI_IER0_PE2IE_Msk (0x1UL << DSI_IER0_PE2IE_Pos)
20468#define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk
20469#define DSI_IER0_PE3IE_Pos (19U)
20470#define DSI_IER0_PE3IE_Msk (0x1UL << DSI_IER0_PE3IE_Pos)
20471#define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk
20472#define DSI_IER0_PE4IE_Pos (20U)
20473#define DSI_IER0_PE4IE_Msk (0x1UL << DSI_IER0_PE4IE_Pos)
20474#define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk
20476/******************* Bit definition for DSI_IER1 register ***************/
20477#define DSI_IER1_TOHSTXIE_Pos (0U)
20478#define DSI_IER1_TOHSTXIE_Msk (0x1UL << DSI_IER1_TOHSTXIE_Pos)
20479#define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk
20480#define DSI_IER1_TOLPRXIE_Pos (1U)
20481#define DSI_IER1_TOLPRXIE_Msk (0x1UL << DSI_IER1_TOLPRXIE_Pos)
20482#define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk
20483#define DSI_IER1_ECCSEIE_Pos (2U)
20484#define DSI_IER1_ECCSEIE_Msk (0x1UL << DSI_IER1_ECCSEIE_Pos)
20485#define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk
20486#define DSI_IER1_ECCMEIE_Pos (3U)
20487#define DSI_IER1_ECCMEIE_Msk (0x1UL << DSI_IER1_ECCMEIE_Pos)
20488#define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk
20489#define DSI_IER1_CRCEIE_Pos (4U)
20490#define DSI_IER1_CRCEIE_Msk (0x1UL << DSI_IER1_CRCEIE_Pos)
20491#define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk
20492#define DSI_IER1_PSEIE_Pos (5U)
20493#define DSI_IER1_PSEIE_Msk (0x1UL << DSI_IER1_PSEIE_Pos)
20494#define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk
20495#define DSI_IER1_EOTPEIE_Pos (6U)
20496#define DSI_IER1_EOTPEIE_Msk (0x1UL << DSI_IER1_EOTPEIE_Pos)
20497#define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk
20498#define DSI_IER1_LPWREIE_Pos (7U)
20499#define DSI_IER1_LPWREIE_Msk (0x1UL << DSI_IER1_LPWREIE_Pos)
20500#define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk
20501#define DSI_IER1_GCWREIE_Pos (8U)
20502#define DSI_IER1_GCWREIE_Msk (0x1UL << DSI_IER1_GCWREIE_Pos)
20503#define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk
20504#define DSI_IER1_GPWREIE_Pos (9U)
20505#define DSI_IER1_GPWREIE_Msk (0x1UL << DSI_IER1_GPWREIE_Pos)
20506#define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk
20507#define DSI_IER1_GPTXEIE_Pos (10U)
20508#define DSI_IER1_GPTXEIE_Msk (0x1UL << DSI_IER1_GPTXEIE_Pos)
20509#define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk
20510#define DSI_IER1_GPRDEIE_Pos (11U)
20511#define DSI_IER1_GPRDEIE_Msk (0x1UL << DSI_IER1_GPRDEIE_Pos)
20512#define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk
20513#define DSI_IER1_GPRXEIE_Pos (12U)
20514#define DSI_IER1_GPRXEIE_Msk (0x1UL << DSI_IER1_GPRXEIE_Pos)
20515#define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk
20517/******************* Bit definition for DSI_FIR0 register ***************/
20518#define DSI_FIR0_FAE0_Pos (0U)
20519#define DSI_FIR0_FAE0_Msk (0x1UL << DSI_FIR0_FAE0_Pos)
20520#define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk
20521#define DSI_FIR0_FAE1_Pos (1U)
20522#define DSI_FIR0_FAE1_Msk (0x1UL << DSI_FIR0_FAE1_Pos)
20523#define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk
20524#define DSI_FIR0_FAE2_Pos (2U)
20525#define DSI_FIR0_FAE2_Msk (0x1UL << DSI_FIR0_FAE2_Pos)
20526#define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk
20527#define DSI_FIR0_FAE3_Pos (3U)
20528#define DSI_FIR0_FAE3_Msk (0x1UL << DSI_FIR0_FAE3_Pos)
20529#define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk
20530#define DSI_FIR0_FAE4_Pos (4U)
20531#define DSI_FIR0_FAE4_Msk (0x1UL << DSI_FIR0_FAE4_Pos)
20532#define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk
20533#define DSI_FIR0_FAE5_Pos (5U)
20534#define DSI_FIR0_FAE5_Msk (0x1UL << DSI_FIR0_FAE5_Pos)
20535#define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk
20536#define DSI_FIR0_FAE6_Pos (6U)
20537#define DSI_FIR0_FAE6_Msk (0x1UL << DSI_FIR0_FAE6_Pos)
20538#define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk
20539#define DSI_FIR0_FAE7_Pos (7U)
20540#define DSI_FIR0_FAE7_Msk (0x1UL << DSI_FIR0_FAE7_Pos)
20541#define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk
20542#define DSI_FIR0_FAE8_Pos (8U)
20543#define DSI_FIR0_FAE8_Msk (0x1UL << DSI_FIR0_FAE8_Pos)
20544#define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk
20545#define DSI_FIR0_FAE9_Pos (9U)
20546#define DSI_FIR0_FAE9_Msk (0x1UL << DSI_FIR0_FAE9_Pos)
20547#define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk
20548#define DSI_FIR0_FAE10_Pos (10U)
20549#define DSI_FIR0_FAE10_Msk (0x1UL << DSI_FIR0_FAE10_Pos)
20550#define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk
20551#define DSI_FIR0_FAE11_Pos (11U)
20552#define DSI_FIR0_FAE11_Msk (0x1UL << DSI_FIR0_FAE11_Pos)
20553#define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk
20554#define DSI_FIR0_FAE12_Pos (12U)
20555#define DSI_FIR0_FAE12_Msk (0x1UL << DSI_FIR0_FAE12_Pos)
20556#define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk
20557#define DSI_FIR0_FAE13_Pos (13U)
20558#define DSI_FIR0_FAE13_Msk (0x1UL << DSI_FIR0_FAE13_Pos)
20559#define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk
20560#define DSI_FIR0_FAE14_Pos (14U)
20561#define DSI_FIR0_FAE14_Msk (0x1UL << DSI_FIR0_FAE14_Pos)
20562#define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk
20563#define DSI_FIR0_FAE15_Pos (15U)
20564#define DSI_FIR0_FAE15_Msk (0x1UL << DSI_FIR0_FAE15_Pos)
20565#define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk
20566#define DSI_FIR0_FPE0_Pos (16U)
20567#define DSI_FIR0_FPE0_Msk (0x1UL << DSI_FIR0_FPE0_Pos)
20568#define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk
20569#define DSI_FIR0_FPE1_Pos (17U)
20570#define DSI_FIR0_FPE1_Msk (0x1UL << DSI_FIR0_FPE1_Pos)
20571#define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk
20572#define DSI_FIR0_FPE2_Pos (18U)
20573#define DSI_FIR0_FPE2_Msk (0x1UL << DSI_FIR0_FPE2_Pos)
20574#define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk
20575#define DSI_FIR0_FPE3_Pos (19U)
20576#define DSI_FIR0_FPE3_Msk (0x1UL << DSI_FIR0_FPE3_Pos)
20577#define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk
20578#define DSI_FIR0_FPE4_Pos (20U)
20579#define DSI_FIR0_FPE4_Msk (0x1UL << DSI_FIR0_FPE4_Pos)
20580#define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk
20582/******************* Bit definition for DSI_FIR1 register ***************/
20583#define DSI_FIR1_FTOHSTX_Pos (0U)
20584#define DSI_FIR1_FTOHSTX_Msk (0x1UL << DSI_FIR1_FTOHSTX_Pos)
20585#define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk
20586#define DSI_FIR1_FTOLPRX_Pos (1U)
20587#define DSI_FIR1_FTOLPRX_Msk (0x1UL << DSI_FIR1_FTOLPRX_Pos)
20588#define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk
20589#define DSI_FIR1_FECCSE_Pos (2U)
20590#define DSI_FIR1_FECCSE_Msk (0x1UL << DSI_FIR1_FECCSE_Pos)
20591#define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk
20592#define DSI_FIR1_FECCME_Pos (3U)
20593#define DSI_FIR1_FECCME_Msk (0x1UL << DSI_FIR1_FECCME_Pos)
20594#define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk
20595#define DSI_FIR1_FCRCE_Pos (4U)
20596#define DSI_FIR1_FCRCE_Msk (0x1UL << DSI_FIR1_FCRCE_Pos)
20597#define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk
20598#define DSI_FIR1_FPSE_Pos (5U)
20599#define DSI_FIR1_FPSE_Msk (0x1UL << DSI_FIR1_FPSE_Pos)
20600#define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk
20601#define DSI_FIR1_FEOTPE_Pos (6U)
20602#define DSI_FIR1_FEOTPE_Msk (0x1UL << DSI_FIR1_FEOTPE_Pos)
20603#define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk
20604#define DSI_FIR1_FLPWRE_Pos (7U)
20605#define DSI_FIR1_FLPWRE_Msk (0x1UL << DSI_FIR1_FLPWRE_Pos)
20606#define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk
20607#define DSI_FIR1_FGCWRE_Pos (8U)
20608#define DSI_FIR1_FGCWRE_Msk (0x1UL << DSI_FIR1_FGCWRE_Pos)
20609#define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk
20610#define DSI_FIR1_FGPWRE_Pos (9U)
20611#define DSI_FIR1_FGPWRE_Msk (0x1UL << DSI_FIR1_FGPWRE_Pos)
20612#define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk
20613#define DSI_FIR1_FGPTXE_Pos (10U)
20614#define DSI_FIR1_FGPTXE_Msk (0x1UL << DSI_FIR1_FGPTXE_Pos)
20615#define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk
20616#define DSI_FIR1_FGPRDE_Pos (11U)
20617#define DSI_FIR1_FGPRDE_Msk (0x1UL << DSI_FIR1_FGPRDE_Pos)
20618#define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk
20619#define DSI_FIR1_FGPRXE_Pos (12U)
20620#define DSI_FIR1_FGPRXE_Msk (0x1UL << DSI_FIR1_FGPRXE_Pos)
20621#define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk
20623/******************* Bit definition for DSI_VSCR register ***************/
20624#define DSI_VSCR_EN_Pos (0U)
20625#define DSI_VSCR_EN_Msk (0x1UL << DSI_VSCR_EN_Pos)
20626#define DSI_VSCR_EN DSI_VSCR_EN_Msk
20627#define DSI_VSCR_UR_Pos (8U)
20628#define DSI_VSCR_UR_Msk (0x1UL << DSI_VSCR_UR_Pos)
20629#define DSI_VSCR_UR DSI_VSCR_UR_Msk
20631/******************* Bit definition for DSI_LCVCIDR register ************/
20632#define DSI_LCVCIDR_VCID_Pos (0U)
20633#define DSI_LCVCIDR_VCID_Msk (0x3UL << DSI_LCVCIDR_VCID_Pos)
20634#define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk
20635#define DSI_LCVCIDR_VCID0_Pos (0U)
20636#define DSI_LCVCIDR_VCID0_Msk (0x1UL << DSI_LCVCIDR_VCID0_Pos)
20637#define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
20638#define DSI_LCVCIDR_VCID1_Pos (1U)
20639#define DSI_LCVCIDR_VCID1_Msk (0x1UL << DSI_LCVCIDR_VCID1_Pos)
20640#define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
20641
20642/******************* Bit definition for DSI_LCCCR register **************/
20643#define DSI_LCCCR_COLC_Pos (0U)
20644#define DSI_LCCCR_COLC_Msk (0xFUL << DSI_LCCCR_COLC_Pos)
20645#define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk
20646#define DSI_LCCCR_COLC0_Pos (0U)
20647#define DSI_LCCCR_COLC0_Msk (0x1UL << DSI_LCCCR_COLC0_Pos)
20648#define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
20649#define DSI_LCCCR_COLC1_Pos (1U)
20650#define DSI_LCCCR_COLC1_Msk (0x1UL << DSI_LCCCR_COLC1_Pos)
20651#define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
20652#define DSI_LCCCR_COLC2_Pos (2U)
20653#define DSI_LCCCR_COLC2_Msk (0x1UL << DSI_LCCCR_COLC2_Pos)
20654#define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
20655#define DSI_LCCCR_COLC3_Pos (3U)
20656#define DSI_LCCCR_COLC3_Msk (0x1UL << DSI_LCCCR_COLC3_Pos)
20657#define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
20658
20659#define DSI_LCCCR_LPE_Pos (8U)
20660#define DSI_LCCCR_LPE_Msk (0x1UL << DSI_LCCCR_LPE_Pos)
20661#define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk
20663/******************* Bit definition for DSI_LPMCCR register *************/
20664#define DSI_LPMCCR_VLPSIZE_Pos (0U)
20665#define DSI_LPMCCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos)
20666#define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk
20667#define DSI_LPMCCR_VLPSIZE0_Pos (0U)
20668#define DSI_LPMCCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos)
20669#define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
20670#define DSI_LPMCCR_VLPSIZE1_Pos (1U)
20671#define DSI_LPMCCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos)
20672#define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
20673#define DSI_LPMCCR_VLPSIZE2_Pos (2U)
20674#define DSI_LPMCCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos)
20675#define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
20676#define DSI_LPMCCR_VLPSIZE3_Pos (3U)
20677#define DSI_LPMCCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos)
20678#define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
20679#define DSI_LPMCCR_VLPSIZE4_Pos (4U)
20680#define DSI_LPMCCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos)
20681#define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
20682#define DSI_LPMCCR_VLPSIZE5_Pos (5U)
20683#define DSI_LPMCCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos)
20684#define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
20685#define DSI_LPMCCR_VLPSIZE6_Pos (6U)
20686#define DSI_LPMCCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos)
20687#define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
20688#define DSI_LPMCCR_VLPSIZE7_Pos (7U)
20689#define DSI_LPMCCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos)
20690#define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
20691
20692#define DSI_LPMCCR_LPSIZE_Pos (16U)
20693#define DSI_LPMCCR_LPSIZE_Msk (0xFFUL << DSI_LPMCCR_LPSIZE_Pos)
20694#define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk
20695#define DSI_LPMCCR_LPSIZE0_Pos (16U)
20696#define DSI_LPMCCR_LPSIZE0_Msk (0x1UL << DSI_LPMCCR_LPSIZE0_Pos)
20697#define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
20698#define DSI_LPMCCR_LPSIZE1_Pos (17U)
20699#define DSI_LPMCCR_LPSIZE1_Msk (0x1UL << DSI_LPMCCR_LPSIZE1_Pos)
20700#define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
20701#define DSI_LPMCCR_LPSIZE2_Pos (18U)
20702#define DSI_LPMCCR_LPSIZE2_Msk (0x1UL << DSI_LPMCCR_LPSIZE2_Pos)
20703#define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
20704#define DSI_LPMCCR_LPSIZE3_Pos (19U)
20705#define DSI_LPMCCR_LPSIZE3_Msk (0x1UL << DSI_LPMCCR_LPSIZE3_Pos)
20706#define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
20707#define DSI_LPMCCR_LPSIZE4_Pos (20U)
20708#define DSI_LPMCCR_LPSIZE4_Msk (0x1UL << DSI_LPMCCR_LPSIZE4_Pos)
20709#define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
20710#define DSI_LPMCCR_LPSIZE5_Pos (21U)
20711#define DSI_LPMCCR_LPSIZE5_Msk (0x1UL << DSI_LPMCCR_LPSIZE5_Pos)
20712#define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
20713#define DSI_LPMCCR_LPSIZE6_Pos (22U)
20714#define DSI_LPMCCR_LPSIZE6_Msk (0x1UL << DSI_LPMCCR_LPSIZE6_Pos)
20715#define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
20716#define DSI_LPMCCR_LPSIZE7_Pos (23U)
20717#define DSI_LPMCCR_LPSIZE7_Msk (0x1UL << DSI_LPMCCR_LPSIZE7_Pos)
20718#define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
20719
20720/******************* Bit definition for DSI_VMCCR register **************/
20721#define DSI_VMCCR_VMT_Pos (0U)
20722#define DSI_VMCCR_VMT_Msk (0x3UL << DSI_VMCCR_VMT_Pos)
20723#define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk
20724#define DSI_VMCCR_VMT0_Pos (0U)
20725#define DSI_VMCCR_VMT0_Msk (0x1UL << DSI_VMCCR_VMT0_Pos)
20726#define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
20727#define DSI_VMCCR_VMT1_Pos (1U)
20728#define DSI_VMCCR_VMT1_Msk (0x1UL << DSI_VMCCR_VMT1_Pos)
20729#define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
20730
20731#define DSI_VMCCR_LPVSAE_Pos (8U)
20732#define DSI_VMCCR_LPVSAE_Msk (0x1UL << DSI_VMCCR_LPVSAE_Pos)
20733#define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk
20734#define DSI_VMCCR_LPVBPE_Pos (9U)
20735#define DSI_VMCCR_LPVBPE_Msk (0x1UL << DSI_VMCCR_LPVBPE_Pos)
20736#define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk
20737#define DSI_VMCCR_LPVFPE_Pos (10U)
20738#define DSI_VMCCR_LPVFPE_Msk (0x1UL << DSI_VMCCR_LPVFPE_Pos)
20739#define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk
20740#define DSI_VMCCR_LPVAE_Pos (11U)
20741#define DSI_VMCCR_LPVAE_Msk (0x1UL << DSI_VMCCR_LPVAE_Pos)
20742#define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk
20743#define DSI_VMCCR_LPHBPE_Pos (12U)
20744#define DSI_VMCCR_LPHBPE_Msk (0x1UL << DSI_VMCCR_LPHBPE_Pos)
20745#define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk
20746#define DSI_VMCCR_LPHFE_Pos (13U)
20747#define DSI_VMCCR_LPHFE_Msk (0x1UL << DSI_VMCCR_LPHFE_Pos)
20748#define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk
20749#define DSI_VMCCR_FBTAAE_Pos (14U)
20750#define DSI_VMCCR_FBTAAE_Msk (0x1UL << DSI_VMCCR_FBTAAE_Pos)
20751#define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk
20752#define DSI_VMCCR_LPCE_Pos (15U)
20753#define DSI_VMCCR_LPCE_Msk (0x1UL << DSI_VMCCR_LPCE_Pos)
20754#define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk
20756/******************* Bit definition for DSI_VPCCR register **************/
20757#define DSI_VPCCR_VPSIZE_Pos (0U)
20758#define DSI_VPCCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos)
20759#define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk
20760#define DSI_VPCCR_VPSIZE0_Pos (0U)
20761#define DSI_VPCCR_VPSIZE0_Msk (0x1UL << DSI_VPCCR_VPSIZE0_Pos)
20762#define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
20763#define DSI_VPCCR_VPSIZE1_Pos (1U)
20764#define DSI_VPCCR_VPSIZE1_Msk (0x1UL << DSI_VPCCR_VPSIZE1_Pos)
20765#define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
20766#define DSI_VPCCR_VPSIZE2_Pos (2U)
20767#define DSI_VPCCR_VPSIZE2_Msk (0x1UL << DSI_VPCCR_VPSIZE2_Pos)
20768#define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
20769#define DSI_VPCCR_VPSIZE3_Pos (3U)
20770#define DSI_VPCCR_VPSIZE3_Msk (0x1UL << DSI_VPCCR_VPSIZE3_Pos)
20771#define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
20772#define DSI_VPCCR_VPSIZE4_Pos (4U)
20773#define DSI_VPCCR_VPSIZE4_Msk (0x1UL << DSI_VPCCR_VPSIZE4_Pos)
20774#define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
20775#define DSI_VPCCR_VPSIZE5_Pos (5U)
20776#define DSI_VPCCR_VPSIZE5_Msk (0x1UL << DSI_VPCCR_VPSIZE5_Pos)
20777#define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
20778#define DSI_VPCCR_VPSIZE6_Pos (6U)
20779#define DSI_VPCCR_VPSIZE6_Msk (0x1UL << DSI_VPCCR_VPSIZE6_Pos)
20780#define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
20781#define DSI_VPCCR_VPSIZE7_Pos (7U)
20782#define DSI_VPCCR_VPSIZE7_Msk (0x1UL << DSI_VPCCR_VPSIZE7_Pos)
20783#define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
20784#define DSI_VPCCR_VPSIZE8_Pos (8U)
20785#define DSI_VPCCR_VPSIZE8_Msk (0x1UL << DSI_VPCCR_VPSIZE8_Pos)
20786#define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
20787#define DSI_VPCCR_VPSIZE9_Pos (9U)
20788#define DSI_VPCCR_VPSIZE9_Msk (0x1UL << DSI_VPCCR_VPSIZE9_Pos)
20789#define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
20790#define DSI_VPCCR_VPSIZE10_Pos (10U)
20791#define DSI_VPCCR_VPSIZE10_Msk (0x1UL << DSI_VPCCR_VPSIZE10_Pos)
20792#define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
20793#define DSI_VPCCR_VPSIZE11_Pos (11U)
20794#define DSI_VPCCR_VPSIZE11_Msk (0x1UL << DSI_VPCCR_VPSIZE11_Pos)
20795#define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
20796#define DSI_VPCCR_VPSIZE12_Pos (12U)
20797#define DSI_VPCCR_VPSIZE12_Msk (0x1UL << DSI_VPCCR_VPSIZE12_Pos)
20798#define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
20799#define DSI_VPCCR_VPSIZE13_Pos (13U)
20800#define DSI_VPCCR_VPSIZE13_Msk (0x1UL << DSI_VPCCR_VPSIZE13_Pos)
20801#define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
20802
20803/******************* Bit definition for DSI_VCCCR register **************/
20804#define DSI_VCCCR_NUMC_Pos (0U)
20805#define DSI_VCCCR_NUMC_Msk (0x1FFFUL << DSI_VCCCR_NUMC_Pos)
20806#define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk
20807#define DSI_VCCCR_NUMC0_Pos (0U)
20808#define DSI_VCCCR_NUMC0_Msk (0x1UL << DSI_VCCCR_NUMC0_Pos)
20809#define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
20810#define DSI_VCCCR_NUMC1_Pos (1U)
20811#define DSI_VCCCR_NUMC1_Msk (0x1UL << DSI_VCCCR_NUMC1_Pos)
20812#define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
20813#define DSI_VCCCR_NUMC2_Pos (2U)
20814#define DSI_VCCCR_NUMC2_Msk (0x1UL << DSI_VCCCR_NUMC2_Pos)
20815#define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
20816#define DSI_VCCCR_NUMC3_Pos (3U)
20817#define DSI_VCCCR_NUMC3_Msk (0x1UL << DSI_VCCCR_NUMC3_Pos)
20818#define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
20819#define DSI_VCCCR_NUMC4_Pos (4U)
20820#define DSI_VCCCR_NUMC4_Msk (0x1UL << DSI_VCCCR_NUMC4_Pos)
20821#define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
20822#define DSI_VCCCR_NUMC5_Pos (5U)
20823#define DSI_VCCCR_NUMC5_Msk (0x1UL << DSI_VCCCR_NUMC5_Pos)
20824#define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
20825#define DSI_VCCCR_NUMC6_Pos (6U)
20826#define DSI_VCCCR_NUMC6_Msk (0x1UL << DSI_VCCCR_NUMC6_Pos)
20827#define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
20828#define DSI_VCCCR_NUMC7_Pos (7U)
20829#define DSI_VCCCR_NUMC7_Msk (0x1UL << DSI_VCCCR_NUMC7_Pos)
20830#define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
20831#define DSI_VCCCR_NUMC8_Pos (8U)
20832#define DSI_VCCCR_NUMC8_Msk (0x1UL << DSI_VCCCR_NUMC8_Pos)
20833#define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
20834#define DSI_VCCCR_NUMC9_Pos (9U)
20835#define DSI_VCCCR_NUMC9_Msk (0x1UL << DSI_VCCCR_NUMC9_Pos)
20836#define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
20837#define DSI_VCCCR_NUMC10_Pos (10U)
20838#define DSI_VCCCR_NUMC10_Msk (0x1UL << DSI_VCCCR_NUMC10_Pos)
20839#define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
20840#define DSI_VCCCR_NUMC11_Pos (11U)
20841#define DSI_VCCCR_NUMC11_Msk (0x1UL << DSI_VCCCR_NUMC11_Pos)
20842#define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
20843#define DSI_VCCCR_NUMC12_Pos (12U)
20844#define DSI_VCCCR_NUMC12_Msk (0x1UL << DSI_VCCCR_NUMC12_Pos)
20845#define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
20846
20847/******************* Bit definition for DSI_VNPCCR register *************/
20848#define DSI_VNPCCR_NPSIZE_Pos (0U)
20849#define DSI_VNPCCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos)
20850#define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk
20851#define DSI_VNPCCR_NPSIZE0_Pos (0U)
20852#define DSI_VNPCCR_NPSIZE0_Msk (0x1UL << DSI_VNPCCR_NPSIZE0_Pos)
20853#define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
20854#define DSI_VNPCCR_NPSIZE1_Pos (1U)
20855#define DSI_VNPCCR_NPSIZE1_Msk (0x1UL << DSI_VNPCCR_NPSIZE1_Pos)
20856#define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
20857#define DSI_VNPCCR_NPSIZE2_Pos (2U)
20858#define DSI_VNPCCR_NPSIZE2_Msk (0x1UL << DSI_VNPCCR_NPSIZE2_Pos)
20859#define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
20860#define DSI_VNPCCR_NPSIZE3_Pos (3U)
20861#define DSI_VNPCCR_NPSIZE3_Msk (0x1UL << DSI_VNPCCR_NPSIZE3_Pos)
20862#define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
20863#define DSI_VNPCCR_NPSIZE4_Pos (4U)
20864#define DSI_VNPCCR_NPSIZE4_Msk (0x1UL << DSI_VNPCCR_NPSIZE4_Pos)
20865#define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
20866#define DSI_VNPCCR_NPSIZE5_Pos (5U)
20867#define DSI_VNPCCR_NPSIZE5_Msk (0x1UL << DSI_VNPCCR_NPSIZE5_Pos)
20868#define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
20869#define DSI_VNPCCR_NPSIZE6_Pos (6U)
20870#define DSI_VNPCCR_NPSIZE6_Msk (0x1UL << DSI_VNPCCR_NPSIZE6_Pos)
20871#define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
20872#define DSI_VNPCCR_NPSIZE7_Pos (7U)
20873#define DSI_VNPCCR_NPSIZE7_Msk (0x1UL << DSI_VNPCCR_NPSIZE7_Pos)
20874#define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
20875#define DSI_VNPCCR_NPSIZE8_Pos (8U)
20876#define DSI_VNPCCR_NPSIZE8_Msk (0x1UL << DSI_VNPCCR_NPSIZE8_Pos)
20877#define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
20878#define DSI_VNPCCR_NPSIZE9_Pos (9U)
20879#define DSI_VNPCCR_NPSIZE9_Msk (0x1UL << DSI_VNPCCR_NPSIZE9_Pos)
20880#define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
20881#define DSI_VNPCCR_NPSIZE10_Pos (10U)
20882#define DSI_VNPCCR_NPSIZE10_Msk (0x1UL << DSI_VNPCCR_NPSIZE10_Pos)
20883#define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
20884#define DSI_VNPCCR_NPSIZE11_Pos (11U)
20885#define DSI_VNPCCR_NPSIZE11_Msk (0x1UL << DSI_VNPCCR_NPSIZE11_Pos)
20886#define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
20887#define DSI_VNPCCR_NPSIZE12_Pos (12U)
20888#define DSI_VNPCCR_NPSIZE12_Msk (0x1UL << DSI_VNPCCR_NPSIZE12_Pos)
20889#define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
20890
20891/******************* Bit definition for DSI_VHSACCR register ************/
20892#define DSI_VHSACCR_HSA_Pos (0U)
20893#define DSI_VHSACCR_HSA_Msk (0xFFFUL << DSI_VHSACCR_HSA_Pos)
20894#define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk
20895#define DSI_VHSACCR_HSA0_Pos (0U)
20896#define DSI_VHSACCR_HSA0_Msk (0x1UL << DSI_VHSACCR_HSA0_Pos)
20897#define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
20898#define DSI_VHSACCR_HSA1_Pos (1U)
20899#define DSI_VHSACCR_HSA1_Msk (0x1UL << DSI_VHSACCR_HSA1_Pos)
20900#define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
20901#define DSI_VHSACCR_HSA2_Pos (2U)
20902#define DSI_VHSACCR_HSA2_Msk (0x1UL << DSI_VHSACCR_HSA2_Pos)
20903#define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
20904#define DSI_VHSACCR_HSA3_Pos (3U)
20905#define DSI_VHSACCR_HSA3_Msk (0x1UL << DSI_VHSACCR_HSA3_Pos)
20906#define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
20907#define DSI_VHSACCR_HSA4_Pos (4U)
20908#define DSI_VHSACCR_HSA4_Msk (0x1UL << DSI_VHSACCR_HSA4_Pos)
20909#define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
20910#define DSI_VHSACCR_HSA5_Pos (5U)
20911#define DSI_VHSACCR_HSA5_Msk (0x1UL << DSI_VHSACCR_HSA5_Pos)
20912#define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
20913#define DSI_VHSACCR_HSA6_Pos (6U)
20914#define DSI_VHSACCR_HSA6_Msk (0x1UL << DSI_VHSACCR_HSA6_Pos)
20915#define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
20916#define DSI_VHSACCR_HSA7_Pos (7U)
20917#define DSI_VHSACCR_HSA7_Msk (0x1UL << DSI_VHSACCR_HSA7_Pos)
20918#define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
20919#define DSI_VHSACCR_HSA8_Pos (8U)
20920#define DSI_VHSACCR_HSA8_Msk (0x1UL << DSI_VHSACCR_HSA8_Pos)
20921#define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
20922#define DSI_VHSACCR_HSA9_Pos (9U)
20923#define DSI_VHSACCR_HSA9_Msk (0x1UL << DSI_VHSACCR_HSA9_Pos)
20924#define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
20925#define DSI_VHSACCR_HSA10_Pos (10U)
20926#define DSI_VHSACCR_HSA10_Msk (0x1UL << DSI_VHSACCR_HSA10_Pos)
20927#define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
20928#define DSI_VHSACCR_HSA11_Pos (11U)
20929#define DSI_VHSACCR_HSA11_Msk (0x1UL << DSI_VHSACCR_HSA11_Pos)
20930#define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
20931
20932/******************* Bit definition for DSI_VHBPCCR register ************/
20933#define DSI_VHBPCCR_HBP_Pos (0U)
20934#define DSI_VHBPCCR_HBP_Msk (0xFFFUL << DSI_VHBPCCR_HBP_Pos)
20935#define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk
20936#define DSI_VHBPCCR_HBP0_Pos (0U)
20937#define DSI_VHBPCCR_HBP0_Msk (0x1UL << DSI_VHBPCCR_HBP0_Pos)
20938#define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
20939#define DSI_VHBPCCR_HBP1_Pos (1U)
20940#define DSI_VHBPCCR_HBP1_Msk (0x1UL << DSI_VHBPCCR_HBP1_Pos)
20941#define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
20942#define DSI_VHBPCCR_HBP2_Pos (2U)
20943#define DSI_VHBPCCR_HBP2_Msk (0x1UL << DSI_VHBPCCR_HBP2_Pos)
20944#define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
20945#define DSI_VHBPCCR_HBP3_Pos (3U)
20946#define DSI_VHBPCCR_HBP3_Msk (0x1UL << DSI_VHBPCCR_HBP3_Pos)
20947#define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
20948#define DSI_VHBPCCR_HBP4_Pos (4U)
20949#define DSI_VHBPCCR_HBP4_Msk (0x1UL << DSI_VHBPCCR_HBP4_Pos)
20950#define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
20951#define DSI_VHBPCCR_HBP5_Pos (5U)
20952#define DSI_VHBPCCR_HBP5_Msk (0x1UL << DSI_VHBPCCR_HBP5_Pos)
20953#define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
20954#define DSI_VHBPCCR_HBP6_Pos (6U)
20955#define DSI_VHBPCCR_HBP6_Msk (0x1UL << DSI_VHBPCCR_HBP6_Pos)
20956#define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
20957#define DSI_VHBPCCR_HBP7_Pos (7U)
20958#define DSI_VHBPCCR_HBP7_Msk (0x1UL << DSI_VHBPCCR_HBP7_Pos)
20959#define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
20960#define DSI_VHBPCCR_HBP8_Pos (8U)
20961#define DSI_VHBPCCR_HBP8_Msk (0x1UL << DSI_VHBPCCR_HBP8_Pos)
20962#define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
20963#define DSI_VHBPCCR_HBP9_Pos (9U)
20964#define DSI_VHBPCCR_HBP9_Msk (0x1UL << DSI_VHBPCCR_HBP9_Pos)
20965#define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
20966#define DSI_VHBPCCR_HBP10_Pos (10U)
20967#define DSI_VHBPCCR_HBP10_Msk (0x1UL << DSI_VHBPCCR_HBP10_Pos)
20968#define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
20969#define DSI_VHBPCCR_HBP11_Pos (11U)
20970#define DSI_VHBPCCR_HBP11_Msk (0x1UL << DSI_VHBPCCR_HBP11_Pos)
20971#define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
20972
20973/******************* Bit definition for DSI_VLCCR register **************/
20974#define DSI_VLCCR_HLINE_Pos (0U)
20975#define DSI_VLCCR_HLINE_Msk (0x7FFFUL << DSI_VLCCR_HLINE_Pos)
20976#define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk
20977#define DSI_VLCCR_HLINE0_Pos (0U)
20978#define DSI_VLCCR_HLINE0_Msk (0x1UL << DSI_VLCCR_HLINE0_Pos)
20979#define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
20980#define DSI_VLCCR_HLINE1_Pos (1U)
20981#define DSI_VLCCR_HLINE1_Msk (0x1UL << DSI_VLCCR_HLINE1_Pos)
20982#define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
20983#define DSI_VLCCR_HLINE2_Pos (2U)
20984#define DSI_VLCCR_HLINE2_Msk (0x1UL << DSI_VLCCR_HLINE2_Pos)
20985#define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
20986#define DSI_VLCCR_HLINE3_Pos (3U)
20987#define DSI_VLCCR_HLINE3_Msk (0x1UL << DSI_VLCCR_HLINE3_Pos)
20988#define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
20989#define DSI_VLCCR_HLINE4_Pos (4U)
20990#define DSI_VLCCR_HLINE4_Msk (0x1UL << DSI_VLCCR_HLINE4_Pos)
20991#define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
20992#define DSI_VLCCR_HLINE5_Pos (5U)
20993#define DSI_VLCCR_HLINE5_Msk (0x1UL << DSI_VLCCR_HLINE5_Pos)
20994#define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
20995#define DSI_VLCCR_HLINE6_Pos (6U)
20996#define DSI_VLCCR_HLINE6_Msk (0x1UL << DSI_VLCCR_HLINE6_Pos)
20997#define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
20998#define DSI_VLCCR_HLINE7_Pos (7U)
20999#define DSI_VLCCR_HLINE7_Msk (0x1UL << DSI_VLCCR_HLINE7_Pos)
21000#define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
21001#define DSI_VLCCR_HLINE8_Pos (8U)
21002#define DSI_VLCCR_HLINE8_Msk (0x1UL << DSI_VLCCR_HLINE8_Pos)
21003#define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
21004#define DSI_VLCCR_HLINE9_Pos (9U)
21005#define DSI_VLCCR_HLINE9_Msk (0x1UL << DSI_VLCCR_HLINE9_Pos)
21006#define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
21007#define DSI_VLCCR_HLINE10_Pos (10U)
21008#define DSI_VLCCR_HLINE10_Msk (0x1UL << DSI_VLCCR_HLINE10_Pos)
21009#define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
21010#define DSI_VLCCR_HLINE11_Pos (11U)
21011#define DSI_VLCCR_HLINE11_Msk (0x1UL << DSI_VLCCR_HLINE11_Pos)
21012#define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
21013#define DSI_VLCCR_HLINE12_Pos (12U)
21014#define DSI_VLCCR_HLINE12_Msk (0x1UL << DSI_VLCCR_HLINE12_Pos)
21015#define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
21016#define DSI_VLCCR_HLINE13_Pos (13U)
21017#define DSI_VLCCR_HLINE13_Msk (0x1UL << DSI_VLCCR_HLINE13_Pos)
21018#define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
21019#define DSI_VLCCR_HLINE14_Pos (14U)
21020#define DSI_VLCCR_HLINE14_Msk (0x1UL << DSI_VLCCR_HLINE14_Pos)
21021#define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
21022
21023/******************* Bit definition for DSI_VVSACCR register ***************/
21024#define DSI_VVSACCR_VSA_Pos (0U)
21025#define DSI_VVSACCR_VSA_Msk (0x3FFUL << DSI_VVSACCR_VSA_Pos)
21026#define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk
21027#define DSI_VVSACCR_VSA0_Pos (0U)
21028#define DSI_VVSACCR_VSA0_Msk (0x1UL << DSI_VVSACCR_VSA0_Pos)
21029#define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
21030#define DSI_VVSACCR_VSA1_Pos (1U)
21031#define DSI_VVSACCR_VSA1_Msk (0x1UL << DSI_VVSACCR_VSA1_Pos)
21032#define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
21033#define DSI_VVSACCR_VSA2_Pos (2U)
21034#define DSI_VVSACCR_VSA2_Msk (0x1UL << DSI_VVSACCR_VSA2_Pos)
21035#define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
21036#define DSI_VVSACCR_VSA3_Pos (3U)
21037#define DSI_VVSACCR_VSA3_Msk (0x1UL << DSI_VVSACCR_VSA3_Pos)
21038#define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
21039#define DSI_VVSACCR_VSA4_Pos (4U)
21040#define DSI_VVSACCR_VSA4_Msk (0x1UL << DSI_VVSACCR_VSA4_Pos)
21041#define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
21042#define DSI_VVSACCR_VSA5_Pos (5U)
21043#define DSI_VVSACCR_VSA5_Msk (0x1UL << DSI_VVSACCR_VSA5_Pos)
21044#define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
21045#define DSI_VVSACCR_VSA6_Pos (6U)
21046#define DSI_VVSACCR_VSA6_Msk (0x1UL << DSI_VVSACCR_VSA6_Pos)
21047#define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
21048#define DSI_VVSACCR_VSA7_Pos (7U)
21049#define DSI_VVSACCR_VSA7_Msk (0x1UL << DSI_VVSACCR_VSA7_Pos)
21050#define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
21051#define DSI_VVSACCR_VSA8_Pos (8U)
21052#define DSI_VVSACCR_VSA8_Msk (0x1UL << DSI_VVSACCR_VSA8_Pos)
21053#define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
21054#define DSI_VVSACCR_VSA9_Pos (9U)
21055#define DSI_VVSACCR_VSA9_Msk (0x1UL << DSI_VVSACCR_VSA9_Pos)
21056#define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
21057
21058/******************* Bit definition for DSI_VVBPCCR register ************/
21059#define DSI_VVBPCCR_VBP_Pos (0U)
21060#define DSI_VVBPCCR_VBP_Msk (0x3FFUL << DSI_VVBPCCR_VBP_Pos)
21061#define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk
21062#define DSI_VVBPCCR_VBP0_Pos (0U)
21063#define DSI_VVBPCCR_VBP0_Msk (0x1UL << DSI_VVBPCCR_VBP0_Pos)
21064#define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
21065#define DSI_VVBPCCR_VBP1_Pos (1U)
21066#define DSI_VVBPCCR_VBP1_Msk (0x1UL << DSI_VVBPCCR_VBP1_Pos)
21067#define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
21068#define DSI_VVBPCCR_VBP2_Pos (2U)
21069#define DSI_VVBPCCR_VBP2_Msk (0x1UL << DSI_VVBPCCR_VBP2_Pos)
21070#define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
21071#define DSI_VVBPCCR_VBP3_Pos (3U)
21072#define DSI_VVBPCCR_VBP3_Msk (0x1UL << DSI_VVBPCCR_VBP3_Pos)
21073#define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
21074#define DSI_VVBPCCR_VBP4_Pos (4U)
21075#define DSI_VVBPCCR_VBP4_Msk (0x1UL << DSI_VVBPCCR_VBP4_Pos)
21076#define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
21077#define DSI_VVBPCCR_VBP5_Pos (5U)
21078#define DSI_VVBPCCR_VBP5_Msk (0x1UL << DSI_VVBPCCR_VBP5_Pos)
21079#define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
21080#define DSI_VVBPCCR_VBP6_Pos (6U)
21081#define DSI_VVBPCCR_VBP6_Msk (0x1UL << DSI_VVBPCCR_VBP6_Pos)
21082#define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
21083#define DSI_VVBPCCR_VBP7_Pos (7U)
21084#define DSI_VVBPCCR_VBP7_Msk (0x1UL << DSI_VVBPCCR_VBP7_Pos)
21085#define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
21086#define DSI_VVBPCCR_VBP8_Pos (8U)
21087#define DSI_VVBPCCR_VBP8_Msk (0x1UL << DSI_VVBPCCR_VBP8_Pos)
21088#define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
21089#define DSI_VVBPCCR_VBP9_Pos (9U)
21090#define DSI_VVBPCCR_VBP9_Msk (0x1UL << DSI_VVBPCCR_VBP9_Pos)
21091#define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
21092
21093/******************* Bit definition for DSI_VVFPCCR register ************/
21094#define DSI_VVFPCCR_VFP_Pos (0U)
21095#define DSI_VVFPCCR_VFP_Msk (0x3FFUL << DSI_VVFPCCR_VFP_Pos)
21096#define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk
21097#define DSI_VVFPCCR_VFP0_Pos (0U)
21098#define DSI_VVFPCCR_VFP0_Msk (0x1UL << DSI_VVFPCCR_VFP0_Pos)
21099#define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
21100#define DSI_VVFPCCR_VFP1_Pos (1U)
21101#define DSI_VVFPCCR_VFP1_Msk (0x1UL << DSI_VVFPCCR_VFP1_Pos)
21102#define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
21103#define DSI_VVFPCCR_VFP2_Pos (2U)
21104#define DSI_VVFPCCR_VFP2_Msk (0x1UL << DSI_VVFPCCR_VFP2_Pos)
21105#define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
21106#define DSI_VVFPCCR_VFP3_Pos (3U)
21107#define DSI_VVFPCCR_VFP3_Msk (0x1UL << DSI_VVFPCCR_VFP3_Pos)
21108#define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
21109#define DSI_VVFPCCR_VFP4_Pos (4U)
21110#define DSI_VVFPCCR_VFP4_Msk (0x1UL << DSI_VVFPCCR_VFP4_Pos)
21111#define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
21112#define DSI_VVFPCCR_VFP5_Pos (5U)
21113#define DSI_VVFPCCR_VFP5_Msk (0x1UL << DSI_VVFPCCR_VFP5_Pos)
21114#define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
21115#define DSI_VVFPCCR_VFP6_Pos (6U)
21116#define DSI_VVFPCCR_VFP6_Msk (0x1UL << DSI_VVFPCCR_VFP6_Pos)
21117#define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
21118#define DSI_VVFPCCR_VFP7_Pos (7U)
21119#define DSI_VVFPCCR_VFP7_Msk (0x1UL << DSI_VVFPCCR_VFP7_Pos)
21120#define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
21121#define DSI_VVFPCCR_VFP8_Pos (8U)
21122#define DSI_VVFPCCR_VFP8_Msk (0x1UL << DSI_VVFPCCR_VFP8_Pos)
21123#define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
21124#define DSI_VVFPCCR_VFP9_Pos (9U)
21125#define DSI_VVFPCCR_VFP9_Msk (0x1UL << DSI_VVFPCCR_VFP9_Pos)
21126#define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
21127
21128/******************* Bit definition for DSI_VVACCR register *************/
21129#define DSI_VVACCR_VA_Pos (0U)
21130#define DSI_VVACCR_VA_Msk (0x3FFFUL << DSI_VVACCR_VA_Pos)
21131#define DSI_VVACCR_VA DSI_VVACCR_VA_Msk
21132#define DSI_VVACCR_VA0_Pos (0U)
21133#define DSI_VVACCR_VA0_Msk (0x1UL << DSI_VVACCR_VA0_Pos)
21134#define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
21135#define DSI_VVACCR_VA1_Pos (1U)
21136#define DSI_VVACCR_VA1_Msk (0x1UL << DSI_VVACCR_VA1_Pos)
21137#define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
21138#define DSI_VVACCR_VA2_Pos (2U)
21139#define DSI_VVACCR_VA2_Msk (0x1UL << DSI_VVACCR_VA2_Pos)
21140#define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
21141#define DSI_VVACCR_VA3_Pos (3U)
21142#define DSI_VVACCR_VA3_Msk (0x1UL << DSI_VVACCR_VA3_Pos)
21143#define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
21144#define DSI_VVACCR_VA4_Pos (4U)
21145#define DSI_VVACCR_VA4_Msk (0x1UL << DSI_VVACCR_VA4_Pos)
21146#define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
21147#define DSI_VVACCR_VA5_Pos (5U)
21148#define DSI_VVACCR_VA5_Msk (0x1UL << DSI_VVACCR_VA5_Pos)
21149#define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
21150#define DSI_VVACCR_VA6_Pos (6U)
21151#define DSI_VVACCR_VA6_Msk (0x1UL << DSI_VVACCR_VA6_Pos)
21152#define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
21153#define DSI_VVACCR_VA7_Pos (7U)
21154#define DSI_VVACCR_VA7_Msk (0x1UL << DSI_VVACCR_VA7_Pos)
21155#define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
21156#define DSI_VVACCR_VA8_Pos (8U)
21157#define DSI_VVACCR_VA8_Msk (0x1UL << DSI_VVACCR_VA8_Pos)
21158#define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
21159#define DSI_VVACCR_VA9_Pos (9U)
21160#define DSI_VVACCR_VA9_Msk (0x1UL << DSI_VVACCR_VA9_Pos)
21161#define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
21162#define DSI_VVACCR_VA10_Pos (10U)
21163#define DSI_VVACCR_VA10_Msk (0x1UL << DSI_VVACCR_VA10_Pos)
21164#define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
21165#define DSI_VVACCR_VA11_Pos (11U)
21166#define DSI_VVACCR_VA11_Msk (0x1UL << DSI_VVACCR_VA11_Pos)
21167#define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
21168#define DSI_VVACCR_VA12_Pos (12U)
21169#define DSI_VVACCR_VA12_Msk (0x1UL << DSI_VVACCR_VA12_Pos)
21170#define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
21171#define DSI_VVACCR_VA13_Pos (13U)
21172#define DSI_VVACCR_VA13_Msk (0x1UL << DSI_VVACCR_VA13_Pos)
21173#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
21174
21175/******************* Bit definition for DSI_TDCCR register **************/
21176#define DSI_TDCCR_3DM 0x00000003U
21177#define DSI_TDCCR_3DM0 0x00000001U
21178#define DSI_TDCCR_3DM1 0x00000002U
21179
21180#define DSI_TDCCR_3DF 0x0000000CU
21181#define DSI_TDCCR_3DF0 0x00000004U
21182#define DSI_TDCCR_3DF1 0x00000008U
21183
21184#define DSI_TDCCR_SVS_Pos (4U)
21185#define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos)
21186#define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk
21187#define DSI_TDCCR_RF_Pos (5U)
21188#define DSI_TDCCR_RF_Msk (0x1UL << DSI_TDCCR_RF_Pos)
21189#define DSI_TDCCR_RF DSI_TDCCR_RF_Msk
21190#define DSI_TDCCR_S3DC_Pos (16U)
21191#define DSI_TDCCR_S3DC_Msk (0x1UL << DSI_TDCCR_S3DC_Pos)
21192#define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk
21194/******************* Bit definition for DSI_WCFGR register ***************/
21195#define DSI_WCFGR_DSIM_Pos (0U)
21196#define DSI_WCFGR_DSIM_Msk (0x1UL << DSI_WCFGR_DSIM_Pos)
21197#define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk
21198#define DSI_WCFGR_COLMUX_Pos (1U)
21199#define DSI_WCFGR_COLMUX_Msk (0x7UL << DSI_WCFGR_COLMUX_Pos)
21200#define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk
21201#define DSI_WCFGR_COLMUX0_Pos (1U)
21202#define DSI_WCFGR_COLMUX0_Msk (0x1UL << DSI_WCFGR_COLMUX0_Pos)
21203#define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
21204#define DSI_WCFGR_COLMUX1_Pos (2U)
21205#define DSI_WCFGR_COLMUX1_Msk (0x1UL << DSI_WCFGR_COLMUX1_Pos)
21206#define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
21207#define DSI_WCFGR_COLMUX2_Pos (3U)
21208#define DSI_WCFGR_COLMUX2_Msk (0x1UL << DSI_WCFGR_COLMUX2_Pos)
21209#define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
21210
21211#define DSI_WCFGR_TESRC_Pos (4U)
21212#define DSI_WCFGR_TESRC_Msk (0x1UL << DSI_WCFGR_TESRC_Pos)
21213#define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk
21214#define DSI_WCFGR_TEPOL_Pos (5U)
21215#define DSI_WCFGR_TEPOL_Msk (0x1UL << DSI_WCFGR_TEPOL_Pos)
21216#define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk
21217#define DSI_WCFGR_AR_Pos (6U)
21218#define DSI_WCFGR_AR_Msk (0x1UL << DSI_WCFGR_AR_Pos)
21219#define DSI_WCFGR_AR DSI_WCFGR_AR_Msk
21220#define DSI_WCFGR_VSPOL_Pos (7U)
21221#define DSI_WCFGR_VSPOL_Msk (0x1UL << DSI_WCFGR_VSPOL_Pos)
21222#define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk
21224/******************* Bit definition for DSI_WCR register *****************/
21225#define DSI_WCR_COLM_Pos (0U)
21226#define DSI_WCR_COLM_Msk (0x1UL << DSI_WCR_COLM_Pos)
21227#define DSI_WCR_COLM DSI_WCR_COLM_Msk
21228#define DSI_WCR_SHTDN_Pos (1U)
21229#define DSI_WCR_SHTDN_Msk (0x1UL << DSI_WCR_SHTDN_Pos)
21230#define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk
21231#define DSI_WCR_LTDCEN_Pos (2U)
21232#define DSI_WCR_LTDCEN_Msk (0x1UL << DSI_WCR_LTDCEN_Pos)
21233#define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk
21234#define DSI_WCR_DSIEN_Pos (3U)
21235#define DSI_WCR_DSIEN_Msk (0x1UL << DSI_WCR_DSIEN_Pos)
21236#define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk
21238/******************* Bit definition for DSI_WIER register ****************/
21239#define DSI_WIER_TEIE_Pos (0U)
21240#define DSI_WIER_TEIE_Msk (0x1UL << DSI_WIER_TEIE_Pos)
21241#define DSI_WIER_TEIE DSI_WIER_TEIE_Msk
21242#define DSI_WIER_ERIE_Pos (1U)
21243#define DSI_WIER_ERIE_Msk (0x1UL << DSI_WIER_ERIE_Pos)
21244#define DSI_WIER_ERIE DSI_WIER_ERIE_Msk
21245#define DSI_WIER_PLLLIE_Pos (9U)
21246#define DSI_WIER_PLLLIE_Msk (0x1UL << DSI_WIER_PLLLIE_Pos)
21247#define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk
21248#define DSI_WIER_PLLUIE_Pos (10U)
21249#define DSI_WIER_PLLUIE_Msk (0x1UL << DSI_WIER_PLLUIE_Pos)
21250#define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk
21251#define DSI_WIER_RRIE_Pos (13U)
21252#define DSI_WIER_RRIE_Msk (0x1UL << DSI_WIER_RRIE_Pos)
21253#define DSI_WIER_RRIE DSI_WIER_RRIE_Msk
21255/******************* Bit definition for DSI_WISR register ****************/
21256#define DSI_WISR_TEIF_Pos (0U)
21257#define DSI_WISR_TEIF_Msk (0x1UL << DSI_WISR_TEIF_Pos)
21258#define DSI_WISR_TEIF DSI_WISR_TEIF_Msk
21259#define DSI_WISR_ERIF_Pos (1U)
21260#define DSI_WISR_ERIF_Msk (0x1UL << DSI_WISR_ERIF_Pos)
21261#define DSI_WISR_ERIF DSI_WISR_ERIF_Msk
21262#define DSI_WISR_BUSY_Pos (2U)
21263#define DSI_WISR_BUSY_Msk (0x1UL << DSI_WISR_BUSY_Pos)
21264#define DSI_WISR_BUSY DSI_WISR_BUSY_Msk
21265#define DSI_WISR_PLLLS_Pos (8U)
21266#define DSI_WISR_PLLLS_Msk (0x1UL << DSI_WISR_PLLLS_Pos)
21267#define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk
21268#define DSI_WISR_PLLLIF_Pos (9U)
21269#define DSI_WISR_PLLLIF_Msk (0x1UL << DSI_WISR_PLLLIF_Pos)
21270#define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk
21271#define DSI_WISR_PLLUIF_Pos (10U)
21272#define DSI_WISR_PLLUIF_Msk (0x1UL << DSI_WISR_PLLUIF_Pos)
21273#define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk
21274#define DSI_WISR_RRS_Pos (12U)
21275#define DSI_WISR_RRS_Msk (0x1UL << DSI_WISR_RRS_Pos)
21276#define DSI_WISR_RRS DSI_WISR_RRS_Msk
21277#define DSI_WISR_RRIF_Pos (13U)
21278#define DSI_WISR_RRIF_Msk (0x1UL << DSI_WISR_RRIF_Pos)
21279#define DSI_WISR_RRIF DSI_WISR_RRIF_Msk
21281/******************* Bit definition for DSI_WIFCR register ***************/
21282#define DSI_WIFCR_CTEIF_Pos (0U)
21283#define DSI_WIFCR_CTEIF_Msk (0x1UL << DSI_WIFCR_CTEIF_Pos)
21284#define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk
21285#define DSI_WIFCR_CERIF_Pos (1U)
21286#define DSI_WIFCR_CERIF_Msk (0x1UL << DSI_WIFCR_CERIF_Pos)
21287#define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk
21288#define DSI_WIFCR_CPLLLIF_Pos (9U)
21289#define DSI_WIFCR_CPLLLIF_Msk (0x1UL << DSI_WIFCR_CPLLLIF_Pos)
21290#define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk
21291#define DSI_WIFCR_CPLLUIF_Pos (10U)
21292#define DSI_WIFCR_CPLLUIF_Msk (0x1UL << DSI_WIFCR_CPLLUIF_Pos)
21293#define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk
21294#define DSI_WIFCR_CRRIF_Pos (13U)
21295#define DSI_WIFCR_CRRIF_Msk (0x1UL << DSI_WIFCR_CRRIF_Pos)
21296#define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk
21298/******************* Bit definition for DSI_WPCR0 register ***************/
21299#define DSI_WPCR0_UIX4_Pos (0U)
21300#define DSI_WPCR0_UIX4_Msk (0x3FUL << DSI_WPCR0_UIX4_Pos)
21301#define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk
21302#define DSI_WPCR0_UIX4_0 (0x01UL << DSI_WPCR0_UIX4_Pos)
21303#define DSI_WPCR0_UIX4_1 (0x02UL << DSI_WPCR0_UIX4_Pos)
21304#define DSI_WPCR0_UIX4_2 (0x04UL << DSI_WPCR0_UIX4_Pos)
21305#define DSI_WPCR0_UIX4_3 (0x08UL << DSI_WPCR0_UIX4_Pos)
21306#define DSI_WPCR0_UIX4_4 (0x10UL << DSI_WPCR0_UIX4_Pos)
21307#define DSI_WPCR0_UIX4_5 (0x20UL << DSI_WPCR0_UIX4_Pos)
21309#define DSI_WPCR0_SWCL_Pos (6U)
21310#define DSI_WPCR0_SWCL_Msk (0x1UL << DSI_WPCR0_SWCL_Pos)
21311#define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk
21312#define DSI_WPCR0_SWDL0_Pos (7U)
21313#define DSI_WPCR0_SWDL0_Msk (0x1UL << DSI_WPCR0_SWDL0_Pos)
21314#define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk
21315#define DSI_WPCR0_SWDL1_Pos (8U)
21316#define DSI_WPCR0_SWDL1_Msk (0x1UL << DSI_WPCR0_SWDL1_Pos)
21317#define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk
21318#define DSI_WPCR0_HSICL_Pos (9U)
21319#define DSI_WPCR0_HSICL_Msk (0x1UL << DSI_WPCR0_HSICL_Pos)
21320#define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk
21321#define DSI_WPCR0_HSIDL0_Pos (10U)
21322#define DSI_WPCR0_HSIDL0_Msk (0x1UL << DSI_WPCR0_HSIDL0_Pos)
21323#define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk
21324#define DSI_WPCR0_HSIDL1_Pos (11U)
21325#define DSI_WPCR0_HSIDL1_Msk (0x1UL << DSI_WPCR0_HSIDL1_Pos)
21326#define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk
21327#define DSI_WPCR0_FTXSMCL_Pos (12U)
21328#define DSI_WPCR0_FTXSMCL_Msk (0x1UL << DSI_WPCR0_FTXSMCL_Pos)
21329#define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk
21330#define DSI_WPCR0_FTXSMDL_Pos (13U)
21331#define DSI_WPCR0_FTXSMDL_Msk (0x1UL << DSI_WPCR0_FTXSMDL_Pos)
21332#define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk
21333#define DSI_WPCR0_CDOFFDL_Pos (14U)
21334#define DSI_WPCR0_CDOFFDL_Msk (0x1UL << DSI_WPCR0_CDOFFDL_Pos)
21335#define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk
21336#define DSI_WPCR0_TDDL_Pos (16U)
21337#define DSI_WPCR0_TDDL_Msk (0x1UL << DSI_WPCR0_TDDL_Pos)
21338#define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk
21339#define DSI_WPCR0_PDEN_Pos (18U)
21340#define DSI_WPCR0_PDEN_Msk (0x1UL << DSI_WPCR0_PDEN_Pos)
21341#define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk
21342#define DSI_WPCR0_TCLKPREPEN_Pos (19U)
21343#define DSI_WPCR0_TCLKPREPEN_Msk (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos)
21344#define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk
21345#define DSI_WPCR0_TCLKZEROEN_Pos (20U)
21346#define DSI_WPCR0_TCLKZEROEN_Msk (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos)
21347#define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk
21348#define DSI_WPCR0_THSPREPEN_Pos (21U)
21349#define DSI_WPCR0_THSPREPEN_Msk (0x1UL << DSI_WPCR0_THSPREPEN_Pos)
21350#define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk
21351#define DSI_WPCR0_THSTRAILEN_Pos (22U)
21352#define DSI_WPCR0_THSTRAILEN_Msk (0x1UL << DSI_WPCR0_THSTRAILEN_Pos)
21353#define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk
21354#define DSI_WPCR0_THSZEROEN_Pos (23U)
21355#define DSI_WPCR0_THSZEROEN_Msk (0x1UL << DSI_WPCR0_THSZEROEN_Pos)
21356#define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk
21357#define DSI_WPCR0_TLPXDEN_Pos (24U)
21358#define DSI_WPCR0_TLPXDEN_Msk (0x1UL << DSI_WPCR0_TLPXDEN_Pos)
21359#define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk
21360#define DSI_WPCR0_THSEXITEN_Pos (25U)
21361#define DSI_WPCR0_THSEXITEN_Msk (0x1UL << DSI_WPCR0_THSEXITEN_Pos)
21362#define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk
21363#define DSI_WPCR0_TLPXCEN_Pos (26U)
21364#define DSI_WPCR0_TLPXCEN_Msk (0x1UL << DSI_WPCR0_TLPXCEN_Pos)
21365#define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk
21366#define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
21367#define DSI_WPCR0_TCLKPOSTEN_Msk (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos)
21368#define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk
21370/******************* Bit definition for DSI_WPCR1 register ***************/
21371#define DSI_WPCR1_HSTXDCL_Pos (0U)
21372#define DSI_WPCR1_HSTXDCL_Msk (0x3UL << DSI_WPCR1_HSTXDCL_Pos)
21373#define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk
21374#define DSI_WPCR1_HSTXDCL0_Pos (0U)
21375#define DSI_WPCR1_HSTXDCL0_Msk (0x1UL << DSI_WPCR1_HSTXDCL0_Pos)
21376#define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
21377#define DSI_WPCR1_HSTXDCL1_Pos (1U)
21378#define DSI_WPCR1_HSTXDCL1_Msk (0x1UL << DSI_WPCR1_HSTXDCL1_Pos)
21379#define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
21380
21381#define DSI_WPCR1_HSTXDDL_Pos (2U)
21382#define DSI_WPCR1_HSTXDDL_Msk (0x3UL << DSI_WPCR1_HSTXDDL_Pos)
21383#define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk
21384#define DSI_WPCR1_HSTXDDL0_Pos (2U)
21385#define DSI_WPCR1_HSTXDDL0_Msk (0x1UL << DSI_WPCR1_HSTXDDL0_Pos)
21386#define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
21387#define DSI_WPCR1_HSTXDDL1_Pos (3U)
21388#define DSI_WPCR1_HSTXDDL1_Msk (0x1UL << DSI_WPCR1_HSTXDDL1_Pos)
21389#define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
21390
21391#define DSI_WPCR1_LPSRCCL_Pos (6U)
21392#define DSI_WPCR1_LPSRCCL_Msk (0x3UL << DSI_WPCR1_LPSRCCL_Pos)
21393#define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk
21394#define DSI_WPCR1_LPSRCCL0_Pos (6U)
21395#define DSI_WPCR1_LPSRCCL0_Msk (0x1UL << DSI_WPCR1_LPSRCCL0_Pos)
21396#define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
21397#define DSI_WPCR1_LPSRCCL1_Pos (7U)
21398#define DSI_WPCR1_LPSRCCL1_Msk (0x1UL << DSI_WPCR1_LPSRCCL1_Pos)
21399#define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
21400
21401#define DSI_WPCR1_LPSRCDL_Pos (8U)
21402#define DSI_WPCR1_LPSRCDL_Msk (0x3UL << DSI_WPCR1_LPSRCDL_Pos)
21403#define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk
21404#define DSI_WPCR1_LPSRCDL0_Pos (8U)
21405#define DSI_WPCR1_LPSRCDL0_Msk (0x1UL << DSI_WPCR1_LPSRCDL0_Pos)
21406#define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
21407#define DSI_WPCR1_LPSRCDL1_Pos (9U)
21408#define DSI_WPCR1_LPSRCDL1_Msk (0x1UL << DSI_WPCR1_LPSRCDL1_Pos)
21409#define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
21410
21411#define DSI_WPCR1_SDDC_Pos (12U)
21412#define DSI_WPCR1_SDDC_Msk (0x1UL << DSI_WPCR1_SDDC_Pos)
21413#define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk
21415#define DSI_WPCR1_LPRXVCDL_Pos (14U)
21416#define DSI_WPCR1_LPRXVCDL_Msk (0x3UL << DSI_WPCR1_LPRXVCDL_Pos)
21417#define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk
21418#define DSI_WPCR1_LPRXVCDL0_Pos (14U)
21419#define DSI_WPCR1_LPRXVCDL0_Msk (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos)
21420#define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
21421#define DSI_WPCR1_LPRXVCDL1_Pos (15U)
21422#define DSI_WPCR1_LPRXVCDL1_Msk (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos)
21423#define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
21424
21425#define DSI_WPCR1_HSTXSRCCL_Pos (16U)
21426#define DSI_WPCR1_HSTXSRCCL_Msk (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos)
21427#define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk
21428#define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
21429#define DSI_WPCR1_HSTXSRCCL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos)
21430#define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
21431#define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
21432#define DSI_WPCR1_HSTXSRCCL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos)
21433#define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
21434
21435#define DSI_WPCR1_HSTXSRCDL_Pos (18U)
21436#define DSI_WPCR1_HSTXSRCDL_Msk (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos)
21437#define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk
21438#define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
21439#define DSI_WPCR1_HSTXSRCDL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos)
21440#define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
21441#define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
21442#define DSI_WPCR1_HSTXSRCDL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos)
21443#define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
21444
21445#define DSI_WPCR1_FLPRXLPM_Pos (22U)
21446#define DSI_WPCR1_FLPRXLPM_Msk (0x1UL << DSI_WPCR1_FLPRXLPM_Pos)
21447#define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk
21449#define DSI_WPCR1_LPRXFT_Pos (25U)
21450#define DSI_WPCR1_LPRXFT_Msk (0x3UL << DSI_WPCR1_LPRXFT_Pos)
21451#define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk
21452#define DSI_WPCR1_LPRXFT0_Pos (25U)
21453#define DSI_WPCR1_LPRXFT0_Msk (0x1UL << DSI_WPCR1_LPRXFT0_Pos)
21454#define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
21455#define DSI_WPCR1_LPRXFT1_Pos (26U)
21456#define DSI_WPCR1_LPRXFT1_Msk (0x1UL << DSI_WPCR1_LPRXFT1_Pos)
21457#define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
21458
21459/******************* Bit definition for DSI_WPCR2 register ***************/
21460#define DSI_WPCR2_TCLKPREP_Pos (0U)
21461#define DSI_WPCR2_TCLKPREP_Msk (0xFFUL << DSI_WPCR2_TCLKPREP_Pos)
21462#define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk
21463#define DSI_WPCR2_TCLKPREP0_Pos (0U)
21464#define DSI_WPCR2_TCLKPREP0_Msk (0x1UL << DSI_WPCR2_TCLKPREP0_Pos)
21465#define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
21466#define DSI_WPCR2_TCLKPREP1_Pos (1U)
21467#define DSI_WPCR2_TCLKPREP1_Msk (0x1UL << DSI_WPCR2_TCLKPREP1_Pos)
21468#define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
21469#define DSI_WPCR2_TCLKPREP2_Pos (2U)
21470#define DSI_WPCR2_TCLKPREP2_Msk (0x1UL << DSI_WPCR2_TCLKPREP2_Pos)
21471#define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
21472#define DSI_WPCR2_TCLKPREP3_Pos (3U)
21473#define DSI_WPCR2_TCLKPREP3_Msk (0x1UL << DSI_WPCR2_TCLKPREP3_Pos)
21474#define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
21475#define DSI_WPCR2_TCLKPREP4_Pos (4U)
21476#define DSI_WPCR2_TCLKPREP4_Msk (0x1UL << DSI_WPCR2_TCLKPREP4_Pos)
21477#define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
21478#define DSI_WPCR2_TCLKPREP5_Pos (5U)
21479#define DSI_WPCR2_TCLKPREP5_Msk (0x1UL << DSI_WPCR2_TCLKPREP5_Pos)
21480#define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
21481#define DSI_WPCR2_TCLKPREP6_Pos (6U)
21482#define DSI_WPCR2_TCLKPREP6_Msk (0x1UL << DSI_WPCR2_TCLKPREP6_Pos)
21483#define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
21484#define DSI_WPCR2_TCLKPREP7_Pos (7U)
21485#define DSI_WPCR2_TCLKPREP7_Msk (0x1UL << DSI_WPCR2_TCLKPREP7_Pos)
21486#define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
21487
21488#define DSI_WPCR2_TCLKZERO_Pos (8U)
21489#define DSI_WPCR2_TCLKZERO_Msk (0xFFUL << DSI_WPCR2_TCLKZERO_Pos)
21490#define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk
21491#define DSI_WPCR2_TCLKZERO0_Pos (8U)
21492#define DSI_WPCR2_TCLKZERO0_Msk (0x1UL << DSI_WPCR2_TCLKZERO0_Pos)
21493#define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
21494#define DSI_WPCR2_TCLKZERO1_Pos (9U)
21495#define DSI_WPCR2_TCLKZERO1_Msk (0x1UL << DSI_WPCR2_TCLKZERO1_Pos)
21496#define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
21497#define DSI_WPCR2_TCLKZERO2_Pos (10U)
21498#define DSI_WPCR2_TCLKZERO2_Msk (0x1UL << DSI_WPCR2_TCLKZERO2_Pos)
21499#define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
21500#define DSI_WPCR2_TCLKZERO3_Pos (11U)
21501#define DSI_WPCR2_TCLKZERO3_Msk (0x1UL << DSI_WPCR2_TCLKZERO3_Pos)
21502#define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
21503#define DSI_WPCR2_TCLKZERO4_Pos (12U)
21504#define DSI_WPCR2_TCLKZERO4_Msk (0x1UL << DSI_WPCR2_TCLKZERO4_Pos)
21505#define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
21506#define DSI_WPCR2_TCLKZERO5_Pos (13U)
21507#define DSI_WPCR2_TCLKZERO5_Msk (0x1UL << DSI_WPCR2_TCLKZERO5_Pos)
21508#define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
21509#define DSI_WPCR2_TCLKZERO6_Pos (14U)
21510#define DSI_WPCR2_TCLKZERO6_Msk (0x1UL << DSI_WPCR2_TCLKZERO6_Pos)
21511#define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
21512#define DSI_WPCR2_TCLKZERO7_Pos (15U)
21513#define DSI_WPCR2_TCLKZERO7_Msk (0x1UL << DSI_WPCR2_TCLKZERO7_Pos)
21514#define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
21515
21516#define DSI_WPCR2_THSPREP_Pos (16U)
21517#define DSI_WPCR2_THSPREP_Msk (0xFFUL << DSI_WPCR2_THSPREP_Pos)
21518#define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk
21519#define DSI_WPCR2_THSPREP0_Pos (16U)
21520#define DSI_WPCR2_THSPREP0_Msk (0x1UL << DSI_WPCR2_THSPREP0_Pos)
21521#define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
21522#define DSI_WPCR2_THSPREP1_Pos (17U)
21523#define DSI_WPCR2_THSPREP1_Msk (0x1UL << DSI_WPCR2_THSPREP1_Pos)
21524#define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
21525#define DSI_WPCR2_THSPREP2_Pos (18U)
21526#define DSI_WPCR2_THSPREP2_Msk (0x1UL << DSI_WPCR2_THSPREP2_Pos)
21527#define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
21528#define DSI_WPCR2_THSPREP3_Pos (19U)
21529#define DSI_WPCR2_THSPREP3_Msk (0x1UL << DSI_WPCR2_THSPREP3_Pos)
21530#define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
21531#define DSI_WPCR2_THSPREP4_Pos (20U)
21532#define DSI_WPCR2_THSPREP4_Msk (0x1UL << DSI_WPCR2_THSPREP4_Pos)
21533#define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
21534#define DSI_WPCR2_THSPREP5_Pos (21U)
21535#define DSI_WPCR2_THSPREP5_Msk (0x1UL << DSI_WPCR2_THSPREP5_Pos)
21536#define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
21537#define DSI_WPCR2_THSPREP6_Pos (22U)
21538#define DSI_WPCR2_THSPREP6_Msk (0x1UL << DSI_WPCR2_THSPREP6_Pos)
21539#define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
21540#define DSI_WPCR2_THSPREP7_Pos (23U)
21541#define DSI_WPCR2_THSPREP7_Msk (0x1UL << DSI_WPCR2_THSPREP7_Pos)
21542#define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
21543
21544#define DSI_WPCR2_THSTRAIL_Pos (24U)
21545#define DSI_WPCR2_THSTRAIL_Msk (0xFFUL << DSI_WPCR2_THSTRAIL_Pos)
21546#define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk
21547#define DSI_WPCR2_THSTRAIL0_Pos (24U)
21548#define DSI_WPCR2_THSTRAIL0_Msk (0x1UL << DSI_WPCR2_THSTRAIL0_Pos)
21549#define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
21550#define DSI_WPCR2_THSTRAIL1_Pos (25U)
21551#define DSI_WPCR2_THSTRAIL1_Msk (0x1UL << DSI_WPCR2_THSTRAIL1_Pos)
21552#define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
21553#define DSI_WPCR2_THSTRAIL2_Pos (26U)
21554#define DSI_WPCR2_THSTRAIL2_Msk (0x1UL << DSI_WPCR2_THSTRAIL2_Pos)
21555#define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
21556#define DSI_WPCR2_THSTRAIL3_Pos (27U)
21557#define DSI_WPCR2_THSTRAIL3_Msk (0x1UL << DSI_WPCR2_THSTRAIL3_Pos)
21558#define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
21559#define DSI_WPCR2_THSTRAIL4_Pos (28U)
21560#define DSI_WPCR2_THSTRAIL4_Msk (0x1UL << DSI_WPCR2_THSTRAIL4_Pos)
21561#define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
21562#define DSI_WPCR2_THSTRAIL5_Pos (29U)
21563#define DSI_WPCR2_THSTRAIL5_Msk (0x1UL << DSI_WPCR2_THSTRAIL5_Pos)
21564#define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
21565#define DSI_WPCR2_THSTRAIL6_Pos (30U)
21566#define DSI_WPCR2_THSTRAIL6_Msk (0x1UL << DSI_WPCR2_THSTRAIL6_Pos)
21567#define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
21568#define DSI_WPCR2_THSTRAIL7_Pos (31U)
21569#define DSI_WPCR2_THSTRAIL7_Msk (0x1UL << DSI_WPCR2_THSTRAIL7_Pos)
21570#define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
21571
21572/******************* Bit definition for DSI_WPCR3 register ***************/
21573#define DSI_WPCR3_THSZERO_Pos (0U)
21574#define DSI_WPCR3_THSZERO_Msk (0xFFUL << DSI_WPCR3_THSZERO_Pos)
21575#define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk
21576#define DSI_WPCR3_THSZERO0_Pos (0U)
21577#define DSI_WPCR3_THSZERO0_Msk (0x1UL << DSI_WPCR3_THSZERO0_Pos)
21578#define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
21579#define DSI_WPCR3_THSZERO1_Pos (1U)
21580#define DSI_WPCR3_THSZERO1_Msk (0x1UL << DSI_WPCR3_THSZERO1_Pos)
21581#define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
21582#define DSI_WPCR3_THSZERO2_Pos (2U)
21583#define DSI_WPCR3_THSZERO2_Msk (0x1UL << DSI_WPCR3_THSZERO2_Pos)
21584#define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
21585#define DSI_WPCR3_THSZERO3_Pos (3U)
21586#define DSI_WPCR3_THSZERO3_Msk (0x1UL << DSI_WPCR3_THSZERO3_Pos)
21587#define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
21588#define DSI_WPCR3_THSZERO4_Pos (4U)
21589#define DSI_WPCR3_THSZERO4_Msk (0x1UL << DSI_WPCR3_THSZERO4_Pos)
21590#define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
21591#define DSI_WPCR3_THSZERO5_Pos (5U)
21592#define DSI_WPCR3_THSZERO5_Msk (0x1UL << DSI_WPCR3_THSZERO5_Pos)
21593#define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
21594#define DSI_WPCR3_THSZERO6_Pos (6U)
21595#define DSI_WPCR3_THSZERO6_Msk (0x1UL << DSI_WPCR3_THSZERO6_Pos)
21596#define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
21597#define DSI_WPCR3_THSZERO7_Pos (7U)
21598#define DSI_WPCR3_THSZERO7_Msk (0x1UL << DSI_WPCR3_THSZERO7_Pos)
21599#define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
21600
21601#define DSI_WPCR3_TLPXD_Pos (8U)
21602#define DSI_WPCR3_TLPXD_Msk (0xFFUL << DSI_WPCR3_TLPXD_Pos)
21603#define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk
21604#define DSI_WPCR3_TLPXD0_Pos (8U)
21605#define DSI_WPCR3_TLPXD0_Msk (0x1UL << DSI_WPCR3_TLPXD0_Pos)
21606#define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
21607#define DSI_WPCR3_TLPXD1_Pos (9U)
21608#define DSI_WPCR3_TLPXD1_Msk (0x1UL << DSI_WPCR3_TLPXD1_Pos)
21609#define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
21610#define DSI_WPCR3_TLPXD2_Pos (10U)
21611#define DSI_WPCR3_TLPXD2_Msk (0x1UL << DSI_WPCR3_TLPXD2_Pos)
21612#define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
21613#define DSI_WPCR3_TLPXD3_Pos (11U)
21614#define DSI_WPCR3_TLPXD3_Msk (0x1UL << DSI_WPCR3_TLPXD3_Pos)
21615#define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
21616#define DSI_WPCR3_TLPXD4_Pos (12U)
21617#define DSI_WPCR3_TLPXD4_Msk (0x1UL << DSI_WPCR3_TLPXD4_Pos)
21618#define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
21619#define DSI_WPCR3_TLPXD5_Pos (13U)
21620#define DSI_WPCR3_TLPXD5_Msk (0x1UL << DSI_WPCR3_TLPXD5_Pos)
21621#define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
21622#define DSI_WPCR3_TLPXD6_Pos (14U)
21623#define DSI_WPCR3_TLPXD6_Msk (0x1UL << DSI_WPCR3_TLPXD6_Pos)
21624#define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
21625#define DSI_WPCR3_TLPXD7_Pos (15U)
21626#define DSI_WPCR3_TLPXD7_Msk (0x1UL << DSI_WPCR3_TLPXD7_Pos)
21627#define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
21628
21629#define DSI_WPCR3_THSEXIT_Pos (16U)
21630#define DSI_WPCR3_THSEXIT_Msk (0xFFUL << DSI_WPCR3_THSEXIT_Pos)
21631#define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk
21632#define DSI_WPCR3_THSEXIT0_Pos (16U)
21633#define DSI_WPCR3_THSEXIT0_Msk (0x1UL << DSI_WPCR3_THSEXIT0_Pos)
21634#define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
21635#define DSI_WPCR3_THSEXIT1_Pos (17U)
21636#define DSI_WPCR3_THSEXIT1_Msk (0x1UL << DSI_WPCR3_THSEXIT1_Pos)
21637#define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
21638#define DSI_WPCR3_THSEXIT2_Pos (18U)
21639#define DSI_WPCR3_THSEXIT2_Msk (0x1UL << DSI_WPCR3_THSEXIT2_Pos)
21640#define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
21641#define DSI_WPCR3_THSEXIT3_Pos (19U)
21642#define DSI_WPCR3_THSEXIT3_Msk (0x1UL << DSI_WPCR3_THSEXIT3_Pos)
21643#define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
21644#define DSI_WPCR3_THSEXIT4_Pos (20U)
21645#define DSI_WPCR3_THSEXIT4_Msk (0x1UL << DSI_WPCR3_THSEXIT4_Pos)
21646#define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
21647#define DSI_WPCR3_THSEXIT5_Pos (21U)
21648#define DSI_WPCR3_THSEXIT5_Msk (0x1UL << DSI_WPCR3_THSEXIT5_Pos)
21649#define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
21650#define DSI_WPCR3_THSEXIT6_Pos (22U)
21651#define DSI_WPCR3_THSEXIT6_Msk (0x1UL << DSI_WPCR3_THSEXIT6_Pos)
21652#define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
21653#define DSI_WPCR3_THSEXIT7_Pos (23U)
21654#define DSI_WPCR3_THSEXIT7_Msk (0x1UL << DSI_WPCR3_THSEXIT7_Pos)
21655#define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
21656
21657#define DSI_WPCR3_TLPXC_Pos (24U)
21658#define DSI_WPCR3_TLPXC_Msk (0xFFUL << DSI_WPCR3_TLPXC_Pos)
21659#define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk
21660#define DSI_WPCR3_TLPXC0_Pos (24U)
21661#define DSI_WPCR3_TLPXC0_Msk (0x1UL << DSI_WPCR3_TLPXC0_Pos)
21662#define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
21663#define DSI_WPCR3_TLPXC1_Pos (25U)
21664#define DSI_WPCR3_TLPXC1_Msk (0x1UL << DSI_WPCR3_TLPXC1_Pos)
21665#define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
21666#define DSI_WPCR3_TLPXC2_Pos (26U)
21667#define DSI_WPCR3_TLPXC2_Msk (0x1UL << DSI_WPCR3_TLPXC2_Pos)
21668#define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
21669#define DSI_WPCR3_TLPXC3_Pos (27U)
21670#define DSI_WPCR3_TLPXC3_Msk (0x1UL << DSI_WPCR3_TLPXC3_Pos)
21671#define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
21672#define DSI_WPCR3_TLPXC4_Pos (28U)
21673#define DSI_WPCR3_TLPXC4_Msk (0x1UL << DSI_WPCR3_TLPXC4_Pos)
21674#define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
21675#define DSI_WPCR3_TLPXC5_Pos (29U)
21676#define DSI_WPCR3_TLPXC5_Msk (0x1UL << DSI_WPCR3_TLPXC5_Pos)
21677#define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
21678#define DSI_WPCR3_TLPXC6_Pos (30U)
21679#define DSI_WPCR3_TLPXC6_Msk (0x1UL << DSI_WPCR3_TLPXC6_Pos)
21680#define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
21681#define DSI_WPCR3_TLPXC7_Pos (31U)
21682#define DSI_WPCR3_TLPXC7_Msk (0x1UL << DSI_WPCR3_TLPXC7_Pos)
21683#define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
21684
21685/******************* Bit definition for DSI_WPCR4 register ***************/
21686#define DSI_WPCR4_TCLKPOST_Pos (0U)
21687#define DSI_WPCR4_TCLKPOST_Msk (0xFFUL << DSI_WPCR4_TCLKPOST_Pos)
21688#define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk
21689#define DSI_WPCR4_TCLKPOST0_Pos (0U)
21690#define DSI_WPCR4_TCLKPOST0_Msk (0x1UL << DSI_WPCR4_TCLKPOST0_Pos)
21691#define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
21692#define DSI_WPCR4_TCLKPOST1_Pos (1U)
21693#define DSI_WPCR4_TCLKPOST1_Msk (0x1UL << DSI_WPCR4_TCLKPOST1_Pos)
21694#define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
21695#define DSI_WPCR4_TCLKPOST2_Pos (2U)
21696#define DSI_WPCR4_TCLKPOST2_Msk (0x1UL << DSI_WPCR4_TCLKPOST2_Pos)
21697#define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
21698#define DSI_WPCR4_TCLKPOST3_Pos (3U)
21699#define DSI_WPCR4_TCLKPOST3_Msk (0x1UL << DSI_WPCR4_TCLKPOST3_Pos)
21700#define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
21701#define DSI_WPCR4_TCLKPOST4_Pos (4U)
21702#define DSI_WPCR4_TCLKPOST4_Msk (0x1UL << DSI_WPCR4_TCLKPOST4_Pos)
21703#define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
21704#define DSI_WPCR4_TCLKPOST5_Pos (5U)
21705#define DSI_WPCR4_TCLKPOST5_Msk (0x1UL << DSI_WPCR4_TCLKPOST5_Pos)
21706#define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
21707#define DSI_WPCR4_TCLKPOST6_Pos (6U)
21708#define DSI_WPCR4_TCLKPOST6_Msk (0x1UL << DSI_WPCR4_TCLKPOST6_Pos)
21709#define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
21710#define DSI_WPCR4_TCLKPOST7_Pos (7U)
21711#define DSI_WPCR4_TCLKPOST7_Msk (0x1UL << DSI_WPCR4_TCLKPOST7_Pos)
21712#define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
21713
21714/******************* Bit definition for DSI_WRPCR register ***************/
21715#define DSI_WRPCR_PLLEN_Pos (0U)
21716#define DSI_WRPCR_PLLEN_Msk (0x1UL << DSI_WRPCR_PLLEN_Pos)
21717#define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk
21718#define DSI_WRPCR_PLL_NDIV_Pos (2U)
21719#define DSI_WRPCR_PLL_NDIV_Msk (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos)
21720#define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk
21721#define DSI_WRPCR_PLL_NDIV0_Pos (2U)
21722#define DSI_WRPCR_PLL_NDIV0_Msk (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos)
21723#define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
21724#define DSI_WRPCR_PLL_NDIV1_Pos (3U)
21725#define DSI_WRPCR_PLL_NDIV1_Msk (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos)
21726#define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
21727#define DSI_WRPCR_PLL_NDIV2_Pos (4U)
21728#define DSI_WRPCR_PLL_NDIV2_Msk (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos)
21729#define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
21730#define DSI_WRPCR_PLL_NDIV3_Pos (5U)
21731#define DSI_WRPCR_PLL_NDIV3_Msk (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos)
21732#define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
21733#define DSI_WRPCR_PLL_NDIV4_Pos (6U)
21734#define DSI_WRPCR_PLL_NDIV4_Msk (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos)
21735#define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
21736#define DSI_WRPCR_PLL_NDIV5_Pos (7U)
21737#define DSI_WRPCR_PLL_NDIV5_Msk (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos)
21738#define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
21739#define DSI_WRPCR_PLL_NDIV6_Pos (8U)
21740#define DSI_WRPCR_PLL_NDIV6_Msk (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos)
21741#define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
21742
21743#define DSI_WRPCR_PLL_IDF_Pos (11U)
21744#define DSI_WRPCR_PLL_IDF_Msk (0xFUL << DSI_WRPCR_PLL_IDF_Pos)
21745#define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk
21746#define DSI_WRPCR_PLL_IDF0_Pos (11U)
21747#define DSI_WRPCR_PLL_IDF0_Msk (0x1UL << DSI_WRPCR_PLL_IDF0_Pos)
21748#define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
21749#define DSI_WRPCR_PLL_IDF1_Pos (12U)
21750#define DSI_WRPCR_PLL_IDF1_Msk (0x1UL << DSI_WRPCR_PLL_IDF1_Pos)
21751#define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
21752#define DSI_WRPCR_PLL_IDF2_Pos (13U)
21753#define DSI_WRPCR_PLL_IDF2_Msk (0x1UL << DSI_WRPCR_PLL_IDF2_Pos)
21754#define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
21755#define DSI_WRPCR_PLL_IDF3_Pos (14U)
21756#define DSI_WRPCR_PLL_IDF3_Msk (0x1UL << DSI_WRPCR_PLL_IDF3_Pos)
21757#define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
21758
21759#define DSI_WRPCR_PLL_ODF_Pos (16U)
21760#define DSI_WRPCR_PLL_ODF_Msk (0x3UL << DSI_WRPCR_PLL_ODF_Pos)
21761#define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk
21762#define DSI_WRPCR_PLL_ODF0_Pos (16U)
21763#define DSI_WRPCR_PLL_ODF0_Msk (0x1UL << DSI_WRPCR_PLL_ODF0_Pos)
21764#define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
21765#define DSI_WRPCR_PLL_ODF1_Pos (17U)
21766#define DSI_WRPCR_PLL_ODF1_Msk (0x1UL << DSI_WRPCR_PLL_ODF1_Pos)
21767#define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
21768
21769#define DSI_WRPCR_REGEN_Pos (24U)
21770#define DSI_WRPCR_REGEN_Msk (0x1UL << DSI_WRPCR_REGEN_Pos)
21771#define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk
21785/******************************* ADC Instances ********************************/
21786#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
21787 ((__INSTANCE__) == ADC2) || \
21788 ((__INSTANCE__) == ADC3))
21789#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
21790
21791#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
21792
21793/******************************* CAN Instances ********************************/
21794#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
21795 ((__INSTANCE__) == CAN2) || \
21796 ((__INSTANCE__) == CAN3))
21797/******************************* CRC Instances ********************************/
21798#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
21799
21800/******************************* DAC Instances ********************************/
21801#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)
21802
21803/******************************* DCMI Instances *******************************/
21804#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
21805
21806/****************************** DFSDM Instances *******************************/
21807#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
21808 ((INSTANCE) == DFSDM1_Filter1) || \
21809 ((INSTANCE) == DFSDM1_Filter2) || \
21810 ((INSTANCE) == DFSDM1_Filter3))
21811
21812#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
21813 ((INSTANCE) == DFSDM1_Channel1) || \
21814 ((INSTANCE) == DFSDM1_Channel2) || \
21815 ((INSTANCE) == DFSDM1_Channel3) || \
21816 ((INSTANCE) == DFSDM1_Channel4) || \
21817 ((INSTANCE) == DFSDM1_Channel5) || \
21818 ((INSTANCE) == DFSDM1_Channel6) || \
21819 ((INSTANCE) == DFSDM1_Channel7))
21820
21821/******************************* DMA2D Instances *******************************/
21822#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
21823
21824/******************************** DMA Instances *******************************/
21825#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
21826 ((__INSTANCE__) == DMA1_Stream1) || \
21827 ((__INSTANCE__) == DMA1_Stream2) || \
21828 ((__INSTANCE__) == DMA1_Stream3) || \
21829 ((__INSTANCE__) == DMA1_Stream4) || \
21830 ((__INSTANCE__) == DMA1_Stream5) || \
21831 ((__INSTANCE__) == DMA1_Stream6) || \
21832 ((__INSTANCE__) == DMA1_Stream7) || \
21833 ((__INSTANCE__) == DMA2_Stream0) || \
21834 ((__INSTANCE__) == DMA2_Stream1) || \
21835 ((__INSTANCE__) == DMA2_Stream2) || \
21836 ((__INSTANCE__) == DMA2_Stream3) || \
21837 ((__INSTANCE__) == DMA2_Stream4) || \
21838 ((__INSTANCE__) == DMA2_Stream5) || \
21839 ((__INSTANCE__) == DMA2_Stream6) || \
21840 ((__INSTANCE__) == DMA2_Stream7))
21841
21842/******************************* GPIO Instances *******************************/
21843#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
21844 ((__INSTANCE__) == GPIOB) || \
21845 ((__INSTANCE__) == GPIOC) || \
21846 ((__INSTANCE__) == GPIOD) || \
21847 ((__INSTANCE__) == GPIOE) || \
21848 ((__INSTANCE__) == GPIOF) || \
21849 ((__INSTANCE__) == GPIOG) || \
21850 ((__INSTANCE__) == GPIOH) || \
21851 ((__INSTANCE__) == GPIOI) || \
21852 ((__INSTANCE__) == GPIOJ) || \
21853 ((__INSTANCE__) == GPIOK))
21854
21855#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
21856 ((__INSTANCE__) == GPIOB) || \
21857 ((__INSTANCE__) == GPIOC) || \
21858 ((__INSTANCE__) == GPIOD) || \
21859 ((__INSTANCE__) == GPIOE) || \
21860 ((__INSTANCE__) == GPIOF) || \
21861 ((__INSTANCE__) == GPIOG) || \
21862 ((__INSTANCE__) == GPIOH) || \
21863 ((__INSTANCE__) == GPIOI) || \
21864 ((__INSTANCE__) == GPIOJ) || \
21865 ((__INSTANCE__) == GPIOK))
21866
21867/****************************** CEC Instances *********************************/
21868#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
21869
21870/****************************** QSPI Instances *********************************/
21871#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
21872
21873
21874/******************************** I2C Instances *******************************/
21875#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
21876 ((__INSTANCE__) == I2C2) || \
21877 ((__INSTANCE__) == I2C3) || \
21878 ((__INSTANCE__) == I2C4))
21879
21880/****************************** SMBUS Instances *******************************/
21881#define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
21882 ((__INSTANCE__) == I2C2) || \
21883 ((__INSTANCE__) == I2C3) || \
21884 ((__INSTANCE__) == I2C4))
21885
21886
21887/******************************** I2S Instances *******************************/
21888#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
21889 ((__INSTANCE__) == SPI2) || \
21890 ((__INSTANCE__) == SPI3))
21891
21892/******************************* LPTIM Instances ********************************/
21893#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
21894
21895/****************************** LTDC Instances ********************************/
21896#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
21897
21898/****************************** MDIOS Instances ********************************/
21899#define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
21900
21901/****************************** MDIOS Instances ********************************/
21902#define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
21903
21904
21905/******************************* RNG Instances ********************************/
21906#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
21907
21908/****************************** RTC Instances *********************************/
21909#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
21910
21911/******************************* SAI Instances ********************************/
21912#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
21913 ((__PERIPH__) == SAI1_Block_B) || \
21914 ((__PERIPH__) == SAI2_Block_A) || \
21915 ((__PERIPH__) == SAI2_Block_B))
21916/* Legacy define */
21917#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
21918
21919/******************************** SDMMC Instances *******************************/
21920#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
21921 ((__INSTANCE__) == SDMMC2))
21922
21923/****************************** SPDIFRX Instances *********************************/
21924#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
21925
21926/******************************** SPI Instances *******************************/
21927#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
21928 ((__INSTANCE__) == SPI2) || \
21929 ((__INSTANCE__) == SPI3) || \
21930 ((__INSTANCE__) == SPI4) || \
21931 ((__INSTANCE__) == SPI5) || \
21932 ((__INSTANCE__) == SPI6))
21933
21934/****************** TIM Instances : All supported instances *******************/
21935#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21936 ((__INSTANCE__) == TIM2) || \
21937 ((__INSTANCE__) == TIM3) || \
21938 ((__INSTANCE__) == TIM4) || \
21939 ((__INSTANCE__) == TIM5) || \
21940 ((__INSTANCE__) == TIM6) || \
21941 ((__INSTANCE__) == TIM7) || \
21942 ((__INSTANCE__) == TIM8) || \
21943 ((__INSTANCE__) == TIM9) || \
21944 ((__INSTANCE__) == TIM10) || \
21945 ((__INSTANCE__) == TIM11) || \
21946 ((__INSTANCE__) == TIM12) || \
21947 ((__INSTANCE__) == TIM13) || \
21948 ((__INSTANCE__) == TIM14))
21949
21950/****************** TIM Instances : supporting 32 bits counter ****************/
21951#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
21952 ((__INSTANCE__) == TIM5))
21953
21954/****************** TIM Instances : supporting the break function *************/
21955#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21956 ((INSTANCE) == TIM8))
21957
21958/************** TIM Instances : supporting Break source selection *************/
21959#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21960 ((INSTANCE) == TIM8))
21961
21962/****************** TIM Instances : supporting 2 break inputs *****************/
21963#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21964 ((INSTANCE) == TIM8))
21965
21966/************* TIM Instances : at least 1 capture/compare channel *************/
21967#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21968 ((__INSTANCE__) == TIM2) || \
21969 ((__INSTANCE__) == TIM3) || \
21970 ((__INSTANCE__) == TIM4) || \
21971 ((__INSTANCE__) == TIM5) || \
21972 ((__INSTANCE__) == TIM8) || \
21973 ((__INSTANCE__) == TIM9) || \
21974 ((__INSTANCE__) == TIM10) || \
21975 ((__INSTANCE__) == TIM11) || \
21976 ((__INSTANCE__) == TIM12) || \
21977 ((__INSTANCE__) == TIM13) || \
21978 ((__INSTANCE__) == TIM14))
21979
21980/************ TIM Instances : at least 2 capture/compare channels *************/
21981#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21982 ((__INSTANCE__) == TIM2) || \
21983 ((__INSTANCE__) == TIM3) || \
21984 ((__INSTANCE__) == TIM4) || \
21985 ((__INSTANCE__) == TIM5) || \
21986 ((__INSTANCE__) == TIM8) || \
21987 ((__INSTANCE__) == TIM9) || \
21988 ((__INSTANCE__) == TIM12))
21989
21990/************ TIM Instances : at least 3 capture/compare channels *************/
21991#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21992 ((__INSTANCE__) == TIM2) || \
21993 ((__INSTANCE__) == TIM3) || \
21994 ((__INSTANCE__) == TIM4) || \
21995 ((__INSTANCE__) == TIM5) || \
21996 ((__INSTANCE__) == TIM8))
21997
21998/************ TIM Instances : at least 4 capture/compare channels *************/
21999#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22000 ((__INSTANCE__) == TIM2) || \
22001 ((__INSTANCE__) == TIM3) || \
22002 ((__INSTANCE__) == TIM4) || \
22003 ((__INSTANCE__) == TIM5) || \
22004 ((__INSTANCE__) == TIM8))
22005
22006/****************** TIM Instances : at least 5 capture/compare channels *******/
22007#define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22008 ((__INSTANCE__) == TIM8))
22009
22010/****************** TIM Instances : at least 6 capture/compare channels *******/
22011#define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22012 ((__INSTANCE__) == TIM8))
22013
22014/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
22015#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22016 ((__INSTANCE__) == TIM8))
22017
22018/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
22019#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22020 ((__INSTANCE__) == TIM8) || \
22021 ((__INSTANCE__) == TIM2) || \
22022 ((__INSTANCE__) == TIM3) || \
22023 ((__INSTANCE__) == TIM4) || \
22024 ((__INSTANCE__) == TIM5) || \
22025 ((__INSTANCE__) == TIM6) || \
22026 ((__INSTANCE__) == TIM7))
22027
22028/************ TIM Instances : DMA requests generation (CCxDE) *****************/
22029#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22030 ((__INSTANCE__) == TIM2) || \
22031 ((__INSTANCE__) == TIM3) || \
22032 ((__INSTANCE__) == TIM4) || \
22033 ((__INSTANCE__) == TIM5) || \
22034 ((__INSTANCE__) == TIM8))
22035
22036/******************** TIM Instances : DMA burst feature ***********************/
22037#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22038 ((__INSTANCE__) == TIM2) || \
22039 ((__INSTANCE__) == TIM3) || \
22040 ((__INSTANCE__) == TIM4) || \
22041 ((__INSTANCE__) == TIM5) || \
22042 ((__INSTANCE__) == TIM8))
22043
22044/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
22045#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
22046 (((__INSTANCE__) == TIM1) || \
22047 ((__INSTANCE__) == TIM8))
22048
22049/****************** TIM Instances : supporting counting mode selection ********/
22050#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22051 ((__INSTANCE__) == TIM2) || \
22052 ((__INSTANCE__) == TIM3) || \
22053 ((__INSTANCE__) == TIM4) || \
22054 ((__INSTANCE__) == TIM5) || \
22055 ((__INSTANCE__) == TIM8))
22056
22057/****************** TIM Instances : supporting encoder interface **************/
22058#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22059 ((__INSTANCE__) == TIM2) || \
22060 ((__INSTANCE__) == TIM3) || \
22061 ((__INSTANCE__) == TIM4) || \
22062 ((__INSTANCE__) == TIM5) || \
22063 ((__INSTANCE__) == TIM8))
22064
22065/****************** TIM Instances : supporting OCxREF clear *******************/
22066#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
22067 (((__INSTANCE__) == TIM2) || \
22068 ((__INSTANCE__) == TIM3) || \
22069 ((__INSTANCE__) == TIM4) || \
22070 ((__INSTANCE__) == TIM5))
22071
22072/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
22073#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
22074 (((__INSTANCE__) == TIM1) || \
22075 ((__INSTANCE__) == TIM2) || \
22076 ((__INSTANCE__) == TIM3) || \
22077 ((__INSTANCE__) == TIM4) || \
22078 ((__INSTANCE__) == TIM5) || \
22079 ((__INSTANCE__) == TIM8))
22080
22081/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
22082#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
22083 (((__INSTANCE__) == TIM1) || \
22084 ((__INSTANCE__) == TIM2) || \
22085 ((__INSTANCE__) == TIM3) || \
22086 ((__INSTANCE__) == TIM4) || \
22087 ((__INSTANCE__) == TIM5) || \
22088 ((__INSTANCE__) == TIM8))
22089
22090/******************** TIM Instances : Advanced-control timers *****************/
22091#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22092 ((__INSTANCE__) == TIM8))
22093
22094/******************* TIM Instances : Timer input XOR function *****************/
22095#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22096 ((__INSTANCE__) == TIM2) || \
22097 ((__INSTANCE__) == TIM3) || \
22098 ((__INSTANCE__) == TIM4) || \
22099 ((__INSTANCE__) == TIM5) || \
22100 ((__INSTANCE__) == TIM8))
22101
22102/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
22103#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22104 ((__INSTANCE__) == TIM2) || \
22105 ((__INSTANCE__) == TIM3) || \
22106 ((__INSTANCE__) == TIM4) || \
22107 ((__INSTANCE__) == TIM5) || \
22108 ((__INSTANCE__) == TIM6) || \
22109 ((__INSTANCE__) == TIM7) || \
22110 ((__INSTANCE__) == TIM8))
22111
22112/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
22113#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22114 ((__INSTANCE__) == TIM2) || \
22115 ((__INSTANCE__) == TIM3) || \
22116 ((__INSTANCE__) == TIM4) || \
22117 ((__INSTANCE__) == TIM5) || \
22118 ((__INSTANCE__) == TIM8) || \
22119 ((__INSTANCE__) == TIM9) || \
22120 ((__INSTANCE__) == TIM12))
22121
22122/***************** TIM Instances : external trigger input available ************/
22123#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22124 ((__INSTANCE__) == TIM2) || \
22125 ((__INSTANCE__) == TIM3) || \
22126 ((__INSTANCE__) == TIM4) || \
22127 ((__INSTANCE__) == TIM5) || \
22128 ((__INSTANCE__) == TIM8))
22129
22130/****************** TIM Instances : remapping capability **********************/
22131#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
22132 ((__INSTANCE__) == TIM5) || \
22133 ((__INSTANCE__) == TIM11))
22134
22135/******************* TIM Instances : output(s) available **********************/
22136#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
22137 ((((__INSTANCE__) == TIM1) && \
22138 (((__CHANNEL__) == TIM_CHANNEL_1) || \
22139 ((__CHANNEL__) == TIM_CHANNEL_2) || \
22140 ((__CHANNEL__) == TIM_CHANNEL_3) || \
22141 ((__CHANNEL__) == TIM_CHANNEL_4) || \
22142 ((__CHANNEL__) == TIM_CHANNEL_5) || \
22143 ((__CHANNEL__) == TIM_CHANNEL_6))) \
22144 || \
22145 (((__INSTANCE__) == TIM2) && \
22146 (((__CHANNEL__) == TIM_CHANNEL_1) || \
22147 ((__CHANNEL__) == TIM_CHANNEL_2) || \
22148 ((__CHANNEL__) == TIM_CHANNEL_3) || \
22149 ((__CHANNEL__) == TIM_CHANNEL_4))) \
22150 || \
22151 (((__INSTANCE__) == TIM3) && \
22152 (((__CHANNEL__) == TIM_CHANNEL_1) || \
22153 ((__CHANNEL__) == TIM_CHANNEL_2) || \
22154 ((__CHANNEL__) == TIM_CHANNEL_3) || \
22155 ((__CHANNEL__) == TIM_CHANNEL_4))) \
22156 || \
22157 (((__INSTANCE__) == TIM4) && \
22158 (((__CHANNEL__) == TIM_CHANNEL_1) || \
22159 ((__CHANNEL__) == TIM_CHANNEL_2) || \
22160 ((__CHANNEL__) == TIM_CHANNEL_3) || \
22161 ((__CHANNEL__) == TIM_CHANNEL_4))) \
22162 || \
22163 (((__INSTANCE__) == TIM5) && \
22164 (((__CHANNEL__) == TIM_CHANNEL_1) || \
22165 ((__CHANNEL__) == TIM_CHANNEL_2) || \
22166 ((__CHANNEL__) == TIM_CHANNEL_3) || \
22167 ((__CHANNEL__) == TIM_CHANNEL_4))) \
22168 || \
22169 (((__INSTANCE__) == TIM8) && \
22170 (((__CHANNEL__) == TIM_CHANNEL_1) || \
22171 ((__CHANNEL__) == TIM_CHANNEL_2) || \
22172 ((__CHANNEL__) == TIM_CHANNEL_3) || \
22173 ((__CHANNEL__) == TIM_CHANNEL_4) || \
22174 ((__CHANNEL__) == TIM_CHANNEL_5) || \
22175 ((__CHANNEL__) == TIM_CHANNEL_6))) \
22176 || \
22177 (((__INSTANCE__) == TIM9) && \
22178 (((__CHANNEL__) == TIM_CHANNEL_1) || \
22179 ((__CHANNEL__) == TIM_CHANNEL_2))) \
22180 || \
22181 (((__INSTANCE__) == TIM10) && \
22182 (((__CHANNEL__) == TIM_CHANNEL_1))) \
22183 || \
22184 (((__INSTANCE__) == TIM11) && \
22185 (((__CHANNEL__) == TIM_CHANNEL_1))) \
22186 || \
22187 (((__INSTANCE__) == TIM12) && \
22188 (((__CHANNEL__) == TIM_CHANNEL_1) || \
22189 ((__CHANNEL__) == TIM_CHANNEL_2))) \
22190 || \
22191 (((__INSTANCE__) == TIM13) && \
22192 (((__CHANNEL__) == TIM_CHANNEL_1))) \
22193 || \
22194 (((__INSTANCE__) == TIM14) && \
22195 (((__CHANNEL__) == TIM_CHANNEL_1))))
22196
22197/************ TIM Instances : complementary output(s) available ***************/
22198#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
22199 ((((__INSTANCE__) == TIM1) && \
22200 (((__CHANNEL__) == TIM_CHANNEL_1) || \
22201 ((__CHANNEL__) == TIM_CHANNEL_2) || \
22202 ((__CHANNEL__) == TIM_CHANNEL_3))) \
22203 || \
22204 (((__INSTANCE__) == TIM8) && \
22205 (((__CHANNEL__) == TIM_CHANNEL_1) || \
22206 ((__CHANNEL__) == TIM_CHANNEL_2) || \
22207 ((__CHANNEL__) == TIM_CHANNEL_3))))
22208
22209/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
22210#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
22211 (((__INSTANCE__) == TIM1) || \
22212 ((__INSTANCE__) == TIM8) )
22213
22214/****************** TIM Instances : supporting clock division *****************/
22215#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22216 ((__INSTANCE__) == TIM2) || \
22217 ((__INSTANCE__) == TIM3) || \
22218 ((__INSTANCE__) == TIM4) || \
22219 ((__INSTANCE__) == TIM5) || \
22220 ((__INSTANCE__) == TIM8) || \
22221 ((__INSTANCE__) == TIM9) || \
22222 ((__INSTANCE__) == TIM10) || \
22223 ((__INSTANCE__) == TIM11) || \
22224 ((__INSTANCE__) == TIM12) || \
22225 ((__INSTANCE__) == TIM13) || \
22226 ((__INSTANCE__) == TIM14))
22227
22228/****************** TIM Instances : supporting repetition counter *************/
22229#define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22230 ((__INSTANCE__) == TIM8))
22231
22232/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
22233#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22234 ((__INSTANCE__) == TIM2) || \
22235 ((__INSTANCE__) == TIM3) || \
22236 ((__INSTANCE__) == TIM4) || \
22237 ((__INSTANCE__) == TIM5) || \
22238 ((__INSTANCE__) == TIM8) || \
22239 ((__INSTANCE__) == TIM9) || \
22240 ((__INSTANCE__) == TIM12))
22241
22242/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
22243#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22244 ((__INSTANCE__) == TIM2) || \
22245 ((__INSTANCE__) == TIM3) || \
22246 ((__INSTANCE__) == TIM4) || \
22247 ((__INSTANCE__) == TIM5) || \
22248 ((__INSTANCE__) == TIM8))
22249
22250/****************** TIM Instances : supporting Hall sensor interface **********/
22251#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22252 ((__INSTANCE__) == TIM2) || \
22253 ((__INSTANCE__) == TIM3) || \
22254 ((__INSTANCE__) == TIM4) || \
22255 ((__INSTANCE__) == TIM5) || \
22256 ((__INSTANCE__) == TIM8))
22257
22258/****************** TIM Instances : supporting commutation event generation ***/
22259#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22260 ((__INSTANCE__) == TIM8))
22261
22262/******************** USART Instances : Synchronous mode **********************/
22263#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22264 ((__INSTANCE__) == USART2) || \
22265 ((__INSTANCE__) == USART3) || \
22266 ((__INSTANCE__) == USART6))
22267
22268/******************** UART Instances : Asynchronous mode **********************/
22269#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22270 ((__INSTANCE__) == USART2) || \
22271 ((__INSTANCE__) == USART3) || \
22272 ((__INSTANCE__) == UART4) || \
22273 ((__INSTANCE__) == UART5) || \
22274 ((__INSTANCE__) == USART6) || \
22275 ((__INSTANCE__) == UART7) || \
22276 ((__INSTANCE__) == UART8))
22277
22278/****************** UART Instances : Auto Baud Rate detection ****************/
22279#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22280 ((__INSTANCE__) == USART2) || \
22281 ((__INSTANCE__) == USART3) || \
22282 ((__INSTANCE__) == USART6))
22283
22284/****************** UART Instances : Driver Enable *****************/
22285#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22286 ((__INSTANCE__) == USART2) || \
22287 ((__INSTANCE__) == USART3) || \
22288 ((__INSTANCE__) == UART4) || \
22289 ((__INSTANCE__) == UART5) || \
22290 ((__INSTANCE__) == USART6) || \
22291 ((__INSTANCE__) == UART7) || \
22292 ((__INSTANCE__) == UART8))
22293
22294/******************** UART Instances : Half-Duplex mode **********************/
22295#define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22296 ((__INSTANCE__) == USART2) || \
22297 ((__INSTANCE__) == USART3) || \
22298 ((__INSTANCE__) == UART4) || \
22299 ((__INSTANCE__) == UART5) || \
22300 ((__INSTANCE__) == USART6) || \
22301 ((__INSTANCE__) == UART7) || \
22302 ((__INSTANCE__) == UART8))
22303
22304/****************** UART Instances : Hardware Flow control ********************/
22305#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22306 ((__INSTANCE__) == USART2) || \
22307 ((__INSTANCE__) == USART3) || \
22308 ((__INSTANCE__) == UART4) || \
22309 ((__INSTANCE__) == UART5) || \
22310 ((__INSTANCE__) == USART6) || \
22311 ((__INSTANCE__) == UART7) || \
22312 ((__INSTANCE__) == UART8))
22313
22314/******************** UART Instances : LIN mode **********************/
22315#define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22316 ((__INSTANCE__) == USART2) || \
22317 ((__INSTANCE__) == USART3) || \
22318 ((__INSTANCE__) == UART4) || \
22319 ((__INSTANCE__) == UART5) || \
22320 ((__INSTANCE__) == USART6) || \
22321 ((__INSTANCE__) == UART7) || \
22322 ((__INSTANCE__) == UART8))
22323
22324/*********************** UART Instances : Wake-up from Stop mode ***************************/
22325#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22326 ((__INSTANCE__) == USART2) || \
22327 ((__INSTANCE__) == USART3) || \
22328 ((__INSTANCE__) == UART4) || \
22329 ((__INSTANCE__) == UART5) || \
22330 ((__INSTANCE__) == USART6) || \
22331 ((__INSTANCE__) == UART7) || \
22332 ((__INSTANCE__) == UART8))
22333
22334/********************* UART Instances : Smart card mode ***********************/
22335#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22336 ((__INSTANCE__) == USART2) || \
22337 ((__INSTANCE__) == USART3) || \
22338 ((__INSTANCE__) == USART6))
22339
22340/*********************** UART Instances : IRDA mode ***************************/
22341#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
22342 ((__INSTANCE__) == USART2) || \
22343 ((__INSTANCE__) == USART3) || \
22344 ((__INSTANCE__) == UART4) || \
22345 ((__INSTANCE__) == UART5) || \
22346 ((__INSTANCE__) == USART6) || \
22347 ((__INSTANCE__) == UART7) || \
22348 ((__INSTANCE__) == UART8))
22349
22350/****************************** IWDG Instances ********************************/
22351#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
22352
22353/****************************** WWDG Instances ********************************/
22354#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
22355
22356/*********************** PCD Instances ****************************************/
22357#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
22358 ((INSTANCE) == USB_OTG_HS))
22359
22360/*********************** HCD Instances ****************************************/
22361#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
22362 ((INSTANCE) == USB_OTG_HS))
22363
22364/******************************************************************************/
22365/* For a painless codes migration between the STM32F7xx device product */
22366/* lines, the aliases defined below are put in place to overcome the */
22367/* differences in the interrupt handlers and IRQn definitions. */
22368/* No need to update developed interrupt code when moving across */
22369/* product lines within the same STM32F7 Family */
22370/******************************************************************************/
22371
22372/* Aliases for __IRQn */
22373#define RNG_IRQn HASH_RNG_IRQn
22374
22375/* Aliases for __IRQHandler */
22376#define RNG_IRQHandler HASH_RNG_IRQHandler
22377
22390#ifdef __cplusplus
22391}
22392#endif /* __cplusplus */
22393
22394#endif /* __STM32F779xx_H */
22395
22396
22397/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition core_cm3.h:170
__I
#define __I
Definition core_cm3.h:167
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f779xx.h:50
PendSV_IRQn
@ PendSV_IRQn
Definition stm32f779xx.h:58
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition stm32f779xx.h:123
EXTI2_IRQn
@ EXTI2_IRQn
Definition stm32f779xx.h:69
MDIOS_IRQn
@ MDIOS_IRQn
Definition stm32f779xx.h:170
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition stm32f779xx.h:74
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition stm32f779xx.h:83
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition stm32f779xx.h:64
SPDIF_RX_IRQn
@ SPDIF_RX_IRQn
Definition stm32f779xx.h:158
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition stm32f779xx.h:136
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition stm32f779xx.h:117
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition stm32f779xx.h:130
UART7_IRQn
@ UART7_IRQn
Definition stm32f779xx.h:143
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition stm32f779xx.h:93
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition stm32f779xx.h:94
CAN3_SCE_IRQn
@ CAN3_SCE_IRQn
Definition stm32f779xx.h:168
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition stm32f779xx.h:53
SAI1_IRQn
@ SAI1_IRQn
Definition stm32f779xx.h:148
TIM4_IRQn
@ TIM4_IRQn
Definition stm32f779xx.h:91
TIM2_IRQn
@ TIM2_IRQn
Definition stm32f779xx.h:89
LTDC_ER_IRQn
@ LTDC_ER_IRQn
Definition stm32f779xx.h:150
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition stm32f779xx.h:131
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition stm32f779xx.h:104
USART2_IRQn
@ USART2_IRQn
Definition stm32f779xx.h:99
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition stm32f779xx.h:120
SVCall_IRQn
@ SVCall_IRQn
Definition stm32f779xx.h:56
ADC_IRQn
@ ADC_IRQn
Definition stm32f779xx.h:79
SPI3_IRQn
@ SPI3_IRQn
Definition stm32f779xx.h:112
SPI2_IRQn
@ SPI2_IRQn
Definition stm32f779xx.h:97
TIM7_IRQn
@ TIM7_IRQn
Definition stm32f779xx.h:116
UART8_IRQn
@ UART8_IRQn
Definition stm32f779xx.h:144
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition stm32f779xx.h:127
RCC_IRQn
@ RCC_IRQn
Definition stm32f779xx.h:66
CAN3_RX0_IRQn
@ CAN3_RX0_IRQn
Definition stm32f779xx.h:166
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition stm32f779xx.h:115
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition stm32f779xx.h:135
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition stm32f779xx.h:95
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition stm32f779xx.h:153
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition stm32f779xx.h:160
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition stm32f779xx.h:107
JPEG_IRQn
@ JPEG_IRQn
Definition stm32f779xx.h:169
UsageFault_IRQn
@ UsageFault_IRQn
Definition stm32f779xx.h:55
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition stm32f779xx.h:157
SysTick_IRQn
@ SysTick_IRQn
Definition stm32f779xx.h:59
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition stm32f779xx.h:134
CRYP_IRQn
@ CRYP_IRQn
Definition stm32f779xx.h:140
DFSDM1_FLT3_IRQn
@ DFSDM1_FLT3_IRQn
Definition stm32f779xx.h:163
CAN3_TX_IRQn
@ CAN3_TX_IRQn
Definition stm32f779xx.h:165
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition stm32f779xx.h:133
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition stm32f779xx.h:125
BusFault_IRQn
@ BusFault_IRQn
Definition stm32f779xx.h:54
HASH_RNG_IRQn
@ HASH_RNG_IRQn
Definition stm32f779xx.h:141
CEC_IRQn
@ CEC_IRQn
Definition stm32f779xx.h:155
SPI5_IRQn
@ SPI5_IRQn
Definition stm32f779xx.h:146
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition stm32f779xx.h:57
FLASH_IRQn
@ FLASH_IRQn
Definition stm32f779xx.h:65
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition stm32f779xx.h:129
WWDG_IRQn
@ WWDG_IRQn
Definition stm32f779xx.h:61
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition stm32f779xx.h:92
TIM3_IRQn
@ TIM3_IRQn
Definition stm32f779xx.h:90
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition stm32f779xx.h:118
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition stm32f779xx.h:80
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition stm32f779xx.h:137
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition stm32f779xx.h:110
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition stm32f779xx.h:72
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition stm32f779xx.h:101
SPI4_IRQn
@ SPI4_IRQn
Definition stm32f779xx.h:145
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f779xx.h:86
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition stm32f779xx.h:84
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition stm32f779xx.h:73
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition stm32f779xx.h:154
SPI6_IRQn
@ SPI6_IRQn
Definition stm32f779xx.h:147
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition stm32f779xx.h:128
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition stm32f779xx.h:103
FPU_IRQn
@ FPU_IRQn
Definition stm32f779xx.h:142
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition stm32f779xx.h:105
USART6_IRQn
@ USART6_IRQn
Definition stm32f779xx.h:132
SPI1_IRQn
@ SPI1_IRQn
Definition stm32f779xx.h:96
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition stm32f779xx.h:138
PVD_IRQn
@ PVD_IRQn
Definition stm32f779xx.h:62
DFSDM1_FLT2_IRQn
@ DFSDM1_FLT2_IRQn
Definition stm32f779xx.h:162
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f779xx.h:87
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition stm32f779xx.h:85
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition stm32f779xx.h:126
FMC_IRQn
@ FMC_IRQn
Definition stm32f779xx.h:109
EXTI0_IRQn
@ EXTI0_IRQn
Definition stm32f779xx.h:67
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition stm32f779xx.h:81
EXTI4_IRQn
@ EXTI4_IRQn
Definition stm32f779xx.h:71
DSI_IRQn
@ DSI_IRQn
Definition stm32f779xx.h:159
SAI2_IRQn
@ SAI2_IRQn
Definition stm32f779xx.h:152
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition stm32f779xx.h:119
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f779xx.h:63
UART5_IRQn
@ UART5_IRQn
Definition stm32f779xx.h:114
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition stm32f779xx.h:77
DMA2D_IRQn
@ DMA2D_IRQn
Definition stm32f779xx.h:151
DCMI_IRQn
@ DCMI_IRQn
Definition stm32f779xx.h:139
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition stm32f779xx.h:156
ETH_IRQn
@ ETH_IRQn
Definition stm32f779xx.h:122
CAN3_RX1_IRQn
@ CAN3_RX1_IRQn
Definition stm32f779xx.h:167
USART1_IRQn
@ USART1_IRQn
Definition stm32f779xx.h:98
EXTI3_IRQn
@ EXTI3_IRQn
Definition stm32f779xx.h:70
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition stm32f779xx.h:52
UART4_IRQn
@ UART4_IRQn
Definition stm32f779xx.h:113
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition stm32f779xx.h:106
EXTI1_IRQn
@ EXTI1_IRQn
Definition stm32f779xx.h:68
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition stm32f779xx.h:121
TIM5_IRQn
@ TIM5_IRQn
Definition stm32f779xx.h:111
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition stm32f779xx.h:108
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f779xx.h:76
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition stm32f779xx.h:78
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition stm32f779xx.h:88
LTDC_IRQn
@ LTDC_IRQn
Definition stm32f779xx.h:149
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition stm32f779xx.h:124
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition stm32f779xx.h:82
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition stm32f779xx.h:75
SDMMC2_IRQn
@ SDMMC2_IRQn
Definition stm32f779xx.h:164
USART3_IRQn
@ USART3_IRQn
Definition stm32f779xx.h:100
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition stm32f779xx.h:102
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition stm32f779xx.h:161
PMC
#define PMC
Definition MK60D10.h:8809
ADC_Common_TypeDef
Definition stm32f107xc.h:187
ADC_TypeDef
Analog to Digital Converter
Definition stm32f107xc.h:163
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition stm32f107xc.h:267
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition stm32f107xc.h:279
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition stm32f107xc.h:255
CAN_TypeDef
Controller Area Network.
Definition stm32f107xc.h:289
CEC_TypeDef
HDMI-CEC.
Definition stm32f745xx.h:287
CRC_TypeDef
CRC calculation unit.
Definition stm32f107xc.h:319
CRYP_TypeDef
Crypto Processor.
Definition stm32f217xx.h:784
DAC_TypeDef
Digital to Analog Converter.
Definition stm32f107xc.h:332
DBGMCU_TypeDef
Debug MCU.
Definition stm32f107xc.h:353
DCMI_TypeDef
DCMI.
Definition stm32f207xx.h:325
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition stm32f765xx.h:370
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition stm32f765xx.h:348
DIR
Definition ff_types.h:208
DMA2D_TypeDef
DMA2D Controller.
Definition stm32f427xx.h:373
DMA_Stream_TypeDef
DMA Controller.
Definition stm32f207xx.h:344
DMA_TypeDef
Definition stm32f107xc.h:371
DSI_TypeDef
DSI Controller.
Definition stm32f469xx.h:408
ETH_TypeDef
Ethernet MAC.
Definition stm32f107xc.h:383
EXTI_TypeDef
External Interrupt/Event Controller.
Definition stm32f107xc.h:455
FLASH_TypeDef
FLASH Registers.
Definition stm32f107xc.h:469
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition stm32f427xx.h:517
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition stm32f427xx.h:508
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition stm32f469xx.h:611
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition stm32f427xx.h:560
GPIO_TypeDef
General Purpose I/O.
Definition stm32f107xc.h:502
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition stm32f417xx.h:843
HASH_TypeDef
HASH.
Definition stm32f217xx.h:812
I2C_TypeDef
Inter Integrated Circuit Interface.
Definition stm32f107xc.h:529
IWDG_TypeDef
Independent WATCHDOG.
Definition stm32f107xc.h:546
JPEG_TypeDef
JPEG Codec.
Definition stm32f767xx.h:1175
LPTIM_TypeDef
LPTIMIMER.
Definition stm32f745xx.h:892
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition stm32f429xx.h:660
LTDC_TypeDef
LCD-TFT Display Controller.
Definition stm32f429xx.h:635
MDIOS_TypeDef
MDIOS.
Definition stm32f765xx.h:1126
PWR_TypeDef
Power Control.
Definition stm32f107xc.h:558
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition stm32f469xx.h:909
RCC_TypeDef
Reset and Clock Control.
Definition stm32f107xc.h:568
RNG_TypeDef
RNG.
Definition stm32f207xx.h:782
RTC_TypeDef
Real-Time Clock.
Definition stm32f107xc.h:590
SAI_Block_TypeDef
Definition stm32f427xx.h:737
SAI_TypeDef
Serial Audio Interface.
Definition stm32f427xx.h:732
SDMMC_TypeDef
SD host Interface.
Definition stm32f745xx.h:794
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition stm32f745xx.h:779
SPI_TypeDef
Serial Peripheral Interface.
Definition stm32f107xc.h:608
SYSCFG_TypeDef
System configuration controller.
Definition stm32f207xx.h:542
TIM_TypeDef
TIM Timers.
Definition stm32f107xc.h:624
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32f107xc.h:654
USB_OTG_DeviceTypeDef
__device_Registers
Definition stm32f107xc.h:696
USB_OTG_GlobalTypeDef
__USB_OTG_Core_register
Definition stm32f107xc.h:670
USB_OTG_HostChannelTypeDef
__Host_Channel_Specific_Registers
Definition stm32f107xc.h:770
USB_OTG_HostTypeDef
__Host_Mode_Register_Structures
Definition stm32f107xc.h:755
USB_OTG_INEndpointTypeDef
__IN_Endpoint-Specific_Register
Definition stm32f107xc.h:724
USB_OTG_OUTEndpointTypeDef
__OUT_Endpoint-Specific_Registers
Definition stm32f107xc.h:740
WWDG_TypeDef
Window WATCHDOG.
Definition stm32f107xc.h:785
system_stm32f7xx.h
CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.