CMP Peripheral Access Layer

Topics
	CMP Register Masks
	CMT Peripheral Access Layer

Data Structures
struct	CMP_Type

Macros
#define	CMP0_BASE   (0x40073000u)
#define	CMP0   ((CMP_Type *)CMP0_BASE)
#define	CMP1_BASE   (0x40073008u)
#define	CMP1   ((CMP_Type *)CMP1_BASE)
#define	CMP2_BASE   (0x40073010u)
#define	CMP2   ((CMP_Type *)CMP2_BASE)
#define	CMP0_BASE   (0x40073000u)
#define	CMP0   ((CMP_Type *)CMP0_BASE)
#define	CMP1_BASE   (0x40073008u)
#define	CMP1   ((CMP_Type *)CMP1_BASE)
#define	CMP2_BASE   (0x40073010u)
#define	CMP2   ((CMP_Type *)CMP2_BASE)
#define	CMP_BASE_ADDRS   { CMP0_BASE, CMP1_BASE, CMP2_BASE }
#define	CMP_BASE_PTRS   { CMP0, CMP1, CMP2 }
#define	CMP_IRQS   { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
#define	CMP0_BASE   (0x40073000u)
#define	CMP0   ((CMP_Type *)CMP0_BASE)
#define	CMP1_BASE   (0x40073008u)
#define	CMP1   ((CMP_Type *)CMP1_BASE)
#define	CMP2_BASE   (0x40073010u)
#define	CMP2   ((CMP_Type *)CMP2_BASE)
#define	CMP3_BASE   (0x40073018u)
#define	CMP3   ((CMP_Type *)CMP3_BASE)
#define	CMP_BASE_ADDRS   { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
#define	CMP_BASE_PTRS   { CMP0, CMP1, CMP2, CMP3 }
#define	CMP_IRQS   { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }
#define	CMP0_BASE   (0x40073000u)
#define	CMP0   ((CMP_Type *)CMP0_BASE)
#define	CMP1_BASE   (0x40073008u)
#define	CMP1   ((CMP_Type *)CMP1_BASE)
#define	CMP2_BASE   (0x40073010u)
#define	CMP2   ((CMP_Type *)CMP2_BASE)
#define	CMP3_BASE   (0x40073018u)
#define	CMP3   ((CMP_Type *)CMP3_BASE)
#define	CMP_BASE_ADDRS   { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
#define	CMP_BASE_PTRS   { CMP0, CMP1, CMP2, CMP3 }
#define	CMP_IRQS   { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }
#define	CMP0_BASE   (0x40073000u)
#define	CMP0   ((CMP_Type *)CMP0_BASE)
#define	CMP1_BASE   (0x40073008u)
#define	CMP1   ((CMP_Type *)CMP1_BASE)
#define	CMP2_BASE   (0x40073010u)
#define	CMP2   ((CMP_Type *)CMP2_BASE)
#define	CMP3_BASE   (0x40073018u)
#define	CMP3   ((CMP_Type *)CMP3_BASE)
#define	CMP_BASE_ADDRS   { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
#define	CMP_BASE_PTRS   { CMP0, CMP1, CMP2, CMP3 }
#define	CMP_IRQS   { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }

Macro Definition Documentation

CMP0 [1/5]

#define CMP0   ((CMP_Type *)CMP0_BASE)

Peripheral CMP0 base pointer

CMP0 [2/5]

#define CMP0   ((CMP_Type *)CMP0_BASE)

Peripheral CMP0 base pointer

CMP0 [3/5]

#define CMP0   ((CMP_Type *)CMP0_BASE)

Peripheral CMP0 base pointer

CMP0 [4/5]

#define CMP0   ((CMP_Type *)CMP0_BASE)

Peripheral CMP0 base pointer

CMP0 [5/5]

#define CMP0   ((CMP_Type *)CMP0_BASE)

Peripheral CMP0 base pointer

CMP0_BASE [1/5]

#define CMP0_BASE   (0x40073000u)

Peripheral CMP0 base address

CMP0_BASE [2/5]

#define CMP0_BASE   (0x40073000u)

Peripheral CMP0 base address

CMP0_BASE [3/5]

#define CMP0_BASE   (0x40073000u)

Peripheral CMP0 base address

CMP0_BASE [4/5]

#define CMP0_BASE   (0x40073000u)

Peripheral CMP0 base address

CMP0_BASE [5/5]

#define CMP0_BASE   (0x40073000u)

Peripheral CMP0 base address

CMP1 [1/5]

#define CMP1   ((CMP_Type *)CMP1_BASE)

Peripheral CMP1 base pointer

CMP1 [2/5]

#define CMP1   ((CMP_Type *)CMP1_BASE)

Peripheral CMP1 base pointer

CMP1 [3/5]

#define CMP1   ((CMP_Type *)CMP1_BASE)

Peripheral CMP1 base pointer

CMP1 [4/5]

#define CMP1   ((CMP_Type *)CMP1_BASE)

Peripheral CMP1 base pointer

CMP1 [5/5]

#define CMP1   ((CMP_Type *)CMP1_BASE)

Peripheral CMP1 base pointer

CMP1_BASE [1/5]

#define CMP1_BASE   (0x40073008u)

Peripheral CMP1 base address

CMP1_BASE [2/5]

#define CMP1_BASE   (0x40073008u)

Peripheral CMP1 base address

CMP1_BASE [3/5]

#define CMP1_BASE   (0x40073008u)

Peripheral CMP1 base address

CMP1_BASE [4/5]

#define CMP1_BASE   (0x40073008u)

Peripheral CMP1 base address

CMP1_BASE [5/5]

#define CMP1_BASE   (0x40073008u)

Peripheral CMP1 base address

CMP2 [1/5]

#define CMP2   ((CMP_Type *)CMP2_BASE)

Peripheral CMP2 base pointer

CMP2 [2/5]

#define CMP2   ((CMP_Type *)CMP2_BASE)

Peripheral CMP2 base pointer

CMP2 [3/5]

#define CMP2   ((CMP_Type *)CMP2_BASE)

Peripheral CMP2 base pointer

CMP2 [4/5]

#define CMP2   ((CMP_Type *)CMP2_BASE)

Peripheral CMP2 base pointer

CMP2 [5/5]

#define CMP2   ((CMP_Type *)CMP2_BASE)

Peripheral CMP2 base pointer

CMP2_BASE [1/5]

#define CMP2_BASE   (0x40073010u)

Peripheral CMP2 base address

CMP2_BASE [2/5]

#define CMP2_BASE   (0x40073010u)

Peripheral CMP2 base address

CMP2_BASE [3/5]

#define CMP2_BASE   (0x40073010u)

Peripheral CMP2 base address

CMP2_BASE [4/5]

#define CMP2_BASE   (0x40073010u)

Peripheral CMP2 base address

CMP2_BASE [5/5]

#define CMP2_BASE   (0x40073010u)

Peripheral CMP2 base address

CMP3 [1/3]

#define CMP3   ((CMP_Type *)CMP3_BASE)

Peripheral CMP3 base pointer

CMP3 [2/3]

#define CMP3   ((CMP_Type *)CMP3_BASE)

Peripheral CMP3 base pointer

CMP3 [3/3]

#define CMP3   ((CMP_Type *)CMP3_BASE)

Peripheral CMP3 base pointer

CMP3_BASE [1/3]

#define CMP3_BASE   (0x40073018u)

Peripheral CMP3 base address

CMP3_BASE [2/3]

#define CMP3_BASE   (0x40073018u)

Peripheral CMP3 base address

CMP3_BASE [3/3]

#define CMP3_BASE   (0x40073018u)

Peripheral CMP3 base address

CMP_BASE_ADDRS [1/4]

#define CMP_BASE_ADDRS   { CMP0_BASE, CMP1_BASE, CMP2_BASE }

Array initializer of CMP peripheral base addresses

CMP_BASE_ADDRS [2/4]

#define CMP_BASE_ADDRS   { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }

Array initializer of CMP peripheral base addresses

CMP_BASE_ADDRS [3/4]

#define CMP_BASE_ADDRS   { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }

Array initializer of CMP peripheral base addresses

CMP_BASE_ADDRS [4/4]

#define CMP_BASE_ADDRS   { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }

Array initializer of CMP peripheral base addresses

CMP_BASE_PTRS [1/4]

#define CMP_BASE_PTRS   { CMP0, CMP1, CMP2 }

Array initializer of CMP peripheral base pointers

CMP_BASE_PTRS [2/4]

#define CMP_BASE_PTRS   { CMP0, CMP1, CMP2, CMP3 }

Array initializer of CMP peripheral base pointers

CMP_BASE_PTRS [3/4]

#define CMP_BASE_PTRS   { CMP0, CMP1, CMP2, CMP3 }

Array initializer of CMP peripheral base pointers

CMP_BASE_PTRS [4/4]

#define CMP_BASE_PTRS   { CMP0, CMP1, CMP2, CMP3 }

Array initializer of CMP peripheral base pointers

CMP_IRQS [1/4]

#define CMP_IRQS   { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }

Interrupt vectors for the CMP peripheral type

CMP_IRQS [2/4]

#define CMP_IRQS   { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }

Interrupt vectors for the CMP peripheral type

CMP_IRQS [3/4]

#define CMP_IRQS   { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }

Interrupt vectors for the CMP peripheral type

CMP_IRQS [4/4]

#define CMP_IRQS   { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }

Interrupt vectors for the CMP peripheral type