CMP Register Masks

Macros
#define	CMP0_BASE   (0x40073000u)
#define	CMP0   ((CMP_Type *)CMP0_BASE)
#define	CMP1_BASE   (0x40073008u)
#define	CMP1   ((CMP_Type *)CMP1_BASE)
#define	CMP2_BASE   (0x40073010u)
#define	CMP2   ((CMP_Type *)CMP2_BASE)
#define	CMP_BASE_ADDRS   { CMP0_BASE, CMP1_BASE, CMP2_BASE }
#define	CMP_BASE_PTRS   { CMP0, CMP1, CMP2 }
#define	CMP_IRQS   { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
#define	CMP_SCR_SMELB_MASK   0x20u
#define	CMP_SCR_SMELB_SHIFT   5
#define	CMP_MUXCR_MEN_MASK   0x40u
#define	CMP_MUXCR_MEN_SHIFT   6
#define	CMP_MUXCR_PEN_MASK   0x80u
#define	CMP_MUXCR_PEN_SHIFT   7

CR0 - CMP Control Register 0
#define	CMP_CR0_HYSTCTR_MASK   (0x3U)
#define	CMP_CR0_HYSTCTR_SHIFT   (0U)
#define	CMP_CR0_HYSTCTR(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
#define	CMP_CR0_FILTER_CNT_MASK   (0x70U)
#define	CMP_CR0_FILTER_CNT_SHIFT   (4U)
#define	CMP_CR0_FILTER_CNT(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
#define	CMP_CR0_HYSTCTR_MASK   0x3u
#define	CMP_CR0_HYSTCTR_SHIFT   0
#define	CMP_CR0_HYSTCTR(x)   (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
#define	CMP_CR0_FILTER_CNT_MASK   0x70u
#define	CMP_CR0_FILTER_CNT_SHIFT   4
#define	CMP_CR0_FILTER_CNT(x)   (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
#define	CMP_CR0_HYSTCTR_MASK   (0x3U)
#define	CMP_CR0_HYSTCTR_SHIFT   (0U)
#define	CMP_CR0_HYSTCTR(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
#define	CMP_CR0_FILTER_CNT_MASK   (0x70U)
#define	CMP_CR0_FILTER_CNT_SHIFT   (4U)
#define	CMP_CR0_FILTER_CNT(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
#define	CMP_CR0_HYSTCTR_MASK   (0x3U)
#define	CMP_CR0_HYSTCTR_SHIFT   (0U)
#define	CMP_CR0_HYSTCTR(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
#define	CMP_CR0_FILTER_CNT_MASK   (0x70U)
#define	CMP_CR0_FILTER_CNT_SHIFT   (4U)
#define	CMP_CR0_FILTER_CNT(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
#define	CMP_CR0_HYSTCTR_MASK   (0x3U)
#define	CMP_CR0_HYSTCTR_SHIFT   (0U)
#define	CMP_CR0_HYSTCTR(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
#define	CMP_CR0_FILTER_CNT_MASK   (0x70U)
#define	CMP_CR0_FILTER_CNT_SHIFT   (4U)
#define	CMP_CR0_FILTER_CNT(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
#define	CMP_CR0_HYSTCTR_MASK   (0x3U)
#define	CMP_CR0_HYSTCTR_SHIFT   (0U)
#define	CMP_CR0_HYSTCTR(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
#define	CMP_CR0_FILTER_CNT_MASK   (0x70U)
#define	CMP_CR0_FILTER_CNT_SHIFT   (4U)
#define	CMP_CR0_FILTER_CNT(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)

CR1 - CMP Control Register 1
#define	CMP_CR1_EN_MASK   (0x1U)
#define	CMP_CR1_EN_SHIFT   (0U)
#define	CMP_CR1_EN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
#define	CMP_CR1_OPE_MASK   (0x2U)
#define	CMP_CR1_OPE_SHIFT   (1U)
#define	CMP_CR1_OPE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
#define	CMP_CR1_COS_MASK   (0x4U)
#define	CMP_CR1_COS_SHIFT   (2U)
#define	CMP_CR1_COS(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
#define	CMP_CR1_INV_MASK   (0x8U)
#define	CMP_CR1_INV_SHIFT   (3U)
#define	CMP_CR1_INV(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
#define	CMP_CR1_PMODE_MASK   (0x10U)
#define	CMP_CR1_PMODE_SHIFT   (4U)
#define	CMP_CR1_PMODE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
#define	CMP_CR1_WE_MASK   (0x40U)
#define	CMP_CR1_WE_SHIFT   (6U)
#define	CMP_CR1_WE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
#define	CMP_CR1_SE_MASK   (0x80U)
#define	CMP_CR1_SE_SHIFT   (7U)
#define	CMP_CR1_SE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
#define	CMP_CR1_EN_MASK   0x1u
#define	CMP_CR1_EN_SHIFT   0
#define	CMP_CR1_OPE_MASK   0x2u
#define	CMP_CR1_OPE_SHIFT   1
#define	CMP_CR1_COS_MASK   0x4u
#define	CMP_CR1_COS_SHIFT   2
#define	CMP_CR1_INV_MASK   0x8u
#define	CMP_CR1_INV_SHIFT   3
#define	CMP_CR1_PMODE_MASK   0x10u
#define	CMP_CR1_PMODE_SHIFT   4
#define	CMP_CR1_WE_MASK   0x40u
#define	CMP_CR1_WE_SHIFT   6
#define	CMP_CR1_SE_MASK   0x80u
#define	CMP_CR1_SE_SHIFT   7
#define	CMP_CR1_EN_MASK   (0x1U)
#define	CMP_CR1_EN_SHIFT   (0U)
#define	CMP_CR1_EN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
#define	CMP_CR1_OPE_MASK   (0x2U)
#define	CMP_CR1_OPE_SHIFT   (1U)
#define	CMP_CR1_OPE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
#define	CMP_CR1_COS_MASK   (0x4U)
#define	CMP_CR1_COS_SHIFT   (2U)
#define	CMP_CR1_COS(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
#define	CMP_CR1_INV_MASK   (0x8U)
#define	CMP_CR1_INV_SHIFT   (3U)
#define	CMP_CR1_INV(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
#define	CMP_CR1_PMODE_MASK   (0x10U)
#define	CMP_CR1_PMODE_SHIFT   (4U)
#define	CMP_CR1_PMODE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
#define	CMP_CR1_WE_MASK   (0x40U)
#define	CMP_CR1_WE_SHIFT   (6U)
#define	CMP_CR1_WE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
#define	CMP_CR1_SE_MASK   (0x80U)
#define	CMP_CR1_SE_SHIFT   (7U)
#define	CMP_CR1_SE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
#define	CMP_CR1_EN_MASK   (0x1U)
#define	CMP_CR1_EN_SHIFT   (0U)
#define	CMP_CR1_EN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
#define	CMP_CR1_OPE_MASK   (0x2U)
#define	CMP_CR1_OPE_SHIFT   (1U)
#define	CMP_CR1_OPE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
#define	CMP_CR1_COS_MASK   (0x4U)
#define	CMP_CR1_COS_SHIFT   (2U)
#define	CMP_CR1_COS(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
#define	CMP_CR1_INV_MASK   (0x8U)
#define	CMP_CR1_INV_SHIFT   (3U)
#define	CMP_CR1_INV(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
#define	CMP_CR1_PMODE_MASK   (0x10U)
#define	CMP_CR1_PMODE_SHIFT   (4U)
#define	CMP_CR1_PMODE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
#define	CMP_CR1_TRIGM_MASK   (0x20U)
#define	CMP_CR1_TRIGM_SHIFT   (5U)
#define	CMP_CR1_TRIGM(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
#define	CMP_CR1_WE_MASK   (0x40U)
#define	CMP_CR1_WE_SHIFT   (6U)
#define	CMP_CR1_WE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
#define	CMP_CR1_SE_MASK   (0x80U)
#define	CMP_CR1_SE_SHIFT   (7U)
#define	CMP_CR1_SE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
#define	CMP_CR1_EN_MASK   (0x1U)
#define	CMP_CR1_EN_SHIFT   (0U)
#define	CMP_CR1_EN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
#define	CMP_CR1_OPE_MASK   (0x2U)
#define	CMP_CR1_OPE_SHIFT   (1U)
#define	CMP_CR1_OPE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
#define	CMP_CR1_COS_MASK   (0x4U)
#define	CMP_CR1_COS_SHIFT   (2U)
#define	CMP_CR1_COS(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
#define	CMP_CR1_INV_MASK   (0x8U)
#define	CMP_CR1_INV_SHIFT   (3U)
#define	CMP_CR1_INV(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
#define	CMP_CR1_PMODE_MASK   (0x10U)
#define	CMP_CR1_PMODE_SHIFT   (4U)
#define	CMP_CR1_PMODE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
#define	CMP_CR1_TRIGM_MASK   (0x20U)
#define	CMP_CR1_TRIGM_SHIFT   (5U)
#define	CMP_CR1_TRIGM(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
#define	CMP_CR1_WE_MASK   (0x40U)
#define	CMP_CR1_WE_SHIFT   (6U)
#define	CMP_CR1_WE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
#define	CMP_CR1_SE_MASK   (0x80U)
#define	CMP_CR1_SE_SHIFT   (7U)
#define	CMP_CR1_SE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
#define	CMP_CR1_EN_MASK   (0x1U)
#define	CMP_CR1_EN_SHIFT   (0U)
#define	CMP_CR1_EN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
#define	CMP_CR1_OPE_MASK   (0x2U)
#define	CMP_CR1_OPE_SHIFT   (1U)
#define	CMP_CR1_OPE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
#define	CMP_CR1_COS_MASK   (0x4U)
#define	CMP_CR1_COS_SHIFT   (2U)
#define	CMP_CR1_COS(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
#define	CMP_CR1_INV_MASK   (0x8U)
#define	CMP_CR1_INV_SHIFT   (3U)
#define	CMP_CR1_INV(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
#define	CMP_CR1_PMODE_MASK   (0x10U)
#define	CMP_CR1_PMODE_SHIFT   (4U)
#define	CMP_CR1_PMODE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
#define	CMP_CR1_TRIGM_MASK   (0x20U)
#define	CMP_CR1_TRIGM_SHIFT   (5U)
#define	CMP_CR1_TRIGM(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
#define	CMP_CR1_WE_MASK   (0x40U)
#define	CMP_CR1_WE_SHIFT   (6U)
#define	CMP_CR1_WE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
#define	CMP_CR1_SE_MASK   (0x80U)
#define	CMP_CR1_SE_SHIFT   (7U)
#define	CMP_CR1_SE(x)   (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)

FPR - CMP Filter Period Register
#define	CMP_FPR_FILT_PER_MASK   (0xFFU)
#define	CMP_FPR_FILT_PER_SHIFT   (0U)
#define	CMP_FPR_FILT_PER(x)   (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
#define	CMP_FPR_FILT_PER_MASK   0xFFu
#define	CMP_FPR_FILT_PER_SHIFT   0
#define	CMP_FPR_FILT_PER(x)   (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
#define	CMP_FPR_FILT_PER_MASK   (0xFFU)
#define	CMP_FPR_FILT_PER_SHIFT   (0U)
#define	CMP_FPR_FILT_PER(x)   (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
#define	CMP_FPR_FILT_PER_MASK   (0xFFU)
#define	CMP_FPR_FILT_PER_SHIFT   (0U)
#define	CMP_FPR_FILT_PER(x)   (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
#define	CMP_FPR_FILT_PER_MASK   (0xFFU)
#define	CMP_FPR_FILT_PER_SHIFT   (0U)
#define	CMP_FPR_FILT_PER(x)   (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
#define	CMP_FPR_FILT_PER_MASK   (0xFFU)
#define	CMP_FPR_FILT_PER_SHIFT   (0U)
#define	CMP_FPR_FILT_PER(x)   (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)

SCR - CMP Status and Control Register
#define	CMP_SCR_COUT_MASK   (0x1U)
#define	CMP_SCR_COUT_SHIFT   (0U)
#define	CMP_SCR_COUT(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
#define	CMP_SCR_CFF_MASK   (0x2U)
#define	CMP_SCR_CFF_SHIFT   (1U)
#define	CMP_SCR_CFF(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
#define	CMP_SCR_CFR_MASK   (0x4U)
#define	CMP_SCR_CFR_SHIFT   (2U)
#define	CMP_SCR_CFR(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
#define	CMP_SCR_IEF_MASK   (0x8U)
#define	CMP_SCR_IEF_SHIFT   (3U)
#define	CMP_SCR_IEF(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
#define	CMP_SCR_IER_MASK   (0x10U)
#define	CMP_SCR_IER_SHIFT   (4U)
#define	CMP_SCR_IER(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
#define	CMP_SCR_DMAEN_MASK   (0x40U)
#define	CMP_SCR_DMAEN_SHIFT   (6U)
#define	CMP_SCR_DMAEN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
#define	CMP_SCR_COUT_MASK   0x1u
#define	CMP_SCR_COUT_SHIFT   0
#define	CMP_SCR_CFF_MASK   0x2u
#define	CMP_SCR_CFF_SHIFT   1
#define	CMP_SCR_CFR_MASK   0x4u
#define	CMP_SCR_CFR_SHIFT   2
#define	CMP_SCR_IEF_MASK   0x8u
#define	CMP_SCR_IEF_SHIFT   3
#define	CMP_SCR_IER_MASK   0x10u
#define	CMP_SCR_IER_SHIFT   4
#define	CMP_SCR_DMAEN_MASK   0x40u
#define	CMP_SCR_DMAEN_SHIFT   6
#define	CMP_SCR_COUT_MASK   (0x1U)
#define	CMP_SCR_COUT_SHIFT   (0U)
#define	CMP_SCR_COUT(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
#define	CMP_SCR_CFF_MASK   (0x2U)
#define	CMP_SCR_CFF_SHIFT   (1U)
#define	CMP_SCR_CFF(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
#define	CMP_SCR_CFR_MASK   (0x4U)
#define	CMP_SCR_CFR_SHIFT   (2U)
#define	CMP_SCR_CFR(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
#define	CMP_SCR_IEF_MASK   (0x8U)
#define	CMP_SCR_IEF_SHIFT   (3U)
#define	CMP_SCR_IEF(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
#define	CMP_SCR_IER_MASK   (0x10U)
#define	CMP_SCR_IER_SHIFT   (4U)
#define	CMP_SCR_IER(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
#define	CMP_SCR_DMAEN_MASK   (0x40U)
#define	CMP_SCR_DMAEN_SHIFT   (6U)
#define	CMP_SCR_DMAEN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
#define	CMP_SCR_COUT_MASK   (0x1U)
#define	CMP_SCR_COUT_SHIFT   (0U)
#define	CMP_SCR_COUT(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
#define	CMP_SCR_CFF_MASK   (0x2U)
#define	CMP_SCR_CFF_SHIFT   (1U)
#define	CMP_SCR_CFF(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
#define	CMP_SCR_CFR_MASK   (0x4U)
#define	CMP_SCR_CFR_SHIFT   (2U)
#define	CMP_SCR_CFR(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
#define	CMP_SCR_IEF_MASK   (0x8U)
#define	CMP_SCR_IEF_SHIFT   (3U)
#define	CMP_SCR_IEF(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
#define	CMP_SCR_IER_MASK   (0x10U)
#define	CMP_SCR_IER_SHIFT   (4U)
#define	CMP_SCR_IER(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
#define	CMP_SCR_DMAEN_MASK   (0x40U)
#define	CMP_SCR_DMAEN_SHIFT   (6U)
#define	CMP_SCR_DMAEN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
#define	CMP_SCR_COUT_MASK   (0x1U)
#define	CMP_SCR_COUT_SHIFT   (0U)
#define	CMP_SCR_COUT(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
#define	CMP_SCR_CFF_MASK   (0x2U)
#define	CMP_SCR_CFF_SHIFT   (1U)
#define	CMP_SCR_CFF(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
#define	CMP_SCR_CFR_MASK   (0x4U)
#define	CMP_SCR_CFR_SHIFT   (2U)
#define	CMP_SCR_CFR(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
#define	CMP_SCR_IEF_MASK   (0x8U)
#define	CMP_SCR_IEF_SHIFT   (3U)
#define	CMP_SCR_IEF(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
#define	CMP_SCR_IER_MASK   (0x10U)
#define	CMP_SCR_IER_SHIFT   (4U)
#define	CMP_SCR_IER(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
#define	CMP_SCR_DMAEN_MASK   (0x40U)
#define	CMP_SCR_DMAEN_SHIFT   (6U)
#define	CMP_SCR_DMAEN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
#define	CMP_SCR_COUT_MASK   (0x1U)
#define	CMP_SCR_COUT_SHIFT   (0U)
#define	CMP_SCR_COUT(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
#define	CMP_SCR_CFF_MASK   (0x2U)
#define	CMP_SCR_CFF_SHIFT   (1U)
#define	CMP_SCR_CFF(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
#define	CMP_SCR_CFR_MASK   (0x4U)
#define	CMP_SCR_CFR_SHIFT   (2U)
#define	CMP_SCR_CFR(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
#define	CMP_SCR_IEF_MASK   (0x8U)
#define	CMP_SCR_IEF_SHIFT   (3U)
#define	CMP_SCR_IEF(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
#define	CMP_SCR_IER_MASK   (0x10U)
#define	CMP_SCR_IER_SHIFT   (4U)
#define	CMP_SCR_IER(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
#define	CMP_SCR_DMAEN_MASK   (0x40U)
#define	CMP_SCR_DMAEN_SHIFT   (6U)
#define	CMP_SCR_DMAEN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)

DACCR - DAC Control Register
#define	CMP_DACCR_VOSEL_MASK   (0x3FU)
#define	CMP_DACCR_VOSEL_SHIFT   (0U)
#define	CMP_DACCR_VOSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
#define	CMP_DACCR_VRSEL_MASK   (0x40U)
#define	CMP_DACCR_VRSEL_SHIFT   (6U)
#define	CMP_DACCR_VRSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
#define	CMP_DACCR_DACEN_MASK   (0x80U)
#define	CMP_DACCR_DACEN_SHIFT   (7U)
#define	CMP_DACCR_DACEN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
#define	CMP_DACCR_VOSEL_MASK   0x3Fu
#define	CMP_DACCR_VOSEL_SHIFT   0
#define	CMP_DACCR_VOSEL(x)   (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
#define	CMP_DACCR_VRSEL_MASK   0x40u
#define	CMP_DACCR_VRSEL_SHIFT   6
#define	CMP_DACCR_DACEN_MASK   0x80u
#define	CMP_DACCR_DACEN_SHIFT   7
#define	CMP_DACCR_VOSEL_MASK   (0x3FU)
#define	CMP_DACCR_VOSEL_SHIFT   (0U)
#define	CMP_DACCR_VOSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
#define	CMP_DACCR_VRSEL_MASK   (0x40U)
#define	CMP_DACCR_VRSEL_SHIFT   (6U)
#define	CMP_DACCR_VRSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
#define	CMP_DACCR_DACEN_MASK   (0x80U)
#define	CMP_DACCR_DACEN_SHIFT   (7U)
#define	CMP_DACCR_DACEN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
#define	CMP_DACCR_VOSEL_MASK   (0x3FU)
#define	CMP_DACCR_VOSEL_SHIFT   (0U)
#define	CMP_DACCR_VOSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
#define	CMP_DACCR_VRSEL_MASK   (0x40U)
#define	CMP_DACCR_VRSEL_SHIFT   (6U)
#define	CMP_DACCR_VRSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
#define	CMP_DACCR_DACEN_MASK   (0x80U)
#define	CMP_DACCR_DACEN_SHIFT   (7U)
#define	CMP_DACCR_DACEN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
#define	CMP_DACCR_VOSEL_MASK   (0x3FU)
#define	CMP_DACCR_VOSEL_SHIFT   (0U)
#define	CMP_DACCR_VOSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
#define	CMP_DACCR_VRSEL_MASK   (0x40U)
#define	CMP_DACCR_VRSEL_SHIFT   (6U)
#define	CMP_DACCR_VRSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
#define	CMP_DACCR_DACEN_MASK   (0x80U)
#define	CMP_DACCR_DACEN_SHIFT   (7U)
#define	CMP_DACCR_DACEN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
#define	CMP_DACCR_VOSEL_MASK   (0x3FU)
#define	CMP_DACCR_VOSEL_SHIFT   (0U)
#define	CMP_DACCR_VOSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
#define	CMP_DACCR_VRSEL_MASK   (0x40U)
#define	CMP_DACCR_VRSEL_SHIFT   (6U)
#define	CMP_DACCR_VRSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
#define	CMP_DACCR_DACEN_MASK   (0x80U)
#define	CMP_DACCR_DACEN_SHIFT   (7U)
#define	CMP_DACCR_DACEN(x)   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)

MUXCR - MUX Control Register
#define	CMP_MUXCR_MSEL_MASK   (0x7U)
#define	CMP_MUXCR_MSEL_SHIFT   (0U)
#define	CMP_MUXCR_MSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
#define	CMP_MUXCR_PSEL_MASK   (0x38U)
#define	CMP_MUXCR_PSEL_SHIFT   (3U)
#define	CMP_MUXCR_PSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
#define	CMP_MUXCR_MSEL_MASK   0x7u
#define	CMP_MUXCR_MSEL_SHIFT   0
#define	CMP_MUXCR_MSEL(x)   (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
#define	CMP_MUXCR_PSEL_MASK   0x38u
#define	CMP_MUXCR_PSEL_SHIFT   3
#define	CMP_MUXCR_PSEL(x)   (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
#define	CMP_MUXCR_MSEL_MASK   (0x7U)
#define	CMP_MUXCR_MSEL_SHIFT   (0U)
#define	CMP_MUXCR_MSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
#define	CMP_MUXCR_PSEL_MASK   (0x38U)
#define	CMP_MUXCR_PSEL_SHIFT   (3U)
#define	CMP_MUXCR_PSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
#define	CMP_MUXCR_MSEL_MASK   (0x7U)
#define	CMP_MUXCR_MSEL_SHIFT   (0U)
#define	CMP_MUXCR_MSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
#define	CMP_MUXCR_PSEL_MASK   (0x38U)
#define	CMP_MUXCR_PSEL_SHIFT   (3U)
#define	CMP_MUXCR_PSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
#define	CMP_MUXCR_MSEL_MASK   (0x7U)
#define	CMP_MUXCR_MSEL_SHIFT   (0U)
#define	CMP_MUXCR_MSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
#define	CMP_MUXCR_PSEL_MASK   (0x38U)
#define	CMP_MUXCR_PSEL_SHIFT   (3U)
#define	CMP_MUXCR_PSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
#define	CMP_MUXCR_MSEL_MASK   (0x7U)
#define	CMP_MUXCR_MSEL_SHIFT   (0U)
#define	CMP_MUXCR_MSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
#define	CMP_MUXCR_PSEL_MASK   (0x38U)
#define	CMP_MUXCR_PSEL_SHIFT   (3U)
#define	CMP_MUXCR_PSEL(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)

MUXCR - MUX Control Register
#define	CMP_MUXCR_PSTM_MASK   (0x40U)
#define	CMP_MUXCR_PSTM_SHIFT   (6U)
#define	CMP_MUXCR_PSTM(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
#define	CMP_MUXCR_PSTM_MASK   (0x80U)
#define	CMP_MUXCR_PSTM_SHIFT   (7U)
#define	CMP_MUXCR_PSTM(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
#define	CMP_MUXCR_PSTM_MASK   (0x80U)
#define	CMP_MUXCR_PSTM_SHIFT   (7U)
#define	CMP_MUXCR_PSTM(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
#define	CMP_MUXCR_PSTM_MASK   (0x80U)
#define	CMP_MUXCR_PSTM_SHIFT   (7U)
#define	CMP_MUXCR_PSTM(x)   (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)

Macro Definition Documentation

CMP0

#define CMP0   ((CMP_Type *)CMP0_BASE)

Peripheral CMP0 base pointer

CMP0_BASE

#define CMP0_BASE   (0x40073000u)

Peripheral CMP0 base address

CMP1

#define CMP1   ((CMP_Type *)CMP1_BASE)

Peripheral CMP1 base pointer

CMP1_BASE

#define CMP1_BASE   (0x40073008u)

Peripheral CMP1 base address

CMP2

#define CMP2   ((CMP_Type *)CMP2_BASE)

Peripheral CMP2 base pointer

CMP2_BASE

#define CMP2_BASE   (0x40073010u)

Peripheral CMP2 base address

CMP_BASE_ADDRS

#define CMP_BASE_ADDRS   { CMP0_BASE, CMP1_BASE, CMP2_BASE }

Array initializer of CMP peripheral base addresses

CMP_BASE_PTRS

#define CMP_BASE_PTRS   { CMP0, CMP1, CMP2 }

Array initializer of CMP peripheral base pointers

CMP_CR0_FILTER_CNT [1/6]

#define CMP_CR0_FILTER_CNT

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)

FILTER_CNT - Filter Sample Count 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. 0b001..One sample must agree. The comparator output is simply sampled. 0b010..2 consecutive samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5 consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.

CMP_CR0_FILTER_CNT [2/6]

#define CMP_CR0_FILTER_CNT

(

x

)

(((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)

FILTER_CNT - Filter Sample Count 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. 0b001..One sample must agree. The comparator output is simply sampled. 0b010..2 consecutive samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5 consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.

CMP_CR0_FILTER_CNT [3/6]

#define CMP_CR0_FILTER_CNT

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)

FILTER_CNT - Filter Sample Count 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. 0b001..One sample must agree. The comparator output is simply sampled. 0b010..2 consecutive samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5 consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.

CMP_CR0_FILTER_CNT [4/6]

#define CMP_CR0_FILTER_CNT

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)

FILTER_CNT - Filter Sample Count 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. 0b001..One sample must agree. The comparator output is simply sampled. 0b010..2 consecutive samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5 consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.

CMP_CR0_FILTER_CNT [5/6]

#define CMP_CR0_FILTER_CNT

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)

FILTER_CNT - Filter Sample Count 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. 0b001..One sample must agree. The comparator output is simply sampled. 0b010..2 consecutive samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5 consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.

CMP_CR0_FILTER_CNT [6/6]

#define CMP_CR0_FILTER_CNT

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)

FILTER_CNT - Filter Sample Count 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. 0b001..One sample must agree. The comparator output is simply sampled. 0b010..2 consecutive samples must agree. 0b011..3 consecutive samples must agree. 0b100..4 consecutive samples must agree. 0b101..5 consecutive samples must agree. 0b110..6 consecutive samples must agree. 0b111..7 consecutive samples must agree.

CMP_CR0_HYSTCTR [1/6]

#define CMP_CR0_HYSTCTR

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)

HYSTCTR - Comparator hard block hysteresis control 0b00..Level 0 0b01..Level 1 0b10..Level 2 0b11..Level 3

CMP_CR0_HYSTCTR [2/6]

#define CMP_CR0_HYSTCTR

(

x

)

(((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)

HYSTCTR - Comparator hard block hysteresis control 0b00..Level 0 0b01..Level 1 0b10..Level 2 0b11..Level 3

CMP_CR0_HYSTCTR [3/6]

#define CMP_CR0_HYSTCTR

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)

HYSTCTR - Comparator hard block hysteresis control 0b00..Level 0 0b01..Level 1 0b10..Level 2 0b11..Level 3

CMP_CR0_HYSTCTR [4/6]

#define CMP_CR0_HYSTCTR

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)

HYSTCTR - Comparator hard block hysteresis control 0b00..Level 0 0b01..Level 1 0b10..Level 2 0b11..Level 3

CMP_CR0_HYSTCTR [5/6]

#define CMP_CR0_HYSTCTR

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)

HYSTCTR - Comparator hard block hysteresis control 0b00..Level 0 0b01..Level 1 0b10..Level 2 0b11..Level 3

CMP_CR0_HYSTCTR [6/6]

#define CMP_CR0_HYSTCTR

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)

HYSTCTR - Comparator hard block hysteresis control 0b00..Level 0 0b01..Level 1 0b10..Level 2 0b11..Level 3

CMP_CR1_COS [1/5]

#define CMP_CR1_COS

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)

COS - Comparator Output Select 0b0..Set the filtered comparator output (CMPO) to equal COUT. 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.

CMP_CR1_COS [2/5]

#define CMP_CR1_COS

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)

COS - Comparator Output Select 0b0..Set the filtered comparator output (CMPO) to equal COUT. 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.

CMP_CR1_COS [3/5]

#define CMP_CR1_COS

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)

COS - Comparator Output Select 0b0..Set the filtered comparator output (CMPO) to equal COUT. 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.

CMP_CR1_COS [4/5]

#define CMP_CR1_COS

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)

COS - Comparator Output Select 0b0..Set the filtered comparator output (CMPO) to equal COUT. 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.

CMP_CR1_COS [5/5]

#define CMP_CR1_COS

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)

COS - Comparator Output Select 0b0..Set the filtered comparator output (CMPO) to equal COUT. 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.

CMP_CR1_EN [1/5]

#define CMP_CR1_EN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)

EN - Comparator Module Enable 0b0..Analog Comparator is disabled. 0b1..Analog Comparator is enabled.

CMP_CR1_EN [2/5]

#define CMP_CR1_EN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)

EN - Comparator Module Enable 0b0..Analog Comparator is disabled. 0b1..Analog Comparator is enabled.

CMP_CR1_EN [3/5]

#define CMP_CR1_EN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)

EN - Comparator Module Enable 0b0..Analog Comparator is disabled. 0b1..Analog Comparator is enabled.

CMP_CR1_EN [4/5]

#define CMP_CR1_EN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)

EN - Comparator Module Enable 0b0..Analog Comparator is disabled. 0b1..Analog Comparator is enabled.

CMP_CR1_EN [5/5]

#define CMP_CR1_EN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)

EN - Comparator Module Enable 0b0..Analog Comparator is disabled. 0b1..Analog Comparator is enabled.

CMP_CR1_INV [1/5]

#define CMP_CR1_INV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)

INV - Comparator INVERT 0b0..Does not invert the comparator output. 0b1..Inverts the comparator output.

CMP_CR1_INV [2/5]

#define CMP_CR1_INV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)

INV - Comparator INVERT 0b0..Does not invert the comparator output. 0b1..Inverts the comparator output.

CMP_CR1_INV [3/5]

#define CMP_CR1_INV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)

INV - Comparator INVERT 0b0..Does not invert the comparator output. 0b1..Inverts the comparator output.

CMP_CR1_INV [4/5]

#define CMP_CR1_INV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)

INV - Comparator INVERT 0b0..Does not invert the comparator output. 0b1..Inverts the comparator output.

CMP_CR1_INV [5/5]

#define CMP_CR1_INV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)

INV - Comparator INVERT 0b0..Does not invert the comparator output. 0b1..Inverts the comparator output.

CMP_CR1_OPE [1/5]

#define CMP_CR1_OPE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)

OPE - Comparator Output Pin Enable 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.

CMP_CR1_OPE [2/5]

#define CMP_CR1_OPE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)

OPE - Comparator Output Pin Enable 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.

CMP_CR1_OPE [3/5]

#define CMP_CR1_OPE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)

OPE - Comparator Output Pin Enable 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.

CMP_CR1_OPE [4/5]

#define CMP_CR1_OPE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)

OPE - Comparator Output Pin Enable 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.

CMP_CR1_OPE [5/5]

#define CMP_CR1_OPE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)

OPE - Comparator Output Pin Enable 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.

CMP_CR1_PMODE [1/5]

#define CMP_CR1_PMODE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)

PMODE - Power Mode Select 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.

CMP_CR1_PMODE [2/5]

#define CMP_CR1_PMODE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)

PMODE - Power Mode Select 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.

CMP_CR1_PMODE [3/5]

#define CMP_CR1_PMODE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)

PMODE - Power Mode Select 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.

CMP_CR1_PMODE [4/5]

#define CMP_CR1_PMODE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)

PMODE - Power Mode Select 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.

CMP_CR1_PMODE [5/5]

#define CMP_CR1_PMODE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)

PMODE - Power Mode Select 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.

CMP_CR1_SE [1/5]

#define CMP_CR1_SE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)

SE - Sample Enable 0b0..Sampling mode is not selected. 0b1..Sampling mode is selected.

CMP_CR1_SE [2/5]

#define CMP_CR1_SE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)

SE - Sample Enable 0b0..Sampling mode is not selected. 0b1..Sampling mode is selected.

CMP_CR1_SE [3/5]

#define CMP_CR1_SE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)

SE - Sample Enable 0b0..Sampling mode is not selected. 0b1..Sampling mode is selected.

CMP_CR1_SE [4/5]

#define CMP_CR1_SE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)

SE - Sample Enable 0b0..Sampling mode is not selected. 0b1..Sampling mode is selected.

CMP_CR1_SE [5/5]

#define CMP_CR1_SE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)

SE - Sample Enable 0b0..Sampling mode is not selected. 0b1..Sampling mode is selected.

CMP_CR1_TRIGM [1/3]

#define CMP_CR1_TRIGM

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)

TRIGM - Trigger Mode Enable 0b0..Trigger mode is disabled. 0b1..Trigger mode is enabled.

CMP_CR1_TRIGM [2/3]

#define CMP_CR1_TRIGM

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)

TRIGM - Trigger Mode Enable 0b0..Trigger mode is disabled. 0b1..Trigger mode is enabled.

CMP_CR1_TRIGM [3/3]

#define CMP_CR1_TRIGM

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)

TRIGM - Trigger Mode Enable 0b0..Trigger mode is disabled. 0b1..Trigger mode is enabled.

CMP_CR1_WE [1/5]

#define CMP_CR1_WE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)

WE - Windowing Enable 0b0..Windowing mode is not selected. 0b1..Windowing mode is selected.

CMP_CR1_WE [2/5]

#define CMP_CR1_WE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)

WE - Windowing Enable 0b0..Windowing mode is not selected. 0b1..Windowing mode is selected.

CMP_CR1_WE [3/5]

#define CMP_CR1_WE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)

WE - Windowing Enable 0b0..Windowing mode is not selected. 0b1..Windowing mode is selected.

CMP_CR1_WE [4/5]

#define CMP_CR1_WE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)

WE - Windowing Enable 0b0..Windowing mode is not selected. 0b1..Windowing mode is selected.

CMP_CR1_WE [5/5]

#define CMP_CR1_WE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)

WE - Windowing Enable 0b0..Windowing mode is not selected. 0b1..Windowing mode is selected.

CMP_DACCR_DACEN [1/5]

#define CMP_DACCR_DACEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)

DACEN - DAC Enable 0b0..DAC is disabled. 0b1..DAC is enabled.

CMP_DACCR_DACEN [2/5]

#define CMP_DACCR_DACEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)

DACEN - DAC Enable 0b0..DAC is disabled. 0b1..DAC is enabled.

CMP_DACCR_DACEN [3/5]

#define CMP_DACCR_DACEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)

DACEN - DAC Enable 0b0..DAC is disabled. 0b1..DAC is enabled.

CMP_DACCR_DACEN [4/5]

#define CMP_DACCR_DACEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)

DACEN - DAC Enable 0b0..DAC is disabled. 0b1..DAC is enabled.

CMP_DACCR_DACEN [5/5]

#define CMP_DACCR_DACEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)

DACEN - DAC Enable 0b0..DAC is disabled. 0b1..DAC is enabled.

CMP_DACCR_VRSEL [1/5]

#define CMP_DACCR_VRSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)

VRSEL - Supply Voltage Reference Source Select 0b0..V is selected as resistor ladder network supply reference V. in1 in 0b1..V is selected as resistor ladder network supply reference V. in2 in

VRSEL - Supply Voltage Reference Source Select 0b0..Vin1 is selected as resistor ladder network supply reference. 0b1..Vin2 is selected as resistor ladder network supply reference.

CMP_DACCR_VRSEL [2/5]

#define CMP_DACCR_VRSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)

VRSEL - Supply Voltage Reference Source Select 0b0..V is selected as resistor ladder network supply reference V. in1 in 0b1..V is selected as resistor ladder network supply reference V. in2 in

VRSEL - Supply Voltage Reference Source Select 0b0..Vin1 is selected as resistor ladder network supply reference. 0b1..Vin2 is selected as resistor ladder network supply reference.

CMP_DACCR_VRSEL [3/5]

#define CMP_DACCR_VRSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)

VRSEL - Supply Voltage Reference Source Select 0b0..Vin1 is selected as resistor ladder network supply reference. 0b1..Vin2 is selected as resistor ladder network supply reference.

CMP_DACCR_VRSEL [4/5]

#define CMP_DACCR_VRSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)

VRSEL - Supply Voltage Reference Source Select 0b0..Vin1 is selected as resistor ladder network supply reference. 0b1..Vin2 is selected as resistor ladder network supply reference.

CMP_DACCR_VRSEL [5/5]

#define CMP_DACCR_VRSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)

VRSEL - Supply Voltage Reference Source Select 0b0..Vin1 is selected as resistor ladder network supply reference. 0b1..Vin2 is selected as resistor ladder network supply reference.

CMP_IRQS

#define CMP_IRQS   { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }

Interrupt vectors for the CMP peripheral type

CMP_MUXCR_MSEL [1/6]

#define CMP_MUXCR_MSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)

MSEL - Minus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_MSEL [2/6]

#define CMP_MUXCR_MSEL

(

x

)

(((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)

MSEL - Minus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_MSEL [3/6]

#define CMP_MUXCR_MSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)

MSEL - Minus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_MSEL [4/6]

#define CMP_MUXCR_MSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)

MSEL - Minus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_MSEL [5/6]

#define CMP_MUXCR_MSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)

MSEL - Minus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_MSEL [6/6]

#define CMP_MUXCR_MSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)

MSEL - Minus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_PSEL [1/6]

#define CMP_MUXCR_PSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)

PSEL - Plus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_PSEL [2/6]

#define CMP_MUXCR_PSEL

(

x

)

(((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)

PSEL - Plus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_PSEL [3/6]

#define CMP_MUXCR_PSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)

PSEL - Plus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_PSEL [4/6]

#define CMP_MUXCR_PSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)

PSEL - Plus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_PSEL [5/6]

#define CMP_MUXCR_PSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)

PSEL - Plus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_PSEL [6/6]

#define CMP_MUXCR_PSEL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)

PSEL - Plus Input Mux Control 0b000..IN0 0b001..IN1 0b010..IN2 0b011..IN3 0b100..IN4 0b101..IN5 0b110..IN6 0b111..IN7

CMP_MUXCR_PSTM [1/4]

#define CMP_MUXCR_PSTM

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)

PSTM - Pass Through Mode Enable 0b0..Pass Through Mode is disabled. 0b1..Pass Through Mode is enabled.

CMP_MUXCR_PSTM [2/4]

#define CMP_MUXCR_PSTM

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)

PSTM - Pass Through Mode Enable 0b0..Pass Through Mode is disabled. 0b1..Pass Through Mode is enabled.

CMP_MUXCR_PSTM [3/4]

#define CMP_MUXCR_PSTM

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)

PSTM - Pass Through Mode Enable 0b0..Pass Through Mode is disabled. 0b1..Pass Through Mode is enabled.

CMP_MUXCR_PSTM [4/4]

#define CMP_MUXCR_PSTM

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)

PSTM - Pass Through Mode Enable 0b0..Pass Through Mode is disabled. 0b1..Pass Through Mode is enabled.

CMP_SCR_CFF [1/5]

#define CMP_SCR_CFF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)

CFF - Analog Comparator Flag Falling 0b0..Falling-edge on COUT has not been detected. 0b1..Falling-edge on COUT has occurred.

CMP_SCR_CFF [2/5]

#define CMP_SCR_CFF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)

CFF - Analog Comparator Flag Falling 0b0..Falling-edge on COUT has not been detected. 0b1..Falling-edge on COUT has occurred.

CMP_SCR_CFF [3/5]

#define CMP_SCR_CFF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)

CFF - Analog Comparator Flag Falling 0b0..Falling-edge on COUT has not been detected. 0b1..Falling-edge on COUT has occurred.

CMP_SCR_CFF [4/5]

#define CMP_SCR_CFF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)

CFF - Analog Comparator Flag Falling 0b0..Falling-edge on COUT has not been detected. 0b1..Falling-edge on COUT has occurred.

CMP_SCR_CFF [5/5]

#define CMP_SCR_CFF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)

CFF - Analog Comparator Flag Falling 0b0..Falling-edge on COUT has not been detected. 0b1..Falling-edge on COUT has occurred.

CMP_SCR_CFR [1/5]

#define CMP_SCR_CFR

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)

CFR - Analog Comparator Flag Rising 0b0..Rising-edge on COUT has not been detected. 0b1..Rising-edge on COUT has occurred.

CMP_SCR_CFR [2/5]

#define CMP_SCR_CFR

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)

CFR - Analog Comparator Flag Rising 0b0..Rising-edge on COUT has not been detected. 0b1..Rising-edge on COUT has occurred.

CMP_SCR_CFR [3/5]

#define CMP_SCR_CFR

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)

CFR - Analog Comparator Flag Rising 0b0..Rising-edge on COUT has not been detected. 0b1..Rising-edge on COUT has occurred.

CMP_SCR_CFR [4/5]

#define CMP_SCR_CFR

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)

CFR - Analog Comparator Flag Rising 0b0..Rising-edge on COUT has not been detected. 0b1..Rising-edge on COUT has occurred.

CMP_SCR_CFR [5/5]

#define CMP_SCR_CFR

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)

CFR - Analog Comparator Flag Rising 0b0..Rising-edge on COUT has not been detected. 0b1..Rising-edge on COUT has occurred.

CMP_SCR_DMAEN [1/5]

#define CMP_SCR_DMAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)

DMAEN - DMA Enable Control 0b0..DMA is disabled. 0b1..DMA is enabled.

CMP_SCR_DMAEN [2/5]

#define CMP_SCR_DMAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)

DMAEN - DMA Enable Control 0b0..DMA is disabled. 0b1..DMA is enabled.

CMP_SCR_DMAEN [3/5]

#define CMP_SCR_DMAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)

DMAEN - DMA Enable Control 0b0..DMA is disabled. 0b1..DMA is enabled.

CMP_SCR_DMAEN [4/5]

#define CMP_SCR_DMAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)

DMAEN - DMA Enable Control 0b0..DMA is disabled. 0b1..DMA is enabled.

CMP_SCR_DMAEN [5/5]

#define CMP_SCR_DMAEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)

DMAEN - DMA Enable Control 0b0..DMA is disabled. 0b1..DMA is enabled.

CMP_SCR_IEF [1/5]

#define CMP_SCR_IEF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)

IEF - Comparator Interrupt Enable Falling 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

CMP_SCR_IEF [2/5]

#define CMP_SCR_IEF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)

IEF - Comparator Interrupt Enable Falling 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

CMP_SCR_IEF [3/5]

#define CMP_SCR_IEF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)

IEF - Comparator Interrupt Enable Falling 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

CMP_SCR_IEF [4/5]

#define CMP_SCR_IEF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)

IEF - Comparator Interrupt Enable Falling 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

CMP_SCR_IEF [5/5]

#define CMP_SCR_IEF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)

IEF - Comparator Interrupt Enable Falling 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

CMP_SCR_IER [1/5]

#define CMP_SCR_IER

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)

IER - Comparator Interrupt Enable Rising 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

CMP_SCR_IER [2/5]

#define CMP_SCR_IER

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)

IER - Comparator Interrupt Enable Rising 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

CMP_SCR_IER [3/5]

#define CMP_SCR_IER

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)

IER - Comparator Interrupt Enable Rising 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

CMP_SCR_IER [4/5]

#define CMP_SCR_IER

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)

IER - Comparator Interrupt Enable Rising 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.

CMP_SCR_IER [5/5]

#define CMP_SCR_IER

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)

IER - Comparator Interrupt Enable Rising 0b0..Interrupt is disabled. 0b1..Interrupt is enabled.