CMT Register Masks

Macros
#define	CMT_BASE   (0x40062000u)
#define	CMT   ((CMT_Type *)CMT_BASE)
#define	CMT_BASE_ADDRS   { CMT_BASE }
#define	CMT_BASE_PTRS   { CMT }
#define	CMT_IRQS   { CMT_IRQn }

CGH1 - CMT Carrier Generator High Data Register 1
#define	CMT_CGH1_PH_MASK   (0xFFU)
#define	CMT_CGH1_PH_SHIFT   (0U)
#define	CMT_CGH1_PH(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
#define	CMT_CGH1_PH_MASK   0xFFu
#define	CMT_CGH1_PH_SHIFT   0
#define	CMT_CGH1_PH(x)   (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
#define	CMT_CGH1_PH_MASK   (0xFFU)
#define	CMT_CGH1_PH_SHIFT   (0U)
#define	CMT_CGH1_PH(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
#define	CMT_CGH1_PH_MASK   (0xFFU)
#define	CMT_CGH1_PH_SHIFT   (0U)
#define	CMT_CGH1_PH(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
#define	CMT_CGH1_PH_MASK   (0xFFU)
#define	CMT_CGH1_PH_SHIFT   (0U)
#define	CMT_CGH1_PH(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)

CGL1 - CMT Carrier Generator Low Data Register 1
#define	CMT_CGL1_PL_MASK   (0xFFU)
#define	CMT_CGL1_PL_SHIFT   (0U)
#define	CMT_CGL1_PL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
#define	CMT_CGL1_PL_MASK   0xFFu
#define	CMT_CGL1_PL_SHIFT   0
#define	CMT_CGL1_PL(x)   (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
#define	CMT_CGL1_PL_MASK   (0xFFU)
#define	CMT_CGL1_PL_SHIFT   (0U)
#define	CMT_CGL1_PL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
#define	CMT_CGL1_PL_MASK   (0xFFU)
#define	CMT_CGL1_PL_SHIFT   (0U)
#define	CMT_CGL1_PL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
#define	CMT_CGL1_PL_MASK   (0xFFU)
#define	CMT_CGL1_PL_SHIFT   (0U)
#define	CMT_CGL1_PL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)

CGH2 - CMT Carrier Generator High Data Register 2
#define	CMT_CGH2_SH_MASK   (0xFFU)
#define	CMT_CGH2_SH_SHIFT   (0U)
#define	CMT_CGH2_SH(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
#define	CMT_CGH2_SH_MASK   0xFFu
#define	CMT_CGH2_SH_SHIFT   0
#define	CMT_CGH2_SH(x)   (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
#define	CMT_CGH2_SH_MASK   (0xFFU)
#define	CMT_CGH2_SH_SHIFT   (0U)
#define	CMT_CGH2_SH(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
#define	CMT_CGH2_SH_MASK   (0xFFU)
#define	CMT_CGH2_SH_SHIFT   (0U)
#define	CMT_CGH2_SH(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
#define	CMT_CGH2_SH_MASK   (0xFFU)
#define	CMT_CGH2_SH_SHIFT   (0U)
#define	CMT_CGH2_SH(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)

CGL2 - CMT Carrier Generator Low Data Register 2
#define	CMT_CGL2_SL_MASK   (0xFFU)
#define	CMT_CGL2_SL_SHIFT   (0U)
#define	CMT_CGL2_SL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
#define	CMT_CGL2_SL_MASK   0xFFu
#define	CMT_CGL2_SL_SHIFT   0
#define	CMT_CGL2_SL(x)   (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
#define	CMT_CGL2_SL_MASK   (0xFFU)
#define	CMT_CGL2_SL_SHIFT   (0U)
#define	CMT_CGL2_SL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
#define	CMT_CGL2_SL_MASK   (0xFFU)
#define	CMT_CGL2_SL_SHIFT   (0U)
#define	CMT_CGL2_SL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
#define	CMT_CGL2_SL_MASK   (0xFFU)
#define	CMT_CGL2_SL_SHIFT   (0U)
#define	CMT_CGL2_SL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)

OC - CMT Output Control Register
#define	CMT_OC_IROPEN_MASK   (0x20U)
#define	CMT_OC_IROPEN_SHIFT   (5U)
#define	CMT_OC_IROPEN(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
#define	CMT_OC_CMTPOL_MASK   (0x40U)
#define	CMT_OC_CMTPOL_SHIFT   (6U)
#define	CMT_OC_CMTPOL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
#define	CMT_OC_IROL_MASK   (0x80U)
#define	CMT_OC_IROL_SHIFT   (7U)
#define	CMT_OC_IROL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
#define	CMT_OC_IROPEN_MASK   0x20u
#define	CMT_OC_IROPEN_SHIFT   5
#define	CMT_OC_CMTPOL_MASK   0x40u
#define	CMT_OC_CMTPOL_SHIFT   6
#define	CMT_OC_IROL_MASK   0x80u
#define	CMT_OC_IROL_SHIFT   7
#define	CMT_OC_IROPEN_MASK   (0x20U)
#define	CMT_OC_IROPEN_SHIFT   (5U)
#define	CMT_OC_IROPEN(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
#define	CMT_OC_CMTPOL_MASK   (0x40U)
#define	CMT_OC_CMTPOL_SHIFT   (6U)
#define	CMT_OC_CMTPOL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
#define	CMT_OC_IROL_MASK   (0x80U)
#define	CMT_OC_IROL_SHIFT   (7U)
#define	CMT_OC_IROL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
#define	CMT_OC_IROPEN_MASK   (0x20U)
#define	CMT_OC_IROPEN_SHIFT   (5U)
#define	CMT_OC_IROPEN(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
#define	CMT_OC_CMTPOL_MASK   (0x40U)
#define	CMT_OC_CMTPOL_SHIFT   (6U)
#define	CMT_OC_CMTPOL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
#define	CMT_OC_IROL_MASK   (0x80U)
#define	CMT_OC_IROL_SHIFT   (7U)
#define	CMT_OC_IROL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
#define	CMT_OC_IROPEN_MASK   (0x20U)
#define	CMT_OC_IROPEN_SHIFT   (5U)
#define	CMT_OC_IROPEN(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
#define	CMT_OC_CMTPOL_MASK   (0x40U)
#define	CMT_OC_CMTPOL_SHIFT   (6U)
#define	CMT_OC_CMTPOL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
#define	CMT_OC_IROL_MASK   (0x80U)
#define	CMT_OC_IROL_SHIFT   (7U)
#define	CMT_OC_IROL(x)   (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)

MSC - CMT Modulator Status and Control Register
#define	CMT_MSC_MCGEN_MASK   (0x1U)
#define	CMT_MSC_MCGEN_SHIFT   (0U)
#define	CMT_MSC_MCGEN(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
#define	CMT_MSC_EOCIE_MASK   (0x2U)
#define	CMT_MSC_EOCIE_SHIFT   (1U)
#define	CMT_MSC_EOCIE(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
#define	CMT_MSC_FSK_MASK   (0x4U)
#define	CMT_MSC_FSK_SHIFT   (2U)
#define	CMT_MSC_FSK(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
#define	CMT_MSC_BASE_MASK   (0x8U)
#define	CMT_MSC_BASE_SHIFT   (3U)
#define	CMT_MSC_BASE(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
#define	CMT_MSC_EXSPC_MASK   (0x10U)
#define	CMT_MSC_EXSPC_SHIFT   (4U)
#define	CMT_MSC_EXSPC(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
#define	CMT_MSC_CMTDIV_MASK   (0x60U)
#define	CMT_MSC_CMTDIV_SHIFT   (5U)
#define	CMT_MSC_CMTDIV(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
#define	CMT_MSC_EOCF_MASK   (0x80U)
#define	CMT_MSC_EOCF_SHIFT   (7U)
#define	CMT_MSC_EOCF(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
#define	CMT_MSC_MCGEN_MASK   0x1u
#define	CMT_MSC_MCGEN_SHIFT   0
#define	CMT_MSC_EOCIE_MASK   0x2u
#define	CMT_MSC_EOCIE_SHIFT   1
#define	CMT_MSC_FSK_MASK   0x4u
#define	CMT_MSC_FSK_SHIFT   2
#define	CMT_MSC_BASE_MASK   0x8u
#define	CMT_MSC_BASE_SHIFT   3
#define	CMT_MSC_EXSPC_MASK   0x10u
#define	CMT_MSC_EXSPC_SHIFT   4
#define	CMT_MSC_CMTDIV_MASK   0x60u
#define	CMT_MSC_CMTDIV_SHIFT   5
#define	CMT_MSC_CMTDIV(x)   (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
#define	CMT_MSC_EOCF_MASK   0x80u
#define	CMT_MSC_EOCF_SHIFT   7
#define	CMT_MSC_MCGEN_MASK   (0x1U)
#define	CMT_MSC_MCGEN_SHIFT   (0U)
#define	CMT_MSC_MCGEN(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
#define	CMT_MSC_EOCIE_MASK   (0x2U)
#define	CMT_MSC_EOCIE_SHIFT   (1U)
#define	CMT_MSC_EOCIE(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
#define	CMT_MSC_FSK_MASK   (0x4U)
#define	CMT_MSC_FSK_SHIFT   (2U)
#define	CMT_MSC_FSK(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
#define	CMT_MSC_BASE_MASK   (0x8U)
#define	CMT_MSC_BASE_SHIFT   (3U)
#define	CMT_MSC_BASE(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
#define	CMT_MSC_EXSPC_MASK   (0x10U)
#define	CMT_MSC_EXSPC_SHIFT   (4U)
#define	CMT_MSC_EXSPC(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
#define	CMT_MSC_CMTDIV_MASK   (0x60U)
#define	CMT_MSC_CMTDIV_SHIFT   (5U)
#define	CMT_MSC_CMTDIV(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
#define	CMT_MSC_EOCF_MASK   (0x80U)
#define	CMT_MSC_EOCF_SHIFT   (7U)
#define	CMT_MSC_EOCF(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
#define	CMT_MSC_MCGEN_MASK   (0x1U)
#define	CMT_MSC_MCGEN_SHIFT   (0U)
#define	CMT_MSC_MCGEN(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
#define	CMT_MSC_EOCIE_MASK   (0x2U)
#define	CMT_MSC_EOCIE_SHIFT   (1U)
#define	CMT_MSC_EOCIE(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
#define	CMT_MSC_FSK_MASK   (0x4U)
#define	CMT_MSC_FSK_SHIFT   (2U)
#define	CMT_MSC_FSK(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
#define	CMT_MSC_BASE_MASK   (0x8U)
#define	CMT_MSC_BASE_SHIFT   (3U)
#define	CMT_MSC_BASE(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
#define	CMT_MSC_EXSPC_MASK   (0x10U)
#define	CMT_MSC_EXSPC_SHIFT   (4U)
#define	CMT_MSC_EXSPC(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
#define	CMT_MSC_CMTDIV_MASK   (0x60U)
#define	CMT_MSC_CMTDIV_SHIFT   (5U)
#define	CMT_MSC_CMTDIV(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
#define	CMT_MSC_EOCF_MASK   (0x80U)
#define	CMT_MSC_EOCF_SHIFT   (7U)
#define	CMT_MSC_EOCF(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
#define	CMT_MSC_MCGEN_MASK   (0x1U)
#define	CMT_MSC_MCGEN_SHIFT   (0U)
#define	CMT_MSC_MCGEN(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
#define	CMT_MSC_EOCIE_MASK   (0x2U)
#define	CMT_MSC_EOCIE_SHIFT   (1U)
#define	CMT_MSC_EOCIE(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
#define	CMT_MSC_FSK_MASK   (0x4U)
#define	CMT_MSC_FSK_SHIFT   (2U)
#define	CMT_MSC_FSK(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
#define	CMT_MSC_BASE_MASK   (0x8U)
#define	CMT_MSC_BASE_SHIFT   (3U)
#define	CMT_MSC_BASE(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
#define	CMT_MSC_EXSPC_MASK   (0x10U)
#define	CMT_MSC_EXSPC_SHIFT   (4U)
#define	CMT_MSC_EXSPC(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
#define	CMT_MSC_CMTDIV_MASK   (0x60U)
#define	CMT_MSC_CMTDIV_SHIFT   (5U)
#define	CMT_MSC_CMTDIV(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
#define	CMT_MSC_EOCF_MASK   (0x80U)
#define	CMT_MSC_EOCF_SHIFT   (7U)
#define	CMT_MSC_EOCF(x)   (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)

CMD1 - CMT Modulator Data Register Mark High
#define	CMT_CMD1_MB_MASK   (0xFFU)
#define	CMT_CMD1_MB_SHIFT   (0U)
#define	CMT_CMD1_MB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
#define	CMT_CMD1_MB_MASK   0xFFu
#define	CMT_CMD1_MB_SHIFT   0
#define	CMT_CMD1_MB(x)   (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
#define	CMT_CMD1_MB_MASK   (0xFFU)
#define	CMT_CMD1_MB_SHIFT   (0U)
#define	CMT_CMD1_MB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
#define	CMT_CMD1_MB_MASK   (0xFFU)
#define	CMT_CMD1_MB_SHIFT   (0U)
#define	CMT_CMD1_MB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
#define	CMT_CMD1_MB_MASK   (0xFFU)
#define	CMT_CMD1_MB_SHIFT   (0U)
#define	CMT_CMD1_MB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)

CMD2 - CMT Modulator Data Register Mark Low
#define	CMT_CMD2_MB_MASK   (0xFFU)
#define	CMT_CMD2_MB_SHIFT   (0U)
#define	CMT_CMD2_MB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
#define	CMT_CMD2_MB_MASK   0xFFu
#define	CMT_CMD2_MB_SHIFT   0
#define	CMT_CMD2_MB(x)   (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
#define	CMT_CMD2_MB_MASK   (0xFFU)
#define	CMT_CMD2_MB_SHIFT   (0U)
#define	CMT_CMD2_MB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
#define	CMT_CMD2_MB_MASK   (0xFFU)
#define	CMT_CMD2_MB_SHIFT   (0U)
#define	CMT_CMD2_MB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
#define	CMT_CMD2_MB_MASK   (0xFFU)
#define	CMT_CMD2_MB_SHIFT   (0U)
#define	CMT_CMD2_MB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)

CMD3 - CMT Modulator Data Register Space High
#define	CMT_CMD3_SB_MASK   (0xFFU)
#define	CMT_CMD3_SB_SHIFT   (0U)
#define	CMT_CMD3_SB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
#define	CMT_CMD3_SB_MASK   0xFFu
#define	CMT_CMD3_SB_SHIFT   0
#define	CMT_CMD3_SB(x)   (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
#define	CMT_CMD3_SB_MASK   (0xFFU)
#define	CMT_CMD3_SB_SHIFT   (0U)
#define	CMT_CMD3_SB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
#define	CMT_CMD3_SB_MASK   (0xFFU)
#define	CMT_CMD3_SB_SHIFT   (0U)
#define	CMT_CMD3_SB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
#define	CMT_CMD3_SB_MASK   (0xFFU)
#define	CMT_CMD3_SB_SHIFT   (0U)
#define	CMT_CMD3_SB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)

CMD4 - CMT Modulator Data Register Space Low
#define	CMT_CMD4_SB_MASK   (0xFFU)
#define	CMT_CMD4_SB_SHIFT   (0U)
#define	CMT_CMD4_SB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
#define	CMT_CMD4_SB_MASK   0xFFu
#define	CMT_CMD4_SB_SHIFT   0
#define	CMT_CMD4_SB(x)   (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
#define	CMT_CMD4_SB_MASK   (0xFFU)
#define	CMT_CMD4_SB_SHIFT   (0U)
#define	CMT_CMD4_SB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
#define	CMT_CMD4_SB_MASK   (0xFFU)
#define	CMT_CMD4_SB_SHIFT   (0U)
#define	CMT_CMD4_SB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
#define	CMT_CMD4_SB_MASK   (0xFFU)
#define	CMT_CMD4_SB_SHIFT   (0U)
#define	CMT_CMD4_SB(x)   (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)

PPS - CMT Primary Prescaler Register
#define	CMT_PPS_PPSDIV_MASK   (0xFU)
#define	CMT_PPS_PPSDIV_SHIFT   (0U)
#define	CMT_PPS_PPSDIV(x)   (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
#define	CMT_PPS_PPSDIV_MASK   0xFu
#define	CMT_PPS_PPSDIV_SHIFT   0
#define	CMT_PPS_PPSDIV(x)   (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
#define	CMT_PPS_PPSDIV_MASK   (0xFU)
#define	CMT_PPS_PPSDIV_SHIFT   (0U)
#define	CMT_PPS_PPSDIV(x)   (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
#define	CMT_PPS_PPSDIV_MASK   (0xFU)
#define	CMT_PPS_PPSDIV_SHIFT   (0U)
#define	CMT_PPS_PPSDIV(x)   (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
#define	CMT_PPS_PPSDIV_MASK   (0xFU)
#define	CMT_PPS_PPSDIV_SHIFT   (0U)
#define	CMT_PPS_PPSDIV(x)   (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)

DMA - CMT Direct Memory Access Register
#define	CMT_DMA_DMA_MASK   (0x1U)
#define	CMT_DMA_DMA_SHIFT   (0U)
#define	CMT_DMA_DMA(x)   (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
#define	CMT_DMA_DMA_MASK   0x1u
#define	CMT_DMA_DMA_SHIFT   0
#define	CMT_DMA_DMA_MASK   (0x1U)
#define	CMT_DMA_DMA_SHIFT   (0U)
#define	CMT_DMA_DMA(x)   (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
#define	CMT_DMA_DMA_MASK   (0x1U)
#define	CMT_DMA_DMA_SHIFT   (0U)
#define	CMT_DMA_DMA(x)   (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
#define	CMT_DMA_DMA_MASK   (0x1U)
#define	CMT_DMA_DMA_SHIFT   (0U)
#define	CMT_DMA_DMA(x)   (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)

Macro Definition Documentation

CMT

#define CMT   ((CMT_Type *)CMT_BASE)

Peripheral CMT base pointer

CMT_BASE

#define CMT_BASE   (0x40062000u)

Peripheral CMT base address

CMT_BASE_ADDRS

#define CMT_BASE_ADDRS   { CMT_BASE }

Array initializer of CMT peripheral base addresses

CMT_BASE_PTRS

#define CMT_BASE_PTRS   { CMT }

Array initializer of CMT peripheral base pointers

CMT_DMA_DMA [1/4]

#define CMT_DMA_DMA

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)

DMA - DMA Enable 0b0..DMA transfer request and done are disabled. 0b1..DMA transfer request and done are enabled.

CMT_DMA_DMA [2/4]

#define CMT_DMA_DMA

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)

DMA - DMA Enable 0b0..DMA transfer request and done are disabled. 0b1..DMA transfer request and done are enabled.

CMT_DMA_DMA [3/4]

#define CMT_DMA_DMA

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)

DMA - DMA Enable 0b0..DMA transfer request and done are disabled. 0b1..DMA transfer request and done are enabled.

CMT_DMA_DMA [4/4]

#define CMT_DMA_DMA

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)

DMA - DMA Enable 0b0..DMA transfer request and done are disabled. 0b1..DMA transfer request and done are enabled.

CMT_IRQS

#define CMT_IRQS   { CMT_IRQn }

Interrupt vectors for the CMT peripheral type

CMT_MSC_BASE [1/4]

#define CMT_MSC_BASE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)

BASE - Baseband Enable 0b0..Baseband mode is disabled. 0b1..Baseband mode is enabled.

CMT_MSC_BASE [2/4]

#define CMT_MSC_BASE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)

BASE - Baseband Enable 0b0..Baseband mode is disabled. 0b1..Baseband mode is enabled.

CMT_MSC_BASE [3/4]

#define CMT_MSC_BASE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)

BASE - Baseband Enable 0b0..Baseband mode is disabled. 0b1..Baseband mode is enabled.

CMT_MSC_BASE [4/4]

#define CMT_MSC_BASE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)

BASE - Baseband Enable 0b0..Baseband mode is disabled. 0b1..Baseband mode is enabled.

CMT_MSC_CMTDIV [1/5]

#define CMT_MSC_CMTDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)

CMTDIV - CMT Clock Divide Prescaler 0b00..IF * 1 0b01..IF * 2 0b10..IF * 4 0b11..IF * 8

CMT_MSC_CMTDIV [2/5]

#define CMT_MSC_CMTDIV

(

x

)

(((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)

CMTDIV - CMT Clock Divide Prescaler 0b00..IF * 1 0b01..IF * 2 0b10..IF * 4 0b11..IF * 8

CMT_MSC_CMTDIV [3/5]

#define CMT_MSC_CMTDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)

CMTDIV - CMT Clock Divide Prescaler 0b00..IF * 1 0b01..IF * 2 0b10..IF * 4 0b11..IF * 8

CMT_MSC_CMTDIV [4/5]

#define CMT_MSC_CMTDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)

CMTDIV - CMT Clock Divide Prescaler 0b00..IF * 1 0b01..IF * 2 0b10..IF * 4 0b11..IF * 8

CMT_MSC_CMTDIV [5/5]

#define CMT_MSC_CMTDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)

CMTDIV - CMT Clock Divide Prescaler 0b00..IF * 1 0b01..IF * 2 0b10..IF * 4 0b11..IF * 8

CMT_MSC_EOCF [1/4]

#define CMT_MSC_EOCF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)

EOCF - End Of Cycle Status Flag 0b0..End of modulation cycle has not occured since the flag last cleared. 0b1..End of modulator cycle has occurred.

CMT_MSC_EOCF [2/4]

#define CMT_MSC_EOCF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)

EOCF - End Of Cycle Status Flag 0b0..End of modulation cycle has not occured since the flag last cleared. 0b1..End of modulator cycle has occurred.

CMT_MSC_EOCF [3/4]

#define CMT_MSC_EOCF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)

EOCF - End Of Cycle Status Flag 0b0..End of modulation cycle has not occured since the flag last cleared. 0b1..End of modulator cycle has occurred.

CMT_MSC_EOCF [4/4]

#define CMT_MSC_EOCF

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)

EOCF - End Of Cycle Status Flag 0b0..End of modulation cycle has not occured since the flag last cleared. 0b1..End of modulator cycle has occurred.

CMT_MSC_EOCIE [1/4]

#define CMT_MSC_EOCIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)

EOCIE - End of Cycle Interrupt Enable 0b0..CPU interrupt is disabled. 0b1..CPU interrupt is enabled.

CMT_MSC_EOCIE [2/4]

#define CMT_MSC_EOCIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)

EOCIE - End of Cycle Interrupt Enable 0b0..CPU interrupt is disabled. 0b1..CPU interrupt is enabled.

CMT_MSC_EOCIE [3/4]

#define CMT_MSC_EOCIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)

EOCIE - End of Cycle Interrupt Enable 0b0..CPU interrupt is disabled. 0b1..CPU interrupt is enabled.

CMT_MSC_EOCIE [4/4]

#define CMT_MSC_EOCIE

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)

EOCIE - End of Cycle Interrupt Enable 0b0..CPU interrupt is disabled. 0b1..CPU interrupt is enabled.

CMT_MSC_EXSPC [1/4]

#define CMT_MSC_EXSPC

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)

EXSPC - Extended Space Enable 0b0..Extended space is disabled. 0b1..Extended space is enabled.

CMT_MSC_EXSPC [2/4]

#define CMT_MSC_EXSPC

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)

EXSPC - Extended Space Enable 0b0..Extended space is disabled. 0b1..Extended space is enabled.

CMT_MSC_EXSPC [3/4]

#define CMT_MSC_EXSPC

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)

EXSPC - Extended Space Enable 0b0..Extended space is disabled. 0b1..Extended space is enabled.

CMT_MSC_EXSPC [4/4]

#define CMT_MSC_EXSPC

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)

EXSPC - Extended Space Enable 0b0..Extended space is disabled. 0b1..Extended space is enabled.

CMT_MSC_FSK [1/4]

#define CMT_MSC_FSK

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)

FSK - FSK Mode Select 0b0..The CMT operates in Time or Baseband mode. 0b1..The CMT operates in FSK mode.

CMT_MSC_FSK [2/4]

#define CMT_MSC_FSK

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)

FSK - FSK Mode Select 0b0..The CMT operates in Time or Baseband mode. 0b1..The CMT operates in FSK mode.

CMT_MSC_FSK [3/4]

#define CMT_MSC_FSK

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)

FSK - FSK Mode Select 0b0..The CMT operates in Time or Baseband mode. 0b1..The CMT operates in FSK mode.

CMT_MSC_FSK [4/4]

#define CMT_MSC_FSK

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)

FSK - FSK Mode Select 0b0..The CMT operates in Time or Baseband mode. 0b1..The CMT operates in FSK mode.

CMT_MSC_MCGEN [1/4]

#define CMT_MSC_MCGEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)

MCGEN - Modulator and Carrier Generator Enable 0b0..Modulator and carrier generator disabled 0b1..Modulator and carrier generator enabled

CMT_MSC_MCGEN [2/4]

#define CMT_MSC_MCGEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)

MCGEN - Modulator and Carrier Generator Enable 0b0..Modulator and carrier generator disabled 0b1..Modulator and carrier generator enabled

CMT_MSC_MCGEN [3/4]

#define CMT_MSC_MCGEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)

MCGEN - Modulator and Carrier Generator Enable 0b0..Modulator and carrier generator disabled 0b1..Modulator and carrier generator enabled

CMT_MSC_MCGEN [4/4]

#define CMT_MSC_MCGEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)

MCGEN - Modulator and Carrier Generator Enable 0b0..Modulator and carrier generator disabled 0b1..Modulator and carrier generator enabled

CMT_OC_CMTPOL [1/4]

#define CMT_OC_CMTPOL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)

CMTPOL - CMT Output Polarity 0b0..The IRO signal is active-low. 0b1..The IRO signal is active-high.

CMT_OC_CMTPOL [2/4]

#define CMT_OC_CMTPOL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)

CMTPOL - CMT Output Polarity 0b0..The IRO signal is active-low. 0b1..The IRO signal is active-high.

CMT_OC_CMTPOL [3/4]

#define CMT_OC_CMTPOL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)

CMTPOL - CMT Output Polarity 0b0..The IRO signal is active-low. 0b1..The IRO signal is active-high.

CMT_OC_CMTPOL [4/4]

#define CMT_OC_CMTPOL

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)

CMTPOL - CMT Output Polarity 0b0..The IRO signal is active-low. 0b1..The IRO signal is active-high.

CMT_OC_IROPEN [1/4]

#define CMT_OC_IROPEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)

IROPEN - IRO Pin Enable 0b0..The IRO signal is disabled. 0b1..The IRO signal is enabled as output.

CMT_OC_IROPEN [2/4]

#define CMT_OC_IROPEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)

IROPEN - IRO Pin Enable 0b0..The IRO signal is disabled. 0b1..The IRO signal is enabled as output.

CMT_OC_IROPEN [3/4]

#define CMT_OC_IROPEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)

IROPEN - IRO Pin Enable 0b0..The IRO signal is disabled. 0b1..The IRO signal is enabled as output.

CMT_OC_IROPEN [4/4]

#define CMT_OC_IROPEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)

IROPEN - IRO Pin Enable 0b0..The IRO signal is disabled. 0b1..The IRO signal is enabled as output.

CMT_PPS_PPSDIV [1/5]

#define CMT_PPS_PPSDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)

PPSDIV - Primary Prescaler Divider 0b0000..Bus clock * 1 0b0001..Bus clock * 2 0b0010..Bus clock * 3 0b0011..Bus clock * 4 0b0100..Bus clock * 5 0b0101..Bus clock * 6 0b0110..Bus clock * 7 0b0111..Bus clock * 8 0b1000..Bus clock * 9 0b1001..Bus clock * 10 0b1010..Bus clock * 11 0b1011..Bus clock * 12 0b1100..Bus clock * 13 0b1101..Bus clock * 14 0b1110..Bus clock * 15 0b1111..Bus clock * 16

CMT_PPS_PPSDIV [2/5]

#define CMT_PPS_PPSDIV

(

x

)

(((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)

PPSDIV - Primary Prescaler Divider 0b0000..Bus clock * 1 0b0001..Bus clock * 2 0b0010..Bus clock * 3 0b0011..Bus clock * 4 0b0100..Bus clock * 5 0b0101..Bus clock * 6 0b0110..Bus clock * 7 0b0111..Bus clock * 8 0b1000..Bus clock * 9 0b1001..Bus clock * 10 0b1010..Bus clock * 11 0b1011..Bus clock * 12 0b1100..Bus clock * 13 0b1101..Bus clock * 14 0b1110..Bus clock * 15 0b1111..Bus clock * 16

CMT_PPS_PPSDIV [3/5]

#define CMT_PPS_PPSDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)

PPSDIV - Primary Prescaler Divider 0b0000..Bus clock * 1 0b0001..Bus clock * 2 0b0010..Bus clock * 3 0b0011..Bus clock * 4 0b0100..Bus clock * 5 0b0101..Bus clock * 6 0b0110..Bus clock * 7 0b0111..Bus clock * 8 0b1000..Bus clock * 9 0b1001..Bus clock * 10 0b1010..Bus clock * 11 0b1011..Bus clock * 12 0b1100..Bus clock * 13 0b1101..Bus clock * 14 0b1110..Bus clock * 15 0b1111..Bus clock * 16

CMT_PPS_PPSDIV [4/5]

#define CMT_PPS_PPSDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)

PPSDIV - Primary Prescaler Divider 0b0000..Bus clock * 1 0b0001..Bus clock * 2 0b0010..Bus clock * 3 0b0011..Bus clock * 4 0b0100..Bus clock * 5 0b0101..Bus clock * 6 0b0110..Bus clock * 7 0b0111..Bus clock * 8 0b1000..Bus clock * 9 0b1001..Bus clock * 10 0b1010..Bus clock * 11 0b1011..Bus clock * 12 0b1100..Bus clock * 13 0b1101..Bus clock * 14 0b1110..Bus clock * 15 0b1111..Bus clock * 16

CMT_PPS_PPSDIV [5/5]

#define CMT_PPS_PPSDIV

(

x

)

(((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)

PPSDIV - Primary Prescaler Divider 0b0000..Bus clock * 1 0b0001..Bus clock * 2 0b0010..Bus clock * 3 0b0011..Bus clock * 4 0b0100..Bus clock * 5 0b0101..Bus clock * 6 0b0110..Bus clock * 7 0b0111..Bus clock * 8 0b1000..Bus clock * 9 0b1001..Bus clock * 10 0b1010..Bus clock * 11 0b1011..Bus clock * 12 0b1100..Bus clock * 13 0b1101..Bus clock * 14 0b1110..Bus clock * 15 0b1111..Bus clock * 16