mikroSDK Reference Manual
stm32f2xx_hal_rcc.h
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1
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F2xx_HAL_RCC_H
22#define __STM32F2xx_HAL_RCC_H
23
24#ifdef __cplusplus
25 extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f2xx_hal_def.h"
30
39/* Exported types ------------------------------------------------------------*/
47typedef struct
48{
49 uint32_t PLLState;
52 uint32_t PLLSource;
55 uint32_t PLLM;
58 uint32_t PLLN;
61 uint32_t PLLP;
64 uint32_t PLLQ;
67}RCC_PLLInitTypeDef;
68
72typedef struct
73{
74 uint32_t OscillatorType;
77 uint32_t HSEState;
80 uint32_t LSEState;
83 uint32_t HSIState;
86 uint32_t HSICalibrationValue;
89 uint32_t LSIState;
92 RCC_PLLInitTypeDef PLL;
93}RCC_OscInitTypeDef;
94
98typedef struct
99{
100 uint32_t ClockType;
103 uint32_t SYSCLKSource;
106 uint32_t AHBCLKDivider;
109 uint32_t APB1CLKDivider;
112 uint32_t APB2CLKDivider;
115}RCC_ClkInitTypeDef;
116
121/* Exported constants --------------------------------------------------------*/
129#define RCC_OSCILLATORTYPE_NONE 0x00000000U
130#define RCC_OSCILLATORTYPE_HSE 0x00000001U
131#define RCC_OSCILLATORTYPE_HSI 0x00000002U
132#define RCC_OSCILLATORTYPE_LSE 0x00000004U
133#define RCC_OSCILLATORTYPE_LSI 0x00000008U
141#define RCC_HSE_OFF ((uint8_t)0x00)
142#define RCC_HSE_ON ((uint8_t)0x01)
143#define RCC_HSE_BYPASS ((uint8_t)0x05)
151#define RCC_LSE_OFF ((uint8_t)0x00)
152#define RCC_LSE_ON ((uint8_t)0x01)
153#define RCC_LSE_BYPASS ((uint8_t)0x05)
161#define RCC_HSI_OFF ((uint8_t)0x00)
162#define RCC_HSI_ON ((uint8_t)0x01)
163
164#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
172#define RCC_LSI_OFF ((uint8_t)0x00)
173#define RCC_LSI_ON ((uint8_t)0x01)
181#define RCC_PLL_NONE ((uint8_t)0x00)
182#define RCC_PLL_OFF ((uint8_t)0x01)
183#define RCC_PLL_ON ((uint8_t)0x02)
191#define RCC_PLLP_DIV2 0x00000002U
192#define RCC_PLLP_DIV4 0x00000004U
193#define RCC_PLLP_DIV6 0x00000006U
194#define RCC_PLLP_DIV8 0x00000008U
202#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
203#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
211#define RCC_CLOCKTYPE_SYSCLK 0x00000001U
212#define RCC_CLOCKTYPE_HCLK 0x00000002U
213#define RCC_CLOCKTYPE_PCLK1 0x00000004U
214#define RCC_CLOCKTYPE_PCLK2 0x00000008U
222#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
223#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
224#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
232#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
233#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
234#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
242#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
243#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
244#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
245#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
246#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
247#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
248#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
249#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
250#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
258#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
259#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
260#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
261#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
262#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
270#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
271#define RCC_RTCCLKSOURCE_LSE 0x00000100U
272#define RCC_RTCCLKSOURCE_LSI 0x00000200U
273#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
274#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
275#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
276#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
277#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
278#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
279#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
280#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
281#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
282#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
283#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
284#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
285#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
286#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
287#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
288#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
289#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
290#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
291#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
292#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
293#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
294#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
295#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
296#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
297#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
298#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
299#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
300#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
301#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
302#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
303#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
311#define RCC_MCO1 0x00000000U
312#define RCC_MCO2 0x00000001U
320#define RCC_MCO1SOURCE_HSI 0x00000000U
321#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
322#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
323#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
331#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
332#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
333#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
334#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
342#define RCC_MCODIV_1 0x00000000U
343#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
344#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
345#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
346#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
354#define RCC_IT_LSIRDY ((uint8_t)0x01)
355#define RCC_IT_LSERDY ((uint8_t)0x02)
356#define RCC_IT_HSIRDY ((uint8_t)0x04)
357#define RCC_IT_HSERDY ((uint8_t)0x08)
358#define RCC_IT_PLLRDY ((uint8_t)0x10)
359#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
360#define RCC_IT_CSS ((uint8_t)0x80)
374/* Flags in the CR register */
375#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
376#define RCC_FLAG_HSERDY ((uint8_t)0x31)
377#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
378#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
379
380/* Flags in the BDCR register */
381#define RCC_FLAG_LSERDY ((uint8_t)0x41)
382
383/* Flags in the CSR register */
384#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
385#define RCC_FLAG_BORRST ((uint8_t)0x79)
386#define RCC_FLAG_PINRST ((uint8_t)0x7A)
387#define RCC_FLAG_PORRST ((uint8_t)0x7B)
388#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
389#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
390#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
391#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
400/* Exported macro ------------------------------------------------------------*/
412#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
413 __IO uint32_t tmpreg = 0x00U; \
414 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
415 /* Delay after an RCC peripheral clock enabling */ \
416 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
417 UNUSED(tmpreg); \
418 } while(0)
419#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
420 __IO uint32_t tmpreg = 0x00U; \
421 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
422 /* Delay after an RCC peripheral clock enabling */ \
423 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
424 UNUSED(tmpreg); \
425 } while(0)
426#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
427 __IO uint32_t tmpreg = 0x00U; \
428 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
429 /* Delay after an RCC peripheral clock enabling */ \
430 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
431 UNUSED(tmpreg); \
432 } while(0)
433#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
434 __IO uint32_t tmpreg = 0x00U; \
435 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
436 /* Delay after an RCC peripheral clock enabling */ \
437 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
438 UNUSED(tmpreg); \
439 } while(0)
440#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
441 __IO uint32_t tmpreg = 0x00U; \
442 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
443 /* Delay after an RCC peripheral clock enabling */ \
444 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
445 UNUSED(tmpreg); \
446 } while(0)
447#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
448 __IO uint32_t tmpreg = 0x00U; \
449 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
450 /* Delay after an RCC peripheral clock enabling */ \
451 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
452 UNUSED(tmpreg); \
453 } while(0)
454#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
455 __IO uint32_t tmpreg = 0x00U; \
456 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
457 /* Delay after an RCC peripheral clock enabling */ \
458 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
459 UNUSED(tmpreg); \
460 } while(0)
461#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
462 __IO uint32_t tmpreg = 0x00U; \
463 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
464 /* Delay after an RCC peripheral clock enabling */ \
465 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
466 UNUSED(tmpreg); \
467 } while(0)
468#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
469 __IO uint32_t tmpreg = 0x00U; \
470 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
471 /* Delay after an RCC peripheral clock enabling */ \
472 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
473 UNUSED(tmpreg); \
474 } while(0)
475#define __HAL_RCC_CRC_CLK_ENABLE() do { \
476 __IO uint32_t tmpreg = 0x00U; \
477 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
478 /* Delay after an RCC peripheral clock enabling */ \
479 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
480 UNUSED(tmpreg); \
481 } while(0)
482#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
483 __IO uint32_t tmpreg = 0x00U; \
484 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
485 /* Delay after an RCC peripheral clock enabling */ \
486 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
487 UNUSED(tmpreg); \
488 } while(0)
489#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
490 __IO uint32_t tmpreg = 0x00U; \
491 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
492 /* Delay after an RCC peripheral clock enabling */ \
493 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
494 UNUSED(tmpreg); \
495 } while(0)
496#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
497 __IO uint32_t tmpreg = 0x00U; \
498 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
499 /* Delay after an RCC peripheral clock enabling */ \
500 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
501 UNUSED(tmpreg); \
502 } while(0)
503#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
504 __IO uint32_t tmpreg = 0x00U; \
505 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
506 /* Delay after an RCC peripheral clock enabling */ \
507 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
508 UNUSED(tmpreg); \
509 } while(0)
510#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
511 __IO uint32_t tmpreg = 0x00U; \
512 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
513 /* Delay after an RCC peripheral clock enabling */ \
514 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
515 UNUSED(tmpreg); \
516 } while(0)
517#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
518#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
519#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
520#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
521#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
522#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
523#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
524#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
525#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
526#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
527#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
528#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
529#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
530#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
531#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
542#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
543#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
544#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
545#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) != RESET)
546#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) != RESET)
547#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) != RESET)
548#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) != RESET)
549#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
550#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) != RESET)
551#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) != RESET)
552#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) != RESET)
553#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
554#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
555#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) != RESET)
556#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
557
558#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
559#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
560#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
561#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) == RESET)
562#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) == RESET)
563#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) == RESET)
564#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) == RESET)
565#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
566#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) == RESET)
567#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) == RESET)
568#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) == RESET)
569#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
570#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
571#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) == RESET)
572#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
584#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
585 __HAL_RCC_SYSCFG_CLK_ENABLE();\
586 }while(0)
587#define __HAL_RCC_RNG_CLK_ENABLE() do { \
588 __IO uint32_t tmpreg = 0x00U; \
589 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
590 /* Delay after an RCC peripheral clock enabling */ \
591 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
592 UNUSED(tmpreg); \
593 } while(0)
594
595#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
596#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
608#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) != RESET)
609#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) != RESET)
610
611#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) == RESET)
612#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) == RESET)
624#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
625 __IO uint32_t tmpreg = 0x00U; \
626 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
627 /* Delay after an RCC peripheral clock enabling */ \
628 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
629 UNUSED(tmpreg); \
630 } while(0)
631#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
643#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))!= RESET)
644#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))== RESET)
656#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
657 __IO uint32_t tmpreg = 0x00U; \
658 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
659 /* Delay after an RCC peripheral clock enabling */ \
660 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
661 UNUSED(tmpreg); \
662 } while(0)
663#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
664 __IO uint32_t tmpreg = 0x00U; \
665 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
666 /* Delay after an RCC peripheral clock enabling */ \
667 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
668 UNUSED(tmpreg); \
669 } while(0)
670#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
671 __IO uint32_t tmpreg = 0x00U; \
672 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
673 /* Delay after an RCC peripheral clock enabling */ \
674 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
675 UNUSED(tmpreg); \
676 } while(0)
677#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
678 __IO uint32_t tmpreg = 0x00U; \
679 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
680 /* Delay after an RCC peripheral clock enabling */ \
681 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
682 UNUSED(tmpreg); \
683 } while(0)
684#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
685 __IO uint32_t tmpreg = 0x00U; \
686 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
687 /* Delay after an RCC peripheral clock enabling */ \
688 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
689 UNUSED(tmpreg); \
690 } while(0)
691#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
692 __IO uint32_t tmpreg = 0x00U; \
693 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
694 /* Delay after an RCC peripheral clock enabling */ \
695 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
696 UNUSED(tmpreg); \
697 } while(0)
698#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
699 __IO uint32_t tmpreg = 0x00U; \
700 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
701 /* Delay after an RCC peripheral clock enabling */ \
702 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
703 UNUSED(tmpreg); \
704 } while(0)
705#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
706 __IO uint32_t tmpreg = 0x00U; \
707 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
708 /* Delay after an RCC peripheral clock enabling */ \
709 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
710 UNUSED(tmpreg); \
711 } while(0)
712#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
713 __IO uint32_t tmpreg = 0x00U; \
714 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
715 /* Delay after an RCC peripheral clock enabling */ \
716 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
717 UNUSED(tmpreg); \
718 } while(0)
719#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
720 __IO uint32_t tmpreg = 0x00U; \
721 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
722 /* Delay after an RCC peripheral clock enabling */ \
723 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
724 UNUSED(tmpreg); \
725 } while(0)
726#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
727 __IO uint32_t tmpreg = 0x00U; \
728 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
729 /* Delay after an RCC peripheral clock enabling */ \
730 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
731 UNUSED(tmpreg); \
732 } while(0)
733#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
734 __IO uint32_t tmpreg = 0x00U; \
735 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
736 /* Delay after an RCC peripheral clock enabling */ \
737 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
738 UNUSED(tmpreg); \
739 } while(0)
740#define __HAL_RCC_USART2_CLK_ENABLE() do { \
741 __IO uint32_t tmpreg = 0x00U; \
742 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
743 /* Delay after an RCC peripheral clock enabling */ \
744 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
745 UNUSED(tmpreg); \
746 } while(0)
747#define __HAL_RCC_USART3_CLK_ENABLE() do { \
748 __IO uint32_t tmpreg = 0x00U; \
749 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
750 /* Delay after an RCC peripheral clock enabling */ \
751 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
752 UNUSED(tmpreg); \
753 } while(0)
754#define __HAL_RCC_UART4_CLK_ENABLE() do { \
755 __IO uint32_t tmpreg = 0x00U; \
756 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
757 /* Delay after an RCC peripheral clock enabling */ \
758 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
759 UNUSED(tmpreg); \
760 } while(0)
761#define __HAL_RCC_UART5_CLK_ENABLE() do { \
762 __IO uint32_t tmpreg = 0x00U; \
763 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
764 /* Delay after an RCC peripheral clock enabling */ \
765 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
766 UNUSED(tmpreg); \
767 } while(0)
768#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
769 __IO uint32_t tmpreg = 0x00U; \
770 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
771 /* Delay after an RCC peripheral clock enabling */ \
772 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
773 UNUSED(tmpreg); \
774 } while(0)
775#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
776 __IO uint32_t tmpreg = 0x00U; \
777 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
778 /* Delay after an RCC peripheral clock enabling */ \
779 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
780 UNUSED(tmpreg); \
781 } while(0)
782#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
783 __IO uint32_t tmpreg = 0x00U; \
784 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
785 /* Delay after an RCC peripheral clock enabling */ \
786 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
787 UNUSED(tmpreg); \
788 } while(0)
789#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
790 __IO uint32_t tmpreg = 0x00U; \
791 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
792 /* Delay after an RCC peripheral clock enabling */ \
793 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
794 UNUSED(tmpreg); \
795 } while(0)
796#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
797 __IO uint32_t tmpreg = 0x00U; \
798 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
799 /* Delay after an RCC peripheral clock enabling */ \
800 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
801 UNUSED(tmpreg); \
802 } while(0)
803#define __HAL_RCC_PWR_CLK_ENABLE() do { \
804 __IO uint32_t tmpreg = 0x00U; \
805 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
806 /* Delay after an RCC peripheral clock enabling */ \
807 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
808 UNUSED(tmpreg); \
809 } while(0)
810#define __HAL_RCC_DAC_CLK_ENABLE() do { \
811 __IO uint32_t tmpreg = 0x00U; \
812 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
813 /* Delay after an RCC peripheral clock enabling */ \
814 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
815 UNUSED(tmpreg); \
816 } while(0)
817
818#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
819#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
820#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
821#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
822#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
823#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
824#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
825#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
826#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
827#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
828#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
829#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
830#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
831#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
832#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
833#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
834#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
835#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
836#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
837#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
838#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
839#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
840#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
852#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))!= RESET)
853#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))!= RESET)
854#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))!= RESET)
855#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))!= RESET)
856#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))!= RESET)
857#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))!= RESET)
858#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))!= RESET)
859#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))!= RESET)
860#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))!= RESET)
861#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))!= RESET)
862#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))!= RESET)
863#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))!= RESET)
864#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))!= RESET)
865#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))!= RESET)
866#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))!= RESET)
867#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))!= RESET)
868#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))!= RESET)
869#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))!= RESET)
870#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))!= RESET)
871#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))!= RESET)
872#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))!= RESET)
873#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))!= RESET)
874#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))!= RESET)
875
876#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))== RESET)
877#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))== RESET)
878#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))== RESET)
879#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))== RESET)
880#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))== RESET)
881#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))== RESET)
882#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))== RESET)
883#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))== RESET)
884#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))== RESET)
885#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))== RESET)
886#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))== RESET)
887#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))== RESET)
888#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))== RESET)
889#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))== RESET)
890#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))== RESET)
891#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))== RESET)
892#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))== RESET)
893#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))== RESET)
894#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))== RESET)
895#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))== RESET)
896#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))== RESET)
897#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))== RESET)
898#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))== RESET)
910#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
911 __IO uint32_t tmpreg = 0x00U; \
912 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
913 /* Delay after an RCC peripheral clock enabling */ \
914 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
915 UNUSED(tmpreg); \
916 } while(0)
917#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
918 __IO uint32_t tmpreg = 0x00U; \
919 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
920 /* Delay after an RCC peripheral clock enabling */ \
921 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
922 UNUSED(tmpreg); \
923 } while(0)
924#define __HAL_RCC_USART1_CLK_ENABLE() do { \
925 __IO uint32_t tmpreg = 0x00U; \
926 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
927 /* Delay after an RCC peripheral clock enabling */ \
928 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
929 UNUSED(tmpreg); \
930 } while(0)
931#define __HAL_RCC_USART6_CLK_ENABLE() do { \
932 __IO uint32_t tmpreg = 0x00U; \
933 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
934 /* Delay after an RCC peripheral clock enabling */ \
935 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
936 UNUSED(tmpreg); \
937 } while(0)
938#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
939 __IO uint32_t tmpreg = 0x00U; \
940 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
941 /* Delay after an RCC peripheral clock enabling */ \
942 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
943 UNUSED(tmpreg); \
944 } while(0)
945#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
946 __IO uint32_t tmpreg = 0x00U; \
947 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
948 /* Delay after an RCC peripheral clock enabling */ \
949 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
950 UNUSED(tmpreg); \
951 } while(0)
952#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
953 __IO uint32_t tmpreg = 0x00U; \
954 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
955 /* Delay after an RCC peripheral clock enabling */ \
956 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
957 UNUSED(tmpreg); \
958 } while(0)
959#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
960 __IO uint32_t tmpreg = 0x00U; \
961 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
962 /* Delay after an RCC peripheral clock enabling */ \
963 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
964 UNUSED(tmpreg); \
965 } while(0)
966#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
967 __IO uint32_t tmpreg = 0x00U; \
968 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
969 /* Delay after an RCC peripheral clock enabling */ \
970 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
971 UNUSED(tmpreg); \
972 } while(0)
973#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
974 __IO uint32_t tmpreg = 0x00U; \
975 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
976 /* Delay after an RCC peripheral clock enabling */ \
977 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
978 UNUSED(tmpreg); \
979 } while(0)
980
981#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
982 __IO uint32_t tmpreg = 0x00U; \
983 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
984 /* Delay after an RCC peripheral clock enabling */ \
985 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
986 UNUSED(tmpreg); \
987 } while(0)
988#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
989 __IO uint32_t tmpreg = 0x00U; \
990 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
991 /* Delay after an RCC peripheral clock enabling */ \
992 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
993 UNUSED(tmpreg); \
994 } while(0)
995#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
996 __IO uint32_t tmpreg = 0x00U; \
997 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
998 /* Delay after an RCC peripheral clock enabling */ \
999 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1000 UNUSED(tmpreg); \
1001 } while(0)
1002#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
1003#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
1004#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
1005#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
1006#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
1007#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
1008#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
1009#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
1010#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
1011#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
1012#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
1013#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1014#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
1026#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))!= RESET)
1027#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))!= RESET)
1028#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))!= RESET)
1029#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))!= RESET)
1030#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))!= RESET)
1031#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))!= RESET)
1032#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))!= RESET)
1033#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))!= RESET)
1034#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))!= RESET)
1035#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))!= RESET)
1036#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))!= RESET)
1037#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))!= RESET)
1038#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))!= RESET)
1039
1040#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))== RESET)
1041#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))== RESET)
1042#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))== RESET)
1043#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))== RESET)
1044#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))== RESET)
1045#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))== RESET)
1046#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))== RESET)
1047#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))== RESET)
1048#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))== RESET)
1049#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))== RESET)
1050#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))== RESET)
1051#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))== RESET)
1052#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))== RESET)
1061#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
1062#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
1063#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
1064#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
1065#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
1066#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
1067#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
1068#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
1069#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
1070#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
1071#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
1072#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
1073#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
1074#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
1075#define __HAL_RCC_OTGHSULPI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHSULPIRST))
1076
1077#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
1078#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
1079#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
1080#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
1081#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
1082#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
1083#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
1084#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
1085#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
1086#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
1087#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
1088#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
1089#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
1090#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
1091#define __HAL_RCC_OTGHSULPI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHSULPIRST))
1100#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
1101#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
1102#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
1103
1104#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
1105#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
1106#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
1115#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
1116#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
1117#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
1118#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
1119#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
1120#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1121#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1122#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1123#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1124#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1125#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
1126#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
1127#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1128#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
1129#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1130#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1131#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1132#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
1133#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
1134#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
1135#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
1136#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
1137#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
1138#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1139
1140#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
1141#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
1142#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
1143#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
1144#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
1145#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1146#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1147#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1148#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1149#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1150#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
1151#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
1152#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1153#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
1154#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1155#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1156#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1157#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
1158#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
1159#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
1160#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
1161#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
1162#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
1163#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1172#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
1173#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
1174#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
1175#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
1176#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
1177#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
1178#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
1179#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
1180#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
1181#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
1182#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
1183#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
1184
1185#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
1186#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
1187#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
1188#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
1189#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
1190#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
1191#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
1192#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
1193#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
1194#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
1195#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
1196#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
1205#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
1206#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
1207
1208#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
1209#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
1222#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
1223#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
1224#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
1225#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
1226#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
1227#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
1228#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
1229#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
1230#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
1231#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
1232#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
1233#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
1234#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
1235#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
1236#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
1237#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
1238#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
1239#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
1240
1241#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
1242#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
1243#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
1244#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
1245#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
1246#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
1247#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
1248#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
1249#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
1250#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
1251#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
1252#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
1253#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
1254#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
1255#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
1256#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
1257#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
1258#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
1271#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
1272#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
1273
1274#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
1275#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
1288#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
1289#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
1302#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
1303#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
1304#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
1305#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
1306#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
1307#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
1308#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
1309#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
1310#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
1311#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
1312#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
1313#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
1314#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
1315#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
1316#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
1317#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
1318#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
1319#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
1320#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
1321#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
1322#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
1323#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
1324#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
1325#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
1326#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
1327#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
1328#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
1329#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
1330#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
1331#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
1332#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
1333#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
1334#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
1335#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
1336#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
1337#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
1338#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
1339#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
1340#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
1341#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
1342#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
1343#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
1344#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
1345#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
1346#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
1347#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
1360#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
1361#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
1362#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
1363#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
1364#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
1365#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
1366#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
1367#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
1368#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
1369#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
1370#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
1371#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
1372#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
1373
1374#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
1375#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
1376#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
1377#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
1378#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
1379#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
1380#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
1381#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
1382#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
1383#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
1384#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
1385#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
1386#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
1410#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
1411#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
1412
1420#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
1421 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
1438#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
1439#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
1469#define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
1495#define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
1496
1508#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
1509#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
1510
1533#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
1534 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
1535
1536#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
1537 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
1538 } while (0U)
1539
1547#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
1548
1555#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
1556
1562#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
1563#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
1579#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
1580#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
1581
1582
1611#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
1612 MODIFY_REG(RCC->PLLCFGR, \
1613 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ), \
1614 ((__RCC_PLLSource__) | (__PLLM__)| ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \
1615 ((((__PLLP__) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)))
1628#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
1629
1639#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
1640
1648#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
1649#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
1650
1664#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
1665
1674#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
1698#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1699 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
1700
1716#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
1717 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
1733#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
1734
1742#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
1743
1750#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
1771#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1772
1784#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1785
1798#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1799
1812#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1813
1817#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
1818
1837#define RCC_FLAG_MASK ((uint8_t)0x1FU)
1838#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
1839
1840#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
1849/* Include RCC HAL Extended module */
1850#include "stm32f2xx_hal_rcc_ex.h"
1851/* Exported functions --------------------------------------------------------*/
1859/* Initialization and de-initialization functions ******************************/
1860HAL_StatusTypeDef HAL_RCC_DeInit(void);
1861HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1862HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1870/* Peripheral Control functions ************************************************/
1871void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1872void HAL_RCC_EnableCSS(void);
1873void HAL_RCC_DisableCSS(void);
1874uint32_t HAL_RCC_GetSysClockFreq(void);
1875uint32_t HAL_RCC_GetHCLKFreq(void);
1876uint32_t HAL_RCC_GetPCLK1Freq(void);
1877uint32_t HAL_RCC_GetPCLK2Freq(void);
1878void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1879void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1880
1881/* CSS NMI IRQ handler */
1882void HAL_RCC_NMI_IRQHandler(void);
1883
1884/* User Callbacks in non blocking mode (IT mode) */
1885void HAL_RCC_CSSCallback(void);
1886
1895/* Private types -------------------------------------------------------------*/
1896/* Private variables ---------------------------------------------------------*/
1897/* Private constants ---------------------------------------------------------*/
1906#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1907/* --- CR Register ---*/
1908/* Alias word address of HSION bit */
1909#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
1910#define RCC_HSION_BIT_NUMBER 0x00U
1911#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
1912/* Alias word address of CSSON bit */
1913#define RCC_CSSON_BIT_NUMBER 0x13U
1914#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
1915/* Alias word address of PLLON bit */
1916#define RCC_PLLON_BIT_NUMBER 0x18U
1917#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
1918/* Alias word address of PLLI2SON bit */
1919#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
1920#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
1921
1922/* --- CFGR Register ---*/
1923/* Alias word address of I2SSRC bit */
1924#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
1925#define RCC_I2SSRC_BIT_NUMBER 0x17U
1926#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
1927
1928/* --- BDCR Register ---*/
1929/* Alias word address of RTCEN bit */
1930#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
1931#define RCC_RTCEN_BIT_NUMBER 0x0FU
1932#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
1933/* Alias word address of BDRST bit */
1934#define RCC_BDRST_BIT_NUMBER 0x10U
1935#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
1936
1937/* --- CSR Register ---*/
1938/* Alias word address of LSION bit */
1939#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
1940#define RCC_LSION_BIT_NUMBER 0x00U
1941#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
1942
1943/* CR register byte 3 (Bits[23:16]) base address */
1944#define RCC_CR_BYTE2_ADDRESS 0x40023802U
1945
1946/* CIR register byte 2 (Bits[15:8]) base address */
1947#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
1948
1949/* CIR register byte 3 (Bits[23:16]) base address */
1950#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
1951
1952/* BDCR register base address */
1953#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
1954
1955#define RCC_DBP_TIMEOUT_VALUE 2U
1956#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1957
1958#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1959#define HSI_TIMEOUT_VALUE 2U /* 2 ms */
1960#define LSI_TIMEOUT_VALUE 2U /* 2 ms */
1961
1962#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 100 ms */
1971/* Private macros ------------------------------------------------------------*/
1979#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
1980
1981#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
1982 ((HSE) == RCC_HSE_BYPASS))
1983
1984#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
1985 ((LSE) == RCC_LSE_BYPASS))
1986
1987#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
1988
1989#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
1990
1991#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
1992
1993#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
1994 ((SOURCE) == RCC_PLLSOURCE_HSE))
1995
1996#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
1997 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
1998 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
1999
2000#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
2001 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
2002 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
2003 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
2004 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
2005 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
2006 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
2007 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
2008 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
2009 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
2010 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
2011 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
2012 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
2013 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
2014 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
2015 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
2016 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
2017 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
2018 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
2019 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
2020 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
2021 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
2022 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
2023 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
2024 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
2025 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
2026 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
2027 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
2028 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
2029 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
2030 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
2031 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
2032
2033#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
2034
2035#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
2036
2037#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
2038
2039#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
2040
2041#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
2042 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
2043 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
2044 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
2045 ((HCLK) == RCC_SYSCLK_DIV512))
2046
2047#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
2048
2049#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
2050 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
2051 ((PCLK) == RCC_HCLK_DIV16))
2052
2053#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
2054
2055#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
2056 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
2057
2058#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
2059 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
2060
2061#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
2062 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
2063 ((DIV) == RCC_MCODIV_5))
2064#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
2065
2082#ifdef __cplusplus
2083}
2084#endif
2085
2086#endif /* __STM32F2xx_HAL_RCC_H */
2087
2088/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f1xx_hal_def.h:40
stm32f2xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
stm32f2xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition stm32f1xx_hal_rcc.h:65
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition stm32f1xx_hal_rcc_ex.h:229
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition stm32f1xx_hal_rcc.h:50
RCC_PLLInitTypeDef::PLLN
uint32_t PLLN
Definition stm32f2xx_hal_rcc.h:58
RCC_PLLInitTypeDef::PLLQ
uint32_t PLLQ
Definition stm32f2xx_hal_rcc.h:64
RCC_PLLInitTypeDef::PLLP
uint32_t PLLP
Definition stm32f2xx_hal_rcc.h:61
RCC_PLLInitTypeDef::PLLM
uint32_t PLLM
Definition stm32f2xx_hal_rcc.h:55