|
mikroSDK Reference Manual
|
Macros | |
| #define | DMAMUX_BASE (0x40021000u) |
| #define | DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) |
| #define | DMAMUX_BASE_ADDRS { DMAMUX_BASE } |
| #define | DMAMUX_BASE_PTRS { DMAMUX } |
| #define | DMAMUX_CHCFG_COUNT (16U) |
| #define | DMAMUX_CHCFG_COUNT (32U) |
| #define | DMAMUX_CHCFG_COUNT (32U) |
| #define | DMAMUX_CHCFG_COUNT (32U) |
CHCFG - Channel Configuration register | |
| #define | DMAMUX_CHCFG_SOURCE_MASK (0x3FU) |
| #define | DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
| #define | DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
| #define | DMAMUX_CHCFG_TRIG_MASK (0x40U) |
| #define | DMAMUX_CHCFG_TRIG_SHIFT (6U) |
| #define | DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
| #define | DMAMUX_CHCFG_ENBL_MASK (0x80U) |
| #define | DMAMUX_CHCFG_ENBL_SHIFT (7U) |
| #define | DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
| #define | DMAMUX_CHCFG_SOURCE_MASK 0x3Fu |
| #define | DMAMUX_CHCFG_SOURCE_SHIFT 0 |
| #define | DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK) |
| #define | DMAMUX_CHCFG_TRIG_MASK 0x40u |
| #define | DMAMUX_CHCFG_TRIG_SHIFT 6 |
| #define | DMAMUX_CHCFG_ENBL_MASK 0x80u |
| #define | DMAMUX_CHCFG_ENBL_SHIFT 7 |
| #define | DMAMUX_CHCFG_SOURCE_MASK (0x3FU) |
| #define | DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
| #define | DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
| #define | DMAMUX_CHCFG_TRIG_MASK (0x40U) |
| #define | DMAMUX_CHCFG_TRIG_SHIFT (6U) |
| #define | DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
| #define | DMAMUX_CHCFG_ENBL_MASK (0x80U) |
| #define | DMAMUX_CHCFG_ENBL_SHIFT (7U) |
| #define | DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
| #define | DMAMUX_CHCFG_SOURCE_MASK (0x3FU) |
| #define | DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
| #define | DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
| #define | DMAMUX_CHCFG_TRIG_MASK (0x40U) |
| #define | DMAMUX_CHCFG_TRIG_SHIFT (6U) |
| #define | DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
| #define | DMAMUX_CHCFG_ENBL_MASK (0x80U) |
| #define | DMAMUX_CHCFG_ENBL_SHIFT (7U) |
| #define | DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
| #define | DMAMUX_CHCFG_SOURCE_MASK (0x3FU) |
| #define | DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
| #define | DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
| #define | DMAMUX_CHCFG_TRIG_MASK (0x40U) |
| #define | DMAMUX_CHCFG_TRIG_SHIFT (6U) |
| #define | DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
| #define | DMAMUX_CHCFG_ENBL_MASK (0x80U) |
| #define | DMAMUX_CHCFG_ENBL_SHIFT (7U) |
| #define | DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
| #define | DMAMUX_CHCFG_SOURCE_MASK (0x3FU) |
| #define | DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
| #define | DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
| #define | DMAMUX_CHCFG_TRIG_MASK (0x40U) |
| #define | DMAMUX_CHCFG_TRIG_SHIFT (6U) |
| #define | DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
| #define | DMAMUX_CHCFG_ENBL_MASK (0x80U) |
| #define | DMAMUX_CHCFG_ENBL_SHIFT (7U) |
| #define | DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
CHCFG - Channel Configuration register | |
| #define | DMAMUX_CHCFG_COUNT (16U) |
| #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) |
Peripheral DMAMUX base pointer
| #define DMAMUX_BASE (0x40021000u) |
Peripheral DMAMUX base address
| #define DMAMUX_BASE_ADDRS { DMAMUX_BASE } |
Array initializer of DMAMUX peripheral base addresses
| #define DMAMUX_BASE_PTRS { DMAMUX } |
Array initializer of DMAMUX peripheral base pointers
| #define DMAMUX_CHCFG_ENBL | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
ENBL - DMA Channel Enable 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b1..DMA channel is enabled
| #define DMAMUX_CHCFG_ENBL | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
ENBL - DMA Channel Enable 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b1..DMA channel is enabled
| #define DMAMUX_CHCFG_ENBL | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
ENBL - DMA Channel Enable 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b1..DMA channel is enabled
| #define DMAMUX_CHCFG_ENBL | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
ENBL - DMA Channel Enable 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b1..DMA channel is enabled
| #define DMAMUX_CHCFG_ENBL | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
ENBL - DMA Channel Enable 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b1..DMA channel is enabled
| #define DMAMUX_CHCFG_SOURCE | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..UART2_Rx_Signal 0b000111..UART2_Tx_Signal 0b001000..UART3_Rx_Signal 0b001001..UART3_Tx_Signal 0b001010..UART4_Signal 0b001011..UART5_Signal 0b001100..I2S0_Rx_Signal 0b001101..I2S0_Tx_Signal 0b001110..SPI0_Rx_Signal 0b001111..SPI0_Tx_Signal 0b010000..SPI1_Signal 0b010001..SPI2_Signal 0b010010..I2C0_Signal 0b010011..I2C1_I2C2_Signal 0b010100..FTM0_Channel0_Signal 0b010101..FTM0_Channel1_Signal 0b010110..FTM0_Channel2_Signal 0b010111..FTM0_Channel3_Signal 0b011000..FTM0_Channel4_Signal 0b011001..FTM0_Channel5_Signal 0b011010..FTM0_Channel6_Signal 0b011011..FTM0_Channel7_Signal 0b011100..FTM1_Channel0_Signal 0b011101..FTM1_Channel1_Signal 0b011110..FTM2_Channel0_Signal 0b011111..FTM2_Channel1_Signal 0b100000..FTM3_Channel0_Signal 0b100001..FTM3_Channel1_Signal 0b100010..FTM3_Channel2_Signal 0b100011..FTM3_Channel3_Signal 0b100100..FTM3_Channel4_Signal 0b100101..FTM3_Channel5_Signal 0b100110..FTM3_Channel6_Signal 0b100111..FTM3_Channel7_Signal 0b101000..ADC0_Signal 0b101001..ADC1_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_Signal 0b101101..DAC0_Signal 0b101110..DAC1_Signal 0b101111..CMT_Signal 0b110000..PDB_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..IEEE1588Timer0_Signal 0b110111..IEEE1588Timer1_Signal 0b111000..IEEE1588Timer2_Signal 0b111001..IEEE1588Timer3_Signal 0b111010..AlwaysOn58_Signal 0b111011..AlwaysOn59_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000001..TSI0_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..UART2_Rx_Signal 0b000111..UART2_Tx_Signal 0b001000..UART3_Rx_Signal 0b001001..UART3_Tx_Signal 0b001010..UART4_Signal 0b001100..I2S0_Rx_Signal 0b001101..I2S0_Tx_Signal 0b001110..SPI0_Rx_Signal 0b001111..SPI0_Tx_Signal 0b010000..SPI1_Rx_Signal 0b010001..SPI1_Tx_Signal 0b010010..I2C0_I2C3_Signal 0b010011..I2C1_I2C2_Signal 0b010100..FTM0_Channel0_Signal 0b010101..FTM0_Channel1_Signal 0b010110..FTM0_Channel2_Signal 0b010111..FTM0_Channel3_Signal 0b011000..FTM0_Channel4_Signal 0b011001..FTM0_Channel5_Signal 0b011010..FTM0_Channel6_Signal 0b011011..FTM0_Channel7_Signal 0b011100..FTM1_TPM1_Channel0_Signal 0b011101..FTM1_TPM1_Channel1_Signal 0b011110..FTM2_TPM2_Channel0_Signal 0b011111..FTM2_TPM2_Channel1_Signal 0b100000..FTM3_Channel0_Signal 0b100001..FTM3_Channel1_Signal 0b100010..FTM3_Channel2_Signal 0b100011..FTM3_Channel3_Signal 0b100100..FTM3_Channel4_Signal 0b100101..FTM3_Channel5_Signal 0b100110..FTM3_Channel6_SPI2_Rx_Signal 0b100111..FTM3_Channel7_SPI2_Tx_Signal 0b101000..ADC0_Signal 0b101001..ADC1_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_CMP3_Signal 0b101101..DAC0_Signal 0b101110..DAC1_Signal 0b101111..CMT_Signal 0b110000..PDB_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..IEEE1588Timer0_Signal 0b110111..IEEE1588Timer1_TPM1_Overflow_Signal 0b111000..IEEE1588Timer2_TPM2_Overflow_Signal 0b111001..IEEE1588Timer3_Signal 0b111010..LPUART0_Rx_Signal 0b111011..LPUART0_Tx_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..PWM0_WR0_Signal 0b000111..PWM0_WR1_Signal 0b001000..PWM0_WR2_Signal 0b001001..PWM0_WR3_Signal 0b001010..PWM0_CP0_Signal 0b001011..PWM0_CP1_Signal 0b001100..PWM0_CP2_Signal 0b001101..PWM0_CP3_Signal 0b001110..CAN0_Signal 0b001111..CAN1_Signal 0b010000..SPI0_Rx_Signal 0b010001..SPI0_Tx_Signal 0b010010..XBARA_OUT_0_Signal 0b010011..XBARA_OUT_1_Signal 0b010100..XBARA_OUT_2_Signal 0b010101..XBARA_OUT_3_Signal 0b010110..I2C0_Signal 0b011000..FTM0_Channel0_Signal 0b011001..FTM0_Channel1_Signal 0b011010..FTM0_Channel2_Signal 0b011011..FTM0_Channel3_Signal 0b011100..FTM0_Channel4_Signal 0b011101..FTM0_Channel5_Signal 0b011110..FTM0_Channel6_Signal 0b011111..FTM0_Channel7_Signal 0b100000..FTM1_Channel0_Signal 0b100001..FTM1_Channel1_Signal 0b100010..CMP3_Signal 0b100100..FTM3_Channel0_Signal 0b100101..FTM3_Channel1_Signal 0b100110..FTM3_Channel2_Signal 0b100111..FTM3_Channel3_Signal 0b101000..HSADC0A_Signal 0b101001..HSADC0B_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_Signal 0b101101..DAC0_Signal 0b101111..PDB1_Signal 0b110000..PDB0_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..FTM3_Channel4_Signal 0b110111..FTM3_Channel5_Signal 0b111000..FTM3_Channel6_Signal 0b111001..FTM3_Channel7_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
| #define DMAMUX_CHCFG_SOURCE | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK) |
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..UART2_Rx_Signal 0b000111..UART2_Tx_Signal 0b001000..UART3_Rx_Signal 0b001001..UART3_Tx_Signal 0b001010..UART4_Signal 0b001011..UART5_Signal 0b001100..I2S0_Rx_Signal 0b001101..I2S0_Tx_Signal 0b001110..SPI0_Rx_Signal 0b001111..SPI0_Tx_Signal 0b010000..SPI1_Signal 0b010001..SPI2_Signal 0b010010..I2C0_Signal 0b010011..I2C1_I2C2_Signal 0b010100..FTM0_Channel0_Signal 0b010101..FTM0_Channel1_Signal 0b010110..FTM0_Channel2_Signal 0b010111..FTM0_Channel3_Signal 0b011000..FTM0_Channel4_Signal 0b011001..FTM0_Channel5_Signal 0b011010..FTM0_Channel6_Signal 0b011011..FTM0_Channel7_Signal 0b011100..FTM1_Channel0_Signal 0b011101..FTM1_Channel1_Signal 0b011110..FTM2_Channel0_Signal 0b011111..FTM2_Channel1_Signal 0b100000..FTM3_Channel0_Signal 0b100001..FTM3_Channel1_Signal 0b100010..FTM3_Channel2_Signal 0b100011..FTM3_Channel3_Signal 0b100100..FTM3_Channel4_Signal 0b100101..FTM3_Channel5_Signal 0b100110..FTM3_Channel6_Signal 0b100111..FTM3_Channel7_Signal 0b101000..ADC0_Signal 0b101001..ADC1_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_Signal 0b101101..DAC0_Signal 0b101110..DAC1_Signal 0b101111..CMT_Signal 0b110000..PDB_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..IEEE1588Timer0_Signal 0b110111..IEEE1588Timer1_Signal 0b111000..IEEE1588Timer2_Signal 0b111001..IEEE1588Timer3_Signal 0b111010..AlwaysOn58_Signal 0b111011..AlwaysOn59_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000001..TSI0_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..UART2_Rx_Signal 0b000111..UART2_Tx_Signal 0b001000..UART3_Rx_Signal 0b001001..UART3_Tx_Signal 0b001010..UART4_Signal 0b001100..I2S0_Rx_Signal 0b001101..I2S0_Tx_Signal 0b001110..SPI0_Rx_Signal 0b001111..SPI0_Tx_Signal 0b010000..SPI1_Rx_Signal 0b010001..SPI1_Tx_Signal 0b010010..I2C0_I2C3_Signal 0b010011..I2C1_I2C2_Signal 0b010100..FTM0_Channel0_Signal 0b010101..FTM0_Channel1_Signal 0b010110..FTM0_Channel2_Signal 0b010111..FTM0_Channel3_Signal 0b011000..FTM0_Channel4_Signal 0b011001..FTM0_Channel5_Signal 0b011010..FTM0_Channel6_Signal 0b011011..FTM0_Channel7_Signal 0b011100..FTM1_TPM1_Channel0_Signal 0b011101..FTM1_TPM1_Channel1_Signal 0b011110..FTM2_TPM2_Channel0_Signal 0b011111..FTM2_TPM2_Channel1_Signal 0b100000..FTM3_Channel0_Signal 0b100001..FTM3_Channel1_Signal 0b100010..FTM3_Channel2_Signal 0b100011..FTM3_Channel3_Signal 0b100100..FTM3_Channel4_Signal 0b100101..FTM3_Channel5_Signal 0b100110..FTM3_Channel6_SPI2_Rx_Signal 0b100111..FTM3_Channel7_SPI2_Tx_Signal 0b101000..ADC0_Signal 0b101001..ADC1_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_CMP3_Signal 0b101101..DAC0_Signal 0b101110..DAC1_Signal 0b101111..CMT_Signal 0b110000..PDB_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..IEEE1588Timer0_Signal 0b110111..IEEE1588Timer1_TPM1_Overflow_Signal 0b111000..IEEE1588Timer2_TPM2_Overflow_Signal 0b111001..IEEE1588Timer3_Signal 0b111010..LPUART0_Rx_Signal 0b111011..LPUART0_Tx_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..PWM0_WR0_Signal 0b000111..PWM0_WR1_Signal 0b001000..PWM0_WR2_Signal 0b001001..PWM0_WR3_Signal 0b001010..PWM0_CP0_Signal 0b001011..PWM0_CP1_Signal 0b001100..PWM0_CP2_Signal 0b001101..PWM0_CP3_Signal 0b001110..CAN0_Signal 0b001111..CAN1_Signal 0b010000..SPI0_Rx_Signal 0b010001..SPI0_Tx_Signal 0b010010..XBARA_OUT_0_Signal 0b010011..XBARA_OUT_1_Signal 0b010100..XBARA_OUT_2_Signal 0b010101..XBARA_OUT_3_Signal 0b010110..I2C0_Signal 0b011000..FTM0_Channel0_Signal 0b011001..FTM0_Channel1_Signal 0b011010..FTM0_Channel2_Signal 0b011011..FTM0_Channel3_Signal 0b011100..FTM0_Channel4_Signal 0b011101..FTM0_Channel5_Signal 0b011110..FTM0_Channel6_Signal 0b011111..FTM0_Channel7_Signal 0b100000..FTM1_Channel0_Signal 0b100001..FTM1_Channel1_Signal 0b100010..CMP3_Signal 0b100100..FTM3_Channel0_Signal 0b100101..FTM3_Channel1_Signal 0b100110..FTM3_Channel2_Signal 0b100111..FTM3_Channel3_Signal 0b101000..HSADC0A_Signal 0b101001..HSADC0B_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_Signal 0b101101..DAC0_Signal 0b101111..PDB1_Signal 0b110000..PDB0_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..FTM3_Channel4_Signal 0b110111..FTM3_Channel5_Signal 0b111000..FTM3_Channel6_Signal 0b111001..FTM3_Channel7_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
| #define DMAMUX_CHCFG_SOURCE | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..UART2_Rx_Signal 0b000111..UART2_Tx_Signal 0b001000..UART3_Rx_Signal 0b001001..UART3_Tx_Signal 0b001010..UART4_Signal 0b001011..UART5_Signal 0b001100..I2S0_Rx_Signal 0b001101..I2S0_Tx_Signal 0b001110..SPI0_Rx_Signal 0b001111..SPI0_Tx_Signal 0b010000..SPI1_Signal 0b010001..SPI2_Signal 0b010010..I2C0_Signal 0b010011..I2C1_I2C2_Signal 0b010100..FTM0_Channel0_Signal 0b010101..FTM0_Channel1_Signal 0b010110..FTM0_Channel2_Signal 0b010111..FTM0_Channel3_Signal 0b011000..FTM0_Channel4_Signal 0b011001..FTM0_Channel5_Signal 0b011010..FTM0_Channel6_Signal 0b011011..FTM0_Channel7_Signal 0b011100..FTM1_Channel0_Signal 0b011101..FTM1_Channel1_Signal 0b011110..FTM2_Channel0_Signal 0b011111..FTM2_Channel1_Signal 0b100000..FTM3_Channel0_Signal 0b100001..FTM3_Channel1_Signal 0b100010..FTM3_Channel2_Signal 0b100011..FTM3_Channel3_Signal 0b100100..FTM3_Channel4_Signal 0b100101..FTM3_Channel5_Signal 0b100110..FTM3_Channel6_Signal 0b100111..FTM3_Channel7_Signal 0b101000..ADC0_Signal 0b101001..ADC1_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_Signal 0b101101..DAC0_Signal 0b101110..DAC1_Signal 0b101111..CMT_Signal 0b110000..PDB_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..IEEE1588Timer0_Signal 0b110111..IEEE1588Timer1_Signal 0b111000..IEEE1588Timer2_Signal 0b111001..IEEE1588Timer3_Signal 0b111010..AlwaysOn58_Signal 0b111011..AlwaysOn59_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000001..TSI0_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..UART2_Rx_Signal 0b000111..UART2_Tx_Signal 0b001000..UART3_Rx_Signal 0b001001..UART3_Tx_Signal 0b001010..UART4_Signal 0b001100..I2S0_Rx_Signal 0b001101..I2S0_Tx_Signal 0b001110..SPI0_Rx_Signal 0b001111..SPI0_Tx_Signal 0b010000..SPI1_Rx_Signal 0b010001..SPI1_Tx_Signal 0b010010..I2C0_I2C3_Signal 0b010011..I2C1_I2C2_Signal 0b010100..FTM0_Channel0_Signal 0b010101..FTM0_Channel1_Signal 0b010110..FTM0_Channel2_Signal 0b010111..FTM0_Channel3_Signal 0b011000..FTM0_Channel4_Signal 0b011001..FTM0_Channel5_Signal 0b011010..FTM0_Channel6_Signal 0b011011..FTM0_Channel7_Signal 0b011100..FTM1_TPM1_Channel0_Signal 0b011101..FTM1_TPM1_Channel1_Signal 0b011110..FTM2_TPM2_Channel0_Signal 0b011111..FTM2_TPM2_Channel1_Signal 0b100000..FTM3_Channel0_Signal 0b100001..FTM3_Channel1_Signal 0b100010..FTM3_Channel2_Signal 0b100011..FTM3_Channel3_Signal 0b100100..FTM3_Channel4_Signal 0b100101..FTM3_Channel5_Signal 0b100110..FTM3_Channel6_SPI2_Rx_Signal 0b100111..FTM3_Channel7_SPI2_Tx_Signal 0b101000..ADC0_Signal 0b101001..ADC1_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_CMP3_Signal 0b101101..DAC0_Signal 0b101110..DAC1_Signal 0b101111..CMT_Signal 0b110000..PDB_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..IEEE1588Timer0_Signal 0b110111..IEEE1588Timer1_TPM1_Overflow_Signal 0b111000..IEEE1588Timer2_TPM2_Overflow_Signal 0b111001..IEEE1588Timer3_Signal 0b111010..LPUART0_Rx_Signal 0b111011..LPUART0_Tx_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..PWM0_WR0_Signal 0b000111..PWM0_WR1_Signal 0b001000..PWM0_WR2_Signal 0b001001..PWM0_WR3_Signal 0b001010..PWM0_CP0_Signal 0b001011..PWM0_CP1_Signal 0b001100..PWM0_CP2_Signal 0b001101..PWM0_CP3_Signal 0b001110..CAN0_Signal 0b001111..CAN1_Signal 0b010000..SPI0_Rx_Signal 0b010001..SPI0_Tx_Signal 0b010010..XBARA_OUT_0_Signal 0b010011..XBARA_OUT_1_Signal 0b010100..XBARA_OUT_2_Signal 0b010101..XBARA_OUT_3_Signal 0b010110..I2C0_Signal 0b011000..FTM0_Channel0_Signal 0b011001..FTM0_Channel1_Signal 0b011010..FTM0_Channel2_Signal 0b011011..FTM0_Channel3_Signal 0b011100..FTM0_Channel4_Signal 0b011101..FTM0_Channel5_Signal 0b011110..FTM0_Channel6_Signal 0b011111..FTM0_Channel7_Signal 0b100000..FTM1_Channel0_Signal 0b100001..FTM1_Channel1_Signal 0b100010..CMP3_Signal 0b100100..FTM3_Channel0_Signal 0b100101..FTM3_Channel1_Signal 0b100110..FTM3_Channel2_Signal 0b100111..FTM3_Channel3_Signal 0b101000..HSADC0A_Signal 0b101001..HSADC0B_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_Signal 0b101101..DAC0_Signal 0b101111..PDB1_Signal 0b110000..PDB0_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..FTM3_Channel4_Signal 0b110111..FTM3_Channel5_Signal 0b111000..FTM3_Channel6_Signal 0b111001..FTM3_Channel7_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
| #define DMAMUX_CHCFG_SOURCE | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000001..TSI0_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..UART2_Rx_Signal 0b000111..UART2_Tx_Signal 0b001000..UART3_Rx_Signal 0b001001..UART3_Tx_Signal 0b001010..UART4_Signal 0b001100..I2S0_Rx_Signal 0b001101..I2S0_Tx_Signal 0b001110..SPI0_Rx_Signal 0b001111..SPI0_Tx_Signal 0b010000..SPI1_Rx_Signal 0b010001..SPI1_Tx_Signal 0b010010..I2C0_I2C3_Signal 0b010011..I2C1_I2C2_Signal 0b010100..FTM0_Channel0_Signal 0b010101..FTM0_Channel1_Signal 0b010110..FTM0_Channel2_Signal 0b010111..FTM0_Channel3_Signal 0b011000..FTM0_Channel4_Signal 0b011001..FTM0_Channel5_Signal 0b011010..FTM0_Channel6_Signal 0b011011..FTM0_Channel7_Signal 0b011100..FTM1_TPM1_Channel0_Signal 0b011101..FTM1_TPM1_Channel1_Signal 0b011110..FTM2_TPM2_Channel0_Signal 0b011111..FTM2_TPM2_Channel1_Signal 0b100000..FTM3_Channel0_Signal 0b100001..FTM3_Channel1_Signal 0b100010..FTM3_Channel2_Signal 0b100011..FTM3_Channel3_Signal 0b100100..FTM3_Channel4_Signal 0b100101..FTM3_Channel5_Signal 0b100110..FTM3_Channel6_SPI2_Rx_Signal 0b100111..FTM3_Channel7_SPI2_Tx_Signal 0b101000..ADC0_Signal 0b101001..ADC1_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_CMP3_Signal 0b101101..DAC0_Signal 0b101110..DAC1_Signal 0b101111..CMT_Signal 0b110000..PDB_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..IEEE1588Timer0_Signal 0b110111..IEEE1588Timer1_TPM1_Overflow_Signal 0b111000..IEEE1588Timer2_TPM2_Overflow_Signal 0b111001..IEEE1588Timer3_Signal 0b111010..LPUART0_Rx_Signal 0b111011..LPUART0_Tx_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..PWM0_WR0_Signal 0b000111..PWM0_WR1_Signal 0b001000..PWM0_WR2_Signal 0b001001..PWM0_WR3_Signal 0b001010..PWM0_CP0_Signal 0b001011..PWM0_CP1_Signal 0b001100..PWM0_CP2_Signal 0b001101..PWM0_CP3_Signal 0b001110..CAN0_Signal 0b001111..CAN1_Signal 0b010000..SPI0_Rx_Signal 0b010001..SPI0_Tx_Signal 0b010010..XBARA_OUT_0_Signal 0b010011..XBARA_OUT_1_Signal 0b010100..XBARA_OUT_2_Signal 0b010101..XBARA_OUT_3_Signal 0b010110..I2C0_Signal 0b011000..FTM0_Channel0_Signal 0b011001..FTM0_Channel1_Signal 0b011010..FTM0_Channel2_Signal 0b011011..FTM0_Channel3_Signal 0b011100..FTM0_Channel4_Signal 0b011101..FTM0_Channel5_Signal 0b011110..FTM0_Channel6_Signal 0b011111..FTM0_Channel7_Signal 0b100000..FTM1_Channel0_Signal 0b100001..FTM1_Channel1_Signal 0b100010..CMP3_Signal 0b100100..FTM3_Channel0_Signal 0b100101..FTM3_Channel1_Signal 0b100110..FTM3_Channel2_Signal 0b100111..FTM3_Channel3_Signal 0b101000..HSADC0A_Signal 0b101001..HSADC0B_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_Signal 0b101101..DAC0_Signal 0b101111..PDB1_Signal 0b110000..PDB0_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..FTM3_Channel4_Signal 0b110111..FTM3_Channel5_Signal 0b111000..FTM3_Channel6_Signal 0b111001..FTM3_Channel7_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
| #define DMAMUX_CHCFG_SOURCE | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000001..TSI0_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..UART2_Rx_Signal 0b000111..UART2_Tx_Signal 0b001000..UART3_Rx_Signal 0b001001..UART3_Tx_Signal 0b001010..UART4_Signal 0b001100..I2S0_Rx_Signal 0b001101..I2S0_Tx_Signal 0b001110..SPI0_Rx_Signal 0b001111..SPI0_Tx_Signal 0b010000..SPI1_Rx_Signal 0b010001..SPI1_Tx_Signal 0b010010..I2C0_I2C3_Signal 0b010011..I2C1_I2C2_Signal 0b010100..FTM0_Channel0_Signal 0b010101..FTM0_Channel1_Signal 0b010110..FTM0_Channel2_Signal 0b010111..FTM0_Channel3_Signal 0b011000..FTM0_Channel4_Signal 0b011001..FTM0_Channel5_Signal 0b011010..FTM0_Channel6_Signal 0b011011..FTM0_Channel7_Signal 0b011100..FTM1_TPM1_Channel0_Signal 0b011101..FTM1_TPM1_Channel1_Signal 0b011110..FTM2_TPM2_Channel0_Signal 0b011111..FTM2_TPM2_Channel1_Signal 0b100000..FTM3_Channel0_Signal 0b100001..FTM3_Channel1_Signal 0b100010..FTM3_Channel2_Signal 0b100011..FTM3_Channel3_Signal 0b100100..FTM3_Channel4_Signal 0b100101..FTM3_Channel5_Signal 0b100110..FTM3_Channel6_SPI2_Rx_Signal 0b100111..FTM3_Channel7_SPI2_Tx_Signal 0b101000..ADC0_Signal 0b101001..ADC1_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_CMP3_Signal 0b101101..DAC0_Signal 0b101110..DAC1_Signal 0b101111..CMT_Signal 0b110000..PDB_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..IEEE1588Timer0_Signal 0b110111..IEEE1588Timer1_TPM1_Overflow_Signal 0b111000..IEEE1588Timer2_TPM2_Overflow_Signal 0b111001..IEEE1588Timer3_Signal 0b111010..LPUART0_Rx_Signal 0b111011..LPUART0_Tx_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..PWM0_WR0_Signal 0b000111..PWM0_WR1_Signal 0b001000..PWM0_WR2_Signal 0b001001..PWM0_WR3_Signal 0b001010..PWM0_CP0_Signal 0b001011..PWM0_CP1_Signal 0b001100..PWM0_CP2_Signal 0b001101..PWM0_CP3_Signal 0b001110..CAN0_Signal 0b001111..CAN1_Signal 0b010000..SPI0_Rx_Signal 0b010001..SPI0_Tx_Signal 0b010010..XBARA_OUT_0_Signal 0b010011..XBARA_OUT_1_Signal 0b010100..XBARA_OUT_2_Signal 0b010101..XBARA_OUT_3_Signal 0b010110..I2C0_Signal 0b011000..FTM0_Channel0_Signal 0b011001..FTM0_Channel1_Signal 0b011010..FTM0_Channel2_Signal 0b011011..FTM0_Channel3_Signal 0b011100..FTM0_Channel4_Signal 0b011101..FTM0_Channel5_Signal 0b011110..FTM0_Channel6_Signal 0b011111..FTM0_Channel7_Signal 0b100000..FTM1_Channel0_Signal 0b100001..FTM1_Channel1_Signal 0b100010..CMP3_Signal 0b100100..FTM3_Channel0_Signal 0b100101..FTM3_Channel1_Signal 0b100110..FTM3_Channel2_Signal 0b100111..FTM3_Channel3_Signal 0b101000..HSADC0A_Signal 0b101001..HSADC0B_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_Signal 0b101101..DAC0_Signal 0b101111..PDB1_Signal 0b110000..PDB0_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..FTM3_Channel4_Signal 0b110111..FTM3_Channel5_Signal 0b111000..FTM3_Channel6_Signal 0b111001..FTM3_Channel7_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
| #define DMAMUX_CHCFG_SOURCE | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
SOURCE - DMA Channel Source (Slot) 0b000000..Disable_Signal 0b000010..UART0_Rx_Signal 0b000011..UART0_Tx_Signal 0b000100..UART1_Rx_Signal 0b000101..UART1_Tx_Signal 0b000110..PWM0_WR0_Signal 0b000111..PWM0_WR1_Signal 0b001000..PWM0_WR2_Signal 0b001001..PWM0_WR3_Signal 0b001010..PWM0_CP0_Signal 0b001011..PWM0_CP1_Signal 0b001100..PWM0_CP2_Signal 0b001101..PWM0_CP3_Signal 0b001110..CAN0_Signal 0b001111..CAN1_Signal 0b010000..SPI0_Rx_Signal 0b010001..SPI0_Tx_Signal 0b010010..XBARA_OUT_0_Signal 0b010011..XBARA_OUT_1_Signal 0b010100..XBARA_OUT_2_Signal 0b010101..XBARA_OUT_3_Signal 0b010110..I2C0_Signal 0b011000..FTM0_Channel0_Signal 0b011001..FTM0_Channel1_Signal 0b011010..FTM0_Channel2_Signal 0b011011..FTM0_Channel3_Signal 0b011100..FTM0_Channel4_Signal 0b011101..FTM0_Channel5_Signal 0b011110..FTM0_Channel6_Signal 0b011111..FTM0_Channel7_Signal 0b100000..FTM1_Channel0_Signal 0b100001..FTM1_Channel1_Signal 0b100010..CMP3_Signal 0b100100..FTM3_Channel0_Signal 0b100101..FTM3_Channel1_Signal 0b100110..FTM3_Channel2_Signal 0b100111..FTM3_Channel3_Signal 0b101000..HSADC0A_Signal 0b101001..HSADC0B_Signal 0b101010..CMP0_Signal 0b101011..CMP1_Signal 0b101100..CMP2_Signal 0b101101..DAC0_Signal 0b101111..PDB1_Signal 0b110000..PDB0_Signal 0b110001..PortA_Signal 0b110010..PortB_Signal 0b110011..PortC_Signal 0b110100..PortD_Signal 0b110101..PortE_Signal 0b110110..FTM3_Channel4_Signal 0b110111..FTM3_Channel5_Signal 0b111000..FTM3_Channel6_Signal 0b111001..FTM3_Channel7_Signal 0b111100..AlwaysOn60_Signal 0b111101..AlwaysOn61_Signal 0b111110..AlwaysOn62_Signal 0b111111..AlwaysOn63_Signal
| #define DMAMUX_CHCFG_TRIG | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
TRIG - DMA Channel Trigger Enable 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
| #define DMAMUX_CHCFG_TRIG | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
TRIG - DMA Channel Trigger Enable 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
| #define DMAMUX_CHCFG_TRIG | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
TRIG - DMA Channel Trigger Enable 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
| #define DMAMUX_CHCFG_TRIG | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
TRIG - DMA Channel Trigger Enable 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
| #define DMAMUX_CHCFG_TRIG | ( | x | ) | (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
TRIG - DMA Channel Trigger Enable 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.