DMA Peripheral Access Layer

Topics
	DMA Register Masks
	DMAMUX Peripheral Access Layer

Data Structures
struct	DMA_Type

Macros
#define	DMA_BASE   (0x40008000u)
#define	DMA   ((DMA_Type *)DMA_BASE)
#define	DMA_BASE   (0x40008000u)
#define	DMA0   ((DMA_Type *)DMA_BASE)
#define	DMA_BASE_ADDRS   { DMA_BASE }
#define	DMA_BASE_PTRS   { DMA0 }
#define	DMA_CHN_IRQS   { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }
#define	DMA_ERROR_IRQS   { DMA_Error_IRQn }
#define	DMA_BASE   (0x40008000u)
#define	DMA0   ((DMA_Type *)DMA_BASE)
#define	DMA_BASE_ADDRS   { DMA_BASE }
#define	DMA_BASE_PTRS   { DMA0 }
#define	DMA_CHN_IRQS   { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
#define	DMA_ERROR_IRQS   { DMA_Error_IRQn }
#define	DMA_BASE   (0x40008000u)
#define	DMA0   ((DMA_Type *)DMA_BASE)
#define	DMA_BASE_ADDRS   { DMA_BASE }
#define	DMA_BASE_PTRS   { DMA0 }
#define	DMA_CHN_IRQS   { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
#define	DMA_ERROR_IRQS   { DMA_Error_IRQn }
#define	DMA_BASE   (0x40008000u)
#define	DMA0   ((DMA_Type *)DMA_BASE)
#define	DMA_BASE_ADDRS   { DMA_BASE }
#define	DMA_BASE_PTRS   { DMA0 }
#define	DMA_CHN_IRQS   { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
#define	DMA_ERROR_IRQS   { DMA_Error_IRQn }

Macro Definition Documentation

DMA

#define DMA   ((DMA_Type *)DMA_BASE)

Peripheral DMA base pointer

DMA0 [1/4]

#define DMA0   ((DMA_Type *)DMA_BASE)

Peripheral DMA base pointer

DMA0 [2/4]

#define DMA0   ((DMA_Type *)DMA_BASE)

Peripheral DMA base pointer

DMA0 [3/4]

#define DMA0   ((DMA_Type *)DMA_BASE)

Peripheral DMA base pointer

DMA0 [4/4]

#define DMA0   ((DMA_Type *)DMA_BASE)

Peripheral DMA base pointer

DMA_BASE [1/5]

#define DMA_BASE   (0x40008000u)

Peripheral DMA base address

DMA_BASE [2/5]

#define DMA_BASE   (0x40008000u)

Peripheral DMA base address

DMA_BASE [3/5]

#define DMA_BASE   (0x40008000u)

Peripheral DMA base address

DMA_BASE [4/5]

#define DMA_BASE   (0x40008000u)

Peripheral DMA base address

DMA_BASE [5/5]

#define DMA_BASE   (0x40008000u)

Peripheral DMA base address

DMA_BASE_ADDRS [1/4]

#define DMA_BASE_ADDRS   { DMA_BASE }

Array initializer of DMA peripheral base addresses

DMA_BASE_ADDRS [2/4]

#define DMA_BASE_ADDRS   { DMA_BASE }

Array initializer of DMA peripheral base addresses

DMA_BASE_ADDRS [3/4]

#define DMA_BASE_ADDRS   { DMA_BASE }

Array initializer of DMA peripheral base addresses

DMA_BASE_ADDRS [4/4]

#define DMA_BASE_ADDRS   { DMA_BASE }

Array initializer of DMA peripheral base addresses

DMA_BASE_PTRS [1/4]

#define DMA_BASE_PTRS   { DMA0 }

Array initializer of DMA peripheral base pointers

DMA_BASE_PTRS [2/4]

#define DMA_BASE_PTRS   { DMA0 }

Array initializer of DMA peripheral base pointers

DMA_BASE_PTRS [3/4]

#define DMA_BASE_PTRS   { DMA0 }

Array initializer of DMA peripheral base pointers

DMA_BASE_PTRS [4/4]

#define DMA_BASE_PTRS   { DMA0 }

Array initializer of DMA peripheral base pointers

DMA_CHN_IRQS [1/4]

#define DMA_CHN_IRQS   { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }

Interrupt vectors for the DMA peripheral type

DMA_CHN_IRQS [2/4]

#define DMA_CHN_IRQS   { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }

Interrupt vectors for the DMA peripheral type

DMA_CHN_IRQS [3/4]

#define DMA_CHN_IRQS   { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }

Interrupt vectors for the DMA peripheral type

DMA_CHN_IRQS [4/4]

#define DMA_CHN_IRQS   { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }

Interrupt vectors for the DMA peripheral type