Macros
#define	DMA_BASE (0x40008000u)

#define	DMA0 ((DMA_Type *)DMA_BASE)

#define	DMA_BASE_ADDRS { DMA_BASE }

#define	DMA_BASE_PTRS { DMA0 }

#define	DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }

#define	DMA_ERROR_IRQS { DMA_Error_IRQn }

#define	DMA_SADDR_COUNT (16U)

#define	DMA_SOFF_COUNT (16U)

#define	DMA_ATTR_COUNT (16U)

#define	DMA_NBYTES_MLNO_COUNT (16U)

#define	DMA_NBYTES_MLOFFNO_COUNT (16U)

#define	DMA_NBYTES_MLOFFYES_COUNT (16U)

#define	DMA_SLAST_COUNT (16U)

#define	DMA_DADDR_COUNT (16U)

#define	DMA_DOFF_COUNT (16U)

#define	DMA_CITER_ELINKNO_COUNT (16U)

#define	DMA_CITER_ELINKYES_COUNT (16U)

#define	DMA_DLAST_SGA_COUNT (16U)

#define	DMA_CSR_COUNT (16U)

#define	DMA_BITER_ELINKNO_COUNT (16U)

#define	DMA_BITER_ELINKYES_COUNT (16U)

#define	DMA_SADDR_COUNT (32U)

#define	DMA_SOFF_COUNT (32U)

#define	DMA_ATTR_COUNT (32U)

#define	DMA_NBYTES_MLNO_COUNT (32U)

#define	DMA_NBYTES_MLOFFNO_COUNT (32U)

#define	DMA_NBYTES_MLOFFYES_COUNT (32U)

#define	DMA_SLAST_COUNT (32U)

#define	DMA_DADDR_COUNT (32U)

#define	DMA_DOFF_COUNT (32U)

#define	DMA_CITER_ELINKNO_COUNT (32U)

#define	DMA_CITER_ELINKYES_COUNT (32U)

#define	DMA_DLAST_SGA_COUNT (32U)

#define	DMA_CSR_COUNT (32U)

#define	DMA_BITER_ELINKNO_COUNT (32U)

#define	DMA_BITER_ELINKYES_COUNT (32U)

#define	DMA_SADDR_COUNT (32U)

#define	DMA_SOFF_COUNT (32U)

#define	DMA_ATTR_COUNT (32U)

#define	DMA_NBYTES_MLNO_COUNT (32U)

#define	DMA_NBYTES_MLOFFNO_COUNT (32U)

#define	DMA_NBYTES_MLOFFYES_COUNT (32U)

#define	DMA_SLAST_COUNT (32U)

#define	DMA_DADDR_COUNT (32U)

#define	DMA_DOFF_COUNT (32U)

#define	DMA_CITER_ELINKNO_COUNT (32U)

#define	DMA_CITER_ELINKYES_COUNT (32U)

#define	DMA_DLAST_SGA_COUNT (32U)

#define	DMA_CSR_COUNT (32U)

#define	DMA_BITER_ELINKNO_COUNT (32U)

#define	DMA_BITER_ELINKYES_COUNT (32U)

#define	DMA_SADDR_COUNT (32U)

#define	DMA_SOFF_COUNT (32U)

#define	DMA_ATTR_COUNT (32U)

#define	DMA_NBYTES_MLNO_COUNT (32U)

#define	DMA_NBYTES_MLOFFNO_COUNT (32U)

#define	DMA_NBYTES_MLOFFYES_COUNT (32U)

#define	DMA_SLAST_COUNT (32U)

#define	DMA_DADDR_COUNT (32U)

#define	DMA_DOFF_COUNT (32U)

#define	DMA_CITER_ELINKNO_COUNT (32U)

#define	DMA_CITER_ELINKYES_COUNT (32U)

#define	DMA_DLAST_SGA_COUNT (32U)

#define	DMA_CSR_COUNT (32U)

#define	DMA_BITER_ELINKNO_COUNT (32U)

#define	DMA_BITER_ELINKYES_COUNT (32U)

CR - Control Register
#define	DMA_CR_EDBG_MASK (0x2U)

#define	DMA_CR_EDBG_SHIFT (1U)

#define	DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

#define	DMA_CR_ERCA_MASK (0x4U)

#define	DMA_CR_ERCA_SHIFT (2U)

#define	DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

#define	DMA_CR_HOE_MASK (0x10U)

#define	DMA_CR_HOE_SHIFT (4U)

#define	DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

#define	DMA_CR_HALT_MASK (0x20U)

#define	DMA_CR_HALT_SHIFT (5U)

#define	DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

#define	DMA_CR_CLM_MASK (0x40U)

#define	DMA_CR_CLM_SHIFT (6U)

#define	DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

#define	DMA_CR_EMLM_MASK (0x80U)

#define	DMA_CR_EMLM_SHIFT (7U)

#define	DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

#define	DMA_CR_ECX_MASK (0x10000U)

#define	DMA_CR_ECX_SHIFT (16U)

#define	DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

#define	DMA_CR_CX_MASK (0x20000U)

#define	DMA_CR_CX_SHIFT (17U)

#define	DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

#define	DMA_CR_EDBG_MASK 0x2u

#define	DMA_CR_EDBG_SHIFT 1

#define	DMA_CR_ERCA_MASK 0x4u

#define	DMA_CR_ERCA_SHIFT 2

#define	DMA_CR_HOE_MASK 0x10u

#define	DMA_CR_HOE_SHIFT 4

#define	DMA_CR_HALT_MASK 0x20u

#define	DMA_CR_HALT_SHIFT 5

#define	DMA_CR_CLM_MASK 0x40u

#define	DMA_CR_CLM_SHIFT 6

#define	DMA_CR_EMLM_MASK 0x80u

#define	DMA_CR_EMLM_SHIFT 7

#define	DMA_CR_ECX_MASK 0x10000u

#define	DMA_CR_ECX_SHIFT 16

#define	DMA_CR_CX_MASK 0x20000u

#define	DMA_CR_CX_SHIFT 17

#define	DMA_CR_EDBG_MASK (0x2U)

#define	DMA_CR_EDBG_SHIFT (1U)

#define	DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

#define	DMA_CR_ERCA_MASK (0x4U)

#define	DMA_CR_ERCA_SHIFT (2U)

#define	DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

#define	DMA_CR_HOE_MASK (0x10U)

#define	DMA_CR_HOE_SHIFT (4U)

#define	DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

#define	DMA_CR_HALT_MASK (0x20U)

#define	DMA_CR_HALT_SHIFT (5U)

#define	DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

#define	DMA_CR_CLM_MASK (0x40U)

#define	DMA_CR_CLM_SHIFT (6U)

#define	DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

#define	DMA_CR_EMLM_MASK (0x80U)

#define	DMA_CR_EMLM_SHIFT (7U)

#define	DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

#define	DMA_CR_ECX_MASK (0x10000U)

#define	DMA_CR_ECX_SHIFT (16U)

#define	DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

#define	DMA_CR_CX_MASK (0x20000U)

#define	DMA_CR_CX_SHIFT (17U)

#define	DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

#define	DMA_CR_EDBG_MASK (0x2U)

#define	DMA_CR_EDBG_SHIFT (1U)

#define	DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

#define	DMA_CR_ERCA_MASK (0x4U)

#define	DMA_CR_ERCA_SHIFT (2U)

#define	DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

#define	DMA_CR_ERGA_MASK (0x8U)

#define	DMA_CR_ERGA_SHIFT (3U)

#define	DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

#define	DMA_CR_HOE_MASK (0x10U)

#define	DMA_CR_HOE_SHIFT (4U)

#define	DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

#define	DMA_CR_HALT_MASK (0x20U)

#define	DMA_CR_HALT_SHIFT (5U)

#define	DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

#define	DMA_CR_CLM_MASK (0x40U)

#define	DMA_CR_CLM_SHIFT (6U)

#define	DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

#define	DMA_CR_EMLM_MASK (0x80U)

#define	DMA_CR_EMLM_SHIFT (7U)

#define	DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

#define	DMA_CR_GRP0PRI_MASK (0x100U)

#define	DMA_CR_GRP0PRI_SHIFT (8U)

#define	DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)

#define	DMA_CR_GRP1PRI_MASK (0x400U)

#define	DMA_CR_GRP1PRI_SHIFT (10U)

#define	DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)

#define	DMA_CR_ECX_MASK (0x10000U)

#define	DMA_CR_ECX_SHIFT (16U)

#define	DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

#define	DMA_CR_CX_MASK (0x20000U)

#define	DMA_CR_CX_SHIFT (17U)

#define	DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

#define	DMA_CR_EDBG_MASK (0x2U)

#define	DMA_CR_EDBG_SHIFT (1U)

#define	DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

#define	DMA_CR_ERCA_MASK (0x4U)

#define	DMA_CR_ERCA_SHIFT (2U)

#define	DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

#define	DMA_CR_ERGA_MASK (0x8U)

#define	DMA_CR_ERGA_SHIFT (3U)

#define	DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

#define	DMA_CR_HOE_MASK (0x10U)

#define	DMA_CR_HOE_SHIFT (4U)

#define	DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

#define	DMA_CR_HALT_MASK (0x20U)

#define	DMA_CR_HALT_SHIFT (5U)

#define	DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

#define	DMA_CR_CLM_MASK (0x40U)

#define	DMA_CR_CLM_SHIFT (6U)

#define	DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

#define	DMA_CR_EMLM_MASK (0x80U)

#define	DMA_CR_EMLM_SHIFT (7U)

#define	DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

#define	DMA_CR_GRP0PRI_MASK (0x100U)

#define	DMA_CR_GRP0PRI_SHIFT (8U)

#define	DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)

#define	DMA_CR_GRP1PRI_MASK (0x400U)

#define	DMA_CR_GRP1PRI_SHIFT (10U)

#define	DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)

#define	DMA_CR_ECX_MASK (0x10000U)

#define	DMA_CR_ECX_SHIFT (16U)

#define	DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

#define	DMA_CR_CX_MASK (0x20000U)

#define	DMA_CR_CX_SHIFT (17U)

#define	DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

#define	DMA_CR_EDBG_MASK (0x2U)

#define	DMA_CR_EDBG_SHIFT (1U)

#define	DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

#define	DMA_CR_ERCA_MASK (0x4U)

#define	DMA_CR_ERCA_SHIFT (2U)

#define	DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

#define	DMA_CR_ERGA_MASK (0x8U)

#define	DMA_CR_ERGA_SHIFT (3U)

#define	DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

#define	DMA_CR_HOE_MASK (0x10U)

#define	DMA_CR_HOE_SHIFT (4U)

#define	DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

#define	DMA_CR_HALT_MASK (0x20U)

#define	DMA_CR_HALT_SHIFT (5U)

#define	DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

#define	DMA_CR_CLM_MASK (0x40U)

#define	DMA_CR_CLM_SHIFT (6U)

#define	DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

#define	DMA_CR_EMLM_MASK (0x80U)

#define	DMA_CR_EMLM_SHIFT (7U)

#define	DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

#define	DMA_CR_GRP0PRI_MASK (0x100U)

#define	DMA_CR_GRP0PRI_SHIFT (8U)

#define	DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)

#define	DMA_CR_GRP1PRI_MASK (0x400U)

#define	DMA_CR_GRP1PRI_SHIFT (10U)

#define	DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)

#define	DMA_CR_ECX_MASK (0x10000U)

#define	DMA_CR_ECX_SHIFT (16U)

#define	DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

#define	DMA_CR_CX_MASK (0x20000U)

#define	DMA_CR_CX_SHIFT (17U)

#define	DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

#define	MCM_CR_AHBSPRI_MASK (0x8000000U)

#define	MCM_CR_AHBSPRI_SHIFT (27U)

#define	MCM_CR_AHBSPRI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_AHBSPRI_SHIFT)) & MCM_CR_AHBSPRI_MASK)

ES - Error Status Register
#define	DMA_ES_DBE_MASK (0x1U)

#define	DMA_ES_DBE_SHIFT (0U)

#define	DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

#define	DMA_ES_SBE_MASK (0x2U)

#define	DMA_ES_SBE_SHIFT (1U)

#define	DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

#define	DMA_ES_SGE_MASK (0x4U)

#define	DMA_ES_SGE_SHIFT (2U)

#define	DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

#define	DMA_ES_NCE_MASK (0x8U)

#define	DMA_ES_NCE_SHIFT (3U)

#define	DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

#define	DMA_ES_DOE_MASK (0x10U)

#define	DMA_ES_DOE_SHIFT (4U)

#define	DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

#define	DMA_ES_DAE_MASK (0x20U)

#define	DMA_ES_DAE_SHIFT (5U)

#define	DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

#define	DMA_ES_SOE_MASK (0x40U)

#define	DMA_ES_SOE_SHIFT (6U)

#define	DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

#define	DMA_ES_SAE_MASK (0x80U)

#define	DMA_ES_SAE_SHIFT (7U)

#define	DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

#define	DMA_ES_ERRCHN_MASK (0xF00U)

#define	DMA_ES_ERRCHN_SHIFT (8U)

#define	DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

#define	DMA_ES_CPE_MASK (0x4000U)

#define	DMA_ES_CPE_SHIFT (14U)

#define	DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

#define	DMA_ES_ECX_MASK (0x10000U)

#define	DMA_ES_ECX_SHIFT (16U)

#define	DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

#define	DMA_ES_VLD_MASK (0x80000000U)

#define	DMA_ES_VLD_SHIFT (31U)

#define	DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

#define	DMA_ES_DBE_MASK 0x1u

#define	DMA_ES_DBE_SHIFT 0

#define	DMA_ES_SBE_MASK 0x2u

#define	DMA_ES_SBE_SHIFT 1

#define	DMA_ES_SGE_MASK 0x4u

#define	DMA_ES_SGE_SHIFT 2

#define	DMA_ES_NCE_MASK 0x8u

#define	DMA_ES_NCE_SHIFT 3

#define	DMA_ES_DOE_MASK 0x10u

#define	DMA_ES_DOE_SHIFT 4

#define	DMA_ES_DAE_MASK 0x20u

#define	DMA_ES_DAE_SHIFT 5

#define	DMA_ES_SOE_MASK 0x40u

#define	DMA_ES_SOE_SHIFT 6

#define	DMA_ES_SAE_MASK 0x80u

#define	DMA_ES_SAE_SHIFT 7

#define	DMA_ES_ERRCHN_MASK 0xF00u

#define	DMA_ES_ERRCHN_SHIFT 8

#define	DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)

#define	DMA_ES_CPE_MASK 0x4000u

#define	DMA_ES_CPE_SHIFT 14

#define	DMA_ES_ECX_MASK 0x10000u

#define	DMA_ES_ECX_SHIFT 16

#define	DMA_ES_VLD_MASK 0x80000000u

#define	DMA_ES_VLD_SHIFT 31

#define	DMA_ES_DBE_MASK (0x1U)

#define	DMA_ES_DBE_SHIFT (0U)

#define	DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

#define	DMA_ES_SBE_MASK (0x2U)

#define	DMA_ES_SBE_SHIFT (1U)

#define	DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

#define	DMA_ES_SGE_MASK (0x4U)

#define	DMA_ES_SGE_SHIFT (2U)

#define	DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

#define	DMA_ES_NCE_MASK (0x8U)

#define	DMA_ES_NCE_SHIFT (3U)

#define	DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

#define	DMA_ES_DOE_MASK (0x10U)

#define	DMA_ES_DOE_SHIFT (4U)

#define	DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

#define	DMA_ES_DAE_MASK (0x20U)

#define	DMA_ES_DAE_SHIFT (5U)

#define	DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

#define	DMA_ES_SOE_MASK (0x40U)

#define	DMA_ES_SOE_SHIFT (6U)

#define	DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

#define	DMA_ES_SAE_MASK (0x80U)

#define	DMA_ES_SAE_SHIFT (7U)

#define	DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

#define	DMA_ES_ERRCHN_MASK (0xF00U)

#define	DMA_ES_ERRCHN_SHIFT (8U)

#define	DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

#define	DMA_ES_CPE_MASK (0x4000U)

#define	DMA_ES_CPE_SHIFT (14U)

#define	DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

#define	DMA_ES_ECX_MASK (0x10000U)

#define	DMA_ES_ECX_SHIFT (16U)

#define	DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

#define	DMA_ES_VLD_MASK (0x80000000U)

#define	DMA_ES_VLD_SHIFT (31U)

#define	DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

#define	DMA_ES_DBE_MASK (0x1U)

#define	DMA_ES_DBE_SHIFT (0U)

#define	DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

#define	DMA_ES_SBE_MASK (0x2U)

#define	DMA_ES_SBE_SHIFT (1U)

#define	DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

#define	DMA_ES_SGE_MASK (0x4U)

#define	DMA_ES_SGE_SHIFT (2U)

#define	DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

#define	DMA_ES_NCE_MASK (0x8U)

#define	DMA_ES_NCE_SHIFT (3U)

#define	DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

#define	DMA_ES_DOE_MASK (0x10U)

#define	DMA_ES_DOE_SHIFT (4U)

#define	DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

#define	DMA_ES_DAE_MASK (0x20U)

#define	DMA_ES_DAE_SHIFT (5U)

#define	DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

#define	DMA_ES_SOE_MASK (0x40U)

#define	DMA_ES_SOE_SHIFT (6U)

#define	DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

#define	DMA_ES_SAE_MASK (0x80U)

#define	DMA_ES_SAE_SHIFT (7U)

#define	DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

#define	DMA_ES_ERRCHN_MASK (0x1F00U)

#define	DMA_ES_ERRCHN_SHIFT (8U)

#define	DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

#define	DMA_ES_CPE_MASK (0x4000U)

#define	DMA_ES_CPE_SHIFT (14U)

#define	DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

#define	DMA_ES_GPE_MASK (0x8000U)

#define	DMA_ES_GPE_SHIFT (15U)

#define	DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

#define	DMA_ES_ECX_MASK (0x10000U)

#define	DMA_ES_ECX_SHIFT (16U)

#define	DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

#define	DMA_ES_VLD_MASK (0x80000000U)

#define	DMA_ES_VLD_SHIFT (31U)

#define	DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

#define	DMA_ES_DBE_MASK (0x1U)

#define	DMA_ES_DBE_SHIFT (0U)

#define	DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

#define	DMA_ES_SBE_MASK (0x2U)

#define	DMA_ES_SBE_SHIFT (1U)

#define	DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

#define	DMA_ES_SGE_MASK (0x4U)

#define	DMA_ES_SGE_SHIFT (2U)

#define	DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

#define	DMA_ES_NCE_MASK (0x8U)

#define	DMA_ES_NCE_SHIFT (3U)

#define	DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

#define	DMA_ES_DOE_MASK (0x10U)

#define	DMA_ES_DOE_SHIFT (4U)

#define	DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

#define	DMA_ES_DAE_MASK (0x20U)

#define	DMA_ES_DAE_SHIFT (5U)

#define	DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

#define	DMA_ES_SOE_MASK (0x40U)

#define	DMA_ES_SOE_SHIFT (6U)

#define	DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

#define	DMA_ES_SAE_MASK (0x80U)

#define	DMA_ES_SAE_SHIFT (7U)

#define	DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

#define	DMA_ES_ERRCHN_MASK (0x1F00U)

#define	DMA_ES_ERRCHN_SHIFT (8U)

#define	DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

#define	DMA_ES_CPE_MASK (0x4000U)

#define	DMA_ES_CPE_SHIFT (14U)

#define	DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

#define	DMA_ES_GPE_MASK (0x8000U)

#define	DMA_ES_GPE_SHIFT (15U)

#define	DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

#define	DMA_ES_ECX_MASK (0x10000U)

#define	DMA_ES_ECX_SHIFT (16U)

#define	DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

#define	DMA_ES_VLD_MASK (0x80000000U)

#define	DMA_ES_VLD_SHIFT (31U)

#define	DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

#define	DMA_ES_DBE_MASK (0x1U)

#define	DMA_ES_DBE_SHIFT (0U)

#define	DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

#define	DMA_ES_SBE_MASK (0x2U)

#define	DMA_ES_SBE_SHIFT (1U)

#define	DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

#define	DMA_ES_SGE_MASK (0x4U)

#define	DMA_ES_SGE_SHIFT (2U)

#define	DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

#define	DMA_ES_NCE_MASK (0x8U)

#define	DMA_ES_NCE_SHIFT (3U)

#define	DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

#define	DMA_ES_DOE_MASK (0x10U)

#define	DMA_ES_DOE_SHIFT (4U)

#define	DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

#define	DMA_ES_DAE_MASK (0x20U)

#define	DMA_ES_DAE_SHIFT (5U)

#define	DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

#define	DMA_ES_SOE_MASK (0x40U)

#define	DMA_ES_SOE_SHIFT (6U)

#define	DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

#define	DMA_ES_SAE_MASK (0x80U)

#define	DMA_ES_SAE_SHIFT (7U)

#define	DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

#define	DMA_ES_ERRCHN_MASK (0x1F00U)

#define	DMA_ES_ERRCHN_SHIFT (8U)

#define	DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)

#define	DMA_ES_CPE_MASK (0x4000U)

#define	DMA_ES_CPE_SHIFT (14U)

#define	DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

#define	DMA_ES_GPE_MASK (0x8000U)

#define	DMA_ES_GPE_SHIFT (15U)

#define	DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

#define	DMA_ES_ECX_MASK (0x10000U)

#define	DMA_ES_ECX_SHIFT (16U)

#define	DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

#define	DMA_ES_VLD_MASK (0x80000000U)

#define	DMA_ES_VLD_SHIFT (31U)

#define	DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

ERQ - Enable Request Register
#define	DMA_ERQ_ERQ0_MASK (0x1U)

#define	DMA_ERQ_ERQ0_SHIFT (0U)

#define	DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

#define	DMA_ERQ_ERQ1_MASK (0x2U)

#define	DMA_ERQ_ERQ1_SHIFT (1U)

#define	DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

#define	DMA_ERQ_ERQ2_MASK (0x4U)

#define	DMA_ERQ_ERQ2_SHIFT (2U)

#define	DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

#define	DMA_ERQ_ERQ3_MASK (0x8U)

#define	DMA_ERQ_ERQ3_SHIFT (3U)

#define	DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

#define	DMA_ERQ_ERQ4_MASK (0x10U)

#define	DMA_ERQ_ERQ4_SHIFT (4U)

#define	DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

#define	DMA_ERQ_ERQ5_MASK (0x20U)

#define	DMA_ERQ_ERQ5_SHIFT (5U)

#define	DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

#define	DMA_ERQ_ERQ6_MASK (0x40U)

#define	DMA_ERQ_ERQ6_SHIFT (6U)

#define	DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

#define	DMA_ERQ_ERQ7_MASK (0x80U)

#define	DMA_ERQ_ERQ7_SHIFT (7U)

#define	DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

#define	DMA_ERQ_ERQ8_MASK (0x100U)

#define	DMA_ERQ_ERQ8_SHIFT (8U)

#define	DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

#define	DMA_ERQ_ERQ9_MASK (0x200U)

#define	DMA_ERQ_ERQ9_SHIFT (9U)

#define	DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

#define	DMA_ERQ_ERQ10_MASK (0x400U)

#define	DMA_ERQ_ERQ10_SHIFT (10U)

#define	DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

#define	DMA_ERQ_ERQ11_MASK (0x800U)

#define	DMA_ERQ_ERQ11_SHIFT (11U)

#define	DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

#define	DMA_ERQ_ERQ12_MASK (0x1000U)

#define	DMA_ERQ_ERQ12_SHIFT (12U)

#define	DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

#define	DMA_ERQ_ERQ13_MASK (0x2000U)

#define	DMA_ERQ_ERQ13_SHIFT (13U)

#define	DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

#define	DMA_ERQ_ERQ14_MASK (0x4000U)

#define	DMA_ERQ_ERQ14_SHIFT (14U)

#define	DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

#define	DMA_ERQ_ERQ15_MASK (0x8000U)

#define	DMA_ERQ_ERQ15_SHIFT (15U)

#define	DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

#define	DMA_ERQ_ERQ0_MASK 0x1u

#define	DMA_ERQ_ERQ0_SHIFT 0

#define	DMA_ERQ_ERQ1_MASK 0x2u

#define	DMA_ERQ_ERQ1_SHIFT 1

#define	DMA_ERQ_ERQ2_MASK 0x4u

#define	DMA_ERQ_ERQ2_SHIFT 2

#define	DMA_ERQ_ERQ3_MASK 0x8u

#define	DMA_ERQ_ERQ3_SHIFT 3

#define	DMA_ERQ_ERQ4_MASK 0x10u

#define	DMA_ERQ_ERQ4_SHIFT 4

#define	DMA_ERQ_ERQ5_MASK 0x20u

#define	DMA_ERQ_ERQ5_SHIFT 5

#define	DMA_ERQ_ERQ6_MASK 0x40u

#define	DMA_ERQ_ERQ6_SHIFT 6

#define	DMA_ERQ_ERQ7_MASK 0x80u

#define	DMA_ERQ_ERQ7_SHIFT 7

#define	DMA_ERQ_ERQ8_MASK 0x100u

#define	DMA_ERQ_ERQ8_SHIFT 8

#define	DMA_ERQ_ERQ9_MASK 0x200u

#define	DMA_ERQ_ERQ9_SHIFT 9

#define	DMA_ERQ_ERQ10_MASK 0x400u

#define	DMA_ERQ_ERQ10_SHIFT 10

#define	DMA_ERQ_ERQ11_MASK 0x800u

#define	DMA_ERQ_ERQ11_SHIFT 11

#define	DMA_ERQ_ERQ12_MASK 0x1000u

#define	DMA_ERQ_ERQ12_SHIFT 12

#define	DMA_ERQ_ERQ13_MASK 0x2000u

#define	DMA_ERQ_ERQ13_SHIFT 13

#define	DMA_ERQ_ERQ14_MASK 0x4000u

#define	DMA_ERQ_ERQ14_SHIFT 14

#define	DMA_ERQ_ERQ15_MASK 0x8000u

#define	DMA_ERQ_ERQ15_SHIFT 15

#define	DMA_ERQ_ERQ0_MASK (0x1U)

#define	DMA_ERQ_ERQ0_SHIFT (0U)

#define	DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

#define	DMA_ERQ_ERQ1_MASK (0x2U)

#define	DMA_ERQ_ERQ1_SHIFT (1U)

#define	DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

#define	DMA_ERQ_ERQ2_MASK (0x4U)

#define	DMA_ERQ_ERQ2_SHIFT (2U)

#define	DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

#define	DMA_ERQ_ERQ3_MASK (0x8U)

#define	DMA_ERQ_ERQ3_SHIFT (3U)

#define	DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

#define	DMA_ERQ_ERQ4_MASK (0x10U)

#define	DMA_ERQ_ERQ4_SHIFT (4U)

#define	DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

#define	DMA_ERQ_ERQ5_MASK (0x20U)

#define	DMA_ERQ_ERQ5_SHIFT (5U)

#define	DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

#define	DMA_ERQ_ERQ6_MASK (0x40U)

#define	DMA_ERQ_ERQ6_SHIFT (6U)

#define	DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

#define	DMA_ERQ_ERQ7_MASK (0x80U)

#define	DMA_ERQ_ERQ7_SHIFT (7U)

#define	DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

#define	DMA_ERQ_ERQ8_MASK (0x100U)

#define	DMA_ERQ_ERQ8_SHIFT (8U)

#define	DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

#define	DMA_ERQ_ERQ9_MASK (0x200U)

#define	DMA_ERQ_ERQ9_SHIFT (9U)

#define	DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

#define	DMA_ERQ_ERQ10_MASK (0x400U)

#define	DMA_ERQ_ERQ10_SHIFT (10U)

#define	DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

#define	DMA_ERQ_ERQ11_MASK (0x800U)

#define	DMA_ERQ_ERQ11_SHIFT (11U)

#define	DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

#define	DMA_ERQ_ERQ12_MASK (0x1000U)

#define	DMA_ERQ_ERQ12_SHIFT (12U)

#define	DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

#define	DMA_ERQ_ERQ13_MASK (0x2000U)

#define	DMA_ERQ_ERQ13_SHIFT (13U)

#define	DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

#define	DMA_ERQ_ERQ14_MASK (0x4000U)

#define	DMA_ERQ_ERQ14_SHIFT (14U)

#define	DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

#define	DMA_ERQ_ERQ15_MASK (0x8000U)

#define	DMA_ERQ_ERQ15_SHIFT (15U)

#define	DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

#define	DMA_ERQ_ERQ0_MASK (0x1U)

#define	DMA_ERQ_ERQ0_SHIFT (0U)

#define	DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

#define	DMA_ERQ_ERQ1_MASK (0x2U)

#define	DMA_ERQ_ERQ1_SHIFT (1U)

#define	DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

#define	DMA_ERQ_ERQ2_MASK (0x4U)

#define	DMA_ERQ_ERQ2_SHIFT (2U)

#define	DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

#define	DMA_ERQ_ERQ3_MASK (0x8U)

#define	DMA_ERQ_ERQ3_SHIFT (3U)

#define	DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

#define	DMA_ERQ_ERQ4_MASK (0x10U)

#define	DMA_ERQ_ERQ4_SHIFT (4U)

#define	DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

#define	DMA_ERQ_ERQ5_MASK (0x20U)

#define	DMA_ERQ_ERQ5_SHIFT (5U)

#define	DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

#define	DMA_ERQ_ERQ6_MASK (0x40U)

#define	DMA_ERQ_ERQ6_SHIFT (6U)

#define	DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

#define	DMA_ERQ_ERQ7_MASK (0x80U)

#define	DMA_ERQ_ERQ7_SHIFT (7U)

#define	DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

#define	DMA_ERQ_ERQ8_MASK (0x100U)

#define	DMA_ERQ_ERQ8_SHIFT (8U)

#define	DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

#define	DMA_ERQ_ERQ9_MASK (0x200U)

#define	DMA_ERQ_ERQ9_SHIFT (9U)

#define	DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

#define	DMA_ERQ_ERQ10_MASK (0x400U)

#define	DMA_ERQ_ERQ10_SHIFT (10U)

#define	DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

#define	DMA_ERQ_ERQ11_MASK (0x800U)

#define	DMA_ERQ_ERQ11_SHIFT (11U)

#define	DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

#define	DMA_ERQ_ERQ12_MASK (0x1000U)

#define	DMA_ERQ_ERQ12_SHIFT (12U)

#define	DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

#define	DMA_ERQ_ERQ13_MASK (0x2000U)

#define	DMA_ERQ_ERQ13_SHIFT (13U)

#define	DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

#define	DMA_ERQ_ERQ14_MASK (0x4000U)

#define	DMA_ERQ_ERQ14_SHIFT (14U)

#define	DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

#define	DMA_ERQ_ERQ15_MASK (0x8000U)

#define	DMA_ERQ_ERQ15_SHIFT (15U)

#define	DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

#define	DMA_ERQ_ERQ16_MASK (0x10000U)

#define	DMA_ERQ_ERQ16_SHIFT (16U)

#define	DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

#define	DMA_ERQ_ERQ17_MASK (0x20000U)

#define	DMA_ERQ_ERQ17_SHIFT (17U)

#define	DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

#define	DMA_ERQ_ERQ18_MASK (0x40000U)

#define	DMA_ERQ_ERQ18_SHIFT (18U)

#define	DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

#define	DMA_ERQ_ERQ19_MASK (0x80000U)

#define	DMA_ERQ_ERQ19_SHIFT (19U)

#define	DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

#define	DMA_ERQ_ERQ20_MASK (0x100000U)

#define	DMA_ERQ_ERQ20_SHIFT (20U)

#define	DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

#define	DMA_ERQ_ERQ21_MASK (0x200000U)

#define	DMA_ERQ_ERQ21_SHIFT (21U)

#define	DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

#define	DMA_ERQ_ERQ22_MASK (0x400000U)

#define	DMA_ERQ_ERQ22_SHIFT (22U)

#define	DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

#define	DMA_ERQ_ERQ23_MASK (0x800000U)

#define	DMA_ERQ_ERQ23_SHIFT (23U)

#define	DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

#define	DMA_ERQ_ERQ24_MASK (0x1000000U)

#define	DMA_ERQ_ERQ24_SHIFT (24U)

#define	DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

#define	DMA_ERQ_ERQ25_MASK (0x2000000U)

#define	DMA_ERQ_ERQ25_SHIFT (25U)

#define	DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

#define	DMA_ERQ_ERQ26_MASK (0x4000000U)

#define	DMA_ERQ_ERQ26_SHIFT (26U)

#define	DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

#define	DMA_ERQ_ERQ27_MASK (0x8000000U)

#define	DMA_ERQ_ERQ27_SHIFT (27U)

#define	DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

#define	DMA_ERQ_ERQ28_MASK (0x10000000U)

#define	DMA_ERQ_ERQ28_SHIFT (28U)

#define	DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

#define	DMA_ERQ_ERQ29_MASK (0x20000000U)

#define	DMA_ERQ_ERQ29_SHIFT (29U)

#define	DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

#define	DMA_ERQ_ERQ30_MASK (0x40000000U)

#define	DMA_ERQ_ERQ30_SHIFT (30U)

#define	DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

#define	DMA_ERQ_ERQ31_MASK (0x80000000U)

#define	DMA_ERQ_ERQ31_SHIFT (31U)

#define	DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

#define	DMA_ERQ_ERQ0_MASK (0x1U)

#define	DMA_ERQ_ERQ0_SHIFT (0U)

#define	DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

#define	DMA_ERQ_ERQ1_MASK (0x2U)

#define	DMA_ERQ_ERQ1_SHIFT (1U)

#define	DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

#define	DMA_ERQ_ERQ2_MASK (0x4U)

#define	DMA_ERQ_ERQ2_SHIFT (2U)

#define	DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

#define	DMA_ERQ_ERQ3_MASK (0x8U)

#define	DMA_ERQ_ERQ3_SHIFT (3U)

#define	DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

#define	DMA_ERQ_ERQ4_MASK (0x10U)

#define	DMA_ERQ_ERQ4_SHIFT (4U)

#define	DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

#define	DMA_ERQ_ERQ5_MASK (0x20U)

#define	DMA_ERQ_ERQ5_SHIFT (5U)

#define	DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

#define	DMA_ERQ_ERQ6_MASK (0x40U)

#define	DMA_ERQ_ERQ6_SHIFT (6U)

#define	DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

#define	DMA_ERQ_ERQ7_MASK (0x80U)

#define	DMA_ERQ_ERQ7_SHIFT (7U)

#define	DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

#define	DMA_ERQ_ERQ8_MASK (0x100U)

#define	DMA_ERQ_ERQ8_SHIFT (8U)

#define	DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

#define	DMA_ERQ_ERQ9_MASK (0x200U)

#define	DMA_ERQ_ERQ9_SHIFT (9U)

#define	DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

#define	DMA_ERQ_ERQ10_MASK (0x400U)

#define	DMA_ERQ_ERQ10_SHIFT (10U)

#define	DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

#define	DMA_ERQ_ERQ11_MASK (0x800U)

#define	DMA_ERQ_ERQ11_SHIFT (11U)

#define	DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

#define	DMA_ERQ_ERQ12_MASK (0x1000U)

#define	DMA_ERQ_ERQ12_SHIFT (12U)

#define	DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

#define	DMA_ERQ_ERQ13_MASK (0x2000U)

#define	DMA_ERQ_ERQ13_SHIFT (13U)

#define	DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

#define	DMA_ERQ_ERQ14_MASK (0x4000U)

#define	DMA_ERQ_ERQ14_SHIFT (14U)

#define	DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

#define	DMA_ERQ_ERQ15_MASK (0x8000U)

#define	DMA_ERQ_ERQ15_SHIFT (15U)

#define	DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

#define	DMA_ERQ_ERQ16_MASK (0x10000U)

#define	DMA_ERQ_ERQ16_SHIFT (16U)

#define	DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

#define	DMA_ERQ_ERQ17_MASK (0x20000U)

#define	DMA_ERQ_ERQ17_SHIFT (17U)

#define	DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

#define	DMA_ERQ_ERQ18_MASK (0x40000U)

#define	DMA_ERQ_ERQ18_SHIFT (18U)

#define	DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

#define	DMA_ERQ_ERQ19_MASK (0x80000U)

#define	DMA_ERQ_ERQ19_SHIFT (19U)

#define	DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

#define	DMA_ERQ_ERQ20_MASK (0x100000U)

#define	DMA_ERQ_ERQ20_SHIFT (20U)

#define	DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

#define	DMA_ERQ_ERQ21_MASK (0x200000U)

#define	DMA_ERQ_ERQ21_SHIFT (21U)

#define	DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

#define	DMA_ERQ_ERQ22_MASK (0x400000U)

#define	DMA_ERQ_ERQ22_SHIFT (22U)

#define	DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

#define	DMA_ERQ_ERQ23_MASK (0x800000U)

#define	DMA_ERQ_ERQ23_SHIFT (23U)

#define	DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

#define	DMA_ERQ_ERQ24_MASK (0x1000000U)

#define	DMA_ERQ_ERQ24_SHIFT (24U)

#define	DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

#define	DMA_ERQ_ERQ25_MASK (0x2000000U)

#define	DMA_ERQ_ERQ25_SHIFT (25U)

#define	DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

#define	DMA_ERQ_ERQ26_MASK (0x4000000U)

#define	DMA_ERQ_ERQ26_SHIFT (26U)

#define	DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

#define	DMA_ERQ_ERQ27_MASK (0x8000000U)

#define	DMA_ERQ_ERQ27_SHIFT (27U)

#define	DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

#define	DMA_ERQ_ERQ28_MASK (0x10000000U)

#define	DMA_ERQ_ERQ28_SHIFT (28U)

#define	DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

#define	DMA_ERQ_ERQ29_MASK (0x20000000U)

#define	DMA_ERQ_ERQ29_SHIFT (29U)

#define	DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

#define	DMA_ERQ_ERQ30_MASK (0x40000000U)

#define	DMA_ERQ_ERQ30_SHIFT (30U)

#define	DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

#define	DMA_ERQ_ERQ31_MASK (0x80000000U)

#define	DMA_ERQ_ERQ31_SHIFT (31U)

#define	DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

#define	DMA_ERQ_ERQ0_MASK (0x1U)

#define	DMA_ERQ_ERQ0_SHIFT (0U)

#define	DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

#define	DMA_ERQ_ERQ1_MASK (0x2U)

#define	DMA_ERQ_ERQ1_SHIFT (1U)

#define	DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

#define	DMA_ERQ_ERQ2_MASK (0x4U)

#define	DMA_ERQ_ERQ2_SHIFT (2U)

#define	DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

#define	DMA_ERQ_ERQ3_MASK (0x8U)

#define	DMA_ERQ_ERQ3_SHIFT (3U)

#define	DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

#define	DMA_ERQ_ERQ4_MASK (0x10U)

#define	DMA_ERQ_ERQ4_SHIFT (4U)

#define	DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

#define	DMA_ERQ_ERQ5_MASK (0x20U)

#define	DMA_ERQ_ERQ5_SHIFT (5U)

#define	DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

#define	DMA_ERQ_ERQ6_MASK (0x40U)

#define	DMA_ERQ_ERQ6_SHIFT (6U)

#define	DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

#define	DMA_ERQ_ERQ7_MASK (0x80U)

#define	DMA_ERQ_ERQ7_SHIFT (7U)

#define	DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

#define	DMA_ERQ_ERQ8_MASK (0x100U)

#define	DMA_ERQ_ERQ8_SHIFT (8U)

#define	DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

#define	DMA_ERQ_ERQ9_MASK (0x200U)

#define	DMA_ERQ_ERQ9_SHIFT (9U)

#define	DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

#define	DMA_ERQ_ERQ10_MASK (0x400U)

#define	DMA_ERQ_ERQ10_SHIFT (10U)

#define	DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

#define	DMA_ERQ_ERQ11_MASK (0x800U)

#define	DMA_ERQ_ERQ11_SHIFT (11U)

#define	DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

#define	DMA_ERQ_ERQ12_MASK (0x1000U)

#define	DMA_ERQ_ERQ12_SHIFT (12U)

#define	DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

#define	DMA_ERQ_ERQ13_MASK (0x2000U)

#define	DMA_ERQ_ERQ13_SHIFT (13U)

#define	DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

#define	DMA_ERQ_ERQ14_MASK (0x4000U)

#define	DMA_ERQ_ERQ14_SHIFT (14U)

#define	DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

#define	DMA_ERQ_ERQ15_MASK (0x8000U)

#define	DMA_ERQ_ERQ15_SHIFT (15U)

#define	DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

#define	DMA_ERQ_ERQ16_MASK (0x10000U)

#define	DMA_ERQ_ERQ16_SHIFT (16U)

#define	DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

#define	DMA_ERQ_ERQ17_MASK (0x20000U)

#define	DMA_ERQ_ERQ17_SHIFT (17U)

#define	DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

#define	DMA_ERQ_ERQ18_MASK (0x40000U)

#define	DMA_ERQ_ERQ18_SHIFT (18U)

#define	DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

#define	DMA_ERQ_ERQ19_MASK (0x80000U)

#define	DMA_ERQ_ERQ19_SHIFT (19U)

#define	DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

#define	DMA_ERQ_ERQ20_MASK (0x100000U)

#define	DMA_ERQ_ERQ20_SHIFT (20U)

#define	DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

#define	DMA_ERQ_ERQ21_MASK (0x200000U)

#define	DMA_ERQ_ERQ21_SHIFT (21U)

#define	DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

#define	DMA_ERQ_ERQ22_MASK (0x400000U)

#define	DMA_ERQ_ERQ22_SHIFT (22U)

#define	DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

#define	DMA_ERQ_ERQ23_MASK (0x800000U)

#define	DMA_ERQ_ERQ23_SHIFT (23U)

#define	DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

#define	DMA_ERQ_ERQ24_MASK (0x1000000U)

#define	DMA_ERQ_ERQ24_SHIFT (24U)

#define	DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

#define	DMA_ERQ_ERQ25_MASK (0x2000000U)

#define	DMA_ERQ_ERQ25_SHIFT (25U)

#define	DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

#define	DMA_ERQ_ERQ26_MASK (0x4000000U)

#define	DMA_ERQ_ERQ26_SHIFT (26U)

#define	DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

#define	DMA_ERQ_ERQ27_MASK (0x8000000U)

#define	DMA_ERQ_ERQ27_SHIFT (27U)

#define	DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

#define	DMA_ERQ_ERQ28_MASK (0x10000000U)

#define	DMA_ERQ_ERQ28_SHIFT (28U)

#define	DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

#define	DMA_ERQ_ERQ29_MASK (0x20000000U)

#define	DMA_ERQ_ERQ29_SHIFT (29U)

#define	DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

#define	DMA_ERQ_ERQ30_MASK (0x40000000U)

#define	DMA_ERQ_ERQ30_SHIFT (30U)

#define	DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

#define	DMA_ERQ_ERQ31_MASK (0x80000000U)

#define	DMA_ERQ_ERQ31_SHIFT (31U)

#define	DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

EEI - Enable Error Interrupt Register
#define	DMA_EEI_EEI0_MASK (0x1U)

#define	DMA_EEI_EEI0_SHIFT (0U)

#define	DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

#define	DMA_EEI_EEI1_MASK (0x2U)

#define	DMA_EEI_EEI1_SHIFT (1U)

#define	DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

#define	DMA_EEI_EEI2_MASK (0x4U)

#define	DMA_EEI_EEI2_SHIFT (2U)

#define	DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

#define	DMA_EEI_EEI3_MASK (0x8U)

#define	DMA_EEI_EEI3_SHIFT (3U)

#define	DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

#define	DMA_EEI_EEI4_MASK (0x10U)

#define	DMA_EEI_EEI4_SHIFT (4U)

#define	DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

#define	DMA_EEI_EEI5_MASK (0x20U)

#define	DMA_EEI_EEI5_SHIFT (5U)

#define	DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

#define	DMA_EEI_EEI6_MASK (0x40U)

#define	DMA_EEI_EEI6_SHIFT (6U)

#define	DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

#define	DMA_EEI_EEI7_MASK (0x80U)

#define	DMA_EEI_EEI7_SHIFT (7U)

#define	DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

#define	DMA_EEI_EEI8_MASK (0x100U)

#define	DMA_EEI_EEI8_SHIFT (8U)

#define	DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

#define	DMA_EEI_EEI9_MASK (0x200U)

#define	DMA_EEI_EEI9_SHIFT (9U)

#define	DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

#define	DMA_EEI_EEI10_MASK (0x400U)

#define	DMA_EEI_EEI10_SHIFT (10U)

#define	DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

#define	DMA_EEI_EEI11_MASK (0x800U)

#define	DMA_EEI_EEI11_SHIFT (11U)

#define	DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

#define	DMA_EEI_EEI12_MASK (0x1000U)

#define	DMA_EEI_EEI12_SHIFT (12U)

#define	DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

#define	DMA_EEI_EEI13_MASK (0x2000U)

#define	DMA_EEI_EEI13_SHIFT (13U)

#define	DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

#define	DMA_EEI_EEI14_MASK (0x4000U)

#define	DMA_EEI_EEI14_SHIFT (14U)

#define	DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

#define	DMA_EEI_EEI15_MASK (0x8000U)

#define	DMA_EEI_EEI15_SHIFT (15U)

#define	DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

#define	DMA_EEI_EEI0_MASK 0x1u

#define	DMA_EEI_EEI0_SHIFT 0

#define	DMA_EEI_EEI1_MASK 0x2u

#define	DMA_EEI_EEI1_SHIFT 1

#define	DMA_EEI_EEI2_MASK 0x4u

#define	DMA_EEI_EEI2_SHIFT 2

#define	DMA_EEI_EEI3_MASK 0x8u

#define	DMA_EEI_EEI3_SHIFT 3

#define	DMA_EEI_EEI4_MASK 0x10u

#define	DMA_EEI_EEI4_SHIFT 4

#define	DMA_EEI_EEI5_MASK 0x20u

#define	DMA_EEI_EEI5_SHIFT 5

#define	DMA_EEI_EEI6_MASK 0x40u

#define	DMA_EEI_EEI6_SHIFT 6

#define	DMA_EEI_EEI7_MASK 0x80u

#define	DMA_EEI_EEI7_SHIFT 7

#define	DMA_EEI_EEI8_MASK 0x100u

#define	DMA_EEI_EEI8_SHIFT 8

#define	DMA_EEI_EEI9_MASK 0x200u

#define	DMA_EEI_EEI9_SHIFT 9

#define	DMA_EEI_EEI10_MASK 0x400u

#define	DMA_EEI_EEI10_SHIFT 10

#define	DMA_EEI_EEI11_MASK 0x800u

#define	DMA_EEI_EEI11_SHIFT 11

#define	DMA_EEI_EEI12_MASK 0x1000u

#define	DMA_EEI_EEI12_SHIFT 12

#define	DMA_EEI_EEI13_MASK 0x2000u

#define	DMA_EEI_EEI13_SHIFT 13

#define	DMA_EEI_EEI14_MASK 0x4000u

#define	DMA_EEI_EEI14_SHIFT 14

#define	DMA_EEI_EEI15_MASK 0x8000u

#define	DMA_EEI_EEI15_SHIFT 15

#define	DMA_EEI_EEI0_MASK (0x1U)

#define	DMA_EEI_EEI0_SHIFT (0U)

#define	DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

#define	DMA_EEI_EEI1_MASK (0x2U)

#define	DMA_EEI_EEI1_SHIFT (1U)

#define	DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

#define	DMA_EEI_EEI2_MASK (0x4U)

#define	DMA_EEI_EEI2_SHIFT (2U)

#define	DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

#define	DMA_EEI_EEI3_MASK (0x8U)

#define	DMA_EEI_EEI3_SHIFT (3U)

#define	DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

#define	DMA_EEI_EEI4_MASK (0x10U)

#define	DMA_EEI_EEI4_SHIFT (4U)

#define	DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

#define	DMA_EEI_EEI5_MASK (0x20U)

#define	DMA_EEI_EEI5_SHIFT (5U)

#define	DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

#define	DMA_EEI_EEI6_MASK (0x40U)

#define	DMA_EEI_EEI6_SHIFT (6U)

#define	DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

#define	DMA_EEI_EEI7_MASK (0x80U)

#define	DMA_EEI_EEI7_SHIFT (7U)

#define	DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

#define	DMA_EEI_EEI8_MASK (0x100U)

#define	DMA_EEI_EEI8_SHIFT (8U)

#define	DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

#define	DMA_EEI_EEI9_MASK (0x200U)

#define	DMA_EEI_EEI9_SHIFT (9U)

#define	DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

#define	DMA_EEI_EEI10_MASK (0x400U)

#define	DMA_EEI_EEI10_SHIFT (10U)

#define	DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

#define	DMA_EEI_EEI11_MASK (0x800U)

#define	DMA_EEI_EEI11_SHIFT (11U)

#define	DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

#define	DMA_EEI_EEI12_MASK (0x1000U)

#define	DMA_EEI_EEI12_SHIFT (12U)

#define	DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

#define	DMA_EEI_EEI13_MASK (0x2000U)

#define	DMA_EEI_EEI13_SHIFT (13U)

#define	DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

#define	DMA_EEI_EEI14_MASK (0x4000U)

#define	DMA_EEI_EEI14_SHIFT (14U)

#define	DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

#define	DMA_EEI_EEI15_MASK (0x8000U)

#define	DMA_EEI_EEI15_SHIFT (15U)

#define	DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

#define	DMA_EEI_EEI0_MASK (0x1U)

#define	DMA_EEI_EEI0_SHIFT (0U)

#define	DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

#define	DMA_EEI_EEI1_MASK (0x2U)

#define	DMA_EEI_EEI1_SHIFT (1U)

#define	DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

#define	DMA_EEI_EEI2_MASK (0x4U)

#define	DMA_EEI_EEI2_SHIFT (2U)

#define	DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

#define	DMA_EEI_EEI3_MASK (0x8U)

#define	DMA_EEI_EEI3_SHIFT (3U)

#define	DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

#define	DMA_EEI_EEI4_MASK (0x10U)

#define	DMA_EEI_EEI4_SHIFT (4U)

#define	DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

#define	DMA_EEI_EEI5_MASK (0x20U)

#define	DMA_EEI_EEI5_SHIFT (5U)

#define	DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

#define	DMA_EEI_EEI6_MASK (0x40U)

#define	DMA_EEI_EEI6_SHIFT (6U)

#define	DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

#define	DMA_EEI_EEI7_MASK (0x80U)

#define	DMA_EEI_EEI7_SHIFT (7U)

#define	DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

#define	DMA_EEI_EEI8_MASK (0x100U)

#define	DMA_EEI_EEI8_SHIFT (8U)

#define	DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

#define	DMA_EEI_EEI9_MASK (0x200U)

#define	DMA_EEI_EEI9_SHIFT (9U)

#define	DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

#define	DMA_EEI_EEI10_MASK (0x400U)

#define	DMA_EEI_EEI10_SHIFT (10U)

#define	DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

#define	DMA_EEI_EEI11_MASK (0x800U)

#define	DMA_EEI_EEI11_SHIFT (11U)

#define	DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

#define	DMA_EEI_EEI12_MASK (0x1000U)

#define	DMA_EEI_EEI12_SHIFT (12U)

#define	DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

#define	DMA_EEI_EEI13_MASK (0x2000U)

#define	DMA_EEI_EEI13_SHIFT (13U)

#define	DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

#define	DMA_EEI_EEI14_MASK (0x4000U)

#define	DMA_EEI_EEI14_SHIFT (14U)

#define	DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

#define	DMA_EEI_EEI15_MASK (0x8000U)

#define	DMA_EEI_EEI15_SHIFT (15U)

#define	DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

#define	DMA_EEI_EEI16_MASK (0x10000U)

#define	DMA_EEI_EEI16_SHIFT (16U)

#define	DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

#define	DMA_EEI_EEI17_MASK (0x20000U)

#define	DMA_EEI_EEI17_SHIFT (17U)

#define	DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

#define	DMA_EEI_EEI18_MASK (0x40000U)

#define	DMA_EEI_EEI18_SHIFT (18U)

#define	DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

#define	DMA_EEI_EEI19_MASK (0x80000U)

#define	DMA_EEI_EEI19_SHIFT (19U)

#define	DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

#define	DMA_EEI_EEI20_MASK (0x100000U)

#define	DMA_EEI_EEI20_SHIFT (20U)

#define	DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

#define	DMA_EEI_EEI21_MASK (0x200000U)

#define	DMA_EEI_EEI21_SHIFT (21U)

#define	DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

#define	DMA_EEI_EEI22_MASK (0x400000U)

#define	DMA_EEI_EEI22_SHIFT (22U)

#define	DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

#define	DMA_EEI_EEI23_MASK (0x800000U)

#define	DMA_EEI_EEI23_SHIFT (23U)

#define	DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

#define	DMA_EEI_EEI24_MASK (0x1000000U)

#define	DMA_EEI_EEI24_SHIFT (24U)

#define	DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

#define	DMA_EEI_EEI25_MASK (0x2000000U)

#define	DMA_EEI_EEI25_SHIFT (25U)

#define	DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

#define	DMA_EEI_EEI26_MASK (0x4000000U)

#define	DMA_EEI_EEI26_SHIFT (26U)

#define	DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

#define	DMA_EEI_EEI27_MASK (0x8000000U)

#define	DMA_EEI_EEI27_SHIFT (27U)

#define	DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

#define	DMA_EEI_EEI28_MASK (0x10000000U)

#define	DMA_EEI_EEI28_SHIFT (28U)

#define	DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

#define	DMA_EEI_EEI29_MASK (0x20000000U)

#define	DMA_EEI_EEI29_SHIFT (29U)

#define	DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

#define	DMA_EEI_EEI30_MASK (0x40000000U)

#define	DMA_EEI_EEI30_SHIFT (30U)

#define	DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

#define	DMA_EEI_EEI31_MASK (0x80000000U)

#define	DMA_EEI_EEI31_SHIFT (31U)

#define	DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

#define	DMA_EEI_EEI0_MASK (0x1U)

#define	DMA_EEI_EEI0_SHIFT (0U)

#define	DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

#define	DMA_EEI_EEI1_MASK (0x2U)

#define	DMA_EEI_EEI1_SHIFT (1U)

#define	DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

#define	DMA_EEI_EEI2_MASK (0x4U)

#define	DMA_EEI_EEI2_SHIFT (2U)

#define	DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

#define	DMA_EEI_EEI3_MASK (0x8U)

#define	DMA_EEI_EEI3_SHIFT (3U)

#define	DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

#define	DMA_EEI_EEI4_MASK (0x10U)

#define	DMA_EEI_EEI4_SHIFT (4U)

#define	DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

#define	DMA_EEI_EEI5_MASK (0x20U)

#define	DMA_EEI_EEI5_SHIFT (5U)

#define	DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

#define	DMA_EEI_EEI6_MASK (0x40U)

#define	DMA_EEI_EEI6_SHIFT (6U)

#define	DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

#define	DMA_EEI_EEI7_MASK (0x80U)

#define	DMA_EEI_EEI7_SHIFT (7U)

#define	DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

#define	DMA_EEI_EEI8_MASK (0x100U)

#define	DMA_EEI_EEI8_SHIFT (8U)

#define	DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

#define	DMA_EEI_EEI9_MASK (0x200U)

#define	DMA_EEI_EEI9_SHIFT (9U)

#define	DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

#define	DMA_EEI_EEI10_MASK (0x400U)

#define	DMA_EEI_EEI10_SHIFT (10U)

#define	DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

#define	DMA_EEI_EEI11_MASK (0x800U)

#define	DMA_EEI_EEI11_SHIFT (11U)

#define	DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

#define	DMA_EEI_EEI12_MASK (0x1000U)

#define	DMA_EEI_EEI12_SHIFT (12U)

#define	DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

#define	DMA_EEI_EEI13_MASK (0x2000U)

#define	DMA_EEI_EEI13_SHIFT (13U)

#define	DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

#define	DMA_EEI_EEI14_MASK (0x4000U)

#define	DMA_EEI_EEI14_SHIFT (14U)

#define	DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

#define	DMA_EEI_EEI15_MASK (0x8000U)

#define	DMA_EEI_EEI15_SHIFT (15U)

#define	DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

#define	DMA_EEI_EEI16_MASK (0x10000U)

#define	DMA_EEI_EEI16_SHIFT (16U)

#define	DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

#define	DMA_EEI_EEI17_MASK (0x20000U)

#define	DMA_EEI_EEI17_SHIFT (17U)

#define	DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

#define	DMA_EEI_EEI18_MASK (0x40000U)

#define	DMA_EEI_EEI18_SHIFT (18U)

#define	DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

#define	DMA_EEI_EEI19_MASK (0x80000U)

#define	DMA_EEI_EEI19_SHIFT (19U)

#define	DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

#define	DMA_EEI_EEI20_MASK (0x100000U)

#define	DMA_EEI_EEI20_SHIFT (20U)

#define	DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

#define	DMA_EEI_EEI21_MASK (0x200000U)

#define	DMA_EEI_EEI21_SHIFT (21U)

#define	DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

#define	DMA_EEI_EEI22_MASK (0x400000U)

#define	DMA_EEI_EEI22_SHIFT (22U)

#define	DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

#define	DMA_EEI_EEI23_MASK (0x800000U)

#define	DMA_EEI_EEI23_SHIFT (23U)

#define	DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

#define	DMA_EEI_EEI24_MASK (0x1000000U)

#define	DMA_EEI_EEI24_SHIFT (24U)

#define	DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

#define	DMA_EEI_EEI25_MASK (0x2000000U)

#define	DMA_EEI_EEI25_SHIFT (25U)

#define	DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

#define	DMA_EEI_EEI26_MASK (0x4000000U)

#define	DMA_EEI_EEI26_SHIFT (26U)

#define	DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

#define	DMA_EEI_EEI27_MASK (0x8000000U)

#define	DMA_EEI_EEI27_SHIFT (27U)

#define	DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

#define	DMA_EEI_EEI28_MASK (0x10000000U)

#define	DMA_EEI_EEI28_SHIFT (28U)

#define	DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

#define	DMA_EEI_EEI29_MASK (0x20000000U)

#define	DMA_EEI_EEI29_SHIFT (29U)

#define	DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

#define	DMA_EEI_EEI30_MASK (0x40000000U)

#define	DMA_EEI_EEI30_SHIFT (30U)

#define	DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

#define	DMA_EEI_EEI31_MASK (0x80000000U)

#define	DMA_EEI_EEI31_SHIFT (31U)

#define	DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

#define	DMA_EEI_EEI0_MASK (0x1U)

#define	DMA_EEI_EEI0_SHIFT (0U)

#define	DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

#define	DMA_EEI_EEI1_MASK (0x2U)

#define	DMA_EEI_EEI1_SHIFT (1U)

#define	DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

#define	DMA_EEI_EEI2_MASK (0x4U)

#define	DMA_EEI_EEI2_SHIFT (2U)

#define	DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

#define	DMA_EEI_EEI3_MASK (0x8U)

#define	DMA_EEI_EEI3_SHIFT (3U)

#define	DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

#define	DMA_EEI_EEI4_MASK (0x10U)

#define	DMA_EEI_EEI4_SHIFT (4U)

#define	DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

#define	DMA_EEI_EEI5_MASK (0x20U)

#define	DMA_EEI_EEI5_SHIFT (5U)

#define	DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

#define	DMA_EEI_EEI6_MASK (0x40U)

#define	DMA_EEI_EEI6_SHIFT (6U)

#define	DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

#define	DMA_EEI_EEI7_MASK (0x80U)

#define	DMA_EEI_EEI7_SHIFT (7U)

#define	DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

#define	DMA_EEI_EEI8_MASK (0x100U)

#define	DMA_EEI_EEI8_SHIFT (8U)

#define	DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

#define	DMA_EEI_EEI9_MASK (0x200U)

#define	DMA_EEI_EEI9_SHIFT (9U)

#define	DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

#define	DMA_EEI_EEI10_MASK (0x400U)

#define	DMA_EEI_EEI10_SHIFT (10U)

#define	DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

#define	DMA_EEI_EEI11_MASK (0x800U)

#define	DMA_EEI_EEI11_SHIFT (11U)

#define	DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

#define	DMA_EEI_EEI12_MASK (0x1000U)

#define	DMA_EEI_EEI12_SHIFT (12U)

#define	DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

#define	DMA_EEI_EEI13_MASK (0x2000U)

#define	DMA_EEI_EEI13_SHIFT (13U)

#define	DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

#define	DMA_EEI_EEI14_MASK (0x4000U)

#define	DMA_EEI_EEI14_SHIFT (14U)

#define	DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

#define	DMA_EEI_EEI15_MASK (0x8000U)

#define	DMA_EEI_EEI15_SHIFT (15U)

#define	DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

#define	DMA_EEI_EEI16_MASK (0x10000U)

#define	DMA_EEI_EEI16_SHIFT (16U)

#define	DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

#define	DMA_EEI_EEI17_MASK (0x20000U)

#define	DMA_EEI_EEI17_SHIFT (17U)

#define	DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

#define	DMA_EEI_EEI18_MASK (0x40000U)

#define	DMA_EEI_EEI18_SHIFT (18U)

#define	DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

#define	DMA_EEI_EEI19_MASK (0x80000U)

#define	DMA_EEI_EEI19_SHIFT (19U)

#define	DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

#define	DMA_EEI_EEI20_MASK (0x100000U)

#define	DMA_EEI_EEI20_SHIFT (20U)

#define	DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

#define	DMA_EEI_EEI21_MASK (0x200000U)

#define	DMA_EEI_EEI21_SHIFT (21U)

#define	DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

#define	DMA_EEI_EEI22_MASK (0x400000U)

#define	DMA_EEI_EEI22_SHIFT (22U)

#define	DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

#define	DMA_EEI_EEI23_MASK (0x800000U)

#define	DMA_EEI_EEI23_SHIFT (23U)

#define	DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

#define	DMA_EEI_EEI24_MASK (0x1000000U)

#define	DMA_EEI_EEI24_SHIFT (24U)

#define	DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

#define	DMA_EEI_EEI25_MASK (0x2000000U)

#define	DMA_EEI_EEI25_SHIFT (25U)

#define	DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

#define	DMA_EEI_EEI26_MASK (0x4000000U)

#define	DMA_EEI_EEI26_SHIFT (26U)

#define	DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

#define	DMA_EEI_EEI27_MASK (0x8000000U)

#define	DMA_EEI_EEI27_SHIFT (27U)

#define	DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

#define	DMA_EEI_EEI28_MASK (0x10000000U)

#define	DMA_EEI_EEI28_SHIFT (28U)

#define	DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

#define	DMA_EEI_EEI29_MASK (0x20000000U)

#define	DMA_EEI_EEI29_SHIFT (29U)

#define	DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

#define	DMA_EEI_EEI30_MASK (0x40000000U)

#define	DMA_EEI_EEI30_SHIFT (30U)

#define	DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

#define	DMA_EEI_EEI31_MASK (0x80000000U)

#define	DMA_EEI_EEI31_SHIFT (31U)

#define	DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

CEEI - Clear Enable Error Interrupt Register
#define	DMA_CEEI_CEEI_MASK (0xFU)

#define	DMA_CEEI_CEEI_SHIFT (0U)

#define	DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

#define	DMA_CEEI_CAEE_MASK (0x40U)

#define	DMA_CEEI_CAEE_SHIFT (6U)

#define	DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

#define	DMA_CEEI_NOP_MASK (0x80U)

#define	DMA_CEEI_NOP_SHIFT (7U)

#define	DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

#define	DMA_CEEI_CEEI_MASK 0xFu

#define	DMA_CEEI_CEEI_SHIFT 0

#define	DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)

#define	DMA_CEEI_CAEE_MASK 0x40u

#define	DMA_CEEI_CAEE_SHIFT 6

#define	DMA_CEEI_NOP_MASK 0x80u

#define	DMA_CEEI_NOP_SHIFT 7

#define	DMA_CEEI_CEEI_MASK (0xFU)

#define	DMA_CEEI_CEEI_SHIFT (0U)

#define	DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

#define	DMA_CEEI_CAEE_MASK (0x40U)

#define	DMA_CEEI_CAEE_SHIFT (6U)

#define	DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

#define	DMA_CEEI_NOP_MASK (0x80U)

#define	DMA_CEEI_NOP_SHIFT (7U)

#define	DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

#define	DMA_CEEI_CEEI_MASK (0x1FU)

#define	DMA_CEEI_CEEI_SHIFT (0U)

#define	DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

#define	DMA_CEEI_CAEE_MASK (0x40U)

#define	DMA_CEEI_CAEE_SHIFT (6U)

#define	DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

#define	DMA_CEEI_NOP_MASK (0x80U)

#define	DMA_CEEI_NOP_SHIFT (7U)

#define	DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

#define	DMA_CEEI_CEEI_MASK (0x1FU)

#define	DMA_CEEI_CEEI_SHIFT (0U)

#define	DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

#define	DMA_CEEI_CAEE_MASK (0x40U)

#define	DMA_CEEI_CAEE_SHIFT (6U)

#define	DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

#define	DMA_CEEI_NOP_MASK (0x80U)

#define	DMA_CEEI_NOP_SHIFT (7U)

#define	DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

#define	DMA_CEEI_CEEI_MASK (0x1FU)

#define	DMA_CEEI_CEEI_SHIFT (0U)

#define	DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)

#define	DMA_CEEI_CAEE_MASK (0x40U)

#define	DMA_CEEI_CAEE_SHIFT (6U)

#define	DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

#define	DMA_CEEI_NOP_MASK (0x80U)

#define	DMA_CEEI_NOP_SHIFT (7U)

#define	DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

SEEI - Set Enable Error Interrupt Register
#define	DMA_SEEI_SEEI_MASK (0xFU)

#define	DMA_SEEI_SEEI_SHIFT (0U)

#define	DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

#define	DMA_SEEI_SAEE_MASK (0x40U)

#define	DMA_SEEI_SAEE_SHIFT (6U)

#define	DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

#define	DMA_SEEI_NOP_MASK (0x80U)

#define	DMA_SEEI_NOP_SHIFT (7U)

#define	DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

#define	DMA_SEEI_SEEI_MASK 0xFu

#define	DMA_SEEI_SEEI_SHIFT 0

#define	DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)

#define	DMA_SEEI_SAEE_MASK 0x40u

#define	DMA_SEEI_SAEE_SHIFT 6

#define	DMA_SEEI_NOP_MASK 0x80u

#define	DMA_SEEI_NOP_SHIFT 7

#define	DMA_SEEI_SEEI_MASK (0xFU)

#define	DMA_SEEI_SEEI_SHIFT (0U)

#define	DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

#define	DMA_SEEI_SAEE_MASK (0x40U)

#define	DMA_SEEI_SAEE_SHIFT (6U)

#define	DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

#define	DMA_SEEI_NOP_MASK (0x80U)

#define	DMA_SEEI_NOP_SHIFT (7U)

#define	DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

#define	DMA_SEEI_SEEI_MASK (0x1FU)

#define	DMA_SEEI_SEEI_SHIFT (0U)

#define	DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

#define	DMA_SEEI_SAEE_MASK (0x40U)

#define	DMA_SEEI_SAEE_SHIFT (6U)

#define	DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

#define	DMA_SEEI_NOP_MASK (0x80U)

#define	DMA_SEEI_NOP_SHIFT (7U)

#define	DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

#define	DMA_SEEI_SEEI_MASK (0x1FU)

#define	DMA_SEEI_SEEI_SHIFT (0U)

#define	DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

#define	DMA_SEEI_SAEE_MASK (0x40U)

#define	DMA_SEEI_SAEE_SHIFT (6U)

#define	DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

#define	DMA_SEEI_NOP_MASK (0x80U)

#define	DMA_SEEI_NOP_SHIFT (7U)

#define	DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

#define	DMA_SEEI_SEEI_MASK (0x1FU)

#define	DMA_SEEI_SEEI_SHIFT (0U)

#define	DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)

#define	DMA_SEEI_SAEE_MASK (0x40U)

#define	DMA_SEEI_SAEE_SHIFT (6U)

#define	DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

#define	DMA_SEEI_NOP_MASK (0x80U)

#define	DMA_SEEI_NOP_SHIFT (7U)

#define	DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

CERQ - Clear Enable Request Register
#define	DMA_CERQ_CERQ_MASK (0xFU)

#define	DMA_CERQ_CERQ_SHIFT (0U)

#define	DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

#define	DMA_CERQ_CAER_MASK (0x40U)

#define	DMA_CERQ_CAER_SHIFT (6U)

#define	DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

#define	DMA_CERQ_NOP_MASK (0x80U)

#define	DMA_CERQ_NOP_SHIFT (7U)

#define	DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

#define	DMA_CERQ_CERQ_MASK 0xFu

#define	DMA_CERQ_CERQ_SHIFT 0

#define	DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)

#define	DMA_CERQ_CAER_MASK 0x40u

#define	DMA_CERQ_CAER_SHIFT 6

#define	DMA_CERQ_NOP_MASK 0x80u

#define	DMA_CERQ_NOP_SHIFT 7

#define	DMA_CERQ_CERQ_MASK (0xFU)

#define	DMA_CERQ_CERQ_SHIFT (0U)

#define	DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

#define	DMA_CERQ_CAER_MASK (0x40U)

#define	DMA_CERQ_CAER_SHIFT (6U)

#define	DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

#define	DMA_CERQ_NOP_MASK (0x80U)

#define	DMA_CERQ_NOP_SHIFT (7U)

#define	DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

#define	DMA_CERQ_CERQ_MASK (0x1FU)

#define	DMA_CERQ_CERQ_SHIFT (0U)

#define	DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

#define	DMA_CERQ_CAER_MASK (0x40U)

#define	DMA_CERQ_CAER_SHIFT (6U)

#define	DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

#define	DMA_CERQ_NOP_MASK (0x80U)

#define	DMA_CERQ_NOP_SHIFT (7U)

#define	DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

#define	DMA_CERQ_CERQ_MASK (0x1FU)

#define	DMA_CERQ_CERQ_SHIFT (0U)

#define	DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

#define	DMA_CERQ_CAER_MASK (0x40U)

#define	DMA_CERQ_CAER_SHIFT (6U)

#define	DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

#define	DMA_CERQ_NOP_MASK (0x80U)

#define	DMA_CERQ_NOP_SHIFT (7U)

#define	DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

#define	DMA_CERQ_CERQ_MASK (0x1FU)

#define	DMA_CERQ_CERQ_SHIFT (0U)

#define	DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)

#define	DMA_CERQ_CAER_MASK (0x40U)

#define	DMA_CERQ_CAER_SHIFT (6U)

#define	DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

#define	DMA_CERQ_NOP_MASK (0x80U)

#define	DMA_CERQ_NOP_SHIFT (7U)

#define	DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

SERQ - Set Enable Request Register
#define	DMA_SERQ_SERQ_MASK (0xFU)

#define	DMA_SERQ_SERQ_SHIFT (0U)

#define	DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

#define	DMA_SERQ_SAER_MASK (0x40U)

#define	DMA_SERQ_SAER_SHIFT (6U)

#define	DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

#define	DMA_SERQ_NOP_MASK (0x80U)

#define	DMA_SERQ_NOP_SHIFT (7U)

#define	DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

#define	DMA_SERQ_SERQ_MASK 0xFu

#define	DMA_SERQ_SERQ_SHIFT 0

#define	DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)

#define	DMA_SERQ_SAER_MASK 0x40u

#define	DMA_SERQ_SAER_SHIFT 6

#define	DMA_SERQ_NOP_MASK 0x80u

#define	DMA_SERQ_NOP_SHIFT 7

#define	DMA_SERQ_SERQ_MASK (0xFU)

#define	DMA_SERQ_SERQ_SHIFT (0U)

#define	DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

#define	DMA_SERQ_SAER_MASK (0x40U)

#define	DMA_SERQ_SAER_SHIFT (6U)

#define	DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

#define	DMA_SERQ_NOP_MASK (0x80U)

#define	DMA_SERQ_NOP_SHIFT (7U)

#define	DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

#define	DMA_SERQ_SERQ_MASK (0x1FU)

#define	DMA_SERQ_SERQ_SHIFT (0U)

#define	DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

#define	DMA_SERQ_SAER_MASK (0x40U)

#define	DMA_SERQ_SAER_SHIFT (6U)

#define	DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

#define	DMA_SERQ_NOP_MASK (0x80U)

#define	DMA_SERQ_NOP_SHIFT (7U)

#define	DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

#define	DMA_SERQ_SERQ_MASK (0x1FU)

#define	DMA_SERQ_SERQ_SHIFT (0U)

#define	DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

#define	DMA_SERQ_SAER_MASK (0x40U)

#define	DMA_SERQ_SAER_SHIFT (6U)

#define	DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

#define	DMA_SERQ_NOP_MASK (0x80U)

#define	DMA_SERQ_NOP_SHIFT (7U)

#define	DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

#define	DMA_SERQ_SERQ_MASK (0x1FU)

#define	DMA_SERQ_SERQ_SHIFT (0U)

#define	DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)

#define	DMA_SERQ_SAER_MASK (0x40U)

#define	DMA_SERQ_SAER_SHIFT (6U)

#define	DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

#define	DMA_SERQ_NOP_MASK (0x80U)

#define	DMA_SERQ_NOP_SHIFT (7U)

#define	DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

CDNE - Clear DONE Status Bit Register
#define	DMA_CDNE_CDNE_MASK (0xFU)

#define	DMA_CDNE_CDNE_SHIFT (0U)

#define	DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

#define	DMA_CDNE_CADN_MASK (0x40U)

#define	DMA_CDNE_CADN_SHIFT (6U)

#define	DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

#define	DMA_CDNE_NOP_MASK (0x80U)

#define	DMA_CDNE_NOP_SHIFT (7U)

#define	DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

#define	DMA_CDNE_CDNE_MASK 0xFu

#define	DMA_CDNE_CDNE_SHIFT 0

#define	DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)

#define	DMA_CDNE_CADN_MASK 0x40u

#define	DMA_CDNE_CADN_SHIFT 6

#define	DMA_CDNE_NOP_MASK 0x80u

#define	DMA_CDNE_NOP_SHIFT 7

#define	DMA_CDNE_CDNE_MASK (0xFU)

#define	DMA_CDNE_CDNE_SHIFT (0U)

#define	DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

#define	DMA_CDNE_CADN_MASK (0x40U)

#define	DMA_CDNE_CADN_SHIFT (6U)

#define	DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

#define	DMA_CDNE_NOP_MASK (0x80U)

#define	DMA_CDNE_NOP_SHIFT (7U)

#define	DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

#define	DMA_CDNE_CDNE_MASK (0x1FU)

#define	DMA_CDNE_CDNE_SHIFT (0U)

#define	DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

#define	DMA_CDNE_CADN_MASK (0x40U)

#define	DMA_CDNE_CADN_SHIFT (6U)

#define	DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

#define	DMA_CDNE_NOP_MASK (0x80U)

#define	DMA_CDNE_NOP_SHIFT (7U)

#define	DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

#define	DMA_CDNE_CDNE_MASK (0x1FU)

#define	DMA_CDNE_CDNE_SHIFT (0U)

#define	DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

#define	DMA_CDNE_CADN_MASK (0x40U)

#define	DMA_CDNE_CADN_SHIFT (6U)

#define	DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

#define	DMA_CDNE_NOP_MASK (0x80U)

#define	DMA_CDNE_NOP_SHIFT (7U)

#define	DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

#define	DMA_CDNE_CDNE_MASK (0x1FU)

#define	DMA_CDNE_CDNE_SHIFT (0U)

#define	DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)

#define	DMA_CDNE_CADN_MASK (0x40U)

#define	DMA_CDNE_CADN_SHIFT (6U)

#define	DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

#define	DMA_CDNE_NOP_MASK (0x80U)

#define	DMA_CDNE_NOP_SHIFT (7U)

#define	DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

SSRT - Set START Bit Register
#define	DMA_SSRT_SSRT_MASK (0xFU)

#define	DMA_SSRT_SSRT_SHIFT (0U)

#define	DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

#define	DMA_SSRT_SAST_MASK (0x40U)

#define	DMA_SSRT_SAST_SHIFT (6U)

#define	DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

#define	DMA_SSRT_NOP_MASK (0x80U)

#define	DMA_SSRT_NOP_SHIFT (7U)

#define	DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

#define	DMA_SSRT_SSRT_MASK 0xFu

#define	DMA_SSRT_SSRT_SHIFT 0

#define	DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)

#define	DMA_SSRT_SAST_MASK 0x40u

#define	DMA_SSRT_SAST_SHIFT 6

#define	DMA_SSRT_NOP_MASK 0x80u

#define	DMA_SSRT_NOP_SHIFT 7

#define	DMA_SSRT_SSRT_MASK (0xFU)

#define	DMA_SSRT_SSRT_SHIFT (0U)

#define	DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

#define	DMA_SSRT_SAST_MASK (0x40U)

#define	DMA_SSRT_SAST_SHIFT (6U)

#define	DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

#define	DMA_SSRT_NOP_MASK (0x80U)

#define	DMA_SSRT_NOP_SHIFT (7U)

#define	DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

#define	DMA_SSRT_SSRT_MASK (0x1FU)

#define	DMA_SSRT_SSRT_SHIFT (0U)

#define	DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

#define	DMA_SSRT_SAST_MASK (0x40U)

#define	DMA_SSRT_SAST_SHIFT (6U)

#define	DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

#define	DMA_SSRT_NOP_MASK (0x80U)

#define	DMA_SSRT_NOP_SHIFT (7U)

#define	DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

#define	DMA_SSRT_SSRT_MASK (0x1FU)

#define	DMA_SSRT_SSRT_SHIFT (0U)

#define	DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

#define	DMA_SSRT_SAST_MASK (0x40U)

#define	DMA_SSRT_SAST_SHIFT (6U)

#define	DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

#define	DMA_SSRT_NOP_MASK (0x80U)

#define	DMA_SSRT_NOP_SHIFT (7U)

#define	DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

#define	DMA_SSRT_SSRT_MASK (0x1FU)

#define	DMA_SSRT_SSRT_SHIFT (0U)

#define	DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)

#define	DMA_SSRT_SAST_MASK (0x40U)

#define	DMA_SSRT_SAST_SHIFT (6U)

#define	DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

#define	DMA_SSRT_NOP_MASK (0x80U)

#define	DMA_SSRT_NOP_SHIFT (7U)

#define	DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

CERR - Clear Error Register
#define	DMA_CERR_CERR_MASK (0xFU)

#define	DMA_CERR_CERR_SHIFT (0U)

#define	DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

#define	DMA_CERR_CAEI_MASK (0x40U)

#define	DMA_CERR_CAEI_SHIFT (6U)

#define	DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

#define	DMA_CERR_NOP_MASK (0x80U)

#define	DMA_CERR_NOP_SHIFT (7U)

#define	DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

#define	DMA_CERR_CERR_MASK 0xFu

#define	DMA_CERR_CERR_SHIFT 0

#define	DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)

#define	DMA_CERR_CAEI_MASK 0x40u

#define	DMA_CERR_CAEI_SHIFT 6

#define	DMA_CERR_NOP_MASK 0x80u

#define	DMA_CERR_NOP_SHIFT 7

#define	DMA_CERR_CERR_MASK (0xFU)

#define	DMA_CERR_CERR_SHIFT (0U)

#define	DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

#define	DMA_CERR_CAEI_MASK (0x40U)

#define	DMA_CERR_CAEI_SHIFT (6U)

#define	DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

#define	DMA_CERR_NOP_MASK (0x80U)

#define	DMA_CERR_NOP_SHIFT (7U)

#define	DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

#define	DMA_CERR_CERR_MASK (0x1FU)

#define	DMA_CERR_CERR_SHIFT (0U)

#define	DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

#define	DMA_CERR_CAEI_MASK (0x40U)

#define	DMA_CERR_CAEI_SHIFT (6U)

#define	DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

#define	DMA_CERR_NOP_MASK (0x80U)

#define	DMA_CERR_NOP_SHIFT (7U)

#define	DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

#define	DMA_CERR_CERR_MASK (0x1FU)

#define	DMA_CERR_CERR_SHIFT (0U)

#define	DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

#define	DMA_CERR_CAEI_MASK (0x40U)

#define	DMA_CERR_CAEI_SHIFT (6U)

#define	DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

#define	DMA_CERR_NOP_MASK (0x80U)

#define	DMA_CERR_NOP_SHIFT (7U)

#define	DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

#define	DMA_CERR_CERR_MASK (0x1FU)

#define	DMA_CERR_CERR_SHIFT (0U)

#define	DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)

#define	DMA_CERR_CAEI_MASK (0x40U)

#define	DMA_CERR_CAEI_SHIFT (6U)

#define	DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

#define	DMA_CERR_NOP_MASK (0x80U)

#define	DMA_CERR_NOP_SHIFT (7U)

#define	DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

CINT - Clear Interrupt Request Register
#define	DMA_CINT_CINT_MASK (0xFU)

#define	DMA_CINT_CINT_SHIFT (0U)

#define	DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

#define	DMA_CINT_CAIR_MASK (0x40U)

#define	DMA_CINT_CAIR_SHIFT (6U)

#define	DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

#define	DMA_CINT_NOP_MASK (0x80U)

#define	DMA_CINT_NOP_SHIFT (7U)

#define	DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

#define	DMA_CINT_CINT_MASK 0xFu

#define	DMA_CINT_CINT_SHIFT 0

#define	DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)

#define	DMA_CINT_CAIR_MASK 0x40u

#define	DMA_CINT_CAIR_SHIFT 6

#define	DMA_CINT_NOP_MASK 0x80u

#define	DMA_CINT_NOP_SHIFT 7

#define	DMA_CINT_CINT_MASK (0xFU)

#define	DMA_CINT_CINT_SHIFT (0U)

#define	DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

#define	DMA_CINT_CAIR_MASK (0x40U)

#define	DMA_CINT_CAIR_SHIFT (6U)

#define	DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

#define	DMA_CINT_NOP_MASK (0x80U)

#define	DMA_CINT_NOP_SHIFT (7U)

#define	DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

#define	DMA_CINT_CINT_MASK (0x1FU)

#define	DMA_CINT_CINT_SHIFT (0U)

#define	DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

#define	DMA_CINT_CAIR_MASK (0x40U)

#define	DMA_CINT_CAIR_SHIFT (6U)

#define	DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

#define	DMA_CINT_NOP_MASK (0x80U)

#define	DMA_CINT_NOP_SHIFT (7U)

#define	DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

#define	DMA_CINT_CINT_MASK (0x1FU)

#define	DMA_CINT_CINT_SHIFT (0U)

#define	DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

#define	DMA_CINT_CAIR_MASK (0x40U)

#define	DMA_CINT_CAIR_SHIFT (6U)

#define	DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

#define	DMA_CINT_NOP_MASK (0x80U)

#define	DMA_CINT_NOP_SHIFT (7U)

#define	DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

#define	DMA_CINT_CINT_MASK (0x1FU)

#define	DMA_CINT_CINT_SHIFT (0U)

#define	DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)

#define	DMA_CINT_CAIR_MASK (0x40U)

#define	DMA_CINT_CAIR_SHIFT (6U)

#define	DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

#define	DMA_CINT_NOP_MASK (0x80U)

#define	DMA_CINT_NOP_SHIFT (7U)

#define	DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

INT - Interrupt Request Register
#define	DMA_INT_INT0_MASK (0x1U)

#define	DMA_INT_INT0_SHIFT (0U)

#define	DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

#define	DMA_INT_INT1_MASK (0x2U)

#define	DMA_INT_INT1_SHIFT (1U)

#define	DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

#define	DMA_INT_INT2_MASK (0x4U)

#define	DMA_INT_INT2_SHIFT (2U)

#define	DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

#define	DMA_INT_INT3_MASK (0x8U)

#define	DMA_INT_INT3_SHIFT (3U)

#define	DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

#define	DMA_INT_INT4_MASK (0x10U)

#define	DMA_INT_INT4_SHIFT (4U)

#define	DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

#define	DMA_INT_INT5_MASK (0x20U)

#define	DMA_INT_INT5_SHIFT (5U)

#define	DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

#define	DMA_INT_INT6_MASK (0x40U)

#define	DMA_INT_INT6_SHIFT (6U)

#define	DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

#define	DMA_INT_INT7_MASK (0x80U)

#define	DMA_INT_INT7_SHIFT (7U)

#define	DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

#define	DMA_INT_INT8_MASK (0x100U)

#define	DMA_INT_INT8_SHIFT (8U)

#define	DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

#define	DMA_INT_INT9_MASK (0x200U)

#define	DMA_INT_INT9_SHIFT (9U)

#define	DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

#define	DMA_INT_INT10_MASK (0x400U)

#define	DMA_INT_INT10_SHIFT (10U)

#define	DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

#define	DMA_INT_INT11_MASK (0x800U)

#define	DMA_INT_INT11_SHIFT (11U)

#define	DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

#define	DMA_INT_INT12_MASK (0x1000U)

#define	DMA_INT_INT12_SHIFT (12U)

#define	DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

#define	DMA_INT_INT13_MASK (0x2000U)

#define	DMA_INT_INT13_SHIFT (13U)

#define	DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

#define	DMA_INT_INT14_MASK (0x4000U)

#define	DMA_INT_INT14_SHIFT (14U)

#define	DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

#define	DMA_INT_INT15_MASK (0x8000U)

#define	DMA_INT_INT15_SHIFT (15U)

#define	DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

#define	DMA_INT_INT0_MASK 0x1u

#define	DMA_INT_INT0_SHIFT 0

#define	DMA_INT_INT1_MASK 0x2u

#define	DMA_INT_INT1_SHIFT 1

#define	DMA_INT_INT2_MASK 0x4u

#define	DMA_INT_INT2_SHIFT 2

#define	DMA_INT_INT3_MASK 0x8u

#define	DMA_INT_INT3_SHIFT 3

#define	DMA_INT_INT4_MASK 0x10u

#define	DMA_INT_INT4_SHIFT 4

#define	DMA_INT_INT5_MASK 0x20u

#define	DMA_INT_INT5_SHIFT 5

#define	DMA_INT_INT6_MASK 0x40u

#define	DMA_INT_INT6_SHIFT 6

#define	DMA_INT_INT7_MASK 0x80u

#define	DMA_INT_INT7_SHIFT 7

#define	DMA_INT_INT8_MASK 0x100u

#define	DMA_INT_INT8_SHIFT 8

#define	DMA_INT_INT9_MASK 0x200u

#define	DMA_INT_INT9_SHIFT 9

#define	DMA_INT_INT10_MASK 0x400u

#define	DMA_INT_INT10_SHIFT 10

#define	DMA_INT_INT11_MASK 0x800u

#define	DMA_INT_INT11_SHIFT 11

#define	DMA_INT_INT12_MASK 0x1000u

#define	DMA_INT_INT12_SHIFT 12

#define	DMA_INT_INT13_MASK 0x2000u

#define	DMA_INT_INT13_SHIFT 13

#define	DMA_INT_INT14_MASK 0x4000u

#define	DMA_INT_INT14_SHIFT 14

#define	DMA_INT_INT15_MASK 0x8000u

#define	DMA_INT_INT15_SHIFT 15

#define	DMA_INT_INT0_MASK (0x1U)

#define	DMA_INT_INT0_SHIFT (0U)

#define	DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

#define	DMA_INT_INT1_MASK (0x2U)

#define	DMA_INT_INT1_SHIFT (1U)

#define	DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

#define	DMA_INT_INT2_MASK (0x4U)

#define	DMA_INT_INT2_SHIFT (2U)

#define	DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

#define	DMA_INT_INT3_MASK (0x8U)

#define	DMA_INT_INT3_SHIFT (3U)

#define	DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

#define	DMA_INT_INT4_MASK (0x10U)

#define	DMA_INT_INT4_SHIFT (4U)

#define	DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

#define	DMA_INT_INT5_MASK (0x20U)

#define	DMA_INT_INT5_SHIFT (5U)

#define	DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

#define	DMA_INT_INT6_MASK (0x40U)

#define	DMA_INT_INT6_SHIFT (6U)

#define	DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

#define	DMA_INT_INT7_MASK (0x80U)

#define	DMA_INT_INT7_SHIFT (7U)

#define	DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

#define	DMA_INT_INT8_MASK (0x100U)

#define	DMA_INT_INT8_SHIFT (8U)

#define	DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

#define	DMA_INT_INT9_MASK (0x200U)

#define	DMA_INT_INT9_SHIFT (9U)

#define	DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

#define	DMA_INT_INT10_MASK (0x400U)

#define	DMA_INT_INT10_SHIFT (10U)

#define	DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

#define	DMA_INT_INT11_MASK (0x800U)

#define	DMA_INT_INT11_SHIFT (11U)

#define	DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

#define	DMA_INT_INT12_MASK (0x1000U)

#define	DMA_INT_INT12_SHIFT (12U)

#define	DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

#define	DMA_INT_INT13_MASK (0x2000U)

#define	DMA_INT_INT13_SHIFT (13U)

#define	DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

#define	DMA_INT_INT14_MASK (0x4000U)

#define	DMA_INT_INT14_SHIFT (14U)

#define	DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

#define	DMA_INT_INT15_MASK (0x8000U)

#define	DMA_INT_INT15_SHIFT (15U)

#define	DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

#define	DMA_INT_INT0_MASK (0x1U)

#define	DMA_INT_INT0_SHIFT (0U)

#define	DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

#define	DMA_INT_INT1_MASK (0x2U)

#define	DMA_INT_INT1_SHIFT (1U)

#define	DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

#define	DMA_INT_INT2_MASK (0x4U)

#define	DMA_INT_INT2_SHIFT (2U)

#define	DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

#define	DMA_INT_INT3_MASK (0x8U)

#define	DMA_INT_INT3_SHIFT (3U)

#define	DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

#define	DMA_INT_INT4_MASK (0x10U)

#define	DMA_INT_INT4_SHIFT (4U)

#define	DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

#define	DMA_INT_INT5_MASK (0x20U)

#define	DMA_INT_INT5_SHIFT (5U)

#define	DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

#define	DMA_INT_INT6_MASK (0x40U)

#define	DMA_INT_INT6_SHIFT (6U)

#define	DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

#define	DMA_INT_INT7_MASK (0x80U)

#define	DMA_INT_INT7_SHIFT (7U)

#define	DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

#define	DMA_INT_INT8_MASK (0x100U)

#define	DMA_INT_INT8_SHIFT (8U)

#define	DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

#define	DMA_INT_INT9_MASK (0x200U)

#define	DMA_INT_INT9_SHIFT (9U)

#define	DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

#define	DMA_INT_INT10_MASK (0x400U)

#define	DMA_INT_INT10_SHIFT (10U)

#define	DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

#define	DMA_INT_INT11_MASK (0x800U)

#define	DMA_INT_INT11_SHIFT (11U)

#define	DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

#define	DMA_INT_INT12_MASK (0x1000U)

#define	DMA_INT_INT12_SHIFT (12U)

#define	DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

#define	DMA_INT_INT13_MASK (0x2000U)

#define	DMA_INT_INT13_SHIFT (13U)

#define	DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

#define	DMA_INT_INT14_MASK (0x4000U)

#define	DMA_INT_INT14_SHIFT (14U)

#define	DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

#define	DMA_INT_INT15_MASK (0x8000U)

#define	DMA_INT_INT15_SHIFT (15U)

#define	DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

#define	DMA_INT_INT16_MASK (0x10000U)

#define	DMA_INT_INT16_SHIFT (16U)

#define	DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

#define	DMA_INT_INT17_MASK (0x20000U)

#define	DMA_INT_INT17_SHIFT (17U)

#define	DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

#define	DMA_INT_INT18_MASK (0x40000U)

#define	DMA_INT_INT18_SHIFT (18U)

#define	DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

#define	DMA_INT_INT19_MASK (0x80000U)

#define	DMA_INT_INT19_SHIFT (19U)

#define	DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

#define	DMA_INT_INT20_MASK (0x100000U)

#define	DMA_INT_INT20_SHIFT (20U)

#define	DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

#define	DMA_INT_INT21_MASK (0x200000U)

#define	DMA_INT_INT21_SHIFT (21U)

#define	DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

#define	DMA_INT_INT22_MASK (0x400000U)

#define	DMA_INT_INT22_SHIFT (22U)

#define	DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

#define	DMA_INT_INT23_MASK (0x800000U)

#define	DMA_INT_INT23_SHIFT (23U)

#define	DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

#define	DMA_INT_INT24_MASK (0x1000000U)

#define	DMA_INT_INT24_SHIFT (24U)

#define	DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

#define	DMA_INT_INT25_MASK (0x2000000U)

#define	DMA_INT_INT25_SHIFT (25U)

#define	DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

#define	DMA_INT_INT26_MASK (0x4000000U)

#define	DMA_INT_INT26_SHIFT (26U)

#define	DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

#define	DMA_INT_INT27_MASK (0x8000000U)

#define	DMA_INT_INT27_SHIFT (27U)

#define	DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

#define	DMA_INT_INT28_MASK (0x10000000U)

#define	DMA_INT_INT28_SHIFT (28U)

#define	DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

#define	DMA_INT_INT29_MASK (0x20000000U)

#define	DMA_INT_INT29_SHIFT (29U)

#define	DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

#define	DMA_INT_INT30_MASK (0x40000000U)

#define	DMA_INT_INT30_SHIFT (30U)

#define	DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

#define	DMA_INT_INT31_MASK (0x80000000U)

#define	DMA_INT_INT31_SHIFT (31U)

#define	DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

#define	DMA_INT_INT0_MASK (0x1U)

#define	DMA_INT_INT0_SHIFT (0U)

#define	DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

#define	DMA_INT_INT1_MASK (0x2U)

#define	DMA_INT_INT1_SHIFT (1U)

#define	DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

#define	DMA_INT_INT2_MASK (0x4U)

#define	DMA_INT_INT2_SHIFT (2U)

#define	DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

#define	DMA_INT_INT3_MASK (0x8U)

#define	DMA_INT_INT3_SHIFT (3U)

#define	DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

#define	DMA_INT_INT4_MASK (0x10U)

#define	DMA_INT_INT4_SHIFT (4U)

#define	DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

#define	DMA_INT_INT5_MASK (0x20U)

#define	DMA_INT_INT5_SHIFT (5U)

#define	DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

#define	DMA_INT_INT6_MASK (0x40U)

#define	DMA_INT_INT6_SHIFT (6U)

#define	DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

#define	DMA_INT_INT7_MASK (0x80U)

#define	DMA_INT_INT7_SHIFT (7U)

#define	DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

#define	DMA_INT_INT8_MASK (0x100U)

#define	DMA_INT_INT8_SHIFT (8U)

#define	DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

#define	DMA_INT_INT9_MASK (0x200U)

#define	DMA_INT_INT9_SHIFT (9U)

#define	DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

#define	DMA_INT_INT10_MASK (0x400U)

#define	DMA_INT_INT10_SHIFT (10U)

#define	DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

#define	DMA_INT_INT11_MASK (0x800U)

#define	DMA_INT_INT11_SHIFT (11U)

#define	DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

#define	DMA_INT_INT12_MASK (0x1000U)

#define	DMA_INT_INT12_SHIFT (12U)

#define	DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

#define	DMA_INT_INT13_MASK (0x2000U)

#define	DMA_INT_INT13_SHIFT (13U)

#define	DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

#define	DMA_INT_INT14_MASK (0x4000U)

#define	DMA_INT_INT14_SHIFT (14U)

#define	DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

#define	DMA_INT_INT15_MASK (0x8000U)

#define	DMA_INT_INT15_SHIFT (15U)

#define	DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

#define	DMA_INT_INT16_MASK (0x10000U)

#define	DMA_INT_INT16_SHIFT (16U)

#define	DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

#define	DMA_INT_INT17_MASK (0x20000U)

#define	DMA_INT_INT17_SHIFT (17U)

#define	DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

#define	DMA_INT_INT18_MASK (0x40000U)

#define	DMA_INT_INT18_SHIFT (18U)

#define	DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

#define	DMA_INT_INT19_MASK (0x80000U)

#define	DMA_INT_INT19_SHIFT (19U)

#define	DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

#define	DMA_INT_INT20_MASK (0x100000U)

#define	DMA_INT_INT20_SHIFT (20U)

#define	DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

#define	DMA_INT_INT21_MASK (0x200000U)

#define	DMA_INT_INT21_SHIFT (21U)

#define	DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

#define	DMA_INT_INT22_MASK (0x400000U)

#define	DMA_INT_INT22_SHIFT (22U)

#define	DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

#define	DMA_INT_INT23_MASK (0x800000U)

#define	DMA_INT_INT23_SHIFT (23U)

#define	DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

#define	DMA_INT_INT24_MASK (0x1000000U)

#define	DMA_INT_INT24_SHIFT (24U)

#define	DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

#define	DMA_INT_INT25_MASK (0x2000000U)

#define	DMA_INT_INT25_SHIFT (25U)

#define	DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

#define	DMA_INT_INT26_MASK (0x4000000U)

#define	DMA_INT_INT26_SHIFT (26U)

#define	DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

#define	DMA_INT_INT27_MASK (0x8000000U)

#define	DMA_INT_INT27_SHIFT (27U)

#define	DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

#define	DMA_INT_INT28_MASK (0x10000000U)

#define	DMA_INT_INT28_SHIFT (28U)

#define	DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

#define	DMA_INT_INT29_MASK (0x20000000U)

#define	DMA_INT_INT29_SHIFT (29U)

#define	DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

#define	DMA_INT_INT30_MASK (0x40000000U)

#define	DMA_INT_INT30_SHIFT (30U)

#define	DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

#define	DMA_INT_INT31_MASK (0x80000000U)

#define	DMA_INT_INT31_SHIFT (31U)

#define	DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

#define	DMA_INT_INT0_MASK (0x1U)

#define	DMA_INT_INT0_SHIFT (0U)

#define	DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

#define	DMA_INT_INT1_MASK (0x2U)

#define	DMA_INT_INT1_SHIFT (1U)

#define	DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

#define	DMA_INT_INT2_MASK (0x4U)

#define	DMA_INT_INT2_SHIFT (2U)

#define	DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

#define	DMA_INT_INT3_MASK (0x8U)

#define	DMA_INT_INT3_SHIFT (3U)

#define	DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

#define	DMA_INT_INT4_MASK (0x10U)

#define	DMA_INT_INT4_SHIFT (4U)

#define	DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

#define	DMA_INT_INT5_MASK (0x20U)

#define	DMA_INT_INT5_SHIFT (5U)

#define	DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

#define	DMA_INT_INT6_MASK (0x40U)

#define	DMA_INT_INT6_SHIFT (6U)

#define	DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

#define	DMA_INT_INT7_MASK (0x80U)

#define	DMA_INT_INT7_SHIFT (7U)

#define	DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

#define	DMA_INT_INT8_MASK (0x100U)

#define	DMA_INT_INT8_SHIFT (8U)

#define	DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

#define	DMA_INT_INT9_MASK (0x200U)

#define	DMA_INT_INT9_SHIFT (9U)

#define	DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

#define	DMA_INT_INT10_MASK (0x400U)

#define	DMA_INT_INT10_SHIFT (10U)

#define	DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

#define	DMA_INT_INT11_MASK (0x800U)

#define	DMA_INT_INT11_SHIFT (11U)

#define	DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

#define	DMA_INT_INT12_MASK (0x1000U)

#define	DMA_INT_INT12_SHIFT (12U)

#define	DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

#define	DMA_INT_INT13_MASK (0x2000U)

#define	DMA_INT_INT13_SHIFT (13U)

#define	DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

#define	DMA_INT_INT14_MASK (0x4000U)

#define	DMA_INT_INT14_SHIFT (14U)

#define	DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

#define	DMA_INT_INT15_MASK (0x8000U)

#define	DMA_INT_INT15_SHIFT (15U)

#define	DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

#define	DMA_INT_INT16_MASK (0x10000U)

#define	DMA_INT_INT16_SHIFT (16U)

#define	DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

#define	DMA_INT_INT17_MASK (0x20000U)

#define	DMA_INT_INT17_SHIFT (17U)

#define	DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

#define	DMA_INT_INT18_MASK (0x40000U)

#define	DMA_INT_INT18_SHIFT (18U)

#define	DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

#define	DMA_INT_INT19_MASK (0x80000U)

#define	DMA_INT_INT19_SHIFT (19U)

#define	DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

#define	DMA_INT_INT20_MASK (0x100000U)

#define	DMA_INT_INT20_SHIFT (20U)

#define	DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

#define	DMA_INT_INT21_MASK (0x200000U)

#define	DMA_INT_INT21_SHIFT (21U)

#define	DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

#define	DMA_INT_INT22_MASK (0x400000U)

#define	DMA_INT_INT22_SHIFT (22U)

#define	DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

#define	DMA_INT_INT23_MASK (0x800000U)

#define	DMA_INT_INT23_SHIFT (23U)

#define	DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

#define	DMA_INT_INT24_MASK (0x1000000U)

#define	DMA_INT_INT24_SHIFT (24U)

#define	DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

#define	DMA_INT_INT25_MASK (0x2000000U)

#define	DMA_INT_INT25_SHIFT (25U)

#define	DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

#define	DMA_INT_INT26_MASK (0x4000000U)

#define	DMA_INT_INT26_SHIFT (26U)

#define	DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

#define	DMA_INT_INT27_MASK (0x8000000U)

#define	DMA_INT_INT27_SHIFT (27U)

#define	DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

#define	DMA_INT_INT28_MASK (0x10000000U)

#define	DMA_INT_INT28_SHIFT (28U)

#define	DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

#define	DMA_INT_INT29_MASK (0x20000000U)

#define	DMA_INT_INT29_SHIFT (29U)

#define	DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

#define	DMA_INT_INT30_MASK (0x40000000U)

#define	DMA_INT_INT30_SHIFT (30U)

#define	DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

#define	DMA_INT_INT31_MASK (0x80000000U)

#define	DMA_INT_INT31_SHIFT (31U)

#define	DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

ERR - Error Register
#define	DMA_ERR_ERR0_MASK (0x1U)

#define	DMA_ERR_ERR0_SHIFT (0U)

#define	DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

#define	DMA_ERR_ERR1_MASK (0x2U)

#define	DMA_ERR_ERR1_SHIFT (1U)

#define	DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

#define	DMA_ERR_ERR2_MASK (0x4U)

#define	DMA_ERR_ERR2_SHIFT (2U)

#define	DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

#define	DMA_ERR_ERR3_MASK (0x8U)

#define	DMA_ERR_ERR3_SHIFT (3U)

#define	DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

#define	DMA_ERR_ERR4_MASK (0x10U)

#define	DMA_ERR_ERR4_SHIFT (4U)

#define	DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

#define	DMA_ERR_ERR5_MASK (0x20U)

#define	DMA_ERR_ERR5_SHIFT (5U)

#define	DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

#define	DMA_ERR_ERR6_MASK (0x40U)

#define	DMA_ERR_ERR6_SHIFT (6U)

#define	DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

#define	DMA_ERR_ERR7_MASK (0x80U)

#define	DMA_ERR_ERR7_SHIFT (7U)

#define	DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

#define	DMA_ERR_ERR8_MASK (0x100U)

#define	DMA_ERR_ERR8_SHIFT (8U)

#define	DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

#define	DMA_ERR_ERR9_MASK (0x200U)

#define	DMA_ERR_ERR9_SHIFT (9U)

#define	DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

#define	DMA_ERR_ERR10_MASK (0x400U)

#define	DMA_ERR_ERR10_SHIFT (10U)

#define	DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

#define	DMA_ERR_ERR11_MASK (0x800U)

#define	DMA_ERR_ERR11_SHIFT (11U)

#define	DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

#define	DMA_ERR_ERR12_MASK (0x1000U)

#define	DMA_ERR_ERR12_SHIFT (12U)

#define	DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

#define	DMA_ERR_ERR13_MASK (0x2000U)

#define	DMA_ERR_ERR13_SHIFT (13U)

#define	DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

#define	DMA_ERR_ERR14_MASK (0x4000U)

#define	DMA_ERR_ERR14_SHIFT (14U)

#define	DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

#define	DMA_ERR_ERR15_MASK (0x8000U)

#define	DMA_ERR_ERR15_SHIFT (15U)

#define	DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

#define	DMA_ERR_ERR0_MASK 0x1u

#define	DMA_ERR_ERR0_SHIFT 0

#define	DMA_ERR_ERR1_MASK 0x2u

#define	DMA_ERR_ERR1_SHIFT 1

#define	DMA_ERR_ERR2_MASK 0x4u

#define	DMA_ERR_ERR2_SHIFT 2

#define	DMA_ERR_ERR3_MASK 0x8u

#define	DMA_ERR_ERR3_SHIFT 3

#define	DMA_ERR_ERR4_MASK 0x10u

#define	DMA_ERR_ERR4_SHIFT 4

#define	DMA_ERR_ERR5_MASK 0x20u

#define	DMA_ERR_ERR5_SHIFT 5

#define	DMA_ERR_ERR6_MASK 0x40u

#define	DMA_ERR_ERR6_SHIFT 6

#define	DMA_ERR_ERR7_MASK 0x80u

#define	DMA_ERR_ERR7_SHIFT 7

#define	DMA_ERR_ERR8_MASK 0x100u

#define	DMA_ERR_ERR8_SHIFT 8

#define	DMA_ERR_ERR9_MASK 0x200u

#define	DMA_ERR_ERR9_SHIFT 9

#define	DMA_ERR_ERR10_MASK 0x400u

#define	DMA_ERR_ERR10_SHIFT 10

#define	DMA_ERR_ERR11_MASK 0x800u

#define	DMA_ERR_ERR11_SHIFT 11

#define	DMA_ERR_ERR12_MASK 0x1000u

#define	DMA_ERR_ERR12_SHIFT 12

#define	DMA_ERR_ERR13_MASK 0x2000u

#define	DMA_ERR_ERR13_SHIFT 13

#define	DMA_ERR_ERR14_MASK 0x4000u

#define	DMA_ERR_ERR14_SHIFT 14

#define	DMA_ERR_ERR15_MASK 0x8000u

#define	DMA_ERR_ERR15_SHIFT 15

#define	DMA_ERR_ERR0_MASK (0x1U)

#define	DMA_ERR_ERR0_SHIFT (0U)

#define	DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

#define	DMA_ERR_ERR1_MASK (0x2U)

#define	DMA_ERR_ERR1_SHIFT (1U)

#define	DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

#define	DMA_ERR_ERR2_MASK (0x4U)

#define	DMA_ERR_ERR2_SHIFT (2U)

#define	DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

#define	DMA_ERR_ERR3_MASK (0x8U)

#define	DMA_ERR_ERR3_SHIFT (3U)

#define	DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

#define	DMA_ERR_ERR4_MASK (0x10U)

#define	DMA_ERR_ERR4_SHIFT (4U)

#define	DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

#define	DMA_ERR_ERR5_MASK (0x20U)

#define	DMA_ERR_ERR5_SHIFT (5U)

#define	DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

#define	DMA_ERR_ERR6_MASK (0x40U)

#define	DMA_ERR_ERR6_SHIFT (6U)

#define	DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

#define	DMA_ERR_ERR7_MASK (0x80U)

#define	DMA_ERR_ERR7_SHIFT (7U)

#define	DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

#define	DMA_ERR_ERR8_MASK (0x100U)

#define	DMA_ERR_ERR8_SHIFT (8U)

#define	DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

#define	DMA_ERR_ERR9_MASK (0x200U)

#define	DMA_ERR_ERR9_SHIFT (9U)

#define	DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

#define	DMA_ERR_ERR10_MASK (0x400U)

#define	DMA_ERR_ERR10_SHIFT (10U)

#define	DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

#define	DMA_ERR_ERR11_MASK (0x800U)

#define	DMA_ERR_ERR11_SHIFT (11U)

#define	DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

#define	DMA_ERR_ERR12_MASK (0x1000U)

#define	DMA_ERR_ERR12_SHIFT (12U)

#define	DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

#define	DMA_ERR_ERR13_MASK (0x2000U)

#define	DMA_ERR_ERR13_SHIFT (13U)

#define	DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

#define	DMA_ERR_ERR14_MASK (0x4000U)

#define	DMA_ERR_ERR14_SHIFT (14U)

#define	DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

#define	DMA_ERR_ERR15_MASK (0x8000U)

#define	DMA_ERR_ERR15_SHIFT (15U)

#define	DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

#define	DMA_ERR_ERR0_MASK (0x1U)

#define	DMA_ERR_ERR0_SHIFT (0U)

#define	DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

#define	DMA_ERR_ERR1_MASK (0x2U)

#define	DMA_ERR_ERR1_SHIFT (1U)

#define	DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

#define	DMA_ERR_ERR2_MASK (0x4U)

#define	DMA_ERR_ERR2_SHIFT (2U)

#define	DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

#define	DMA_ERR_ERR3_MASK (0x8U)

#define	DMA_ERR_ERR3_SHIFT (3U)

#define	DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

#define	DMA_ERR_ERR4_MASK (0x10U)

#define	DMA_ERR_ERR4_SHIFT (4U)

#define	DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

#define	DMA_ERR_ERR5_MASK (0x20U)

#define	DMA_ERR_ERR5_SHIFT (5U)

#define	DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

#define	DMA_ERR_ERR6_MASK (0x40U)

#define	DMA_ERR_ERR6_SHIFT (6U)

#define	DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

#define	DMA_ERR_ERR7_MASK (0x80U)

#define	DMA_ERR_ERR7_SHIFT (7U)

#define	DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

#define	DMA_ERR_ERR8_MASK (0x100U)

#define	DMA_ERR_ERR8_SHIFT (8U)

#define	DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

#define	DMA_ERR_ERR9_MASK (0x200U)

#define	DMA_ERR_ERR9_SHIFT (9U)

#define	DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

#define	DMA_ERR_ERR10_MASK (0x400U)

#define	DMA_ERR_ERR10_SHIFT (10U)

#define	DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

#define	DMA_ERR_ERR11_MASK (0x800U)

#define	DMA_ERR_ERR11_SHIFT (11U)

#define	DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

#define	DMA_ERR_ERR12_MASK (0x1000U)

#define	DMA_ERR_ERR12_SHIFT (12U)

#define	DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

#define	DMA_ERR_ERR13_MASK (0x2000U)

#define	DMA_ERR_ERR13_SHIFT (13U)

#define	DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

#define	DMA_ERR_ERR14_MASK (0x4000U)

#define	DMA_ERR_ERR14_SHIFT (14U)

#define	DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

#define	DMA_ERR_ERR15_MASK (0x8000U)

#define	DMA_ERR_ERR15_SHIFT (15U)

#define	DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

#define	DMA_ERR_ERR16_MASK (0x10000U)

#define	DMA_ERR_ERR16_SHIFT (16U)

#define	DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

#define	DMA_ERR_ERR17_MASK (0x20000U)

#define	DMA_ERR_ERR17_SHIFT (17U)

#define	DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

#define	DMA_ERR_ERR18_MASK (0x40000U)

#define	DMA_ERR_ERR18_SHIFT (18U)

#define	DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

#define	DMA_ERR_ERR19_MASK (0x80000U)

#define	DMA_ERR_ERR19_SHIFT (19U)

#define	DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

#define	DMA_ERR_ERR20_MASK (0x100000U)

#define	DMA_ERR_ERR20_SHIFT (20U)

#define	DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

#define	DMA_ERR_ERR21_MASK (0x200000U)

#define	DMA_ERR_ERR21_SHIFT (21U)

#define	DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

#define	DMA_ERR_ERR22_MASK (0x400000U)

#define	DMA_ERR_ERR22_SHIFT (22U)

#define	DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

#define	DMA_ERR_ERR23_MASK (0x800000U)

#define	DMA_ERR_ERR23_SHIFT (23U)

#define	DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

#define	DMA_ERR_ERR24_MASK (0x1000000U)

#define	DMA_ERR_ERR24_SHIFT (24U)

#define	DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

#define	DMA_ERR_ERR25_MASK (0x2000000U)

#define	DMA_ERR_ERR25_SHIFT (25U)

#define	DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

#define	DMA_ERR_ERR26_MASK (0x4000000U)

#define	DMA_ERR_ERR26_SHIFT (26U)

#define	DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

#define	DMA_ERR_ERR27_MASK (0x8000000U)

#define	DMA_ERR_ERR27_SHIFT (27U)

#define	DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

#define	DMA_ERR_ERR28_MASK (0x10000000U)

#define	DMA_ERR_ERR28_SHIFT (28U)

#define	DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

#define	DMA_ERR_ERR29_MASK (0x20000000U)

#define	DMA_ERR_ERR29_SHIFT (29U)

#define	DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

#define	DMA_ERR_ERR30_MASK (0x40000000U)

#define	DMA_ERR_ERR30_SHIFT (30U)

#define	DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

#define	DMA_ERR_ERR31_MASK (0x80000000U)

#define	DMA_ERR_ERR31_SHIFT (31U)

#define	DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

#define	DMA_ERR_ERR0_MASK (0x1U)

#define	DMA_ERR_ERR0_SHIFT (0U)

#define	DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

#define	DMA_ERR_ERR1_MASK (0x2U)

#define	DMA_ERR_ERR1_SHIFT (1U)

#define	DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

#define	DMA_ERR_ERR2_MASK (0x4U)

#define	DMA_ERR_ERR2_SHIFT (2U)

#define	DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

#define	DMA_ERR_ERR3_MASK (0x8U)

#define	DMA_ERR_ERR3_SHIFT (3U)

#define	DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

#define	DMA_ERR_ERR4_MASK (0x10U)

#define	DMA_ERR_ERR4_SHIFT (4U)

#define	DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

#define	DMA_ERR_ERR5_MASK (0x20U)

#define	DMA_ERR_ERR5_SHIFT (5U)

#define	DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

#define	DMA_ERR_ERR6_MASK (0x40U)

#define	DMA_ERR_ERR6_SHIFT (6U)

#define	DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

#define	DMA_ERR_ERR7_MASK (0x80U)

#define	DMA_ERR_ERR7_SHIFT (7U)

#define	DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

#define	DMA_ERR_ERR8_MASK (0x100U)

#define	DMA_ERR_ERR8_SHIFT (8U)

#define	DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

#define	DMA_ERR_ERR9_MASK (0x200U)

#define	DMA_ERR_ERR9_SHIFT (9U)

#define	DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

#define	DMA_ERR_ERR10_MASK (0x400U)

#define	DMA_ERR_ERR10_SHIFT (10U)

#define	DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

#define	DMA_ERR_ERR11_MASK (0x800U)

#define	DMA_ERR_ERR11_SHIFT (11U)

#define	DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

#define	DMA_ERR_ERR12_MASK (0x1000U)

#define	DMA_ERR_ERR12_SHIFT (12U)

#define	DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

#define	DMA_ERR_ERR13_MASK (0x2000U)

#define	DMA_ERR_ERR13_SHIFT (13U)

#define	DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

#define	DMA_ERR_ERR14_MASK (0x4000U)

#define	DMA_ERR_ERR14_SHIFT (14U)

#define	DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

#define	DMA_ERR_ERR15_MASK (0x8000U)

#define	DMA_ERR_ERR15_SHIFT (15U)

#define	DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

#define	DMA_ERR_ERR16_MASK (0x10000U)

#define	DMA_ERR_ERR16_SHIFT (16U)

#define	DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

#define	DMA_ERR_ERR17_MASK (0x20000U)

#define	DMA_ERR_ERR17_SHIFT (17U)

#define	DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

#define	DMA_ERR_ERR18_MASK (0x40000U)

#define	DMA_ERR_ERR18_SHIFT (18U)

#define	DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

#define	DMA_ERR_ERR19_MASK (0x80000U)

#define	DMA_ERR_ERR19_SHIFT (19U)

#define	DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

#define	DMA_ERR_ERR20_MASK (0x100000U)

#define	DMA_ERR_ERR20_SHIFT (20U)

#define	DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

#define	DMA_ERR_ERR21_MASK (0x200000U)

#define	DMA_ERR_ERR21_SHIFT (21U)

#define	DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

#define	DMA_ERR_ERR22_MASK (0x400000U)

#define	DMA_ERR_ERR22_SHIFT (22U)

#define	DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

#define	DMA_ERR_ERR23_MASK (0x800000U)

#define	DMA_ERR_ERR23_SHIFT (23U)

#define	DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

#define	DMA_ERR_ERR24_MASK (0x1000000U)

#define	DMA_ERR_ERR24_SHIFT (24U)

#define	DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

#define	DMA_ERR_ERR25_MASK (0x2000000U)

#define	DMA_ERR_ERR25_SHIFT (25U)

#define	DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

#define	DMA_ERR_ERR26_MASK (0x4000000U)

#define	DMA_ERR_ERR26_SHIFT (26U)

#define	DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

#define	DMA_ERR_ERR27_MASK (0x8000000U)

#define	DMA_ERR_ERR27_SHIFT (27U)

#define	DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

#define	DMA_ERR_ERR28_MASK (0x10000000U)

#define	DMA_ERR_ERR28_SHIFT (28U)

#define	DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

#define	DMA_ERR_ERR29_MASK (0x20000000U)

#define	DMA_ERR_ERR29_SHIFT (29U)

#define	DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

#define	DMA_ERR_ERR30_MASK (0x40000000U)

#define	DMA_ERR_ERR30_SHIFT (30U)

#define	DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

#define	DMA_ERR_ERR31_MASK (0x80000000U)

#define	DMA_ERR_ERR31_SHIFT (31U)

#define	DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

#define	DMA_ERR_ERR0_MASK (0x1U)

#define	DMA_ERR_ERR0_SHIFT (0U)

#define	DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

#define	DMA_ERR_ERR1_MASK (0x2U)

#define	DMA_ERR_ERR1_SHIFT (1U)

#define	DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

#define	DMA_ERR_ERR2_MASK (0x4U)

#define	DMA_ERR_ERR2_SHIFT (2U)

#define	DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

#define	DMA_ERR_ERR3_MASK (0x8U)

#define	DMA_ERR_ERR3_SHIFT (3U)

#define	DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

#define	DMA_ERR_ERR4_MASK (0x10U)

#define	DMA_ERR_ERR4_SHIFT (4U)

#define	DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

#define	DMA_ERR_ERR5_MASK (0x20U)

#define	DMA_ERR_ERR5_SHIFT (5U)

#define	DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

#define	DMA_ERR_ERR6_MASK (0x40U)

#define	DMA_ERR_ERR6_SHIFT (6U)

#define	DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

#define	DMA_ERR_ERR7_MASK (0x80U)

#define	DMA_ERR_ERR7_SHIFT (7U)

#define	DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

#define	DMA_ERR_ERR8_MASK (0x100U)

#define	DMA_ERR_ERR8_SHIFT (8U)

#define	DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

#define	DMA_ERR_ERR9_MASK (0x200U)

#define	DMA_ERR_ERR9_SHIFT (9U)

#define	DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

#define	DMA_ERR_ERR10_MASK (0x400U)

#define	DMA_ERR_ERR10_SHIFT (10U)

#define	DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

#define	DMA_ERR_ERR11_MASK (0x800U)

#define	DMA_ERR_ERR11_SHIFT (11U)

#define	DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

#define	DMA_ERR_ERR12_MASK (0x1000U)

#define	DMA_ERR_ERR12_SHIFT (12U)

#define	DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

#define	DMA_ERR_ERR13_MASK (0x2000U)

#define	DMA_ERR_ERR13_SHIFT (13U)

#define	DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

#define	DMA_ERR_ERR14_MASK (0x4000U)

#define	DMA_ERR_ERR14_SHIFT (14U)

#define	DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

#define	DMA_ERR_ERR15_MASK (0x8000U)

#define	DMA_ERR_ERR15_SHIFT (15U)

#define	DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

#define	DMA_ERR_ERR16_MASK (0x10000U)

#define	DMA_ERR_ERR16_SHIFT (16U)

#define	DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

#define	DMA_ERR_ERR17_MASK (0x20000U)

#define	DMA_ERR_ERR17_SHIFT (17U)

#define	DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

#define	DMA_ERR_ERR18_MASK (0x40000U)

#define	DMA_ERR_ERR18_SHIFT (18U)

#define	DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

#define	DMA_ERR_ERR19_MASK (0x80000U)

#define	DMA_ERR_ERR19_SHIFT (19U)

#define	DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

#define	DMA_ERR_ERR20_MASK (0x100000U)

#define	DMA_ERR_ERR20_SHIFT (20U)

#define	DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

#define	DMA_ERR_ERR21_MASK (0x200000U)

#define	DMA_ERR_ERR21_SHIFT (21U)

#define	DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

#define	DMA_ERR_ERR22_MASK (0x400000U)

#define	DMA_ERR_ERR22_SHIFT (22U)

#define	DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

#define	DMA_ERR_ERR23_MASK (0x800000U)

#define	DMA_ERR_ERR23_SHIFT (23U)

#define	DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

#define	DMA_ERR_ERR24_MASK (0x1000000U)

#define	DMA_ERR_ERR24_SHIFT (24U)

#define	DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

#define	DMA_ERR_ERR25_MASK (0x2000000U)

#define	DMA_ERR_ERR25_SHIFT (25U)

#define	DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

#define	DMA_ERR_ERR26_MASK (0x4000000U)

#define	DMA_ERR_ERR26_SHIFT (26U)

#define	DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

#define	DMA_ERR_ERR27_MASK (0x8000000U)

#define	DMA_ERR_ERR27_SHIFT (27U)

#define	DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

#define	DMA_ERR_ERR28_MASK (0x10000000U)

#define	DMA_ERR_ERR28_SHIFT (28U)

#define	DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

#define	DMA_ERR_ERR29_MASK (0x20000000U)

#define	DMA_ERR_ERR29_SHIFT (29U)

#define	DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

#define	DMA_ERR_ERR30_MASK (0x40000000U)

#define	DMA_ERR_ERR30_SHIFT (30U)

#define	DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

#define	DMA_ERR_ERR31_MASK (0x80000000U)

#define	DMA_ERR_ERR31_SHIFT (31U)

#define	DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

HRS - Hardware Request Status Register
#define	DMA_HRS_HRS0_MASK (0x1U)

#define	DMA_HRS_HRS0_SHIFT (0U)

#define	DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

#define	DMA_HRS_HRS1_MASK (0x2U)

#define	DMA_HRS_HRS1_SHIFT (1U)

#define	DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

#define	DMA_HRS_HRS2_MASK (0x4U)

#define	DMA_HRS_HRS2_SHIFT (2U)

#define	DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

#define	DMA_HRS_HRS3_MASK (0x8U)

#define	DMA_HRS_HRS3_SHIFT (3U)

#define	DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

#define	DMA_HRS_HRS4_MASK (0x10U)

#define	DMA_HRS_HRS4_SHIFT (4U)

#define	DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

#define	DMA_HRS_HRS5_MASK (0x20U)

#define	DMA_HRS_HRS5_SHIFT (5U)

#define	DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

#define	DMA_HRS_HRS6_MASK (0x40U)

#define	DMA_HRS_HRS6_SHIFT (6U)

#define	DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

#define	DMA_HRS_HRS7_MASK (0x80U)

#define	DMA_HRS_HRS7_SHIFT (7U)

#define	DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

#define	DMA_HRS_HRS8_MASK (0x100U)

#define	DMA_HRS_HRS8_SHIFT (8U)

#define	DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

#define	DMA_HRS_HRS9_MASK (0x200U)

#define	DMA_HRS_HRS9_SHIFT (9U)

#define	DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

#define	DMA_HRS_HRS10_MASK (0x400U)

#define	DMA_HRS_HRS10_SHIFT (10U)

#define	DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

#define	DMA_HRS_HRS11_MASK (0x800U)

#define	DMA_HRS_HRS11_SHIFT (11U)

#define	DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

#define	DMA_HRS_HRS12_MASK (0x1000U)

#define	DMA_HRS_HRS12_SHIFT (12U)

#define	DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

#define	DMA_HRS_HRS13_MASK (0x2000U)

#define	DMA_HRS_HRS13_SHIFT (13U)

#define	DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

#define	DMA_HRS_HRS14_MASK (0x4000U)

#define	DMA_HRS_HRS14_SHIFT (14U)

#define	DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

#define	DMA_HRS_HRS15_MASK (0x8000U)

#define	DMA_HRS_HRS15_SHIFT (15U)

#define	DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

#define	DMA_HRS_HRS0_MASK 0x1u

#define	DMA_HRS_HRS0_SHIFT 0

#define	DMA_HRS_HRS1_MASK 0x2u

#define	DMA_HRS_HRS1_SHIFT 1

#define	DMA_HRS_HRS2_MASK 0x4u

#define	DMA_HRS_HRS2_SHIFT 2

#define	DMA_HRS_HRS3_MASK 0x8u

#define	DMA_HRS_HRS3_SHIFT 3

#define	DMA_HRS_HRS4_MASK 0x10u

#define	DMA_HRS_HRS4_SHIFT 4

#define	DMA_HRS_HRS5_MASK 0x20u

#define	DMA_HRS_HRS5_SHIFT 5

#define	DMA_HRS_HRS6_MASK 0x40u

#define	DMA_HRS_HRS6_SHIFT 6

#define	DMA_HRS_HRS7_MASK 0x80u

#define	DMA_HRS_HRS7_SHIFT 7

#define	DMA_HRS_HRS8_MASK 0x100u

#define	DMA_HRS_HRS8_SHIFT 8

#define	DMA_HRS_HRS9_MASK 0x200u

#define	DMA_HRS_HRS9_SHIFT 9

#define	DMA_HRS_HRS10_MASK 0x400u

#define	DMA_HRS_HRS10_SHIFT 10

#define	DMA_HRS_HRS11_MASK 0x800u

#define	DMA_HRS_HRS11_SHIFT 11

#define	DMA_HRS_HRS12_MASK 0x1000u

#define	DMA_HRS_HRS12_SHIFT 12

#define	DMA_HRS_HRS13_MASK 0x2000u

#define	DMA_HRS_HRS13_SHIFT 13

#define	DMA_HRS_HRS14_MASK 0x4000u

#define	DMA_HRS_HRS14_SHIFT 14

#define	DMA_HRS_HRS15_MASK 0x8000u

#define	DMA_HRS_HRS15_SHIFT 15

#define	DMA_HRS_HRS0_MASK (0x1U)

#define	DMA_HRS_HRS0_SHIFT (0U)

#define	DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

#define	DMA_HRS_HRS1_MASK (0x2U)

#define	DMA_HRS_HRS1_SHIFT (1U)

#define	DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

#define	DMA_HRS_HRS2_MASK (0x4U)

#define	DMA_HRS_HRS2_SHIFT (2U)

#define	DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

#define	DMA_HRS_HRS3_MASK (0x8U)

#define	DMA_HRS_HRS3_SHIFT (3U)

#define	DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

#define	DMA_HRS_HRS4_MASK (0x10U)

#define	DMA_HRS_HRS4_SHIFT (4U)

#define	DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

#define	DMA_HRS_HRS5_MASK (0x20U)

#define	DMA_HRS_HRS5_SHIFT (5U)

#define	DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

#define	DMA_HRS_HRS6_MASK (0x40U)

#define	DMA_HRS_HRS6_SHIFT (6U)

#define	DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

#define	DMA_HRS_HRS7_MASK (0x80U)

#define	DMA_HRS_HRS7_SHIFT (7U)

#define	DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

#define	DMA_HRS_HRS8_MASK (0x100U)

#define	DMA_HRS_HRS8_SHIFT (8U)

#define	DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

#define	DMA_HRS_HRS9_MASK (0x200U)

#define	DMA_HRS_HRS9_SHIFT (9U)

#define	DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

#define	DMA_HRS_HRS10_MASK (0x400U)

#define	DMA_HRS_HRS10_SHIFT (10U)

#define	DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

#define	DMA_HRS_HRS11_MASK (0x800U)

#define	DMA_HRS_HRS11_SHIFT (11U)

#define	DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

#define	DMA_HRS_HRS12_MASK (0x1000U)

#define	DMA_HRS_HRS12_SHIFT (12U)

#define	DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

#define	DMA_HRS_HRS13_MASK (0x2000U)

#define	DMA_HRS_HRS13_SHIFT (13U)

#define	DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

#define	DMA_HRS_HRS14_MASK (0x4000U)

#define	DMA_HRS_HRS14_SHIFT (14U)

#define	DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

#define	DMA_HRS_HRS15_MASK (0x8000U)

#define	DMA_HRS_HRS15_SHIFT (15U)

#define	DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

#define	DMA_HRS_HRS0_MASK (0x1U)

#define	DMA_HRS_HRS0_SHIFT (0U)

#define	DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

#define	DMA_HRS_HRS1_MASK (0x2U)

#define	DMA_HRS_HRS1_SHIFT (1U)

#define	DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

#define	DMA_HRS_HRS2_MASK (0x4U)

#define	DMA_HRS_HRS2_SHIFT (2U)

#define	DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

#define	DMA_HRS_HRS3_MASK (0x8U)

#define	DMA_HRS_HRS3_SHIFT (3U)

#define	DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

#define	DMA_HRS_HRS4_MASK (0x10U)

#define	DMA_HRS_HRS4_SHIFT (4U)

#define	DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

#define	DMA_HRS_HRS5_MASK (0x20U)

#define	DMA_HRS_HRS5_SHIFT (5U)

#define	DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

#define	DMA_HRS_HRS6_MASK (0x40U)

#define	DMA_HRS_HRS6_SHIFT (6U)

#define	DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

#define	DMA_HRS_HRS7_MASK (0x80U)

#define	DMA_HRS_HRS7_SHIFT (7U)

#define	DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

#define	DMA_HRS_HRS8_MASK (0x100U)

#define	DMA_HRS_HRS8_SHIFT (8U)

#define	DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

#define	DMA_HRS_HRS9_MASK (0x200U)

#define	DMA_HRS_HRS9_SHIFT (9U)

#define	DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

#define	DMA_HRS_HRS10_MASK (0x400U)

#define	DMA_HRS_HRS10_SHIFT (10U)

#define	DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

#define	DMA_HRS_HRS11_MASK (0x800U)

#define	DMA_HRS_HRS11_SHIFT (11U)

#define	DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

#define	DMA_HRS_HRS12_MASK (0x1000U)

#define	DMA_HRS_HRS12_SHIFT (12U)

#define	DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

#define	DMA_HRS_HRS13_MASK (0x2000U)

#define	DMA_HRS_HRS13_SHIFT (13U)

#define	DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

#define	DMA_HRS_HRS14_MASK (0x4000U)

#define	DMA_HRS_HRS14_SHIFT (14U)

#define	DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

#define	DMA_HRS_HRS15_MASK (0x8000U)

#define	DMA_HRS_HRS15_SHIFT (15U)

#define	DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

#define	DMA_HRS_HRS16_MASK (0x10000U)

#define	DMA_HRS_HRS16_SHIFT (16U)

#define	DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

#define	DMA_HRS_HRS17_MASK (0x20000U)

#define	DMA_HRS_HRS17_SHIFT (17U)

#define	DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

#define	DMA_HRS_HRS18_MASK (0x40000U)

#define	DMA_HRS_HRS18_SHIFT (18U)

#define	DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

#define	DMA_HRS_HRS19_MASK (0x80000U)

#define	DMA_HRS_HRS19_SHIFT (19U)

#define	DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

#define	DMA_HRS_HRS20_MASK (0x100000U)

#define	DMA_HRS_HRS20_SHIFT (20U)

#define	DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

#define	DMA_HRS_HRS21_MASK (0x200000U)

#define	DMA_HRS_HRS21_SHIFT (21U)

#define	DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

#define	DMA_HRS_HRS22_MASK (0x400000U)

#define	DMA_HRS_HRS22_SHIFT (22U)

#define	DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

#define	DMA_HRS_HRS23_MASK (0x800000U)

#define	DMA_HRS_HRS23_SHIFT (23U)

#define	DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

#define	DMA_HRS_HRS24_MASK (0x1000000U)

#define	DMA_HRS_HRS24_SHIFT (24U)

#define	DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

#define	DMA_HRS_HRS25_MASK (0x2000000U)

#define	DMA_HRS_HRS25_SHIFT (25U)

#define	DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

#define	DMA_HRS_HRS26_MASK (0x4000000U)

#define	DMA_HRS_HRS26_SHIFT (26U)

#define	DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

#define	DMA_HRS_HRS27_MASK (0x8000000U)

#define	DMA_HRS_HRS27_SHIFT (27U)

#define	DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

#define	DMA_HRS_HRS28_MASK (0x10000000U)

#define	DMA_HRS_HRS28_SHIFT (28U)

#define	DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

#define	DMA_HRS_HRS29_MASK (0x20000000U)

#define	DMA_HRS_HRS29_SHIFT (29U)

#define	DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

#define	DMA_HRS_HRS30_MASK (0x40000000U)

#define	DMA_HRS_HRS30_SHIFT (30U)

#define	DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

#define	DMA_HRS_HRS31_MASK (0x80000000U)

#define	DMA_HRS_HRS31_SHIFT (31U)

#define	DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

#define	DMA_HRS_HRS0_MASK (0x1U)

#define	DMA_HRS_HRS0_SHIFT (0U)

#define	DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

#define	DMA_HRS_HRS1_MASK (0x2U)

#define	DMA_HRS_HRS1_SHIFT (1U)

#define	DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

#define	DMA_HRS_HRS2_MASK (0x4U)

#define	DMA_HRS_HRS2_SHIFT (2U)

#define	DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

#define	DMA_HRS_HRS3_MASK (0x8U)

#define	DMA_HRS_HRS3_SHIFT (3U)

#define	DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

#define	DMA_HRS_HRS4_MASK (0x10U)

#define	DMA_HRS_HRS4_SHIFT (4U)

#define	DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

#define	DMA_HRS_HRS5_MASK (0x20U)

#define	DMA_HRS_HRS5_SHIFT (5U)

#define	DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

#define	DMA_HRS_HRS6_MASK (0x40U)

#define	DMA_HRS_HRS6_SHIFT (6U)

#define	DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

#define	DMA_HRS_HRS7_MASK (0x80U)

#define	DMA_HRS_HRS7_SHIFT (7U)

#define	DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

#define	DMA_HRS_HRS8_MASK (0x100U)

#define	DMA_HRS_HRS8_SHIFT (8U)

#define	DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

#define	DMA_HRS_HRS9_MASK (0x200U)

#define	DMA_HRS_HRS9_SHIFT (9U)

#define	DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

#define	DMA_HRS_HRS10_MASK (0x400U)

#define	DMA_HRS_HRS10_SHIFT (10U)

#define	DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

#define	DMA_HRS_HRS11_MASK (0x800U)

#define	DMA_HRS_HRS11_SHIFT (11U)

#define	DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

#define	DMA_HRS_HRS12_MASK (0x1000U)

#define	DMA_HRS_HRS12_SHIFT (12U)

#define	DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

#define	DMA_HRS_HRS13_MASK (0x2000U)

#define	DMA_HRS_HRS13_SHIFT (13U)

#define	DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

#define	DMA_HRS_HRS14_MASK (0x4000U)

#define	DMA_HRS_HRS14_SHIFT (14U)

#define	DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

#define	DMA_HRS_HRS15_MASK (0x8000U)

#define	DMA_HRS_HRS15_SHIFT (15U)

#define	DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

#define	DMA_HRS_HRS16_MASK (0x10000U)

#define	DMA_HRS_HRS16_SHIFT (16U)

#define	DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

#define	DMA_HRS_HRS17_MASK (0x20000U)

#define	DMA_HRS_HRS17_SHIFT (17U)

#define	DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

#define	DMA_HRS_HRS18_MASK (0x40000U)

#define	DMA_HRS_HRS18_SHIFT (18U)

#define	DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

#define	DMA_HRS_HRS19_MASK (0x80000U)

#define	DMA_HRS_HRS19_SHIFT (19U)

#define	DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

#define	DMA_HRS_HRS20_MASK (0x100000U)

#define	DMA_HRS_HRS20_SHIFT (20U)

#define	DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

#define	DMA_HRS_HRS21_MASK (0x200000U)

#define	DMA_HRS_HRS21_SHIFT (21U)

#define	DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

#define	DMA_HRS_HRS22_MASK (0x400000U)

#define	DMA_HRS_HRS22_SHIFT (22U)

#define	DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

#define	DMA_HRS_HRS23_MASK (0x800000U)

#define	DMA_HRS_HRS23_SHIFT (23U)

#define	DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

#define	DMA_HRS_HRS24_MASK (0x1000000U)

#define	DMA_HRS_HRS24_SHIFT (24U)

#define	DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

#define	DMA_HRS_HRS25_MASK (0x2000000U)

#define	DMA_HRS_HRS25_SHIFT (25U)

#define	DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

#define	DMA_HRS_HRS26_MASK (0x4000000U)

#define	DMA_HRS_HRS26_SHIFT (26U)

#define	DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

#define	DMA_HRS_HRS27_MASK (0x8000000U)

#define	DMA_HRS_HRS27_SHIFT (27U)

#define	DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

#define	DMA_HRS_HRS28_MASK (0x10000000U)

#define	DMA_HRS_HRS28_SHIFT (28U)

#define	DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

#define	DMA_HRS_HRS29_MASK (0x20000000U)

#define	DMA_HRS_HRS29_SHIFT (29U)

#define	DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

#define	DMA_HRS_HRS30_MASK (0x40000000U)

#define	DMA_HRS_HRS30_SHIFT (30U)

#define	DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

#define	DMA_HRS_HRS31_MASK (0x80000000U)

#define	DMA_HRS_HRS31_SHIFT (31U)

#define	DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

#define	DMA_HRS_HRS0_MASK (0x1U)

#define	DMA_HRS_HRS0_SHIFT (0U)

#define	DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

#define	DMA_HRS_HRS1_MASK (0x2U)

#define	DMA_HRS_HRS1_SHIFT (1U)

#define	DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

#define	DMA_HRS_HRS2_MASK (0x4U)

#define	DMA_HRS_HRS2_SHIFT (2U)

#define	DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

#define	DMA_HRS_HRS3_MASK (0x8U)

#define	DMA_HRS_HRS3_SHIFT (3U)

#define	DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

#define	DMA_HRS_HRS4_MASK (0x10U)

#define	DMA_HRS_HRS4_SHIFT (4U)

#define	DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

#define	DMA_HRS_HRS5_MASK (0x20U)

#define	DMA_HRS_HRS5_SHIFT (5U)

#define	DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

#define	DMA_HRS_HRS6_MASK (0x40U)

#define	DMA_HRS_HRS6_SHIFT (6U)

#define	DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

#define	DMA_HRS_HRS7_MASK (0x80U)

#define	DMA_HRS_HRS7_SHIFT (7U)

#define	DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

#define	DMA_HRS_HRS8_MASK (0x100U)

#define	DMA_HRS_HRS8_SHIFT (8U)

#define	DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

#define	DMA_HRS_HRS9_MASK (0x200U)

#define	DMA_HRS_HRS9_SHIFT (9U)

#define	DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

#define	DMA_HRS_HRS10_MASK (0x400U)

#define	DMA_HRS_HRS10_SHIFT (10U)

#define	DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

#define	DMA_HRS_HRS11_MASK (0x800U)

#define	DMA_HRS_HRS11_SHIFT (11U)

#define	DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

#define	DMA_HRS_HRS12_MASK (0x1000U)

#define	DMA_HRS_HRS12_SHIFT (12U)

#define	DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

#define	DMA_HRS_HRS13_MASK (0x2000U)

#define	DMA_HRS_HRS13_SHIFT (13U)

#define	DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

#define	DMA_HRS_HRS14_MASK (0x4000U)

#define	DMA_HRS_HRS14_SHIFT (14U)

#define	DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

#define	DMA_HRS_HRS15_MASK (0x8000U)

#define	DMA_HRS_HRS15_SHIFT (15U)

#define	DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

#define	DMA_HRS_HRS16_MASK (0x10000U)

#define	DMA_HRS_HRS16_SHIFT (16U)

#define	DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

#define	DMA_HRS_HRS17_MASK (0x20000U)

#define	DMA_HRS_HRS17_SHIFT (17U)

#define	DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

#define	DMA_HRS_HRS18_MASK (0x40000U)

#define	DMA_HRS_HRS18_SHIFT (18U)

#define	DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

#define	DMA_HRS_HRS19_MASK (0x80000U)

#define	DMA_HRS_HRS19_SHIFT (19U)

#define	DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

#define	DMA_HRS_HRS20_MASK (0x100000U)

#define	DMA_HRS_HRS20_SHIFT (20U)

#define	DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

#define	DMA_HRS_HRS21_MASK (0x200000U)

#define	DMA_HRS_HRS21_SHIFT (21U)

#define	DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

#define	DMA_HRS_HRS22_MASK (0x400000U)

#define	DMA_HRS_HRS22_SHIFT (22U)

#define	DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

#define	DMA_HRS_HRS23_MASK (0x800000U)

#define	DMA_HRS_HRS23_SHIFT (23U)

#define	DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

#define	DMA_HRS_HRS24_MASK (0x1000000U)

#define	DMA_HRS_HRS24_SHIFT (24U)

#define	DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

#define	DMA_HRS_HRS25_MASK (0x2000000U)

#define	DMA_HRS_HRS25_SHIFT (25U)

#define	DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

#define	DMA_HRS_HRS26_MASK (0x4000000U)

#define	DMA_HRS_HRS26_SHIFT (26U)

#define	DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

#define	DMA_HRS_HRS27_MASK (0x8000000U)

#define	DMA_HRS_HRS27_SHIFT (27U)

#define	DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

#define	DMA_HRS_HRS28_MASK (0x10000000U)

#define	DMA_HRS_HRS28_SHIFT (28U)

#define	DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

#define	DMA_HRS_HRS29_MASK (0x20000000U)

#define	DMA_HRS_HRS29_SHIFT (29U)

#define	DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

#define	DMA_HRS_HRS30_MASK (0x40000000U)

#define	DMA_HRS_HRS30_SHIFT (30U)

#define	DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

#define	DMA_HRS_HRS31_MASK (0x80000000U)

#define	DMA_HRS_HRS31_SHIFT (31U)

#define	DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

DCHPRI3 - Channel n Priority Register
#define	DMA_DCHPRI3_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI3_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

#define	DMA_DCHPRI3_DPA_MASK (0x40U)

#define	DMA_DCHPRI3_DPA_SHIFT (6U)

#define	DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

#define	DMA_DCHPRI3_ECP_MASK (0x80U)

#define	DMA_DCHPRI3_ECP_SHIFT (7U)

#define	DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

#define	DMA_DCHPRI3_CHPRI_MASK 0xFu

#define	DMA_DCHPRI3_CHPRI_SHIFT 0

#define	DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)

#define	DMA_DCHPRI3_DPA_MASK 0x40u

#define	DMA_DCHPRI3_DPA_SHIFT 6

#define	DMA_DCHPRI3_ECP_MASK 0x80u

#define	DMA_DCHPRI3_ECP_SHIFT 7

#define	DMA_DCHPRI3_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI3_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

#define	DMA_DCHPRI3_DPA_MASK (0x40U)

#define	DMA_DCHPRI3_DPA_SHIFT (6U)

#define	DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

#define	DMA_DCHPRI3_ECP_MASK (0x80U)

#define	DMA_DCHPRI3_ECP_SHIFT (7U)

#define	DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

#define	DMA_DCHPRI3_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI3_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

#define	DMA_DCHPRI3_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI3_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)

#define	DMA_DCHPRI3_DPA_MASK (0x40U)

#define	DMA_DCHPRI3_DPA_SHIFT (6U)

#define	DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

#define	DMA_DCHPRI3_ECP_MASK (0x80U)

#define	DMA_DCHPRI3_ECP_SHIFT (7U)

#define	DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

#define	DMA_DCHPRI3_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI3_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

#define	DMA_DCHPRI3_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI3_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)

#define	DMA_DCHPRI3_DPA_MASK (0x40U)

#define	DMA_DCHPRI3_DPA_SHIFT (6U)

#define	DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

#define	DMA_DCHPRI3_ECP_MASK (0x80U)

#define	DMA_DCHPRI3_ECP_SHIFT (7U)

#define	DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

#define	DMA_DCHPRI3_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI3_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)

#define	DMA_DCHPRI3_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI3_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)

#define	DMA_DCHPRI3_DPA_MASK (0x40U)

#define	DMA_DCHPRI3_DPA_SHIFT (6U)

#define	DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

#define	DMA_DCHPRI3_ECP_MASK (0x80U)

#define	DMA_DCHPRI3_ECP_SHIFT (7U)

#define	DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

DCHPRI2 - Channel n Priority Register
#define	DMA_DCHPRI2_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI2_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

#define	DMA_DCHPRI2_DPA_MASK (0x40U)

#define	DMA_DCHPRI2_DPA_SHIFT (6U)

#define	DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

#define	DMA_DCHPRI2_ECP_MASK (0x80U)

#define	DMA_DCHPRI2_ECP_SHIFT (7U)

#define	DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

#define	DMA_DCHPRI2_CHPRI_MASK 0xFu

#define	DMA_DCHPRI2_CHPRI_SHIFT 0

#define	DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)

#define	DMA_DCHPRI2_DPA_MASK 0x40u

#define	DMA_DCHPRI2_DPA_SHIFT 6

#define	DMA_DCHPRI2_ECP_MASK 0x80u

#define	DMA_DCHPRI2_ECP_SHIFT 7

#define	DMA_DCHPRI2_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI2_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

#define	DMA_DCHPRI2_DPA_MASK (0x40U)

#define	DMA_DCHPRI2_DPA_SHIFT (6U)

#define	DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

#define	DMA_DCHPRI2_ECP_MASK (0x80U)

#define	DMA_DCHPRI2_ECP_SHIFT (7U)

#define	DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

#define	DMA_DCHPRI2_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI2_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

#define	DMA_DCHPRI2_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI2_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)

#define	DMA_DCHPRI2_DPA_MASK (0x40U)

#define	DMA_DCHPRI2_DPA_SHIFT (6U)

#define	DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

#define	DMA_DCHPRI2_ECP_MASK (0x80U)

#define	DMA_DCHPRI2_ECP_SHIFT (7U)

#define	DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

#define	DMA_DCHPRI2_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI2_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

#define	DMA_DCHPRI2_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI2_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)

#define	DMA_DCHPRI2_DPA_MASK (0x40U)

#define	DMA_DCHPRI2_DPA_SHIFT (6U)

#define	DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

#define	DMA_DCHPRI2_ECP_MASK (0x80U)

#define	DMA_DCHPRI2_ECP_SHIFT (7U)

#define	DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

#define	DMA_DCHPRI2_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI2_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)

#define	DMA_DCHPRI2_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI2_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)

#define	DMA_DCHPRI2_DPA_MASK (0x40U)

#define	DMA_DCHPRI2_DPA_SHIFT (6U)

#define	DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

#define	DMA_DCHPRI2_ECP_MASK (0x80U)

#define	DMA_DCHPRI2_ECP_SHIFT (7U)

#define	DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

DCHPRI1 - Channel n Priority Register
#define	DMA_DCHPRI1_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI1_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

#define	DMA_DCHPRI1_DPA_MASK (0x40U)

#define	DMA_DCHPRI1_DPA_SHIFT (6U)

#define	DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

#define	DMA_DCHPRI1_ECP_MASK (0x80U)

#define	DMA_DCHPRI1_ECP_SHIFT (7U)

#define	DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

#define	DMA_DCHPRI1_CHPRI_MASK 0xFu

#define	DMA_DCHPRI1_CHPRI_SHIFT 0

#define	DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)

#define	DMA_DCHPRI1_DPA_MASK 0x40u

#define	DMA_DCHPRI1_DPA_SHIFT 6

#define	DMA_DCHPRI1_ECP_MASK 0x80u

#define	DMA_DCHPRI1_ECP_SHIFT 7

#define	DMA_DCHPRI1_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI1_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

#define	DMA_DCHPRI1_DPA_MASK (0x40U)

#define	DMA_DCHPRI1_DPA_SHIFT (6U)

#define	DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

#define	DMA_DCHPRI1_ECP_MASK (0x80U)

#define	DMA_DCHPRI1_ECP_SHIFT (7U)

#define	DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

#define	DMA_DCHPRI1_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI1_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

#define	DMA_DCHPRI1_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI1_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)

#define	DMA_DCHPRI1_DPA_MASK (0x40U)

#define	DMA_DCHPRI1_DPA_SHIFT (6U)

#define	DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

#define	DMA_DCHPRI1_ECP_MASK (0x80U)

#define	DMA_DCHPRI1_ECP_SHIFT (7U)

#define	DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

#define	DMA_DCHPRI1_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI1_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

#define	DMA_DCHPRI1_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI1_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)

#define	DMA_DCHPRI1_DPA_MASK (0x40U)

#define	DMA_DCHPRI1_DPA_SHIFT (6U)

#define	DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

#define	DMA_DCHPRI1_ECP_MASK (0x80U)

#define	DMA_DCHPRI1_ECP_SHIFT (7U)

#define	DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

#define	DMA_DCHPRI1_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI1_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)

#define	DMA_DCHPRI1_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI1_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)

#define	DMA_DCHPRI1_DPA_MASK (0x40U)

#define	DMA_DCHPRI1_DPA_SHIFT (6U)

#define	DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

#define	DMA_DCHPRI1_ECP_MASK (0x80U)

#define	DMA_DCHPRI1_ECP_SHIFT (7U)

#define	DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

DCHPRI0 - Channel n Priority Register
#define	DMA_DCHPRI0_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI0_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

#define	DMA_DCHPRI0_DPA_MASK (0x40U)

#define	DMA_DCHPRI0_DPA_SHIFT (6U)

#define	DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

#define	DMA_DCHPRI0_ECP_MASK (0x80U)

#define	DMA_DCHPRI0_ECP_SHIFT (7U)

#define	DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

#define	DMA_DCHPRI0_CHPRI_MASK 0xFu

#define	DMA_DCHPRI0_CHPRI_SHIFT 0

#define	DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)

#define	DMA_DCHPRI0_DPA_MASK 0x40u

#define	DMA_DCHPRI0_DPA_SHIFT 6

#define	DMA_DCHPRI0_ECP_MASK 0x80u

#define	DMA_DCHPRI0_ECP_SHIFT 7

#define	DMA_DCHPRI0_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI0_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

#define	DMA_DCHPRI0_DPA_MASK (0x40U)

#define	DMA_DCHPRI0_DPA_SHIFT (6U)

#define	DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

#define	DMA_DCHPRI0_ECP_MASK (0x80U)

#define	DMA_DCHPRI0_ECP_SHIFT (7U)

#define	DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

#define	DMA_DCHPRI0_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI0_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

#define	DMA_DCHPRI0_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI0_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)

#define	DMA_DCHPRI0_DPA_MASK (0x40U)

#define	DMA_DCHPRI0_DPA_SHIFT (6U)

#define	DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

#define	DMA_DCHPRI0_ECP_MASK (0x80U)

#define	DMA_DCHPRI0_ECP_SHIFT (7U)

#define	DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

#define	DMA_DCHPRI0_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI0_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

#define	DMA_DCHPRI0_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI0_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)

#define	DMA_DCHPRI0_DPA_MASK (0x40U)

#define	DMA_DCHPRI0_DPA_SHIFT (6U)

#define	DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

#define	DMA_DCHPRI0_ECP_MASK (0x80U)

#define	DMA_DCHPRI0_ECP_SHIFT (7U)

#define	DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

#define	DMA_DCHPRI0_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI0_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)

#define	DMA_DCHPRI0_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI0_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)

#define	DMA_DCHPRI0_DPA_MASK (0x40U)

#define	DMA_DCHPRI0_DPA_SHIFT (6U)

#define	DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

#define	DMA_DCHPRI0_ECP_MASK (0x80U)

#define	DMA_DCHPRI0_ECP_SHIFT (7U)

#define	DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

DCHPRI7 - Channel n Priority Register
#define	DMA_DCHPRI7_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI7_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

#define	DMA_DCHPRI7_DPA_MASK (0x40U)

#define	DMA_DCHPRI7_DPA_SHIFT (6U)

#define	DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

#define	DMA_DCHPRI7_ECP_MASK (0x80U)

#define	DMA_DCHPRI7_ECP_SHIFT (7U)

#define	DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

#define	DMA_DCHPRI7_CHPRI_MASK 0xFu

#define	DMA_DCHPRI7_CHPRI_SHIFT 0

#define	DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)

#define	DMA_DCHPRI7_DPA_MASK 0x40u

#define	DMA_DCHPRI7_DPA_SHIFT 6

#define	DMA_DCHPRI7_ECP_MASK 0x80u

#define	DMA_DCHPRI7_ECP_SHIFT 7

#define	DMA_DCHPRI7_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI7_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

#define	DMA_DCHPRI7_DPA_MASK (0x40U)

#define	DMA_DCHPRI7_DPA_SHIFT (6U)

#define	DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

#define	DMA_DCHPRI7_ECP_MASK (0x80U)

#define	DMA_DCHPRI7_ECP_SHIFT (7U)

#define	DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

#define	DMA_DCHPRI7_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI7_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

#define	DMA_DCHPRI7_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI7_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)

#define	DMA_DCHPRI7_DPA_MASK (0x40U)

#define	DMA_DCHPRI7_DPA_SHIFT (6U)

#define	DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

#define	DMA_DCHPRI7_ECP_MASK (0x80U)

#define	DMA_DCHPRI7_ECP_SHIFT (7U)

#define	DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

#define	DMA_DCHPRI7_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI7_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

#define	DMA_DCHPRI7_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI7_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)

#define	DMA_DCHPRI7_DPA_MASK (0x40U)

#define	DMA_DCHPRI7_DPA_SHIFT (6U)

#define	DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

#define	DMA_DCHPRI7_ECP_MASK (0x80U)

#define	DMA_DCHPRI7_ECP_SHIFT (7U)

#define	DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

#define	DMA_DCHPRI7_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI7_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)

#define	DMA_DCHPRI7_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI7_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)

#define	DMA_DCHPRI7_DPA_MASK (0x40U)

#define	DMA_DCHPRI7_DPA_SHIFT (6U)

#define	DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

#define	DMA_DCHPRI7_ECP_MASK (0x80U)

#define	DMA_DCHPRI7_ECP_SHIFT (7U)

#define	DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

DCHPRI6 - Channel n Priority Register
#define	DMA_DCHPRI6_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI6_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

#define	DMA_DCHPRI6_DPA_MASK (0x40U)

#define	DMA_DCHPRI6_DPA_SHIFT (6U)

#define	DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

#define	DMA_DCHPRI6_ECP_MASK (0x80U)

#define	DMA_DCHPRI6_ECP_SHIFT (7U)

#define	DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

#define	DMA_DCHPRI6_CHPRI_MASK 0xFu

#define	DMA_DCHPRI6_CHPRI_SHIFT 0

#define	DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)

#define	DMA_DCHPRI6_DPA_MASK 0x40u

#define	DMA_DCHPRI6_DPA_SHIFT 6

#define	DMA_DCHPRI6_ECP_MASK 0x80u

#define	DMA_DCHPRI6_ECP_SHIFT 7

#define	DMA_DCHPRI6_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI6_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

#define	DMA_DCHPRI6_DPA_MASK (0x40U)

#define	DMA_DCHPRI6_DPA_SHIFT (6U)

#define	DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

#define	DMA_DCHPRI6_ECP_MASK (0x80U)

#define	DMA_DCHPRI6_ECP_SHIFT (7U)

#define	DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

#define	DMA_DCHPRI6_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI6_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

#define	DMA_DCHPRI6_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI6_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)

#define	DMA_DCHPRI6_DPA_MASK (0x40U)

#define	DMA_DCHPRI6_DPA_SHIFT (6U)

#define	DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

#define	DMA_DCHPRI6_ECP_MASK (0x80U)

#define	DMA_DCHPRI6_ECP_SHIFT (7U)

#define	DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

#define	DMA_DCHPRI6_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI6_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

#define	DMA_DCHPRI6_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI6_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)

#define	DMA_DCHPRI6_DPA_MASK (0x40U)

#define	DMA_DCHPRI6_DPA_SHIFT (6U)

#define	DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

#define	DMA_DCHPRI6_ECP_MASK (0x80U)

#define	DMA_DCHPRI6_ECP_SHIFT (7U)

#define	DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

#define	DMA_DCHPRI6_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI6_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)

#define	DMA_DCHPRI6_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI6_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)

#define	DMA_DCHPRI6_DPA_MASK (0x40U)

#define	DMA_DCHPRI6_DPA_SHIFT (6U)

#define	DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

#define	DMA_DCHPRI6_ECP_MASK (0x80U)

#define	DMA_DCHPRI6_ECP_SHIFT (7U)

#define	DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

DCHPRI5 - Channel n Priority Register
#define	DMA_DCHPRI5_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI5_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

#define	DMA_DCHPRI5_DPA_MASK (0x40U)

#define	DMA_DCHPRI5_DPA_SHIFT (6U)

#define	DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

#define	DMA_DCHPRI5_ECP_MASK (0x80U)

#define	DMA_DCHPRI5_ECP_SHIFT (7U)

#define	DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

#define	DMA_DCHPRI5_CHPRI_MASK 0xFu

#define	DMA_DCHPRI5_CHPRI_SHIFT 0

#define	DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)

#define	DMA_DCHPRI5_DPA_MASK 0x40u

#define	DMA_DCHPRI5_DPA_SHIFT 6

#define	DMA_DCHPRI5_ECP_MASK 0x80u

#define	DMA_DCHPRI5_ECP_SHIFT 7

#define	DMA_DCHPRI5_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI5_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

#define	DMA_DCHPRI5_DPA_MASK (0x40U)

#define	DMA_DCHPRI5_DPA_SHIFT (6U)

#define	DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

#define	DMA_DCHPRI5_ECP_MASK (0x80U)

#define	DMA_DCHPRI5_ECP_SHIFT (7U)

#define	DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

#define	DMA_DCHPRI5_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI5_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

#define	DMA_DCHPRI5_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI5_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)

#define	DMA_DCHPRI5_DPA_MASK (0x40U)

#define	DMA_DCHPRI5_DPA_SHIFT (6U)

#define	DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

#define	DMA_DCHPRI5_ECP_MASK (0x80U)

#define	DMA_DCHPRI5_ECP_SHIFT (7U)

#define	DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

#define	DMA_DCHPRI5_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI5_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

#define	DMA_DCHPRI5_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI5_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)

#define	DMA_DCHPRI5_DPA_MASK (0x40U)

#define	DMA_DCHPRI5_DPA_SHIFT (6U)

#define	DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

#define	DMA_DCHPRI5_ECP_MASK (0x80U)

#define	DMA_DCHPRI5_ECP_SHIFT (7U)

#define	DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

#define	DMA_DCHPRI5_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI5_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)

#define	DMA_DCHPRI5_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI5_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)

#define	DMA_DCHPRI5_DPA_MASK (0x40U)

#define	DMA_DCHPRI5_DPA_SHIFT (6U)

#define	DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

#define	DMA_DCHPRI5_ECP_MASK (0x80U)

#define	DMA_DCHPRI5_ECP_SHIFT (7U)

#define	DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

DCHPRI4 - Channel n Priority Register
#define	DMA_DCHPRI4_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI4_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

#define	DMA_DCHPRI4_DPA_MASK (0x40U)

#define	DMA_DCHPRI4_DPA_SHIFT (6U)

#define	DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

#define	DMA_DCHPRI4_ECP_MASK (0x80U)

#define	DMA_DCHPRI4_ECP_SHIFT (7U)

#define	DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

#define	DMA_DCHPRI4_CHPRI_MASK 0xFu

#define	DMA_DCHPRI4_CHPRI_SHIFT 0

#define	DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)

#define	DMA_DCHPRI4_DPA_MASK 0x40u

#define	DMA_DCHPRI4_DPA_SHIFT 6

#define	DMA_DCHPRI4_ECP_MASK 0x80u

#define	DMA_DCHPRI4_ECP_SHIFT 7

#define	DMA_DCHPRI4_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI4_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

#define	DMA_DCHPRI4_DPA_MASK (0x40U)

#define	DMA_DCHPRI4_DPA_SHIFT (6U)

#define	DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

#define	DMA_DCHPRI4_ECP_MASK (0x80U)

#define	DMA_DCHPRI4_ECP_SHIFT (7U)

#define	DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

#define	DMA_DCHPRI4_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI4_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

#define	DMA_DCHPRI4_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI4_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)

#define	DMA_DCHPRI4_DPA_MASK (0x40U)

#define	DMA_DCHPRI4_DPA_SHIFT (6U)

#define	DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

#define	DMA_DCHPRI4_ECP_MASK (0x80U)

#define	DMA_DCHPRI4_ECP_SHIFT (7U)

#define	DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

#define	DMA_DCHPRI4_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI4_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

#define	DMA_DCHPRI4_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI4_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)

#define	DMA_DCHPRI4_DPA_MASK (0x40U)

#define	DMA_DCHPRI4_DPA_SHIFT (6U)

#define	DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

#define	DMA_DCHPRI4_ECP_MASK (0x80U)

#define	DMA_DCHPRI4_ECP_SHIFT (7U)

#define	DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

#define	DMA_DCHPRI4_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI4_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)

#define	DMA_DCHPRI4_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI4_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)

#define	DMA_DCHPRI4_DPA_MASK (0x40U)

#define	DMA_DCHPRI4_DPA_SHIFT (6U)

#define	DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

#define	DMA_DCHPRI4_ECP_MASK (0x80U)

#define	DMA_DCHPRI4_ECP_SHIFT (7U)

#define	DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

DCHPRI11 - Channel n Priority Register
#define	DMA_DCHPRI11_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI11_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

#define	DMA_DCHPRI11_DPA_MASK (0x40U)

#define	DMA_DCHPRI11_DPA_SHIFT (6U)

#define	DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

#define	DMA_DCHPRI11_ECP_MASK (0x80U)

#define	DMA_DCHPRI11_ECP_SHIFT (7U)

#define	DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

#define	DMA_DCHPRI11_CHPRI_MASK 0xFu

#define	DMA_DCHPRI11_CHPRI_SHIFT 0

#define	DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)

#define	DMA_DCHPRI11_DPA_MASK 0x40u

#define	DMA_DCHPRI11_DPA_SHIFT 6

#define	DMA_DCHPRI11_ECP_MASK 0x80u

#define	DMA_DCHPRI11_ECP_SHIFT 7

#define	DMA_DCHPRI11_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI11_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

#define	DMA_DCHPRI11_DPA_MASK (0x40U)

#define	DMA_DCHPRI11_DPA_SHIFT (6U)

#define	DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

#define	DMA_DCHPRI11_ECP_MASK (0x80U)

#define	DMA_DCHPRI11_ECP_SHIFT (7U)

#define	DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

#define	DMA_DCHPRI11_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI11_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

#define	DMA_DCHPRI11_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI11_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)

#define	DMA_DCHPRI11_DPA_MASK (0x40U)

#define	DMA_DCHPRI11_DPA_SHIFT (6U)

#define	DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

#define	DMA_DCHPRI11_ECP_MASK (0x80U)

#define	DMA_DCHPRI11_ECP_SHIFT (7U)

#define	DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

#define	DMA_DCHPRI11_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI11_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

#define	DMA_DCHPRI11_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI11_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)

#define	DMA_DCHPRI11_DPA_MASK (0x40U)

#define	DMA_DCHPRI11_DPA_SHIFT (6U)

#define	DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

#define	DMA_DCHPRI11_ECP_MASK (0x80U)

#define	DMA_DCHPRI11_ECP_SHIFT (7U)

#define	DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

#define	DMA_DCHPRI11_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI11_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)

#define	DMA_DCHPRI11_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI11_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)

#define	DMA_DCHPRI11_DPA_MASK (0x40U)

#define	DMA_DCHPRI11_DPA_SHIFT (6U)

#define	DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

#define	DMA_DCHPRI11_ECP_MASK (0x80U)

#define	DMA_DCHPRI11_ECP_SHIFT (7U)

#define	DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

DCHPRI10 - Channel n Priority Register
#define	DMA_DCHPRI10_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI10_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

#define	DMA_DCHPRI10_DPA_MASK (0x40U)

#define	DMA_DCHPRI10_DPA_SHIFT (6U)

#define	DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

#define	DMA_DCHPRI10_ECP_MASK (0x80U)

#define	DMA_DCHPRI10_ECP_SHIFT (7U)

#define	DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

#define	DMA_DCHPRI10_CHPRI_MASK 0xFu

#define	DMA_DCHPRI10_CHPRI_SHIFT 0

#define	DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)

#define	DMA_DCHPRI10_DPA_MASK 0x40u

#define	DMA_DCHPRI10_DPA_SHIFT 6

#define	DMA_DCHPRI10_ECP_MASK 0x80u

#define	DMA_DCHPRI10_ECP_SHIFT 7

#define	DMA_DCHPRI10_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI10_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

#define	DMA_DCHPRI10_DPA_MASK (0x40U)

#define	DMA_DCHPRI10_DPA_SHIFT (6U)

#define	DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

#define	DMA_DCHPRI10_ECP_MASK (0x80U)

#define	DMA_DCHPRI10_ECP_SHIFT (7U)

#define	DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

#define	DMA_DCHPRI10_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI10_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

#define	DMA_DCHPRI10_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI10_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)

#define	DMA_DCHPRI10_DPA_MASK (0x40U)

#define	DMA_DCHPRI10_DPA_SHIFT (6U)

#define	DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

#define	DMA_DCHPRI10_ECP_MASK (0x80U)

#define	DMA_DCHPRI10_ECP_SHIFT (7U)

#define	DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

#define	DMA_DCHPRI10_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI10_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

#define	DMA_DCHPRI10_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI10_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)

#define	DMA_DCHPRI10_DPA_MASK (0x40U)

#define	DMA_DCHPRI10_DPA_SHIFT (6U)

#define	DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

#define	DMA_DCHPRI10_ECP_MASK (0x80U)

#define	DMA_DCHPRI10_ECP_SHIFT (7U)

#define	DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

#define	DMA_DCHPRI10_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI10_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)

#define	DMA_DCHPRI10_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI10_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)

#define	DMA_DCHPRI10_DPA_MASK (0x40U)

#define	DMA_DCHPRI10_DPA_SHIFT (6U)

#define	DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

#define	DMA_DCHPRI10_ECP_MASK (0x80U)

#define	DMA_DCHPRI10_ECP_SHIFT (7U)

#define	DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

DCHPRI9 - Channel n Priority Register
#define	DMA_DCHPRI9_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI9_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

#define	DMA_DCHPRI9_DPA_MASK (0x40U)

#define	DMA_DCHPRI9_DPA_SHIFT (6U)

#define	DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

#define	DMA_DCHPRI9_ECP_MASK (0x80U)

#define	DMA_DCHPRI9_ECP_SHIFT (7U)

#define	DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

#define	DMA_DCHPRI9_CHPRI_MASK 0xFu

#define	DMA_DCHPRI9_CHPRI_SHIFT 0

#define	DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)

#define	DMA_DCHPRI9_DPA_MASK 0x40u

#define	DMA_DCHPRI9_DPA_SHIFT 6

#define	DMA_DCHPRI9_ECP_MASK 0x80u

#define	DMA_DCHPRI9_ECP_SHIFT 7

#define	DMA_DCHPRI9_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI9_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

#define	DMA_DCHPRI9_DPA_MASK (0x40U)

#define	DMA_DCHPRI9_DPA_SHIFT (6U)

#define	DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

#define	DMA_DCHPRI9_ECP_MASK (0x80U)

#define	DMA_DCHPRI9_ECP_SHIFT (7U)

#define	DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

#define	DMA_DCHPRI9_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI9_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

#define	DMA_DCHPRI9_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI9_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)

#define	DMA_DCHPRI9_DPA_MASK (0x40U)

#define	DMA_DCHPRI9_DPA_SHIFT (6U)

#define	DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

#define	DMA_DCHPRI9_ECP_MASK (0x80U)

#define	DMA_DCHPRI9_ECP_SHIFT (7U)

#define	DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

#define	DMA_DCHPRI9_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI9_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

#define	DMA_DCHPRI9_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI9_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)

#define	DMA_DCHPRI9_DPA_MASK (0x40U)

#define	DMA_DCHPRI9_DPA_SHIFT (6U)

#define	DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

#define	DMA_DCHPRI9_ECP_MASK (0x80U)

#define	DMA_DCHPRI9_ECP_SHIFT (7U)

#define	DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

#define	DMA_DCHPRI9_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI9_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)

#define	DMA_DCHPRI9_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI9_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)

#define	DMA_DCHPRI9_DPA_MASK (0x40U)

#define	DMA_DCHPRI9_DPA_SHIFT (6U)

#define	DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

#define	DMA_DCHPRI9_ECP_MASK (0x80U)

#define	DMA_DCHPRI9_ECP_SHIFT (7U)

#define	DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

DCHPRI8 - Channel n Priority Register
#define	DMA_DCHPRI8_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI8_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

#define	DMA_DCHPRI8_DPA_MASK (0x40U)

#define	DMA_DCHPRI8_DPA_SHIFT (6U)

#define	DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

#define	DMA_DCHPRI8_ECP_MASK (0x80U)

#define	DMA_DCHPRI8_ECP_SHIFT (7U)

#define	DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

#define	DMA_DCHPRI8_CHPRI_MASK 0xFu

#define	DMA_DCHPRI8_CHPRI_SHIFT 0

#define	DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)

#define	DMA_DCHPRI8_DPA_MASK 0x40u

#define	DMA_DCHPRI8_DPA_SHIFT 6

#define	DMA_DCHPRI8_ECP_MASK 0x80u

#define	DMA_DCHPRI8_ECP_SHIFT 7

#define	DMA_DCHPRI8_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI8_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

#define	DMA_DCHPRI8_DPA_MASK (0x40U)

#define	DMA_DCHPRI8_DPA_SHIFT (6U)

#define	DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

#define	DMA_DCHPRI8_ECP_MASK (0x80U)

#define	DMA_DCHPRI8_ECP_SHIFT (7U)

#define	DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

#define	DMA_DCHPRI8_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI8_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

#define	DMA_DCHPRI8_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI8_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)

#define	DMA_DCHPRI8_DPA_MASK (0x40U)

#define	DMA_DCHPRI8_DPA_SHIFT (6U)

#define	DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

#define	DMA_DCHPRI8_ECP_MASK (0x80U)

#define	DMA_DCHPRI8_ECP_SHIFT (7U)

#define	DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

#define	DMA_DCHPRI8_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI8_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

#define	DMA_DCHPRI8_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI8_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)

#define	DMA_DCHPRI8_DPA_MASK (0x40U)

#define	DMA_DCHPRI8_DPA_SHIFT (6U)

#define	DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

#define	DMA_DCHPRI8_ECP_MASK (0x80U)

#define	DMA_DCHPRI8_ECP_SHIFT (7U)

#define	DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

#define	DMA_DCHPRI8_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI8_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)

#define	DMA_DCHPRI8_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI8_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)

#define	DMA_DCHPRI8_DPA_MASK (0x40U)

#define	DMA_DCHPRI8_DPA_SHIFT (6U)

#define	DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

#define	DMA_DCHPRI8_ECP_MASK (0x80U)

#define	DMA_DCHPRI8_ECP_SHIFT (7U)

#define	DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

DCHPRI15 - Channel n Priority Register
#define	DMA_DCHPRI15_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI15_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

#define	DMA_DCHPRI15_DPA_MASK (0x40U)

#define	DMA_DCHPRI15_DPA_SHIFT (6U)

#define	DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

#define	DMA_DCHPRI15_ECP_MASK (0x80U)

#define	DMA_DCHPRI15_ECP_SHIFT (7U)

#define	DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

#define	DMA_DCHPRI15_CHPRI_MASK 0xFu

#define	DMA_DCHPRI15_CHPRI_SHIFT 0

#define	DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)

#define	DMA_DCHPRI15_DPA_MASK 0x40u

#define	DMA_DCHPRI15_DPA_SHIFT 6

#define	DMA_DCHPRI15_ECP_MASK 0x80u

#define	DMA_DCHPRI15_ECP_SHIFT 7

#define	DMA_DCHPRI15_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI15_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

#define	DMA_DCHPRI15_DPA_MASK (0x40U)

#define	DMA_DCHPRI15_DPA_SHIFT (6U)

#define	DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

#define	DMA_DCHPRI15_ECP_MASK (0x80U)

#define	DMA_DCHPRI15_ECP_SHIFT (7U)

#define	DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

#define	DMA_DCHPRI15_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI15_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

#define	DMA_DCHPRI15_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI15_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)

#define	DMA_DCHPRI15_DPA_MASK (0x40U)

#define	DMA_DCHPRI15_DPA_SHIFT (6U)

#define	DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

#define	DMA_DCHPRI15_ECP_MASK (0x80U)

#define	DMA_DCHPRI15_ECP_SHIFT (7U)

#define	DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

#define	DMA_DCHPRI15_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI15_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

#define	DMA_DCHPRI15_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI15_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)

#define	DMA_DCHPRI15_DPA_MASK (0x40U)

#define	DMA_DCHPRI15_DPA_SHIFT (6U)

#define	DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

#define	DMA_DCHPRI15_ECP_MASK (0x80U)

#define	DMA_DCHPRI15_ECP_SHIFT (7U)

#define	DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

#define	DMA_DCHPRI15_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI15_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)

#define	DMA_DCHPRI15_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI15_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)

#define	DMA_DCHPRI15_DPA_MASK (0x40U)

#define	DMA_DCHPRI15_DPA_SHIFT (6U)

#define	DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

#define	DMA_DCHPRI15_ECP_MASK (0x80U)

#define	DMA_DCHPRI15_ECP_SHIFT (7U)

#define	DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

DCHPRI14 - Channel n Priority Register
#define	DMA_DCHPRI14_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI14_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

#define	DMA_DCHPRI14_DPA_MASK (0x40U)

#define	DMA_DCHPRI14_DPA_SHIFT (6U)

#define	DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

#define	DMA_DCHPRI14_ECP_MASK (0x80U)

#define	DMA_DCHPRI14_ECP_SHIFT (7U)

#define	DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

#define	DMA_DCHPRI14_CHPRI_MASK 0xFu

#define	DMA_DCHPRI14_CHPRI_SHIFT 0

#define	DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)

#define	DMA_DCHPRI14_DPA_MASK 0x40u

#define	DMA_DCHPRI14_DPA_SHIFT 6

#define	DMA_DCHPRI14_ECP_MASK 0x80u

#define	DMA_DCHPRI14_ECP_SHIFT 7

#define	DMA_DCHPRI14_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI14_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

#define	DMA_DCHPRI14_DPA_MASK (0x40U)

#define	DMA_DCHPRI14_DPA_SHIFT (6U)

#define	DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

#define	DMA_DCHPRI14_ECP_MASK (0x80U)

#define	DMA_DCHPRI14_ECP_SHIFT (7U)

#define	DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

#define	DMA_DCHPRI14_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI14_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

#define	DMA_DCHPRI14_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI14_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)

#define	DMA_DCHPRI14_DPA_MASK (0x40U)

#define	DMA_DCHPRI14_DPA_SHIFT (6U)

#define	DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

#define	DMA_DCHPRI14_ECP_MASK (0x80U)

#define	DMA_DCHPRI14_ECP_SHIFT (7U)

#define	DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

#define	DMA_DCHPRI14_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI14_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

#define	DMA_DCHPRI14_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI14_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)

#define	DMA_DCHPRI14_DPA_MASK (0x40U)

#define	DMA_DCHPRI14_DPA_SHIFT (6U)

#define	DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

#define	DMA_DCHPRI14_ECP_MASK (0x80U)

#define	DMA_DCHPRI14_ECP_SHIFT (7U)

#define	DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

#define	DMA_DCHPRI14_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI14_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)

#define	DMA_DCHPRI14_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI14_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)

#define	DMA_DCHPRI14_DPA_MASK (0x40U)

#define	DMA_DCHPRI14_DPA_SHIFT (6U)

#define	DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

#define	DMA_DCHPRI14_ECP_MASK (0x80U)

#define	DMA_DCHPRI14_ECP_SHIFT (7U)

#define	DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

DCHPRI13 - Channel n Priority Register
#define	DMA_DCHPRI13_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI13_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

#define	DMA_DCHPRI13_DPA_MASK (0x40U)

#define	DMA_DCHPRI13_DPA_SHIFT (6U)

#define	DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

#define	DMA_DCHPRI13_ECP_MASK (0x80U)

#define	DMA_DCHPRI13_ECP_SHIFT (7U)

#define	DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

#define	DMA_DCHPRI13_CHPRI_MASK 0xFu

#define	DMA_DCHPRI13_CHPRI_SHIFT 0

#define	DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)

#define	DMA_DCHPRI13_DPA_MASK 0x40u

#define	DMA_DCHPRI13_DPA_SHIFT 6

#define	DMA_DCHPRI13_ECP_MASK 0x80u

#define	DMA_DCHPRI13_ECP_SHIFT 7

#define	DMA_DCHPRI13_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI13_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

#define	DMA_DCHPRI13_DPA_MASK (0x40U)

#define	DMA_DCHPRI13_DPA_SHIFT (6U)

#define	DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

#define	DMA_DCHPRI13_ECP_MASK (0x80U)

#define	DMA_DCHPRI13_ECP_SHIFT (7U)

#define	DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

#define	DMA_DCHPRI13_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI13_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

#define	DMA_DCHPRI13_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI13_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)

#define	DMA_DCHPRI13_DPA_MASK (0x40U)

#define	DMA_DCHPRI13_DPA_SHIFT (6U)

#define	DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

#define	DMA_DCHPRI13_ECP_MASK (0x80U)

#define	DMA_DCHPRI13_ECP_SHIFT (7U)

#define	DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

#define	DMA_DCHPRI13_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI13_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

#define	DMA_DCHPRI13_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI13_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)

#define	DMA_DCHPRI13_DPA_MASK (0x40U)

#define	DMA_DCHPRI13_DPA_SHIFT (6U)

#define	DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

#define	DMA_DCHPRI13_ECP_MASK (0x80U)

#define	DMA_DCHPRI13_ECP_SHIFT (7U)

#define	DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

#define	DMA_DCHPRI13_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI13_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)

#define	DMA_DCHPRI13_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI13_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)

#define	DMA_DCHPRI13_DPA_MASK (0x40U)

#define	DMA_DCHPRI13_DPA_SHIFT (6U)

#define	DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

#define	DMA_DCHPRI13_ECP_MASK (0x80U)

#define	DMA_DCHPRI13_ECP_SHIFT (7U)

#define	DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

DCHPRI12 - Channel n Priority Register
#define	DMA_DCHPRI12_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI12_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

#define	DMA_DCHPRI12_DPA_MASK (0x40U)

#define	DMA_DCHPRI12_DPA_SHIFT (6U)

#define	DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

#define	DMA_DCHPRI12_ECP_MASK (0x80U)

#define	DMA_DCHPRI12_ECP_SHIFT (7U)

#define	DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

#define	DMA_DCHPRI12_CHPRI_MASK 0xFu

#define	DMA_DCHPRI12_CHPRI_SHIFT 0

#define	DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)

#define	DMA_DCHPRI12_DPA_MASK 0x40u

#define	DMA_DCHPRI12_DPA_SHIFT 6

#define	DMA_DCHPRI12_ECP_MASK 0x80u

#define	DMA_DCHPRI12_ECP_SHIFT 7

#define	DMA_DCHPRI12_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI12_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

#define	DMA_DCHPRI12_DPA_MASK (0x40U)

#define	DMA_DCHPRI12_DPA_SHIFT (6U)

#define	DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

#define	DMA_DCHPRI12_ECP_MASK (0x80U)

#define	DMA_DCHPRI12_ECP_SHIFT (7U)

#define	DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

#define	DMA_DCHPRI12_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI12_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

#define	DMA_DCHPRI12_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI12_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)

#define	DMA_DCHPRI12_DPA_MASK (0x40U)

#define	DMA_DCHPRI12_DPA_SHIFT (6U)

#define	DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

#define	DMA_DCHPRI12_ECP_MASK (0x80U)

#define	DMA_DCHPRI12_ECP_SHIFT (7U)

#define	DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

#define	DMA_DCHPRI12_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI12_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

#define	DMA_DCHPRI12_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI12_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)

#define	DMA_DCHPRI12_DPA_MASK (0x40U)

#define	DMA_DCHPRI12_DPA_SHIFT (6U)

#define	DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

#define	DMA_DCHPRI12_ECP_MASK (0x80U)

#define	DMA_DCHPRI12_ECP_SHIFT (7U)

#define	DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

#define	DMA_DCHPRI12_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI12_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)

#define	DMA_DCHPRI12_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI12_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)

#define	DMA_DCHPRI12_DPA_MASK (0x40U)

#define	DMA_DCHPRI12_DPA_SHIFT (6U)

#define	DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

#define	DMA_DCHPRI12_ECP_MASK (0x80U)

#define	DMA_DCHPRI12_ECP_SHIFT (7U)

#define	DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

SADDR - TCD Source Address
#define	DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)

#define	DMA_SADDR_SADDR_SHIFT (0U)

#define	DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

#define	DMA_SADDR_SADDR_MASK 0xFFFFFFFFu

#define	DMA_SADDR_SADDR_SHIFT 0

#define	DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)

#define	DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)

#define	DMA_SADDR_SADDR_SHIFT (0U)

#define	DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

#define	DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)

#define	DMA_SADDR_SADDR_SHIFT (0U)

#define	DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

#define	DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)

#define	DMA_SADDR_SADDR_SHIFT (0U)

#define	DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

#define	DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)

#define	DMA_SADDR_SADDR_SHIFT (0U)

#define	DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)

SADDR - TCD Source Address
#define	DMA_SADDR_COUNT (16U)

SOFF - TCD Signed Source Address Offset
#define	DMA_SOFF_SOFF_MASK (0xFFFFU)

#define	DMA_SOFF_SOFF_SHIFT (0U)

#define	DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

#define	DMA_SOFF_SOFF_MASK 0xFFFFu

#define	DMA_SOFF_SOFF_SHIFT 0

#define	DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)

#define	DMA_SOFF_SOFF_MASK (0xFFFFU)

#define	DMA_SOFF_SOFF_SHIFT (0U)

#define	DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

#define	DMA_SOFF_SOFF_MASK (0xFFFFU)

#define	DMA_SOFF_SOFF_SHIFT (0U)

#define	DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

#define	DMA_SOFF_SOFF_MASK (0xFFFFU)

#define	DMA_SOFF_SOFF_SHIFT (0U)

#define	DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

#define	DMA_SOFF_SOFF_MASK (0xFFFFU)

#define	DMA_SOFF_SOFF_SHIFT (0U)

#define	DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)

SOFF - TCD Signed Source Address Offset
#define	DMA_SOFF_COUNT (16U)

ATTR - TCD Transfer Attributes
#define	DMA_ATTR_DSIZE_MASK (0x7U)

#define	DMA_ATTR_DSIZE_SHIFT (0U)

#define	DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

#define	DMA_ATTR_DMOD_MASK (0xF8U)

#define	DMA_ATTR_DMOD_SHIFT (3U)

#define	DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

#define	DMA_ATTR_SSIZE_MASK (0x700U)

#define	DMA_ATTR_SSIZE_SHIFT (8U)

#define	DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

#define	DMA_ATTR_SMOD_MASK (0xF800U)

#define	DMA_ATTR_SMOD_SHIFT (11U)

#define	DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

#define	DMA_ATTR_DSIZE_MASK 0x7u

#define	DMA_ATTR_DSIZE_SHIFT 0

#define	DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)

#define	DMA_ATTR_DMOD_MASK 0xF8u

#define	DMA_ATTR_DMOD_SHIFT 3

#define	DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)

#define	DMA_ATTR_SSIZE_MASK 0x700u

#define	DMA_ATTR_SSIZE_SHIFT 8

#define	DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)

#define	DMA_ATTR_SMOD_MASK 0xF800u

#define	DMA_ATTR_SMOD_SHIFT 11

#define	DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)

#define	DMA_ATTR_DSIZE_MASK (0x7U)

#define	DMA_ATTR_DSIZE_SHIFT (0U)

#define	DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

#define	DMA_ATTR_DMOD_MASK (0xF8U)

#define	DMA_ATTR_DMOD_SHIFT (3U)

#define	DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

#define	DMA_ATTR_SSIZE_MASK (0x700U)

#define	DMA_ATTR_SSIZE_SHIFT (8U)

#define	DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

#define	DMA_ATTR_SMOD_MASK (0xF800U)

#define	DMA_ATTR_SMOD_SHIFT (11U)

#define	DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

#define	DMA_ATTR_DSIZE_MASK (0x7U)

#define	DMA_ATTR_DSIZE_SHIFT (0U)

#define	DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

#define	DMA_ATTR_DMOD_MASK (0xF8U)

#define	DMA_ATTR_DMOD_SHIFT (3U)

#define	DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

#define	DMA_ATTR_SSIZE_MASK (0x700U)

#define	DMA_ATTR_SSIZE_SHIFT (8U)

#define	DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

#define	DMA_ATTR_SMOD_MASK (0xF800U)

#define	DMA_ATTR_SMOD_SHIFT (11U)

#define	DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

#define	DMA_ATTR_DSIZE_MASK (0x7U)

#define	DMA_ATTR_DSIZE_SHIFT (0U)

#define	DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

#define	DMA_ATTR_DMOD_MASK (0xF8U)

#define	DMA_ATTR_DMOD_SHIFT (3U)

#define	DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

#define	DMA_ATTR_SSIZE_MASK (0x700U)

#define	DMA_ATTR_SSIZE_SHIFT (8U)

#define	DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

#define	DMA_ATTR_SMOD_MASK (0xF800U)

#define	DMA_ATTR_SMOD_SHIFT (11U)

#define	DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

#define	DMA_ATTR_DSIZE_MASK (0x7U)

#define	DMA_ATTR_DSIZE_SHIFT (0U)

#define	DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)

#define	DMA_ATTR_DMOD_MASK (0xF8U)

#define	DMA_ATTR_DMOD_SHIFT (3U)

#define	DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)

#define	DMA_ATTR_SSIZE_MASK (0x700U)

#define	DMA_ATTR_SSIZE_SHIFT (8U)

#define	DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

#define	DMA_ATTR_SMOD_MASK (0xF800U)

#define	DMA_ATTR_SMOD_SHIFT (11U)

#define	DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

ATTR - TCD Transfer Attributes
#define	DMA_ATTR_COUNT (16U)

NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled)
#define	DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)

#define	DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

#define	DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu

#define	DMA_NBYTES_MLNO_NBYTES_SHIFT 0

#define	DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)

#define	DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)

#define	DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

#define	DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)

#define	DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

#define	DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)

#define	DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

#define	DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)

#define	DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)

NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
#define	DMA_NBYTES_MLNO_COUNT (16U)

NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)

#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu

#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0

#define	DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u

#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30

#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u

#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31

#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)

#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)

#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)

#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

#define	DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)

#define	DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
#define	DMA_NBYTES_MLOFFNO_COUNT (16U)

NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)

#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)

#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)

#define	DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu

#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0

#define	DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u

#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10

#define	DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)

#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u

#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30

#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u

#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31

#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)

#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)

#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)

#define	DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)

#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)

#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)

#define	DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)

#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)

#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)

#define	DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

#define	DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)

#define	DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)

#define	DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)

#define	DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)

#define	DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)

#define	DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)

#define	DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)

#define	DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)

#define	DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

#define	DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)

#define	DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)

#define	DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
#define	DMA_NBYTES_MLOFFYES_COUNT (16U)

SLAST - TCD Last Source Address Adjustment
#define	DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)

#define	DMA_SLAST_SLAST_SHIFT (0U)

#define	DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

#define	DMA_SLAST_SLAST_MASK 0xFFFFFFFFu

#define	DMA_SLAST_SLAST_SHIFT 0

#define	DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)

#define	DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)

#define	DMA_SLAST_SLAST_SHIFT (0U)

#define	DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

#define	DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)

#define	DMA_SLAST_SLAST_SHIFT (0U)

#define	DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

#define	DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)

#define	DMA_SLAST_SLAST_SHIFT (0U)

#define	DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

#define	DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)

#define	DMA_SLAST_SLAST_SHIFT (0U)

#define	DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)

SLAST - TCD Last Source Address Adjustment
#define	DMA_SLAST_COUNT (16U)

DADDR - TCD Destination Address
#define	DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)

#define	DMA_DADDR_DADDR_SHIFT (0U)

#define	DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

#define	DMA_DADDR_DADDR_MASK 0xFFFFFFFFu

#define	DMA_DADDR_DADDR_SHIFT 0

#define	DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)

#define	DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)

#define	DMA_DADDR_DADDR_SHIFT (0U)

#define	DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

#define	DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)

#define	DMA_DADDR_DADDR_SHIFT (0U)

#define	DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

#define	DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)

#define	DMA_DADDR_DADDR_SHIFT (0U)

#define	DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

#define	DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)

#define	DMA_DADDR_DADDR_SHIFT (0U)

#define	DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)

DADDR - TCD Destination Address
#define	DMA_DADDR_COUNT (16U)

DOFF - TCD Signed Destination Address Offset
#define	DMA_DOFF_DOFF_MASK (0xFFFFU)

#define	DMA_DOFF_DOFF_SHIFT (0U)

#define	DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

#define	DMA_DOFF_DOFF_MASK 0xFFFFu

#define	DMA_DOFF_DOFF_SHIFT 0

#define	DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)

#define	DMA_DOFF_DOFF_MASK (0xFFFFU)

#define	DMA_DOFF_DOFF_SHIFT (0U)

#define	DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

#define	DMA_DOFF_DOFF_MASK (0xFFFFU)

#define	DMA_DOFF_DOFF_SHIFT (0U)

#define	DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

#define	DMA_DOFF_DOFF_MASK (0xFFFFU)

#define	DMA_DOFF_DOFF_SHIFT (0U)

#define	DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

#define	DMA_DOFF_DOFF_MASK (0xFFFFU)

#define	DMA_DOFF_DOFF_SHIFT (0U)

#define	DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)

DOFF - TCD Signed Destination Address Offset
#define	DMA_DOFF_COUNT (16U)

CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define	DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)

#define	DMA_CITER_ELINKNO_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

#define	DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

#define	DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu

#define	DMA_CITER_ELINKNO_CITER_SHIFT 0

#define	DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)

#define	DMA_CITER_ELINKNO_ELINK_MASK 0x8000u

#define	DMA_CITER_ELINKNO_ELINK_SHIFT 15

#define	DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)

#define	DMA_CITER_ELINKNO_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

#define	DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

#define	DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)

#define	DMA_CITER_ELINKNO_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

#define	DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

#define	DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)

#define	DMA_CITER_ELINKNO_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

#define	DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

#define	DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)

#define	DMA_CITER_ELINKNO_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)

#define	DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define	DMA_CITER_ELINKNO_COUNT (16U)

CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define	DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)

#define	DMA_CITER_ELINKYES_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

#define	DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)

#define	DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

#define	DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

#define	DMA_CITER_ELINKYES_CITER_MASK 0x1FFu

#define	DMA_CITER_ELINKYES_CITER_SHIFT 0

#define	DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)

#define	DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u

#define	DMA_CITER_ELINKYES_LINKCH_SHIFT 9

#define	DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)

#define	DMA_CITER_ELINKYES_ELINK_MASK 0x8000u

#define	DMA_CITER_ELINKYES_ELINK_SHIFT 15

#define	DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)

#define	DMA_CITER_ELINKYES_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

#define	DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)

#define	DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

#define	DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

#define	DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)

#define	DMA_CITER_ELINKYES_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

#define	DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)

#define	DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

#define	DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

#define	DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)

#define	DMA_CITER_ELINKYES_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

#define	DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)

#define	DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

#define	DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

#define	DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)

#define	DMA_CITER_ELINKYES_CITER_SHIFT (0U)

#define	DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)

#define	DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)

#define	DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)

#define	DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_CITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define	DMA_CITER_ELINKYES_COUNT (16U)

DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
#define	DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)

#define	DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)

#define	DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

#define	DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu

#define	DMA_DLAST_SGA_DLASTSGA_SHIFT 0

#define	DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)

#define	DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)

#define	DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)

#define	DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

#define	DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)

#define	DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)

#define	DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

#define	DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)

#define	DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)

#define	DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

#define	DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)

#define	DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)

#define	DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)

DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address
#define	DMA_DLAST_SGA_COUNT (16U)

CSR - TCD Control and Status
#define	DMA_CSR_START_MASK (0x1U)

#define	DMA_CSR_START_SHIFT (0U)

#define	DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

#define	DMA_CSR_INTMAJOR_MASK (0x2U)

#define	DMA_CSR_INTMAJOR_SHIFT (1U)

#define	DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

#define	DMA_CSR_INTHALF_MASK (0x4U)

#define	DMA_CSR_INTHALF_SHIFT (2U)

#define	DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

#define	DMA_CSR_DREQ_MASK (0x8U)

#define	DMA_CSR_DREQ_SHIFT (3U)

#define	DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

#define	DMA_CSR_ESG_MASK (0x10U)

#define	DMA_CSR_ESG_SHIFT (4U)

#define	DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

#define	DMA_CSR_MAJORELINK_MASK (0x20U)

#define	DMA_CSR_MAJORELINK_SHIFT (5U)

#define	DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

#define	DMA_CSR_ACTIVE_MASK (0x40U)

#define	DMA_CSR_ACTIVE_SHIFT (6U)

#define	DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

#define	DMA_CSR_DONE_MASK (0x80U)

#define	DMA_CSR_DONE_SHIFT (7U)

#define	DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

#define	DMA_CSR_MAJORLINKCH_MASK (0xF00U)

#define	DMA_CSR_MAJORLINKCH_SHIFT (8U)

#define	DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

#define	DMA_CSR_BWC_MASK (0xC000U)

#define	DMA_CSR_BWC_SHIFT (14U)

#define	DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

#define	DMA_CSR_START_MASK 0x1u

#define	DMA_CSR_START_SHIFT 0

#define	DMA_CSR_INTMAJOR_MASK 0x2u

#define	DMA_CSR_INTMAJOR_SHIFT 1

#define	DMA_CSR_INTHALF_MASK 0x4u

#define	DMA_CSR_INTHALF_SHIFT 2

#define	DMA_CSR_DREQ_MASK 0x8u

#define	DMA_CSR_DREQ_SHIFT 3

#define	DMA_CSR_ESG_MASK 0x10u

#define	DMA_CSR_ESG_SHIFT 4

#define	DMA_CSR_MAJORELINK_MASK 0x20u

#define	DMA_CSR_MAJORELINK_SHIFT 5

#define	DMA_CSR_ACTIVE_MASK 0x40u

#define	DMA_CSR_ACTIVE_SHIFT 6

#define	DMA_CSR_DONE_MASK 0x80u

#define	DMA_CSR_DONE_SHIFT 7

#define	DMA_CSR_MAJORLINKCH_MASK 0xF00u

#define	DMA_CSR_MAJORLINKCH_SHIFT 8

#define	DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)

#define	DMA_CSR_BWC_MASK 0xC000u

#define	DMA_CSR_BWC_SHIFT 14

#define	DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)

#define	DMA_CSR_START_MASK (0x1U)

#define	DMA_CSR_START_SHIFT (0U)

#define	DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

#define	DMA_CSR_INTMAJOR_MASK (0x2U)

#define	DMA_CSR_INTMAJOR_SHIFT (1U)

#define	DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

#define	DMA_CSR_INTHALF_MASK (0x4U)

#define	DMA_CSR_INTHALF_SHIFT (2U)

#define	DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

#define	DMA_CSR_DREQ_MASK (0x8U)

#define	DMA_CSR_DREQ_SHIFT (3U)

#define	DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

#define	DMA_CSR_ESG_MASK (0x10U)

#define	DMA_CSR_ESG_SHIFT (4U)

#define	DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

#define	DMA_CSR_MAJORELINK_MASK (0x20U)

#define	DMA_CSR_MAJORELINK_SHIFT (5U)

#define	DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

#define	DMA_CSR_ACTIVE_MASK (0x40U)

#define	DMA_CSR_ACTIVE_SHIFT (6U)

#define	DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

#define	DMA_CSR_DONE_MASK (0x80U)

#define	DMA_CSR_DONE_SHIFT (7U)

#define	DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

#define	DMA_CSR_MAJORLINKCH_MASK (0xF00U)

#define	DMA_CSR_MAJORLINKCH_SHIFT (8U)

#define	DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

#define	DMA_CSR_BWC_MASK (0xC000U)

#define	DMA_CSR_BWC_SHIFT (14U)

#define	DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

#define	DMA_CSR_START_MASK (0x1U)

#define	DMA_CSR_START_SHIFT (0U)

#define	DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

#define	DMA_CSR_INTMAJOR_MASK (0x2U)

#define	DMA_CSR_INTMAJOR_SHIFT (1U)

#define	DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

#define	DMA_CSR_INTHALF_MASK (0x4U)

#define	DMA_CSR_INTHALF_SHIFT (2U)

#define	DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

#define	DMA_CSR_DREQ_MASK (0x8U)

#define	DMA_CSR_DREQ_SHIFT (3U)

#define	DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

#define	DMA_CSR_ESG_MASK (0x10U)

#define	DMA_CSR_ESG_SHIFT (4U)

#define	DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

#define	DMA_CSR_MAJORELINK_MASK (0x20U)

#define	DMA_CSR_MAJORELINK_SHIFT (5U)

#define	DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

#define	DMA_CSR_ACTIVE_MASK (0x40U)

#define	DMA_CSR_ACTIVE_SHIFT (6U)

#define	DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

#define	DMA_CSR_DONE_MASK (0x80U)

#define	DMA_CSR_DONE_SHIFT (7U)

#define	DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

#define	DMA_CSR_MAJORLINKCH_MASK (0x1F00U)

#define	DMA_CSR_MAJORLINKCH_SHIFT (8U)

#define	DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

#define	DMA_CSR_BWC_MASK (0xC000U)

#define	DMA_CSR_BWC_SHIFT (14U)

#define	DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

#define	DMA_CSR_START_MASK (0x1U)

#define	DMA_CSR_START_SHIFT (0U)

#define	DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

#define	DMA_CSR_INTMAJOR_MASK (0x2U)

#define	DMA_CSR_INTMAJOR_SHIFT (1U)

#define	DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

#define	DMA_CSR_INTHALF_MASK (0x4U)

#define	DMA_CSR_INTHALF_SHIFT (2U)

#define	DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

#define	DMA_CSR_DREQ_MASK (0x8U)

#define	DMA_CSR_DREQ_SHIFT (3U)

#define	DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

#define	DMA_CSR_ESG_MASK (0x10U)

#define	DMA_CSR_ESG_SHIFT (4U)

#define	DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

#define	DMA_CSR_MAJORELINK_MASK (0x20U)

#define	DMA_CSR_MAJORELINK_SHIFT (5U)

#define	DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

#define	DMA_CSR_ACTIVE_MASK (0x40U)

#define	DMA_CSR_ACTIVE_SHIFT (6U)

#define	DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

#define	DMA_CSR_DONE_MASK (0x80U)

#define	DMA_CSR_DONE_SHIFT (7U)

#define	DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

#define	DMA_CSR_MAJORLINKCH_MASK (0x1F00U)

#define	DMA_CSR_MAJORLINKCH_SHIFT (8U)

#define	DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

#define	DMA_CSR_BWC_MASK (0xC000U)

#define	DMA_CSR_BWC_SHIFT (14U)

#define	DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

#define	DMA_CSR_START_MASK (0x1U)

#define	DMA_CSR_START_SHIFT (0U)

#define	DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

#define	DMA_CSR_INTMAJOR_MASK (0x2U)

#define	DMA_CSR_INTMAJOR_SHIFT (1U)

#define	DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

#define	DMA_CSR_INTHALF_MASK (0x4U)

#define	DMA_CSR_INTHALF_SHIFT (2U)

#define	DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

#define	DMA_CSR_DREQ_MASK (0x8U)

#define	DMA_CSR_DREQ_SHIFT (3U)

#define	DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

#define	DMA_CSR_ESG_MASK (0x10U)

#define	DMA_CSR_ESG_SHIFT (4U)

#define	DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

#define	DMA_CSR_MAJORELINK_MASK (0x20U)

#define	DMA_CSR_MAJORELINK_SHIFT (5U)

#define	DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

#define	DMA_CSR_ACTIVE_MASK (0x40U)

#define	DMA_CSR_ACTIVE_SHIFT (6U)

#define	DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)

#define	DMA_CSR_DONE_MASK (0x80U)

#define	DMA_CSR_DONE_SHIFT (7U)

#define	DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)

#define	DMA_CSR_MAJORLINKCH_MASK (0x1F00U)

#define	DMA_CSR_MAJORLINKCH_SHIFT (8U)

#define	DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)

#define	DMA_CSR_BWC_MASK (0xC000U)

#define	DMA_CSR_BWC_SHIFT (14U)

#define	DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

CSR - TCD Control and Status
#define	DMA_CSR_COUNT (16U)

BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define	DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)

#define	DMA_BITER_ELINKNO_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

#define	DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

#define	DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu

#define	DMA_BITER_ELINKNO_BITER_SHIFT 0

#define	DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)

#define	DMA_BITER_ELINKNO_ELINK_MASK 0x8000u

#define	DMA_BITER_ELINKNO_ELINK_SHIFT 15

#define	DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)

#define	DMA_BITER_ELINKNO_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

#define	DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

#define	DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)

#define	DMA_BITER_ELINKNO_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

#define	DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

#define	DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)

#define	DMA_BITER_ELINKNO_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

#define	DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

#define	DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)

#define	DMA_BITER_ELINKNO_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)

#define	DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKNO_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
#define	DMA_BITER_ELINKNO_COUNT (16U)

BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define	DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)

#define	DMA_BITER_ELINKYES_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

#define	DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)

#define	DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

#define	DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

#define	DMA_BITER_ELINKYES_BITER_MASK 0x1FFu

#define	DMA_BITER_ELINKYES_BITER_SHIFT 0

#define	DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)

#define	DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u

#define	DMA_BITER_ELINKYES_LINKCH_SHIFT 9

#define	DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)

#define	DMA_BITER_ELINKYES_ELINK_MASK 0x8000u

#define	DMA_BITER_ELINKYES_ELINK_SHIFT 15

#define	DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)

#define	DMA_BITER_ELINKYES_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

#define	DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)

#define	DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

#define	DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

#define	DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)

#define	DMA_BITER_ELINKYES_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

#define	DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)

#define	DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

#define	DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

#define	DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)

#define	DMA_BITER_ELINKYES_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

#define	DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)

#define	DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

#define	DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

#define	DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)

#define	DMA_BITER_ELINKYES_BITER_SHIFT (0U)

#define	DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)

#define	DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)

#define	DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)

#define	DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)

#define	DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)

#define	DMA_BITER_ELINKYES_ELINK_SHIFT (15U)

#define	DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
#define	DMA_BITER_ELINKYES_COUNT (16U)

EARS - Enable Asynchronous Request in Stop Register
#define	DMA_EARS_EDREQ_0_MASK (0x1U)

#define	DMA_EARS_EDREQ_0_SHIFT (0U)

#define	DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

#define	DMA_EARS_EDREQ_1_MASK (0x2U)

#define	DMA_EARS_EDREQ_1_SHIFT (1U)

#define	DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

#define	DMA_EARS_EDREQ_2_MASK (0x4U)

#define	DMA_EARS_EDREQ_2_SHIFT (2U)

#define	DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

#define	DMA_EARS_EDREQ_3_MASK (0x8U)

#define	DMA_EARS_EDREQ_3_SHIFT (3U)

#define	DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

#define	DMA_EARS_EDREQ_4_MASK (0x10U)

#define	DMA_EARS_EDREQ_4_SHIFT (4U)

#define	DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

#define	DMA_EARS_EDREQ_5_MASK (0x20U)

#define	DMA_EARS_EDREQ_5_SHIFT (5U)

#define	DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

#define	DMA_EARS_EDREQ_6_MASK (0x40U)

#define	DMA_EARS_EDREQ_6_SHIFT (6U)

#define	DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

#define	DMA_EARS_EDREQ_7_MASK (0x80U)

#define	DMA_EARS_EDREQ_7_SHIFT (7U)

#define	DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

#define	DMA_EARS_EDREQ_8_MASK (0x100U)

#define	DMA_EARS_EDREQ_8_SHIFT (8U)

#define	DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

#define	DMA_EARS_EDREQ_9_MASK (0x200U)

#define	DMA_EARS_EDREQ_9_SHIFT (9U)

#define	DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

#define	DMA_EARS_EDREQ_10_MASK (0x400U)

#define	DMA_EARS_EDREQ_10_SHIFT (10U)

#define	DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

#define	DMA_EARS_EDREQ_11_MASK (0x800U)

#define	DMA_EARS_EDREQ_11_SHIFT (11U)

#define	DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

#define	DMA_EARS_EDREQ_12_MASK (0x1000U)

#define	DMA_EARS_EDREQ_12_SHIFT (12U)

#define	DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

#define	DMA_EARS_EDREQ_13_MASK (0x2000U)

#define	DMA_EARS_EDREQ_13_SHIFT (13U)

#define	DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

#define	DMA_EARS_EDREQ_14_MASK (0x4000U)

#define	DMA_EARS_EDREQ_14_SHIFT (14U)

#define	DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

#define	DMA_EARS_EDREQ_15_MASK (0x8000U)

#define	DMA_EARS_EDREQ_15_SHIFT (15U)

#define	DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

#define	DMA_EARS_EDREQ_16_MASK (0x10000U)

#define	DMA_EARS_EDREQ_16_SHIFT (16U)

#define	DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

#define	DMA_EARS_EDREQ_17_MASK (0x20000U)

#define	DMA_EARS_EDREQ_17_SHIFT (17U)

#define	DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

#define	DMA_EARS_EDREQ_18_MASK (0x40000U)

#define	DMA_EARS_EDREQ_18_SHIFT (18U)

#define	DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

#define	DMA_EARS_EDREQ_19_MASK (0x80000U)

#define	DMA_EARS_EDREQ_19_SHIFT (19U)

#define	DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

#define	DMA_EARS_EDREQ_20_MASK (0x100000U)

#define	DMA_EARS_EDREQ_20_SHIFT (20U)

#define	DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

#define	DMA_EARS_EDREQ_21_MASK (0x200000U)

#define	DMA_EARS_EDREQ_21_SHIFT (21U)

#define	DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

#define	DMA_EARS_EDREQ_22_MASK (0x400000U)

#define	DMA_EARS_EDREQ_22_SHIFT (22U)

#define	DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

#define	DMA_EARS_EDREQ_23_MASK (0x800000U)

#define	DMA_EARS_EDREQ_23_SHIFT (23U)

#define	DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

#define	DMA_EARS_EDREQ_24_MASK (0x1000000U)

#define	DMA_EARS_EDREQ_24_SHIFT (24U)

#define	DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

#define	DMA_EARS_EDREQ_25_MASK (0x2000000U)

#define	DMA_EARS_EDREQ_25_SHIFT (25U)

#define	DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

#define	DMA_EARS_EDREQ_26_MASK (0x4000000U)

#define	DMA_EARS_EDREQ_26_SHIFT (26U)

#define	DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

#define	DMA_EARS_EDREQ_27_MASK (0x8000000U)

#define	DMA_EARS_EDREQ_27_SHIFT (27U)

#define	DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

#define	DMA_EARS_EDREQ_28_MASK (0x10000000U)

#define	DMA_EARS_EDREQ_28_SHIFT (28U)

#define	DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

#define	DMA_EARS_EDREQ_29_MASK (0x20000000U)

#define	DMA_EARS_EDREQ_29_SHIFT (29U)

#define	DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

#define	DMA_EARS_EDREQ_30_MASK (0x40000000U)

#define	DMA_EARS_EDREQ_30_SHIFT (30U)

#define	DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

#define	DMA_EARS_EDREQ_31_MASK (0x80000000U)

#define	DMA_EARS_EDREQ_31_SHIFT (31U)

#define	DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

#define	DMA_EARS_EDREQ_0_MASK (0x1U)

#define	DMA_EARS_EDREQ_0_SHIFT (0U)

#define	DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

#define	DMA_EARS_EDREQ_1_MASK (0x2U)

#define	DMA_EARS_EDREQ_1_SHIFT (1U)

#define	DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

#define	DMA_EARS_EDREQ_2_MASK (0x4U)

#define	DMA_EARS_EDREQ_2_SHIFT (2U)

#define	DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

#define	DMA_EARS_EDREQ_3_MASK (0x8U)

#define	DMA_EARS_EDREQ_3_SHIFT (3U)

#define	DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

#define	DMA_EARS_EDREQ_4_MASK (0x10U)

#define	DMA_EARS_EDREQ_4_SHIFT (4U)

#define	DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

#define	DMA_EARS_EDREQ_5_MASK (0x20U)

#define	DMA_EARS_EDREQ_5_SHIFT (5U)

#define	DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

#define	DMA_EARS_EDREQ_6_MASK (0x40U)

#define	DMA_EARS_EDREQ_6_SHIFT (6U)

#define	DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

#define	DMA_EARS_EDREQ_7_MASK (0x80U)

#define	DMA_EARS_EDREQ_7_SHIFT (7U)

#define	DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

#define	DMA_EARS_EDREQ_8_MASK (0x100U)

#define	DMA_EARS_EDREQ_8_SHIFT (8U)

#define	DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

#define	DMA_EARS_EDREQ_9_MASK (0x200U)

#define	DMA_EARS_EDREQ_9_SHIFT (9U)

#define	DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

#define	DMA_EARS_EDREQ_10_MASK (0x400U)

#define	DMA_EARS_EDREQ_10_SHIFT (10U)

#define	DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

#define	DMA_EARS_EDREQ_11_MASK (0x800U)

#define	DMA_EARS_EDREQ_11_SHIFT (11U)

#define	DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

#define	DMA_EARS_EDREQ_12_MASK (0x1000U)

#define	DMA_EARS_EDREQ_12_SHIFT (12U)

#define	DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

#define	DMA_EARS_EDREQ_13_MASK (0x2000U)

#define	DMA_EARS_EDREQ_13_SHIFT (13U)

#define	DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

#define	DMA_EARS_EDREQ_14_MASK (0x4000U)

#define	DMA_EARS_EDREQ_14_SHIFT (14U)

#define	DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

#define	DMA_EARS_EDREQ_15_MASK (0x8000U)

#define	DMA_EARS_EDREQ_15_SHIFT (15U)

#define	DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

#define	DMA_EARS_EDREQ_16_MASK (0x10000U)

#define	DMA_EARS_EDREQ_16_SHIFT (16U)

#define	DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

#define	DMA_EARS_EDREQ_17_MASK (0x20000U)

#define	DMA_EARS_EDREQ_17_SHIFT (17U)

#define	DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

#define	DMA_EARS_EDREQ_18_MASK (0x40000U)

#define	DMA_EARS_EDREQ_18_SHIFT (18U)

#define	DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

#define	DMA_EARS_EDREQ_19_MASK (0x80000U)

#define	DMA_EARS_EDREQ_19_SHIFT (19U)

#define	DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

#define	DMA_EARS_EDREQ_20_MASK (0x100000U)

#define	DMA_EARS_EDREQ_20_SHIFT (20U)

#define	DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

#define	DMA_EARS_EDREQ_21_MASK (0x200000U)

#define	DMA_EARS_EDREQ_21_SHIFT (21U)

#define	DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

#define	DMA_EARS_EDREQ_22_MASK (0x400000U)

#define	DMA_EARS_EDREQ_22_SHIFT (22U)

#define	DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

#define	DMA_EARS_EDREQ_23_MASK (0x800000U)

#define	DMA_EARS_EDREQ_23_SHIFT (23U)

#define	DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

#define	DMA_EARS_EDREQ_24_MASK (0x1000000U)

#define	DMA_EARS_EDREQ_24_SHIFT (24U)

#define	DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

#define	DMA_EARS_EDREQ_25_MASK (0x2000000U)

#define	DMA_EARS_EDREQ_25_SHIFT (25U)

#define	DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

#define	DMA_EARS_EDREQ_26_MASK (0x4000000U)

#define	DMA_EARS_EDREQ_26_SHIFT (26U)

#define	DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

#define	DMA_EARS_EDREQ_27_MASK (0x8000000U)

#define	DMA_EARS_EDREQ_27_SHIFT (27U)

#define	DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

#define	DMA_EARS_EDREQ_28_MASK (0x10000000U)

#define	DMA_EARS_EDREQ_28_SHIFT (28U)

#define	DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

#define	DMA_EARS_EDREQ_29_MASK (0x20000000U)

#define	DMA_EARS_EDREQ_29_SHIFT (29U)

#define	DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

#define	DMA_EARS_EDREQ_30_MASK (0x40000000U)

#define	DMA_EARS_EDREQ_30_SHIFT (30U)

#define	DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

#define	DMA_EARS_EDREQ_31_MASK (0x80000000U)

#define	DMA_EARS_EDREQ_31_SHIFT (31U)

#define	DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

#define	DMA_EARS_EDREQ_0_MASK (0x1U)

#define	DMA_EARS_EDREQ_0_SHIFT (0U)

#define	DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

#define	DMA_EARS_EDREQ_1_MASK (0x2U)

#define	DMA_EARS_EDREQ_1_SHIFT (1U)

#define	DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

#define	DMA_EARS_EDREQ_2_MASK (0x4U)

#define	DMA_EARS_EDREQ_2_SHIFT (2U)

#define	DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

#define	DMA_EARS_EDREQ_3_MASK (0x8U)

#define	DMA_EARS_EDREQ_3_SHIFT (3U)

#define	DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

#define	DMA_EARS_EDREQ_4_MASK (0x10U)

#define	DMA_EARS_EDREQ_4_SHIFT (4U)

#define	DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

#define	DMA_EARS_EDREQ_5_MASK (0x20U)

#define	DMA_EARS_EDREQ_5_SHIFT (5U)

#define	DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

#define	DMA_EARS_EDREQ_6_MASK (0x40U)

#define	DMA_EARS_EDREQ_6_SHIFT (6U)

#define	DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

#define	DMA_EARS_EDREQ_7_MASK (0x80U)

#define	DMA_EARS_EDREQ_7_SHIFT (7U)

#define	DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

#define	DMA_EARS_EDREQ_8_MASK (0x100U)

#define	DMA_EARS_EDREQ_8_SHIFT (8U)

#define	DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

#define	DMA_EARS_EDREQ_9_MASK (0x200U)

#define	DMA_EARS_EDREQ_9_SHIFT (9U)

#define	DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

#define	DMA_EARS_EDREQ_10_MASK (0x400U)

#define	DMA_EARS_EDREQ_10_SHIFT (10U)

#define	DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

#define	DMA_EARS_EDREQ_11_MASK (0x800U)

#define	DMA_EARS_EDREQ_11_SHIFT (11U)

#define	DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

#define	DMA_EARS_EDREQ_12_MASK (0x1000U)

#define	DMA_EARS_EDREQ_12_SHIFT (12U)

#define	DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

#define	DMA_EARS_EDREQ_13_MASK (0x2000U)

#define	DMA_EARS_EDREQ_13_SHIFT (13U)

#define	DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

#define	DMA_EARS_EDREQ_14_MASK (0x4000U)

#define	DMA_EARS_EDREQ_14_SHIFT (14U)

#define	DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

#define	DMA_EARS_EDREQ_15_MASK (0x8000U)

#define	DMA_EARS_EDREQ_15_SHIFT (15U)

#define	DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

#define	DMA_EARS_EDREQ_16_MASK (0x10000U)

#define	DMA_EARS_EDREQ_16_SHIFT (16U)

#define	DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

#define	DMA_EARS_EDREQ_17_MASK (0x20000U)

#define	DMA_EARS_EDREQ_17_SHIFT (17U)

#define	DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

#define	DMA_EARS_EDREQ_18_MASK (0x40000U)

#define	DMA_EARS_EDREQ_18_SHIFT (18U)

#define	DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

#define	DMA_EARS_EDREQ_19_MASK (0x80000U)

#define	DMA_EARS_EDREQ_19_SHIFT (19U)

#define	DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

#define	DMA_EARS_EDREQ_20_MASK (0x100000U)

#define	DMA_EARS_EDREQ_20_SHIFT (20U)

#define	DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

#define	DMA_EARS_EDREQ_21_MASK (0x200000U)

#define	DMA_EARS_EDREQ_21_SHIFT (21U)

#define	DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

#define	DMA_EARS_EDREQ_22_MASK (0x400000U)

#define	DMA_EARS_EDREQ_22_SHIFT (22U)

#define	DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

#define	DMA_EARS_EDREQ_23_MASK (0x800000U)

#define	DMA_EARS_EDREQ_23_SHIFT (23U)

#define	DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

#define	DMA_EARS_EDREQ_24_MASK (0x1000000U)

#define	DMA_EARS_EDREQ_24_SHIFT (24U)

#define	DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

#define	DMA_EARS_EDREQ_25_MASK (0x2000000U)

#define	DMA_EARS_EDREQ_25_SHIFT (25U)

#define	DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

#define	DMA_EARS_EDREQ_26_MASK (0x4000000U)

#define	DMA_EARS_EDREQ_26_SHIFT (26U)

#define	DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

#define	DMA_EARS_EDREQ_27_MASK (0x8000000U)

#define	DMA_EARS_EDREQ_27_SHIFT (27U)

#define	DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

#define	DMA_EARS_EDREQ_28_MASK (0x10000000U)

#define	DMA_EARS_EDREQ_28_SHIFT (28U)

#define	DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

#define	DMA_EARS_EDREQ_29_MASK (0x20000000U)

#define	DMA_EARS_EDREQ_29_SHIFT (29U)

#define	DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

#define	DMA_EARS_EDREQ_30_MASK (0x40000000U)

#define	DMA_EARS_EDREQ_30_SHIFT (30U)

#define	DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

#define	DMA_EARS_EDREQ_31_MASK (0x80000000U)

#define	DMA_EARS_EDREQ_31_SHIFT (31U)

#define	DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

DCHPRI19 - Channel n Priority Register
#define	DMA_DCHPRI19_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI19_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)

#define	DMA_DCHPRI19_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI19_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)

#define	DMA_DCHPRI19_DPA_MASK (0x40U)

#define	DMA_DCHPRI19_DPA_SHIFT (6U)

#define	DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

#define	DMA_DCHPRI19_ECP_MASK (0x80U)

#define	DMA_DCHPRI19_ECP_SHIFT (7U)

#define	DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

#define	DMA_DCHPRI19_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI19_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)

#define	DMA_DCHPRI19_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI19_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)

#define	DMA_DCHPRI19_DPA_MASK (0x40U)

#define	DMA_DCHPRI19_DPA_SHIFT (6U)

#define	DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

#define	DMA_DCHPRI19_ECP_MASK (0x80U)

#define	DMA_DCHPRI19_ECP_SHIFT (7U)

#define	DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

#define	DMA_DCHPRI19_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI19_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)

#define	DMA_DCHPRI19_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI19_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)

#define	DMA_DCHPRI19_DPA_MASK (0x40U)

#define	DMA_DCHPRI19_DPA_SHIFT (6U)

#define	DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

#define	DMA_DCHPRI19_ECP_MASK (0x80U)

#define	DMA_DCHPRI19_ECP_SHIFT (7U)

#define	DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

DCHPRI18 - Channel n Priority Register
#define	DMA_DCHPRI18_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI18_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)

#define	DMA_DCHPRI18_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI18_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)

#define	DMA_DCHPRI18_DPA_MASK (0x40U)

#define	DMA_DCHPRI18_DPA_SHIFT (6U)

#define	DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

#define	DMA_DCHPRI18_ECP_MASK (0x80U)

#define	DMA_DCHPRI18_ECP_SHIFT (7U)

#define	DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

#define	DMA_DCHPRI18_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI18_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)

#define	DMA_DCHPRI18_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI18_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)

#define	DMA_DCHPRI18_DPA_MASK (0x40U)

#define	DMA_DCHPRI18_DPA_SHIFT (6U)

#define	DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

#define	DMA_DCHPRI18_ECP_MASK (0x80U)

#define	DMA_DCHPRI18_ECP_SHIFT (7U)

#define	DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

#define	DMA_DCHPRI18_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI18_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)

#define	DMA_DCHPRI18_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI18_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)

#define	DMA_DCHPRI18_DPA_MASK (0x40U)

#define	DMA_DCHPRI18_DPA_SHIFT (6U)

#define	DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

#define	DMA_DCHPRI18_ECP_MASK (0x80U)

#define	DMA_DCHPRI18_ECP_SHIFT (7U)

#define	DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

DCHPRI17 - Channel n Priority Register
#define	DMA_DCHPRI17_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI17_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)

#define	DMA_DCHPRI17_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI17_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)

#define	DMA_DCHPRI17_DPA_MASK (0x40U)

#define	DMA_DCHPRI17_DPA_SHIFT (6U)

#define	DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

#define	DMA_DCHPRI17_ECP_MASK (0x80U)

#define	DMA_DCHPRI17_ECP_SHIFT (7U)

#define	DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

#define	DMA_DCHPRI17_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI17_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)

#define	DMA_DCHPRI17_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI17_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)

#define	DMA_DCHPRI17_DPA_MASK (0x40U)

#define	DMA_DCHPRI17_DPA_SHIFT (6U)

#define	DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

#define	DMA_DCHPRI17_ECP_MASK (0x80U)

#define	DMA_DCHPRI17_ECP_SHIFT (7U)

#define	DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

#define	DMA_DCHPRI17_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI17_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)

#define	DMA_DCHPRI17_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI17_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)

#define	DMA_DCHPRI17_DPA_MASK (0x40U)

#define	DMA_DCHPRI17_DPA_SHIFT (6U)

#define	DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

#define	DMA_DCHPRI17_ECP_MASK (0x80U)

#define	DMA_DCHPRI17_ECP_SHIFT (7U)

#define	DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

DCHPRI16 - Channel n Priority Register
#define	DMA_DCHPRI16_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI16_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)

#define	DMA_DCHPRI16_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI16_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)

#define	DMA_DCHPRI16_DPA_MASK (0x40U)

#define	DMA_DCHPRI16_DPA_SHIFT (6U)

#define	DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

#define	DMA_DCHPRI16_ECP_MASK (0x80U)

#define	DMA_DCHPRI16_ECP_SHIFT (7U)

#define	DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

#define	DMA_DCHPRI16_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI16_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)

#define	DMA_DCHPRI16_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI16_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)

#define	DMA_DCHPRI16_DPA_MASK (0x40U)

#define	DMA_DCHPRI16_DPA_SHIFT (6U)

#define	DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

#define	DMA_DCHPRI16_ECP_MASK (0x80U)

#define	DMA_DCHPRI16_ECP_SHIFT (7U)

#define	DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

#define	DMA_DCHPRI16_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI16_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)

#define	DMA_DCHPRI16_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI16_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)

#define	DMA_DCHPRI16_DPA_MASK (0x40U)

#define	DMA_DCHPRI16_DPA_SHIFT (6U)

#define	DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

#define	DMA_DCHPRI16_ECP_MASK (0x80U)

#define	DMA_DCHPRI16_ECP_SHIFT (7U)

#define	DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

DCHPRI23 - Channel n Priority Register
#define	DMA_DCHPRI23_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI23_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)

#define	DMA_DCHPRI23_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI23_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)

#define	DMA_DCHPRI23_DPA_MASK (0x40U)

#define	DMA_DCHPRI23_DPA_SHIFT (6U)

#define	DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

#define	DMA_DCHPRI23_ECP_MASK (0x80U)

#define	DMA_DCHPRI23_ECP_SHIFT (7U)

#define	DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

#define	DMA_DCHPRI23_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI23_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)

#define	DMA_DCHPRI23_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI23_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)

#define	DMA_DCHPRI23_DPA_MASK (0x40U)

#define	DMA_DCHPRI23_DPA_SHIFT (6U)

#define	DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

#define	DMA_DCHPRI23_ECP_MASK (0x80U)

#define	DMA_DCHPRI23_ECP_SHIFT (7U)

#define	DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

#define	DMA_DCHPRI23_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI23_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)

#define	DMA_DCHPRI23_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI23_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)

#define	DMA_DCHPRI23_DPA_MASK (0x40U)

#define	DMA_DCHPRI23_DPA_SHIFT (6U)

#define	DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

#define	DMA_DCHPRI23_ECP_MASK (0x80U)

#define	DMA_DCHPRI23_ECP_SHIFT (7U)

#define	DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

DCHPRI22 - Channel n Priority Register
#define	DMA_DCHPRI22_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI22_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)

#define	DMA_DCHPRI22_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI22_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)

#define	DMA_DCHPRI22_DPA_MASK (0x40U)

#define	DMA_DCHPRI22_DPA_SHIFT (6U)

#define	DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

#define	DMA_DCHPRI22_ECP_MASK (0x80U)

#define	DMA_DCHPRI22_ECP_SHIFT (7U)

#define	DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

#define	DMA_DCHPRI22_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI22_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)

#define	DMA_DCHPRI22_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI22_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)

#define	DMA_DCHPRI22_DPA_MASK (0x40U)

#define	DMA_DCHPRI22_DPA_SHIFT (6U)

#define	DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

#define	DMA_DCHPRI22_ECP_MASK (0x80U)

#define	DMA_DCHPRI22_ECP_SHIFT (7U)

#define	DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

#define	DMA_DCHPRI22_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI22_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)

#define	DMA_DCHPRI22_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI22_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)

#define	DMA_DCHPRI22_DPA_MASK (0x40U)

#define	DMA_DCHPRI22_DPA_SHIFT (6U)

#define	DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

#define	DMA_DCHPRI22_ECP_MASK (0x80U)

#define	DMA_DCHPRI22_ECP_SHIFT (7U)

#define	DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

DCHPRI21 - Channel n Priority Register
#define	DMA_DCHPRI21_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI21_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)

#define	DMA_DCHPRI21_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI21_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)

#define	DMA_DCHPRI21_DPA_MASK (0x40U)

#define	DMA_DCHPRI21_DPA_SHIFT (6U)

#define	DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

#define	DMA_DCHPRI21_ECP_MASK (0x80U)

#define	DMA_DCHPRI21_ECP_SHIFT (7U)

#define	DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

#define	DMA_DCHPRI21_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI21_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)

#define	DMA_DCHPRI21_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI21_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)

#define	DMA_DCHPRI21_DPA_MASK (0x40U)

#define	DMA_DCHPRI21_DPA_SHIFT (6U)

#define	DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

#define	DMA_DCHPRI21_ECP_MASK (0x80U)

#define	DMA_DCHPRI21_ECP_SHIFT (7U)

#define	DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

#define	DMA_DCHPRI21_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI21_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)

#define	DMA_DCHPRI21_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI21_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)

#define	DMA_DCHPRI21_DPA_MASK (0x40U)

#define	DMA_DCHPRI21_DPA_SHIFT (6U)

#define	DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

#define	DMA_DCHPRI21_ECP_MASK (0x80U)

#define	DMA_DCHPRI21_ECP_SHIFT (7U)

#define	DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

DCHPRI20 - Channel n Priority Register
#define	DMA_DCHPRI20_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI20_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)

#define	DMA_DCHPRI20_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI20_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)

#define	DMA_DCHPRI20_DPA_MASK (0x40U)

#define	DMA_DCHPRI20_DPA_SHIFT (6U)

#define	DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

#define	DMA_DCHPRI20_ECP_MASK (0x80U)

#define	DMA_DCHPRI20_ECP_SHIFT (7U)

#define	DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

#define	DMA_DCHPRI20_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI20_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)

#define	DMA_DCHPRI20_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI20_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)

#define	DMA_DCHPRI20_DPA_MASK (0x40U)

#define	DMA_DCHPRI20_DPA_SHIFT (6U)

#define	DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

#define	DMA_DCHPRI20_ECP_MASK (0x80U)

#define	DMA_DCHPRI20_ECP_SHIFT (7U)

#define	DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

#define	DMA_DCHPRI20_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI20_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)

#define	DMA_DCHPRI20_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI20_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)

#define	DMA_DCHPRI20_DPA_MASK (0x40U)

#define	DMA_DCHPRI20_DPA_SHIFT (6U)

#define	DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

#define	DMA_DCHPRI20_ECP_MASK (0x80U)

#define	DMA_DCHPRI20_ECP_SHIFT (7U)

#define	DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

DCHPRI27 - Channel n Priority Register
#define	DMA_DCHPRI27_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI27_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)

#define	DMA_DCHPRI27_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI27_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)

#define	DMA_DCHPRI27_DPA_MASK (0x40U)

#define	DMA_DCHPRI27_DPA_SHIFT (6U)

#define	DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

#define	DMA_DCHPRI27_ECP_MASK (0x80U)

#define	DMA_DCHPRI27_ECP_SHIFT (7U)

#define	DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

#define	DMA_DCHPRI27_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI27_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)

#define	DMA_DCHPRI27_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI27_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)

#define	DMA_DCHPRI27_DPA_MASK (0x40U)

#define	DMA_DCHPRI27_DPA_SHIFT (6U)

#define	DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

#define	DMA_DCHPRI27_ECP_MASK (0x80U)

#define	DMA_DCHPRI27_ECP_SHIFT (7U)

#define	DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

#define	DMA_DCHPRI27_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI27_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)

#define	DMA_DCHPRI27_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI27_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)

#define	DMA_DCHPRI27_DPA_MASK (0x40U)

#define	DMA_DCHPRI27_DPA_SHIFT (6U)

#define	DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

#define	DMA_DCHPRI27_ECP_MASK (0x80U)

#define	DMA_DCHPRI27_ECP_SHIFT (7U)

#define	DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

DCHPRI26 - Channel n Priority Register
#define	DMA_DCHPRI26_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI26_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)

#define	DMA_DCHPRI26_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI26_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)

#define	DMA_DCHPRI26_DPA_MASK (0x40U)

#define	DMA_DCHPRI26_DPA_SHIFT (6U)

#define	DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

#define	DMA_DCHPRI26_ECP_MASK (0x80U)

#define	DMA_DCHPRI26_ECP_SHIFT (7U)

#define	DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

#define	DMA_DCHPRI26_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI26_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)

#define	DMA_DCHPRI26_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI26_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)

#define	DMA_DCHPRI26_DPA_MASK (0x40U)

#define	DMA_DCHPRI26_DPA_SHIFT (6U)

#define	DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

#define	DMA_DCHPRI26_ECP_MASK (0x80U)

#define	DMA_DCHPRI26_ECP_SHIFT (7U)

#define	DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

#define	DMA_DCHPRI26_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI26_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)

#define	DMA_DCHPRI26_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI26_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)

#define	DMA_DCHPRI26_DPA_MASK (0x40U)

#define	DMA_DCHPRI26_DPA_SHIFT (6U)

#define	DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

#define	DMA_DCHPRI26_ECP_MASK (0x80U)

#define	DMA_DCHPRI26_ECP_SHIFT (7U)

#define	DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

DCHPRI25 - Channel n Priority Register
#define	DMA_DCHPRI25_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI25_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)

#define	DMA_DCHPRI25_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI25_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)

#define	DMA_DCHPRI25_DPA_MASK (0x40U)

#define	DMA_DCHPRI25_DPA_SHIFT (6U)

#define	DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

#define	DMA_DCHPRI25_ECP_MASK (0x80U)

#define	DMA_DCHPRI25_ECP_SHIFT (7U)

#define	DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

#define	DMA_DCHPRI25_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI25_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)

#define	DMA_DCHPRI25_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI25_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)

#define	DMA_DCHPRI25_DPA_MASK (0x40U)

#define	DMA_DCHPRI25_DPA_SHIFT (6U)

#define	DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

#define	DMA_DCHPRI25_ECP_MASK (0x80U)

#define	DMA_DCHPRI25_ECP_SHIFT (7U)

#define	DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

#define	DMA_DCHPRI25_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI25_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)

#define	DMA_DCHPRI25_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI25_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)

#define	DMA_DCHPRI25_DPA_MASK (0x40U)

#define	DMA_DCHPRI25_DPA_SHIFT (6U)

#define	DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

#define	DMA_DCHPRI25_ECP_MASK (0x80U)

#define	DMA_DCHPRI25_ECP_SHIFT (7U)

#define	DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

DCHPRI24 - Channel n Priority Register
#define	DMA_DCHPRI24_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI24_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)

#define	DMA_DCHPRI24_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI24_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)

#define	DMA_DCHPRI24_DPA_MASK (0x40U)

#define	DMA_DCHPRI24_DPA_SHIFT (6U)

#define	DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

#define	DMA_DCHPRI24_ECP_MASK (0x80U)

#define	DMA_DCHPRI24_ECP_SHIFT (7U)

#define	DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

#define	DMA_DCHPRI24_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI24_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)

#define	DMA_DCHPRI24_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI24_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)

#define	DMA_DCHPRI24_DPA_MASK (0x40U)

#define	DMA_DCHPRI24_DPA_SHIFT (6U)

#define	DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

#define	DMA_DCHPRI24_ECP_MASK (0x80U)

#define	DMA_DCHPRI24_ECP_SHIFT (7U)

#define	DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

#define	DMA_DCHPRI24_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI24_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)

#define	DMA_DCHPRI24_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI24_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)

#define	DMA_DCHPRI24_DPA_MASK (0x40U)

#define	DMA_DCHPRI24_DPA_SHIFT (6U)

#define	DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

#define	DMA_DCHPRI24_ECP_MASK (0x80U)

#define	DMA_DCHPRI24_ECP_SHIFT (7U)

#define	DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

DCHPRI31 - Channel n Priority Register
#define	DMA_DCHPRI31_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI31_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)

#define	DMA_DCHPRI31_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI31_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)

#define	DMA_DCHPRI31_DPA_MASK (0x40U)

#define	DMA_DCHPRI31_DPA_SHIFT (6U)

#define	DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

#define	DMA_DCHPRI31_ECP_MASK (0x80U)

#define	DMA_DCHPRI31_ECP_SHIFT (7U)

#define	DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

#define	DMA_DCHPRI31_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI31_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)

#define	DMA_DCHPRI31_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI31_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)

#define	DMA_DCHPRI31_DPA_MASK (0x40U)

#define	DMA_DCHPRI31_DPA_SHIFT (6U)

#define	DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

#define	DMA_DCHPRI31_ECP_MASK (0x80U)

#define	DMA_DCHPRI31_ECP_SHIFT (7U)

#define	DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

#define	DMA_DCHPRI31_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI31_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)

#define	DMA_DCHPRI31_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI31_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)

#define	DMA_DCHPRI31_DPA_MASK (0x40U)

#define	DMA_DCHPRI31_DPA_SHIFT (6U)

#define	DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

#define	DMA_DCHPRI31_ECP_MASK (0x80U)

#define	DMA_DCHPRI31_ECP_SHIFT (7U)

#define	DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

DCHPRI30 - Channel n Priority Register
#define	DMA_DCHPRI30_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI30_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)

#define	DMA_DCHPRI30_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI30_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)

#define	DMA_DCHPRI30_DPA_MASK (0x40U)

#define	DMA_DCHPRI30_DPA_SHIFT (6U)

#define	DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

#define	DMA_DCHPRI30_ECP_MASK (0x80U)

#define	DMA_DCHPRI30_ECP_SHIFT (7U)

#define	DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

#define	DMA_DCHPRI30_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI30_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)

#define	DMA_DCHPRI30_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI30_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)

#define	DMA_DCHPRI30_DPA_MASK (0x40U)

#define	DMA_DCHPRI30_DPA_SHIFT (6U)

#define	DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

#define	DMA_DCHPRI30_ECP_MASK (0x80U)

#define	DMA_DCHPRI30_ECP_SHIFT (7U)

#define	DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

#define	DMA_DCHPRI30_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI30_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)

#define	DMA_DCHPRI30_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI30_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)

#define	DMA_DCHPRI30_DPA_MASK (0x40U)

#define	DMA_DCHPRI30_DPA_SHIFT (6U)

#define	DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

#define	DMA_DCHPRI30_ECP_MASK (0x80U)

#define	DMA_DCHPRI30_ECP_SHIFT (7U)

#define	DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

DCHPRI29 - Channel n Priority Register
#define	DMA_DCHPRI29_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI29_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)

#define	DMA_DCHPRI29_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI29_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)

#define	DMA_DCHPRI29_DPA_MASK (0x40U)

#define	DMA_DCHPRI29_DPA_SHIFT (6U)

#define	DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

#define	DMA_DCHPRI29_ECP_MASK (0x80U)

#define	DMA_DCHPRI29_ECP_SHIFT (7U)

#define	DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

#define	DMA_DCHPRI29_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI29_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)

#define	DMA_DCHPRI29_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI29_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)

#define	DMA_DCHPRI29_DPA_MASK (0x40U)

#define	DMA_DCHPRI29_DPA_SHIFT (6U)

#define	DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

#define	DMA_DCHPRI29_ECP_MASK (0x80U)

#define	DMA_DCHPRI29_ECP_SHIFT (7U)

#define	DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

#define	DMA_DCHPRI29_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI29_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)

#define	DMA_DCHPRI29_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI29_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)

#define	DMA_DCHPRI29_DPA_MASK (0x40U)

#define	DMA_DCHPRI29_DPA_SHIFT (6U)

#define	DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

#define	DMA_DCHPRI29_ECP_MASK (0x80U)

#define	DMA_DCHPRI29_ECP_SHIFT (7U)

#define	DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

DCHPRI28 - Channel n Priority Register
#define	DMA_DCHPRI28_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI28_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)

#define	DMA_DCHPRI28_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI28_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)

#define	DMA_DCHPRI28_DPA_MASK (0x40U)

#define	DMA_DCHPRI28_DPA_SHIFT (6U)

#define	DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

#define	DMA_DCHPRI28_ECP_MASK (0x80U)

#define	DMA_DCHPRI28_ECP_SHIFT (7U)

#define	DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

#define	DMA_DCHPRI28_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI28_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)

#define	DMA_DCHPRI28_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI28_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)

#define	DMA_DCHPRI28_DPA_MASK (0x40U)

#define	DMA_DCHPRI28_DPA_SHIFT (6U)

#define	DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

#define	DMA_DCHPRI28_ECP_MASK (0x80U)

#define	DMA_DCHPRI28_ECP_SHIFT (7U)

#define	DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

#define	DMA_DCHPRI28_CHPRI_MASK (0xFU)

#define	DMA_DCHPRI28_CHPRI_SHIFT (0U)

#define	DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)

#define	DMA_DCHPRI28_GRPPRI_MASK (0x30U)

#define	DMA_DCHPRI28_GRPPRI_SHIFT (4U)

#define	DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)

#define	DMA_DCHPRI28_DPA_MASK (0x40U)

#define	DMA_DCHPRI28_DPA_SHIFT (6U)

#define	DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

#define	DMA_DCHPRI28_ECP_MASK (0x80U)

#define	DMA_DCHPRI28_ECP_SHIFT (7U)

#define	DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

Macro Definition Documentation

◆ DMA0

#define DMA0 ((DMA_Type *)DMA_BASE)

Peripheral DMA base pointer

◆ DMA_ATTR_SMOD [1/6]

#define DMA_ATTR_SMOD ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo. 0b00000..Source address modulo feature is disabled

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled

◆ DMA_ATTR_SMOD [2/6]

#define DMA_ATTR_SMOD ( x ) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo. 0b00000..Source address modulo feature is disabled

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled

◆ DMA_ATTR_SMOD [3/6]

#define DMA_ATTR_SMOD ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo. 0b00000..Source address modulo feature is disabled

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled

◆ DMA_ATTR_SMOD [4/6]

#define DMA_ATTR_SMOD ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled

◆ DMA_ATTR_SMOD [5/6]

#define DMA_ATTR_SMOD ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled

◆ DMA_ATTR_SMOD [6/6]

#define DMA_ATTR_SMOD ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)

SMOD - Source Address Modulo 0b00000..Source address modulo feature is disabled

◆ DMA_ATTR_SSIZE [1/6]

#define DMA_ATTR_SSIZE ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..Reserved 0b100..16-byte 0b101..32-byte 0b110..Reserved 0b111..Reserved

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..Reserved 0b100..16-byte burst 0b101..32-byte burst 0b110..Reserved 0b111..Reserved

◆ DMA_ATTR_SSIZE [2/6]

#define DMA_ATTR_SSIZE ( x ) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..Reserved 0b100..16-byte 0b101..32-byte 0b110..Reserved 0b111..Reserved

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..Reserved 0b100..16-byte burst 0b101..32-byte burst 0b110..Reserved 0b111..Reserved

◆ DMA_ATTR_SSIZE [3/6]

#define DMA_ATTR_SSIZE ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..Reserved 0b100..16-byte 0b101..32-byte 0b110..Reserved 0b111..Reserved

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..Reserved 0b100..16-byte burst 0b101..32-byte burst 0b110..Reserved 0b111..Reserved

◆ DMA_ATTR_SSIZE [4/6]

#define DMA_ATTR_SSIZE ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..Reserved 0b100..16-byte burst 0b101..32-byte burst 0b110..Reserved 0b111..Reserved

◆ DMA_ATTR_SSIZE [5/6]

#define DMA_ATTR_SSIZE ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..Reserved 0b100..16-byte burst 0b101..32-byte burst 0b110..Reserved 0b111..Reserved

◆ DMA_ATTR_SSIZE [6/6]

#define DMA_ATTR_SSIZE ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)

SSIZE - Source data transfer size 0b000..8-bit 0b001..16-bit 0b010..32-bit 0b011..Reserved 0b100..16-byte burst 0b101..32-byte burst 0b110..Reserved 0b111..Reserved

◆ DMA_BASE

#define DMA_BASE (0x40008000u)

Peripheral DMA base address

◆ DMA_BASE_ADDRS

#define DMA_BASE_ADDRS { DMA_BASE }

Array initializer of DMA peripheral base addresses

◆ DMA_BASE_PTRS

#define DMA_BASE_PTRS { DMA0 }

Array initializer of DMA peripheral base pointers

◆ DMA_BITER_ELINKNO_ELINK [1/5]

#define DMA_BITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_BITER_ELINKNO_ELINK [2/5]

#define DMA_BITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_BITER_ELINKNO_ELINK [3/5]

#define DMA_BITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_BITER_ELINKNO_ELINK [4/5]

#define DMA_BITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_BITER_ELINKNO_ELINK [5/5]

#define DMA_BITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_BITER_ELINKYES_ELINK [1/5]

#define DMA_BITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_BITER_ELINKYES_ELINK [2/5]

#define DMA_BITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_BITER_ELINKYES_ELINK [3/5]

#define DMA_BITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_BITER_ELINKYES_ELINK [4/5]

#define DMA_BITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_BITER_ELINKYES_ELINK [5/5]

#define DMA_BITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)

ELINK - Enables channel-to-channel linking on minor loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CDNE_CADN [1/5]

#define DMA_CDNE_CADN ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

CADN - Clears All DONE Bits 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 0b1..Clears all bits in TCDn_CSR[DONE]

◆ DMA_CDNE_CADN [2/5]

#define DMA_CDNE_CADN ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

CADN - Clears All DONE Bits 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 0b1..Clears all bits in TCDn_CSR[DONE]

◆ DMA_CDNE_CADN [3/5]

#define DMA_CDNE_CADN ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

CADN - Clears All DONE Bits 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 0b1..Clears all bits in TCDn_CSR[DONE]

◆ DMA_CDNE_CADN [4/5]

#define DMA_CDNE_CADN ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

CADN - Clears All DONE Bits 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 0b1..Clears all bits in TCDn_CSR[DONE]

◆ DMA_CDNE_CADN [5/5]

#define DMA_CDNE_CADN ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)

CADN - Clears All DONE Bits 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 0b1..Clears all bits in TCDn_CSR[DONE]

◆ DMA_CDNE_NOP [1/5]

#define DMA_CDNE_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CDNE_NOP [2/5]

#define DMA_CDNE_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CDNE_NOP [3/5]

#define DMA_CDNE_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CDNE_NOP [4/5]

#define DMA_CDNE_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CDNE_NOP [5/5]

#define DMA_CDNE_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CEEI_CAEE [1/5]

#define DMA_CEEI_CAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

CAEE - Clear All Enable Error Interrupts 0b0..Clear only the EEI bit specified in the CEEI field 0b1..Clear all bits in EEI

◆ DMA_CEEI_CAEE [2/5]

#define DMA_CEEI_CAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

CAEE - Clear All Enable Error Interrupts 0b0..Clear only the EEI bit specified in the CEEI field 0b1..Clear all bits in EEI

◆ DMA_CEEI_CAEE [3/5]

#define DMA_CEEI_CAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

CAEE - Clear All Enable Error Interrupts 0b0..Clear only the EEI bit specified in the CEEI field 0b1..Clear all bits in EEI

◆ DMA_CEEI_CAEE [4/5]

#define DMA_CEEI_CAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

CAEE - Clear All Enable Error Interrupts 0b0..Clear only the EEI bit specified in the CEEI field 0b1..Clear all bits in EEI

◆ DMA_CEEI_CAEE [5/5]

#define DMA_CEEI_CAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)

CAEE - Clear All Enable Error Interrupts 0b0..Clear only the EEI bit specified in the CEEI field 0b1..Clear all bits in EEI

◆ DMA_CEEI_NOP [1/5]

#define DMA_CEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CEEI_NOP [2/5]

#define DMA_CEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CEEI_NOP [3/5]

#define DMA_CEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CEEI_NOP [4/5]

#define DMA_CEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CEEI_NOP [5/5]

#define DMA_CEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CERQ_CAER [1/5]

#define DMA_CERQ_CAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

CAER - Clear All Enable Requests 0b0..Clear only the ERQ bit specified in the CERQ field 0b1..Clear all bits in ERQ

◆ DMA_CERQ_CAER [2/5]

#define DMA_CERQ_CAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

CAER - Clear All Enable Requests 0b0..Clear only the ERQ bit specified in the CERQ field 0b1..Clear all bits in ERQ

◆ DMA_CERQ_CAER [3/5]

#define DMA_CERQ_CAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

CAER - Clear All Enable Requests 0b0..Clear only the ERQ bit specified in the CERQ field 0b1..Clear all bits in ERQ

◆ DMA_CERQ_CAER [4/5]

#define DMA_CERQ_CAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

CAER - Clear All Enable Requests 0b0..Clear only the ERQ bit specified in the CERQ field 0b1..Clear all bits in ERQ

◆ DMA_CERQ_CAER [5/5]

#define DMA_CERQ_CAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)

CAER - Clear All Enable Requests 0b0..Clear only the ERQ bit specified in the CERQ field 0b1..Clear all bits in ERQ

◆ DMA_CERQ_NOP [1/5]

#define DMA_CERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CERQ_NOP [2/5]

#define DMA_CERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CERQ_NOP [3/5]

#define DMA_CERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CERQ_NOP [4/5]

#define DMA_CERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CERQ_NOP [5/5]

#define DMA_CERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CERR_CAEI [1/5]

#define DMA_CERR_CAEI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

CAEI - Clear All Error Indicators 0b0..Clear only the ERR bit specified in the CERR field 0b1..Clear all bits in ERR

◆ DMA_CERR_CAEI [2/5]

#define DMA_CERR_CAEI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

CAEI - Clear All Error Indicators 0b0..Clear only the ERR bit specified in the CERR field 0b1..Clear all bits in ERR

◆ DMA_CERR_CAEI [3/5]

#define DMA_CERR_CAEI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

CAEI - Clear All Error Indicators 0b0..Clear only the ERR bit specified in the CERR field 0b1..Clear all bits in ERR

◆ DMA_CERR_CAEI [4/5]

#define DMA_CERR_CAEI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

CAEI - Clear All Error Indicators 0b0..Clear only the ERR bit specified in the CERR field 0b1..Clear all bits in ERR

◆ DMA_CERR_CAEI [5/5]

#define DMA_CERR_CAEI ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)

CAEI - Clear All Error Indicators 0b0..Clear only the ERR bit specified in the CERR field 0b1..Clear all bits in ERR

◆ DMA_CERR_NOP [1/5]

#define DMA_CERR_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CERR_NOP [2/5]

#define DMA_CERR_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CERR_NOP [3/5]

#define DMA_CERR_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CERR_NOP [4/5]

#define DMA_CERR_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CERR_NOP [5/5]

#define DMA_CERR_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CHN_IRQS

#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }

Interrupt vectors for the DMA peripheral type

◆ DMA_CINT_CAIR [1/5]

#define DMA_CINT_CAIR ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

CAIR - Clear All Interrupt Requests 0b0..Clear only the INT bit specified in the CINT field 0b1..Clear all bits in INT

◆ DMA_CINT_CAIR [2/5]

#define DMA_CINT_CAIR ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

CAIR - Clear All Interrupt Requests 0b0..Clear only the INT bit specified in the CINT field 0b1..Clear all bits in INT

◆ DMA_CINT_CAIR [3/5]

#define DMA_CINT_CAIR ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

CAIR - Clear All Interrupt Requests 0b0..Clear only the INT bit specified in the CINT field 0b1..Clear all bits in INT

◆ DMA_CINT_CAIR [4/5]

#define DMA_CINT_CAIR ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

CAIR - Clear All Interrupt Requests 0b0..Clear only the INT bit specified in the CINT field 0b1..Clear all bits in INT

◆ DMA_CINT_CAIR [5/5]

#define DMA_CINT_CAIR ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)

CAIR - Clear All Interrupt Requests 0b0..Clear only the INT bit specified in the CINT field 0b1..Clear all bits in INT

◆ DMA_CINT_NOP [1/5]

#define DMA_CINT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CINT_NOP [2/5]

#define DMA_CINT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CINT_NOP [3/5]

#define DMA_CINT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CINT_NOP [4/5]

#define DMA_CINT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CINT_NOP [5/5]

#define DMA_CINT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_CITER_ELINKNO_ELINK [1/5]

#define DMA_CITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CITER_ELINKNO_ELINK [2/5]

#define DMA_CITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CITER_ELINKNO_ELINK [3/5]

#define DMA_CITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CITER_ELINKNO_ELINK [4/5]

#define DMA_CITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CITER_ELINKNO_ELINK [5/5]

#define DMA_CITER_ELINKNO_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CITER_ELINKYES_ELINK [1/5]

#define DMA_CITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CITER_ELINKYES_ELINK [2/5]

#define DMA_CITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CITER_ELINKYES_ELINK [3/5]

#define DMA_CITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CITER_ELINKYES_ELINK [4/5]

#define DMA_CITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CITER_ELINKYES_ELINK [5/5]

#define DMA_CITER_ELINKYES_ELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)

ELINK - Enable channel-to-channel linking on minor-loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

◆ DMA_CR_CLM [1/5]

#define DMA_CR_CLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

CLM - Continuous Link Mode 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.

◆ DMA_CR_CLM [2/5]

#define DMA_CR_CLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

CLM - Continuous Link Mode 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.

◆ DMA_CR_CLM [3/5]

#define DMA_CR_CLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

CLM - Continuous Link Mode 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.

◆ DMA_CR_CLM [4/5]

#define DMA_CR_CLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

CLM - Continuous Link Mode 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.

◆ DMA_CR_CLM [5/5]

#define DMA_CR_CLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)

CLM - Continuous Link Mode 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.

◆ DMA_CR_CX [1/5]

#define DMA_CR_CX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

CX - Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.

◆ DMA_CR_CX [2/5]

#define DMA_CR_CX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

CX - Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.

◆ DMA_CR_CX [3/5]

#define DMA_CR_CX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

CX - Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.

◆ DMA_CR_CX [4/5]

#define DMA_CR_CX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

CX - Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.

◆ DMA_CR_CX [5/5]

#define DMA_CR_CX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)

CX - Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.

◆ DMA_CR_ECX [1/5]

#define DMA_CR_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

ECX - Error Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.

◆ DMA_CR_ECX [2/5]

#define DMA_CR_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

ECX - Error Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.

◆ DMA_CR_ECX [3/5]

#define DMA_CR_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

ECX - Error Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.

◆ DMA_CR_ECX [4/5]

#define DMA_CR_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

ECX - Error Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.

◆ DMA_CR_ECX [5/5]

#define DMA_CR_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)

ECX - Error Cancel Transfer 0b0..Normal operation 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.

◆ DMA_CR_EDBG [1/5]

#define DMA_CR_EDBG ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

EDBG - Enable Debug 0b0..When in debug mode, the DMA continues to operate. 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.

◆ DMA_CR_EDBG [2/5]

#define DMA_CR_EDBG ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

EDBG - Enable Debug 0b0..When in debug mode, the DMA continues to operate. 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.

◆ DMA_CR_EDBG [3/5]

#define DMA_CR_EDBG ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

EDBG - Enable Debug 0b0..When in debug mode, the DMA continues to operate. 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.

◆ DMA_CR_EDBG [4/5]

#define DMA_CR_EDBG ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

EDBG - Enable Debug 0b0..When in debug mode, the DMA continues to operate. 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.

◆ DMA_CR_EDBG [5/5]

#define DMA_CR_EDBG ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)

EDBG - Enable Debug 0b0..When in debug mode, the DMA continues to operate. 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.

◆ DMA_CR_EMLM [1/5]

#define DMA_CR_EMLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

EMLM - Enable Minor Loop Mapping 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.

◆ DMA_CR_EMLM [2/5]

#define DMA_CR_EMLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

EMLM - Enable Minor Loop Mapping 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.

◆ DMA_CR_EMLM [3/5]

#define DMA_CR_EMLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

EMLM - Enable Minor Loop Mapping 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.

◆ DMA_CR_EMLM [4/5]

#define DMA_CR_EMLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

EMLM - Enable Minor Loop Mapping 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.

◆ DMA_CR_EMLM [5/5]

#define DMA_CR_EMLM ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)

EMLM - Enable Minor Loop Mapping 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.

◆ DMA_CR_ERCA [1/5]

#define DMA_CR_ERCA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration is used for channel selection . 0b1..Round robin arbitration is used for channel selection .

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration is used for channel selection within each group. 0b1..Round robin arbitration is used for channel selection within each group.

◆ DMA_CR_ERCA [2/5]

#define DMA_CR_ERCA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration is used for channel selection . 0b1..Round robin arbitration is used for channel selection .

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration is used for channel selection within each group. 0b1..Round robin arbitration is used for channel selection within each group.

◆ DMA_CR_ERCA [3/5]

#define DMA_CR_ERCA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration is used for channel selection within each group. 0b1..Round robin arbitration is used for channel selection within each group.

◆ DMA_CR_ERCA [4/5]

#define DMA_CR_ERCA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration is used for channel selection within each group. 0b1..Round robin arbitration is used for channel selection within each group.

◆ DMA_CR_ERCA [5/5]

#define DMA_CR_ERCA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)

ERCA - Enable Round Robin Channel Arbitration 0b0..Fixed priority arbitration is used for channel selection within each group. 0b1..Round robin arbitration is used for channel selection within each group.

◆ DMA_CR_ERGA [1/3]

#define DMA_CR_ERGA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

ERGA - Enable Round Robin Group Arbitration 0b0..Fixed priority arbitration is used for selection among the groups. 0b1..Round robin arbitration is used for selection among the groups.

◆ DMA_CR_ERGA [2/3]

#define DMA_CR_ERGA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

ERGA - Enable Round Robin Group Arbitration 0b0..Fixed priority arbitration is used for selection among the groups. 0b1..Round robin arbitration is used for selection among the groups.

◆ DMA_CR_ERGA [3/3]

#define DMA_CR_ERGA ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)

ERGA - Enable Round Robin Group Arbitration 0b0..Fixed priority arbitration is used for selection among the groups. 0b1..Round robin arbitration is used for selection among the groups.

◆ DMA_CR_HALT [1/5]

#define DMA_CR_HALT ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

HALT - Halt DMA Operations 0b0..Normal operation 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.

◆ DMA_CR_HALT [2/5]

#define DMA_CR_HALT ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

HALT - Halt DMA Operations 0b0..Normal operation 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.

◆ DMA_CR_HALT [3/5]

#define DMA_CR_HALT ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

HALT - Halt DMA Operations 0b0..Normal operation 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.

◆ DMA_CR_HALT [4/5]

#define DMA_CR_HALT ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

HALT - Halt DMA Operations 0b0..Normal operation 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.

◆ DMA_CR_HALT [5/5]

#define DMA_CR_HALT ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)

HALT - Halt DMA Operations 0b0..Normal operation 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.

◆ DMA_CR_HOE [1/5]

#define DMA_CR_HOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

HOE - Halt On Error 0b0..Normal operation 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

◆ DMA_CR_HOE [2/5]

#define DMA_CR_HOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

HOE - Halt On Error 0b0..Normal operation 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

◆ DMA_CR_HOE [3/5]

#define DMA_CR_HOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

HOE - Halt On Error 0b0..Normal operation 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

◆ DMA_CR_HOE [4/5]

#define DMA_CR_HOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

HOE - Halt On Error 0b0..Normal operation 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

◆ DMA_CR_HOE [5/5]

#define DMA_CR_HOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)

HOE - Halt On Error 0b0..Normal operation 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.

◆ DMA_CSR_BWC [1/6]

#define DMA_CSR_BWC ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each r/w 0b11..eDMA engine stalls for 8 cycles after each r/w

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

BWC - Bandwidth Control 0b00..No eDMA engine stalls. 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

◆ DMA_CSR_BWC [2/6]

#define DMA_CSR_BWC ( x ) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each r/w 0b11..eDMA engine stalls for 8 cycles after each r/w

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

BWC - Bandwidth Control 0b00..No eDMA engine stalls. 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

◆ DMA_CSR_BWC [3/6]

#define DMA_CSR_BWC ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each r/w 0b11..eDMA engine stalls for 8 cycles after each r/w

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

BWC - Bandwidth Control 0b00..No eDMA engine stalls. 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

◆ DMA_CSR_BWC [4/6]

#define DMA_CSR_BWC ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

BWC - Bandwidth Control 0b00..No eDMA engine stalls. 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

◆ DMA_CSR_BWC [5/6]

#define DMA_CSR_BWC ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

BWC - Bandwidth Control 0b00..No eDMA engine stalls. 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

◆ DMA_CSR_BWC [6/6]

#define DMA_CSR_BWC ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)

BWC - Bandwidth Control 0b00..No eDMA engine stalls. 0b01..Reserved 0b10..eDMA engine stalls for 4 cycles after each R/W. 0b11..eDMA engine stalls for 8 cycles after each R/W.

◆ DMA_CSR_DREQ [1/5]

#define DMA_CSR_DREQ ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

DREQ - Disable Request 0b0..The channel's ERQ bit is not affected 0b1..The channel's ERQ bit is cleared when the major loop is complete

DREQ - Disable Request 0b0..The channel's ERQ bit is not affected. 0b1..The channel's ERQ bit is cleared when the major loop is complete.

◆ DMA_CSR_DREQ [2/5]

#define DMA_CSR_DREQ ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

DREQ - Disable Request 0b0..The channel's ERQ bit is not affected 0b1..The channel's ERQ bit is cleared when the major loop is complete

DREQ - Disable Request 0b0..The channel's ERQ bit is not affected. 0b1..The channel's ERQ bit is cleared when the major loop is complete.

◆ DMA_CSR_DREQ [3/5]

#define DMA_CSR_DREQ ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

DREQ - Disable Request 0b0..The channel's ERQ bit is not affected. 0b1..The channel's ERQ bit is cleared when the major loop is complete.

◆ DMA_CSR_DREQ [4/5]

#define DMA_CSR_DREQ ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

DREQ - Disable Request 0b0..The channel's ERQ bit is not affected. 0b1..The channel's ERQ bit is cleared when the major loop is complete.

◆ DMA_CSR_DREQ [5/5]

#define DMA_CSR_DREQ ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)

DREQ - Disable Request 0b0..The channel's ERQ bit is not affected. 0b1..The channel's ERQ bit is cleared when the major loop is complete.

◆ DMA_CSR_ESG [1/5]

#define DMA_CSR_ESG ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

ESG - Enable Scatter/Gather Processing 0b0..The current channel's TCD is normal format. 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.

◆ DMA_CSR_ESG [2/5]

#define DMA_CSR_ESG ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

ESG - Enable Scatter/Gather Processing 0b0..The current channel's TCD is normal format. 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.

◆ DMA_CSR_ESG [3/5]

#define DMA_CSR_ESG ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

ESG - Enable Scatter/Gather Processing 0b0..The current channel's TCD is normal format. 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.

◆ DMA_CSR_ESG [4/5]

#define DMA_CSR_ESG ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

ESG - Enable Scatter/Gather Processing 0b0..The current channel's TCD is normal format. 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.

◆ DMA_CSR_ESG [5/5]

#define DMA_CSR_ESG ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)

ESG - Enable Scatter/Gather Processing 0b0..The current channel's TCD is normal format. 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.

◆ DMA_CSR_INTHALF [1/5]

#define DMA_CSR_INTHALF ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

INTHALF - Enable an interrupt when major counter is half complete. 0b0..The half-point interrupt is disabled 0b1..The half-point interrupt is enabled

INTHALF - Enable an interrupt when major counter is half complete. 0b0..The half-point interrupt is disabled. 0b1..The half-point interrupt is enabled.

◆ DMA_CSR_INTHALF [2/5]

#define DMA_CSR_INTHALF ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

INTHALF - Enable an interrupt when major counter is half complete. 0b0..The half-point interrupt is disabled 0b1..The half-point interrupt is enabled

INTHALF - Enable an interrupt when major counter is half complete. 0b0..The half-point interrupt is disabled. 0b1..The half-point interrupt is enabled.

◆ DMA_CSR_INTHALF [3/5]

#define DMA_CSR_INTHALF ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

INTHALF - Enable an interrupt when major counter is half complete. 0b0..The half-point interrupt is disabled. 0b1..The half-point interrupt is enabled.

◆ DMA_CSR_INTHALF [4/5]

#define DMA_CSR_INTHALF ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

INTHALF - Enable an interrupt when major counter is half complete. 0b0..The half-point interrupt is disabled. 0b1..The half-point interrupt is enabled.

◆ DMA_CSR_INTHALF [5/5]

#define DMA_CSR_INTHALF ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

INTHALF - Enable an interrupt when major counter is half complete. 0b0..The half-point interrupt is disabled. 0b1..The half-point interrupt is enabled.

◆ DMA_CSR_INTMAJOR [1/5]

#define DMA_CSR_INTMAJOR ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

INTMAJOR - Enable an interrupt when major iteration count completes 0b0..The end-of-major loop interrupt is disabled 0b1..The end-of-major loop interrupt is enabled

INTMAJOR - Enable an interrupt when major iteration count completes. 0b0..The end-of-major loop interrupt is disabled. 0b1..The end-of-major loop interrupt is enabled.

◆ DMA_CSR_INTMAJOR [2/5]

#define DMA_CSR_INTMAJOR ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

INTMAJOR - Enable an interrupt when major iteration count completes 0b0..The end-of-major loop interrupt is disabled 0b1..The end-of-major loop interrupt is enabled

INTMAJOR - Enable an interrupt when major iteration count completes. 0b0..The end-of-major loop interrupt is disabled. 0b1..The end-of-major loop interrupt is enabled.

◆ DMA_CSR_INTMAJOR [3/5]

#define DMA_CSR_INTMAJOR ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

INTMAJOR - Enable an interrupt when major iteration count completes. 0b0..The end-of-major loop interrupt is disabled. 0b1..The end-of-major loop interrupt is enabled.

◆ DMA_CSR_INTMAJOR [4/5]

#define DMA_CSR_INTMAJOR ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

INTMAJOR - Enable an interrupt when major iteration count completes. 0b0..The end-of-major loop interrupt is disabled. 0b1..The end-of-major loop interrupt is enabled.

◆ DMA_CSR_INTMAJOR [5/5]

#define DMA_CSR_INTMAJOR ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)

INTMAJOR - Enable an interrupt when major iteration count completes. 0b0..The end-of-major loop interrupt is disabled. 0b1..The end-of-major loop interrupt is enabled.

◆ DMA_CSR_MAJORELINK [1/5]

#define DMA_CSR_MAJORELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..The channel-to-channel linking is disabled. 0b1..The channel-to-channel linking is enabled.

◆ DMA_CSR_MAJORELINK [2/5]

#define DMA_CSR_MAJORELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..The channel-to-channel linking is disabled 0b1..The channel-to-channel linking is enabled

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..The channel-to-channel linking is disabled. 0b1..The channel-to-channel linking is enabled.

◆ DMA_CSR_MAJORELINK [3/5]

#define DMA_CSR_MAJORELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..The channel-to-channel linking is disabled. 0b1..The channel-to-channel linking is enabled.

◆ DMA_CSR_MAJORELINK [4/5]

#define DMA_CSR_MAJORELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..The channel-to-channel linking is disabled. 0b1..The channel-to-channel linking is enabled.

◆ DMA_CSR_MAJORELINK [5/5]

#define DMA_CSR_MAJORELINK ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)

MAJORELINK - Enable channel-to-channel linking on major loop complete 0b0..The channel-to-channel linking is disabled. 0b1..The channel-to-channel linking is enabled.

◆ DMA_CSR_START [1/5]

#define DMA_CSR_START ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

START - Channel Start 0b0..The channel is not explicitly started 0b1..The channel is explicitly started via a software initiated service request

START - Channel Start 0b0..The channel is not explicitly started. 0b1..The channel is explicitly started via a software initiated service request.

◆ DMA_CSR_START [2/5]

#define DMA_CSR_START ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

START - Channel Start 0b0..The channel is not explicitly started 0b1..The channel is explicitly started via a software initiated service request

START - Channel Start 0b0..The channel is not explicitly started. 0b1..The channel is explicitly started via a software initiated service request.

◆ DMA_CSR_START [3/5]

#define DMA_CSR_START ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

START - Channel Start 0b0..The channel is not explicitly started. 0b1..The channel is explicitly started via a software initiated service request.

◆ DMA_CSR_START [4/5]

#define DMA_CSR_START ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

START - Channel Start 0b0..The channel is not explicitly started. 0b1..The channel is explicitly started via a software initiated service request.

◆ DMA_CSR_START [5/5]

#define DMA_CSR_START ( x ) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)

START - Channel Start 0b0..The channel is not explicitly started. 0b1..The channel is explicitly started via a software initiated service request.

◆ DMA_DCHPRI0_DPA [1/5]

#define DMA_DCHPRI0_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI0_DPA [2/5]

#define DMA_DCHPRI0_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI0_DPA [3/5]

#define DMA_DCHPRI0_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI0_DPA [4/5]

#define DMA_DCHPRI0_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI0_DPA [5/5]

#define DMA_DCHPRI0_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI0_ECP [1/5]

#define DMA_DCHPRI0_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI0_ECP [2/5]

#define DMA_DCHPRI0_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI0_ECP [3/5]

#define DMA_DCHPRI0_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI0_ECP [4/5]

#define DMA_DCHPRI0_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI0_ECP [5/5]

#define DMA_DCHPRI0_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI10_DPA [1/5]

#define DMA_DCHPRI10_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI10_DPA [2/5]

#define DMA_DCHPRI10_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI10_DPA [3/5]

#define DMA_DCHPRI10_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI10_DPA [4/5]

#define DMA_DCHPRI10_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI10_DPA [5/5]

#define DMA_DCHPRI10_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI10_ECP [1/5]

#define DMA_DCHPRI10_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI10_ECP [2/5]

#define DMA_DCHPRI10_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI10_ECP [3/5]

#define DMA_DCHPRI10_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI10_ECP [4/5]

#define DMA_DCHPRI10_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI10_ECP [5/5]

#define DMA_DCHPRI10_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI11_DPA [1/5]

#define DMA_DCHPRI11_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI11_DPA [2/5]

#define DMA_DCHPRI11_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI11_DPA [3/5]

#define DMA_DCHPRI11_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI11_DPA [4/5]

#define DMA_DCHPRI11_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI11_DPA [5/5]

#define DMA_DCHPRI11_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI11_ECP [1/5]

#define DMA_DCHPRI11_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI11_ECP [2/5]

#define DMA_DCHPRI11_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI11_ECP [3/5]

#define DMA_DCHPRI11_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI11_ECP [4/5]

#define DMA_DCHPRI11_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI11_ECP [5/5]

#define DMA_DCHPRI11_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI12_DPA [1/5]

#define DMA_DCHPRI12_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI12_DPA [2/5]

#define DMA_DCHPRI12_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI12_DPA [3/5]

#define DMA_DCHPRI12_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI12_DPA [4/5]

#define DMA_DCHPRI12_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI12_DPA [5/5]

#define DMA_DCHPRI12_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI12_ECP [1/5]

#define DMA_DCHPRI12_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI12_ECP [2/5]

#define DMA_DCHPRI12_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI12_ECP [3/5]

#define DMA_DCHPRI12_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI12_ECP [4/5]

#define DMA_DCHPRI12_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI12_ECP [5/5]

#define DMA_DCHPRI12_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI13_DPA [1/5]

#define DMA_DCHPRI13_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI13_DPA [2/5]

#define DMA_DCHPRI13_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI13_DPA [3/5]

#define DMA_DCHPRI13_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI13_DPA [4/5]

#define DMA_DCHPRI13_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI13_DPA [5/5]

#define DMA_DCHPRI13_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI13_ECP [1/5]

#define DMA_DCHPRI13_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI13_ECP [2/5]

#define DMA_DCHPRI13_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI13_ECP [3/5]

#define DMA_DCHPRI13_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI13_ECP [4/5]

#define DMA_DCHPRI13_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI13_ECP [5/5]

#define DMA_DCHPRI13_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI14_DPA [1/5]

#define DMA_DCHPRI14_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI14_DPA [2/5]

#define DMA_DCHPRI14_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI14_DPA [3/5]

#define DMA_DCHPRI14_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI14_DPA [4/5]

#define DMA_DCHPRI14_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI14_DPA [5/5]

#define DMA_DCHPRI14_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI14_ECP [1/5]

#define DMA_DCHPRI14_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI14_ECP [2/5]

#define DMA_DCHPRI14_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI14_ECP [3/5]

#define DMA_DCHPRI14_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI14_ECP [4/5]

#define DMA_DCHPRI14_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI14_ECP [5/5]

#define DMA_DCHPRI14_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI15_DPA [1/5]

#define DMA_DCHPRI15_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI15_DPA [2/5]

#define DMA_DCHPRI15_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI15_DPA [3/5]

#define DMA_DCHPRI15_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI15_DPA [4/5]

#define DMA_DCHPRI15_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI15_DPA [5/5]

#define DMA_DCHPRI15_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI15_ECP [1/5]

#define DMA_DCHPRI15_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI15_ECP [2/5]

#define DMA_DCHPRI15_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI15_ECP [3/5]

#define DMA_DCHPRI15_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI15_ECP [4/5]

#define DMA_DCHPRI15_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI15_ECP [5/5]

#define DMA_DCHPRI15_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI16_DPA [1/3]

#define DMA_DCHPRI16_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI16_DPA [2/3]

#define DMA_DCHPRI16_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI16_DPA [3/3]

#define DMA_DCHPRI16_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI16_ECP [1/3]

#define DMA_DCHPRI16_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI16_ECP [2/3]

#define DMA_DCHPRI16_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI16_ECP [3/3]

#define DMA_DCHPRI16_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI17_DPA [1/3]

#define DMA_DCHPRI17_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI17_DPA [2/3]

#define DMA_DCHPRI17_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI17_DPA [3/3]

#define DMA_DCHPRI17_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI17_ECP [1/3]

#define DMA_DCHPRI17_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI17_ECP [2/3]

#define DMA_DCHPRI17_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI17_ECP [3/3]

#define DMA_DCHPRI17_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI18_DPA [1/3]

#define DMA_DCHPRI18_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI18_DPA [2/3]

#define DMA_DCHPRI18_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI18_DPA [3/3]

#define DMA_DCHPRI18_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI18_ECP [1/3]

#define DMA_DCHPRI18_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI18_ECP [2/3]

#define DMA_DCHPRI18_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI18_ECP [3/3]

#define DMA_DCHPRI18_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI19_DPA [1/3]

#define DMA_DCHPRI19_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI19_DPA [2/3]

#define DMA_DCHPRI19_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI19_DPA [3/3]

#define DMA_DCHPRI19_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI19_ECP [1/3]

#define DMA_DCHPRI19_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI19_ECP [2/3]

#define DMA_DCHPRI19_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI19_ECP [3/3]

#define DMA_DCHPRI19_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI1_DPA [1/5]

#define DMA_DCHPRI1_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI1_DPA [2/5]

#define DMA_DCHPRI1_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI1_DPA [3/5]

#define DMA_DCHPRI1_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI1_DPA [4/5]

#define DMA_DCHPRI1_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI1_DPA [5/5]

#define DMA_DCHPRI1_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI1_ECP [1/5]

#define DMA_DCHPRI1_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI1_ECP [2/5]

#define DMA_DCHPRI1_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI1_ECP [3/5]

#define DMA_DCHPRI1_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI1_ECP [4/5]

#define DMA_DCHPRI1_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI1_ECP [5/5]

#define DMA_DCHPRI1_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI20_DPA [1/3]

#define DMA_DCHPRI20_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI20_DPA [2/3]

#define DMA_DCHPRI20_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI20_DPA [3/3]

#define DMA_DCHPRI20_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI20_ECP [1/3]

#define DMA_DCHPRI20_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI20_ECP [2/3]

#define DMA_DCHPRI20_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI20_ECP [3/3]

#define DMA_DCHPRI20_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI21_DPA [1/3]

#define DMA_DCHPRI21_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI21_DPA [2/3]

#define DMA_DCHPRI21_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI21_DPA [3/3]

#define DMA_DCHPRI21_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI21_ECP [1/3]

#define DMA_DCHPRI21_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI21_ECP [2/3]

#define DMA_DCHPRI21_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI21_ECP [3/3]

#define DMA_DCHPRI21_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI22_DPA [1/3]

#define DMA_DCHPRI22_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI22_DPA [2/3]

#define DMA_DCHPRI22_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI22_DPA [3/3]

#define DMA_DCHPRI22_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI22_ECP [1/3]

#define DMA_DCHPRI22_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI22_ECP [2/3]

#define DMA_DCHPRI22_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI22_ECP [3/3]

#define DMA_DCHPRI22_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI23_DPA [1/3]

#define DMA_DCHPRI23_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI23_DPA [2/3]

#define DMA_DCHPRI23_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI23_DPA [3/3]

#define DMA_DCHPRI23_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI23_ECP [1/3]

#define DMA_DCHPRI23_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI23_ECP [2/3]

#define DMA_DCHPRI23_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI23_ECP [3/3]

#define DMA_DCHPRI23_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI24_DPA [1/3]

#define DMA_DCHPRI24_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI24_DPA [2/3]

#define DMA_DCHPRI24_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI24_DPA [3/3]

#define DMA_DCHPRI24_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI24_ECP [1/3]

#define DMA_DCHPRI24_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI24_ECP [2/3]

#define DMA_DCHPRI24_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI24_ECP [3/3]

#define DMA_DCHPRI24_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI25_DPA [1/3]

#define DMA_DCHPRI25_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI25_DPA [2/3]

#define DMA_DCHPRI25_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI25_DPA [3/3]

#define DMA_DCHPRI25_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI25_ECP [1/3]

#define DMA_DCHPRI25_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI25_ECP [2/3]

#define DMA_DCHPRI25_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI25_ECP [3/3]

#define DMA_DCHPRI25_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI26_DPA [1/3]

#define DMA_DCHPRI26_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI26_DPA [2/3]

#define DMA_DCHPRI26_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI26_DPA [3/3]

#define DMA_DCHPRI26_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI26_ECP [1/3]

#define DMA_DCHPRI26_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI26_ECP [2/3]

#define DMA_DCHPRI26_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI26_ECP [3/3]

#define DMA_DCHPRI26_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI27_DPA [1/3]

#define DMA_DCHPRI27_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI27_DPA [2/3]

#define DMA_DCHPRI27_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI27_DPA [3/3]

#define DMA_DCHPRI27_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI27_ECP [1/3]

#define DMA_DCHPRI27_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI27_ECP [2/3]

#define DMA_DCHPRI27_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI27_ECP [3/3]

#define DMA_DCHPRI27_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI28_DPA [1/3]

#define DMA_DCHPRI28_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI28_DPA [2/3]

#define DMA_DCHPRI28_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI28_DPA [3/3]

#define DMA_DCHPRI28_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI28_ECP [1/3]

#define DMA_DCHPRI28_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI28_ECP [2/3]

#define DMA_DCHPRI28_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI28_ECP [3/3]

#define DMA_DCHPRI28_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI29_DPA [1/3]

#define DMA_DCHPRI29_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI29_DPA [2/3]

#define DMA_DCHPRI29_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI29_DPA [3/3]

#define DMA_DCHPRI29_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI29_ECP [1/3]

#define DMA_DCHPRI29_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI29_ECP [2/3]

#define DMA_DCHPRI29_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI29_ECP [3/3]

#define DMA_DCHPRI29_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI2_DPA [1/5]

#define DMA_DCHPRI2_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI2_DPA [2/5]

#define DMA_DCHPRI2_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI2_DPA [3/5]

#define DMA_DCHPRI2_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI2_DPA [4/5]

#define DMA_DCHPRI2_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI2_DPA [5/5]

#define DMA_DCHPRI2_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI2_ECP [1/5]

#define DMA_DCHPRI2_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI2_ECP [2/5]

#define DMA_DCHPRI2_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI2_ECP [3/5]

#define DMA_DCHPRI2_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI2_ECP [4/5]

#define DMA_DCHPRI2_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI2_ECP [5/5]

#define DMA_DCHPRI2_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI30_DPA [1/3]

#define DMA_DCHPRI30_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI30_DPA [2/3]

#define DMA_DCHPRI30_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI30_DPA [3/3]

#define DMA_DCHPRI30_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI30_ECP [1/3]

#define DMA_DCHPRI30_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI30_ECP [2/3]

#define DMA_DCHPRI30_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI30_ECP [3/3]

#define DMA_DCHPRI30_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI31_DPA [1/3]

#define DMA_DCHPRI31_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI31_DPA [2/3]

#define DMA_DCHPRI31_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI31_DPA [3/3]

#define DMA_DCHPRI31_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI31_ECP [1/3]

#define DMA_DCHPRI31_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI31_ECP [2/3]

#define DMA_DCHPRI31_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI31_ECP [3/3]

#define DMA_DCHPRI31_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI3_DPA [1/5]

#define DMA_DCHPRI3_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI3_DPA [2/5]

#define DMA_DCHPRI3_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI3_DPA [3/5]

#define DMA_DCHPRI3_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI3_DPA [4/5]

#define DMA_DCHPRI3_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI3_DPA [5/5]

#define DMA_DCHPRI3_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI3_ECP [1/5]

#define DMA_DCHPRI3_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI3_ECP [2/5]

#define DMA_DCHPRI3_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI3_ECP [3/5]

#define DMA_DCHPRI3_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI3_ECP [4/5]

#define DMA_DCHPRI3_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI3_ECP [5/5]

#define DMA_DCHPRI3_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI4_DPA [1/5]

#define DMA_DCHPRI4_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI4_DPA [2/5]

#define DMA_DCHPRI4_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI4_DPA [3/5]

#define DMA_DCHPRI4_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI4_DPA [4/5]

#define DMA_DCHPRI4_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI4_DPA [5/5]

#define DMA_DCHPRI4_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI4_ECP [1/5]

#define DMA_DCHPRI4_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI4_ECP [2/5]

#define DMA_DCHPRI4_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI4_ECP [3/5]

#define DMA_DCHPRI4_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI4_ECP [4/5]

#define DMA_DCHPRI4_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI4_ECP [5/5]

#define DMA_DCHPRI4_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI5_DPA [1/5]

#define DMA_DCHPRI5_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI5_DPA [2/5]

#define DMA_DCHPRI5_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI5_DPA [3/5]

#define DMA_DCHPRI5_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI5_DPA [4/5]

#define DMA_DCHPRI5_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI5_DPA [5/5]

#define DMA_DCHPRI5_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI5_ECP [1/5]

#define DMA_DCHPRI5_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI5_ECP [2/5]

#define DMA_DCHPRI5_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI5_ECP [3/5]

#define DMA_DCHPRI5_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI5_ECP [4/5]

#define DMA_DCHPRI5_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI5_ECP [5/5]

#define DMA_DCHPRI5_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI6_DPA [1/5]

#define DMA_DCHPRI6_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI6_DPA [2/5]

#define DMA_DCHPRI6_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI6_DPA [3/5]

#define DMA_DCHPRI6_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI6_DPA [4/5]

#define DMA_DCHPRI6_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI6_DPA [5/5]

#define DMA_DCHPRI6_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI6_ECP [1/5]

#define DMA_DCHPRI6_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI6_ECP [2/5]

#define DMA_DCHPRI6_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI6_ECP [3/5]

#define DMA_DCHPRI6_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI6_ECP [4/5]

#define DMA_DCHPRI6_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI6_ECP [5/5]

#define DMA_DCHPRI6_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI7_DPA [1/5]

#define DMA_DCHPRI7_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI7_DPA [2/5]

#define DMA_DCHPRI7_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI7_DPA [3/5]

#define DMA_DCHPRI7_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI7_DPA [4/5]

#define DMA_DCHPRI7_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI7_DPA [5/5]

#define DMA_DCHPRI7_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI7_ECP [1/5]

#define DMA_DCHPRI7_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI7_ECP [2/5]

#define DMA_DCHPRI7_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI7_ECP [3/5]

#define DMA_DCHPRI7_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI7_ECP [4/5]

#define DMA_DCHPRI7_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI7_ECP [5/5]

#define DMA_DCHPRI7_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI8_DPA [1/5]

#define DMA_DCHPRI8_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI8_DPA [2/5]

#define DMA_DCHPRI8_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI8_DPA [3/5]

#define DMA_DCHPRI8_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI8_DPA [4/5]

#define DMA_DCHPRI8_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI8_DPA [5/5]

#define DMA_DCHPRI8_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI8_ECP [1/5]

#define DMA_DCHPRI8_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI8_ECP [2/5]

#define DMA_DCHPRI8_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI8_ECP [3/5]

#define DMA_DCHPRI8_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI8_ECP [4/5]

#define DMA_DCHPRI8_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI8_ECP [5/5]

#define DMA_DCHPRI8_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI9_DPA [1/5]

#define DMA_DCHPRI9_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI9_DPA [2/5]

#define DMA_DCHPRI9_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

DPA - Disable Preempt Ability 0b0..Channel n can suspend a lower priority channel 0b1..Channel n cannot suspend any channel, regardless of channel priority

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI9_DPA [3/5]

#define DMA_DCHPRI9_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI9_DPA [4/5]

#define DMA_DCHPRI9_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI9_DPA [5/5]

#define DMA_DCHPRI9_DPA ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)

DPA - Disable Preempt Ability. 0b0..Channel n can suspend a lower priority channel. 0b1..Channel n cannot suspend any channel, regardless of channel priority.

◆ DMA_DCHPRI9_ECP [1/5]

#define DMA_DCHPRI9_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI9_ECP [2/5]

#define DMA_DCHPRI9_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

ECP - Enable Channel Preemption 0b0..Channel n cannot be suspended by a higher priority channel's service request 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI9_ECP [3/5]

#define DMA_DCHPRI9_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI9_ECP [4/5]

#define DMA_DCHPRI9_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_DCHPRI9_ECP [5/5]

#define DMA_DCHPRI9_ECP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)

ECP - Enable Channel Preemption. 0b0..Channel n cannot be suspended by a higher priority channel's service request. 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.

◆ DMA_EARS_EDREQ_0 [1/3]

#define DMA_EARS_EDREQ_0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. 0b0..Disable asynchronous DMA request for channel 0. 0b1..Enable asynchronous DMA request for channel 0.

◆ DMA_EARS_EDREQ_0 [2/3]

#define DMA_EARS_EDREQ_0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. 0b0..Disable asynchronous DMA request for channel 0. 0b1..Enable asynchronous DMA request for channel 0.

◆ DMA_EARS_EDREQ_0 [3/3]

#define DMA_EARS_EDREQ_0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)

EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. 0b0..Disable asynchronous DMA request for channel 0. 0b1..Enable asynchronous DMA request for channel 0.

◆ DMA_EARS_EDREQ_1 [1/3]

#define DMA_EARS_EDREQ_1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. 0b0..Disable asynchronous DMA request for channel 1 0b1..Enable asynchronous DMA request for channel 1.

◆ DMA_EARS_EDREQ_1 [2/3]

#define DMA_EARS_EDREQ_1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. 0b0..Disable asynchronous DMA request for channel 1 0b1..Enable asynchronous DMA request for channel 1.

◆ DMA_EARS_EDREQ_1 [3/3]

#define DMA_EARS_EDREQ_1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)

EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. 0b0..Disable asynchronous DMA request for channel 1 0b1..Enable asynchronous DMA request for channel 1.

◆ DMA_EARS_EDREQ_10 [1/3]

#define DMA_EARS_EDREQ_10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 0b0..Disable asynchronous DMA request for channel 10. 0b1..Enable asynchronous DMA request for channel 10.

◆ DMA_EARS_EDREQ_10 [2/3]

#define DMA_EARS_EDREQ_10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 0b0..Disable asynchronous DMA request for channel 10. 0b1..Enable asynchronous DMA request for channel 10.

◆ DMA_EARS_EDREQ_10 [3/3]

#define DMA_EARS_EDREQ_10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)

EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 0b0..Disable asynchronous DMA request for channel 10. 0b1..Enable asynchronous DMA request for channel 10.

◆ DMA_EARS_EDREQ_11 [1/3]

#define DMA_EARS_EDREQ_11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 0b0..Disable asynchronous DMA request for channel 11. 0b1..Enable asynchronous DMA request for channel 11.

◆ DMA_EARS_EDREQ_11 [2/3]

#define DMA_EARS_EDREQ_11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 0b0..Disable asynchronous DMA request for channel 11. 0b1..Enable asynchronous DMA request for channel 11.

◆ DMA_EARS_EDREQ_11 [3/3]

#define DMA_EARS_EDREQ_11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)

EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 0b0..Disable asynchronous DMA request for channel 11. 0b1..Enable asynchronous DMA request for channel 11.

◆ DMA_EARS_EDREQ_12 [1/3]

#define DMA_EARS_EDREQ_12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 0b0..Disable asynchronous DMA request for channel 12. 0b1..Enable asynchronous DMA request for channel 12.

◆ DMA_EARS_EDREQ_12 [2/3]

#define DMA_EARS_EDREQ_12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 0b0..Disable asynchronous DMA request for channel 12. 0b1..Enable asynchronous DMA request for channel 12.

◆ DMA_EARS_EDREQ_12 [3/3]

#define DMA_EARS_EDREQ_12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)

EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 0b0..Disable asynchronous DMA request for channel 12. 0b1..Enable asynchronous DMA request for channel 12.

◆ DMA_EARS_EDREQ_13 [1/3]

#define DMA_EARS_EDREQ_13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 0b0..Disable asynchronous DMA request for channel 13. 0b1..Enable asynchronous DMA request for channel 13.

◆ DMA_EARS_EDREQ_13 [2/3]

#define DMA_EARS_EDREQ_13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 0b0..Disable asynchronous DMA request for channel 13. 0b1..Enable asynchronous DMA request for channel 13.

◆ DMA_EARS_EDREQ_13 [3/3]

#define DMA_EARS_EDREQ_13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)

EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 0b0..Disable asynchronous DMA request for channel 13. 0b1..Enable asynchronous DMA request for channel 13.

◆ DMA_EARS_EDREQ_14 [1/3]

#define DMA_EARS_EDREQ_14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 0b0..Disable asynchronous DMA request for channel 14. 0b1..Enable asynchronous DMA request for channel 14.

◆ DMA_EARS_EDREQ_14 [2/3]

#define DMA_EARS_EDREQ_14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 0b0..Disable asynchronous DMA request for channel 14. 0b1..Enable asynchronous DMA request for channel 14.

◆ DMA_EARS_EDREQ_14 [3/3]

#define DMA_EARS_EDREQ_14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)

EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 0b0..Disable asynchronous DMA request for channel 14. 0b1..Enable asynchronous DMA request for channel 14.

◆ DMA_EARS_EDREQ_15 [1/3]

#define DMA_EARS_EDREQ_15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 0b0..Disable asynchronous DMA request for channel 15. 0b1..Enable asynchronous DMA request for channel 15.

◆ DMA_EARS_EDREQ_15 [2/3]

#define DMA_EARS_EDREQ_15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 0b0..Disable asynchronous DMA request for channel 15. 0b1..Enable asynchronous DMA request for channel 15.

◆ DMA_EARS_EDREQ_15 [3/3]

#define DMA_EARS_EDREQ_15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)

EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 0b0..Disable asynchronous DMA request for channel 15. 0b1..Enable asynchronous DMA request for channel 15.

◆ DMA_EARS_EDREQ_16 [1/3]

#define DMA_EARS_EDREQ_16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 0b0..Disable asynchronous DMA request for channel 16 0b1..Enable asynchronous DMA request for channel 16

◆ DMA_EARS_EDREQ_16 [2/3]

#define DMA_EARS_EDREQ_16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 0b0..Disable asynchronous DMA request for channel 16 0b1..Enable asynchronous DMA request for channel 16

◆ DMA_EARS_EDREQ_16 [3/3]

#define DMA_EARS_EDREQ_16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)

EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 0b0..Disable asynchronous DMA request for channel 16 0b1..Enable asynchronous DMA request for channel 16

◆ DMA_EARS_EDREQ_17 [1/3]

#define DMA_EARS_EDREQ_17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 0b0..Disable asynchronous DMA request for channel 17 0b1..Enable asynchronous DMA request for channel 17

◆ DMA_EARS_EDREQ_17 [2/3]

#define DMA_EARS_EDREQ_17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 0b0..Disable asynchronous DMA request for channel 17 0b1..Enable asynchronous DMA request for channel 17

◆ DMA_EARS_EDREQ_17 [3/3]

#define DMA_EARS_EDREQ_17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)

EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 0b0..Disable asynchronous DMA request for channel 17 0b1..Enable asynchronous DMA request for channel 17

◆ DMA_EARS_EDREQ_18 [1/3]

#define DMA_EARS_EDREQ_18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 0b0..Disable asynchronous DMA request for channel 18 0b1..Enable asynchronous DMA request for channel 18

◆ DMA_EARS_EDREQ_18 [2/3]

#define DMA_EARS_EDREQ_18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 0b0..Disable asynchronous DMA request for channel 18 0b1..Enable asynchronous DMA request for channel 18

◆ DMA_EARS_EDREQ_18 [3/3]

#define DMA_EARS_EDREQ_18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)

EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 0b0..Disable asynchronous DMA request for channel 18 0b1..Enable asynchronous DMA request for channel 18

◆ DMA_EARS_EDREQ_19 [1/3]

#define DMA_EARS_EDREQ_19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 0b0..Disable asynchronous DMA request for channel 19 0b1..Enable asynchronous DMA request for channel 19

◆ DMA_EARS_EDREQ_19 [2/3]

#define DMA_EARS_EDREQ_19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 0b0..Disable asynchronous DMA request for channel 19 0b1..Enable asynchronous DMA request for channel 19

◆ DMA_EARS_EDREQ_19 [3/3]

#define DMA_EARS_EDREQ_19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)

EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 0b0..Disable asynchronous DMA request for channel 19 0b1..Enable asynchronous DMA request for channel 19

◆ DMA_EARS_EDREQ_2 [1/3]

#define DMA_EARS_EDREQ_2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. 0b0..Disable asynchronous DMA request for channel 2. 0b1..Enable asynchronous DMA request for channel 2.

◆ DMA_EARS_EDREQ_2 [2/3]

#define DMA_EARS_EDREQ_2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. 0b0..Disable asynchronous DMA request for channel 2. 0b1..Enable asynchronous DMA request for channel 2.

◆ DMA_EARS_EDREQ_2 [3/3]

#define DMA_EARS_EDREQ_2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)

EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. 0b0..Disable asynchronous DMA request for channel 2. 0b1..Enable asynchronous DMA request for channel 2.

◆ DMA_EARS_EDREQ_20 [1/3]

#define DMA_EARS_EDREQ_20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 0b0..Disable asynchronous DMA request for channel 20 0b1..Enable asynchronous DMA request for channel 20

◆ DMA_EARS_EDREQ_20 [2/3]

#define DMA_EARS_EDREQ_20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 0b0..Disable asynchronous DMA request for channel 20 0b1..Enable asynchronous DMA request for channel 20

◆ DMA_EARS_EDREQ_20 [3/3]

#define DMA_EARS_EDREQ_20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)

EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 0b0..Disable asynchronous DMA request for channel 20 0b1..Enable asynchronous DMA request for channel 20

◆ DMA_EARS_EDREQ_21 [1/3]

#define DMA_EARS_EDREQ_21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 0b0..Disable asynchronous DMA request for channel 21 0b1..Enable asynchronous DMA request for channel 21

◆ DMA_EARS_EDREQ_21 [2/3]

#define DMA_EARS_EDREQ_21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 0b0..Disable asynchronous DMA request for channel 21 0b1..Enable asynchronous DMA request for channel 21

◆ DMA_EARS_EDREQ_21 [3/3]

#define DMA_EARS_EDREQ_21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)

EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 0b0..Disable asynchronous DMA request for channel 21 0b1..Enable asynchronous DMA request for channel 21

◆ DMA_EARS_EDREQ_22 [1/3]

#define DMA_EARS_EDREQ_22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 0b0..Disable asynchronous DMA request for channel 22 0b1..Enable asynchronous DMA request for channel 22

◆ DMA_EARS_EDREQ_22 [2/3]

#define DMA_EARS_EDREQ_22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 0b0..Disable asynchronous DMA request for channel 22 0b1..Enable asynchronous DMA request for channel 22

◆ DMA_EARS_EDREQ_22 [3/3]

#define DMA_EARS_EDREQ_22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)

EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 0b0..Disable asynchronous DMA request for channel 22 0b1..Enable asynchronous DMA request for channel 22

◆ DMA_EARS_EDREQ_23 [1/3]

#define DMA_EARS_EDREQ_23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 0b0..Disable asynchronous DMA request for channel 23 0b1..Enable asynchronous DMA request for channel 23

◆ DMA_EARS_EDREQ_23 [2/3]

#define DMA_EARS_EDREQ_23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 0b0..Disable asynchronous DMA request for channel 23 0b1..Enable asynchronous DMA request for channel 23

◆ DMA_EARS_EDREQ_23 [3/3]

#define DMA_EARS_EDREQ_23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)

EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 0b0..Disable asynchronous DMA request for channel 23 0b1..Enable asynchronous DMA request for channel 23

◆ DMA_EARS_EDREQ_24 [1/3]

#define DMA_EARS_EDREQ_24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 0b0..Disable asynchronous DMA request for channel 24 0b1..Enable asynchronous DMA request for channel 24

◆ DMA_EARS_EDREQ_24 [2/3]

#define DMA_EARS_EDREQ_24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 0b0..Disable asynchronous DMA request for channel 24 0b1..Enable asynchronous DMA request for channel 24

◆ DMA_EARS_EDREQ_24 [3/3]

#define DMA_EARS_EDREQ_24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)

EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 0b0..Disable asynchronous DMA request for channel 24 0b1..Enable asynchronous DMA request for channel 24

◆ DMA_EARS_EDREQ_25 [1/3]

#define DMA_EARS_EDREQ_25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 0b0..Disable asynchronous DMA request for channel 25 0b1..Enable asynchronous DMA request for channel 25

◆ DMA_EARS_EDREQ_25 [2/3]

#define DMA_EARS_EDREQ_25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 0b0..Disable asynchronous DMA request for channel 25 0b1..Enable asynchronous DMA request for channel 25

◆ DMA_EARS_EDREQ_25 [3/3]

#define DMA_EARS_EDREQ_25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)

EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 0b0..Disable asynchronous DMA request for channel 25 0b1..Enable asynchronous DMA request for channel 25

◆ DMA_EARS_EDREQ_26 [1/3]

#define DMA_EARS_EDREQ_26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 0b0..Disable asynchronous DMA request for channel 26 0b1..Enable asynchronous DMA request for channel 26

◆ DMA_EARS_EDREQ_26 [2/3]

#define DMA_EARS_EDREQ_26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 0b0..Disable asynchronous DMA request for channel 26 0b1..Enable asynchronous DMA request for channel 26

◆ DMA_EARS_EDREQ_26 [3/3]

#define DMA_EARS_EDREQ_26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)

EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 0b0..Disable asynchronous DMA request for channel 26 0b1..Enable asynchronous DMA request for channel 26

◆ DMA_EARS_EDREQ_27 [1/3]

#define DMA_EARS_EDREQ_27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 0b0..Disable asynchronous DMA request for channel 27 0b1..Enable asynchronous DMA request for channel 27

◆ DMA_EARS_EDREQ_27 [2/3]

#define DMA_EARS_EDREQ_27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 0b0..Disable asynchronous DMA request for channel 27 0b1..Enable asynchronous DMA request for channel 27

◆ DMA_EARS_EDREQ_27 [3/3]

#define DMA_EARS_EDREQ_27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)

EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 0b0..Disable asynchronous DMA request for channel 27 0b1..Enable asynchronous DMA request for channel 27

◆ DMA_EARS_EDREQ_28 [1/3]

#define DMA_EARS_EDREQ_28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 0b0..Disable asynchronous DMA request for channel 28 0b1..Enable asynchronous DMA request for channel 28

◆ DMA_EARS_EDREQ_28 [2/3]

#define DMA_EARS_EDREQ_28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 0b0..Disable asynchronous DMA request for channel 28 0b1..Enable asynchronous DMA request for channel 28

◆ DMA_EARS_EDREQ_28 [3/3]

#define DMA_EARS_EDREQ_28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)

EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 0b0..Disable asynchronous DMA request for channel 28 0b1..Enable asynchronous DMA request for channel 28

◆ DMA_EARS_EDREQ_29 [1/3]

#define DMA_EARS_EDREQ_29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 0b0..Disable asynchronous DMA request for channel 29 0b1..Enable asynchronous DMA request for channel 29

◆ DMA_EARS_EDREQ_29 [2/3]

#define DMA_EARS_EDREQ_29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 0b0..Disable asynchronous DMA request for channel 29 0b1..Enable asynchronous DMA request for channel 29

◆ DMA_EARS_EDREQ_29 [3/3]

#define DMA_EARS_EDREQ_29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)

EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 0b0..Disable asynchronous DMA request for channel 29 0b1..Enable asynchronous DMA request for channel 29

◆ DMA_EARS_EDREQ_3 [1/3]

#define DMA_EARS_EDREQ_3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. 0b0..Disable asynchronous DMA request for channel 3. 0b1..Enable asynchronous DMA request for channel 3.

◆ DMA_EARS_EDREQ_3 [2/3]

#define DMA_EARS_EDREQ_3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. 0b0..Disable asynchronous DMA request for channel 3. 0b1..Enable asynchronous DMA request for channel 3.

◆ DMA_EARS_EDREQ_3 [3/3]

#define DMA_EARS_EDREQ_3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)

EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. 0b0..Disable asynchronous DMA request for channel 3. 0b1..Enable asynchronous DMA request for channel 3.

◆ DMA_EARS_EDREQ_30 [1/3]

#define DMA_EARS_EDREQ_30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 0b0..Disable asynchronous DMA request for channel 30 0b1..Enable asynchronous DMA request for channel 30

◆ DMA_EARS_EDREQ_30 [2/3]

#define DMA_EARS_EDREQ_30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 0b0..Disable asynchronous DMA request for channel 30 0b1..Enable asynchronous DMA request for channel 30

◆ DMA_EARS_EDREQ_30 [3/3]

#define DMA_EARS_EDREQ_30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)

EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 0b0..Disable asynchronous DMA request for channel 30 0b1..Enable asynchronous DMA request for channel 30

◆ DMA_EARS_EDREQ_31 [1/3]

#define DMA_EARS_EDREQ_31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 0b0..Disable asynchronous DMA request for channel 31 0b1..Enable asynchronous DMA request for channel 31

◆ DMA_EARS_EDREQ_31 [2/3]

#define DMA_EARS_EDREQ_31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 0b0..Disable asynchronous DMA request for channel 31 0b1..Enable asynchronous DMA request for channel 31

◆ DMA_EARS_EDREQ_31 [3/3]

#define DMA_EARS_EDREQ_31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)

EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 0b0..Disable asynchronous DMA request for channel 31 0b1..Enable asynchronous DMA request for channel 31

◆ DMA_EARS_EDREQ_4 [1/3]

#define DMA_EARS_EDREQ_4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 0b0..Disable asynchronous DMA request for channel 4. 0b1..Enable asynchronous DMA request for channel 4.

◆ DMA_EARS_EDREQ_4 [2/3]

#define DMA_EARS_EDREQ_4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 0b0..Disable asynchronous DMA request for channel 4. 0b1..Enable asynchronous DMA request for channel 4.

◆ DMA_EARS_EDREQ_4 [3/3]

#define DMA_EARS_EDREQ_4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)

EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 0b0..Disable asynchronous DMA request for channel 4. 0b1..Enable asynchronous DMA request for channel 4.

◆ DMA_EARS_EDREQ_5 [1/3]

#define DMA_EARS_EDREQ_5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 0b0..Disable asynchronous DMA request for channel 5. 0b1..Enable asynchronous DMA request for channel 5.

◆ DMA_EARS_EDREQ_5 [2/3]

#define DMA_EARS_EDREQ_5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 0b0..Disable asynchronous DMA request for channel 5. 0b1..Enable asynchronous DMA request for channel 5.

◆ DMA_EARS_EDREQ_5 [3/3]

#define DMA_EARS_EDREQ_5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)

EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 0b0..Disable asynchronous DMA request for channel 5. 0b1..Enable asynchronous DMA request for channel 5.

◆ DMA_EARS_EDREQ_6 [1/3]

#define DMA_EARS_EDREQ_6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 0b0..Disable asynchronous DMA request for channel 6. 0b1..Enable asynchronous DMA request for channel 6.

◆ DMA_EARS_EDREQ_6 [2/3]

#define DMA_EARS_EDREQ_6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 0b0..Disable asynchronous DMA request for channel 6. 0b1..Enable asynchronous DMA request for channel 6.

◆ DMA_EARS_EDREQ_6 [3/3]

#define DMA_EARS_EDREQ_6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)

EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 0b0..Disable asynchronous DMA request for channel 6. 0b1..Enable asynchronous DMA request for channel 6.

◆ DMA_EARS_EDREQ_7 [1/3]

#define DMA_EARS_EDREQ_7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 0b0..Disable asynchronous DMA request for channel 7. 0b1..Enable asynchronous DMA request for channel 7.

◆ DMA_EARS_EDREQ_7 [2/3]

#define DMA_EARS_EDREQ_7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 0b0..Disable asynchronous DMA request for channel 7. 0b1..Enable asynchronous DMA request for channel 7.

◆ DMA_EARS_EDREQ_7 [3/3]

#define DMA_EARS_EDREQ_7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)

EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 0b0..Disable asynchronous DMA request for channel 7. 0b1..Enable asynchronous DMA request for channel 7.

◆ DMA_EARS_EDREQ_8 [1/3]

#define DMA_EARS_EDREQ_8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 0b0..Disable asynchronous DMA request for channel 8. 0b1..Enable asynchronous DMA request for channel 8.

◆ DMA_EARS_EDREQ_8 [2/3]

#define DMA_EARS_EDREQ_8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 0b0..Disable asynchronous DMA request for channel 8. 0b1..Enable asynchronous DMA request for channel 8.

◆ DMA_EARS_EDREQ_8 [3/3]

#define DMA_EARS_EDREQ_8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)

EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 0b0..Disable asynchronous DMA request for channel 8. 0b1..Enable asynchronous DMA request for channel 8.

◆ DMA_EARS_EDREQ_9 [1/3]

#define DMA_EARS_EDREQ_9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 0b0..Disable asynchronous DMA request for channel 9. 0b1..Enable asynchronous DMA request for channel 9.

◆ DMA_EARS_EDREQ_9 [2/3]

#define DMA_EARS_EDREQ_9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 0b0..Disable asynchronous DMA request for channel 9. 0b1..Enable asynchronous DMA request for channel 9.

◆ DMA_EARS_EDREQ_9 [3/3]

#define DMA_EARS_EDREQ_9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)

EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 0b0..Disable asynchronous DMA request for channel 9. 0b1..Enable asynchronous DMA request for channel 9.

◆ DMA_EEI_EEI0 [1/5]

#define DMA_EEI_EEI0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

EEI0 - Enable Error Interrupt 0 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI0 [2/5]

#define DMA_EEI_EEI0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

EEI0 - Enable Error Interrupt 0 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI0 [3/5]

#define DMA_EEI_EEI0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

EEI0 - Enable Error Interrupt 0 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI0 [4/5]

#define DMA_EEI_EEI0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

EEI0 - Enable Error Interrupt 0 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI0 [5/5]

#define DMA_EEI_EEI0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)

EEI0 - Enable Error Interrupt 0 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI1 [1/5]

#define DMA_EEI_EEI1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

EEI1 - Enable Error Interrupt 1 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI1 [2/5]

#define DMA_EEI_EEI1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

EEI1 - Enable Error Interrupt 1 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI1 [3/5]

#define DMA_EEI_EEI1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

EEI1 - Enable Error Interrupt 1 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI1 [4/5]

#define DMA_EEI_EEI1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

EEI1 - Enable Error Interrupt 1 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI1 [5/5]

#define DMA_EEI_EEI1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)

EEI1 - Enable Error Interrupt 1 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI10 [1/5]

#define DMA_EEI_EEI10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

EEI10 - Enable Error Interrupt 10 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI10 [2/5]

#define DMA_EEI_EEI10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

EEI10 - Enable Error Interrupt 10 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI10 [3/5]

#define DMA_EEI_EEI10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

EEI10 - Enable Error Interrupt 10 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI10 [4/5]

#define DMA_EEI_EEI10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

EEI10 - Enable Error Interrupt 10 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI10 [5/5]

#define DMA_EEI_EEI10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)

EEI10 - Enable Error Interrupt 10 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI11 [1/5]

#define DMA_EEI_EEI11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

EEI11 - Enable Error Interrupt 11 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI11 [2/5]

#define DMA_EEI_EEI11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

EEI11 - Enable Error Interrupt 11 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI11 [3/5]

#define DMA_EEI_EEI11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

EEI11 - Enable Error Interrupt 11 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI11 [4/5]

#define DMA_EEI_EEI11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

EEI11 - Enable Error Interrupt 11 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI11 [5/5]

#define DMA_EEI_EEI11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)

EEI11 - Enable Error Interrupt 11 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI12 [1/5]

#define DMA_EEI_EEI12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

EEI12 - Enable Error Interrupt 12 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI12 [2/5]

#define DMA_EEI_EEI12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

EEI12 - Enable Error Interrupt 12 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI12 [3/5]

#define DMA_EEI_EEI12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

EEI12 - Enable Error Interrupt 12 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI12 [4/5]

#define DMA_EEI_EEI12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

EEI12 - Enable Error Interrupt 12 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI12 [5/5]

#define DMA_EEI_EEI12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)

EEI12 - Enable Error Interrupt 12 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI13 [1/5]

#define DMA_EEI_EEI13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

EEI13 - Enable Error Interrupt 13 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI13 [2/5]

#define DMA_EEI_EEI13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

EEI13 - Enable Error Interrupt 13 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI13 [3/5]

#define DMA_EEI_EEI13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

EEI13 - Enable Error Interrupt 13 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI13 [4/5]

#define DMA_EEI_EEI13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

EEI13 - Enable Error Interrupt 13 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI13 [5/5]

#define DMA_EEI_EEI13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)

EEI13 - Enable Error Interrupt 13 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI14 [1/5]

#define DMA_EEI_EEI14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

EEI14 - Enable Error Interrupt 14 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI14 [2/5]

#define DMA_EEI_EEI14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

EEI14 - Enable Error Interrupt 14 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI14 [3/5]

#define DMA_EEI_EEI14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

EEI14 - Enable Error Interrupt 14 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI14 [4/5]

#define DMA_EEI_EEI14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

EEI14 - Enable Error Interrupt 14 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI14 [5/5]

#define DMA_EEI_EEI14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)

EEI14 - Enable Error Interrupt 14 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI15 [1/5]

#define DMA_EEI_EEI15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

EEI15 - Enable Error Interrupt 15 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI15 [2/5]

#define DMA_EEI_EEI15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

EEI15 - Enable Error Interrupt 15 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI15 [3/5]

#define DMA_EEI_EEI15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

EEI15 - Enable Error Interrupt 15 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI15 [4/5]

#define DMA_EEI_EEI15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

EEI15 - Enable Error Interrupt 15 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI15 [5/5]

#define DMA_EEI_EEI15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)

EEI15 - Enable Error Interrupt 15 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI16 [1/3]

#define DMA_EEI_EEI16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

EEI16 - Enable Error Interrupt 16 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI16 [2/3]

#define DMA_EEI_EEI16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

EEI16 - Enable Error Interrupt 16 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI16 [3/3]

#define DMA_EEI_EEI16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)

EEI16 - Enable Error Interrupt 16 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI17 [1/3]

#define DMA_EEI_EEI17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

EEI17 - Enable Error Interrupt 17 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI17 [2/3]

#define DMA_EEI_EEI17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

EEI17 - Enable Error Interrupt 17 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI17 [3/3]

#define DMA_EEI_EEI17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)

EEI17 - Enable Error Interrupt 17 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI18 [1/3]

#define DMA_EEI_EEI18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

EEI18 - Enable Error Interrupt 18 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI18 [2/3]

#define DMA_EEI_EEI18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

EEI18 - Enable Error Interrupt 18 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI18 [3/3]

#define DMA_EEI_EEI18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)

EEI18 - Enable Error Interrupt 18 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI19 [1/3]

#define DMA_EEI_EEI19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

EEI19 - Enable Error Interrupt 19 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI19 [2/3]

#define DMA_EEI_EEI19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

EEI19 - Enable Error Interrupt 19 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI19 [3/3]

#define DMA_EEI_EEI19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)

EEI19 - Enable Error Interrupt 19 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI2 [1/5]

#define DMA_EEI_EEI2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

EEI2 - Enable Error Interrupt 2 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI2 [2/5]

#define DMA_EEI_EEI2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

EEI2 - Enable Error Interrupt 2 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI2 [3/5]

#define DMA_EEI_EEI2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

EEI2 - Enable Error Interrupt 2 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI2 [4/5]

#define DMA_EEI_EEI2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

EEI2 - Enable Error Interrupt 2 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI2 [5/5]

#define DMA_EEI_EEI2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)

EEI2 - Enable Error Interrupt 2 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI20 [1/3]

#define DMA_EEI_EEI20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

EEI20 - Enable Error Interrupt 20 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI20 [2/3]

#define DMA_EEI_EEI20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

EEI20 - Enable Error Interrupt 20 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI20 [3/3]

#define DMA_EEI_EEI20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)

EEI20 - Enable Error Interrupt 20 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI21 [1/3]

#define DMA_EEI_EEI21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

EEI21 - Enable Error Interrupt 21 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI21 [2/3]

#define DMA_EEI_EEI21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

EEI21 - Enable Error Interrupt 21 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI21 [3/3]

#define DMA_EEI_EEI21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)

EEI21 - Enable Error Interrupt 21 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI22 [1/3]

#define DMA_EEI_EEI22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

EEI22 - Enable Error Interrupt 22 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI22 [2/3]

#define DMA_EEI_EEI22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

EEI22 - Enable Error Interrupt 22 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI22 [3/3]

#define DMA_EEI_EEI22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)

EEI22 - Enable Error Interrupt 22 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI23 [1/3]

#define DMA_EEI_EEI23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

EEI23 - Enable Error Interrupt 23 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI23 [2/3]

#define DMA_EEI_EEI23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

EEI23 - Enable Error Interrupt 23 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI23 [3/3]

#define DMA_EEI_EEI23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)

EEI23 - Enable Error Interrupt 23 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI24 [1/3]

#define DMA_EEI_EEI24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

EEI24 - Enable Error Interrupt 24 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI24 [2/3]

#define DMA_EEI_EEI24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

EEI24 - Enable Error Interrupt 24 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI24 [3/3]

#define DMA_EEI_EEI24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)

EEI24 - Enable Error Interrupt 24 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI25 [1/3]

#define DMA_EEI_EEI25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

EEI25 - Enable Error Interrupt 25 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI25 [2/3]

#define DMA_EEI_EEI25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

EEI25 - Enable Error Interrupt 25 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI25 [3/3]

#define DMA_EEI_EEI25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)

EEI25 - Enable Error Interrupt 25 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI26 [1/3]

#define DMA_EEI_EEI26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

EEI26 - Enable Error Interrupt 26 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI26 [2/3]

#define DMA_EEI_EEI26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

EEI26 - Enable Error Interrupt 26 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI26 [3/3]

#define DMA_EEI_EEI26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)

EEI26 - Enable Error Interrupt 26 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI27 [1/3]

#define DMA_EEI_EEI27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

EEI27 - Enable Error Interrupt 27 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI27 [2/3]

#define DMA_EEI_EEI27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

EEI27 - Enable Error Interrupt 27 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI27 [3/3]

#define DMA_EEI_EEI27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)

EEI27 - Enable Error Interrupt 27 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI28 [1/3]

#define DMA_EEI_EEI28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

EEI28 - Enable Error Interrupt 28 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI28 [2/3]

#define DMA_EEI_EEI28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

EEI28 - Enable Error Interrupt 28 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI28 [3/3]

#define DMA_EEI_EEI28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)

EEI28 - Enable Error Interrupt 28 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI29 [1/3]

#define DMA_EEI_EEI29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

EEI29 - Enable Error Interrupt 29 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI29 [2/3]

#define DMA_EEI_EEI29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

EEI29 - Enable Error Interrupt 29 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI29 [3/3]

#define DMA_EEI_EEI29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)

EEI29 - Enable Error Interrupt 29 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI3 [1/5]

#define DMA_EEI_EEI3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

EEI3 - Enable Error Interrupt 3 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI3 [2/5]

#define DMA_EEI_EEI3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

EEI3 - Enable Error Interrupt 3 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI3 [3/5]

#define DMA_EEI_EEI3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

EEI3 - Enable Error Interrupt 3 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI3 [4/5]

#define DMA_EEI_EEI3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

EEI3 - Enable Error Interrupt 3 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI3 [5/5]

#define DMA_EEI_EEI3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)

EEI3 - Enable Error Interrupt 3 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI30 [1/3]

#define DMA_EEI_EEI30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

EEI30 - Enable Error Interrupt 30 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI30 [2/3]

#define DMA_EEI_EEI30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

EEI30 - Enable Error Interrupt 30 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI30 [3/3]

#define DMA_EEI_EEI30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)

EEI30 - Enable Error Interrupt 30 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI31 [1/3]

#define DMA_EEI_EEI31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

EEI31 - Enable Error Interrupt 31 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI31 [2/3]

#define DMA_EEI_EEI31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

EEI31 - Enable Error Interrupt 31 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI31 [3/3]

#define DMA_EEI_EEI31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)

EEI31 - Enable Error Interrupt 31 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI4 [1/5]

#define DMA_EEI_EEI4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

EEI4 - Enable Error Interrupt 4 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI4 [2/5]

#define DMA_EEI_EEI4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

EEI4 - Enable Error Interrupt 4 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI4 [3/5]

#define DMA_EEI_EEI4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

EEI4 - Enable Error Interrupt 4 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI4 [4/5]

#define DMA_EEI_EEI4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

EEI4 - Enable Error Interrupt 4 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI4 [5/5]

#define DMA_EEI_EEI4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)

EEI4 - Enable Error Interrupt 4 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI5 [1/5]

#define DMA_EEI_EEI5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

EEI5 - Enable Error Interrupt 5 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI5 [2/5]

#define DMA_EEI_EEI5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

EEI5 - Enable Error Interrupt 5 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI5 [3/5]

#define DMA_EEI_EEI5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

EEI5 - Enable Error Interrupt 5 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI5 [4/5]

#define DMA_EEI_EEI5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

EEI5 - Enable Error Interrupt 5 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI5 [5/5]

#define DMA_EEI_EEI5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)

EEI5 - Enable Error Interrupt 5 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI6 [1/5]

#define DMA_EEI_EEI6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

EEI6 - Enable Error Interrupt 6 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI6 [2/5]

#define DMA_EEI_EEI6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

EEI6 - Enable Error Interrupt 6 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI6 [3/5]

#define DMA_EEI_EEI6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

EEI6 - Enable Error Interrupt 6 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI6 [4/5]

#define DMA_EEI_EEI6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

EEI6 - Enable Error Interrupt 6 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI6 [5/5]

#define DMA_EEI_EEI6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)

EEI6 - Enable Error Interrupt 6 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI7 [1/5]

#define DMA_EEI_EEI7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

EEI7 - Enable Error Interrupt 7 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI7 [2/5]

#define DMA_EEI_EEI7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

EEI7 - Enable Error Interrupt 7 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI7 [3/5]

#define DMA_EEI_EEI7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

EEI7 - Enable Error Interrupt 7 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI7 [4/5]

#define DMA_EEI_EEI7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

EEI7 - Enable Error Interrupt 7 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI7 [5/5]

#define DMA_EEI_EEI7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)

EEI7 - Enable Error Interrupt 7 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI8 [1/5]

#define DMA_EEI_EEI8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

EEI8 - Enable Error Interrupt 8 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI8 [2/5]

#define DMA_EEI_EEI8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

EEI8 - Enable Error Interrupt 8 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI8 [3/5]

#define DMA_EEI_EEI8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

EEI8 - Enable Error Interrupt 8 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI8 [4/5]

#define DMA_EEI_EEI8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

EEI8 - Enable Error Interrupt 8 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI8 [5/5]

#define DMA_EEI_EEI8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)

EEI8 - Enable Error Interrupt 8 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI9 [1/5]

#define DMA_EEI_EEI9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

EEI9 - Enable Error Interrupt 9 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI9 [2/5]

#define DMA_EEI_EEI9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

EEI9 - Enable Error Interrupt 9 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI9 [3/5]

#define DMA_EEI_EEI9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

EEI9 - Enable Error Interrupt 9 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI9 [4/5]

#define DMA_EEI_EEI9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

EEI9 - Enable Error Interrupt 9 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_EEI_EEI9 [5/5]

#define DMA_EEI_EEI9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)

EEI9 - Enable Error Interrupt 9 0b0..The error signal for corresponding channel does not generate an error interrupt 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request

◆ DMA_ERQ_ERQ0 [1/5]

#define DMA_ERQ_ERQ0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

ERQ0 - Enable DMA Request 0 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ0 [2/5]

#define DMA_ERQ_ERQ0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

ERQ0 - Enable DMA Request 0 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ0 [3/5]

#define DMA_ERQ_ERQ0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

ERQ0 - Enable DMA Request 0 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ0 [4/5]

#define DMA_ERQ_ERQ0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

ERQ0 - Enable DMA Request 0 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ0 [5/5]

#define DMA_ERQ_ERQ0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)

ERQ0 - Enable DMA Request 0 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ1 [1/5]

#define DMA_ERQ_ERQ1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

ERQ1 - Enable DMA Request 1 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ1 [2/5]

#define DMA_ERQ_ERQ1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

ERQ1 - Enable DMA Request 1 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ1 [3/5]

#define DMA_ERQ_ERQ1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

ERQ1 - Enable DMA Request 1 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ1 [4/5]

#define DMA_ERQ_ERQ1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

ERQ1 - Enable DMA Request 1 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ1 [5/5]

#define DMA_ERQ_ERQ1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)

ERQ1 - Enable DMA Request 1 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ10 [1/5]

#define DMA_ERQ_ERQ10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

ERQ10 - Enable DMA Request 10 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ10 [2/5]

#define DMA_ERQ_ERQ10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

ERQ10 - Enable DMA Request 10 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ10 [3/5]

#define DMA_ERQ_ERQ10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

ERQ10 - Enable DMA Request 10 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ10 [4/5]

#define DMA_ERQ_ERQ10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

ERQ10 - Enable DMA Request 10 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ10 [5/5]

#define DMA_ERQ_ERQ10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)

ERQ10 - Enable DMA Request 10 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ11 [1/5]

#define DMA_ERQ_ERQ11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

ERQ11 - Enable DMA Request 11 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ11 [2/5]

#define DMA_ERQ_ERQ11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

ERQ11 - Enable DMA Request 11 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ11 [3/5]

#define DMA_ERQ_ERQ11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

ERQ11 - Enable DMA Request 11 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ11 [4/5]

#define DMA_ERQ_ERQ11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

ERQ11 - Enable DMA Request 11 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ11 [5/5]

#define DMA_ERQ_ERQ11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)

ERQ11 - Enable DMA Request 11 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ12 [1/5]

#define DMA_ERQ_ERQ12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

ERQ12 - Enable DMA Request 12 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ12 [2/5]

#define DMA_ERQ_ERQ12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

ERQ12 - Enable DMA Request 12 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ12 [3/5]

#define DMA_ERQ_ERQ12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

ERQ12 - Enable DMA Request 12 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ12 [4/5]

#define DMA_ERQ_ERQ12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

ERQ12 - Enable DMA Request 12 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ12 [5/5]

#define DMA_ERQ_ERQ12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)

ERQ12 - Enable DMA Request 12 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ13 [1/5]

#define DMA_ERQ_ERQ13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

ERQ13 - Enable DMA Request 13 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ13 [2/5]

#define DMA_ERQ_ERQ13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

ERQ13 - Enable DMA Request 13 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ13 [3/5]

#define DMA_ERQ_ERQ13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

ERQ13 - Enable DMA Request 13 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ13 [4/5]

#define DMA_ERQ_ERQ13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

ERQ13 - Enable DMA Request 13 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ13 [5/5]

#define DMA_ERQ_ERQ13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)

ERQ13 - Enable DMA Request 13 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ14 [1/5]

#define DMA_ERQ_ERQ14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

ERQ14 - Enable DMA Request 14 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ14 [2/5]

#define DMA_ERQ_ERQ14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

ERQ14 - Enable DMA Request 14 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ14 [3/5]

#define DMA_ERQ_ERQ14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

ERQ14 - Enable DMA Request 14 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ14 [4/5]

#define DMA_ERQ_ERQ14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

ERQ14 - Enable DMA Request 14 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ14 [5/5]

#define DMA_ERQ_ERQ14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)

ERQ14 - Enable DMA Request 14 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ15 [1/5]

#define DMA_ERQ_ERQ15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

ERQ15 - Enable DMA Request 15 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ15 [2/5]

#define DMA_ERQ_ERQ15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

ERQ15 - Enable DMA Request 15 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ15 [3/5]

#define DMA_ERQ_ERQ15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

ERQ15 - Enable DMA Request 15 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ15 [4/5]

#define DMA_ERQ_ERQ15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

ERQ15 - Enable DMA Request 15 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ15 [5/5]

#define DMA_ERQ_ERQ15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)

ERQ15 - Enable DMA Request 15 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ16 [1/3]

#define DMA_ERQ_ERQ16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

ERQ16 - Enable DMA Request 16 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ16 [2/3]

#define DMA_ERQ_ERQ16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

ERQ16 - Enable DMA Request 16 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ16 [3/3]

#define DMA_ERQ_ERQ16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)

ERQ16 - Enable DMA Request 16 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ17 [1/3]

#define DMA_ERQ_ERQ17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

ERQ17 - Enable DMA Request 17 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ17 [2/3]

#define DMA_ERQ_ERQ17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

ERQ17 - Enable DMA Request 17 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ17 [3/3]

#define DMA_ERQ_ERQ17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)

ERQ17 - Enable DMA Request 17 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ18 [1/3]

#define DMA_ERQ_ERQ18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

ERQ18 - Enable DMA Request 18 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ18 [2/3]

#define DMA_ERQ_ERQ18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

ERQ18 - Enable DMA Request 18 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ18 [3/3]

#define DMA_ERQ_ERQ18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)

ERQ18 - Enable DMA Request 18 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ19 [1/3]

#define DMA_ERQ_ERQ19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

ERQ19 - Enable DMA Request 19 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ19 [2/3]

#define DMA_ERQ_ERQ19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

ERQ19 - Enable DMA Request 19 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ19 [3/3]

#define DMA_ERQ_ERQ19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)

ERQ19 - Enable DMA Request 19 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ2 [1/5]

#define DMA_ERQ_ERQ2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

ERQ2 - Enable DMA Request 2 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ2 [2/5]

#define DMA_ERQ_ERQ2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

ERQ2 - Enable DMA Request 2 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ2 [3/5]

#define DMA_ERQ_ERQ2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

ERQ2 - Enable DMA Request 2 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ2 [4/5]

#define DMA_ERQ_ERQ2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

ERQ2 - Enable DMA Request 2 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ2 [5/5]

#define DMA_ERQ_ERQ2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)

ERQ2 - Enable DMA Request 2 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ20 [1/3]

#define DMA_ERQ_ERQ20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

ERQ20 - Enable DMA Request 20 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ20 [2/3]

#define DMA_ERQ_ERQ20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

ERQ20 - Enable DMA Request 20 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ20 [3/3]

#define DMA_ERQ_ERQ20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)

ERQ20 - Enable DMA Request 20 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ21 [1/3]

#define DMA_ERQ_ERQ21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

ERQ21 - Enable DMA Request 21 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ21 [2/3]

#define DMA_ERQ_ERQ21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

ERQ21 - Enable DMA Request 21 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ21 [3/3]

#define DMA_ERQ_ERQ21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)

ERQ21 - Enable DMA Request 21 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ22 [1/3]

#define DMA_ERQ_ERQ22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

ERQ22 - Enable DMA Request 22 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ22 [2/3]

#define DMA_ERQ_ERQ22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

ERQ22 - Enable DMA Request 22 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ22 [3/3]

#define DMA_ERQ_ERQ22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)

ERQ22 - Enable DMA Request 22 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ23 [1/3]

#define DMA_ERQ_ERQ23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

ERQ23 - Enable DMA Request 23 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ23 [2/3]

#define DMA_ERQ_ERQ23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

ERQ23 - Enable DMA Request 23 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ23 [3/3]

#define DMA_ERQ_ERQ23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)

ERQ23 - Enable DMA Request 23 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ24 [1/3]

#define DMA_ERQ_ERQ24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

ERQ24 - Enable DMA Request 24 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ24 [2/3]

#define DMA_ERQ_ERQ24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

ERQ24 - Enable DMA Request 24 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ24 [3/3]

#define DMA_ERQ_ERQ24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)

ERQ24 - Enable DMA Request 24 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ25 [1/3]

#define DMA_ERQ_ERQ25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

ERQ25 - Enable DMA Request 25 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ25 [2/3]

#define DMA_ERQ_ERQ25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

ERQ25 - Enable DMA Request 25 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ25 [3/3]

#define DMA_ERQ_ERQ25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)

ERQ25 - Enable DMA Request 25 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ26 [1/3]

#define DMA_ERQ_ERQ26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

ERQ26 - Enable DMA Request 26 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ26 [2/3]

#define DMA_ERQ_ERQ26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

ERQ26 - Enable DMA Request 26 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ26 [3/3]

#define DMA_ERQ_ERQ26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)

ERQ26 - Enable DMA Request 26 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ27 [1/3]

#define DMA_ERQ_ERQ27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

ERQ27 - Enable DMA Request 27 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ27 [2/3]

#define DMA_ERQ_ERQ27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

ERQ27 - Enable DMA Request 27 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ27 [3/3]

#define DMA_ERQ_ERQ27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)

ERQ27 - Enable DMA Request 27 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ28 [1/3]

#define DMA_ERQ_ERQ28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

ERQ28 - Enable DMA Request 28 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ28 [2/3]

#define DMA_ERQ_ERQ28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

ERQ28 - Enable DMA Request 28 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ28 [3/3]

#define DMA_ERQ_ERQ28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)

ERQ28 - Enable DMA Request 28 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ29 [1/3]

#define DMA_ERQ_ERQ29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

ERQ29 - Enable DMA Request 29 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ29 [2/3]

#define DMA_ERQ_ERQ29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

ERQ29 - Enable DMA Request 29 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ29 [3/3]

#define DMA_ERQ_ERQ29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)

ERQ29 - Enable DMA Request 29 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ3 [1/5]

#define DMA_ERQ_ERQ3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

ERQ3 - Enable DMA Request 3 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ3 [2/5]

#define DMA_ERQ_ERQ3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

ERQ3 - Enable DMA Request 3 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ3 [3/5]

#define DMA_ERQ_ERQ3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

ERQ3 - Enable DMA Request 3 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ3 [4/5]

#define DMA_ERQ_ERQ3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

ERQ3 - Enable DMA Request 3 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ3 [5/5]

#define DMA_ERQ_ERQ3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)

ERQ3 - Enable DMA Request 3 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ30 [1/3]

#define DMA_ERQ_ERQ30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

ERQ30 - Enable DMA Request 30 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ30 [2/3]

#define DMA_ERQ_ERQ30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

ERQ30 - Enable DMA Request 30 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ30 [3/3]

#define DMA_ERQ_ERQ30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)

ERQ30 - Enable DMA Request 30 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ31 [1/3]

#define DMA_ERQ_ERQ31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

ERQ31 - Enable DMA Request 31 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ31 [2/3]

#define DMA_ERQ_ERQ31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

ERQ31 - Enable DMA Request 31 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ31 [3/3]

#define DMA_ERQ_ERQ31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)

ERQ31 - Enable DMA Request 31 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ4 [1/5]

#define DMA_ERQ_ERQ4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

ERQ4 - Enable DMA Request 4 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ4 [2/5]

#define DMA_ERQ_ERQ4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

ERQ4 - Enable DMA Request 4 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ4 [3/5]

#define DMA_ERQ_ERQ4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

ERQ4 - Enable DMA Request 4 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ4 [4/5]

#define DMA_ERQ_ERQ4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

ERQ4 - Enable DMA Request 4 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ4 [5/5]

#define DMA_ERQ_ERQ4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)

ERQ4 - Enable DMA Request 4 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ5 [1/5]

#define DMA_ERQ_ERQ5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

ERQ5 - Enable DMA Request 5 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ5 [2/5]

#define DMA_ERQ_ERQ5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

ERQ5 - Enable DMA Request 5 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ5 [3/5]

#define DMA_ERQ_ERQ5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

ERQ5 - Enable DMA Request 5 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ5 [4/5]

#define DMA_ERQ_ERQ5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

ERQ5 - Enable DMA Request 5 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ5 [5/5]

#define DMA_ERQ_ERQ5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)

ERQ5 - Enable DMA Request 5 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ6 [1/5]

#define DMA_ERQ_ERQ6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

ERQ6 - Enable DMA Request 6 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ6 [2/5]

#define DMA_ERQ_ERQ6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

ERQ6 - Enable DMA Request 6 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ6 [3/5]

#define DMA_ERQ_ERQ6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

ERQ6 - Enable DMA Request 6 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ6 [4/5]

#define DMA_ERQ_ERQ6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

ERQ6 - Enable DMA Request 6 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ6 [5/5]

#define DMA_ERQ_ERQ6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)

ERQ6 - Enable DMA Request 6 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ7 [1/5]

#define DMA_ERQ_ERQ7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

ERQ7 - Enable DMA Request 7 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ7 [2/5]

#define DMA_ERQ_ERQ7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

ERQ7 - Enable DMA Request 7 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ7 [3/5]

#define DMA_ERQ_ERQ7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

ERQ7 - Enable DMA Request 7 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ7 [4/5]

#define DMA_ERQ_ERQ7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

ERQ7 - Enable DMA Request 7 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ7 [5/5]

#define DMA_ERQ_ERQ7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)

ERQ7 - Enable DMA Request 7 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ8 [1/5]

#define DMA_ERQ_ERQ8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

ERQ8 - Enable DMA Request 8 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ8 [2/5]

#define DMA_ERQ_ERQ8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

ERQ8 - Enable DMA Request 8 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ8 [3/5]

#define DMA_ERQ_ERQ8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

ERQ8 - Enable DMA Request 8 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ8 [4/5]

#define DMA_ERQ_ERQ8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

ERQ8 - Enable DMA Request 8 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ8 [5/5]

#define DMA_ERQ_ERQ8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)

ERQ8 - Enable DMA Request 8 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ9 [1/5]

#define DMA_ERQ_ERQ9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

ERQ9 - Enable DMA Request 9 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ9 [2/5]

#define DMA_ERQ_ERQ9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

ERQ9 - Enable DMA Request 9 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ9 [3/5]

#define DMA_ERQ_ERQ9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

ERQ9 - Enable DMA Request 9 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ9 [4/5]

#define DMA_ERQ_ERQ9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

ERQ9 - Enable DMA Request 9 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERQ_ERQ9 [5/5]

#define DMA_ERQ_ERQ9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)

ERQ9 - Enable DMA Request 9 0b0..The DMA request signal for the corresponding channel is disabled 0b1..The DMA request signal for the corresponding channel is enabled

◆ DMA_ERR_ERR0 [1/5]

#define DMA_ERR_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

ERR0 - Error In Channel 0 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR0 - Error In Channel 0 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR0 [2/5]

#define DMA_ERR_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

ERR0 - Error In Channel 0 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR0 - Error In Channel 0 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR0 [3/5]

#define DMA_ERR_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

ERR0 - Error In Channel 0 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR0 [4/5]

#define DMA_ERR_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

ERR0 - Error In Channel 0 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR0 [5/5]

#define DMA_ERR_ERR0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)

ERR0 - Error In Channel 0 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR1 [1/5]

#define DMA_ERR_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

ERR1 - Error In Channel 1 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR1 - Error In Channel 1 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR1 [2/5]

#define DMA_ERR_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

ERR1 - Error In Channel 1 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR1 - Error In Channel 1 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR1 [3/5]

#define DMA_ERR_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

ERR1 - Error In Channel 1 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR1 [4/5]

#define DMA_ERR_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

ERR1 - Error In Channel 1 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR1 [5/5]

#define DMA_ERR_ERR1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)

ERR1 - Error In Channel 1 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR10 [1/5]

#define DMA_ERR_ERR10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

ERR10 - Error In Channel 10 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR10 - Error In Channel 10 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR10 [2/5]

#define DMA_ERR_ERR10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

ERR10 - Error In Channel 10 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR10 - Error In Channel 10 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR10 [3/5]

#define DMA_ERR_ERR10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

ERR10 - Error In Channel 10 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR10 [4/5]

#define DMA_ERR_ERR10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

ERR10 - Error In Channel 10 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR10 [5/5]

#define DMA_ERR_ERR10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)

ERR10 - Error In Channel 10 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR11 [1/5]

#define DMA_ERR_ERR11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

ERR11 - Error In Channel 11 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR11 - Error In Channel 11 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR11 [2/5]

#define DMA_ERR_ERR11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

ERR11 - Error In Channel 11 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR11 - Error In Channel 11 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR11 [3/5]

#define DMA_ERR_ERR11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

ERR11 - Error In Channel 11 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR11 [4/5]

#define DMA_ERR_ERR11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

ERR11 - Error In Channel 11 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR11 [5/5]

#define DMA_ERR_ERR11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)

ERR11 - Error In Channel 11 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR12 [1/5]

#define DMA_ERR_ERR12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

ERR12 - Error In Channel 12 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR12 - Error In Channel 12 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR12 [2/5]

#define DMA_ERR_ERR12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

ERR12 - Error In Channel 12 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR12 - Error In Channel 12 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR12 [3/5]

#define DMA_ERR_ERR12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

ERR12 - Error In Channel 12 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR12 [4/5]

#define DMA_ERR_ERR12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

ERR12 - Error In Channel 12 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR12 [5/5]

#define DMA_ERR_ERR12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)

ERR12 - Error In Channel 12 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR13 [1/5]

#define DMA_ERR_ERR13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

ERR13 - Error In Channel 13 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR13 - Error In Channel 13 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR13 [2/5]

#define DMA_ERR_ERR13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

ERR13 - Error In Channel 13 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR13 - Error In Channel 13 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR13 [3/5]

#define DMA_ERR_ERR13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

ERR13 - Error In Channel 13 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR13 [4/5]

#define DMA_ERR_ERR13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

ERR13 - Error In Channel 13 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR13 [5/5]

#define DMA_ERR_ERR13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)

ERR13 - Error In Channel 13 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR14 [1/5]

#define DMA_ERR_ERR14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

ERR14 - Error In Channel 14 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR14 - Error In Channel 14 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR14 [2/5]

#define DMA_ERR_ERR14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

ERR14 - Error In Channel 14 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR14 - Error In Channel 14 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR14 [3/5]

#define DMA_ERR_ERR14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

ERR14 - Error In Channel 14 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR14 [4/5]

#define DMA_ERR_ERR14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

ERR14 - Error In Channel 14 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR14 [5/5]

#define DMA_ERR_ERR14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)

ERR14 - Error In Channel 14 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR15 [1/5]

#define DMA_ERR_ERR15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

ERR15 - Error In Channel 15 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR15 - Error In Channel 15 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR15 [2/5]

#define DMA_ERR_ERR15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

ERR15 - Error In Channel 15 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR15 - Error In Channel 15 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR15 [3/5]

#define DMA_ERR_ERR15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

ERR15 - Error In Channel 15 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR15 [4/5]

#define DMA_ERR_ERR15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

ERR15 - Error In Channel 15 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR15 [5/5]

#define DMA_ERR_ERR15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)

ERR15 - Error In Channel 15 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR16 [1/3]

#define DMA_ERR_ERR16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

ERR16 - Error In Channel 16 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR16 [2/3]

#define DMA_ERR_ERR16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

ERR16 - Error In Channel 16 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR16 [3/3]

#define DMA_ERR_ERR16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)

ERR16 - Error In Channel 16 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR17 [1/3]

#define DMA_ERR_ERR17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

ERR17 - Error In Channel 17 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR17 [2/3]

#define DMA_ERR_ERR17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

ERR17 - Error In Channel 17 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR17 [3/3]

#define DMA_ERR_ERR17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)

ERR17 - Error In Channel 17 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR18 [1/3]

#define DMA_ERR_ERR18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

ERR18 - Error In Channel 18 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR18 [2/3]

#define DMA_ERR_ERR18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

ERR18 - Error In Channel 18 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR18 [3/3]

#define DMA_ERR_ERR18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)

ERR18 - Error In Channel 18 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR19 [1/3]

#define DMA_ERR_ERR19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

ERR19 - Error In Channel 19 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR19 [2/3]

#define DMA_ERR_ERR19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

ERR19 - Error In Channel 19 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR19 [3/3]

#define DMA_ERR_ERR19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)

ERR19 - Error In Channel 19 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR2 [1/5]

#define DMA_ERR_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

ERR2 - Error In Channel 2 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR2 - Error In Channel 2 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR2 [2/5]

#define DMA_ERR_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

ERR2 - Error In Channel 2 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR2 - Error In Channel 2 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR2 [3/5]

#define DMA_ERR_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

ERR2 - Error In Channel 2 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR2 [4/5]

#define DMA_ERR_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

ERR2 - Error In Channel 2 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR2 [5/5]

#define DMA_ERR_ERR2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)

ERR2 - Error In Channel 2 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR20 [1/3]

#define DMA_ERR_ERR20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

ERR20 - Error In Channel 20 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR20 [2/3]

#define DMA_ERR_ERR20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

ERR20 - Error In Channel 20 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR20 [3/3]

#define DMA_ERR_ERR20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)

ERR20 - Error In Channel 20 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR21 [1/3]

#define DMA_ERR_ERR21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

ERR21 - Error In Channel 21 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR21 [2/3]

#define DMA_ERR_ERR21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

ERR21 - Error In Channel 21 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR21 [3/3]

#define DMA_ERR_ERR21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)

ERR21 - Error In Channel 21 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR22 [1/3]

#define DMA_ERR_ERR22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

ERR22 - Error In Channel 22 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR22 [2/3]

#define DMA_ERR_ERR22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

ERR22 - Error In Channel 22 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR22 [3/3]

#define DMA_ERR_ERR22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)

ERR22 - Error In Channel 22 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR23 [1/3]

#define DMA_ERR_ERR23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

ERR23 - Error In Channel 23 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR23 [2/3]

#define DMA_ERR_ERR23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

ERR23 - Error In Channel 23 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR23 [3/3]

#define DMA_ERR_ERR23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)

ERR23 - Error In Channel 23 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR24 [1/3]

#define DMA_ERR_ERR24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

ERR24 - Error In Channel 24 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR24 [2/3]

#define DMA_ERR_ERR24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

ERR24 - Error In Channel 24 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR24 [3/3]

#define DMA_ERR_ERR24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)

ERR24 - Error In Channel 24 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR25 [1/3]

#define DMA_ERR_ERR25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

ERR25 - Error In Channel 25 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR25 [2/3]

#define DMA_ERR_ERR25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

ERR25 - Error In Channel 25 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR25 [3/3]

#define DMA_ERR_ERR25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)

ERR25 - Error In Channel 25 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR26 [1/3]

#define DMA_ERR_ERR26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

ERR26 - Error In Channel 26 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR26 [2/3]

#define DMA_ERR_ERR26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

ERR26 - Error In Channel 26 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR26 [3/3]

#define DMA_ERR_ERR26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)

ERR26 - Error In Channel 26 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR27 [1/3]

#define DMA_ERR_ERR27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

ERR27 - Error In Channel 27 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR27 [2/3]

#define DMA_ERR_ERR27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

ERR27 - Error In Channel 27 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR27 [3/3]

#define DMA_ERR_ERR27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)

ERR27 - Error In Channel 27 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR28 [1/3]

#define DMA_ERR_ERR28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

ERR28 - Error In Channel 28 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR28 [2/3]

#define DMA_ERR_ERR28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

ERR28 - Error In Channel 28 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR28 [3/3]

#define DMA_ERR_ERR28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)

ERR28 - Error In Channel 28 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR29 [1/3]

#define DMA_ERR_ERR29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

ERR29 - Error In Channel 29 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR29 [2/3]

#define DMA_ERR_ERR29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

ERR29 - Error In Channel 29 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR29 [3/3]

#define DMA_ERR_ERR29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)

ERR29 - Error In Channel 29 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR3 [1/5]

#define DMA_ERR_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

ERR3 - Error In Channel 3 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR3 - Error In Channel 3 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR3 [2/5]

#define DMA_ERR_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

ERR3 - Error In Channel 3 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR3 - Error In Channel 3 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR3 [3/5]

#define DMA_ERR_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

ERR3 - Error In Channel 3 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR3 [4/5]

#define DMA_ERR_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

ERR3 - Error In Channel 3 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR3 [5/5]

#define DMA_ERR_ERR3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)

ERR3 - Error In Channel 3 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR30 [1/3]

#define DMA_ERR_ERR30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

ERR30 - Error In Channel 30 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR30 [2/3]

#define DMA_ERR_ERR30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

ERR30 - Error In Channel 30 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR30 [3/3]

#define DMA_ERR_ERR30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)

ERR30 - Error In Channel 30 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR31 [1/3]

#define DMA_ERR_ERR31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

ERR31 - Error In Channel 31 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR31 [2/3]

#define DMA_ERR_ERR31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

ERR31 - Error In Channel 31 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR31 [3/3]

#define DMA_ERR_ERR31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)

ERR31 - Error In Channel 31 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR4 [1/5]

#define DMA_ERR_ERR4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

ERR4 - Error In Channel 4 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR4 - Error In Channel 4 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR4 [2/5]

#define DMA_ERR_ERR4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

ERR4 - Error In Channel 4 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR4 - Error In Channel 4 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR4 [3/5]

#define DMA_ERR_ERR4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

ERR4 - Error In Channel 4 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR4 [4/5]

#define DMA_ERR_ERR4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

ERR4 - Error In Channel 4 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR4 [5/5]

#define DMA_ERR_ERR4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)

ERR4 - Error In Channel 4 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR5 [1/5]

#define DMA_ERR_ERR5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

ERR5 - Error In Channel 5 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR5 - Error In Channel 5 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR5 [2/5]

#define DMA_ERR_ERR5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

ERR5 - Error In Channel 5 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR5 - Error In Channel 5 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR5 [3/5]

#define DMA_ERR_ERR5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

ERR5 - Error In Channel 5 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR5 [4/5]

#define DMA_ERR_ERR5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

ERR5 - Error In Channel 5 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR5 [5/5]

#define DMA_ERR_ERR5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)

ERR5 - Error In Channel 5 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR6 [1/5]

#define DMA_ERR_ERR6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

ERR6 - Error In Channel 6 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR6 - Error In Channel 6 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR6 [2/5]

#define DMA_ERR_ERR6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

ERR6 - Error In Channel 6 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR6 - Error In Channel 6 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR6 [3/5]

#define DMA_ERR_ERR6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

ERR6 - Error In Channel 6 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR6 [4/5]

#define DMA_ERR_ERR6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

ERR6 - Error In Channel 6 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR6 [5/5]

#define DMA_ERR_ERR6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)

ERR6 - Error In Channel 6 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR7 [1/5]

#define DMA_ERR_ERR7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

ERR7 - Error In Channel 7 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR7 - Error In Channel 7 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR7 [2/5]

#define DMA_ERR_ERR7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

ERR7 - Error In Channel 7 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR7 - Error In Channel 7 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR7 [3/5]

#define DMA_ERR_ERR7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

ERR7 - Error In Channel 7 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR7 [4/5]

#define DMA_ERR_ERR7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

ERR7 - Error In Channel 7 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR7 [5/5]

#define DMA_ERR_ERR7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)

ERR7 - Error In Channel 7 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR8 [1/5]

#define DMA_ERR_ERR8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

ERR8 - Error In Channel 8 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR8 - Error In Channel 8 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR8 [2/5]

#define DMA_ERR_ERR8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

ERR8 - Error In Channel 8 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR8 - Error In Channel 8 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR8 [3/5]

#define DMA_ERR_ERR8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

ERR8 - Error In Channel 8 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR8 [4/5]

#define DMA_ERR_ERR8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

ERR8 - Error In Channel 8 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR8 [5/5]

#define DMA_ERR_ERR8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)

ERR8 - Error In Channel 8 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR9 [1/5]

#define DMA_ERR_ERR9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

ERR9 - Error In Channel 9 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR9 - Error In Channel 9 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR9 [2/5]

#define DMA_ERR_ERR9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

ERR9 - Error In Channel 9 0b0..An error in the corresponding channel has not occurred 0b1..An error in the corresponding channel has occurred

ERR9 - Error In Channel 9 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR9 [3/5]

#define DMA_ERR_ERR9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

ERR9 - Error In Channel 9 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR9 [4/5]

#define DMA_ERR_ERR9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

ERR9 - Error In Channel 9 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ERR_ERR9 [5/5]

#define DMA_ERR_ERR9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)

ERR9 - Error In Channel 9 0b0..An error in this channel has not occurred 0b1..An error in this channel has occurred

◆ DMA_ES_CPE [1/5]

#define DMA_ES_CPE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

CPE - Channel Priority Error 0b0..No channel priority error 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.

CPE - Channel Priority Error 0b0..No channel priority error 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.

◆ DMA_ES_CPE [2/5]

#define DMA_ES_CPE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

CPE - Channel Priority Error 0b0..No channel priority error 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.

CPE - Channel Priority Error 0b0..No channel priority error 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.

◆ DMA_ES_CPE [3/5]

#define DMA_ES_CPE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

CPE - Channel Priority Error 0b0..No channel priority error 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.

◆ DMA_ES_CPE [4/5]

#define DMA_ES_CPE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

CPE - Channel Priority Error 0b0..No channel priority error 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.

◆ DMA_ES_CPE [5/5]

#define DMA_ES_CPE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)

CPE - Channel Priority Error 0b0..No channel priority error 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.

◆ DMA_ES_DAE [1/5]

#define DMA_ES_DAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

DAE - Destination Address Error 0b0..No destination address configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DAE [2/5]

#define DMA_ES_DAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

DAE - Destination Address Error 0b0..No destination address configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DAE [3/5]

#define DMA_ES_DAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

DAE - Destination Address Error 0b0..No destination address configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DAE [4/5]

#define DMA_ES_DAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

DAE - Destination Address Error 0b0..No destination address configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DAE [5/5]

#define DMA_ES_DAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)

DAE - Destination Address Error 0b0..No destination address configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DBE [1/5]

#define DMA_ES_DBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

DBE - Destination Bus Error 0b0..No destination bus error 0b1..The last recorded error was a bus error on a destination write

◆ DMA_ES_DBE [2/5]

#define DMA_ES_DBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

DBE - Destination Bus Error 0b0..No destination bus error 0b1..The last recorded error was a bus error on a destination write

◆ DMA_ES_DBE [3/5]

#define DMA_ES_DBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

DBE - Destination Bus Error 0b0..No destination bus error 0b1..The last recorded error was a bus error on a destination write

◆ DMA_ES_DBE [4/5]

#define DMA_ES_DBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

DBE - Destination Bus Error 0b0..No destination bus error 0b1..The last recorded error was a bus error on a destination write

◆ DMA_ES_DBE [5/5]

#define DMA_ES_DBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)

DBE - Destination Bus Error 0b0..No destination bus error 0b1..The last recorded error was a bus error on a destination write

◆ DMA_ES_DOE [1/5]

#define DMA_ES_DOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

DOE - Destination Offset Error 0b0..No destination offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DOE [2/5]

#define DMA_ES_DOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

DOE - Destination Offset Error 0b0..No destination offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DOE [3/5]

#define DMA_ES_DOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

DOE - Destination Offset Error 0b0..No destination offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DOE [4/5]

#define DMA_ES_DOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

DOE - Destination Offset Error 0b0..No destination offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_DOE [5/5]

#define DMA_ES_DOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)

DOE - Destination Offset Error 0b0..No destination offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].

◆ DMA_ES_ECX [1/5]

#define DMA_ES_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

ECX - Transfer Canceled 0b0..No canceled transfers 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input

◆ DMA_ES_ECX [2/5]

#define DMA_ES_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

ECX - Transfer Canceled 0b0..No canceled transfers 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input

◆ DMA_ES_ECX [3/5]

#define DMA_ES_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

ECX - Transfer Canceled 0b0..No canceled transfers 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input

◆ DMA_ES_ECX [4/5]

#define DMA_ES_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

ECX - Transfer Canceled 0b0..No canceled transfers 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input

◆ DMA_ES_ECX [5/5]

#define DMA_ES_ECX ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)

ECX - Transfer Canceled 0b0..No canceled transfers 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input

◆ DMA_ES_GPE [1/3]

#define DMA_ES_GPE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

GPE - Group Priority Error 0b0..No group priority error 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.

◆ DMA_ES_GPE [2/3]

#define DMA_ES_GPE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

GPE - Group Priority Error 0b0..No group priority error 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.

◆ DMA_ES_GPE [3/3]

#define DMA_ES_GPE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)

GPE - Group Priority Error 0b0..No group priority error 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.

◆ DMA_ES_NCE [1/5]

#define DMA_ES_NCE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

NCE - NBYTES/CITER Configuration Error 0b0..No NBYTES/CITER configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]

◆ DMA_ES_NCE [2/5]

#define DMA_ES_NCE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

NCE - NBYTES/CITER Configuration Error 0b0..No NBYTES/CITER configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]

◆ DMA_ES_NCE [3/5]

#define DMA_ES_NCE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

NCE - NBYTES/CITER Configuration Error 0b0..No NBYTES/CITER configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]

◆ DMA_ES_NCE [4/5]

#define DMA_ES_NCE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

NCE - NBYTES/CITER Configuration Error 0b0..No NBYTES/CITER configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]

◆ DMA_ES_NCE [5/5]

#define DMA_ES_NCE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)

NCE - NBYTES/CITER Configuration Error 0b0..No NBYTES/CITER configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]

◆ DMA_ES_SAE [1/5]

#define DMA_ES_SAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

SAE - Source Address Error 0b0..No source address configuration error. 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SAE [2/5]

#define DMA_ES_SAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

SAE - Source Address Error 0b0..No source address configuration error. 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SAE [3/5]

#define DMA_ES_SAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

SAE - Source Address Error 0b0..No source address configuration error. 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SAE [4/5]

#define DMA_ES_SAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

SAE - Source Address Error 0b0..No source address configuration error. 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SAE [5/5]

#define DMA_ES_SAE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)

SAE - Source Address Error 0b0..No source address configuration error. 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SBE [1/5]

#define DMA_ES_SBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

SBE - Source Bus Error 0b0..No source bus error 0b1..The last recorded error was a bus error on a source read

◆ DMA_ES_SBE [2/5]

#define DMA_ES_SBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

SBE - Source Bus Error 0b0..No source bus error 0b1..The last recorded error was a bus error on a source read

◆ DMA_ES_SBE [3/5]

#define DMA_ES_SBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

SBE - Source Bus Error 0b0..No source bus error 0b1..The last recorded error was a bus error on a source read

◆ DMA_ES_SBE [4/5]

#define DMA_ES_SBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

SBE - Source Bus Error 0b0..No source bus error 0b1..The last recorded error was a bus error on a source read

◆ DMA_ES_SBE [5/5]

#define DMA_ES_SBE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)

SBE - Source Bus Error 0b0..No source bus error 0b1..The last recorded error was a bus error on a source read

◆ DMA_ES_SGE [1/5]

#define DMA_ES_SGE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

SGE - Scatter/Gather Configuration Error 0b0..No scatter/gather configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.

◆ DMA_ES_SGE [2/5]

#define DMA_ES_SGE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

SGE - Scatter/Gather Configuration Error 0b0..No scatter/gather configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.

◆ DMA_ES_SGE [3/5]

#define DMA_ES_SGE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

SGE - Scatter/Gather Configuration Error 0b0..No scatter/gather configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.

◆ DMA_ES_SGE [4/5]

#define DMA_ES_SGE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

SGE - Scatter/Gather Configuration Error 0b0..No scatter/gather configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.

◆ DMA_ES_SGE [5/5]

#define DMA_ES_SGE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)

SGE - Scatter/Gather Configuration Error 0b0..No scatter/gather configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.

◆ DMA_ES_SOE [1/5]

#define DMA_ES_SOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

SOE - Source Offset Error 0b0..No source offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SOE [2/5]

#define DMA_ES_SOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

SOE - Source Offset Error 0b0..No source offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SOE [3/5]

#define DMA_ES_SOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

SOE - Source Offset Error 0b0..No source offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SOE [4/5]

#define DMA_ES_SOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

SOE - Source Offset Error 0b0..No source offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_SOE [5/5]

#define DMA_ES_SOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)

SOE - Source Offset Error 0b0..No source offset configuration error 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].

◆ DMA_ES_VLD [1/5]

#define DMA_ES_VLD ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

VLD 0b0..No ERR bits are set 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared

VLD 0b0..No ERR bits are set. 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.

◆ DMA_ES_VLD [2/5]

#define DMA_ES_VLD ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

VLD 0b0..No ERR bits are set 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared

VLD 0b0..No ERR bits are set. 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.

◆ DMA_ES_VLD [3/5]

#define DMA_ES_VLD ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

VLD 0b0..No ERR bits are set. 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.

◆ DMA_ES_VLD [4/5]

#define DMA_ES_VLD ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

VLD 0b0..No ERR bits are set. 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.

◆ DMA_ES_VLD [5/5]

#define DMA_ES_VLD ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)

VLD 0b0..No ERR bits are set. 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.

◆ DMA_HRS_HRS0 [1/5]

#define DMA_HRS_HRS0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

HRS0 - Hardware Request Status Channel 0 0b0..A hardware service request for channel 0 is not present 0b1..A hardware service request for channel 0 is present

◆ DMA_HRS_HRS0 [2/5]

#define DMA_HRS_HRS0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

HRS0 - Hardware Request Status Channel 0 0b0..A hardware service request for channel 0 is not present 0b1..A hardware service request for channel 0 is present

◆ DMA_HRS_HRS0 [3/5]

#define DMA_HRS_HRS0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

HRS0 - Hardware Request Status Channel 0 0b0..A hardware service request for channel 0 is not present 0b1..A hardware service request for channel 0 is present

◆ DMA_HRS_HRS0 [4/5]

#define DMA_HRS_HRS0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

HRS0 - Hardware Request Status Channel 0 0b0..A hardware service request for channel 0 is not present 0b1..A hardware service request for channel 0 is present

◆ DMA_HRS_HRS0 [5/5]

#define DMA_HRS_HRS0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)

HRS0 - Hardware Request Status Channel 0 0b0..A hardware service request for channel 0 is not present 0b1..A hardware service request for channel 0 is present

◆ DMA_HRS_HRS1 [1/5]

#define DMA_HRS_HRS1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

HRS1 - Hardware Request Status Channel 1 0b0..A hardware service request for channel 1 is not present 0b1..A hardware service request for channel 1 is present

◆ DMA_HRS_HRS1 [2/5]

#define DMA_HRS_HRS1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

HRS1 - Hardware Request Status Channel 1 0b0..A hardware service request for channel 1 is not present 0b1..A hardware service request for channel 1 is present

◆ DMA_HRS_HRS1 [3/5]

#define DMA_HRS_HRS1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

HRS1 - Hardware Request Status Channel 1 0b0..A hardware service request for channel 1 is not present 0b1..A hardware service request for channel 1 is present

◆ DMA_HRS_HRS1 [4/5]

#define DMA_HRS_HRS1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

HRS1 - Hardware Request Status Channel 1 0b0..A hardware service request for channel 1 is not present 0b1..A hardware service request for channel 1 is present

◆ DMA_HRS_HRS1 [5/5]

#define DMA_HRS_HRS1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)

HRS1 - Hardware Request Status Channel 1 0b0..A hardware service request for channel 1 is not present 0b1..A hardware service request for channel 1 is present

◆ DMA_HRS_HRS10 [1/5]

#define DMA_HRS_HRS10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

HRS10 - Hardware Request Status Channel 10 0b0..A hardware service request for channel 10 is not present 0b1..A hardware service request for channel 10 is present

◆ DMA_HRS_HRS10 [2/5]

#define DMA_HRS_HRS10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

HRS10 - Hardware Request Status Channel 10 0b0..A hardware service request for channel 10 is not present 0b1..A hardware service request for channel 10 is present

◆ DMA_HRS_HRS10 [3/5]

#define DMA_HRS_HRS10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

HRS10 - Hardware Request Status Channel 10 0b0..A hardware service request for channel 10 is not present 0b1..A hardware service request for channel 10 is present

◆ DMA_HRS_HRS10 [4/5]

#define DMA_HRS_HRS10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

HRS10 - Hardware Request Status Channel 10 0b0..A hardware service request for channel 10 is not present 0b1..A hardware service request for channel 10 is present

◆ DMA_HRS_HRS10 [5/5]

#define DMA_HRS_HRS10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)

HRS10 - Hardware Request Status Channel 10 0b0..A hardware service request for channel 10 is not present 0b1..A hardware service request for channel 10 is present

◆ DMA_HRS_HRS11 [1/5]

#define DMA_HRS_HRS11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

HRS11 - Hardware Request Status Channel 11 0b0..A hardware service request for channel 11 is not present 0b1..A hardware service request for channel 11 is present

◆ DMA_HRS_HRS11 [2/5]

#define DMA_HRS_HRS11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

HRS11 - Hardware Request Status Channel 11 0b0..A hardware service request for channel 11 is not present 0b1..A hardware service request for channel 11 is present

◆ DMA_HRS_HRS11 [3/5]

#define DMA_HRS_HRS11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

HRS11 - Hardware Request Status Channel 11 0b0..A hardware service request for channel 11 is not present 0b1..A hardware service request for channel 11 is present

◆ DMA_HRS_HRS11 [4/5]

#define DMA_HRS_HRS11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

HRS11 - Hardware Request Status Channel 11 0b0..A hardware service request for channel 11 is not present 0b1..A hardware service request for channel 11 is present

◆ DMA_HRS_HRS11 [5/5]

#define DMA_HRS_HRS11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)

HRS11 - Hardware Request Status Channel 11 0b0..A hardware service request for channel 11 is not present 0b1..A hardware service request for channel 11 is present

◆ DMA_HRS_HRS12 [1/5]

#define DMA_HRS_HRS12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

HRS12 - Hardware Request Status Channel 12 0b0..A hardware service request for channel 12 is not present 0b1..A hardware service request for channel 12 is present

◆ DMA_HRS_HRS12 [2/5]

#define DMA_HRS_HRS12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

HRS12 - Hardware Request Status Channel 12 0b0..A hardware service request for channel 12 is not present 0b1..A hardware service request for channel 12 is present

◆ DMA_HRS_HRS12 [3/5]

#define DMA_HRS_HRS12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

HRS12 - Hardware Request Status Channel 12 0b0..A hardware service request for channel 12 is not present 0b1..A hardware service request for channel 12 is present

◆ DMA_HRS_HRS12 [4/5]

#define DMA_HRS_HRS12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

HRS12 - Hardware Request Status Channel 12 0b0..A hardware service request for channel 12 is not present 0b1..A hardware service request for channel 12 is present

◆ DMA_HRS_HRS12 [5/5]

#define DMA_HRS_HRS12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)

HRS12 - Hardware Request Status Channel 12 0b0..A hardware service request for channel 12 is not present 0b1..A hardware service request for channel 12 is present

◆ DMA_HRS_HRS13 [1/5]

#define DMA_HRS_HRS13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

HRS13 - Hardware Request Status Channel 13 0b0..A hardware service request for channel 13 is not present 0b1..A hardware service request for channel 13 is present

◆ DMA_HRS_HRS13 [2/5]

#define DMA_HRS_HRS13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

HRS13 - Hardware Request Status Channel 13 0b0..A hardware service request for channel 13 is not present 0b1..A hardware service request for channel 13 is present

◆ DMA_HRS_HRS13 [3/5]

#define DMA_HRS_HRS13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

HRS13 - Hardware Request Status Channel 13 0b0..A hardware service request for channel 13 is not present 0b1..A hardware service request for channel 13 is present

◆ DMA_HRS_HRS13 [4/5]

#define DMA_HRS_HRS13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

HRS13 - Hardware Request Status Channel 13 0b0..A hardware service request for channel 13 is not present 0b1..A hardware service request for channel 13 is present

◆ DMA_HRS_HRS13 [5/5]

#define DMA_HRS_HRS13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)

HRS13 - Hardware Request Status Channel 13 0b0..A hardware service request for channel 13 is not present 0b1..A hardware service request for channel 13 is present

◆ DMA_HRS_HRS14 [1/5]

#define DMA_HRS_HRS14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

HRS14 - Hardware Request Status Channel 14 0b0..A hardware service request for channel 14 is not present 0b1..A hardware service request for channel 14 is present

◆ DMA_HRS_HRS14 [2/5]

#define DMA_HRS_HRS14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

HRS14 - Hardware Request Status Channel 14 0b0..A hardware service request for channel 14 is not present 0b1..A hardware service request for channel 14 is present

◆ DMA_HRS_HRS14 [3/5]

#define DMA_HRS_HRS14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

HRS14 - Hardware Request Status Channel 14 0b0..A hardware service request for channel 14 is not present 0b1..A hardware service request for channel 14 is present

◆ DMA_HRS_HRS14 [4/5]

#define DMA_HRS_HRS14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

HRS14 - Hardware Request Status Channel 14 0b0..A hardware service request for channel 14 is not present 0b1..A hardware service request for channel 14 is present

◆ DMA_HRS_HRS14 [5/5]

#define DMA_HRS_HRS14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)

HRS14 - Hardware Request Status Channel 14 0b0..A hardware service request for channel 14 is not present 0b1..A hardware service request for channel 14 is present

◆ DMA_HRS_HRS15 [1/5]

#define DMA_HRS_HRS15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

HRS15 - Hardware Request Status Channel 15 0b0..A hardware service request for channel 15 is not present 0b1..A hardware service request for channel 15 is present

◆ DMA_HRS_HRS15 [2/5]

#define DMA_HRS_HRS15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

HRS15 - Hardware Request Status Channel 15 0b0..A hardware service request for channel 15 is not present 0b1..A hardware service request for channel 15 is present

◆ DMA_HRS_HRS15 [3/5]

#define DMA_HRS_HRS15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

HRS15 - Hardware Request Status Channel 15 0b0..A hardware service request for channel 15 is not present 0b1..A hardware service request for channel 15 is present

◆ DMA_HRS_HRS15 [4/5]

#define DMA_HRS_HRS15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

HRS15 - Hardware Request Status Channel 15 0b0..A hardware service request for channel 15 is not present 0b1..A hardware service request for channel 15 is present

◆ DMA_HRS_HRS15 [5/5]

#define DMA_HRS_HRS15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)

HRS15 - Hardware Request Status Channel 15 0b0..A hardware service request for channel 15 is not present 0b1..A hardware service request for channel 15 is present

◆ DMA_HRS_HRS16 [1/3]

#define DMA_HRS_HRS16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

HRS16 - Hardware Request Status Channel 16 0b0..A hardware service request for channel 16 is not present 0b1..A hardware service request for channel 16 is present

◆ DMA_HRS_HRS16 [2/3]

#define DMA_HRS_HRS16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

HRS16 - Hardware Request Status Channel 16 0b0..A hardware service request for channel 16 is not present 0b1..A hardware service request for channel 16 is present

◆ DMA_HRS_HRS16 [3/3]

#define DMA_HRS_HRS16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)

HRS16 - Hardware Request Status Channel 16 0b0..A hardware service request for channel 16 is not present 0b1..A hardware service request for channel 16 is present

◆ DMA_HRS_HRS17 [1/3]

#define DMA_HRS_HRS17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

HRS17 - Hardware Request Status Channel 17 0b0..A hardware service request for channel 17 is not present 0b1..A hardware service request for channel 17 is present

◆ DMA_HRS_HRS17 [2/3]

#define DMA_HRS_HRS17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

HRS17 - Hardware Request Status Channel 17 0b0..A hardware service request for channel 17 is not present 0b1..A hardware service request for channel 17 is present

◆ DMA_HRS_HRS17 [3/3]

#define DMA_HRS_HRS17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)

HRS17 - Hardware Request Status Channel 17 0b0..A hardware service request for channel 17 is not present 0b1..A hardware service request for channel 17 is present

◆ DMA_HRS_HRS18 [1/3]

#define DMA_HRS_HRS18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

HRS18 - Hardware Request Status Channel 18 0b0..A hardware service request for channel 18 is not present 0b1..A hardware service request for channel 18 is present

◆ DMA_HRS_HRS18 [2/3]

#define DMA_HRS_HRS18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

HRS18 - Hardware Request Status Channel 18 0b0..A hardware service request for channel 18 is not present 0b1..A hardware service request for channel 18 is present

◆ DMA_HRS_HRS18 [3/3]

#define DMA_HRS_HRS18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)

HRS18 - Hardware Request Status Channel 18 0b0..A hardware service request for channel 18 is not present 0b1..A hardware service request for channel 18 is present

◆ DMA_HRS_HRS19 [1/3]

#define DMA_HRS_HRS19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

HRS19 - Hardware Request Status Channel 19 0b0..A hardware service request for channel 19 is not present 0b1..A hardware service request for channel 19 is present

◆ DMA_HRS_HRS19 [2/3]

#define DMA_HRS_HRS19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

HRS19 - Hardware Request Status Channel 19 0b0..A hardware service request for channel 19 is not present 0b1..A hardware service request for channel 19 is present

◆ DMA_HRS_HRS19 [3/3]

#define DMA_HRS_HRS19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)

HRS19 - Hardware Request Status Channel 19 0b0..A hardware service request for channel 19 is not present 0b1..A hardware service request for channel 19 is present

◆ DMA_HRS_HRS2 [1/5]

#define DMA_HRS_HRS2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

HRS2 - Hardware Request Status Channel 2 0b0..A hardware service request for channel 2 is not present 0b1..A hardware service request for channel 2 is present

◆ DMA_HRS_HRS2 [2/5]

#define DMA_HRS_HRS2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

HRS2 - Hardware Request Status Channel 2 0b0..A hardware service request for channel 2 is not present 0b1..A hardware service request for channel 2 is present

◆ DMA_HRS_HRS2 [3/5]

#define DMA_HRS_HRS2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

HRS2 - Hardware Request Status Channel 2 0b0..A hardware service request for channel 2 is not present 0b1..A hardware service request for channel 2 is present

◆ DMA_HRS_HRS2 [4/5]

#define DMA_HRS_HRS2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

HRS2 - Hardware Request Status Channel 2 0b0..A hardware service request for channel 2 is not present 0b1..A hardware service request for channel 2 is present

◆ DMA_HRS_HRS2 [5/5]

#define DMA_HRS_HRS2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)

HRS2 - Hardware Request Status Channel 2 0b0..A hardware service request for channel 2 is not present 0b1..A hardware service request for channel 2 is present

◆ DMA_HRS_HRS20 [1/3]

#define DMA_HRS_HRS20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

HRS20 - Hardware Request Status Channel 20 0b0..A hardware service request for channel 20 is not present 0b1..A hardware service request for channel 20 is present

◆ DMA_HRS_HRS20 [2/3]

#define DMA_HRS_HRS20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

HRS20 - Hardware Request Status Channel 20 0b0..A hardware service request for channel 20 is not present 0b1..A hardware service request for channel 20 is present

◆ DMA_HRS_HRS20 [3/3]

#define DMA_HRS_HRS20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)

HRS20 - Hardware Request Status Channel 20 0b0..A hardware service request for channel 20 is not present 0b1..A hardware service request for channel 20 is present

◆ DMA_HRS_HRS21 [1/3]

#define DMA_HRS_HRS21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

HRS21 - Hardware Request Status Channel 21 0b0..A hardware service request for channel 21 is not present 0b1..A hardware service request for channel 21 is present

◆ DMA_HRS_HRS21 [2/3]

#define DMA_HRS_HRS21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

HRS21 - Hardware Request Status Channel 21 0b0..A hardware service request for channel 21 is not present 0b1..A hardware service request for channel 21 is present

◆ DMA_HRS_HRS21 [3/3]

#define DMA_HRS_HRS21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)

HRS21 - Hardware Request Status Channel 21 0b0..A hardware service request for channel 21 is not present 0b1..A hardware service request for channel 21 is present

◆ DMA_HRS_HRS22 [1/3]

#define DMA_HRS_HRS22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

HRS22 - Hardware Request Status Channel 22 0b0..A hardware service request for channel 22 is not present 0b1..A hardware service request for channel 22 is present

◆ DMA_HRS_HRS22 [2/3]

#define DMA_HRS_HRS22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

HRS22 - Hardware Request Status Channel 22 0b0..A hardware service request for channel 22 is not present 0b1..A hardware service request for channel 22 is present

◆ DMA_HRS_HRS22 [3/3]

#define DMA_HRS_HRS22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)

HRS22 - Hardware Request Status Channel 22 0b0..A hardware service request for channel 22 is not present 0b1..A hardware service request for channel 22 is present

◆ DMA_HRS_HRS23 [1/3]

#define DMA_HRS_HRS23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

HRS23 - Hardware Request Status Channel 23 0b0..A hardware service request for channel 23 is not present 0b1..A hardware service request for channel 23 is present

◆ DMA_HRS_HRS23 [2/3]

#define DMA_HRS_HRS23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

HRS23 - Hardware Request Status Channel 23 0b0..A hardware service request for channel 23 is not present 0b1..A hardware service request for channel 23 is present

◆ DMA_HRS_HRS23 [3/3]

#define DMA_HRS_HRS23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)

HRS23 - Hardware Request Status Channel 23 0b0..A hardware service request for channel 23 is not present 0b1..A hardware service request for channel 23 is present

◆ DMA_HRS_HRS24 [1/3]

#define DMA_HRS_HRS24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

HRS24 - Hardware Request Status Channel 24 0b0..A hardware service request for channel 24 is not present 0b1..A hardware service request for channel 24 is present

◆ DMA_HRS_HRS24 [2/3]

#define DMA_HRS_HRS24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

HRS24 - Hardware Request Status Channel 24 0b0..A hardware service request for channel 24 is not present 0b1..A hardware service request for channel 24 is present

◆ DMA_HRS_HRS24 [3/3]

#define DMA_HRS_HRS24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)

HRS24 - Hardware Request Status Channel 24 0b0..A hardware service request for channel 24 is not present 0b1..A hardware service request for channel 24 is present

◆ DMA_HRS_HRS25 [1/3]

#define DMA_HRS_HRS25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

HRS25 - Hardware Request Status Channel 25 0b0..A hardware service request for channel 25 is not present 0b1..A hardware service request for channel 25 is present

◆ DMA_HRS_HRS25 [2/3]

#define DMA_HRS_HRS25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

HRS25 - Hardware Request Status Channel 25 0b0..A hardware service request for channel 25 is not present 0b1..A hardware service request for channel 25 is present

◆ DMA_HRS_HRS25 [3/3]

#define DMA_HRS_HRS25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)

HRS25 - Hardware Request Status Channel 25 0b0..A hardware service request for channel 25 is not present 0b1..A hardware service request for channel 25 is present

◆ DMA_HRS_HRS26 [1/3]

#define DMA_HRS_HRS26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

HRS26 - Hardware Request Status Channel 26 0b0..A hardware service request for channel 26 is not present 0b1..A hardware service request for channel 26 is present

◆ DMA_HRS_HRS26 [2/3]

#define DMA_HRS_HRS26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

HRS26 - Hardware Request Status Channel 26 0b0..A hardware service request for channel 26 is not present 0b1..A hardware service request for channel 26 is present

◆ DMA_HRS_HRS26 [3/3]

#define DMA_HRS_HRS26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)

HRS26 - Hardware Request Status Channel 26 0b0..A hardware service request for channel 26 is not present 0b1..A hardware service request for channel 26 is present

◆ DMA_HRS_HRS27 [1/3]

#define DMA_HRS_HRS27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

HRS27 - Hardware Request Status Channel 27 0b0..A hardware service request for channel 27 is not present 0b1..A hardware service request for channel 27 is present

◆ DMA_HRS_HRS27 [2/3]

#define DMA_HRS_HRS27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

HRS27 - Hardware Request Status Channel 27 0b0..A hardware service request for channel 27 is not present 0b1..A hardware service request for channel 27 is present

◆ DMA_HRS_HRS27 [3/3]

#define DMA_HRS_HRS27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)

HRS27 - Hardware Request Status Channel 27 0b0..A hardware service request for channel 27 is not present 0b1..A hardware service request for channel 27 is present

◆ DMA_HRS_HRS28 [1/3]

#define DMA_HRS_HRS28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

HRS28 - Hardware Request Status Channel 28 0b0..A hardware service request for channel 28 is not present 0b1..A hardware service request for channel 28 is present

◆ DMA_HRS_HRS28 [2/3]

#define DMA_HRS_HRS28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

HRS28 - Hardware Request Status Channel 28 0b0..A hardware service request for channel 28 is not present 0b1..A hardware service request for channel 28 is present

◆ DMA_HRS_HRS28 [3/3]

#define DMA_HRS_HRS28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)

HRS28 - Hardware Request Status Channel 28 0b0..A hardware service request for channel 28 is not present 0b1..A hardware service request for channel 28 is present

◆ DMA_HRS_HRS29 [1/3]

#define DMA_HRS_HRS29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

HRS29 - Hardware Request Status Channel 29 0b0..A hardware service request for channel 29 is not preset 0b1..A hardware service request for channel 29 is present

◆ DMA_HRS_HRS29 [2/3]

#define DMA_HRS_HRS29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

HRS29 - Hardware Request Status Channel 29 0b0..A hardware service request for channel 29 is not preset 0b1..A hardware service request for channel 29 is present

◆ DMA_HRS_HRS29 [3/3]

#define DMA_HRS_HRS29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)

HRS29 - Hardware Request Status Channel 29 0b0..A hardware service request for channel 29 is not preset 0b1..A hardware service request for channel 29 is present

◆ DMA_HRS_HRS3 [1/5]

#define DMA_HRS_HRS3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

HRS3 - Hardware Request Status Channel 3 0b0..A hardware service request for channel 3 is not present 0b1..A hardware service request for channel 3 is present

◆ DMA_HRS_HRS3 [2/5]

#define DMA_HRS_HRS3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

HRS3 - Hardware Request Status Channel 3 0b0..A hardware service request for channel 3 is not present 0b1..A hardware service request for channel 3 is present

◆ DMA_HRS_HRS3 [3/5]

#define DMA_HRS_HRS3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

HRS3 - Hardware Request Status Channel 3 0b0..A hardware service request for channel 3 is not present 0b1..A hardware service request for channel 3 is present

◆ DMA_HRS_HRS3 [4/5]

#define DMA_HRS_HRS3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

HRS3 - Hardware Request Status Channel 3 0b0..A hardware service request for channel 3 is not present 0b1..A hardware service request for channel 3 is present

◆ DMA_HRS_HRS3 [5/5]

#define DMA_HRS_HRS3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)

HRS3 - Hardware Request Status Channel 3 0b0..A hardware service request for channel 3 is not present 0b1..A hardware service request for channel 3 is present

◆ DMA_HRS_HRS30 [1/3]

#define DMA_HRS_HRS30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

HRS30 - Hardware Request Status Channel 30 0b0..A hardware service request for channel 30 is not present 0b1..A hardware service request for for channel 30 is present

◆ DMA_HRS_HRS30 [2/3]

#define DMA_HRS_HRS30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

HRS30 - Hardware Request Status Channel 30 0b0..A hardware service request for channel 30 is not present 0b1..A hardware service request for for channel 30 is present

◆ DMA_HRS_HRS30 [3/3]

#define DMA_HRS_HRS30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)

HRS30 - Hardware Request Status Channel 30 0b0..A hardware service request for channel 30 is not present 0b1..A hardware service request for for channel 30 is present

◆ DMA_HRS_HRS31 [1/3]

#define DMA_HRS_HRS31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

HRS31 - Hardware Request Status Channel 31 0b0..A hardware service request for channel 31 is not present 0b1..A hardware service request for channel 31 is present

◆ DMA_HRS_HRS31 [2/3]

#define DMA_HRS_HRS31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

HRS31 - Hardware Request Status Channel 31 0b0..A hardware service request for channel 31 is not present 0b1..A hardware service request for channel 31 is present

◆ DMA_HRS_HRS31 [3/3]

#define DMA_HRS_HRS31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)

HRS31 - Hardware Request Status Channel 31 0b0..A hardware service request for channel 31 is not present 0b1..A hardware service request for channel 31 is present

◆ DMA_HRS_HRS4 [1/5]

#define DMA_HRS_HRS4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

HRS4 - Hardware Request Status Channel 4 0b0..A hardware service request for channel 4 is not present 0b1..A hardware service request for channel 4 is present

◆ DMA_HRS_HRS4 [2/5]

#define DMA_HRS_HRS4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

HRS4 - Hardware Request Status Channel 4 0b0..A hardware service request for channel 4 is not present 0b1..A hardware service request for channel 4 is present

◆ DMA_HRS_HRS4 [3/5]

#define DMA_HRS_HRS4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

HRS4 - Hardware Request Status Channel 4 0b0..A hardware service request for channel 4 is not present 0b1..A hardware service request for channel 4 is present

◆ DMA_HRS_HRS4 [4/5]

#define DMA_HRS_HRS4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

HRS4 - Hardware Request Status Channel 4 0b0..A hardware service request for channel 4 is not present 0b1..A hardware service request for channel 4 is present

◆ DMA_HRS_HRS4 [5/5]

#define DMA_HRS_HRS4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)

HRS4 - Hardware Request Status Channel 4 0b0..A hardware service request for channel 4 is not present 0b1..A hardware service request for channel 4 is present

◆ DMA_HRS_HRS5 [1/5]

#define DMA_HRS_HRS5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

HRS5 - Hardware Request Status Channel 5 0b0..A hardware service request for channel 5 is not present 0b1..A hardware service request for channel 5 is present

◆ DMA_HRS_HRS5 [2/5]

#define DMA_HRS_HRS5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

HRS5 - Hardware Request Status Channel 5 0b0..A hardware service request for channel 5 is not present 0b1..A hardware service request for channel 5 is present

◆ DMA_HRS_HRS5 [3/5]

#define DMA_HRS_HRS5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

HRS5 - Hardware Request Status Channel 5 0b0..A hardware service request for channel 5 is not present 0b1..A hardware service request for channel 5 is present

◆ DMA_HRS_HRS5 [4/5]

#define DMA_HRS_HRS5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

HRS5 - Hardware Request Status Channel 5 0b0..A hardware service request for channel 5 is not present 0b1..A hardware service request for channel 5 is present

◆ DMA_HRS_HRS5 [5/5]

#define DMA_HRS_HRS5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)

HRS5 - Hardware Request Status Channel 5 0b0..A hardware service request for channel 5 is not present 0b1..A hardware service request for channel 5 is present

◆ DMA_HRS_HRS6 [1/5]

#define DMA_HRS_HRS6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

HRS6 - Hardware Request Status Channel 6 0b0..A hardware service request for channel 6 is not present 0b1..A hardware service request for channel 6 is present

◆ DMA_HRS_HRS6 [2/5]

#define DMA_HRS_HRS6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

HRS6 - Hardware Request Status Channel 6 0b0..A hardware service request for channel 6 is not present 0b1..A hardware service request for channel 6 is present

◆ DMA_HRS_HRS6 [3/5]

#define DMA_HRS_HRS6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

HRS6 - Hardware Request Status Channel 6 0b0..A hardware service request for channel 6 is not present 0b1..A hardware service request for channel 6 is present

◆ DMA_HRS_HRS6 [4/5]

#define DMA_HRS_HRS6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

HRS6 - Hardware Request Status Channel 6 0b0..A hardware service request for channel 6 is not present 0b1..A hardware service request for channel 6 is present

◆ DMA_HRS_HRS6 [5/5]

#define DMA_HRS_HRS6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)

HRS6 - Hardware Request Status Channel 6 0b0..A hardware service request for channel 6 is not present 0b1..A hardware service request for channel 6 is present

◆ DMA_HRS_HRS7 [1/5]

#define DMA_HRS_HRS7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

HRS7 - Hardware Request Status Channel 7 0b0..A hardware service request for channel 7 is not present 0b1..A hardware service request for channel 7 is present

◆ DMA_HRS_HRS7 [2/5]

#define DMA_HRS_HRS7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

HRS7 - Hardware Request Status Channel 7 0b0..A hardware service request for channel 7 is not present 0b1..A hardware service request for channel 7 is present

◆ DMA_HRS_HRS7 [3/5]

#define DMA_HRS_HRS7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

HRS7 - Hardware Request Status Channel 7 0b0..A hardware service request for channel 7 is not present 0b1..A hardware service request for channel 7 is present

◆ DMA_HRS_HRS7 [4/5]

#define DMA_HRS_HRS7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

HRS7 - Hardware Request Status Channel 7 0b0..A hardware service request for channel 7 is not present 0b1..A hardware service request for channel 7 is present

◆ DMA_HRS_HRS7 [5/5]

#define DMA_HRS_HRS7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)

HRS7 - Hardware Request Status Channel 7 0b0..A hardware service request for channel 7 is not present 0b1..A hardware service request for channel 7 is present

◆ DMA_HRS_HRS8 [1/5]

#define DMA_HRS_HRS8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

HRS8 - Hardware Request Status Channel 8 0b0..A hardware service request for channel 8 is not present 0b1..A hardware service request for channel 8 is present

◆ DMA_HRS_HRS8 [2/5]

#define DMA_HRS_HRS8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

HRS8 - Hardware Request Status Channel 8 0b0..A hardware service request for channel 8 is not present 0b1..A hardware service request for channel 8 is present

◆ DMA_HRS_HRS8 [3/5]

#define DMA_HRS_HRS8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

HRS8 - Hardware Request Status Channel 8 0b0..A hardware service request for channel 8 is not present 0b1..A hardware service request for channel 8 is present

◆ DMA_HRS_HRS8 [4/5]

#define DMA_HRS_HRS8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

HRS8 - Hardware Request Status Channel 8 0b0..A hardware service request for channel 8 is not present 0b1..A hardware service request for channel 8 is present

◆ DMA_HRS_HRS8 [5/5]

#define DMA_HRS_HRS8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)

HRS8 - Hardware Request Status Channel 8 0b0..A hardware service request for channel 8 is not present 0b1..A hardware service request for channel 8 is present

◆ DMA_HRS_HRS9 [1/5]

#define DMA_HRS_HRS9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

HRS9 - Hardware Request Status Channel 9 0b0..A hardware service request for channel 9 is not present 0b1..A hardware service request for channel 9 is present

◆ DMA_HRS_HRS9 [2/5]

#define DMA_HRS_HRS9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

HRS9 - Hardware Request Status Channel 9 0b0..A hardware service request for channel 9 is not present 0b1..A hardware service request for channel 9 is present

◆ DMA_HRS_HRS9 [3/5]

#define DMA_HRS_HRS9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

HRS9 - Hardware Request Status Channel 9 0b0..A hardware service request for channel 9 is not present 0b1..A hardware service request for channel 9 is present

◆ DMA_HRS_HRS9 [4/5]

#define DMA_HRS_HRS9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

HRS9 - Hardware Request Status Channel 9 0b0..A hardware service request for channel 9 is not present 0b1..A hardware service request for channel 9 is present

◆ DMA_HRS_HRS9 [5/5]

#define DMA_HRS_HRS9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)

HRS9 - Hardware Request Status Channel 9 0b0..A hardware service request for channel 9 is not present 0b1..A hardware service request for channel 9 is present

◆ DMA_INT_INT0 [1/5]

#define DMA_INT_INT0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

INT0 - Interrupt Request 0 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT0 [2/5]

#define DMA_INT_INT0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

INT0 - Interrupt Request 0 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT0 [3/5]

#define DMA_INT_INT0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

INT0 - Interrupt Request 0 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT0 [4/5]

#define DMA_INT_INT0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

INT0 - Interrupt Request 0 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT0 [5/5]

#define DMA_INT_INT0 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)

INT0 - Interrupt Request 0 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT1 [1/5]

#define DMA_INT_INT1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

INT1 - Interrupt Request 1 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT1 [2/5]

#define DMA_INT_INT1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

INT1 - Interrupt Request 1 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT1 [3/5]

#define DMA_INT_INT1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

INT1 - Interrupt Request 1 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT1 [4/5]

#define DMA_INT_INT1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

INT1 - Interrupt Request 1 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT1 [5/5]

#define DMA_INT_INT1 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)

INT1 - Interrupt Request 1 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT10 [1/5]

#define DMA_INT_INT10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

INT10 - Interrupt Request 10 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT10 [2/5]

#define DMA_INT_INT10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

INT10 - Interrupt Request 10 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT10 [3/5]

#define DMA_INT_INT10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

INT10 - Interrupt Request 10 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT10 [4/5]

#define DMA_INT_INT10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

INT10 - Interrupt Request 10 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT10 [5/5]

#define DMA_INT_INT10 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)

INT10 - Interrupt Request 10 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT11 [1/5]

#define DMA_INT_INT11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

INT11 - Interrupt Request 11 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT11 [2/5]

#define DMA_INT_INT11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

INT11 - Interrupt Request 11 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT11 [3/5]

#define DMA_INT_INT11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

INT11 - Interrupt Request 11 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT11 [4/5]

#define DMA_INT_INT11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

INT11 - Interrupt Request 11 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT11 [5/5]

#define DMA_INT_INT11 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)

INT11 - Interrupt Request 11 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT12 [1/5]

#define DMA_INT_INT12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

INT12 - Interrupt Request 12 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT12 [2/5]

#define DMA_INT_INT12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

INT12 - Interrupt Request 12 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT12 [3/5]

#define DMA_INT_INT12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

INT12 - Interrupt Request 12 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT12 [4/5]

#define DMA_INT_INT12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

INT12 - Interrupt Request 12 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT12 [5/5]

#define DMA_INT_INT12 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)

INT12 - Interrupt Request 12 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT13 [1/5]

#define DMA_INT_INT13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

INT13 - Interrupt Request 13 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT13 [2/5]

#define DMA_INT_INT13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

INT13 - Interrupt Request 13 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT13 [3/5]

#define DMA_INT_INT13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

INT13 - Interrupt Request 13 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT13 [4/5]

#define DMA_INT_INT13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

INT13 - Interrupt Request 13 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT13 [5/5]

#define DMA_INT_INT13 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)

INT13 - Interrupt Request 13 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT14 [1/5]

#define DMA_INT_INT14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

INT14 - Interrupt Request 14 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT14 [2/5]

#define DMA_INT_INT14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

INT14 - Interrupt Request 14 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT14 [3/5]

#define DMA_INT_INT14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

INT14 - Interrupt Request 14 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT14 [4/5]

#define DMA_INT_INT14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

INT14 - Interrupt Request 14 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT14 [5/5]

#define DMA_INT_INT14 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)

INT14 - Interrupt Request 14 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT15 [1/5]

#define DMA_INT_INT15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

INT15 - Interrupt Request 15 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT15 [2/5]

#define DMA_INT_INT15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

INT15 - Interrupt Request 15 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT15 [3/5]

#define DMA_INT_INT15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

INT15 - Interrupt Request 15 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT15 [4/5]

#define DMA_INT_INT15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

INT15 - Interrupt Request 15 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT15 [5/5]

#define DMA_INT_INT15 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)

INT15 - Interrupt Request 15 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT16 [1/3]

#define DMA_INT_INT16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

INT16 - Interrupt Request 16 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT16 [2/3]

#define DMA_INT_INT16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

INT16 - Interrupt Request 16 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT16 [3/3]

#define DMA_INT_INT16 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)

INT16 - Interrupt Request 16 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT17 [1/3]

#define DMA_INT_INT17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

INT17 - Interrupt Request 17 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT17 [2/3]

#define DMA_INT_INT17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

INT17 - Interrupt Request 17 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT17 [3/3]

#define DMA_INT_INT17 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)

INT17 - Interrupt Request 17 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT18 [1/3]

#define DMA_INT_INT18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

INT18 - Interrupt Request 18 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT18 [2/3]

#define DMA_INT_INT18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

INT18 - Interrupt Request 18 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT18 [3/3]

#define DMA_INT_INT18 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)

INT18 - Interrupt Request 18 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT19 [1/3]

#define DMA_INT_INT19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

INT19 - Interrupt Request 19 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT19 [2/3]

#define DMA_INT_INT19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

INT19 - Interrupt Request 19 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT19 [3/3]

#define DMA_INT_INT19 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)

INT19 - Interrupt Request 19 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT2 [1/5]

#define DMA_INT_INT2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

INT2 - Interrupt Request 2 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT2 [2/5]

#define DMA_INT_INT2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

INT2 - Interrupt Request 2 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT2 [3/5]

#define DMA_INT_INT2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

INT2 - Interrupt Request 2 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT2 [4/5]

#define DMA_INT_INT2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

INT2 - Interrupt Request 2 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT2 [5/5]

#define DMA_INT_INT2 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)

INT2 - Interrupt Request 2 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT20 [1/3]

#define DMA_INT_INT20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

INT20 - Interrupt Request 20 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT20 [2/3]

#define DMA_INT_INT20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

INT20 - Interrupt Request 20 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT20 [3/3]

#define DMA_INT_INT20 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)

INT20 - Interrupt Request 20 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT21 [1/3]

#define DMA_INT_INT21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

INT21 - Interrupt Request 21 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT21 [2/3]

#define DMA_INT_INT21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

INT21 - Interrupt Request 21 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT21 [3/3]

#define DMA_INT_INT21 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)

INT21 - Interrupt Request 21 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT22 [1/3]

#define DMA_INT_INT22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

INT22 - Interrupt Request 22 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT22 [2/3]

#define DMA_INT_INT22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

INT22 - Interrupt Request 22 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT22 [3/3]

#define DMA_INT_INT22 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)

INT22 - Interrupt Request 22 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT23 [1/3]

#define DMA_INT_INT23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

INT23 - Interrupt Request 23 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT23 [2/3]

#define DMA_INT_INT23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

INT23 - Interrupt Request 23 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT23 [3/3]

#define DMA_INT_INT23 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)

INT23 - Interrupt Request 23 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT24 [1/3]

#define DMA_INT_INT24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

INT24 - Interrupt Request 24 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT24 [2/3]

#define DMA_INT_INT24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

INT24 - Interrupt Request 24 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT24 [3/3]

#define DMA_INT_INT24 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)

INT24 - Interrupt Request 24 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT25 [1/3]

#define DMA_INT_INT25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

INT25 - Interrupt Request 25 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT25 [2/3]

#define DMA_INT_INT25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

INT25 - Interrupt Request 25 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT25 [3/3]

#define DMA_INT_INT25 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)

INT25 - Interrupt Request 25 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT26 [1/3]

#define DMA_INT_INT26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

INT26 - Interrupt Request 26 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT26 [2/3]

#define DMA_INT_INT26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

INT26 - Interrupt Request 26 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT26 [3/3]

#define DMA_INT_INT26 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)

INT26 - Interrupt Request 26 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT27 [1/3]

#define DMA_INT_INT27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

INT27 - Interrupt Request 27 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT27 [2/3]

#define DMA_INT_INT27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

INT27 - Interrupt Request 27 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT27 [3/3]

#define DMA_INT_INT27 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)

INT27 - Interrupt Request 27 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT28 [1/3]

#define DMA_INT_INT28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

INT28 - Interrupt Request 28 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT28 [2/3]

#define DMA_INT_INT28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

INT28 - Interrupt Request 28 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT28 [3/3]

#define DMA_INT_INT28 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)

INT28 - Interrupt Request 28 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT29 [1/3]

#define DMA_INT_INT29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

INT29 - Interrupt Request 29 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT29 [2/3]

#define DMA_INT_INT29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

INT29 - Interrupt Request 29 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT29 [3/3]

#define DMA_INT_INT29 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)

INT29 - Interrupt Request 29 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT3 [1/5]

#define DMA_INT_INT3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

INT3 - Interrupt Request 3 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT3 [2/5]

#define DMA_INT_INT3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

INT3 - Interrupt Request 3 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT3 [3/5]

#define DMA_INT_INT3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

INT3 - Interrupt Request 3 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT3 [4/5]

#define DMA_INT_INT3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

INT3 - Interrupt Request 3 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT3 [5/5]

#define DMA_INT_INT3 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)

INT3 - Interrupt Request 3 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT30 [1/3]

#define DMA_INT_INT30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

INT30 - Interrupt Request 30 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT30 [2/3]

#define DMA_INT_INT30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

INT30 - Interrupt Request 30 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT30 [3/3]

#define DMA_INT_INT30 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)

INT30 - Interrupt Request 30 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT31 [1/3]

#define DMA_INT_INT31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

INT31 - Interrupt Request 31 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT31 [2/3]

#define DMA_INT_INT31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

INT31 - Interrupt Request 31 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT31 [3/3]

#define DMA_INT_INT31 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)

INT31 - Interrupt Request 31 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT4 [1/5]

#define DMA_INT_INT4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

INT4 - Interrupt Request 4 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT4 [2/5]

#define DMA_INT_INT4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

INT4 - Interrupt Request 4 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT4 [3/5]

#define DMA_INT_INT4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

INT4 - Interrupt Request 4 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT4 [4/5]

#define DMA_INT_INT4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

INT4 - Interrupt Request 4 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT4 [5/5]

#define DMA_INT_INT4 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)

INT4 - Interrupt Request 4 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT5 [1/5]

#define DMA_INT_INT5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

INT5 - Interrupt Request 5 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT5 [2/5]

#define DMA_INT_INT5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

INT5 - Interrupt Request 5 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT5 [3/5]

#define DMA_INT_INT5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

INT5 - Interrupt Request 5 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT5 [4/5]

#define DMA_INT_INT5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

INT5 - Interrupt Request 5 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT5 [5/5]

#define DMA_INT_INT5 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)

INT5 - Interrupt Request 5 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT6 [1/5]

#define DMA_INT_INT6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

INT6 - Interrupt Request 6 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT6 [2/5]

#define DMA_INT_INT6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

INT6 - Interrupt Request 6 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT6 [3/5]

#define DMA_INT_INT6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

INT6 - Interrupt Request 6 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT6 [4/5]

#define DMA_INT_INT6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

INT6 - Interrupt Request 6 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT6 [5/5]

#define DMA_INT_INT6 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)

INT6 - Interrupt Request 6 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT7 [1/5]

#define DMA_INT_INT7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

INT7 - Interrupt Request 7 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT7 [2/5]

#define DMA_INT_INT7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

INT7 - Interrupt Request 7 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT7 [3/5]

#define DMA_INT_INT7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

INT7 - Interrupt Request 7 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT7 [4/5]

#define DMA_INT_INT7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

INT7 - Interrupt Request 7 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT7 [5/5]

#define DMA_INT_INT7 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)

INT7 - Interrupt Request 7 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT8 [1/5]

#define DMA_INT_INT8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

INT8 - Interrupt Request 8 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT8 [2/5]

#define DMA_INT_INT8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

INT8 - Interrupt Request 8 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT8 [3/5]

#define DMA_INT_INT8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

INT8 - Interrupt Request 8 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT8 [4/5]

#define DMA_INT_INT8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

INT8 - Interrupt Request 8 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT8 [5/5]

#define DMA_INT_INT8 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)

INT8 - Interrupt Request 8 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT9 [1/5]

#define DMA_INT_INT9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

INT9 - Interrupt Request 9 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT9 [2/5]

#define DMA_INT_INT9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

INT9 - Interrupt Request 9 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT9 [3/5]

#define DMA_INT_INT9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

INT9 - Interrupt Request 9 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT9 [4/5]

#define DMA_INT_INT9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

INT9 - Interrupt Request 9 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_INT_INT9 [5/5]

#define DMA_INT_INT9 ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)

INT9 - Interrupt Request 9 0b0..The interrupt request for corresponding channel is cleared 0b1..The interrupt request for corresponding channel is active

◆ DMA_NBYTES_MLOFFNO_DMLOE [1/5]

#define DMA_NBYTES_MLOFFNO_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFNO_DMLOE [2/5]

#define DMA_NBYTES_MLOFFNO_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFNO_DMLOE [3/5]

#define DMA_NBYTES_MLOFFNO_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFNO_DMLOE [4/5]

#define DMA_NBYTES_MLOFFNO_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFNO_DMLOE [5/5]

#define DMA_NBYTES_MLOFFNO_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFNO_SMLOE [1/5]

#define DMA_NBYTES_MLOFFNO_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFNO_SMLOE [2/5]

#define DMA_NBYTES_MLOFFNO_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFNO_SMLOE [3/5]

#define DMA_NBYTES_MLOFFNO_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFNO_SMLOE [4/5]

#define DMA_NBYTES_MLOFFNO_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFNO_SMLOE [5/5]

#define DMA_NBYTES_MLOFFNO_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFYES_DMLOE [1/5]

#define DMA_NBYTES_MLOFFYES_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFYES_DMLOE [2/5]

#define DMA_NBYTES_MLOFFYES_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFYES_DMLOE [3/5]

#define DMA_NBYTES_MLOFFYES_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFYES_DMLOE [4/5]

#define DMA_NBYTES_MLOFFYES_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFYES_DMLOE [5/5]

#define DMA_NBYTES_MLOFFYES_DMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)

DMLOE - Destination Minor Loop Offset enable 0b0..The minor loop offset is not applied to the DADDR 0b1..The minor loop offset is applied to the DADDR

◆ DMA_NBYTES_MLOFFYES_SMLOE [1/5]

#define DMA_NBYTES_MLOFFYES_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFYES_SMLOE [2/5]

#define DMA_NBYTES_MLOFFYES_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFYES_SMLOE [3/5]

#define DMA_NBYTES_MLOFFYES_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFYES_SMLOE [4/5]

#define DMA_NBYTES_MLOFFYES_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_NBYTES_MLOFFYES_SMLOE [5/5]

#define DMA_NBYTES_MLOFFYES_SMLOE ( x ) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)

SMLOE - Source Minor Loop Offset Enable 0b0..The minor loop offset is not applied to the SADDR 0b1..The minor loop offset is applied to the SADDR

◆ DMA_SEEI_NOP [1/5]

#define DMA_SEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SEEI_NOP [2/5]

#define DMA_SEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SEEI_NOP [3/5]

#define DMA_SEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SEEI_NOP [4/5]

#define DMA_SEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SEEI_NOP [5/5]

#define DMA_SEEI_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SEEI_SAEE [1/5]

#define DMA_SEEI_SAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

SAEE - Sets All Enable Error Interrupts 0b0..Set only the EEI bit specified in the SEEI field. 0b1..Sets all bits in EEI

◆ DMA_SEEI_SAEE [2/5]

#define DMA_SEEI_SAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

SAEE - Sets All Enable Error Interrupts 0b0..Set only the EEI bit specified in the SEEI field. 0b1..Sets all bits in EEI

◆ DMA_SEEI_SAEE [3/5]

#define DMA_SEEI_SAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

SAEE - Sets All Enable Error Interrupts 0b0..Set only the EEI bit specified in the SEEI field. 0b1..Sets all bits in EEI

◆ DMA_SEEI_SAEE [4/5]

#define DMA_SEEI_SAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

SAEE - Sets All Enable Error Interrupts 0b0..Set only the EEI bit specified in the SEEI field. 0b1..Sets all bits in EEI

◆ DMA_SEEI_SAEE [5/5]

#define DMA_SEEI_SAEE ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)

SAEE - Sets All Enable Error Interrupts 0b0..Set only the EEI bit specified in the SEEI field. 0b1..Sets all bits in EEI

◆ DMA_SERQ_NOP [1/5]

#define DMA_SERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SERQ_NOP [2/5]

#define DMA_SERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SERQ_NOP [3/5]

#define DMA_SERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SERQ_NOP [4/5]

#define DMA_SERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SERQ_NOP [5/5]

#define DMA_SERQ_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SERQ_SAER [1/5]

#define DMA_SERQ_SAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

SAER - Set All Enable Requests 0b0..Set only the ERQ bit specified in the SERQ field 0b1..Set all bits in ERQ

◆ DMA_SERQ_SAER [2/5]

#define DMA_SERQ_SAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

SAER - Set All Enable Requests 0b0..Set only the ERQ bit specified in the SERQ field 0b1..Set all bits in ERQ

◆ DMA_SERQ_SAER [3/5]

#define DMA_SERQ_SAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

SAER - Set All Enable Requests 0b0..Set only the ERQ bit specified in the SERQ field 0b1..Set all bits in ERQ

◆ DMA_SERQ_SAER [4/5]

#define DMA_SERQ_SAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

SAER - Set All Enable Requests 0b0..Set only the ERQ bit specified in the SERQ field 0b1..Set all bits in ERQ

◆ DMA_SERQ_SAER [5/5]

#define DMA_SERQ_SAER ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)

SAER - Set All Enable Requests 0b0..Set only the ERQ bit specified in the SERQ field 0b1..Set all bits in ERQ

◆ DMA_SSRT_NOP [1/5]

#define DMA_SSRT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SSRT_NOP [2/5]

#define DMA_SSRT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SSRT_NOP [3/5]

#define DMA_SSRT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SSRT_NOP [4/5]

#define DMA_SSRT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SSRT_NOP [5/5]

#define DMA_SSRT_NOP ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)

NOP - No Op enable 0b0..Normal operation 0b1..No operation, ignore the other bits in this register

◆ DMA_SSRT_SAST [1/5]

#define DMA_SSRT_SAST ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

SAST - Set All START Bits (activates all channels) 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field 0b1..Set all bits in TCDn_CSR[START]

◆ DMA_SSRT_SAST [2/5]

#define DMA_SSRT_SAST ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

SAST - Set All START Bits (activates all channels) 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field 0b1..Set all bits in TCDn_CSR[START]

◆ DMA_SSRT_SAST [3/5]

#define DMA_SSRT_SAST ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

SAST - Set All START Bits (activates all channels) 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field 0b1..Set all bits in TCDn_CSR[START]

◆ DMA_SSRT_SAST [4/5]

#define DMA_SSRT_SAST ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

SAST - Set All START Bits (activates all channels) 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field 0b1..Set all bits in TCDn_CSR[START]

◆ DMA_SSRT_SAST [5/5]

#define DMA_SSRT_SAST ( x ) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)

SAST - Set All START Bits (activates all channels) 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field 0b1..Set all bits in TCDn_CSR[START]

◆ MCM_CR_AHBSPRI

#define MCM_CR_AHBSPRI ( x ) (((uint32_t)(((uint32_t)(x)) << MCM_CR_AHBSPRI_SHIFT)) & MCM_CR_AHBSPRI_MASK)

AHBSPRI - AHB Slave Interface Priority 0b0..SW accesses take priority over AHBS accesses 0b1..AHBS accesses take priority over SW accesses

Macros

CR - Control Register

ES - Error Status Register

ERQ - Enable Request Register

EEI - Enable Error Interrupt Register

CEEI - Clear Enable Error Interrupt Register

SEEI - Set Enable Error Interrupt Register

CERQ - Clear Enable Request Register

SERQ - Set Enable Request Register

CDNE - Clear DONE Status Bit Register

SSRT - Set START Bit Register

CERR - Clear Error Register

CINT - Clear Interrupt Request Register

INT - Interrupt Request Register

ERR - Error Register

HRS - Hardware Request Status Register

DCHPRI3 - Channel n Priority Register

DCHPRI2 - Channel n Priority Register

DCHPRI1 - Channel n Priority Register

DCHPRI0 - Channel n Priority Register

DCHPRI7 - Channel n Priority Register

DCHPRI6 - Channel n Priority Register

DCHPRI5 - Channel n Priority Register

DCHPRI4 - Channel n Priority Register

DCHPRI11 - Channel n Priority Register

DCHPRI10 - Channel n Priority Register

DCHPRI9 - Channel n Priority Register

DCHPRI8 - Channel n Priority Register

DCHPRI15 - Channel n Priority Register

DCHPRI14 - Channel n Priority Register

DCHPRI13 - Channel n Priority Register

DCHPRI12 - Channel n Priority Register

SADDR - TCD Source Address

SADDR - TCD Source Address

SOFF - TCD Signed Source Address Offset

SOFF - TCD Signed Source Address Offset

ATTR - TCD Transfer Attributes

ATTR - TCD Transfer Attributes

NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled)

NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)

NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)

NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)

NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)

NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)

SLAST - TCD Last Source Address Adjustment

SLAST - TCD Last Source Address Adjustment

DADDR - TCD Destination Address

DADDR - TCD Destination Address

DOFF - TCD Signed Destination Address Offset

DOFF - TCD Signed Destination Address Offset

CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address

DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address

CSR - TCD Control and Status

CSR - TCD Control and Status

BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

EARS - Enable Asynchronous Request in Stop Register

DCHPRI19 - Channel n Priority Register

DCHPRI18 - Channel n Priority Register

DCHPRI17 - Channel n Priority Register

DCHPRI16 - Channel n Priority Register

DCHPRI23 - Channel n Priority Register

DCHPRI22 - Channel n Priority Register

DCHPRI21 - Channel n Priority Register

DCHPRI20 - Channel n Priority Register

DCHPRI27 - Channel n Priority Register

DCHPRI26 - Channel n Priority Register

DCHPRI25 - Channel n Priority Register

DCHPRI24 - Channel n Priority Register

DCHPRI31 - Channel n Priority Register

DCHPRI30 - Channel n Priority Register

DCHPRI29 - Channel n Priority Register

DCHPRI28 - Channel n Priority Register

Macro Definition Documentation