ENET Register Masks

Macros
#define	ENET_BASE   (0x400C0000u)
#define	ENET   ((ENET_Type *)ENET_BASE)
#define	ENET_BASE_ADDRS   { ENET_BASE }
#define	ENET_BASE_PTRS   { ENET }
#define	ENET_Transmit_IRQS   { ENET_Transmit_IRQn }
#define	ENET_Receive_IRQS   { ENET_Receive_IRQn }
#define	ENET_Error_IRQS   { ENET_Error_IRQn }
#define	ENET_1588_Timer_IRQS   { ENET_1588_Timer_IRQn }
#define	ENET_BUFF_ALIGNMENT   (16U)
#define	ENET_TCSR_COUNT   (4U)
#define	ENET_TCCR_COUNT   (4U)
#define	ENET_TCSR_COUNT   (4U)
#define	ENET_TCCR_COUNT   (4U)
#define	ENET_TCSR_COUNT   (4U)
#define	ENET_TCCR_COUNT   (4U)
#define	ENET_TCSR_COUNT   (4U)
#define	ENET_TCCR_COUNT   (4U)

EIR - Interrupt Event Register
#define	ENET_EIR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
#define	ENET_EIR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
#define	ENET_EIR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIR_WAKEUP_SHIFT   (17U)
#define	ENET_EIR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
#define	ENET_EIR_PLR_MASK   (0x40000U)
#define	ENET_EIR_PLR_SHIFT   (18U)
#define	ENET_EIR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
#define	ENET_EIR_UN_MASK   (0x80000U)
#define	ENET_EIR_UN_SHIFT   (19U)
#define	ENET_EIR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
#define	ENET_EIR_RL_MASK   (0x100000U)
#define	ENET_EIR_RL_SHIFT   (20U)
#define	ENET_EIR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
#define	ENET_EIR_LC_MASK   (0x200000U)
#define	ENET_EIR_LC_SHIFT   (21U)
#define	ENET_EIR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
#define	ENET_EIR_EBERR_MASK   (0x400000U)
#define	ENET_EIR_EBERR_SHIFT   (22U)
#define	ENET_EIR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
#define	ENET_EIR_MII_MASK   (0x800000U)
#define	ENET_EIR_MII_SHIFT   (23U)
#define	ENET_EIR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
#define	ENET_EIR_RXB_MASK   (0x1000000U)
#define	ENET_EIR_RXB_SHIFT   (24U)
#define	ENET_EIR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
#define	ENET_EIR_RXF_MASK   (0x2000000U)
#define	ENET_EIR_RXF_SHIFT   (25U)
#define	ENET_EIR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
#define	ENET_EIR_TXB_MASK   (0x4000000U)
#define	ENET_EIR_TXB_SHIFT   (26U)
#define	ENET_EIR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
#define	ENET_EIR_TXF_MASK   (0x8000000U)
#define	ENET_EIR_TXF_SHIFT   (27U)
#define	ENET_EIR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
#define	ENET_EIR_GRA_MASK   (0x10000000U)
#define	ENET_EIR_GRA_SHIFT   (28U)
#define	ENET_EIR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
#define	ENET_EIR_BABT_MASK   (0x20000000U)
#define	ENET_EIR_BABT_SHIFT   (29U)
#define	ENET_EIR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
#define	ENET_EIR_BABR_MASK   (0x40000000U)
#define	ENET_EIR_BABR_SHIFT   (30U)
#define	ENET_EIR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
#define	ENET_EIR_TS_TIMER_MASK   0x8000u
#define	ENET_EIR_TS_TIMER_SHIFT   15
#define	ENET_EIR_TS_AVAIL_MASK   0x10000u
#define	ENET_EIR_TS_AVAIL_SHIFT   16
#define	ENET_EIR_WAKEUP_MASK   0x20000u
#define	ENET_EIR_WAKEUP_SHIFT   17
#define	ENET_EIR_PLR_MASK   0x40000u
#define	ENET_EIR_PLR_SHIFT   18
#define	ENET_EIR_UN_MASK   0x80000u
#define	ENET_EIR_UN_SHIFT   19
#define	ENET_EIR_RL_MASK   0x100000u
#define	ENET_EIR_RL_SHIFT   20
#define	ENET_EIR_LC_MASK   0x200000u
#define	ENET_EIR_LC_SHIFT   21
#define	ENET_EIR_EBERR_MASK   0x400000u
#define	ENET_EIR_EBERR_SHIFT   22
#define	ENET_EIR_MII_MASK   0x800000u
#define	ENET_EIR_MII_SHIFT   23
#define	ENET_EIR_RXB_MASK   0x1000000u
#define	ENET_EIR_RXB_SHIFT   24
#define	ENET_EIR_RXF_MASK   0x2000000u
#define	ENET_EIR_RXF_SHIFT   25
#define	ENET_EIR_TXB_MASK   0x4000000u
#define	ENET_EIR_TXB_SHIFT   26
#define	ENET_EIR_TXF_MASK   0x8000000u
#define	ENET_EIR_TXF_SHIFT   27
#define	ENET_EIR_GRA_MASK   0x10000000u
#define	ENET_EIR_GRA_SHIFT   28
#define	ENET_EIR_BABT_MASK   0x20000000u
#define	ENET_EIR_BABT_SHIFT   29
#define	ENET_EIR_BABR_MASK   0x40000000u
#define	ENET_EIR_BABR_SHIFT   30
#define	ENET_EIR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
#define	ENET_EIR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
#define	ENET_EIR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIR_WAKEUP_SHIFT   (17U)
#define	ENET_EIR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
#define	ENET_EIR_PLR_MASK   (0x40000U)
#define	ENET_EIR_PLR_SHIFT   (18U)
#define	ENET_EIR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
#define	ENET_EIR_UN_MASK   (0x80000U)
#define	ENET_EIR_UN_SHIFT   (19U)
#define	ENET_EIR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
#define	ENET_EIR_RL_MASK   (0x100000U)
#define	ENET_EIR_RL_SHIFT   (20U)
#define	ENET_EIR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
#define	ENET_EIR_LC_MASK   (0x200000U)
#define	ENET_EIR_LC_SHIFT   (21U)
#define	ENET_EIR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
#define	ENET_EIR_EBERR_MASK   (0x400000U)
#define	ENET_EIR_EBERR_SHIFT   (22U)
#define	ENET_EIR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
#define	ENET_EIR_MII_MASK   (0x800000U)
#define	ENET_EIR_MII_SHIFT   (23U)
#define	ENET_EIR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
#define	ENET_EIR_RXB_MASK   (0x1000000U)
#define	ENET_EIR_RXB_SHIFT   (24U)
#define	ENET_EIR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
#define	ENET_EIR_RXF_MASK   (0x2000000U)
#define	ENET_EIR_RXF_SHIFT   (25U)
#define	ENET_EIR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
#define	ENET_EIR_TXB_MASK   (0x4000000U)
#define	ENET_EIR_TXB_SHIFT   (26U)
#define	ENET_EIR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
#define	ENET_EIR_TXF_MASK   (0x8000000U)
#define	ENET_EIR_TXF_SHIFT   (27U)
#define	ENET_EIR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
#define	ENET_EIR_GRA_MASK   (0x10000000U)
#define	ENET_EIR_GRA_SHIFT   (28U)
#define	ENET_EIR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
#define	ENET_EIR_BABT_MASK   (0x20000000U)
#define	ENET_EIR_BABT_SHIFT   (29U)
#define	ENET_EIR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
#define	ENET_EIR_BABR_MASK   (0x40000000U)
#define	ENET_EIR_BABR_SHIFT   (30U)
#define	ENET_EIR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
#define	ENET_EIR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
#define	ENET_EIR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
#define	ENET_EIR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIR_WAKEUP_SHIFT   (17U)
#define	ENET_EIR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
#define	ENET_EIR_PLR_MASK   (0x40000U)
#define	ENET_EIR_PLR_SHIFT   (18U)
#define	ENET_EIR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
#define	ENET_EIR_UN_MASK   (0x80000U)
#define	ENET_EIR_UN_SHIFT   (19U)
#define	ENET_EIR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
#define	ENET_EIR_RL_MASK   (0x100000U)
#define	ENET_EIR_RL_SHIFT   (20U)
#define	ENET_EIR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
#define	ENET_EIR_LC_MASK   (0x200000U)
#define	ENET_EIR_LC_SHIFT   (21U)
#define	ENET_EIR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
#define	ENET_EIR_EBERR_MASK   (0x400000U)
#define	ENET_EIR_EBERR_SHIFT   (22U)
#define	ENET_EIR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
#define	ENET_EIR_MII_MASK   (0x800000U)
#define	ENET_EIR_MII_SHIFT   (23U)
#define	ENET_EIR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
#define	ENET_EIR_RXB_MASK   (0x1000000U)
#define	ENET_EIR_RXB_SHIFT   (24U)
#define	ENET_EIR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
#define	ENET_EIR_RXF_MASK   (0x2000000U)
#define	ENET_EIR_RXF_SHIFT   (25U)
#define	ENET_EIR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
#define	ENET_EIR_TXB_MASK   (0x4000000U)
#define	ENET_EIR_TXB_SHIFT   (26U)
#define	ENET_EIR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
#define	ENET_EIR_TXF_MASK   (0x8000000U)
#define	ENET_EIR_TXF_SHIFT   (27U)
#define	ENET_EIR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
#define	ENET_EIR_GRA_MASK   (0x10000000U)
#define	ENET_EIR_GRA_SHIFT   (28U)
#define	ENET_EIR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
#define	ENET_EIR_BABT_MASK   (0x20000000U)
#define	ENET_EIR_BABT_SHIFT   (29U)
#define	ENET_EIR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
#define	ENET_EIR_BABR_MASK   (0x40000000U)
#define	ENET_EIR_BABR_SHIFT   (30U)
#define	ENET_EIR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
#define	ENET_EIR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
#define	ENET_EIR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
#define	ENET_EIR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIR_WAKEUP_SHIFT   (17U)
#define	ENET_EIR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
#define	ENET_EIR_PLR_MASK   (0x40000U)
#define	ENET_EIR_PLR_SHIFT   (18U)
#define	ENET_EIR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
#define	ENET_EIR_UN_MASK   (0x80000U)
#define	ENET_EIR_UN_SHIFT   (19U)
#define	ENET_EIR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
#define	ENET_EIR_RL_MASK   (0x100000U)
#define	ENET_EIR_RL_SHIFT   (20U)
#define	ENET_EIR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
#define	ENET_EIR_LC_MASK   (0x200000U)
#define	ENET_EIR_LC_SHIFT   (21U)
#define	ENET_EIR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
#define	ENET_EIR_EBERR_MASK   (0x400000U)
#define	ENET_EIR_EBERR_SHIFT   (22U)
#define	ENET_EIR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
#define	ENET_EIR_MII_MASK   (0x800000U)
#define	ENET_EIR_MII_SHIFT   (23U)
#define	ENET_EIR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
#define	ENET_EIR_RXB_MASK   (0x1000000U)
#define	ENET_EIR_RXB_SHIFT   (24U)
#define	ENET_EIR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
#define	ENET_EIR_RXF_MASK   (0x2000000U)
#define	ENET_EIR_RXF_SHIFT   (25U)
#define	ENET_EIR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
#define	ENET_EIR_TXB_MASK   (0x4000000U)
#define	ENET_EIR_TXB_SHIFT   (26U)
#define	ENET_EIR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
#define	ENET_EIR_TXF_MASK   (0x8000000U)
#define	ENET_EIR_TXF_SHIFT   (27U)
#define	ENET_EIR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
#define	ENET_EIR_GRA_MASK   (0x10000000U)
#define	ENET_EIR_GRA_SHIFT   (28U)
#define	ENET_EIR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
#define	ENET_EIR_BABT_MASK   (0x20000000U)
#define	ENET_EIR_BABT_SHIFT   (29U)
#define	ENET_EIR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
#define	ENET_EIR_BABR_MASK   (0x40000000U)
#define	ENET_EIR_BABR_SHIFT   (30U)
#define	ENET_EIR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
#define	ENET_EIR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
#define	ENET_EIR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
#define	ENET_EIR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIR_WAKEUP_SHIFT   (17U)
#define	ENET_EIR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
#define	ENET_EIR_PLR_MASK   (0x40000U)
#define	ENET_EIR_PLR_SHIFT   (18U)
#define	ENET_EIR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
#define	ENET_EIR_UN_MASK   (0x80000U)
#define	ENET_EIR_UN_SHIFT   (19U)
#define	ENET_EIR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
#define	ENET_EIR_RL_MASK   (0x100000U)
#define	ENET_EIR_RL_SHIFT   (20U)
#define	ENET_EIR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
#define	ENET_EIR_LC_MASK   (0x200000U)
#define	ENET_EIR_LC_SHIFT   (21U)
#define	ENET_EIR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
#define	ENET_EIR_EBERR_MASK   (0x400000U)
#define	ENET_EIR_EBERR_SHIFT   (22U)
#define	ENET_EIR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
#define	ENET_EIR_MII_MASK   (0x800000U)
#define	ENET_EIR_MII_SHIFT   (23U)
#define	ENET_EIR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
#define	ENET_EIR_RXB_MASK   (0x1000000U)
#define	ENET_EIR_RXB_SHIFT   (24U)
#define	ENET_EIR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
#define	ENET_EIR_RXF_MASK   (0x2000000U)
#define	ENET_EIR_RXF_SHIFT   (25U)
#define	ENET_EIR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
#define	ENET_EIR_TXB_MASK   (0x4000000U)
#define	ENET_EIR_TXB_SHIFT   (26U)
#define	ENET_EIR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
#define	ENET_EIR_TXF_MASK   (0x8000000U)
#define	ENET_EIR_TXF_SHIFT   (27U)
#define	ENET_EIR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
#define	ENET_EIR_GRA_MASK   (0x10000000U)
#define	ENET_EIR_GRA_SHIFT   (28U)
#define	ENET_EIR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
#define	ENET_EIR_BABT_MASK   (0x20000000U)
#define	ENET_EIR_BABT_SHIFT   (29U)
#define	ENET_EIR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
#define	ENET_EIR_BABR_MASK   (0x40000000U)
#define	ENET_EIR_BABR_SHIFT   (30U)
#define	ENET_EIR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)

EIMR - Interrupt Mask Register
#define	ENET_EIMR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIMR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIMR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
#define	ENET_EIMR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIMR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIMR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
#define	ENET_EIMR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIMR_WAKEUP_SHIFT   (17U)
#define	ENET_EIMR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
#define	ENET_EIMR_PLR_MASK   (0x40000U)
#define	ENET_EIMR_PLR_SHIFT   (18U)
#define	ENET_EIMR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
#define	ENET_EIMR_UN_MASK   (0x80000U)
#define	ENET_EIMR_UN_SHIFT   (19U)
#define	ENET_EIMR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
#define	ENET_EIMR_RL_MASK   (0x100000U)
#define	ENET_EIMR_RL_SHIFT   (20U)
#define	ENET_EIMR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
#define	ENET_EIMR_LC_MASK   (0x200000U)
#define	ENET_EIMR_LC_SHIFT   (21U)
#define	ENET_EIMR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
#define	ENET_EIMR_EBERR_MASK   (0x400000U)
#define	ENET_EIMR_EBERR_SHIFT   (22U)
#define	ENET_EIMR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
#define	ENET_EIMR_MII_MASK   (0x800000U)
#define	ENET_EIMR_MII_SHIFT   (23U)
#define	ENET_EIMR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
#define	ENET_EIMR_RXB_MASK   (0x1000000U)
#define	ENET_EIMR_RXB_SHIFT   (24U)
#define	ENET_EIMR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
#define	ENET_EIMR_RXF_MASK   (0x2000000U)
#define	ENET_EIMR_RXF_SHIFT   (25U)
#define	ENET_EIMR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
#define	ENET_EIMR_TXB_MASK   (0x4000000U)
#define	ENET_EIMR_TXB_SHIFT   (26U)
#define	ENET_EIMR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
#define	ENET_EIMR_TXF_MASK   (0x8000000U)
#define	ENET_EIMR_TXF_SHIFT   (27U)
#define	ENET_EIMR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
#define	ENET_EIMR_GRA_MASK   (0x10000000U)
#define	ENET_EIMR_GRA_SHIFT   (28U)
#define	ENET_EIMR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
#define	ENET_EIMR_BABT_MASK   (0x20000000U)
#define	ENET_EIMR_BABT_SHIFT   (29U)
#define	ENET_EIMR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
#define	ENET_EIMR_BABR_MASK   (0x40000000U)
#define	ENET_EIMR_BABR_SHIFT   (30U)
#define	ENET_EIMR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
#define	ENET_EIMR_TS_TIMER_MASK   0x8000u
#define	ENET_EIMR_TS_TIMER_SHIFT   15
#define	ENET_EIMR_TS_AVAIL_MASK   0x10000u
#define	ENET_EIMR_TS_AVAIL_SHIFT   16
#define	ENET_EIMR_WAKEUP_MASK   0x20000u
#define	ENET_EIMR_WAKEUP_SHIFT   17
#define	ENET_EIMR_PLR_MASK   0x40000u
#define	ENET_EIMR_PLR_SHIFT   18
#define	ENET_EIMR_UN_MASK   0x80000u
#define	ENET_EIMR_UN_SHIFT   19
#define	ENET_EIMR_RL_MASK   0x100000u
#define	ENET_EIMR_RL_SHIFT   20
#define	ENET_EIMR_LC_MASK   0x200000u
#define	ENET_EIMR_LC_SHIFT   21
#define	ENET_EIMR_EBERR_MASK   0x400000u
#define	ENET_EIMR_EBERR_SHIFT   22
#define	ENET_EIMR_MII_MASK   0x800000u
#define	ENET_EIMR_MII_SHIFT   23
#define	ENET_EIMR_RXB_MASK   0x1000000u
#define	ENET_EIMR_RXB_SHIFT   24
#define	ENET_EIMR_RXF_MASK   0x2000000u
#define	ENET_EIMR_RXF_SHIFT   25
#define	ENET_EIMR_TXB_MASK   0x4000000u
#define	ENET_EIMR_TXB_SHIFT   26
#define	ENET_EIMR_TXF_MASK   0x8000000u
#define	ENET_EIMR_TXF_SHIFT   27
#define	ENET_EIMR_GRA_MASK   0x10000000u
#define	ENET_EIMR_GRA_SHIFT   28
#define	ENET_EIMR_BABT_MASK   0x20000000u
#define	ENET_EIMR_BABT_SHIFT   29
#define	ENET_EIMR_BABR_MASK   0x40000000u
#define	ENET_EIMR_BABR_SHIFT   30
#define	ENET_EIMR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIMR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIMR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
#define	ENET_EIMR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIMR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIMR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
#define	ENET_EIMR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIMR_WAKEUP_SHIFT   (17U)
#define	ENET_EIMR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
#define	ENET_EIMR_PLR_MASK   (0x40000U)
#define	ENET_EIMR_PLR_SHIFT   (18U)
#define	ENET_EIMR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
#define	ENET_EIMR_UN_MASK   (0x80000U)
#define	ENET_EIMR_UN_SHIFT   (19U)
#define	ENET_EIMR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
#define	ENET_EIMR_RL_MASK   (0x100000U)
#define	ENET_EIMR_RL_SHIFT   (20U)
#define	ENET_EIMR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
#define	ENET_EIMR_LC_MASK   (0x200000U)
#define	ENET_EIMR_LC_SHIFT   (21U)
#define	ENET_EIMR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
#define	ENET_EIMR_EBERR_MASK   (0x400000U)
#define	ENET_EIMR_EBERR_SHIFT   (22U)
#define	ENET_EIMR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
#define	ENET_EIMR_MII_MASK   (0x800000U)
#define	ENET_EIMR_MII_SHIFT   (23U)
#define	ENET_EIMR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
#define	ENET_EIMR_RXB_MASK   (0x1000000U)
#define	ENET_EIMR_RXB_SHIFT   (24U)
#define	ENET_EIMR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
#define	ENET_EIMR_RXF_MASK   (0x2000000U)
#define	ENET_EIMR_RXF_SHIFT   (25U)
#define	ENET_EIMR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
#define	ENET_EIMR_TXB_MASK   (0x4000000U)
#define	ENET_EIMR_TXB_SHIFT   (26U)
#define	ENET_EIMR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
#define	ENET_EIMR_TXF_MASK   (0x8000000U)
#define	ENET_EIMR_TXF_SHIFT   (27U)
#define	ENET_EIMR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
#define	ENET_EIMR_GRA_MASK   (0x10000000U)
#define	ENET_EIMR_GRA_SHIFT   (28U)
#define	ENET_EIMR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
#define	ENET_EIMR_BABT_MASK   (0x20000000U)
#define	ENET_EIMR_BABT_SHIFT   (29U)
#define	ENET_EIMR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
#define	ENET_EIMR_BABR_MASK   (0x40000000U)
#define	ENET_EIMR_BABR_SHIFT   (30U)
#define	ENET_EIMR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
#define	ENET_EIMR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIMR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIMR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
#define	ENET_EIMR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIMR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIMR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
#define	ENET_EIMR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIMR_WAKEUP_SHIFT   (17U)
#define	ENET_EIMR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
#define	ENET_EIMR_PLR_MASK   (0x40000U)
#define	ENET_EIMR_PLR_SHIFT   (18U)
#define	ENET_EIMR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
#define	ENET_EIMR_UN_MASK   (0x80000U)
#define	ENET_EIMR_UN_SHIFT   (19U)
#define	ENET_EIMR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
#define	ENET_EIMR_RL_MASK   (0x100000U)
#define	ENET_EIMR_RL_SHIFT   (20U)
#define	ENET_EIMR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
#define	ENET_EIMR_LC_MASK   (0x200000U)
#define	ENET_EIMR_LC_SHIFT   (21U)
#define	ENET_EIMR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
#define	ENET_EIMR_EBERR_MASK   (0x400000U)
#define	ENET_EIMR_EBERR_SHIFT   (22U)
#define	ENET_EIMR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
#define	ENET_EIMR_MII_MASK   (0x800000U)
#define	ENET_EIMR_MII_SHIFT   (23U)
#define	ENET_EIMR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
#define	ENET_EIMR_RXB_MASK   (0x1000000U)
#define	ENET_EIMR_RXB_SHIFT   (24U)
#define	ENET_EIMR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
#define	ENET_EIMR_RXF_MASK   (0x2000000U)
#define	ENET_EIMR_RXF_SHIFT   (25U)
#define	ENET_EIMR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
#define	ENET_EIMR_TXB_MASK   (0x4000000U)
#define	ENET_EIMR_TXB_SHIFT   (26U)
#define	ENET_EIMR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
#define	ENET_EIMR_TXF_MASK   (0x8000000U)
#define	ENET_EIMR_TXF_SHIFT   (27U)
#define	ENET_EIMR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
#define	ENET_EIMR_GRA_MASK   (0x10000000U)
#define	ENET_EIMR_GRA_SHIFT   (28U)
#define	ENET_EIMR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
#define	ENET_EIMR_BABT_MASK   (0x20000000U)
#define	ENET_EIMR_BABT_SHIFT   (29U)
#define	ENET_EIMR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
#define	ENET_EIMR_BABR_MASK   (0x40000000U)
#define	ENET_EIMR_BABR_SHIFT   (30U)
#define	ENET_EIMR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
#define	ENET_EIMR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIMR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIMR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
#define	ENET_EIMR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIMR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIMR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
#define	ENET_EIMR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIMR_WAKEUP_SHIFT   (17U)
#define	ENET_EIMR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
#define	ENET_EIMR_PLR_MASK   (0x40000U)
#define	ENET_EIMR_PLR_SHIFT   (18U)
#define	ENET_EIMR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
#define	ENET_EIMR_UN_MASK   (0x80000U)
#define	ENET_EIMR_UN_SHIFT   (19U)
#define	ENET_EIMR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
#define	ENET_EIMR_RL_MASK   (0x100000U)
#define	ENET_EIMR_RL_SHIFT   (20U)
#define	ENET_EIMR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
#define	ENET_EIMR_LC_MASK   (0x200000U)
#define	ENET_EIMR_LC_SHIFT   (21U)
#define	ENET_EIMR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
#define	ENET_EIMR_EBERR_MASK   (0x400000U)
#define	ENET_EIMR_EBERR_SHIFT   (22U)
#define	ENET_EIMR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
#define	ENET_EIMR_MII_MASK   (0x800000U)
#define	ENET_EIMR_MII_SHIFT   (23U)
#define	ENET_EIMR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
#define	ENET_EIMR_RXB_MASK   (0x1000000U)
#define	ENET_EIMR_RXB_SHIFT   (24U)
#define	ENET_EIMR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
#define	ENET_EIMR_RXF_MASK   (0x2000000U)
#define	ENET_EIMR_RXF_SHIFT   (25U)
#define	ENET_EIMR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
#define	ENET_EIMR_TXB_MASK   (0x4000000U)
#define	ENET_EIMR_TXB_SHIFT   (26U)
#define	ENET_EIMR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
#define	ENET_EIMR_TXF_MASK   (0x8000000U)
#define	ENET_EIMR_TXF_SHIFT   (27U)
#define	ENET_EIMR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
#define	ENET_EIMR_GRA_MASK   (0x10000000U)
#define	ENET_EIMR_GRA_SHIFT   (28U)
#define	ENET_EIMR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
#define	ENET_EIMR_BABT_MASK   (0x20000000U)
#define	ENET_EIMR_BABT_SHIFT   (29U)
#define	ENET_EIMR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
#define	ENET_EIMR_BABR_MASK   (0x40000000U)
#define	ENET_EIMR_BABR_SHIFT   (30U)
#define	ENET_EIMR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
#define	ENET_EIMR_TS_TIMER_MASK   (0x8000U)
#define	ENET_EIMR_TS_TIMER_SHIFT   (15U)
#define	ENET_EIMR_TS_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
#define	ENET_EIMR_TS_AVAIL_MASK   (0x10000U)
#define	ENET_EIMR_TS_AVAIL_SHIFT   (16U)
#define	ENET_EIMR_TS_AVAIL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
#define	ENET_EIMR_WAKEUP_MASK   (0x20000U)
#define	ENET_EIMR_WAKEUP_SHIFT   (17U)
#define	ENET_EIMR_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
#define	ENET_EIMR_PLR_MASK   (0x40000U)
#define	ENET_EIMR_PLR_SHIFT   (18U)
#define	ENET_EIMR_PLR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
#define	ENET_EIMR_UN_MASK   (0x80000U)
#define	ENET_EIMR_UN_SHIFT   (19U)
#define	ENET_EIMR_UN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
#define	ENET_EIMR_RL_MASK   (0x100000U)
#define	ENET_EIMR_RL_SHIFT   (20U)
#define	ENET_EIMR_RL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
#define	ENET_EIMR_LC_MASK   (0x200000U)
#define	ENET_EIMR_LC_SHIFT   (21U)
#define	ENET_EIMR_LC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
#define	ENET_EIMR_EBERR_MASK   (0x400000U)
#define	ENET_EIMR_EBERR_SHIFT   (22U)
#define	ENET_EIMR_EBERR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
#define	ENET_EIMR_MII_MASK   (0x800000U)
#define	ENET_EIMR_MII_SHIFT   (23U)
#define	ENET_EIMR_MII(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
#define	ENET_EIMR_RXB_MASK   (0x1000000U)
#define	ENET_EIMR_RXB_SHIFT   (24U)
#define	ENET_EIMR_RXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
#define	ENET_EIMR_RXF_MASK   (0x2000000U)
#define	ENET_EIMR_RXF_SHIFT   (25U)
#define	ENET_EIMR_RXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
#define	ENET_EIMR_TXB_MASK   (0x4000000U)
#define	ENET_EIMR_TXB_SHIFT   (26U)
#define	ENET_EIMR_TXB(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
#define	ENET_EIMR_TXF_MASK   (0x8000000U)
#define	ENET_EIMR_TXF_SHIFT   (27U)
#define	ENET_EIMR_TXF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
#define	ENET_EIMR_GRA_MASK   (0x10000000U)
#define	ENET_EIMR_GRA_SHIFT   (28U)
#define	ENET_EIMR_GRA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
#define	ENET_EIMR_BABT_MASK   (0x20000000U)
#define	ENET_EIMR_BABT_SHIFT   (29U)
#define	ENET_EIMR_BABT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
#define	ENET_EIMR_BABR_MASK   (0x40000000U)
#define	ENET_EIMR_BABR_SHIFT   (30U)
#define	ENET_EIMR_BABR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

RDAR - Receive Descriptor Active Register
#define	ENET_RDAR_RDAR_MASK   (0x1000000U)
#define	ENET_RDAR_RDAR_SHIFT   (24U)
#define	ENET_RDAR_RDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
#define	ENET_RDAR_RDAR_MASK   0x1000000u
#define	ENET_RDAR_RDAR_SHIFT   24
#define	ENET_RDAR_RDAR_MASK   (0x1000000U)
#define	ENET_RDAR_RDAR_SHIFT   (24U)
#define	ENET_RDAR_RDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
#define	ENET_RDAR_RDAR_MASK   (0x1000000U)
#define	ENET_RDAR_RDAR_SHIFT   (24U)
#define	ENET_RDAR_RDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
#define	ENET_RDAR_RDAR_MASK   (0x1000000U)
#define	ENET_RDAR_RDAR_SHIFT   (24U)
#define	ENET_RDAR_RDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
#define	ENET_RDAR_RDAR_MASK   (0x1000000U)
#define	ENET_RDAR_RDAR_SHIFT   (24U)
#define	ENET_RDAR_RDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)

TDAR - Transmit Descriptor Active Register
#define	ENET_TDAR_TDAR_MASK   (0x1000000U)
#define	ENET_TDAR_TDAR_SHIFT   (24U)
#define	ENET_TDAR_TDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
#define	ENET_TDAR_TDAR_MASK   0x1000000u
#define	ENET_TDAR_TDAR_SHIFT   24
#define	ENET_TDAR_TDAR_MASK   (0x1000000U)
#define	ENET_TDAR_TDAR_SHIFT   (24U)
#define	ENET_TDAR_TDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
#define	ENET_TDAR_TDAR_MASK   (0x1000000U)
#define	ENET_TDAR_TDAR_SHIFT   (24U)
#define	ENET_TDAR_TDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
#define	ENET_TDAR_TDAR_MASK   (0x1000000U)
#define	ENET_TDAR_TDAR_SHIFT   (24U)
#define	ENET_TDAR_TDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
#define	ENET_TDAR_TDAR_MASK   (0x1000000U)
#define	ENET_TDAR_TDAR_SHIFT   (24U)
#define	ENET_TDAR_TDAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)

ECR - Ethernet Control Register
#define	ENET_ECR_RESET_MASK   (0x1U)
#define	ENET_ECR_RESET_SHIFT   (0U)
#define	ENET_ECR_RESET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
#define	ENET_ECR_ETHEREN_MASK   (0x2U)
#define	ENET_ECR_ETHEREN_SHIFT   (1U)
#define	ENET_ECR_ETHEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
#define	ENET_ECR_MAGICEN_MASK   (0x4U)
#define	ENET_ECR_MAGICEN_SHIFT   (2U)
#define	ENET_ECR_MAGICEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
#define	ENET_ECR_SLEEP_MASK   (0x8U)
#define	ENET_ECR_SLEEP_SHIFT   (3U)
#define	ENET_ECR_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
#define	ENET_ECR_EN1588_MASK   (0x10U)
#define	ENET_ECR_EN1588_SHIFT   (4U)
#define	ENET_ECR_EN1588(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
#define	ENET_ECR_DBGEN_MASK   (0x40U)
#define	ENET_ECR_DBGEN_SHIFT   (6U)
#define	ENET_ECR_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
#define	ENET_ECR_STOPEN_MASK   (0x80U)
#define	ENET_ECR_STOPEN_SHIFT   (7U)
#define	ENET_ECR_STOPEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
#define	ENET_ECR_DBSWP_MASK   (0x100U)
#define	ENET_ECR_DBSWP_SHIFT   (8U)
#define	ENET_ECR_DBSWP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
#define	ENET_ECR_RESET_MASK   0x1u
#define	ENET_ECR_RESET_SHIFT   0
#define	ENET_ECR_ETHEREN_MASK   0x2u
#define	ENET_ECR_ETHEREN_SHIFT   1
#define	ENET_ECR_MAGICEN_MASK   0x4u
#define	ENET_ECR_MAGICEN_SHIFT   2
#define	ENET_ECR_SLEEP_MASK   0x8u
#define	ENET_ECR_SLEEP_SHIFT   3
#define	ENET_ECR_EN1588_MASK   0x10u
#define	ENET_ECR_EN1588_SHIFT   4
#define	ENET_ECR_DBGEN_MASK   0x40u
#define	ENET_ECR_DBGEN_SHIFT   6
#define	ENET_ECR_STOPEN_MASK   0x80u
#define	ENET_ECR_STOPEN_SHIFT   7
#define	ENET_ECR_RESET_MASK   (0x1U)
#define	ENET_ECR_RESET_SHIFT   (0U)
#define	ENET_ECR_RESET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
#define	ENET_ECR_ETHEREN_MASK   (0x2U)
#define	ENET_ECR_ETHEREN_SHIFT   (1U)
#define	ENET_ECR_ETHEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
#define	ENET_ECR_MAGICEN_MASK   (0x4U)
#define	ENET_ECR_MAGICEN_SHIFT   (2U)
#define	ENET_ECR_MAGICEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
#define	ENET_ECR_SLEEP_MASK   (0x8U)
#define	ENET_ECR_SLEEP_SHIFT   (3U)
#define	ENET_ECR_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
#define	ENET_ECR_EN1588_MASK   (0x10U)
#define	ENET_ECR_EN1588_SHIFT   (4U)
#define	ENET_ECR_EN1588(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
#define	ENET_ECR_DBGEN_MASK   (0x40U)
#define	ENET_ECR_DBGEN_SHIFT   (6U)
#define	ENET_ECR_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
#define	ENET_ECR_STOPEN_MASK   (0x80U)
#define	ENET_ECR_STOPEN_SHIFT   (7U)
#define	ENET_ECR_STOPEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
#define	ENET_ECR_DBSWP_MASK   (0x100U)
#define	ENET_ECR_DBSWP_SHIFT   (8U)
#define	ENET_ECR_DBSWP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
#define	ENET_ECR_RESET_MASK   (0x1U)
#define	ENET_ECR_RESET_SHIFT   (0U)
#define	ENET_ECR_RESET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
#define	ENET_ECR_ETHEREN_MASK   (0x2U)
#define	ENET_ECR_ETHEREN_SHIFT   (1U)
#define	ENET_ECR_ETHEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
#define	ENET_ECR_MAGICEN_MASK   (0x4U)
#define	ENET_ECR_MAGICEN_SHIFT   (2U)
#define	ENET_ECR_MAGICEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
#define	ENET_ECR_SLEEP_MASK   (0x8U)
#define	ENET_ECR_SLEEP_SHIFT   (3U)
#define	ENET_ECR_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
#define	ENET_ECR_EN1588_MASK   (0x10U)
#define	ENET_ECR_EN1588_SHIFT   (4U)
#define	ENET_ECR_EN1588(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
#define	ENET_ECR_DBGEN_MASK   (0x40U)
#define	ENET_ECR_DBGEN_SHIFT   (6U)
#define	ENET_ECR_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
#define	ENET_ECR_STOPEN_MASK   (0x80U)
#define	ENET_ECR_STOPEN_SHIFT   (7U)
#define	ENET_ECR_STOPEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
#define	ENET_ECR_DBSWP_MASK   (0x100U)
#define	ENET_ECR_DBSWP_SHIFT   (8U)
#define	ENET_ECR_DBSWP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
#define	ENET_ECR_RESET_MASK   (0x1U)
#define	ENET_ECR_RESET_SHIFT   (0U)
#define	ENET_ECR_RESET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
#define	ENET_ECR_ETHEREN_MASK   (0x2U)
#define	ENET_ECR_ETHEREN_SHIFT   (1U)
#define	ENET_ECR_ETHEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
#define	ENET_ECR_MAGICEN_MASK   (0x4U)
#define	ENET_ECR_MAGICEN_SHIFT   (2U)
#define	ENET_ECR_MAGICEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
#define	ENET_ECR_SLEEP_MASK   (0x8U)
#define	ENET_ECR_SLEEP_SHIFT   (3U)
#define	ENET_ECR_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
#define	ENET_ECR_EN1588_MASK   (0x10U)
#define	ENET_ECR_EN1588_SHIFT   (4U)
#define	ENET_ECR_EN1588(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
#define	ENET_ECR_DBGEN_MASK   (0x40U)
#define	ENET_ECR_DBGEN_SHIFT   (6U)
#define	ENET_ECR_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
#define	ENET_ECR_STOPEN_MASK   (0x80U)
#define	ENET_ECR_STOPEN_SHIFT   (7U)
#define	ENET_ECR_STOPEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
#define	ENET_ECR_DBSWP_MASK   (0x100U)
#define	ENET_ECR_DBSWP_SHIFT   (8U)
#define	ENET_ECR_DBSWP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
#define	ENET_ECR_RESET_MASK   (0x1U)
#define	ENET_ECR_RESET_SHIFT   (0U)
#define	ENET_ECR_RESET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
#define	ENET_ECR_ETHEREN_MASK   (0x2U)
#define	ENET_ECR_ETHEREN_SHIFT   (1U)
#define	ENET_ECR_ETHEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
#define	ENET_ECR_MAGICEN_MASK   (0x4U)
#define	ENET_ECR_MAGICEN_SHIFT   (2U)
#define	ENET_ECR_MAGICEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
#define	ENET_ECR_SLEEP_MASK   (0x8U)
#define	ENET_ECR_SLEEP_SHIFT   (3U)
#define	ENET_ECR_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
#define	ENET_ECR_EN1588_MASK   (0x10U)
#define	ENET_ECR_EN1588_SHIFT   (4U)
#define	ENET_ECR_EN1588(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
#define	ENET_ECR_DBGEN_MASK   (0x40U)
#define	ENET_ECR_DBGEN_SHIFT   (6U)
#define	ENET_ECR_DBGEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
#define	ENET_ECR_STOPEN_MASK   (0x80U)
#define	ENET_ECR_STOPEN_SHIFT   (7U)
#define	ENET_ECR_STOPEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
#define	ENET_ECR_DBSWP_MASK   (0x100U)
#define	ENET_ECR_DBSWP_SHIFT   (8U)
#define	ENET_ECR_DBSWP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

MMFR - MII Management Frame Register
#define	ENET_MMFR_DATA_MASK   (0xFFFFU)
#define	ENET_MMFR_DATA_SHIFT   (0U)
#define	ENET_MMFR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
#define	ENET_MMFR_TA_MASK   (0x30000U)
#define	ENET_MMFR_TA_SHIFT   (16U)
#define	ENET_MMFR_TA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
#define	ENET_MMFR_RA_MASK   (0x7C0000U)
#define	ENET_MMFR_RA_SHIFT   (18U)
#define	ENET_MMFR_RA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
#define	ENET_MMFR_PA_MASK   (0xF800000U)
#define	ENET_MMFR_PA_SHIFT   (23U)
#define	ENET_MMFR_PA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
#define	ENET_MMFR_OP_MASK   (0x30000000U)
#define	ENET_MMFR_OP_SHIFT   (28U)
#define	ENET_MMFR_OP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
#define	ENET_MMFR_ST_MASK   (0xC0000000U)
#define	ENET_MMFR_ST_SHIFT   (30U)
#define	ENET_MMFR_ST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
#define	ENET_MMFR_DATA_MASK   0xFFFFu
#define	ENET_MMFR_DATA_SHIFT   0
#define	ENET_MMFR_DATA(x)   (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
#define	ENET_MMFR_TA_MASK   0x30000u
#define	ENET_MMFR_TA_SHIFT   16
#define	ENET_MMFR_TA(x)   (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
#define	ENET_MMFR_RA_MASK   0x7C0000u
#define	ENET_MMFR_RA_SHIFT   18
#define	ENET_MMFR_RA(x)   (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
#define	ENET_MMFR_PA_MASK   0xF800000u
#define	ENET_MMFR_PA_SHIFT   23
#define	ENET_MMFR_PA(x)   (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
#define	ENET_MMFR_OP_MASK   0x30000000u
#define	ENET_MMFR_OP_SHIFT   28
#define	ENET_MMFR_OP(x)   (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
#define	ENET_MMFR_ST_MASK   0xC0000000u
#define	ENET_MMFR_ST_SHIFT   30
#define	ENET_MMFR_ST(x)   (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
#define	ENET_MMFR_DATA_MASK   (0xFFFFU)
#define	ENET_MMFR_DATA_SHIFT   (0U)
#define	ENET_MMFR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
#define	ENET_MMFR_TA_MASK   (0x30000U)
#define	ENET_MMFR_TA_SHIFT   (16U)
#define	ENET_MMFR_TA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
#define	ENET_MMFR_RA_MASK   (0x7C0000U)
#define	ENET_MMFR_RA_SHIFT   (18U)
#define	ENET_MMFR_RA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
#define	ENET_MMFR_PA_MASK   (0xF800000U)
#define	ENET_MMFR_PA_SHIFT   (23U)
#define	ENET_MMFR_PA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
#define	ENET_MMFR_OP_MASK   (0x30000000U)
#define	ENET_MMFR_OP_SHIFT   (28U)
#define	ENET_MMFR_OP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
#define	ENET_MMFR_ST_MASK   (0xC0000000U)
#define	ENET_MMFR_ST_SHIFT   (30U)
#define	ENET_MMFR_ST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
#define	ENET_MMFR_DATA_MASK   (0xFFFFU)
#define	ENET_MMFR_DATA_SHIFT   (0U)
#define	ENET_MMFR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
#define	ENET_MMFR_TA_MASK   (0x30000U)
#define	ENET_MMFR_TA_SHIFT   (16U)
#define	ENET_MMFR_TA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
#define	ENET_MMFR_RA_MASK   (0x7C0000U)
#define	ENET_MMFR_RA_SHIFT   (18U)
#define	ENET_MMFR_RA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
#define	ENET_MMFR_PA_MASK   (0xF800000U)
#define	ENET_MMFR_PA_SHIFT   (23U)
#define	ENET_MMFR_PA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
#define	ENET_MMFR_OP_MASK   (0x30000000U)
#define	ENET_MMFR_OP_SHIFT   (28U)
#define	ENET_MMFR_OP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
#define	ENET_MMFR_ST_MASK   (0xC0000000U)
#define	ENET_MMFR_ST_SHIFT   (30U)
#define	ENET_MMFR_ST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
#define	ENET_MMFR_DATA_MASK   (0xFFFFU)
#define	ENET_MMFR_DATA_SHIFT   (0U)
#define	ENET_MMFR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
#define	ENET_MMFR_TA_MASK   (0x30000U)
#define	ENET_MMFR_TA_SHIFT   (16U)
#define	ENET_MMFR_TA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
#define	ENET_MMFR_RA_MASK   (0x7C0000U)
#define	ENET_MMFR_RA_SHIFT   (18U)
#define	ENET_MMFR_RA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
#define	ENET_MMFR_PA_MASK   (0xF800000U)
#define	ENET_MMFR_PA_SHIFT   (23U)
#define	ENET_MMFR_PA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
#define	ENET_MMFR_OP_MASK   (0x30000000U)
#define	ENET_MMFR_OP_SHIFT   (28U)
#define	ENET_MMFR_OP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
#define	ENET_MMFR_ST_MASK   (0xC0000000U)
#define	ENET_MMFR_ST_SHIFT   (30U)
#define	ENET_MMFR_ST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
#define	ENET_MMFR_DATA_MASK   (0xFFFFU)
#define	ENET_MMFR_DATA_SHIFT   (0U)
#define	ENET_MMFR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
#define	ENET_MMFR_TA_MASK   (0x30000U)
#define	ENET_MMFR_TA_SHIFT   (16U)
#define	ENET_MMFR_TA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
#define	ENET_MMFR_RA_MASK   (0x7C0000U)
#define	ENET_MMFR_RA_SHIFT   (18U)
#define	ENET_MMFR_RA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
#define	ENET_MMFR_PA_MASK   (0xF800000U)
#define	ENET_MMFR_PA_SHIFT   (23U)
#define	ENET_MMFR_PA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
#define	ENET_MMFR_OP_MASK   (0x30000000U)
#define	ENET_MMFR_OP_SHIFT   (28U)
#define	ENET_MMFR_OP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
#define	ENET_MMFR_ST_MASK   (0xC0000000U)
#define	ENET_MMFR_ST_SHIFT   (30U)
#define	ENET_MMFR_ST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)

MSCR - MII Speed Control Register
#define	ENET_MSCR_MII_SPEED_MASK   (0x7EU)
#define	ENET_MSCR_MII_SPEED_SHIFT   (1U)
#define	ENET_MSCR_MII_SPEED(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
#define	ENET_MSCR_DIS_PRE_MASK   (0x80U)
#define	ENET_MSCR_DIS_PRE_SHIFT   (7U)
#define	ENET_MSCR_DIS_PRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
#define	ENET_MSCR_HOLDTIME_MASK   (0x700U)
#define	ENET_MSCR_HOLDTIME_SHIFT   (8U)
#define	ENET_MSCR_HOLDTIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
#define	ENET_MSCR_MII_SPEED_MASK   0x7Eu
#define	ENET_MSCR_MII_SPEED_SHIFT   1
#define	ENET_MSCR_MII_SPEED(x)   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
#define	ENET_MSCR_DIS_PRE_MASK   0x80u
#define	ENET_MSCR_DIS_PRE_SHIFT   7
#define	ENET_MSCR_HOLDTIME_MASK   0x700u
#define	ENET_MSCR_HOLDTIME_SHIFT   8
#define	ENET_MSCR_HOLDTIME(x)   (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
#define	ENET_MSCR_MII_SPEED_MASK   (0x7EU)
#define	ENET_MSCR_MII_SPEED_SHIFT   (1U)
#define	ENET_MSCR_MII_SPEED(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
#define	ENET_MSCR_DIS_PRE_MASK   (0x80U)
#define	ENET_MSCR_DIS_PRE_SHIFT   (7U)
#define	ENET_MSCR_DIS_PRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
#define	ENET_MSCR_HOLDTIME_MASK   (0x700U)
#define	ENET_MSCR_HOLDTIME_SHIFT   (8U)
#define	ENET_MSCR_HOLDTIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
#define	ENET_MSCR_MII_SPEED_MASK   (0x7EU)
#define	ENET_MSCR_MII_SPEED_SHIFT   (1U)
#define	ENET_MSCR_MII_SPEED(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
#define	ENET_MSCR_DIS_PRE_MASK   (0x80U)
#define	ENET_MSCR_DIS_PRE_SHIFT   (7U)
#define	ENET_MSCR_DIS_PRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
#define	ENET_MSCR_HOLDTIME_MASK   (0x700U)
#define	ENET_MSCR_HOLDTIME_SHIFT   (8U)
#define	ENET_MSCR_HOLDTIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
#define	ENET_MSCR_MII_SPEED_MASK   (0x7EU)
#define	ENET_MSCR_MII_SPEED_SHIFT   (1U)
#define	ENET_MSCR_MII_SPEED(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
#define	ENET_MSCR_DIS_PRE_MASK   (0x80U)
#define	ENET_MSCR_DIS_PRE_SHIFT   (7U)
#define	ENET_MSCR_DIS_PRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
#define	ENET_MSCR_HOLDTIME_MASK   (0x700U)
#define	ENET_MSCR_HOLDTIME_SHIFT   (8U)
#define	ENET_MSCR_HOLDTIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
#define	ENET_MSCR_MII_SPEED_MASK   (0x7EU)
#define	ENET_MSCR_MII_SPEED_SHIFT   (1U)
#define	ENET_MSCR_MII_SPEED(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
#define	ENET_MSCR_DIS_PRE_MASK   (0x80U)
#define	ENET_MSCR_DIS_PRE_SHIFT   (7U)
#define	ENET_MSCR_DIS_PRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
#define	ENET_MSCR_HOLDTIME_MASK   (0x700U)
#define	ENET_MSCR_HOLDTIME_SHIFT   (8U)
#define	ENET_MSCR_HOLDTIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

MIBC - MIB Control Register
#define	ENET_MIBC_MIB_CLEAR_MASK   (0x20000000U)
#define	ENET_MIBC_MIB_CLEAR_SHIFT   (29U)
#define	ENET_MIBC_MIB_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
#define	ENET_MIBC_MIB_IDLE_MASK   (0x40000000U)
#define	ENET_MIBC_MIB_IDLE_SHIFT   (30U)
#define	ENET_MIBC_MIB_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
#define	ENET_MIBC_MIB_DIS_MASK   (0x80000000U)
#define	ENET_MIBC_MIB_DIS_SHIFT   (31U)
#define	ENET_MIBC_MIB_DIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
#define	ENET_MIBC_MIB_CLEAR_MASK   0x20000000u
#define	ENET_MIBC_MIB_CLEAR_SHIFT   29
#define	ENET_MIBC_MIB_IDLE_MASK   0x40000000u
#define	ENET_MIBC_MIB_IDLE_SHIFT   30
#define	ENET_MIBC_MIB_DIS_MASK   0x80000000u
#define	ENET_MIBC_MIB_DIS_SHIFT   31
#define	ENET_MIBC_MIB_CLEAR_MASK   (0x20000000U)
#define	ENET_MIBC_MIB_CLEAR_SHIFT   (29U)
#define	ENET_MIBC_MIB_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
#define	ENET_MIBC_MIB_IDLE_MASK   (0x40000000U)
#define	ENET_MIBC_MIB_IDLE_SHIFT   (30U)
#define	ENET_MIBC_MIB_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
#define	ENET_MIBC_MIB_DIS_MASK   (0x80000000U)
#define	ENET_MIBC_MIB_DIS_SHIFT   (31U)
#define	ENET_MIBC_MIB_DIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
#define	ENET_MIBC_MIB_CLEAR_MASK   (0x20000000U)
#define	ENET_MIBC_MIB_CLEAR_SHIFT   (29U)
#define	ENET_MIBC_MIB_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
#define	ENET_MIBC_MIB_IDLE_MASK   (0x40000000U)
#define	ENET_MIBC_MIB_IDLE_SHIFT   (30U)
#define	ENET_MIBC_MIB_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
#define	ENET_MIBC_MIB_DIS_MASK   (0x80000000U)
#define	ENET_MIBC_MIB_DIS_SHIFT   (31U)
#define	ENET_MIBC_MIB_DIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
#define	ENET_MIBC_MIB_CLEAR_MASK   (0x20000000U)
#define	ENET_MIBC_MIB_CLEAR_SHIFT   (29U)
#define	ENET_MIBC_MIB_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
#define	ENET_MIBC_MIB_IDLE_MASK   (0x40000000U)
#define	ENET_MIBC_MIB_IDLE_SHIFT   (30U)
#define	ENET_MIBC_MIB_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
#define	ENET_MIBC_MIB_DIS_MASK   (0x80000000U)
#define	ENET_MIBC_MIB_DIS_SHIFT   (31U)
#define	ENET_MIBC_MIB_DIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
#define	ENET_MIBC_MIB_CLEAR_MASK   (0x20000000U)
#define	ENET_MIBC_MIB_CLEAR_SHIFT   (29U)
#define	ENET_MIBC_MIB_CLEAR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
#define	ENET_MIBC_MIB_IDLE_MASK   (0x40000000U)
#define	ENET_MIBC_MIB_IDLE_SHIFT   (30U)
#define	ENET_MIBC_MIB_IDLE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
#define	ENET_MIBC_MIB_DIS_MASK   (0x80000000U)
#define	ENET_MIBC_MIB_DIS_SHIFT   (31U)
#define	ENET_MIBC_MIB_DIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

RCR - Receive Control Register
#define	ENET_RCR_LOOP_MASK   (0x1U)
#define	ENET_RCR_LOOP_SHIFT   (0U)
#define	ENET_RCR_LOOP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
#define	ENET_RCR_DRT_MASK   (0x2U)
#define	ENET_RCR_DRT_SHIFT   (1U)
#define	ENET_RCR_DRT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
#define	ENET_RCR_MII_MODE_MASK   (0x4U)
#define	ENET_RCR_MII_MODE_SHIFT   (2U)
#define	ENET_RCR_MII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
#define	ENET_RCR_PROM_MASK   (0x8U)
#define	ENET_RCR_PROM_SHIFT   (3U)
#define	ENET_RCR_PROM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
#define	ENET_RCR_BC_REJ_MASK   (0x10U)
#define	ENET_RCR_BC_REJ_SHIFT   (4U)
#define	ENET_RCR_BC_REJ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
#define	ENET_RCR_FCE_MASK   (0x20U)
#define	ENET_RCR_FCE_SHIFT   (5U)
#define	ENET_RCR_FCE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
#define	ENET_RCR_RMII_MODE_MASK   (0x100U)
#define	ENET_RCR_RMII_MODE_SHIFT   (8U)
#define	ENET_RCR_RMII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
#define	ENET_RCR_RMII_10T_MASK   (0x200U)
#define	ENET_RCR_RMII_10T_SHIFT   (9U)
#define	ENET_RCR_RMII_10T(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
#define	ENET_RCR_PADEN_MASK   (0x1000U)
#define	ENET_RCR_PADEN_SHIFT   (12U)
#define	ENET_RCR_PADEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
#define	ENET_RCR_PAUFWD_MASK   (0x2000U)
#define	ENET_RCR_PAUFWD_SHIFT   (13U)
#define	ENET_RCR_PAUFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
#define	ENET_RCR_CRCFWD_MASK   (0x4000U)
#define	ENET_RCR_CRCFWD_SHIFT   (14U)
#define	ENET_RCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
#define	ENET_RCR_CFEN_MASK   (0x8000U)
#define	ENET_RCR_CFEN_SHIFT   (15U)
#define	ENET_RCR_CFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
#define	ENET_RCR_MAX_FL_MASK   (0x3FFF0000U)
#define	ENET_RCR_MAX_FL_SHIFT   (16U)
#define	ENET_RCR_MAX_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
#define	ENET_RCR_NLC_MASK   (0x40000000U)
#define	ENET_RCR_NLC_SHIFT   (30U)
#define	ENET_RCR_NLC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
#define	ENET_RCR_GRS_MASK   (0x80000000U)
#define	ENET_RCR_GRS_SHIFT   (31U)
#define	ENET_RCR_GRS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
#define	ENET_RCR_LOOP_MASK   0x1u
#define	ENET_RCR_LOOP_SHIFT   0
#define	ENET_RCR_DRT_MASK   0x2u
#define	ENET_RCR_DRT_SHIFT   1
#define	ENET_RCR_MII_MODE_MASK   0x4u
#define	ENET_RCR_MII_MODE_SHIFT   2
#define	ENET_RCR_PROM_MASK   0x8u
#define	ENET_RCR_PROM_SHIFT   3
#define	ENET_RCR_BC_REJ_MASK   0x10u
#define	ENET_RCR_BC_REJ_SHIFT   4
#define	ENET_RCR_FCE_MASK   0x20u
#define	ENET_RCR_FCE_SHIFT   5
#define	ENET_RCR_RMII_MODE_MASK   0x100u
#define	ENET_RCR_RMII_MODE_SHIFT   8
#define	ENET_RCR_RMII_10T_MASK   0x200u
#define	ENET_RCR_RMII_10T_SHIFT   9
#define	ENET_RCR_PADEN_MASK   0x1000u
#define	ENET_RCR_PADEN_SHIFT   12
#define	ENET_RCR_PAUFWD_MASK   0x2000u
#define	ENET_RCR_PAUFWD_SHIFT   13
#define	ENET_RCR_CRCFWD_MASK   0x4000u
#define	ENET_RCR_CRCFWD_SHIFT   14
#define	ENET_RCR_CFEN_MASK   0x8000u
#define	ENET_RCR_CFEN_SHIFT   15
#define	ENET_RCR_MAX_FL_MASK   0x3FFF0000u
#define	ENET_RCR_MAX_FL_SHIFT   16
#define	ENET_RCR_MAX_FL(x)   (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
#define	ENET_RCR_NLC_MASK   0x40000000u
#define	ENET_RCR_NLC_SHIFT   30
#define	ENET_RCR_GRS_MASK   0x80000000u
#define	ENET_RCR_GRS_SHIFT   31
#define	ENET_RCR_LOOP_MASK   (0x1U)
#define	ENET_RCR_LOOP_SHIFT   (0U)
#define	ENET_RCR_LOOP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
#define	ENET_RCR_DRT_MASK   (0x2U)
#define	ENET_RCR_DRT_SHIFT   (1U)
#define	ENET_RCR_DRT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
#define	ENET_RCR_MII_MODE_MASK   (0x4U)
#define	ENET_RCR_MII_MODE_SHIFT   (2U)
#define	ENET_RCR_MII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
#define	ENET_RCR_PROM_MASK   (0x8U)
#define	ENET_RCR_PROM_SHIFT   (3U)
#define	ENET_RCR_PROM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
#define	ENET_RCR_BC_REJ_MASK   (0x10U)
#define	ENET_RCR_BC_REJ_SHIFT   (4U)
#define	ENET_RCR_BC_REJ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
#define	ENET_RCR_FCE_MASK   (0x20U)
#define	ENET_RCR_FCE_SHIFT   (5U)
#define	ENET_RCR_FCE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
#define	ENET_RCR_RMII_MODE_MASK   (0x100U)
#define	ENET_RCR_RMII_MODE_SHIFT   (8U)
#define	ENET_RCR_RMII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
#define	ENET_RCR_RMII_10T_MASK   (0x200U)
#define	ENET_RCR_RMII_10T_SHIFT   (9U)
#define	ENET_RCR_RMII_10T(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
#define	ENET_RCR_PADEN_MASK   (0x1000U)
#define	ENET_RCR_PADEN_SHIFT   (12U)
#define	ENET_RCR_PADEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
#define	ENET_RCR_PAUFWD_MASK   (0x2000U)
#define	ENET_RCR_PAUFWD_SHIFT   (13U)
#define	ENET_RCR_PAUFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
#define	ENET_RCR_CRCFWD_MASK   (0x4000U)
#define	ENET_RCR_CRCFWD_SHIFT   (14U)
#define	ENET_RCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
#define	ENET_RCR_CFEN_MASK   (0x8000U)
#define	ENET_RCR_CFEN_SHIFT   (15U)
#define	ENET_RCR_CFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
#define	ENET_RCR_MAX_FL_MASK   (0x3FFF0000U)
#define	ENET_RCR_MAX_FL_SHIFT   (16U)
#define	ENET_RCR_MAX_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
#define	ENET_RCR_NLC_MASK   (0x40000000U)
#define	ENET_RCR_NLC_SHIFT   (30U)
#define	ENET_RCR_NLC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
#define	ENET_RCR_GRS_MASK   (0x80000000U)
#define	ENET_RCR_GRS_SHIFT   (31U)
#define	ENET_RCR_GRS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
#define	ENET_RCR_LOOP_MASK   (0x1U)
#define	ENET_RCR_LOOP_SHIFT   (0U)
#define	ENET_RCR_LOOP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
#define	ENET_RCR_DRT_MASK   (0x2U)
#define	ENET_RCR_DRT_SHIFT   (1U)
#define	ENET_RCR_DRT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
#define	ENET_RCR_MII_MODE_MASK   (0x4U)
#define	ENET_RCR_MII_MODE_SHIFT   (2U)
#define	ENET_RCR_MII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
#define	ENET_RCR_PROM_MASK   (0x8U)
#define	ENET_RCR_PROM_SHIFT   (3U)
#define	ENET_RCR_PROM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
#define	ENET_RCR_BC_REJ_MASK   (0x10U)
#define	ENET_RCR_BC_REJ_SHIFT   (4U)
#define	ENET_RCR_BC_REJ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
#define	ENET_RCR_FCE_MASK   (0x20U)
#define	ENET_RCR_FCE_SHIFT   (5U)
#define	ENET_RCR_FCE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
#define	ENET_RCR_RMII_MODE_MASK   (0x100U)
#define	ENET_RCR_RMII_MODE_SHIFT   (8U)
#define	ENET_RCR_RMII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
#define	ENET_RCR_RMII_10T_MASK   (0x200U)
#define	ENET_RCR_RMII_10T_SHIFT   (9U)
#define	ENET_RCR_RMII_10T(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
#define	ENET_RCR_PADEN_MASK   (0x1000U)
#define	ENET_RCR_PADEN_SHIFT   (12U)
#define	ENET_RCR_PADEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
#define	ENET_RCR_PAUFWD_MASK   (0x2000U)
#define	ENET_RCR_PAUFWD_SHIFT   (13U)
#define	ENET_RCR_PAUFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
#define	ENET_RCR_CRCFWD_MASK   (0x4000U)
#define	ENET_RCR_CRCFWD_SHIFT   (14U)
#define	ENET_RCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
#define	ENET_RCR_CFEN_MASK   (0x8000U)
#define	ENET_RCR_CFEN_SHIFT   (15U)
#define	ENET_RCR_CFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
#define	ENET_RCR_MAX_FL_MASK   (0x3FFF0000U)
#define	ENET_RCR_MAX_FL_SHIFT   (16U)
#define	ENET_RCR_MAX_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
#define	ENET_RCR_NLC_MASK   (0x40000000U)
#define	ENET_RCR_NLC_SHIFT   (30U)
#define	ENET_RCR_NLC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
#define	ENET_RCR_GRS_MASK   (0x80000000U)
#define	ENET_RCR_GRS_SHIFT   (31U)
#define	ENET_RCR_GRS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
#define	ENET_RCR_LOOP_MASK   (0x1U)
#define	ENET_RCR_LOOP_SHIFT   (0U)
#define	ENET_RCR_LOOP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
#define	ENET_RCR_DRT_MASK   (0x2U)
#define	ENET_RCR_DRT_SHIFT   (1U)
#define	ENET_RCR_DRT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
#define	ENET_RCR_MII_MODE_MASK   (0x4U)
#define	ENET_RCR_MII_MODE_SHIFT   (2U)
#define	ENET_RCR_MII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
#define	ENET_RCR_PROM_MASK   (0x8U)
#define	ENET_RCR_PROM_SHIFT   (3U)
#define	ENET_RCR_PROM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
#define	ENET_RCR_BC_REJ_MASK   (0x10U)
#define	ENET_RCR_BC_REJ_SHIFT   (4U)
#define	ENET_RCR_BC_REJ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
#define	ENET_RCR_FCE_MASK   (0x20U)
#define	ENET_RCR_FCE_SHIFT   (5U)
#define	ENET_RCR_FCE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
#define	ENET_RCR_RMII_MODE_MASK   (0x100U)
#define	ENET_RCR_RMII_MODE_SHIFT   (8U)
#define	ENET_RCR_RMII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
#define	ENET_RCR_RMII_10T_MASK   (0x200U)
#define	ENET_RCR_RMII_10T_SHIFT   (9U)
#define	ENET_RCR_RMII_10T(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
#define	ENET_RCR_PADEN_MASK   (0x1000U)
#define	ENET_RCR_PADEN_SHIFT   (12U)
#define	ENET_RCR_PADEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
#define	ENET_RCR_PAUFWD_MASK   (0x2000U)
#define	ENET_RCR_PAUFWD_SHIFT   (13U)
#define	ENET_RCR_PAUFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
#define	ENET_RCR_CRCFWD_MASK   (0x4000U)
#define	ENET_RCR_CRCFWD_SHIFT   (14U)
#define	ENET_RCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
#define	ENET_RCR_CFEN_MASK   (0x8000U)
#define	ENET_RCR_CFEN_SHIFT   (15U)
#define	ENET_RCR_CFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
#define	ENET_RCR_MAX_FL_MASK   (0x3FFF0000U)
#define	ENET_RCR_MAX_FL_SHIFT   (16U)
#define	ENET_RCR_MAX_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
#define	ENET_RCR_NLC_MASK   (0x40000000U)
#define	ENET_RCR_NLC_SHIFT   (30U)
#define	ENET_RCR_NLC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
#define	ENET_RCR_GRS_MASK   (0x80000000U)
#define	ENET_RCR_GRS_SHIFT   (31U)
#define	ENET_RCR_GRS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
#define	ENET_RCR_LOOP_MASK   (0x1U)
#define	ENET_RCR_LOOP_SHIFT   (0U)
#define	ENET_RCR_LOOP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
#define	ENET_RCR_DRT_MASK   (0x2U)
#define	ENET_RCR_DRT_SHIFT   (1U)
#define	ENET_RCR_DRT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
#define	ENET_RCR_MII_MODE_MASK   (0x4U)
#define	ENET_RCR_MII_MODE_SHIFT   (2U)
#define	ENET_RCR_MII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
#define	ENET_RCR_PROM_MASK   (0x8U)
#define	ENET_RCR_PROM_SHIFT   (3U)
#define	ENET_RCR_PROM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
#define	ENET_RCR_BC_REJ_MASK   (0x10U)
#define	ENET_RCR_BC_REJ_SHIFT   (4U)
#define	ENET_RCR_BC_REJ(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
#define	ENET_RCR_FCE_MASK   (0x20U)
#define	ENET_RCR_FCE_SHIFT   (5U)
#define	ENET_RCR_FCE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
#define	ENET_RCR_RMII_MODE_MASK   (0x100U)
#define	ENET_RCR_RMII_MODE_SHIFT   (8U)
#define	ENET_RCR_RMII_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
#define	ENET_RCR_RMII_10T_MASK   (0x200U)
#define	ENET_RCR_RMII_10T_SHIFT   (9U)
#define	ENET_RCR_RMII_10T(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
#define	ENET_RCR_PADEN_MASK   (0x1000U)
#define	ENET_RCR_PADEN_SHIFT   (12U)
#define	ENET_RCR_PADEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
#define	ENET_RCR_PAUFWD_MASK   (0x2000U)
#define	ENET_RCR_PAUFWD_SHIFT   (13U)
#define	ENET_RCR_PAUFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
#define	ENET_RCR_CRCFWD_MASK   (0x4000U)
#define	ENET_RCR_CRCFWD_SHIFT   (14U)
#define	ENET_RCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
#define	ENET_RCR_CFEN_MASK   (0x8000U)
#define	ENET_RCR_CFEN_SHIFT   (15U)
#define	ENET_RCR_CFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
#define	ENET_RCR_MAX_FL_MASK   (0x3FFF0000U)
#define	ENET_RCR_MAX_FL_SHIFT   (16U)
#define	ENET_RCR_MAX_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
#define	ENET_RCR_NLC_MASK   (0x40000000U)
#define	ENET_RCR_NLC_SHIFT   (30U)
#define	ENET_RCR_NLC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
#define	ENET_RCR_GRS_MASK   (0x80000000U)
#define	ENET_RCR_GRS_SHIFT   (31U)
#define	ENET_RCR_GRS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)

TCR - Transmit Control Register
#define	ENET_TCR_GTS_MASK   (0x1U)
#define	ENET_TCR_GTS_SHIFT   (0U)
#define	ENET_TCR_GTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
#define	ENET_TCR_FDEN_MASK   (0x4U)
#define	ENET_TCR_FDEN_SHIFT   (2U)
#define	ENET_TCR_FDEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
#define	ENET_TCR_TFC_PAUSE_MASK   (0x8U)
#define	ENET_TCR_TFC_PAUSE_SHIFT   (3U)
#define	ENET_TCR_TFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
#define	ENET_TCR_RFC_PAUSE_MASK   (0x10U)
#define	ENET_TCR_RFC_PAUSE_SHIFT   (4U)
#define	ENET_TCR_RFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
#define	ENET_TCR_ADDSEL_MASK   (0xE0U)
#define	ENET_TCR_ADDSEL_SHIFT   (5U)
#define	ENET_TCR_ADDSEL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
#define	ENET_TCR_ADDINS_MASK   (0x100U)
#define	ENET_TCR_ADDINS_SHIFT   (8U)
#define	ENET_TCR_ADDINS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
#define	ENET_TCR_CRCFWD_MASK   (0x200U)
#define	ENET_TCR_CRCFWD_SHIFT   (9U)
#define	ENET_TCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
#define	ENET_TCR_GTS_MASK   0x1u
#define	ENET_TCR_GTS_SHIFT   0
#define	ENET_TCR_FDEN_MASK   0x4u
#define	ENET_TCR_FDEN_SHIFT   2
#define	ENET_TCR_TFC_PAUSE_MASK   0x8u
#define	ENET_TCR_TFC_PAUSE_SHIFT   3
#define	ENET_TCR_RFC_PAUSE_MASK   0x10u
#define	ENET_TCR_RFC_PAUSE_SHIFT   4
#define	ENET_TCR_ADDSEL_MASK   0xE0u
#define	ENET_TCR_ADDSEL_SHIFT   5
#define	ENET_TCR_ADDSEL(x)   (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
#define	ENET_TCR_ADDINS_MASK   0x100u
#define	ENET_TCR_ADDINS_SHIFT   8
#define	ENET_TCR_CRCFWD_MASK   0x200u
#define	ENET_TCR_CRCFWD_SHIFT   9
#define	ENET_TCR_GTS_MASK   (0x1U)
#define	ENET_TCR_GTS_SHIFT   (0U)
#define	ENET_TCR_GTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
#define	ENET_TCR_FDEN_MASK   (0x4U)
#define	ENET_TCR_FDEN_SHIFT   (2U)
#define	ENET_TCR_FDEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
#define	ENET_TCR_TFC_PAUSE_MASK   (0x8U)
#define	ENET_TCR_TFC_PAUSE_SHIFT   (3U)
#define	ENET_TCR_TFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
#define	ENET_TCR_RFC_PAUSE_MASK   (0x10U)
#define	ENET_TCR_RFC_PAUSE_SHIFT   (4U)
#define	ENET_TCR_RFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
#define	ENET_TCR_ADDSEL_MASK   (0xE0U)
#define	ENET_TCR_ADDSEL_SHIFT   (5U)
#define	ENET_TCR_ADDSEL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
#define	ENET_TCR_ADDINS_MASK   (0x100U)
#define	ENET_TCR_ADDINS_SHIFT   (8U)
#define	ENET_TCR_ADDINS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
#define	ENET_TCR_CRCFWD_MASK   (0x200U)
#define	ENET_TCR_CRCFWD_SHIFT   (9U)
#define	ENET_TCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
#define	ENET_TCR_GTS_MASK   (0x1U)
#define	ENET_TCR_GTS_SHIFT   (0U)
#define	ENET_TCR_GTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
#define	ENET_TCR_FDEN_MASK   (0x4U)
#define	ENET_TCR_FDEN_SHIFT   (2U)
#define	ENET_TCR_FDEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
#define	ENET_TCR_TFC_PAUSE_MASK   (0x8U)
#define	ENET_TCR_TFC_PAUSE_SHIFT   (3U)
#define	ENET_TCR_TFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
#define	ENET_TCR_RFC_PAUSE_MASK   (0x10U)
#define	ENET_TCR_RFC_PAUSE_SHIFT   (4U)
#define	ENET_TCR_RFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
#define	ENET_TCR_ADDSEL_MASK   (0xE0U)
#define	ENET_TCR_ADDSEL_SHIFT   (5U)
#define	ENET_TCR_ADDSEL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
#define	ENET_TCR_ADDINS_MASK   (0x100U)
#define	ENET_TCR_ADDINS_SHIFT   (8U)
#define	ENET_TCR_ADDINS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
#define	ENET_TCR_CRCFWD_MASK   (0x200U)
#define	ENET_TCR_CRCFWD_SHIFT   (9U)
#define	ENET_TCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
#define	ENET_TCR_GTS_MASK   (0x1U)
#define	ENET_TCR_GTS_SHIFT   (0U)
#define	ENET_TCR_GTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
#define	ENET_TCR_FDEN_MASK   (0x4U)
#define	ENET_TCR_FDEN_SHIFT   (2U)
#define	ENET_TCR_FDEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
#define	ENET_TCR_TFC_PAUSE_MASK   (0x8U)
#define	ENET_TCR_TFC_PAUSE_SHIFT   (3U)
#define	ENET_TCR_TFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
#define	ENET_TCR_RFC_PAUSE_MASK   (0x10U)
#define	ENET_TCR_RFC_PAUSE_SHIFT   (4U)
#define	ENET_TCR_RFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
#define	ENET_TCR_ADDSEL_MASK   (0xE0U)
#define	ENET_TCR_ADDSEL_SHIFT   (5U)
#define	ENET_TCR_ADDSEL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
#define	ENET_TCR_ADDINS_MASK   (0x100U)
#define	ENET_TCR_ADDINS_SHIFT   (8U)
#define	ENET_TCR_ADDINS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
#define	ENET_TCR_CRCFWD_MASK   (0x200U)
#define	ENET_TCR_CRCFWD_SHIFT   (9U)
#define	ENET_TCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
#define	ENET_TCR_GTS_MASK   (0x1U)
#define	ENET_TCR_GTS_SHIFT   (0U)
#define	ENET_TCR_GTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
#define	ENET_TCR_FDEN_MASK   (0x4U)
#define	ENET_TCR_FDEN_SHIFT   (2U)
#define	ENET_TCR_FDEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
#define	ENET_TCR_TFC_PAUSE_MASK   (0x8U)
#define	ENET_TCR_TFC_PAUSE_SHIFT   (3U)
#define	ENET_TCR_TFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
#define	ENET_TCR_RFC_PAUSE_MASK   (0x10U)
#define	ENET_TCR_RFC_PAUSE_SHIFT   (4U)
#define	ENET_TCR_RFC_PAUSE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
#define	ENET_TCR_ADDSEL_MASK   (0xE0U)
#define	ENET_TCR_ADDSEL_SHIFT   (5U)
#define	ENET_TCR_ADDSEL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
#define	ENET_TCR_ADDINS_MASK   (0x100U)
#define	ENET_TCR_ADDINS_SHIFT   (8U)
#define	ENET_TCR_ADDINS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
#define	ENET_TCR_CRCFWD_MASK   (0x200U)
#define	ENET_TCR_CRCFWD_SHIFT   (9U)
#define	ENET_TCR_CRCFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

PALR - Physical Address Lower Register
#define	ENET_PALR_PADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_PALR_PADDR1_SHIFT   (0U)
#define	ENET_PALR_PADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
#define	ENET_PALR_PADDR1_MASK   0xFFFFFFFFu
#define	ENET_PALR_PADDR1_SHIFT   0
#define	ENET_PALR_PADDR1(x)   (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
#define	ENET_PALR_PADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_PALR_PADDR1_SHIFT   (0U)
#define	ENET_PALR_PADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
#define	ENET_PALR_PADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_PALR_PADDR1_SHIFT   (0U)
#define	ENET_PALR_PADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
#define	ENET_PALR_PADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_PALR_PADDR1_SHIFT   (0U)
#define	ENET_PALR_PADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
#define	ENET_PALR_PADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_PALR_PADDR1_SHIFT   (0U)
#define	ENET_PALR_PADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)

PAUR - Physical Address Upper Register
#define	ENET_PAUR_TYPE_MASK   (0xFFFFU)
#define	ENET_PAUR_TYPE_SHIFT   (0U)
#define	ENET_PAUR_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
#define	ENET_PAUR_PADDR2_MASK   (0xFFFF0000U)
#define	ENET_PAUR_PADDR2_SHIFT   (16U)
#define	ENET_PAUR_PADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
#define	ENET_PAUR_TYPE_MASK   0xFFFFu
#define	ENET_PAUR_TYPE_SHIFT   0
#define	ENET_PAUR_TYPE(x)   (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
#define	ENET_PAUR_PADDR2_MASK   0xFFFF0000u
#define	ENET_PAUR_PADDR2_SHIFT   16
#define	ENET_PAUR_PADDR2(x)   (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
#define	ENET_PAUR_TYPE_MASK   (0xFFFFU)
#define	ENET_PAUR_TYPE_SHIFT   (0U)
#define	ENET_PAUR_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
#define	ENET_PAUR_PADDR2_MASK   (0xFFFF0000U)
#define	ENET_PAUR_PADDR2_SHIFT   (16U)
#define	ENET_PAUR_PADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
#define	ENET_PAUR_TYPE_MASK   (0xFFFFU)
#define	ENET_PAUR_TYPE_SHIFT   (0U)
#define	ENET_PAUR_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
#define	ENET_PAUR_PADDR2_MASK   (0xFFFF0000U)
#define	ENET_PAUR_PADDR2_SHIFT   (16U)
#define	ENET_PAUR_PADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
#define	ENET_PAUR_TYPE_MASK   (0xFFFFU)
#define	ENET_PAUR_TYPE_SHIFT   (0U)
#define	ENET_PAUR_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
#define	ENET_PAUR_PADDR2_MASK   (0xFFFF0000U)
#define	ENET_PAUR_PADDR2_SHIFT   (16U)
#define	ENET_PAUR_PADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
#define	ENET_PAUR_TYPE_MASK   (0xFFFFU)
#define	ENET_PAUR_TYPE_SHIFT   (0U)
#define	ENET_PAUR_TYPE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
#define	ENET_PAUR_PADDR2_MASK   (0xFFFF0000U)
#define	ENET_PAUR_PADDR2_SHIFT   (16U)
#define	ENET_PAUR_PADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)

OPD - Opcode/Pause Duration Register
#define	ENET_OPD_PAUSE_DUR_MASK   (0xFFFFU)
#define	ENET_OPD_PAUSE_DUR_SHIFT   (0U)
#define	ENET_OPD_PAUSE_DUR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
#define	ENET_OPD_OPCODE_MASK   (0xFFFF0000U)
#define	ENET_OPD_OPCODE_SHIFT   (16U)
#define	ENET_OPD_OPCODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
#define	ENET_OPD_PAUSE_DUR_MASK   0xFFFFu
#define	ENET_OPD_PAUSE_DUR_SHIFT   0
#define	ENET_OPD_PAUSE_DUR(x)   (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
#define	ENET_OPD_OPCODE_MASK   0xFFFF0000u
#define	ENET_OPD_OPCODE_SHIFT   16
#define	ENET_OPD_OPCODE(x)   (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
#define	ENET_OPD_PAUSE_DUR_MASK   (0xFFFFU)
#define	ENET_OPD_PAUSE_DUR_SHIFT   (0U)
#define	ENET_OPD_PAUSE_DUR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
#define	ENET_OPD_OPCODE_MASK   (0xFFFF0000U)
#define	ENET_OPD_OPCODE_SHIFT   (16U)
#define	ENET_OPD_OPCODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
#define	ENET_OPD_PAUSE_DUR_MASK   (0xFFFFU)
#define	ENET_OPD_PAUSE_DUR_SHIFT   (0U)
#define	ENET_OPD_PAUSE_DUR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
#define	ENET_OPD_OPCODE_MASK   (0xFFFF0000U)
#define	ENET_OPD_OPCODE_SHIFT   (16U)
#define	ENET_OPD_OPCODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
#define	ENET_OPD_PAUSE_DUR_MASK   (0xFFFFU)
#define	ENET_OPD_PAUSE_DUR_SHIFT   (0U)
#define	ENET_OPD_PAUSE_DUR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
#define	ENET_OPD_OPCODE_MASK   (0xFFFF0000U)
#define	ENET_OPD_OPCODE_SHIFT   (16U)
#define	ENET_OPD_OPCODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
#define	ENET_OPD_PAUSE_DUR_MASK   (0xFFFFU)
#define	ENET_OPD_PAUSE_DUR_SHIFT   (0U)
#define	ENET_OPD_PAUSE_DUR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
#define	ENET_OPD_OPCODE_MASK   (0xFFFF0000U)
#define	ENET_OPD_OPCODE_SHIFT   (16U)
#define	ENET_OPD_OPCODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)

IAUR - Descriptor Individual Upper Address Register
#define	ENET_IAUR_IADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_IAUR_IADDR1_SHIFT   (0U)
#define	ENET_IAUR_IADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
#define	ENET_IAUR_IADDR1_MASK   0xFFFFFFFFu
#define	ENET_IAUR_IADDR1_SHIFT   0
#define	ENET_IAUR_IADDR1(x)   (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
#define	ENET_IAUR_IADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_IAUR_IADDR1_SHIFT   (0U)
#define	ENET_IAUR_IADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
#define	ENET_IAUR_IADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_IAUR_IADDR1_SHIFT   (0U)
#define	ENET_IAUR_IADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
#define	ENET_IAUR_IADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_IAUR_IADDR1_SHIFT   (0U)
#define	ENET_IAUR_IADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
#define	ENET_IAUR_IADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_IAUR_IADDR1_SHIFT   (0U)
#define	ENET_IAUR_IADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)

IALR - Descriptor Individual Lower Address Register
#define	ENET_IALR_IADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_IALR_IADDR2_SHIFT   (0U)
#define	ENET_IALR_IADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
#define	ENET_IALR_IADDR2_MASK   0xFFFFFFFFu
#define	ENET_IALR_IADDR2_SHIFT   0
#define	ENET_IALR_IADDR2(x)   (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
#define	ENET_IALR_IADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_IALR_IADDR2_SHIFT   (0U)
#define	ENET_IALR_IADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
#define	ENET_IALR_IADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_IALR_IADDR2_SHIFT   (0U)
#define	ENET_IALR_IADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
#define	ENET_IALR_IADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_IALR_IADDR2_SHIFT   (0U)
#define	ENET_IALR_IADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
#define	ENET_IALR_IADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_IALR_IADDR2_SHIFT   (0U)
#define	ENET_IALR_IADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)

GAUR - Descriptor Group Upper Address Register
#define	ENET_GAUR_GADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_GAUR_GADDR1_SHIFT   (0U)
#define	ENET_GAUR_GADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
#define	ENET_GAUR_GADDR1_MASK   0xFFFFFFFFu
#define	ENET_GAUR_GADDR1_SHIFT   0
#define	ENET_GAUR_GADDR1(x)   (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
#define	ENET_GAUR_GADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_GAUR_GADDR1_SHIFT   (0U)
#define	ENET_GAUR_GADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
#define	ENET_GAUR_GADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_GAUR_GADDR1_SHIFT   (0U)
#define	ENET_GAUR_GADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
#define	ENET_GAUR_GADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_GAUR_GADDR1_SHIFT   (0U)
#define	ENET_GAUR_GADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
#define	ENET_GAUR_GADDR1_MASK   (0xFFFFFFFFU)
#define	ENET_GAUR_GADDR1_SHIFT   (0U)
#define	ENET_GAUR_GADDR1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)

GALR - Descriptor Group Lower Address Register
#define	ENET_GALR_GADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_GALR_GADDR2_SHIFT   (0U)
#define	ENET_GALR_GADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
#define	ENET_GALR_GADDR2_MASK   0xFFFFFFFFu
#define	ENET_GALR_GADDR2_SHIFT   0
#define	ENET_GALR_GADDR2(x)   (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
#define	ENET_GALR_GADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_GALR_GADDR2_SHIFT   (0U)
#define	ENET_GALR_GADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
#define	ENET_GALR_GADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_GALR_GADDR2_SHIFT   (0U)
#define	ENET_GALR_GADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
#define	ENET_GALR_GADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_GALR_GADDR2_SHIFT   (0U)
#define	ENET_GALR_GADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
#define	ENET_GALR_GADDR2_MASK   (0xFFFFFFFFU)
#define	ENET_GALR_GADDR2_SHIFT   (0U)
#define	ENET_GALR_GADDR2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)

TFWR - Transmit FIFO Watermark Register
#define	ENET_TFWR_TFWR_MASK   (0x3FU)
#define	ENET_TFWR_TFWR_SHIFT   (0U)
#define	ENET_TFWR_TFWR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
#define	ENET_TFWR_STRFWD_MASK   (0x100U)
#define	ENET_TFWR_STRFWD_SHIFT   (8U)
#define	ENET_TFWR_STRFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
#define	ENET_TFWR_TFWR_MASK   0x3Fu
#define	ENET_TFWR_TFWR_SHIFT   0
#define	ENET_TFWR_TFWR(x)   (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
#define	ENET_TFWR_STRFWD_MASK   0x100u
#define	ENET_TFWR_STRFWD_SHIFT   8
#define	ENET_TFWR_TFWR_MASK   (0x3FU)
#define	ENET_TFWR_TFWR_SHIFT   (0U)
#define	ENET_TFWR_TFWR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
#define	ENET_TFWR_STRFWD_MASK   (0x100U)
#define	ENET_TFWR_STRFWD_SHIFT   (8U)
#define	ENET_TFWR_STRFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
#define	ENET_TFWR_TFWR_MASK   (0x3FU)
#define	ENET_TFWR_TFWR_SHIFT   (0U)
#define	ENET_TFWR_TFWR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
#define	ENET_TFWR_STRFWD_MASK   (0x100U)
#define	ENET_TFWR_STRFWD_SHIFT   (8U)
#define	ENET_TFWR_STRFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
#define	ENET_TFWR_TFWR_MASK   (0x3FU)
#define	ENET_TFWR_TFWR_SHIFT   (0U)
#define	ENET_TFWR_TFWR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
#define	ENET_TFWR_STRFWD_MASK   (0x100U)
#define	ENET_TFWR_STRFWD_SHIFT   (8U)
#define	ENET_TFWR_STRFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
#define	ENET_TFWR_TFWR_MASK   (0x3FU)
#define	ENET_TFWR_TFWR_SHIFT   (0U)
#define	ENET_TFWR_TFWR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
#define	ENET_TFWR_STRFWD_MASK   (0x100U)
#define	ENET_TFWR_STRFWD_SHIFT   (8U)
#define	ENET_TFWR_STRFWD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

RDSR - Receive Descriptor Ring Start Register
#define	ENET_RDSR_R_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_RDSR_R_DES_START_SHIFT   (3U)
#define	ENET_RDSR_R_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
#define	ENET_RDSR_R_DES_START_MASK   0xFFFFFFF8u
#define	ENET_RDSR_R_DES_START_SHIFT   3
#define	ENET_RDSR_R_DES_START(x)   (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
#define	ENET_RDSR_R_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_RDSR_R_DES_START_SHIFT   (3U)
#define	ENET_RDSR_R_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
#define	ENET_RDSR_R_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_RDSR_R_DES_START_SHIFT   (3U)
#define	ENET_RDSR_R_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
#define	ENET_RDSR_R_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_RDSR_R_DES_START_SHIFT   (3U)
#define	ENET_RDSR_R_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
#define	ENET_RDSR_R_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_RDSR_R_DES_START_SHIFT   (3U)
#define	ENET_RDSR_R_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)

TDSR - Transmit Buffer Descriptor Ring Start Register
#define	ENET_TDSR_X_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_TDSR_X_DES_START_SHIFT   (3U)
#define	ENET_TDSR_X_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
#define	ENET_TDSR_X_DES_START_MASK   0xFFFFFFF8u
#define	ENET_TDSR_X_DES_START_SHIFT   3
#define	ENET_TDSR_X_DES_START(x)   (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
#define	ENET_TDSR_X_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_TDSR_X_DES_START_SHIFT   (3U)
#define	ENET_TDSR_X_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
#define	ENET_TDSR_X_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_TDSR_X_DES_START_SHIFT   (3U)
#define	ENET_TDSR_X_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
#define	ENET_TDSR_X_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_TDSR_X_DES_START_SHIFT   (3U)
#define	ENET_TDSR_X_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
#define	ENET_TDSR_X_DES_START_MASK   (0xFFFFFFF8U)
#define	ENET_TDSR_X_DES_START_SHIFT   (3U)
#define	ENET_TDSR_X_DES_START(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)

MRBR - Maximum Receive Buffer Size Register
#define	ENET_MRBR_R_BUF_SIZE_MASK   (0x3FF0U)
#define	ENET_MRBR_R_BUF_SIZE_SHIFT   (4U)
#define	ENET_MRBR_R_BUF_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
#define	ENET_MRBR_R_BUF_SIZE_MASK   0x3FF0u
#define	ENET_MRBR_R_BUF_SIZE_SHIFT   4
#define	ENET_MRBR_R_BUF_SIZE(x)   (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
#define	ENET_MRBR_R_BUF_SIZE_MASK   (0x3FF0U)
#define	ENET_MRBR_R_BUF_SIZE_SHIFT   (4U)
#define	ENET_MRBR_R_BUF_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
#define	ENET_MRBR_R_BUF_SIZE_MASK   (0x7F0U)
#define	ENET_MRBR_R_BUF_SIZE_SHIFT   (4U)
#define	ENET_MRBR_R_BUF_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
#define	ENET_MRBR_R_BUF_SIZE_MASK   (0x7F0U)
#define	ENET_MRBR_R_BUF_SIZE_SHIFT   (4U)
#define	ENET_MRBR_R_BUF_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
#define	ENET_MRBR_R_BUF_SIZE_MASK   (0x7F0U)
#define	ENET_MRBR_R_BUF_SIZE_SHIFT   (4U)
#define	ENET_MRBR_R_BUF_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)

RSFL - Receive FIFO Section Full Threshold
#define	ENET_RSFL_RX_SECTION_FULL_MASK   (0xFFU)
#define	ENET_RSFL_RX_SECTION_FULL_SHIFT   (0U)
#define	ENET_RSFL_RX_SECTION_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
#define	ENET_RSFL_RX_SECTION_FULL_MASK   0xFFu
#define	ENET_RSFL_RX_SECTION_FULL_SHIFT   0
#define	ENET_RSFL_RX_SECTION_FULL(x)   (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
#define	ENET_RSFL_RX_SECTION_FULL_MASK   (0xFFU)
#define	ENET_RSFL_RX_SECTION_FULL_SHIFT   (0U)
#define	ENET_RSFL_RX_SECTION_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
#define	ENET_RSFL_RX_SECTION_FULL_MASK   (0xFFU)
#define	ENET_RSFL_RX_SECTION_FULL_SHIFT   (0U)
#define	ENET_RSFL_RX_SECTION_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
#define	ENET_RSFL_RX_SECTION_FULL_MASK   (0xFFU)
#define	ENET_RSFL_RX_SECTION_FULL_SHIFT   (0U)
#define	ENET_RSFL_RX_SECTION_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
#define	ENET_RSFL_RX_SECTION_FULL_MASK   (0xFFU)
#define	ENET_RSFL_RX_SECTION_FULL_SHIFT   (0U)
#define	ENET_RSFL_RX_SECTION_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)

RSEM - Receive FIFO Section Empty Threshold
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_RSEM_RX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK   0xFFu
#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT   0
#define	ENET_RSEM_RX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_RSEM_RX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define	ENET_RSEM_STAT_SECTION_EMPTY_MASK   (0x1F0000U)
#define	ENET_RSEM_STAT_SECTION_EMPTY_SHIFT   (16U)
#define	ENET_RSEM_STAT_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_RSEM_RX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define	ENET_RSEM_STAT_SECTION_EMPTY_MASK   (0x1F0000U)
#define	ENET_RSEM_STAT_SECTION_EMPTY_SHIFT   (16U)
#define	ENET_RSEM_STAT_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_RSEM_RX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define	ENET_RSEM_STAT_SECTION_EMPTY_MASK   (0x1F0000U)
#define	ENET_RSEM_STAT_SECTION_EMPTY_SHIFT   (16U)
#define	ENET_RSEM_STAT_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
#define	ENET_RSEM_RX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_RSEM_RX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_RSEM_RX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
#define	ENET_RSEM_STAT_SECTION_EMPTY_MASK   (0x1F0000U)
#define	ENET_RSEM_STAT_SECTION_EMPTY_SHIFT   (16U)
#define	ENET_RSEM_STAT_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)

RAEM - Receive FIFO Almost Empty Threshold
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_RAEM_RX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK   0xFFu
#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT   0
#define	ENET_RAEM_RX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_RAEM_RX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_RAEM_RX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_RAEM_RX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
#define	ENET_RAEM_RX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_RAEM_RX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_RAEM_RX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)

RAFL - Receive FIFO Almost Full Threshold
#define	ENET_RAFL_RX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_RAFL_RX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
#define	ENET_RAFL_RX_ALMOST_FULL_MASK   0xFFu
#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT   0
#define	ENET_RAFL_RX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
#define	ENET_RAFL_RX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_RAFL_RX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
#define	ENET_RAFL_RX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_RAFL_RX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
#define	ENET_RAFL_RX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_RAFL_RX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
#define	ENET_RAFL_RX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_RAFL_RX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_RAFL_RX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)

TSEM - Transmit FIFO Section Empty Threshold
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_TSEM_TX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK   0xFFu
#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT   0
#define	ENET_TSEM_TX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_TSEM_TX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_TSEM_TX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_TSEM_TX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
#define	ENET_TSEM_TX_SECTION_EMPTY_MASK   (0xFFU)
#define	ENET_TSEM_TX_SECTION_EMPTY_SHIFT   (0U)
#define	ENET_TSEM_TX_SECTION_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)

TAEM - Transmit FIFO Almost Empty Threshold
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_TAEM_TX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK   0xFFu
#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT   0
#define	ENET_TAEM_TX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_TAEM_TX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_TAEM_TX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_TAEM_TX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
#define	ENET_TAEM_TX_ALMOST_EMPTY_MASK   (0xFFU)
#define	ENET_TAEM_TX_ALMOST_EMPTY_SHIFT   (0U)
#define	ENET_TAEM_TX_ALMOST_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)

TAFL - Transmit FIFO Almost Full Threshold
#define	ENET_TAFL_TX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_TAFL_TX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
#define	ENET_TAFL_TX_ALMOST_FULL_MASK   0xFFu
#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT   0
#define	ENET_TAFL_TX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
#define	ENET_TAFL_TX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_TAFL_TX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
#define	ENET_TAFL_TX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_TAFL_TX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
#define	ENET_TAFL_TX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_TAFL_TX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
#define	ENET_TAFL_TX_ALMOST_FULL_MASK   (0xFFU)
#define	ENET_TAFL_TX_ALMOST_FULL_SHIFT   (0U)
#define	ENET_TAFL_TX_ALMOST_FULL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)

TIPG - Transmit Inter-Packet Gap
#define	ENET_TIPG_IPG_MASK   (0x1FU)
#define	ENET_TIPG_IPG_SHIFT   (0U)
#define	ENET_TIPG_IPG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
#define	ENET_TIPG_IPG_MASK   0x1Fu
#define	ENET_TIPG_IPG_SHIFT   0
#define	ENET_TIPG_IPG(x)   (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
#define	ENET_TIPG_IPG_MASK   (0x1FU)
#define	ENET_TIPG_IPG_SHIFT   (0U)
#define	ENET_TIPG_IPG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
#define	ENET_TIPG_IPG_MASK   (0x1FU)
#define	ENET_TIPG_IPG_SHIFT   (0U)
#define	ENET_TIPG_IPG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
#define	ENET_TIPG_IPG_MASK   (0x1FU)
#define	ENET_TIPG_IPG_SHIFT   (0U)
#define	ENET_TIPG_IPG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
#define	ENET_TIPG_IPG_MASK   (0x1FU)
#define	ENET_TIPG_IPG_SHIFT   (0U)
#define	ENET_TIPG_IPG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)

FTRL - Frame Truncation Length
#define	ENET_FTRL_TRUNC_FL_MASK   (0x3FFFU)
#define	ENET_FTRL_TRUNC_FL_SHIFT   (0U)
#define	ENET_FTRL_TRUNC_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
#define	ENET_FTRL_TRUNC_FL_MASK   0x3FFFu
#define	ENET_FTRL_TRUNC_FL_SHIFT   0
#define	ENET_FTRL_TRUNC_FL(x)   (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
#define	ENET_FTRL_TRUNC_FL_MASK   (0x3FFFU)
#define	ENET_FTRL_TRUNC_FL_SHIFT   (0U)
#define	ENET_FTRL_TRUNC_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
#define	ENET_FTRL_TRUNC_FL_MASK   (0x3FFFU)
#define	ENET_FTRL_TRUNC_FL_SHIFT   (0U)
#define	ENET_FTRL_TRUNC_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
#define	ENET_FTRL_TRUNC_FL_MASK   (0x3FFFU)
#define	ENET_FTRL_TRUNC_FL_SHIFT   (0U)
#define	ENET_FTRL_TRUNC_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
#define	ENET_FTRL_TRUNC_FL_MASK   (0x3FFFU)
#define	ENET_FTRL_TRUNC_FL_SHIFT   (0U)
#define	ENET_FTRL_TRUNC_FL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)

TACC - Transmit Accelerator Function Configuration
#define	ENET_TACC_SHIFT16_MASK   (0x1U)
#define	ENET_TACC_SHIFT16_SHIFT   (0U)
#define	ENET_TACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
#define	ENET_TACC_IPCHK_MASK   (0x8U)
#define	ENET_TACC_IPCHK_SHIFT   (3U)
#define	ENET_TACC_IPCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
#define	ENET_TACC_PROCHK_MASK   (0x10U)
#define	ENET_TACC_PROCHK_SHIFT   (4U)
#define	ENET_TACC_PROCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
#define	ENET_TACC_SHIFT16_MASK   0x1u
#define	ENET_TACC_SHIFT16_SHIFT   0
#define	ENET_TACC_IPCHK_MASK   0x8u
#define	ENET_TACC_IPCHK_SHIFT   3
#define	ENET_TACC_PROCHK_MASK   0x10u
#define	ENET_TACC_PROCHK_SHIFT   4
#define	ENET_TACC_SHIFT16_MASK   (0x1U)
#define	ENET_TACC_SHIFT16_SHIFT   (0U)
#define	ENET_TACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
#define	ENET_TACC_IPCHK_MASK   (0x8U)
#define	ENET_TACC_IPCHK_SHIFT   (3U)
#define	ENET_TACC_IPCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
#define	ENET_TACC_PROCHK_MASK   (0x10U)
#define	ENET_TACC_PROCHK_SHIFT   (4U)
#define	ENET_TACC_PROCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
#define	ENET_TACC_SHIFT16_MASK   (0x1U)
#define	ENET_TACC_SHIFT16_SHIFT   (0U)
#define	ENET_TACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
#define	ENET_TACC_IPCHK_MASK   (0x8U)
#define	ENET_TACC_IPCHK_SHIFT   (3U)
#define	ENET_TACC_IPCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
#define	ENET_TACC_PROCHK_MASK   (0x10U)
#define	ENET_TACC_PROCHK_SHIFT   (4U)
#define	ENET_TACC_PROCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
#define	ENET_TACC_SHIFT16_MASK   (0x1U)
#define	ENET_TACC_SHIFT16_SHIFT   (0U)
#define	ENET_TACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
#define	ENET_TACC_IPCHK_MASK   (0x8U)
#define	ENET_TACC_IPCHK_SHIFT   (3U)
#define	ENET_TACC_IPCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
#define	ENET_TACC_PROCHK_MASK   (0x10U)
#define	ENET_TACC_PROCHK_SHIFT   (4U)
#define	ENET_TACC_PROCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
#define	ENET_TACC_SHIFT16_MASK   (0x1U)
#define	ENET_TACC_SHIFT16_SHIFT   (0U)
#define	ENET_TACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
#define	ENET_TACC_IPCHK_MASK   (0x8U)
#define	ENET_TACC_IPCHK_SHIFT   (3U)
#define	ENET_TACC_IPCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
#define	ENET_TACC_PROCHK_MASK   (0x10U)
#define	ENET_TACC_PROCHK_SHIFT   (4U)
#define	ENET_TACC_PROCHK(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

RACC - Receive Accelerator Function Configuration
#define	ENET_RACC_PADREM_MASK   (0x1U)
#define	ENET_RACC_PADREM_SHIFT   (0U)
#define	ENET_RACC_PADREM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
#define	ENET_RACC_IPDIS_MASK   (0x2U)
#define	ENET_RACC_IPDIS_SHIFT   (1U)
#define	ENET_RACC_IPDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
#define	ENET_RACC_PRODIS_MASK   (0x4U)
#define	ENET_RACC_PRODIS_SHIFT   (2U)
#define	ENET_RACC_PRODIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
#define	ENET_RACC_LINEDIS_MASK   (0x40U)
#define	ENET_RACC_LINEDIS_SHIFT   (6U)
#define	ENET_RACC_LINEDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
#define	ENET_RACC_SHIFT16_MASK   (0x80U)
#define	ENET_RACC_SHIFT16_SHIFT   (7U)
#define	ENET_RACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
#define	ENET_RACC_PADREM_MASK   0x1u
#define	ENET_RACC_PADREM_SHIFT   0
#define	ENET_RACC_IPDIS_MASK   0x2u
#define	ENET_RACC_IPDIS_SHIFT   1
#define	ENET_RACC_PRODIS_MASK   0x4u
#define	ENET_RACC_PRODIS_SHIFT   2
#define	ENET_RACC_LINEDIS_MASK   0x40u
#define	ENET_RACC_LINEDIS_SHIFT   6
#define	ENET_RACC_SHIFT16_MASK   0x80u
#define	ENET_RACC_SHIFT16_SHIFT   7
#define	ENET_RACC_PADREM_MASK   (0x1U)
#define	ENET_RACC_PADREM_SHIFT   (0U)
#define	ENET_RACC_PADREM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
#define	ENET_RACC_IPDIS_MASK   (0x2U)
#define	ENET_RACC_IPDIS_SHIFT   (1U)
#define	ENET_RACC_IPDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
#define	ENET_RACC_PRODIS_MASK   (0x4U)
#define	ENET_RACC_PRODIS_SHIFT   (2U)
#define	ENET_RACC_PRODIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
#define	ENET_RACC_LINEDIS_MASK   (0x40U)
#define	ENET_RACC_LINEDIS_SHIFT   (6U)
#define	ENET_RACC_LINEDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
#define	ENET_RACC_SHIFT16_MASK   (0x80U)
#define	ENET_RACC_SHIFT16_SHIFT   (7U)
#define	ENET_RACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
#define	ENET_RACC_PADREM_MASK   (0x1U)
#define	ENET_RACC_PADREM_SHIFT   (0U)
#define	ENET_RACC_PADREM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
#define	ENET_RACC_IPDIS_MASK   (0x2U)
#define	ENET_RACC_IPDIS_SHIFT   (1U)
#define	ENET_RACC_IPDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
#define	ENET_RACC_PRODIS_MASK   (0x4U)
#define	ENET_RACC_PRODIS_SHIFT   (2U)
#define	ENET_RACC_PRODIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
#define	ENET_RACC_LINEDIS_MASK   (0x40U)
#define	ENET_RACC_LINEDIS_SHIFT   (6U)
#define	ENET_RACC_LINEDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
#define	ENET_RACC_SHIFT16_MASK   (0x80U)
#define	ENET_RACC_SHIFT16_SHIFT   (7U)
#define	ENET_RACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
#define	ENET_RACC_PADREM_MASK   (0x1U)
#define	ENET_RACC_PADREM_SHIFT   (0U)
#define	ENET_RACC_PADREM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
#define	ENET_RACC_IPDIS_MASK   (0x2U)
#define	ENET_RACC_IPDIS_SHIFT   (1U)
#define	ENET_RACC_IPDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
#define	ENET_RACC_PRODIS_MASK   (0x4U)
#define	ENET_RACC_PRODIS_SHIFT   (2U)
#define	ENET_RACC_PRODIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
#define	ENET_RACC_LINEDIS_MASK   (0x40U)
#define	ENET_RACC_LINEDIS_SHIFT   (6U)
#define	ENET_RACC_LINEDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
#define	ENET_RACC_SHIFT16_MASK   (0x80U)
#define	ENET_RACC_SHIFT16_SHIFT   (7U)
#define	ENET_RACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
#define	ENET_RACC_PADREM_MASK   (0x1U)
#define	ENET_RACC_PADREM_SHIFT   (0U)
#define	ENET_RACC_PADREM(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
#define	ENET_RACC_IPDIS_MASK   (0x2U)
#define	ENET_RACC_IPDIS_SHIFT   (1U)
#define	ENET_RACC_IPDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
#define	ENET_RACC_PRODIS_MASK   (0x4U)
#define	ENET_RACC_PRODIS_SHIFT   (2U)
#define	ENET_RACC_PRODIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
#define	ENET_RACC_LINEDIS_MASK   (0x40U)
#define	ENET_RACC_LINEDIS_SHIFT   (6U)
#define	ENET_RACC_LINEDIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
#define	ENET_RACC_SHIFT16_MASK   (0x80U)
#define	ENET_RACC_SHIFT16_SHIFT   (7U)
#define	ENET_RACC_SHIFT16(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

RMON_T_PACKETS - Tx Packet Count Statistic Register
#define	ENET_RMON_T_PACKETS_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_PACKETS_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
#define	ENET_RMON_T_PACKETS_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_PACKETS_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
#define	ENET_RMON_T_PACKETS_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_PACKETS_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
#define	ENET_RMON_T_PACKETS_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_PACKETS_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
#define	ENET_RMON_T_PACKETS_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_PACKETS_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_PACKETS_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)

RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_BC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_BC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_BC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_BC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
#define	ENET_RMON_T_BC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_BC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_BC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)

RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_MC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_MC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_MC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_MC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
#define	ENET_RMON_T_MC_PKT_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_MC_PKT_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_MC_PKT_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)

RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_CRC_ALIGN_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)

RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_UNDERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)

RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_OVERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_OVERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_OVERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_OVERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_OVERSIZE_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)

RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_FRAG_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_FRAG_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
#define	ENET_RMON_T_FRAG_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_FRAG_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
#define	ENET_RMON_T_FRAG_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_FRAG_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
#define	ENET_RMON_T_FRAG_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_FRAG_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
#define	ENET_RMON_T_FRAG_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_FRAG_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_FRAG_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)

RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
#define	ENET_RMON_T_JAB_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_JAB_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_JAB_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
#define	ENET_RMON_T_JAB_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_JAB_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_JAB_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
#define	ENET_RMON_T_JAB_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_JAB_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_JAB_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
#define	ENET_RMON_T_JAB_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_JAB_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_JAB_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
#define	ENET_RMON_T_JAB_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_JAB_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_JAB_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)

RMON_T_COL - Tx Collision Count Statistic Register
#define	ENET_RMON_T_COL_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_COL_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_COL_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
#define	ENET_RMON_T_COL_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_COL_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_COL_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
#define	ENET_RMON_T_COL_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_COL_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_COL_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
#define	ENET_RMON_T_COL_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_COL_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_COL_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
#define	ENET_RMON_T_COL_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_COL_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_COL_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)

RMON_T_P64 - Tx 64-Byte Packets Statistic Register
#define	ENET_RMON_T_P64_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P64_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P64_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
#define	ENET_RMON_T_P64_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P64_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P64_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
#define	ENET_RMON_T_P64_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P64_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P64_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
#define	ENET_RMON_T_P64_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P64_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P64_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
#define	ENET_RMON_T_P64_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P64_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P64_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)

RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
#define	ENET_RMON_T_P65TO127_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P65TO127_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
#define	ENET_RMON_T_P65TO127_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P65TO127_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
#define	ENET_RMON_T_P65TO127_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P65TO127_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
#define	ENET_RMON_T_P65TO127_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P65TO127_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
#define	ENET_RMON_T_P65TO127_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P65TO127_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P65TO127_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)

RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
#define	ENET_RMON_T_P128TO255_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P128TO255_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
#define	ENET_RMON_T_P128TO255_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P128TO255_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
#define	ENET_RMON_T_P128TO255_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P128TO255_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
#define	ENET_RMON_T_P128TO255_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P128TO255_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
#define	ENET_RMON_T_P128TO255_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P128TO255_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P128TO255_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)

RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
#define	ENET_RMON_T_P256TO511_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P256TO511_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
#define	ENET_RMON_T_P256TO511_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P256TO511_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
#define	ENET_RMON_T_P256TO511_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P256TO511_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
#define	ENET_RMON_T_P256TO511_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P256TO511_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
#define	ENET_RMON_T_P256TO511_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P256TO511_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P256TO511_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)

RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P512TO1023_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P512TO1023_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P512TO1023_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P512TO1023_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
#define	ENET_RMON_T_P512TO1023_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P512TO1023_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P512TO1023_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)

RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P1024TO2047_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P1024TO2047_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P1024TO2047_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P1024TO2047_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P1024TO2047_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)

RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P_GTE2048_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P_GTE2048_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P_GTE2048_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P_GTE2048_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_MASK   (0xFFFFU)
#define	ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT   (0U)
#define	ENET_RMON_T_P_GTE2048_TXPKTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)

RMON_T_OCTETS - Tx Octets Statistic Register
#define	ENET_RMON_T_OCTETS_TXOCTS_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT   (0U)
#define	ENET_RMON_T_OCTETS_TXOCTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
#define	ENET_RMON_T_OCTETS_TXOCTS_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT   (0U)
#define	ENET_RMON_T_OCTETS_TXOCTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
#define	ENET_RMON_T_OCTETS_TXOCTS_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT   (0U)
#define	ENET_RMON_T_OCTETS_TXOCTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
#define	ENET_RMON_T_OCTETS_TXOCTS_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT   (0U)
#define	ENET_RMON_T_OCTETS_TXOCTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
#define	ENET_RMON_T_OCTETS_TXOCTS_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_T_OCTETS_TXOCTS_SHIFT   (0U)
#define	ENET_RMON_T_OCTETS_TXOCTS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)

IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
#define	ENET_IEEE_T_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)

IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
#define	ENET_IEEE_T_1COL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_1COL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_1COL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
#define	ENET_IEEE_T_1COL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_1COL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_1COL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
#define	ENET_IEEE_T_1COL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_1COL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_1COL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
#define	ENET_IEEE_T_1COL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_1COL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_1COL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
#define	ENET_IEEE_T_1COL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_1COL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_1COL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)

IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
#define	ENET_IEEE_T_MCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
#define	ENET_IEEE_T_MCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
#define	ENET_IEEE_T_MCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
#define	ENET_IEEE_T_MCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
#define	ENET_IEEE_T_MCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)

IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
#define	ENET_IEEE_T_DEF_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_DEF_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_DEF_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
#define	ENET_IEEE_T_DEF_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_DEF_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_DEF_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
#define	ENET_IEEE_T_DEF_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_DEF_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_DEF_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
#define	ENET_IEEE_T_DEF_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_DEF_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_DEF_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
#define	ENET_IEEE_T_DEF_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_DEF_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_DEF_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)

IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
#define	ENET_IEEE_T_LCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_LCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_LCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
#define	ENET_IEEE_T_LCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_LCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_LCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
#define	ENET_IEEE_T_LCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_LCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_LCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
#define	ENET_IEEE_T_LCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_LCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_LCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
#define	ENET_IEEE_T_LCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_LCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_LCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)

IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
#define	ENET_IEEE_T_EXCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_EXCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
#define	ENET_IEEE_T_EXCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_EXCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
#define	ENET_IEEE_T_EXCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_EXCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
#define	ENET_IEEE_T_EXCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_EXCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
#define	ENET_IEEE_T_EXCOL_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_EXCOL_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_EXCOL_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)

IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
#define	ENET_IEEE_T_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
#define	ENET_IEEE_T_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
#define	ENET_IEEE_T_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
#define	ENET_IEEE_T_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
#define	ENET_IEEE_T_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)

IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
#define	ENET_IEEE_T_CSERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_CSERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_CSERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
#define	ENET_IEEE_T_CSERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_CSERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_CSERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
#define	ENET_IEEE_T_CSERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_CSERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_CSERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
#define	ENET_IEEE_T_CSERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_CSERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_CSERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
#define	ENET_IEEE_T_CSERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_CSERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_CSERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)

IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
#define	ENET_IEEE_T_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
#define	ENET_IEEE_T_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
#define	ENET_IEEE_T_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
#define	ENET_IEEE_T_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
#define	ENET_IEEE_T_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)

IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)

RMON_R_PACKETS - Rx Packet Count Statistic Register
#define	ENET_RMON_R_PACKETS_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_PACKETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_PACKETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
#define	ENET_RMON_R_PACKETS_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_PACKETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_PACKETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
#define	ENET_RMON_R_PACKETS_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_PACKETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_PACKETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
#define	ENET_RMON_R_PACKETS_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_PACKETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_PACKETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
#define	ENET_RMON_R_PACKETS_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_PACKETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_PACKETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)

RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
#define	ENET_RMON_R_BC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_BC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
#define	ENET_RMON_R_BC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_BC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
#define	ENET_RMON_R_BC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_BC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
#define	ENET_RMON_R_BC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_BC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
#define	ENET_RMON_R_BC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_BC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_BC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)

RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
#define	ENET_RMON_R_MC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_MC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
#define	ENET_RMON_R_MC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_MC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
#define	ENET_RMON_R_MC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_MC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
#define	ENET_RMON_R_MC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_MC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
#define	ENET_RMON_R_MC_PKT_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_MC_PKT_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_MC_PKT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)

RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_CRC_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_CRC_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_CRC_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_CRC_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_CRC_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)

RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_UNDERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_UNDERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_UNDERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_UNDERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
#define	ENET_RMON_R_UNDERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_UNDERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_UNDERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)

RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
#define	ENET_RMON_R_OVERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OVERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
#define	ENET_RMON_R_OVERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OVERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
#define	ENET_RMON_R_OVERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OVERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
#define	ENET_RMON_R_OVERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OVERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
#define	ENET_RMON_R_OVERSIZE_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_OVERSIZE_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OVERSIZE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)

RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_FRAG_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_FRAG_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_FRAG_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
#define	ENET_RMON_R_FRAG_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_FRAG_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_FRAG_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
#define	ENET_RMON_R_FRAG_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_FRAG_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_FRAG_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
#define	ENET_RMON_R_FRAG_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_FRAG_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_FRAG_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
#define	ENET_RMON_R_FRAG_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_FRAG_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_FRAG_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)

RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
#define	ENET_RMON_R_JAB_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_JAB_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_JAB_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
#define	ENET_RMON_R_JAB_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_JAB_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_JAB_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
#define	ENET_RMON_R_JAB_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_JAB_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_JAB_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
#define	ENET_RMON_R_JAB_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_JAB_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_JAB_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
#define	ENET_RMON_R_JAB_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_JAB_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_JAB_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)

RMON_R_P64 - Rx 64-Byte Packets Statistic Register
#define	ENET_RMON_R_P64_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P64_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P64_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
#define	ENET_RMON_R_P64_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P64_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P64_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
#define	ENET_RMON_R_P64_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P64_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P64_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
#define	ENET_RMON_R_P64_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P64_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P64_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
#define	ENET_RMON_R_P64_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P64_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P64_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)

RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
#define	ENET_RMON_R_P65TO127_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P65TO127_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P65TO127_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
#define	ENET_RMON_R_P65TO127_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P65TO127_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P65TO127_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
#define	ENET_RMON_R_P65TO127_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P65TO127_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P65TO127_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
#define	ENET_RMON_R_P65TO127_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P65TO127_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P65TO127_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
#define	ENET_RMON_R_P65TO127_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P65TO127_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P65TO127_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)

RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
#define	ENET_RMON_R_P128TO255_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P128TO255_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P128TO255_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
#define	ENET_RMON_R_P128TO255_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P128TO255_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P128TO255_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
#define	ENET_RMON_R_P128TO255_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P128TO255_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P128TO255_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
#define	ENET_RMON_R_P128TO255_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P128TO255_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P128TO255_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
#define	ENET_RMON_R_P128TO255_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P128TO255_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P128TO255_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)

RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
#define	ENET_RMON_R_P256TO511_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P256TO511_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P256TO511_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
#define	ENET_RMON_R_P256TO511_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P256TO511_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P256TO511_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
#define	ENET_RMON_R_P256TO511_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P256TO511_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P256TO511_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
#define	ENET_RMON_R_P256TO511_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P256TO511_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P256TO511_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
#define	ENET_RMON_R_P256TO511_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P256TO511_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P256TO511_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)

RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
#define	ENET_RMON_R_P512TO1023_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P512TO1023_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
#define	ENET_RMON_R_P512TO1023_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P512TO1023_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
#define	ENET_RMON_R_P512TO1023_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P512TO1023_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
#define	ENET_RMON_R_P512TO1023_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P512TO1023_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
#define	ENET_RMON_R_P512TO1023_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P512TO1023_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P512TO1023_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)

RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
#define	ENET_RMON_R_P1024TO2047_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P1024TO2047_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
#define	ENET_RMON_R_P1024TO2047_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P1024TO2047_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
#define	ENET_RMON_R_P1024TO2047_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P1024TO2047_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
#define	ENET_RMON_R_P1024TO2047_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P1024TO2047_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
#define	ENET_RMON_R_P1024TO2047_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P1024TO2047_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P1024TO2047_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)

RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
#define	ENET_RMON_R_P_GTE2048_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P_GTE2048_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
#define	ENET_RMON_R_P_GTE2048_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P_GTE2048_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
#define	ENET_RMON_R_P_GTE2048_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P_GTE2048_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
#define	ENET_RMON_R_P_GTE2048_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P_GTE2048_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
#define	ENET_RMON_R_P_GTE2048_COUNT_MASK   (0xFFFFU)
#define	ENET_RMON_R_P_GTE2048_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_P_GTE2048_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)

RMON_R_OCTETS - Rx Octets Statistic Register
#define	ENET_RMON_R_OCTETS_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_R_OCTETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OCTETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
#define	ENET_RMON_R_OCTETS_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_R_OCTETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OCTETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
#define	ENET_RMON_R_OCTETS_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_R_OCTETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OCTETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
#define	ENET_RMON_R_OCTETS_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_R_OCTETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OCTETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
#define	ENET_RMON_R_OCTETS_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_RMON_R_OCTETS_COUNT_SHIFT   (0U)
#define	ENET_RMON_R_OCTETS_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)

IEEE_R_DROP - Frames not Counted Correctly Statistic Register
#define	ENET_IEEE_R_DROP_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_DROP_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_DROP_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
#define	ENET_IEEE_R_DROP_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_DROP_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_DROP_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
#define	ENET_IEEE_R_DROP_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_DROP_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_DROP_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
#define	ENET_IEEE_R_DROP_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_DROP_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_DROP_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
#define	ENET_IEEE_R_DROP_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_DROP_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_DROP_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)

IEEE_R_FRAME_OK - Frames Received OK Statistic Register
#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
#define	ENET_IEEE_R_FRAME_OK_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FRAME_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FRAME_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)

IEEE_R_CRC - Frames Received with CRC Error Statistic Register
#define	ENET_IEEE_R_CRC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_CRC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_CRC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
#define	ENET_IEEE_R_CRC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_CRC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_CRC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
#define	ENET_IEEE_R_CRC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_CRC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_CRC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
#define	ENET_IEEE_R_CRC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_CRC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_CRC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
#define	ENET_IEEE_R_CRC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_CRC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_CRC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)

IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
#define	ENET_IEEE_R_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
#define	ENET_IEEE_R_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
#define	ENET_IEEE_R_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
#define	ENET_IEEE_R_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
#define	ENET_IEEE_R_ALIGN_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_ALIGN_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_ALIGN_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)

IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
#define	ENET_IEEE_R_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
#define	ENET_IEEE_R_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
#define	ENET_IEEE_R_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
#define	ENET_IEEE_R_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
#define	ENET_IEEE_R_MACERR_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_MACERR_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_MACERR_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)

IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
#define	ENET_IEEE_R_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
#define	ENET_IEEE_R_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
#define	ENET_IEEE_R_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
#define	ENET_IEEE_R_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
#define	ENET_IEEE_R_FDXFC_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_R_FDXFC_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_FDXFC_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)

IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_MASK   (0xFFFFFFFFU)
#define	ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT   (0U)
#define	ENET_IEEE_R_OCTETS_OK_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)

ATCR - Adjustable Timer Control Register
#define	ENET_ATCR_EN_MASK   (0x1U)
#define	ENET_ATCR_EN_SHIFT   (0U)
#define	ENET_ATCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
#define	ENET_ATCR_OFFEN_MASK   (0x4U)
#define	ENET_ATCR_OFFEN_SHIFT   (2U)
#define	ENET_ATCR_OFFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
#define	ENET_ATCR_OFFRST_MASK   (0x8U)
#define	ENET_ATCR_OFFRST_SHIFT   (3U)
#define	ENET_ATCR_OFFRST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
#define	ENET_ATCR_PEREN_MASK   (0x10U)
#define	ENET_ATCR_PEREN_SHIFT   (4U)
#define	ENET_ATCR_PEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
#define	ENET_ATCR_PINPER_MASK   (0x80U)
#define	ENET_ATCR_PINPER_SHIFT   (7U)
#define	ENET_ATCR_PINPER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
#define	ENET_ATCR_RESTART_MASK   (0x200U)
#define	ENET_ATCR_RESTART_SHIFT   (9U)
#define	ENET_ATCR_RESTART(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
#define	ENET_ATCR_CAPTURE_MASK   (0x800U)
#define	ENET_ATCR_CAPTURE_SHIFT   (11U)
#define	ENET_ATCR_CAPTURE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
#define	ENET_ATCR_SLAVE_MASK   (0x2000U)
#define	ENET_ATCR_SLAVE_SHIFT   (13U)
#define	ENET_ATCR_SLAVE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
#define	ENET_ATCR_EN_MASK   0x1u
#define	ENET_ATCR_EN_SHIFT   0
#define	ENET_ATCR_OFFEN_MASK   0x4u
#define	ENET_ATCR_OFFEN_SHIFT   2
#define	ENET_ATCR_OFFRST_MASK   0x8u
#define	ENET_ATCR_OFFRST_SHIFT   3
#define	ENET_ATCR_PEREN_MASK   0x10u
#define	ENET_ATCR_PEREN_SHIFT   4
#define	ENET_ATCR_PINPER_MASK   0x80u
#define	ENET_ATCR_PINPER_SHIFT   7
#define	ENET_ATCR_RESTART_MASK   0x200u
#define	ENET_ATCR_RESTART_SHIFT   9
#define	ENET_ATCR_CAPTURE_MASK   0x800u
#define	ENET_ATCR_CAPTURE_SHIFT   11
#define	ENET_ATCR_SLAVE_MASK   0x2000u
#define	ENET_ATCR_SLAVE_SHIFT   13
#define	ENET_ATCR_EN_MASK   (0x1U)
#define	ENET_ATCR_EN_SHIFT   (0U)
#define	ENET_ATCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
#define	ENET_ATCR_OFFEN_MASK   (0x4U)
#define	ENET_ATCR_OFFEN_SHIFT   (2U)
#define	ENET_ATCR_OFFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
#define	ENET_ATCR_OFFRST_MASK   (0x8U)
#define	ENET_ATCR_OFFRST_SHIFT   (3U)
#define	ENET_ATCR_OFFRST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
#define	ENET_ATCR_PEREN_MASK   (0x10U)
#define	ENET_ATCR_PEREN_SHIFT   (4U)
#define	ENET_ATCR_PEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
#define	ENET_ATCR_PINPER_MASK   (0x80U)
#define	ENET_ATCR_PINPER_SHIFT   (7U)
#define	ENET_ATCR_PINPER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
#define	ENET_ATCR_RESTART_MASK   (0x200U)
#define	ENET_ATCR_RESTART_SHIFT   (9U)
#define	ENET_ATCR_RESTART(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
#define	ENET_ATCR_CAPTURE_MASK   (0x800U)
#define	ENET_ATCR_CAPTURE_SHIFT   (11U)
#define	ENET_ATCR_CAPTURE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
#define	ENET_ATCR_SLAVE_MASK   (0x2000U)
#define	ENET_ATCR_SLAVE_SHIFT   (13U)
#define	ENET_ATCR_SLAVE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
#define	ENET_ATCR_EN_MASK   (0x1U)
#define	ENET_ATCR_EN_SHIFT   (0U)
#define	ENET_ATCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
#define	ENET_ATCR_OFFEN_MASK   (0x4U)
#define	ENET_ATCR_OFFEN_SHIFT   (2U)
#define	ENET_ATCR_OFFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
#define	ENET_ATCR_OFFRST_MASK   (0x8U)
#define	ENET_ATCR_OFFRST_SHIFT   (3U)
#define	ENET_ATCR_OFFRST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
#define	ENET_ATCR_PEREN_MASK   (0x10U)
#define	ENET_ATCR_PEREN_SHIFT   (4U)
#define	ENET_ATCR_PEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
#define	ENET_ATCR_PINPER_MASK   (0x80U)
#define	ENET_ATCR_PINPER_SHIFT   (7U)
#define	ENET_ATCR_PINPER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
#define	ENET_ATCR_RESTART_MASK   (0x200U)
#define	ENET_ATCR_RESTART_SHIFT   (9U)
#define	ENET_ATCR_RESTART(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
#define	ENET_ATCR_CAPTURE_MASK   (0x800U)
#define	ENET_ATCR_CAPTURE_SHIFT   (11U)
#define	ENET_ATCR_CAPTURE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
#define	ENET_ATCR_SLAVE_MASK   (0x2000U)
#define	ENET_ATCR_SLAVE_SHIFT   (13U)
#define	ENET_ATCR_SLAVE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
#define	ENET_ATCR_EN_MASK   (0x1U)
#define	ENET_ATCR_EN_SHIFT   (0U)
#define	ENET_ATCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
#define	ENET_ATCR_OFFEN_MASK   (0x4U)
#define	ENET_ATCR_OFFEN_SHIFT   (2U)
#define	ENET_ATCR_OFFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
#define	ENET_ATCR_OFFRST_MASK   (0x8U)
#define	ENET_ATCR_OFFRST_SHIFT   (3U)
#define	ENET_ATCR_OFFRST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
#define	ENET_ATCR_PEREN_MASK   (0x10U)
#define	ENET_ATCR_PEREN_SHIFT   (4U)
#define	ENET_ATCR_PEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
#define	ENET_ATCR_PINPER_MASK   (0x80U)
#define	ENET_ATCR_PINPER_SHIFT   (7U)
#define	ENET_ATCR_PINPER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
#define	ENET_ATCR_RESTART_MASK   (0x200U)
#define	ENET_ATCR_RESTART_SHIFT   (9U)
#define	ENET_ATCR_RESTART(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
#define	ENET_ATCR_CAPTURE_MASK   (0x800U)
#define	ENET_ATCR_CAPTURE_SHIFT   (11U)
#define	ENET_ATCR_CAPTURE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
#define	ENET_ATCR_SLAVE_MASK   (0x2000U)
#define	ENET_ATCR_SLAVE_SHIFT   (13U)
#define	ENET_ATCR_SLAVE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
#define	ENET_ATCR_EN_MASK   (0x1U)
#define	ENET_ATCR_EN_SHIFT   (0U)
#define	ENET_ATCR_EN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
#define	ENET_ATCR_OFFEN_MASK   (0x4U)
#define	ENET_ATCR_OFFEN_SHIFT   (2U)
#define	ENET_ATCR_OFFEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
#define	ENET_ATCR_OFFRST_MASK   (0x8U)
#define	ENET_ATCR_OFFRST_SHIFT   (3U)
#define	ENET_ATCR_OFFRST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
#define	ENET_ATCR_PEREN_MASK   (0x10U)
#define	ENET_ATCR_PEREN_SHIFT   (4U)
#define	ENET_ATCR_PEREN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
#define	ENET_ATCR_PINPER_MASK   (0x80U)
#define	ENET_ATCR_PINPER_SHIFT   (7U)
#define	ENET_ATCR_PINPER(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
#define	ENET_ATCR_RESTART_MASK   (0x200U)
#define	ENET_ATCR_RESTART_SHIFT   (9U)
#define	ENET_ATCR_RESTART(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
#define	ENET_ATCR_CAPTURE_MASK   (0x800U)
#define	ENET_ATCR_CAPTURE_SHIFT   (11U)
#define	ENET_ATCR_CAPTURE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
#define	ENET_ATCR_SLAVE_MASK   (0x2000U)
#define	ENET_ATCR_SLAVE_SHIFT   (13U)
#define	ENET_ATCR_SLAVE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

ATVR - Timer Value Register
#define	ENET_ATVR_ATIME_MASK   (0xFFFFFFFFU)
#define	ENET_ATVR_ATIME_SHIFT   (0U)
#define	ENET_ATVR_ATIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
#define	ENET_ATVR_ATIME_MASK   0xFFFFFFFFu
#define	ENET_ATVR_ATIME_SHIFT   0
#define	ENET_ATVR_ATIME(x)   (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
#define	ENET_ATVR_ATIME_MASK   (0xFFFFFFFFU)
#define	ENET_ATVR_ATIME_SHIFT   (0U)
#define	ENET_ATVR_ATIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
#define	ENET_ATVR_ATIME_MASK   (0xFFFFFFFFU)
#define	ENET_ATVR_ATIME_SHIFT   (0U)
#define	ENET_ATVR_ATIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
#define	ENET_ATVR_ATIME_MASK   (0xFFFFFFFFU)
#define	ENET_ATVR_ATIME_SHIFT   (0U)
#define	ENET_ATVR_ATIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
#define	ENET_ATVR_ATIME_MASK   (0xFFFFFFFFU)
#define	ENET_ATVR_ATIME_SHIFT   (0U)
#define	ENET_ATVR_ATIME(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)

ATOFF - Timer Offset Register
#define	ENET_ATOFF_OFFSET_MASK   (0xFFFFFFFFU)
#define	ENET_ATOFF_OFFSET_SHIFT   (0U)
#define	ENET_ATOFF_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
#define	ENET_ATOFF_OFFSET_MASK   0xFFFFFFFFu
#define	ENET_ATOFF_OFFSET_SHIFT   0
#define	ENET_ATOFF_OFFSET(x)   (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
#define	ENET_ATOFF_OFFSET_MASK   (0xFFFFFFFFU)
#define	ENET_ATOFF_OFFSET_SHIFT   (0U)
#define	ENET_ATOFF_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
#define	ENET_ATOFF_OFFSET_MASK   (0xFFFFFFFFU)
#define	ENET_ATOFF_OFFSET_SHIFT   (0U)
#define	ENET_ATOFF_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
#define	ENET_ATOFF_OFFSET_MASK   (0xFFFFFFFFU)
#define	ENET_ATOFF_OFFSET_SHIFT   (0U)
#define	ENET_ATOFF_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
#define	ENET_ATOFF_OFFSET_MASK   (0xFFFFFFFFU)
#define	ENET_ATOFF_OFFSET_SHIFT   (0U)
#define	ENET_ATOFF_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)

ATPER - Timer Period Register
#define	ENET_ATPER_PERIOD_MASK   (0xFFFFFFFFU)
#define	ENET_ATPER_PERIOD_SHIFT   (0U)
#define	ENET_ATPER_PERIOD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
#define	ENET_ATPER_PERIOD_MASK   0xFFFFFFFFu
#define	ENET_ATPER_PERIOD_SHIFT   0
#define	ENET_ATPER_PERIOD(x)   (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
#define	ENET_ATPER_PERIOD_MASK   (0xFFFFFFFFU)
#define	ENET_ATPER_PERIOD_SHIFT   (0U)
#define	ENET_ATPER_PERIOD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
#define	ENET_ATPER_PERIOD_MASK   (0xFFFFFFFFU)
#define	ENET_ATPER_PERIOD_SHIFT   (0U)
#define	ENET_ATPER_PERIOD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
#define	ENET_ATPER_PERIOD_MASK   (0xFFFFFFFFU)
#define	ENET_ATPER_PERIOD_SHIFT   (0U)
#define	ENET_ATPER_PERIOD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
#define	ENET_ATPER_PERIOD_MASK   (0xFFFFFFFFU)
#define	ENET_ATPER_PERIOD_SHIFT   (0U)
#define	ENET_ATPER_PERIOD(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)

ATCOR - Timer Correction Register
#define	ENET_ATCOR_COR_MASK   (0x7FFFFFFFU)
#define	ENET_ATCOR_COR_SHIFT   (0U)
#define	ENET_ATCOR_COR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
#define	ENET_ATCOR_COR_MASK   0x7FFFFFFFu
#define	ENET_ATCOR_COR_SHIFT   0
#define	ENET_ATCOR_COR(x)   (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
#define	ENET_ATCOR_COR_MASK   (0x7FFFFFFFU)
#define	ENET_ATCOR_COR_SHIFT   (0U)
#define	ENET_ATCOR_COR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
#define	ENET_ATCOR_COR_MASK   (0x7FFFFFFFU)
#define	ENET_ATCOR_COR_SHIFT   (0U)
#define	ENET_ATCOR_COR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
#define	ENET_ATCOR_COR_MASK   (0x7FFFFFFFU)
#define	ENET_ATCOR_COR_SHIFT   (0U)
#define	ENET_ATCOR_COR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
#define	ENET_ATCOR_COR_MASK   (0x7FFFFFFFU)
#define	ENET_ATCOR_COR_SHIFT   (0U)
#define	ENET_ATCOR_COR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)

ATINC - Time-Stamping Clock Period Register
#define	ENET_ATINC_INC_MASK   (0x7FU)
#define	ENET_ATINC_INC_SHIFT   (0U)
#define	ENET_ATINC_INC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
#define	ENET_ATINC_INC_CORR_MASK   (0x7F00U)
#define	ENET_ATINC_INC_CORR_SHIFT   (8U)
#define	ENET_ATINC_INC_CORR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
#define	ENET_ATINC_INC_MASK   0x7Fu
#define	ENET_ATINC_INC_SHIFT   0
#define	ENET_ATINC_INC(x)   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
#define	ENET_ATINC_INC_CORR_MASK   0x7F00u
#define	ENET_ATINC_INC_CORR_SHIFT   8
#define	ENET_ATINC_INC_CORR(x)   (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
#define	ENET_ATINC_INC_MASK   (0x7FU)
#define	ENET_ATINC_INC_SHIFT   (0U)
#define	ENET_ATINC_INC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
#define	ENET_ATINC_INC_CORR_MASK   (0x7F00U)
#define	ENET_ATINC_INC_CORR_SHIFT   (8U)
#define	ENET_ATINC_INC_CORR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
#define	ENET_ATINC_INC_MASK   (0x7FU)
#define	ENET_ATINC_INC_SHIFT   (0U)
#define	ENET_ATINC_INC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
#define	ENET_ATINC_INC_CORR_MASK   (0x7F00U)
#define	ENET_ATINC_INC_CORR_SHIFT   (8U)
#define	ENET_ATINC_INC_CORR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
#define	ENET_ATINC_INC_MASK   (0x7FU)
#define	ENET_ATINC_INC_SHIFT   (0U)
#define	ENET_ATINC_INC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
#define	ENET_ATINC_INC_CORR_MASK   (0x7F00U)
#define	ENET_ATINC_INC_CORR_SHIFT   (8U)
#define	ENET_ATINC_INC_CORR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
#define	ENET_ATINC_INC_MASK   (0x7FU)
#define	ENET_ATINC_INC_SHIFT   (0U)
#define	ENET_ATINC_INC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
#define	ENET_ATINC_INC_CORR_MASK   (0x7F00U)
#define	ENET_ATINC_INC_CORR_SHIFT   (8U)
#define	ENET_ATINC_INC_CORR(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)

ATSTMP - Timestamp of Last Transmitted Frame
#define	ENET_ATSTMP_TIMESTAMP_MASK   (0xFFFFFFFFU)
#define	ENET_ATSTMP_TIMESTAMP_SHIFT   (0U)
#define	ENET_ATSTMP_TIMESTAMP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
#define	ENET_ATSTMP_TIMESTAMP_MASK   0xFFFFFFFFu
#define	ENET_ATSTMP_TIMESTAMP_SHIFT   0
#define	ENET_ATSTMP_TIMESTAMP(x)   (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
#define	ENET_ATSTMP_TIMESTAMP_MASK   (0xFFFFFFFFU)
#define	ENET_ATSTMP_TIMESTAMP_SHIFT   (0U)
#define	ENET_ATSTMP_TIMESTAMP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
#define	ENET_ATSTMP_TIMESTAMP_MASK   (0xFFFFFFFFU)
#define	ENET_ATSTMP_TIMESTAMP_SHIFT   (0U)
#define	ENET_ATSTMP_TIMESTAMP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
#define	ENET_ATSTMP_TIMESTAMP_MASK   (0xFFFFFFFFU)
#define	ENET_ATSTMP_TIMESTAMP_SHIFT   (0U)
#define	ENET_ATSTMP_TIMESTAMP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
#define	ENET_ATSTMP_TIMESTAMP_MASK   (0xFFFFFFFFU)
#define	ENET_ATSTMP_TIMESTAMP_SHIFT   (0U)
#define	ENET_ATSTMP_TIMESTAMP(x)   (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)

TGSR - Timer Global Status Register
#define	ENET_TGSR_TF0_MASK   (0x1U)
#define	ENET_TGSR_TF0_SHIFT   (0U)
#define	ENET_TGSR_TF0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
#define	ENET_TGSR_TF1_MASK   (0x2U)
#define	ENET_TGSR_TF1_SHIFT   (1U)
#define	ENET_TGSR_TF1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
#define	ENET_TGSR_TF2_MASK   (0x4U)
#define	ENET_TGSR_TF2_SHIFT   (2U)
#define	ENET_TGSR_TF2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
#define	ENET_TGSR_TF3_MASK   (0x8U)
#define	ENET_TGSR_TF3_SHIFT   (3U)
#define	ENET_TGSR_TF3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
#define	ENET_TGSR_TF0_MASK   0x1u
#define	ENET_TGSR_TF0_SHIFT   0
#define	ENET_TGSR_TF1_MASK   0x2u
#define	ENET_TGSR_TF1_SHIFT   1
#define	ENET_TGSR_TF2_MASK   0x4u
#define	ENET_TGSR_TF2_SHIFT   2
#define	ENET_TGSR_TF3_MASK   0x8u
#define	ENET_TGSR_TF3_SHIFT   3
#define	ENET_TGSR_TF0_MASK   (0x1U)
#define	ENET_TGSR_TF0_SHIFT   (0U)
#define	ENET_TGSR_TF0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
#define	ENET_TGSR_TF1_MASK   (0x2U)
#define	ENET_TGSR_TF1_SHIFT   (1U)
#define	ENET_TGSR_TF1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
#define	ENET_TGSR_TF2_MASK   (0x4U)
#define	ENET_TGSR_TF2_SHIFT   (2U)
#define	ENET_TGSR_TF2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
#define	ENET_TGSR_TF3_MASK   (0x8U)
#define	ENET_TGSR_TF3_SHIFT   (3U)
#define	ENET_TGSR_TF3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
#define	ENET_TGSR_TF0_MASK   (0x1U)
#define	ENET_TGSR_TF0_SHIFT   (0U)
#define	ENET_TGSR_TF0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
#define	ENET_TGSR_TF1_MASK   (0x2U)
#define	ENET_TGSR_TF1_SHIFT   (1U)
#define	ENET_TGSR_TF1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
#define	ENET_TGSR_TF2_MASK   (0x4U)
#define	ENET_TGSR_TF2_SHIFT   (2U)
#define	ENET_TGSR_TF2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
#define	ENET_TGSR_TF3_MASK   (0x8U)
#define	ENET_TGSR_TF3_SHIFT   (3U)
#define	ENET_TGSR_TF3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
#define	ENET_TGSR_TF0_MASK   (0x1U)
#define	ENET_TGSR_TF0_SHIFT   (0U)
#define	ENET_TGSR_TF0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
#define	ENET_TGSR_TF1_MASK   (0x2U)
#define	ENET_TGSR_TF1_SHIFT   (1U)
#define	ENET_TGSR_TF1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
#define	ENET_TGSR_TF2_MASK   (0x4U)
#define	ENET_TGSR_TF2_SHIFT   (2U)
#define	ENET_TGSR_TF2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
#define	ENET_TGSR_TF3_MASK   (0x8U)
#define	ENET_TGSR_TF3_SHIFT   (3U)
#define	ENET_TGSR_TF3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
#define	ENET_TGSR_TF0_MASK   (0x1U)
#define	ENET_TGSR_TF0_SHIFT   (0U)
#define	ENET_TGSR_TF0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
#define	ENET_TGSR_TF1_MASK   (0x2U)
#define	ENET_TGSR_TF1_SHIFT   (1U)
#define	ENET_TGSR_TF1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
#define	ENET_TGSR_TF2_MASK   (0x4U)
#define	ENET_TGSR_TF2_SHIFT   (2U)
#define	ENET_TGSR_TF2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
#define	ENET_TGSR_TF3_MASK   (0x8U)
#define	ENET_TGSR_TF3_SHIFT   (3U)
#define	ENET_TGSR_TF3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TCSR - Timer Control Status Register
#define	ENET_TCSR_TDRE_MASK   (0x1U)
#define	ENET_TCSR_TDRE_SHIFT   (0U)
#define	ENET_TCSR_TDRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
#define	ENET_TCSR_TMODE_MASK   (0x3CU)
#define	ENET_TCSR_TMODE_SHIFT   (2U)
#define	ENET_TCSR_TMODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
#define	ENET_TCSR_TIE_MASK   (0x40U)
#define	ENET_TCSR_TIE_SHIFT   (6U)
#define	ENET_TCSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
#define	ENET_TCSR_TF_MASK   (0x80U)
#define	ENET_TCSR_TF_SHIFT   (7U)
#define	ENET_TCSR_TF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
#define	ENET_TCSR_TDRE_MASK   0x1u
#define	ENET_TCSR_TDRE_SHIFT   0
#define	ENET_TCSR_TMODE_MASK   0x3Cu
#define	ENET_TCSR_TMODE_SHIFT   2
#define	ENET_TCSR_TMODE(x)   (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
#define	ENET_TCSR_TIE_MASK   0x40u
#define	ENET_TCSR_TIE_SHIFT   6
#define	ENET_TCSR_TF_MASK   0x80u
#define	ENET_TCSR_TF_SHIFT   7
#define	ENET_TCSR_TDRE_MASK   (0x1U)
#define	ENET_TCSR_TDRE_SHIFT   (0U)
#define	ENET_TCSR_TDRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
#define	ENET_TCSR_TMODE_MASK   (0x3CU)
#define	ENET_TCSR_TMODE_SHIFT   (2U)
#define	ENET_TCSR_TMODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
#define	ENET_TCSR_TIE_MASK   (0x40U)
#define	ENET_TCSR_TIE_SHIFT   (6U)
#define	ENET_TCSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
#define	ENET_TCSR_TF_MASK   (0x80U)
#define	ENET_TCSR_TF_SHIFT   (7U)
#define	ENET_TCSR_TF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
#define	ENET_TCSR_TDRE_MASK   (0x1U)
#define	ENET_TCSR_TDRE_SHIFT   (0U)
#define	ENET_TCSR_TDRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
#define	ENET_TCSR_TMODE_MASK   (0x3CU)
#define	ENET_TCSR_TMODE_SHIFT   (2U)
#define	ENET_TCSR_TMODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
#define	ENET_TCSR_TIE_MASK   (0x40U)
#define	ENET_TCSR_TIE_SHIFT   (6U)
#define	ENET_TCSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
#define	ENET_TCSR_TF_MASK   (0x80U)
#define	ENET_TCSR_TF_SHIFT   (7U)
#define	ENET_TCSR_TF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
#define	ENET_TCSR_TDRE_MASK   (0x1U)
#define	ENET_TCSR_TDRE_SHIFT   (0U)
#define	ENET_TCSR_TDRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
#define	ENET_TCSR_TMODE_MASK   (0x3CU)
#define	ENET_TCSR_TMODE_SHIFT   (2U)
#define	ENET_TCSR_TMODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
#define	ENET_TCSR_TIE_MASK   (0x40U)
#define	ENET_TCSR_TIE_SHIFT   (6U)
#define	ENET_TCSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
#define	ENET_TCSR_TF_MASK   (0x80U)
#define	ENET_TCSR_TF_SHIFT   (7U)
#define	ENET_TCSR_TF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
#define	ENET_TCSR_TDRE_MASK   (0x1U)
#define	ENET_TCSR_TDRE_SHIFT   (0U)
#define	ENET_TCSR_TDRE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
#define	ENET_TCSR_TMODE_MASK   (0x3CU)
#define	ENET_TCSR_TMODE_SHIFT   (2U)
#define	ENET_TCSR_TMODE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
#define	ENET_TCSR_TIE_MASK   (0x40U)
#define	ENET_TCSR_TIE_SHIFT   (6U)
#define	ENET_TCSR_TIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
#define	ENET_TCSR_TF_MASK   (0x80U)
#define	ENET_TCSR_TF_SHIFT   (7U)
#define	ENET_TCSR_TF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

TCSR - Timer Control Status Register
#define	ENET_TCSR_COUNT   (4U)

TCCR - Timer Compare Capture Register
#define	ENET_TCCR_TCC_MASK   (0xFFFFFFFFU)
#define	ENET_TCCR_TCC_SHIFT   (0U)
#define	ENET_TCCR_TCC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
#define	ENET_TCCR_TCC_MASK   0xFFFFFFFFu
#define	ENET_TCCR_TCC_SHIFT   0
#define	ENET_TCCR_TCC(x)   (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
#define	ENET_TCCR_TCC_MASK   (0xFFFFFFFFU)
#define	ENET_TCCR_TCC_SHIFT   (0U)
#define	ENET_TCCR_TCC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
#define	ENET_TCCR_TCC_MASK   (0xFFFFFFFFU)
#define	ENET_TCCR_TCC_SHIFT   (0U)
#define	ENET_TCCR_TCC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
#define	ENET_TCCR_TCC_MASK   (0xFFFFFFFFU)
#define	ENET_TCCR_TCC_SHIFT   (0U)
#define	ENET_TCCR_TCC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
#define	ENET_TCCR_TCC_MASK   (0xFFFFFFFFU)
#define	ENET_TCCR_TCC_SHIFT   (0U)
#define	ENET_TCCR_TCC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)

TCCR - Timer Compare Capture Register
#define	ENET_TCCR_COUNT   (4U)

IEEE_T_SQE - Reserved Statistic Register
#define	ENET_IEEE_T_SQE_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_SQE_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_SQE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
#define	ENET_IEEE_T_SQE_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_SQE_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_SQE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
#define	ENET_IEEE_T_SQE_COUNT_MASK   (0xFFFFU)
#define	ENET_IEEE_T_SQE_COUNT_SHIFT   (0U)
#define	ENET_IEEE_T_SQE_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)

Macro Definition Documentation

ENET

#define ENET   ((ENET_Type *)ENET_BASE)

Peripheral ENET base pointer

ENET_ATCR_CAPTURE [1/5]

#define ENET_ATCR_CAPTURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.

ENET_ATCR_CAPTURE [2/5]

#define ENET_ATCR_CAPTURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.

ENET_ATCR_CAPTURE [3/5]

#define ENET_ATCR_CAPTURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.

ENET_ATCR_CAPTURE [4/5]

#define ENET_ATCR_CAPTURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.

ENET_ATCR_CAPTURE [5/5]

#define ENET_ATCR_CAPTURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)

CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.

ENET_ATCR_EN [1/5]

#define ENET_ATCR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.

ENET_ATCR_EN [2/5]

#define ENET_ATCR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.

ENET_ATCR_EN [3/5]

#define ENET_ATCR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.

ENET_ATCR_EN [4/5]

#define ENET_ATCR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.

ENET_ATCR_EN [5/5]

#define ENET_ATCR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)

EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.

ENET_ATCR_OFFEN [1/5]

#define ENET_ATCR_OFFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.

ENET_ATCR_OFFEN [2/5]

#define ENET_ATCR_OFFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.

ENET_ATCR_OFFEN [3/5]

#define ENET_ATCR_OFFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.

ENET_ATCR_OFFEN [4/5]

#define ENET_ATCR_OFFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.

ENET_ATCR_OFFEN [5/5]

#define ENET_ATCR_OFFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)

OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.

ENET_ATCR_OFFRST [1/5]

#define ENET_ATCR_OFFRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.

ENET_ATCR_OFFRST [2/5]

#define ENET_ATCR_OFFRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.

ENET_ATCR_OFFRST [3/5]

#define ENET_ATCR_OFFRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.

ENET_ATCR_OFFRST [4/5]

#define ENET_ATCR_OFFRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.

ENET_ATCR_OFFRST [5/5]

#define ENET_ATCR_OFFRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)

OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.

ENET_ATCR_PEREN [1/5]

#define ENET_ATCR_PEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.

ENET_ATCR_PEREN [2/5]

#define ENET_ATCR_PEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.

ENET_ATCR_PEREN [3/5]

#define ENET_ATCR_PEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.

ENET_ATCR_PEREN [4/5]

#define ENET_ATCR_PEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.

ENET_ATCR_PEREN [5/5]

#define ENET_ATCR_PEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)

PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.

ENET_ATCR_PINPER [1/5]

#define ENET_ATCR_PINPER

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

PINPER 0b0..Disable. 0b1..Enable.

ENET_ATCR_PINPER [2/5]

#define ENET_ATCR_PINPER

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

PINPER 0b0..Disable. 0b1..Enable.

ENET_ATCR_PINPER [3/5]

#define ENET_ATCR_PINPER

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

PINPER 0b0..Disable. 0b1..Enable.

ENET_ATCR_PINPER [4/5]

#define ENET_ATCR_PINPER

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

PINPER 0b0..Disable. 0b1..Enable.

ENET_ATCR_PINPER [5/5]

#define ENET_ATCR_PINPER

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)

PINPER 0b0..Disable. 0b1..Enable.

ENET_ATCR_SLAVE [1/5]

#define ENET_ATCR_SLAVE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.

ENET_ATCR_SLAVE [2/5]

#define ENET_ATCR_SLAVE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.

ENET_ATCR_SLAVE [3/5]

#define ENET_ATCR_SLAVE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.

ENET_ATCR_SLAVE [4/5]

#define ENET_ATCR_SLAVE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.

ENET_ATCR_SLAVE [5/5]

#define ENET_ATCR_SLAVE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)

SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.

ENET_BASE

#define ENET_BASE   (0x400C0000u)

Peripheral ENET base address

ENET_BASE_ADDRS

#define ENET_BASE_ADDRS   { ENET_BASE }

Array initializer of ENET peripheral base addresses

ENET_BASE_PTRS

#define ENET_BASE_PTRS   { ENET }

Array initializer of ENET peripheral base pointers

ENET_ECR_DBGEN [1/5]

#define ENET_ECR_DBGEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.

ENET_ECR_DBGEN [2/5]

#define ENET_ECR_DBGEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.

ENET_ECR_DBGEN [3/5]

#define ENET_ECR_DBGEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.

ENET_ECR_DBGEN [4/5]

#define ENET_ECR_DBGEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.

ENET_ECR_DBGEN [5/5]

#define ENET_ECR_DBGEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)

DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.

ENET_ECR_DBSWP [1/5]

#define ENET_ECR_DBSWP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.

ENET_ECR_DBSWP [2/5]

#define ENET_ECR_DBSWP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.

ENET_ECR_DBSWP [3/5]

#define ENET_ECR_DBSWP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.

ENET_ECR_DBSWP [4/5]

#define ENET_ECR_DBSWP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.

ENET_ECR_DBSWP [5/5]

#define ENET_ECR_DBSWP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)

DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.

ENET_ECR_EN1588 [1/5]

#define ENET_ECR_EN1588

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.

ENET_ECR_EN1588 [2/5]

#define ENET_ECR_EN1588

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.

ENET_ECR_EN1588 [3/5]

#define ENET_ECR_EN1588

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.

ENET_ECR_EN1588 [4/5]

#define ENET_ECR_EN1588

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.

ENET_ECR_EN1588 [5/5]

#define ENET_ECR_EN1588

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)

EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.

ENET_ECR_ETHEREN [1/5]

#define ENET_ECR_ETHEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.

ENET_ECR_ETHEREN [2/5]

#define ENET_ECR_ETHEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.

ENET_ECR_ETHEREN [3/5]

#define ENET_ECR_ETHEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.

ENET_ECR_ETHEREN [4/5]

#define ENET_ECR_ETHEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.

ENET_ECR_ETHEREN [5/5]

#define ENET_ECR_ETHEREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)

ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.

ENET_ECR_MAGICEN [1/5]

#define ENET_ECR_MAGICEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.

ENET_ECR_MAGICEN [2/5]

#define ENET_ECR_MAGICEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.

ENET_ECR_MAGICEN [3/5]

#define ENET_ECR_MAGICEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.

ENET_ECR_MAGICEN [4/5]

#define ENET_ECR_MAGICEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.

ENET_ECR_MAGICEN [5/5]

#define ENET_ECR_MAGICEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)

MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.

ENET_ECR_SLEEP [1/5]

#define ENET_ECR_SLEEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.

ENET_ECR_SLEEP [2/5]

#define ENET_ECR_SLEEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.

ENET_ECR_SLEEP [3/5]

#define ENET_ECR_SLEEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.

ENET_ECR_SLEEP [4/5]

#define ENET_ECR_SLEEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.

ENET_ECR_SLEEP [5/5]

#define ENET_ECR_SLEEP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)

SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.

ENET_EIMR_BABR [1/5]

#define ENET_EIMR_BABR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_BABR [2/5]

#define ENET_EIMR_BABR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_BABR [3/5]

#define ENET_EIMR_BABR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_BABR [4/5]

#define ENET_EIMR_BABR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_BABR [5/5]

#define ENET_EIMR_BABR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)

BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_BABT [1/5]

#define ENET_EIMR_BABT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_BABT [2/5]

#define ENET_EIMR_BABT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_BABT [3/5]

#define ENET_EIMR_BABT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_BABT [4/5]

#define ENET_EIMR_BABT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_BABT [5/5]

#define ENET_EIMR_BABT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)

BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_GRA [1/5]

#define ENET_EIMR_GRA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_GRA [2/5]

#define ENET_EIMR_GRA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_GRA [3/5]

#define ENET_EIMR_GRA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_GRA [4/5]

#define ENET_EIMR_GRA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_GRA [5/5]

#define ENET_EIMR_GRA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)

GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_TXB [1/5]

#define ENET_EIMR_TXB

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_TXB [2/5]

#define ENET_EIMR_TXB

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_TXB [3/5]

#define ENET_EIMR_TXB

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_TXB [4/5]

#define ENET_EIMR_TXB

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_TXB [5/5]

#define ENET_EIMR_TXB

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)

TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_TXF [1/5]

#define ENET_EIMR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_TXF [2/5]

#define ENET_EIMR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_TXF [3/5]

#define ENET_EIMR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_TXF [4/5]

#define ENET_EIMR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_EIMR_TXF [5/5]

#define ENET_EIMR_TXF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)

TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.

ENET_MIBC_MIB_CLEAR [1/5]

#define ENET_MIBC_MIB_CLEAR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.

ENET_MIBC_MIB_CLEAR [2/5]

#define ENET_MIBC_MIB_CLEAR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.

ENET_MIBC_MIB_CLEAR [3/5]

#define ENET_MIBC_MIB_CLEAR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.

ENET_MIBC_MIB_CLEAR [4/5]

#define ENET_MIBC_MIB_CLEAR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.

ENET_MIBC_MIB_CLEAR [5/5]

#define ENET_MIBC_MIB_CLEAR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)

MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.

ENET_MIBC_MIB_DIS [1/5]

#define ENET_MIBC_MIB_DIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.

ENET_MIBC_MIB_DIS [2/5]

#define ENET_MIBC_MIB_DIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.

ENET_MIBC_MIB_DIS [3/5]

#define ENET_MIBC_MIB_DIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.

ENET_MIBC_MIB_DIS [4/5]

#define ENET_MIBC_MIB_DIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.

ENET_MIBC_MIB_DIS [5/5]

#define ENET_MIBC_MIB_DIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)

MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.

ENET_MIBC_MIB_IDLE [1/5]

#define ENET_MIBC_MIB_IDLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.

ENET_MIBC_MIB_IDLE [2/5]

#define ENET_MIBC_MIB_IDLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.

ENET_MIBC_MIB_IDLE [3/5]

#define ENET_MIBC_MIB_IDLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.

ENET_MIBC_MIB_IDLE [4/5]

#define ENET_MIBC_MIB_IDLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.

ENET_MIBC_MIB_IDLE [5/5]

#define ENET_MIBC_MIB_IDLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)

MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.

ENET_MMFR_OP [1/3]

#define ENET_MMFR_OP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)

OP - Operation Code 0b00..Write frame operation, but not MII compliant. 0b01..Write frame operation for a valid MII management frame. 0b10..Read frame operation for a valid MII management frame. 0b11..Read frame operation, but not MII compliant.

ENET_MMFR_OP [2/3]

#define ENET_MMFR_OP

(

x

)

(((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)

OP - Operation Code 0b00..Write frame operation, but not MII compliant. 0b01..Write frame operation for a valid MII management frame. 0b10..Read frame operation for a valid MII management frame. 0b11..Read frame operation, but not MII compliant.

ENET_MMFR_OP [3/3]

#define ENET_MMFR_OP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)

OP - Operation Code 0b00..Write frame operation, but not MII compliant. 0b01..Write frame operation for a valid MII management frame. 0b10..Read frame operation for a valid MII management frame. 0b11..Read frame operation, but not MII compliant.

ENET_MSCR_DIS_PRE [1/5]

#define ENET_MSCR_DIS_PRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.

ENET_MSCR_DIS_PRE [2/5]

#define ENET_MSCR_DIS_PRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.

ENET_MSCR_DIS_PRE [3/5]

#define ENET_MSCR_DIS_PRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.

ENET_MSCR_DIS_PRE [4/5]

#define ENET_MSCR_DIS_PRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.

ENET_MSCR_DIS_PRE [5/5]

#define ENET_MSCR_DIS_PRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)

DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.

ENET_MSCR_HOLDTIME [1/6]

#define ENET_MSCR_HOLDTIME

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles

ENET_MSCR_HOLDTIME [2/6]

#define ENET_MSCR_HOLDTIME

(

x

)

(((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)

HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles

ENET_MSCR_HOLDTIME [3/6]

#define ENET_MSCR_HOLDTIME

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles

ENET_MSCR_HOLDTIME [4/6]

#define ENET_MSCR_HOLDTIME

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles

ENET_MSCR_HOLDTIME [5/6]

#define ENET_MSCR_HOLDTIME

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles

ENET_MSCR_HOLDTIME [6/6]

#define ENET_MSCR_HOLDTIME

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)

HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles

ENET_RACC_IPDIS [1/5]

#define ENET_RACC_IPDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

ENET_RACC_IPDIS [2/5]

#define ENET_RACC_IPDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

ENET_RACC_IPDIS [3/5]

#define ENET_RACC_IPDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

ENET_RACC_IPDIS [4/5]

#define ENET_RACC_IPDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

ENET_RACC_IPDIS [5/5]

#define ENET_RACC_IPDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)

IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

ENET_RACC_LINEDIS [1/5]

#define ENET_RACC_LINEDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.

ENET_RACC_LINEDIS [2/5]

#define ENET_RACC_LINEDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.

ENET_RACC_LINEDIS [3/5]

#define ENET_RACC_LINEDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.

ENET_RACC_LINEDIS [4/5]

#define ENET_RACC_LINEDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.

ENET_RACC_LINEDIS [5/5]

#define ENET_RACC_LINEDIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)

LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.

ENET_RACC_PADREM [1/5]

#define ENET_RACC_PADREM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.

ENET_RACC_PADREM [2/5]

#define ENET_RACC_PADREM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.

ENET_RACC_PADREM [3/5]

#define ENET_RACC_PADREM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.

ENET_RACC_PADREM [4/5]

#define ENET_RACC_PADREM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.

ENET_RACC_PADREM [5/5]

#define ENET_RACC_PADREM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)

PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.

ENET_RACC_PRODIS [1/5]

#define ENET_RACC_PRODIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

ENET_RACC_PRODIS [2/5]

#define ENET_RACC_PRODIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

ENET_RACC_PRODIS [3/5]

#define ENET_RACC_PRODIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

ENET_RACC_PRODIS [4/5]

#define ENET_RACC_PRODIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

ENET_RACC_PRODIS [5/5]

#define ENET_RACC_PRODIS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)

PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).

ENET_RACC_SHIFT16 [1/5]

#define ENET_RACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.

ENET_RACC_SHIFT16 [2/5]

#define ENET_RACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.

ENET_RACC_SHIFT16 [3/5]

#define ENET_RACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.

ENET_RACC_SHIFT16 [4/5]

#define ENET_RACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.

ENET_RACC_SHIFT16 [5/5]

#define ENET_RACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)

SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.

ENET_RCR_CFEN [1/5]

#define ENET_RCR_CFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.

ENET_RCR_CFEN [2/5]

#define ENET_RCR_CFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.

ENET_RCR_CFEN [3/5]

#define ENET_RCR_CFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.

ENET_RCR_CFEN [4/5]

#define ENET_RCR_CFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.

ENET_RCR_CFEN [5/5]

#define ENET_RCR_CFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)

CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.

ENET_RCR_CRCFWD [1/5]

#define ENET_RCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.

ENET_RCR_CRCFWD [2/5]

#define ENET_RCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.

ENET_RCR_CRCFWD [3/5]

#define ENET_RCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.

ENET_RCR_CRCFWD [4/5]

#define ENET_RCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.

ENET_RCR_CRCFWD [5/5]

#define ENET_RCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)

CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.

ENET_RCR_DRT [1/5]

#define ENET_RCR_DRT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. Normally used for half-duplex mode.

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)

ENET_RCR_DRT [2/5]

#define ENET_RCR_DRT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. Normally used for half-duplex mode.

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)

ENET_RCR_DRT [3/5]

#define ENET_RCR_DRT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. Normally used for half-duplex mode.

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)

ENET_RCR_DRT [4/5]

#define ENET_RCR_DRT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. Normally used for half-duplex mode.

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)

ENET_RCR_DRT [5/5]

#define ENET_RCR_DRT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)

DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)

ENET_RCR_LOOP [1/5]

#define ENET_RCR_LOOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.

ENET_RCR_LOOP [2/5]

#define ENET_RCR_LOOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.

ENET_RCR_LOOP [3/5]

#define ENET_RCR_LOOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.

ENET_RCR_LOOP [4/5]

#define ENET_RCR_LOOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.

ENET_RCR_LOOP [5/5]

#define ENET_RCR_LOOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)

LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.

ENET_RCR_MII_MODE [1/5]

#define ENET_RCR_MII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.

ENET_RCR_MII_MODE [2/5]

#define ENET_RCR_MII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.

ENET_RCR_MII_MODE [3/5]

#define ENET_RCR_MII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.

ENET_RCR_MII_MODE [4/5]

#define ENET_RCR_MII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.

ENET_RCR_MII_MODE [5/5]

#define ENET_RCR_MII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)

MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.

ENET_RCR_NLC [1/5]

#define ENET_RCR_NLC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.

ENET_RCR_NLC [2/5]

#define ENET_RCR_NLC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.

ENET_RCR_NLC [3/5]

#define ENET_RCR_NLC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.

ENET_RCR_NLC [4/5]

#define ENET_RCR_NLC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.

ENET_RCR_NLC [5/5]

#define ENET_RCR_NLC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)

NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.

ENET_RCR_PADEN [1/5]

#define ENET_RCR_PADEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.

ENET_RCR_PADEN [2/5]

#define ENET_RCR_PADEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.

ENET_RCR_PADEN [3/5]

#define ENET_RCR_PADEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.

ENET_RCR_PADEN [4/5]

#define ENET_RCR_PADEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.

ENET_RCR_PADEN [5/5]

#define ENET_RCR_PADEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)

PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.

ENET_RCR_PAUFWD [1/5]

#define ENET_RCR_PAUFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.

ENET_RCR_PAUFWD [2/5]

#define ENET_RCR_PAUFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.

ENET_RCR_PAUFWD [3/5]

#define ENET_RCR_PAUFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.

ENET_RCR_PAUFWD [4/5]

#define ENET_RCR_PAUFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.

ENET_RCR_PAUFWD [5/5]

#define ENET_RCR_PAUFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)

PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.

ENET_RCR_PROM [1/5]

#define ENET_RCR_PROM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.

ENET_RCR_PROM [2/5]

#define ENET_RCR_PROM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.

ENET_RCR_PROM [3/5]

#define ENET_RCR_PROM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.

ENET_RCR_PROM [4/5]

#define ENET_RCR_PROM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.

ENET_RCR_PROM [5/5]

#define ENET_RCR_PROM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)

PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.

ENET_RCR_RMII_10T [1/5]

#define ENET_RCR_RMII_10T

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

RMII_10T 0b0..100 Mbps operation. 0b1..10 Mbps operation.

RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.

ENET_RCR_RMII_10T [2/5]

#define ENET_RCR_RMII_10T

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

RMII_10T 0b0..100 Mbps operation. 0b1..10 Mbps operation.

RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.

ENET_RCR_RMII_10T [3/5]

#define ENET_RCR_RMII_10T

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

RMII_10T 0b0..100 Mbps operation. 0b1..10 Mbps operation.

RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.

ENET_RCR_RMII_10T [4/5]

#define ENET_RCR_RMII_10T

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

RMII_10T 0b0..100 Mbps operation. 0b1..10 Mbps operation.

RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.

ENET_RCR_RMII_10T [5/5]

#define ENET_RCR_RMII_10T

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)

RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.

ENET_RCR_RMII_MODE [1/5]

#define ENET_RCR_RMII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.

ENET_RCR_RMII_MODE [2/5]

#define ENET_RCR_RMII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.

ENET_RCR_RMII_MODE [3/5]

#define ENET_RCR_RMII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.

ENET_RCR_RMII_MODE [4/5]

#define ENET_RCR_RMII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.

ENET_RCR_RMII_MODE [5/5]

#define ENET_RCR_RMII_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)

RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.

ENET_TACC_IPCHK [1/5]

#define ENET_TACC_IPCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.

ENET_TACC_IPCHK [2/5]

#define ENET_TACC_IPCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.

ENET_TACC_IPCHK [3/5]

#define ENET_TACC_IPCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.

ENET_TACC_IPCHK [4/5]

#define ENET_TACC_IPCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.

ENET_TACC_IPCHK [5/5]

#define ENET_TACC_IPCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)

IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.

ENET_TACC_PROCHK [1/5]

#define ENET_TACC_PROCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.

ENET_TACC_PROCHK [2/5]

#define ENET_TACC_PROCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.

ENET_TACC_PROCHK [3/5]

#define ENET_TACC_PROCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.

ENET_TACC_PROCHK [4/5]

#define ENET_TACC_PROCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.

ENET_TACC_PROCHK [5/5]

#define ENET_TACC_PROCHK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)

PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.

ENET_TACC_SHIFT16 [1/5]

#define ENET_TACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.

ENET_TACC_SHIFT16 [2/5]

#define ENET_TACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.

ENET_TACC_SHIFT16 [3/5]

#define ENET_TACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.

ENET_TACC_SHIFT16 [4/5]

#define ENET_TACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.

ENET_TACC_SHIFT16 [5/5]

#define ENET_TACC_SHIFT16

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)

SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.

ENET_TCR_ADDINS [1/5]

#define ENET_TCR_ADDINS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.

ENET_TCR_ADDINS [2/5]

#define ENET_TCR_ADDINS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.

ENET_TCR_ADDINS [3/5]

#define ENET_TCR_ADDINS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.

ENET_TCR_ADDINS [4/5]

#define ENET_TCR_ADDINS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.

ENET_TCR_ADDINS [5/5]

#define ENET_TCR_ADDINS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)

ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.

ENET_TCR_ADDSEL [1/6]

#define ENET_TCR_ADDSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.

ENET_TCR_ADDSEL [2/6]

#define ENET_TCR_ADDSEL

(

x

)

(((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)

ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.

ENET_TCR_ADDSEL [3/6]

#define ENET_TCR_ADDSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.

ENET_TCR_ADDSEL [4/6]

#define ENET_TCR_ADDSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.

ENET_TCR_ADDSEL [5/6]

#define ENET_TCR_ADDSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.

ENET_TCR_ADDSEL [6/6]

#define ENET_TCR_ADDSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)

ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.

ENET_TCR_CRCFWD [1/5]

#define ENET_TCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.

ENET_TCR_CRCFWD [2/5]

#define ENET_TCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.

ENET_TCR_CRCFWD [3/5]

#define ENET_TCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.

ENET_TCR_CRCFWD [4/5]

#define ENET_TCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.

ENET_TCR_CRCFWD [5/5]

#define ENET_TCR_CRCFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)

CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.

ENET_TCR_TFC_PAUSE [1/5]

#define ENET_TCR_TFC_PAUSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.

ENET_TCR_TFC_PAUSE [2/5]

#define ENET_TCR_TFC_PAUSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.

ENET_TCR_TFC_PAUSE [3/5]

#define ENET_TCR_TFC_PAUSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.

ENET_TCR_TFC_PAUSE [4/5]

#define ENET_TCR_TFC_PAUSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.

ENET_TCR_TFC_PAUSE [5/5]

#define ENET_TCR_TFC_PAUSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)

TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.

ENET_TCSR_TDRE [1/5]

#define ENET_TCSR_TDRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

ENET_TCSR_TDRE [2/5]

#define ENET_TCSR_TDRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

ENET_TCSR_TDRE [3/5]

#define ENET_TCSR_TDRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

ENET_TCSR_TDRE [4/5]

#define ENET_TCSR_TDRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

ENET_TCSR_TDRE [5/5]

#define ENET_TCSR_TDRE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)

TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled

ENET_TCSR_TF [1/5]

#define ENET_TCSR_TF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred 0b1..Input Capture or Output Compare has occurred

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.

ENET_TCSR_TF [2/5]

#define ENET_TCSR_TF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred 0b1..Input Capture or Output Compare has occurred

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.

ENET_TCSR_TF [3/5]

#define ENET_TCSR_TF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.

ENET_TCSR_TF [4/5]

#define ENET_TCSR_TF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.

ENET_TCSR_TF [5/5]

#define ENET_TCSR_TF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)

TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.

ENET_TCSR_TIE [1/5]

#define ENET_TCSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled

ENET_TCSR_TIE [2/5]

#define ENET_TCSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled

ENET_TCSR_TIE [3/5]

#define ENET_TCSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled

ENET_TCSR_TIE [4/5]

#define ENET_TCSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled

ENET_TCSR_TIE [5/5]

#define ENET_TCSR_TIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)

TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled

ENET_TCSR_TMODE [1/6]

#define ENET_TCSR_TMODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge 0b0010..Timer Channel is configured for Input Capture on falling edge 0b0011..Timer Channel is configured for Input Capture on both edges 0b0100..Timer Channel is configured for Output Compare - software only 0b0101..Timer Channel is configured for Output Compare - toggle output on compare 0b0110..Timer Channel is configured for Output Compare - clear output on compare 0b0111..Timer Channel is configured for Output Compare - set output on compare 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow 0b1100..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.

ENET_TCSR_TMODE [2/6]

#define ENET_TCSR_TMODE

(

x

)

(((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge 0b0010..Timer Channel is configured for Input Capture on falling edge 0b0011..Timer Channel is configured for Input Capture on both edges 0b0100..Timer Channel is configured for Output Compare - software only 0b0101..Timer Channel is configured for Output Compare - toggle output on compare 0b0110..Timer Channel is configured for Output Compare - clear output on compare 0b0111..Timer Channel is configured for Output Compare - set output on compare 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow 0b1100..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.

ENET_TCSR_TMODE [3/6]

#define ENET_TCSR_TMODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge 0b0010..Timer Channel is configured for Input Capture on falling edge 0b0011..Timer Channel is configured for Input Capture on both edges 0b0100..Timer Channel is configured for Output Compare - software only 0b0101..Timer Channel is configured for Output Compare - toggle output on compare 0b0110..Timer Channel is configured for Output Compare - clear output on compare 0b0111..Timer Channel is configured for Output Compare - set output on compare 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow 0b1100..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.

ENET_TCSR_TMODE [4/6]

#define ENET_TCSR_TMODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.

ENET_TCSR_TMODE [5/6]

#define ENET_TCSR_TMODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.

ENET_TCSR_TMODE [6/6]

#define ENET_TCSR_TMODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)

TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.

ENET_TFWR_STRFWD [1/5]

#define ENET_TFWR_STRFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.

ENET_TFWR_STRFWD [2/5]

#define ENET_TFWR_STRFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.

ENET_TFWR_STRFWD [3/5]

#define ENET_TFWR_STRFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.

ENET_TFWR_STRFWD [4/5]

#define ENET_TFWR_STRFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.

ENET_TFWR_STRFWD [5/5]

#define ENET_TFWR_STRFWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)

STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.

ENET_TFWR_TFWR [1/6]

#define ENET_TFWR_TFWR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)

TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b111110..3968 bytes written. 0b111111..4032 bytes written.

TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.

ENET_TFWR_TFWR [2/6]

#define ENET_TFWR_TFWR

(

x

)

(((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)

TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b111110..3968 bytes written. 0b111111..4032 bytes written.

TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.

ENET_TFWR_TFWR [3/6]

#define ENET_TFWR_TFWR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)

TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b111110..3968 bytes written. 0b111111..4032 bytes written.

TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.

ENET_TFWR_TFWR [4/6]

#define ENET_TFWR_TFWR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)

TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.

ENET_TFWR_TFWR [5/6]

#define ENET_TFWR_TFWR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)

TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.

ENET_TFWR_TFWR [6/6]

#define ENET_TFWR_TFWR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)

TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.

ENET_TGSR_TF0 [1/5]

#define ENET_TGSR_TF0

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)

TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set

ENET_TGSR_TF0 [2/5]

#define ENET_TGSR_TF0

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)

TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set

ENET_TGSR_TF0 [3/5]

#define ENET_TGSR_TF0

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)

TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set

ENET_TGSR_TF0 [4/5]

#define ENET_TGSR_TF0

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)

TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set

ENET_TGSR_TF0 [5/5]

#define ENET_TGSR_TF0

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)

TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set

ENET_TGSR_TF1 [1/5]

#define ENET_TGSR_TF1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)

TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set

ENET_TGSR_TF1 [2/5]

#define ENET_TGSR_TF1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)

TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set

ENET_TGSR_TF1 [3/5]

#define ENET_TGSR_TF1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)

TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set

ENET_TGSR_TF1 [4/5]

#define ENET_TGSR_TF1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)

TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set

ENET_TGSR_TF1 [5/5]

#define ENET_TGSR_TF1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)

TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set

ENET_TGSR_TF2 [1/5]

#define ENET_TGSR_TF2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)

TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set

ENET_TGSR_TF2 [2/5]

#define ENET_TGSR_TF2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)

TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set

ENET_TGSR_TF2 [3/5]

#define ENET_TGSR_TF2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)

TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set

ENET_TGSR_TF2 [4/5]

#define ENET_TGSR_TF2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)

TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set

ENET_TGSR_TF2 [5/5]

#define ENET_TGSR_TF2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)

TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set

ENET_TGSR_TF3 [1/5]

#define ENET_TGSR_TF3

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set

ENET_TGSR_TF3 [2/5]

#define ENET_TGSR_TF3

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set

ENET_TGSR_TF3 [3/5]

#define ENET_TGSR_TF3

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set

ENET_TGSR_TF3 [4/5]

#define ENET_TGSR_TF3

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set

ENET_TGSR_TF3 [5/5]

#define ENET_TGSR_TF3

(

x

)

(((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)

TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set

ENET_Transmit_IRQS

#define ENET_Transmit_IRQS   { ENET_Transmit_IRQn }

Interrupt vectors for the ENET peripheral type