mikroSDK Reference Manual
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Macros | |
#define | ENET_BASE (0x400C0000u) |
#define | ENET ((ENET_Type *)ENET_BASE) |
#define | ENET_BASE_ADDRS { ENET_BASE } |
#define | ENET_BASE_PTRS { ENET } |
#define | ENET_Transmit_IRQS { ENET_Transmit_IRQn } |
#define | ENET_Receive_IRQS { ENET_Receive_IRQn } |
#define | ENET_Error_IRQS { ENET_Error_IRQn } |
#define | ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } |
#define | ENET_BUFF_ALIGNMENT (16U) |
#define | ENET_TCSR_COUNT (4U) |
#define | ENET_TCCR_COUNT (4U) |
#define | ENET_TCSR_COUNT (4U) |
#define | ENET_TCCR_COUNT (4U) |
#define | ENET_TCSR_COUNT (4U) |
#define | ENET_TCCR_COUNT (4U) |
#define | ENET_TCSR_COUNT (4U) |
#define | ENET_TCCR_COUNT (4U) |
EIMR - Interrupt Mask Register | |
#define | ENET_EIMR_TS_TIMER_MASK (0x8000U) |
#define | ENET_EIMR_TS_TIMER_SHIFT (15U) |
#define | ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) |
#define | ENET_EIMR_TS_AVAIL_MASK (0x10000U) |
#define | ENET_EIMR_TS_AVAIL_SHIFT (16U) |
#define | ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) |
#define | ENET_EIMR_WAKEUP_MASK (0x20000U) |
#define | ENET_EIMR_WAKEUP_SHIFT (17U) |
#define | ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) |
#define | ENET_EIMR_PLR_MASK (0x40000U) |
#define | ENET_EIMR_PLR_SHIFT (18U) |
#define | ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) |
#define | ENET_EIMR_UN_MASK (0x80000U) |
#define | ENET_EIMR_UN_SHIFT (19U) |
#define | ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) |
#define | ENET_EIMR_RL_MASK (0x100000U) |
#define | ENET_EIMR_RL_SHIFT (20U) |
#define | ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) |
#define | ENET_EIMR_LC_MASK (0x200000U) |
#define | ENET_EIMR_LC_SHIFT (21U) |
#define | ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) |
#define | ENET_EIMR_EBERR_MASK (0x400000U) |
#define | ENET_EIMR_EBERR_SHIFT (22U) |
#define | ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) |
#define | ENET_EIMR_MII_MASK (0x800000U) |
#define | ENET_EIMR_MII_SHIFT (23U) |
#define | ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) |
#define | ENET_EIMR_RXB_MASK (0x1000000U) |
#define | ENET_EIMR_RXB_SHIFT (24U) |
#define | ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) |
#define | ENET_EIMR_RXF_MASK (0x2000000U) |
#define | ENET_EIMR_RXF_SHIFT (25U) |
#define | ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) |
#define | ENET_EIMR_TXB_MASK (0x4000000U) |
#define | ENET_EIMR_TXB_SHIFT (26U) |
#define | ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
#define | ENET_EIMR_TXF_MASK (0x8000000U) |
#define | ENET_EIMR_TXF_SHIFT (27U) |
#define | ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
#define | ENET_EIMR_GRA_MASK (0x10000000U) |
#define | ENET_EIMR_GRA_SHIFT (28U) |
#define | ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
#define | ENET_EIMR_BABT_MASK (0x20000000U) |
#define | ENET_EIMR_BABT_SHIFT (29U) |
#define | ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
#define | ENET_EIMR_BABR_MASK (0x40000000U) |
#define | ENET_EIMR_BABR_SHIFT (30U) |
#define | ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
#define | ENET_EIMR_TS_TIMER_MASK 0x8000u |
#define | ENET_EIMR_TS_TIMER_SHIFT 15 |
#define | ENET_EIMR_TS_AVAIL_MASK 0x10000u |
#define | ENET_EIMR_TS_AVAIL_SHIFT 16 |
#define | ENET_EIMR_WAKEUP_MASK 0x20000u |
#define | ENET_EIMR_WAKEUP_SHIFT 17 |
#define | ENET_EIMR_PLR_MASK 0x40000u |
#define | ENET_EIMR_PLR_SHIFT 18 |
#define | ENET_EIMR_UN_MASK 0x80000u |
#define | ENET_EIMR_UN_SHIFT 19 |
#define | ENET_EIMR_RL_MASK 0x100000u |
#define | ENET_EIMR_RL_SHIFT 20 |
#define | ENET_EIMR_LC_MASK 0x200000u |
#define | ENET_EIMR_LC_SHIFT 21 |
#define | ENET_EIMR_EBERR_MASK 0x400000u |
#define | ENET_EIMR_EBERR_SHIFT 22 |
#define | ENET_EIMR_MII_MASK 0x800000u |
#define | ENET_EIMR_MII_SHIFT 23 |
#define | ENET_EIMR_RXB_MASK 0x1000000u |
#define | ENET_EIMR_RXB_SHIFT 24 |
#define | ENET_EIMR_RXF_MASK 0x2000000u |
#define | ENET_EIMR_RXF_SHIFT 25 |
#define | ENET_EIMR_TXB_MASK 0x4000000u |
#define | ENET_EIMR_TXB_SHIFT 26 |
#define | ENET_EIMR_TXF_MASK 0x8000000u |
#define | ENET_EIMR_TXF_SHIFT 27 |
#define | ENET_EIMR_GRA_MASK 0x10000000u |
#define | ENET_EIMR_GRA_SHIFT 28 |
#define | ENET_EIMR_BABT_MASK 0x20000000u |
#define | ENET_EIMR_BABT_SHIFT 29 |
#define | ENET_EIMR_BABR_MASK 0x40000000u |
#define | ENET_EIMR_BABR_SHIFT 30 |
#define | ENET_EIMR_TS_TIMER_MASK (0x8000U) |
#define | ENET_EIMR_TS_TIMER_SHIFT (15U) |
#define | ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) |
#define | ENET_EIMR_TS_AVAIL_MASK (0x10000U) |
#define | ENET_EIMR_TS_AVAIL_SHIFT (16U) |
#define | ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) |
#define | ENET_EIMR_WAKEUP_MASK (0x20000U) |
#define | ENET_EIMR_WAKEUP_SHIFT (17U) |
#define | ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) |
#define | ENET_EIMR_PLR_MASK (0x40000U) |
#define | ENET_EIMR_PLR_SHIFT (18U) |
#define | ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) |
#define | ENET_EIMR_UN_MASK (0x80000U) |
#define | ENET_EIMR_UN_SHIFT (19U) |
#define | ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) |
#define | ENET_EIMR_RL_MASK (0x100000U) |
#define | ENET_EIMR_RL_SHIFT (20U) |
#define | ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) |
#define | ENET_EIMR_LC_MASK (0x200000U) |
#define | ENET_EIMR_LC_SHIFT (21U) |
#define | ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) |
#define | ENET_EIMR_EBERR_MASK (0x400000U) |
#define | ENET_EIMR_EBERR_SHIFT (22U) |
#define | ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) |
#define | ENET_EIMR_MII_MASK (0x800000U) |
#define | ENET_EIMR_MII_SHIFT (23U) |
#define | ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) |
#define | ENET_EIMR_RXB_MASK (0x1000000U) |
#define | ENET_EIMR_RXB_SHIFT (24U) |
#define | ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) |
#define | ENET_EIMR_RXF_MASK (0x2000000U) |
#define | ENET_EIMR_RXF_SHIFT (25U) |
#define | ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) |
#define | ENET_EIMR_TXB_MASK (0x4000000U) |
#define | ENET_EIMR_TXB_SHIFT (26U) |
#define | ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
#define | ENET_EIMR_TXF_MASK (0x8000000U) |
#define | ENET_EIMR_TXF_SHIFT (27U) |
#define | ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
#define | ENET_EIMR_GRA_MASK (0x10000000U) |
#define | ENET_EIMR_GRA_SHIFT (28U) |
#define | ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
#define | ENET_EIMR_BABT_MASK (0x20000000U) |
#define | ENET_EIMR_BABT_SHIFT (29U) |
#define | ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
#define | ENET_EIMR_BABR_MASK (0x40000000U) |
#define | ENET_EIMR_BABR_SHIFT (30U) |
#define | ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
#define | ENET_EIMR_TS_TIMER_MASK (0x8000U) |
#define | ENET_EIMR_TS_TIMER_SHIFT (15U) |
#define | ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) |
#define | ENET_EIMR_TS_AVAIL_MASK (0x10000U) |
#define | ENET_EIMR_TS_AVAIL_SHIFT (16U) |
#define | ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) |
#define | ENET_EIMR_WAKEUP_MASK (0x20000U) |
#define | ENET_EIMR_WAKEUP_SHIFT (17U) |
#define | ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) |
#define | ENET_EIMR_PLR_MASK (0x40000U) |
#define | ENET_EIMR_PLR_SHIFT (18U) |
#define | ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) |
#define | ENET_EIMR_UN_MASK (0x80000U) |
#define | ENET_EIMR_UN_SHIFT (19U) |
#define | ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) |
#define | ENET_EIMR_RL_MASK (0x100000U) |
#define | ENET_EIMR_RL_SHIFT (20U) |
#define | ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) |
#define | ENET_EIMR_LC_MASK (0x200000U) |
#define | ENET_EIMR_LC_SHIFT (21U) |
#define | ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) |
#define | ENET_EIMR_EBERR_MASK (0x400000U) |
#define | ENET_EIMR_EBERR_SHIFT (22U) |
#define | ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) |
#define | ENET_EIMR_MII_MASK (0x800000U) |
#define | ENET_EIMR_MII_SHIFT (23U) |
#define | ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) |
#define | ENET_EIMR_RXB_MASK (0x1000000U) |
#define | ENET_EIMR_RXB_SHIFT (24U) |
#define | ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) |
#define | ENET_EIMR_RXF_MASK (0x2000000U) |
#define | ENET_EIMR_RXF_SHIFT (25U) |
#define | ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) |
#define | ENET_EIMR_TXB_MASK (0x4000000U) |
#define | ENET_EIMR_TXB_SHIFT (26U) |
#define | ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
#define | ENET_EIMR_TXF_MASK (0x8000000U) |
#define | ENET_EIMR_TXF_SHIFT (27U) |
#define | ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
#define | ENET_EIMR_GRA_MASK (0x10000000U) |
#define | ENET_EIMR_GRA_SHIFT (28U) |
#define | ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
#define | ENET_EIMR_BABT_MASK (0x20000000U) |
#define | ENET_EIMR_BABT_SHIFT (29U) |
#define | ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
#define | ENET_EIMR_BABR_MASK (0x40000000U) |
#define | ENET_EIMR_BABR_SHIFT (30U) |
#define | ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
#define | ENET_EIMR_TS_TIMER_MASK (0x8000U) |
#define | ENET_EIMR_TS_TIMER_SHIFT (15U) |
#define | ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) |
#define | ENET_EIMR_TS_AVAIL_MASK (0x10000U) |
#define | ENET_EIMR_TS_AVAIL_SHIFT (16U) |
#define | ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) |
#define | ENET_EIMR_WAKEUP_MASK (0x20000U) |
#define | ENET_EIMR_WAKEUP_SHIFT (17U) |
#define | ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) |
#define | ENET_EIMR_PLR_MASK (0x40000U) |
#define | ENET_EIMR_PLR_SHIFT (18U) |
#define | ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) |
#define | ENET_EIMR_UN_MASK (0x80000U) |
#define | ENET_EIMR_UN_SHIFT (19U) |
#define | ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) |
#define | ENET_EIMR_RL_MASK (0x100000U) |
#define | ENET_EIMR_RL_SHIFT (20U) |
#define | ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) |
#define | ENET_EIMR_LC_MASK (0x200000U) |
#define | ENET_EIMR_LC_SHIFT (21U) |
#define | ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) |
#define | ENET_EIMR_EBERR_MASK (0x400000U) |
#define | ENET_EIMR_EBERR_SHIFT (22U) |
#define | ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) |
#define | ENET_EIMR_MII_MASK (0x800000U) |
#define | ENET_EIMR_MII_SHIFT (23U) |
#define | ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) |
#define | ENET_EIMR_RXB_MASK (0x1000000U) |
#define | ENET_EIMR_RXB_SHIFT (24U) |
#define | ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) |
#define | ENET_EIMR_RXF_MASK (0x2000000U) |
#define | ENET_EIMR_RXF_SHIFT (25U) |
#define | ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) |
#define | ENET_EIMR_TXB_MASK (0x4000000U) |
#define | ENET_EIMR_TXB_SHIFT (26U) |
#define | ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
#define | ENET_EIMR_TXF_MASK (0x8000000U) |
#define | ENET_EIMR_TXF_SHIFT (27U) |
#define | ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
#define | ENET_EIMR_GRA_MASK (0x10000000U) |
#define | ENET_EIMR_GRA_SHIFT (28U) |
#define | ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
#define | ENET_EIMR_BABT_MASK (0x20000000U) |
#define | ENET_EIMR_BABT_SHIFT (29U) |
#define | ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
#define | ENET_EIMR_BABR_MASK (0x40000000U) |
#define | ENET_EIMR_BABR_SHIFT (30U) |
#define | ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
#define | ENET_EIMR_TS_TIMER_MASK (0x8000U) |
#define | ENET_EIMR_TS_TIMER_SHIFT (15U) |
#define | ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) |
#define | ENET_EIMR_TS_AVAIL_MASK (0x10000U) |
#define | ENET_EIMR_TS_AVAIL_SHIFT (16U) |
#define | ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) |
#define | ENET_EIMR_WAKEUP_MASK (0x20000U) |
#define | ENET_EIMR_WAKEUP_SHIFT (17U) |
#define | ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) |
#define | ENET_EIMR_PLR_MASK (0x40000U) |
#define | ENET_EIMR_PLR_SHIFT (18U) |
#define | ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) |
#define | ENET_EIMR_UN_MASK (0x80000U) |
#define | ENET_EIMR_UN_SHIFT (19U) |
#define | ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) |
#define | ENET_EIMR_RL_MASK (0x100000U) |
#define | ENET_EIMR_RL_SHIFT (20U) |
#define | ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) |
#define | ENET_EIMR_LC_MASK (0x200000U) |
#define | ENET_EIMR_LC_SHIFT (21U) |
#define | ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) |
#define | ENET_EIMR_EBERR_MASK (0x400000U) |
#define | ENET_EIMR_EBERR_SHIFT (22U) |
#define | ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) |
#define | ENET_EIMR_MII_MASK (0x800000U) |
#define | ENET_EIMR_MII_SHIFT (23U) |
#define | ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) |
#define | ENET_EIMR_RXB_MASK (0x1000000U) |
#define | ENET_EIMR_RXB_SHIFT (24U) |
#define | ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) |
#define | ENET_EIMR_RXF_MASK (0x2000000U) |
#define | ENET_EIMR_RXF_SHIFT (25U) |
#define | ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) |
#define | ENET_EIMR_TXB_MASK (0x4000000U) |
#define | ENET_EIMR_TXB_SHIFT (26U) |
#define | ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
#define | ENET_EIMR_TXF_MASK (0x8000000U) |
#define | ENET_EIMR_TXF_SHIFT (27U) |
#define | ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
#define | ENET_EIMR_GRA_MASK (0x10000000U) |
#define | ENET_EIMR_GRA_SHIFT (28U) |
#define | ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
#define | ENET_EIMR_BABT_MASK (0x20000000U) |
#define | ENET_EIMR_BABT_SHIFT (29U) |
#define | ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
#define | ENET_EIMR_BABR_MASK (0x40000000U) |
#define | ENET_EIMR_BABR_SHIFT (30U) |
#define | ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
ECR - Ethernet Control Register | |
#define | ENET_ECR_RESET_MASK (0x1U) |
#define | ENET_ECR_RESET_SHIFT (0U) |
#define | ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) |
#define | ENET_ECR_ETHEREN_MASK (0x2U) |
#define | ENET_ECR_ETHEREN_SHIFT (1U) |
#define | ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
#define | ENET_ECR_MAGICEN_MASK (0x4U) |
#define | ENET_ECR_MAGICEN_SHIFT (2U) |
#define | ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
#define | ENET_ECR_SLEEP_MASK (0x8U) |
#define | ENET_ECR_SLEEP_SHIFT (3U) |
#define | ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
#define | ENET_ECR_EN1588_MASK (0x10U) |
#define | ENET_ECR_EN1588_SHIFT (4U) |
#define | ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
#define | ENET_ECR_DBGEN_MASK (0x40U) |
#define | ENET_ECR_DBGEN_SHIFT (6U) |
#define | ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
#define | ENET_ECR_STOPEN_MASK (0x80U) |
#define | ENET_ECR_STOPEN_SHIFT (7U) |
#define | ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK) |
#define | ENET_ECR_DBSWP_MASK (0x100U) |
#define | ENET_ECR_DBSWP_SHIFT (8U) |
#define | ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
#define | ENET_ECR_RESET_MASK 0x1u |
#define | ENET_ECR_RESET_SHIFT 0 |
#define | ENET_ECR_ETHEREN_MASK 0x2u |
#define | ENET_ECR_ETHEREN_SHIFT 1 |
#define | ENET_ECR_MAGICEN_MASK 0x4u |
#define | ENET_ECR_MAGICEN_SHIFT 2 |
#define | ENET_ECR_SLEEP_MASK 0x8u |
#define | ENET_ECR_SLEEP_SHIFT 3 |
#define | ENET_ECR_EN1588_MASK 0x10u |
#define | ENET_ECR_EN1588_SHIFT 4 |
#define | ENET_ECR_DBGEN_MASK 0x40u |
#define | ENET_ECR_DBGEN_SHIFT 6 |
#define | ENET_ECR_STOPEN_MASK 0x80u |
#define | ENET_ECR_STOPEN_SHIFT 7 |
#define | ENET_ECR_RESET_MASK (0x1U) |
#define | ENET_ECR_RESET_SHIFT (0U) |
#define | ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) |
#define | ENET_ECR_ETHEREN_MASK (0x2U) |
#define | ENET_ECR_ETHEREN_SHIFT (1U) |
#define | ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
#define | ENET_ECR_MAGICEN_MASK (0x4U) |
#define | ENET_ECR_MAGICEN_SHIFT (2U) |
#define | ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
#define | ENET_ECR_SLEEP_MASK (0x8U) |
#define | ENET_ECR_SLEEP_SHIFT (3U) |
#define | ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
#define | ENET_ECR_EN1588_MASK (0x10U) |
#define | ENET_ECR_EN1588_SHIFT (4U) |
#define | ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
#define | ENET_ECR_DBGEN_MASK (0x40U) |
#define | ENET_ECR_DBGEN_SHIFT (6U) |
#define | ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
#define | ENET_ECR_STOPEN_MASK (0x80U) |
#define | ENET_ECR_STOPEN_SHIFT (7U) |
#define | ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK) |
#define | ENET_ECR_DBSWP_MASK (0x100U) |
#define | ENET_ECR_DBSWP_SHIFT (8U) |
#define | ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
#define | ENET_ECR_RESET_MASK (0x1U) |
#define | ENET_ECR_RESET_SHIFT (0U) |
#define | ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) |
#define | ENET_ECR_ETHEREN_MASK (0x2U) |
#define | ENET_ECR_ETHEREN_SHIFT (1U) |
#define | ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
#define | ENET_ECR_MAGICEN_MASK (0x4U) |
#define | ENET_ECR_MAGICEN_SHIFT (2U) |
#define | ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
#define | ENET_ECR_SLEEP_MASK (0x8U) |
#define | ENET_ECR_SLEEP_SHIFT (3U) |
#define | ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
#define | ENET_ECR_EN1588_MASK (0x10U) |
#define | ENET_ECR_EN1588_SHIFT (4U) |
#define | ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
#define | ENET_ECR_DBGEN_MASK (0x40U) |
#define | ENET_ECR_DBGEN_SHIFT (6U) |
#define | ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
#define | ENET_ECR_STOPEN_MASK (0x80U) |
#define | ENET_ECR_STOPEN_SHIFT (7U) |
#define | ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK) |
#define | ENET_ECR_DBSWP_MASK (0x100U) |
#define | ENET_ECR_DBSWP_SHIFT (8U) |
#define | ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
#define | ENET_ECR_RESET_MASK (0x1U) |
#define | ENET_ECR_RESET_SHIFT (0U) |
#define | ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) |
#define | ENET_ECR_ETHEREN_MASK (0x2U) |
#define | ENET_ECR_ETHEREN_SHIFT (1U) |
#define | ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
#define | ENET_ECR_MAGICEN_MASK (0x4U) |
#define | ENET_ECR_MAGICEN_SHIFT (2U) |
#define | ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
#define | ENET_ECR_SLEEP_MASK (0x8U) |
#define | ENET_ECR_SLEEP_SHIFT (3U) |
#define | ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
#define | ENET_ECR_EN1588_MASK (0x10U) |
#define | ENET_ECR_EN1588_SHIFT (4U) |
#define | ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
#define | ENET_ECR_DBGEN_MASK (0x40U) |
#define | ENET_ECR_DBGEN_SHIFT (6U) |
#define | ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
#define | ENET_ECR_STOPEN_MASK (0x80U) |
#define | ENET_ECR_STOPEN_SHIFT (7U) |
#define | ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK) |
#define | ENET_ECR_DBSWP_MASK (0x100U) |
#define | ENET_ECR_DBSWP_SHIFT (8U) |
#define | ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
#define | ENET_ECR_RESET_MASK (0x1U) |
#define | ENET_ECR_RESET_SHIFT (0U) |
#define | ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) |
#define | ENET_ECR_ETHEREN_MASK (0x2U) |
#define | ENET_ECR_ETHEREN_SHIFT (1U) |
#define | ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
#define | ENET_ECR_MAGICEN_MASK (0x4U) |
#define | ENET_ECR_MAGICEN_SHIFT (2U) |
#define | ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
#define | ENET_ECR_SLEEP_MASK (0x8U) |
#define | ENET_ECR_SLEEP_SHIFT (3U) |
#define | ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
#define | ENET_ECR_EN1588_MASK (0x10U) |
#define | ENET_ECR_EN1588_SHIFT (4U) |
#define | ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
#define | ENET_ECR_DBGEN_MASK (0x40U) |
#define | ENET_ECR_DBGEN_SHIFT (6U) |
#define | ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
#define | ENET_ECR_STOPEN_MASK (0x80U) |
#define | ENET_ECR_STOPEN_SHIFT (7U) |
#define | ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK) |
#define | ENET_ECR_DBSWP_MASK (0x100U) |
#define | ENET_ECR_DBSWP_SHIFT (8U) |
#define | ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
MMFR - MII Management Frame Register | |
#define | ENET_MMFR_DATA_MASK (0xFFFFU) |
#define | ENET_MMFR_DATA_SHIFT (0U) |
#define | ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) |
#define | ENET_MMFR_TA_MASK (0x30000U) |
#define | ENET_MMFR_TA_SHIFT (16U) |
#define | ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) |
#define | ENET_MMFR_RA_MASK (0x7C0000U) |
#define | ENET_MMFR_RA_SHIFT (18U) |
#define | ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) |
#define | ENET_MMFR_PA_MASK (0xF800000U) |
#define | ENET_MMFR_PA_SHIFT (23U) |
#define | ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) |
#define | ENET_MMFR_OP_MASK (0x30000000U) |
#define | ENET_MMFR_OP_SHIFT (28U) |
#define | ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) |
#define | ENET_MMFR_ST_MASK (0xC0000000U) |
#define | ENET_MMFR_ST_SHIFT (30U) |
#define | ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) |
#define | ENET_MMFR_DATA_MASK 0xFFFFu |
#define | ENET_MMFR_DATA_SHIFT 0 |
#define | ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK) |
#define | ENET_MMFR_TA_MASK 0x30000u |
#define | ENET_MMFR_TA_SHIFT 16 |
#define | ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK) |
#define | ENET_MMFR_RA_MASK 0x7C0000u |
#define | ENET_MMFR_RA_SHIFT 18 |
#define | ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK) |
#define | ENET_MMFR_PA_MASK 0xF800000u |
#define | ENET_MMFR_PA_SHIFT 23 |
#define | ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK) |
#define | ENET_MMFR_OP_MASK 0x30000000u |
#define | ENET_MMFR_OP_SHIFT 28 |
#define | ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK) |
#define | ENET_MMFR_ST_MASK 0xC0000000u |
#define | ENET_MMFR_ST_SHIFT 30 |
#define | ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK) |
#define | ENET_MMFR_DATA_MASK (0xFFFFU) |
#define | ENET_MMFR_DATA_SHIFT (0U) |
#define | ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) |
#define | ENET_MMFR_TA_MASK (0x30000U) |
#define | ENET_MMFR_TA_SHIFT (16U) |
#define | ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) |
#define | ENET_MMFR_RA_MASK (0x7C0000U) |
#define | ENET_MMFR_RA_SHIFT (18U) |
#define | ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) |
#define | ENET_MMFR_PA_MASK (0xF800000U) |
#define | ENET_MMFR_PA_SHIFT (23U) |
#define | ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) |
#define | ENET_MMFR_OP_MASK (0x30000000U) |
#define | ENET_MMFR_OP_SHIFT (28U) |
#define | ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) |
#define | ENET_MMFR_ST_MASK (0xC0000000U) |
#define | ENET_MMFR_ST_SHIFT (30U) |
#define | ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) |
#define | ENET_MMFR_DATA_MASK (0xFFFFU) |
#define | ENET_MMFR_DATA_SHIFT (0U) |
#define | ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) |
#define | ENET_MMFR_TA_MASK (0x30000U) |
#define | ENET_MMFR_TA_SHIFT (16U) |
#define | ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) |
#define | ENET_MMFR_RA_MASK (0x7C0000U) |
#define | ENET_MMFR_RA_SHIFT (18U) |
#define | ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) |
#define | ENET_MMFR_PA_MASK (0xF800000U) |
#define | ENET_MMFR_PA_SHIFT (23U) |
#define | ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) |
#define | ENET_MMFR_OP_MASK (0x30000000U) |
#define | ENET_MMFR_OP_SHIFT (28U) |
#define | ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) |
#define | ENET_MMFR_ST_MASK (0xC0000000U) |
#define | ENET_MMFR_ST_SHIFT (30U) |
#define | ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) |
#define | ENET_MMFR_DATA_MASK (0xFFFFU) |
#define | ENET_MMFR_DATA_SHIFT (0U) |
#define | ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) |
#define | ENET_MMFR_TA_MASK (0x30000U) |
#define | ENET_MMFR_TA_SHIFT (16U) |
#define | ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) |
#define | ENET_MMFR_RA_MASK (0x7C0000U) |
#define | ENET_MMFR_RA_SHIFT (18U) |
#define | ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) |
#define | ENET_MMFR_PA_MASK (0xF800000U) |
#define | ENET_MMFR_PA_SHIFT (23U) |
#define | ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) |
#define | ENET_MMFR_OP_MASK (0x30000000U) |
#define | ENET_MMFR_OP_SHIFT (28U) |
#define | ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) |
#define | ENET_MMFR_ST_MASK (0xC0000000U) |
#define | ENET_MMFR_ST_SHIFT (30U) |
#define | ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) |
#define | ENET_MMFR_DATA_MASK (0xFFFFU) |
#define | ENET_MMFR_DATA_SHIFT (0U) |
#define | ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) |
#define | ENET_MMFR_TA_MASK (0x30000U) |
#define | ENET_MMFR_TA_SHIFT (16U) |
#define | ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) |
#define | ENET_MMFR_RA_MASK (0x7C0000U) |
#define | ENET_MMFR_RA_SHIFT (18U) |
#define | ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) |
#define | ENET_MMFR_PA_MASK (0xF800000U) |
#define | ENET_MMFR_PA_SHIFT (23U) |
#define | ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) |
#define | ENET_MMFR_OP_MASK (0x30000000U) |
#define | ENET_MMFR_OP_SHIFT (28U) |
#define | ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) |
#define | ENET_MMFR_ST_MASK (0xC0000000U) |
#define | ENET_MMFR_ST_SHIFT (30U) |
#define | ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) |
MSCR - MII Speed Control Register | |
#define | ENET_MSCR_MII_SPEED_MASK (0x7EU) |
#define | ENET_MSCR_MII_SPEED_SHIFT (1U) |
#define | ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) |
#define | ENET_MSCR_DIS_PRE_MASK (0x80U) |
#define | ENET_MSCR_DIS_PRE_SHIFT (7U) |
#define | ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
#define | ENET_MSCR_HOLDTIME_MASK (0x700U) |
#define | ENET_MSCR_HOLDTIME_SHIFT (8U) |
#define | ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
#define | ENET_MSCR_MII_SPEED_MASK 0x7Eu |
#define | ENET_MSCR_MII_SPEED_SHIFT 1 |
#define | ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK) |
#define | ENET_MSCR_DIS_PRE_MASK 0x80u |
#define | ENET_MSCR_DIS_PRE_SHIFT 7 |
#define | ENET_MSCR_HOLDTIME_MASK 0x700u |
#define | ENET_MSCR_HOLDTIME_SHIFT 8 |
#define | ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK) |
#define | ENET_MSCR_MII_SPEED_MASK (0x7EU) |
#define | ENET_MSCR_MII_SPEED_SHIFT (1U) |
#define | ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) |
#define | ENET_MSCR_DIS_PRE_MASK (0x80U) |
#define | ENET_MSCR_DIS_PRE_SHIFT (7U) |
#define | ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
#define | ENET_MSCR_HOLDTIME_MASK (0x700U) |
#define | ENET_MSCR_HOLDTIME_SHIFT (8U) |
#define | ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
#define | ENET_MSCR_MII_SPEED_MASK (0x7EU) |
#define | ENET_MSCR_MII_SPEED_SHIFT (1U) |
#define | ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) |
#define | ENET_MSCR_DIS_PRE_MASK (0x80U) |
#define | ENET_MSCR_DIS_PRE_SHIFT (7U) |
#define | ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
#define | ENET_MSCR_HOLDTIME_MASK (0x700U) |
#define | ENET_MSCR_HOLDTIME_SHIFT (8U) |
#define | ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
#define | ENET_MSCR_MII_SPEED_MASK (0x7EU) |
#define | ENET_MSCR_MII_SPEED_SHIFT (1U) |
#define | ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) |
#define | ENET_MSCR_DIS_PRE_MASK (0x80U) |
#define | ENET_MSCR_DIS_PRE_SHIFT (7U) |
#define | ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
#define | ENET_MSCR_HOLDTIME_MASK (0x700U) |
#define | ENET_MSCR_HOLDTIME_SHIFT (8U) |
#define | ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
#define | ENET_MSCR_MII_SPEED_MASK (0x7EU) |
#define | ENET_MSCR_MII_SPEED_SHIFT (1U) |
#define | ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) |
#define | ENET_MSCR_DIS_PRE_MASK (0x80U) |
#define | ENET_MSCR_DIS_PRE_SHIFT (7U) |
#define | ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
#define | ENET_MSCR_HOLDTIME_MASK (0x700U) |
#define | ENET_MSCR_HOLDTIME_SHIFT (8U) |
#define | ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
MIBC - MIB Control Register | |
#define | ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) |
#define | ENET_MIBC_MIB_CLEAR_SHIFT (29U) |
#define | ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
#define | ENET_MIBC_MIB_IDLE_MASK (0x40000000U) |
#define | ENET_MIBC_MIB_IDLE_SHIFT (30U) |
#define | ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
#define | ENET_MIBC_MIB_DIS_MASK (0x80000000U) |
#define | ENET_MIBC_MIB_DIS_SHIFT (31U) |
#define | ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
#define | ENET_MIBC_MIB_CLEAR_MASK 0x20000000u |
#define | ENET_MIBC_MIB_CLEAR_SHIFT 29 |
#define | ENET_MIBC_MIB_IDLE_MASK 0x40000000u |
#define | ENET_MIBC_MIB_IDLE_SHIFT 30 |
#define | ENET_MIBC_MIB_DIS_MASK 0x80000000u |
#define | ENET_MIBC_MIB_DIS_SHIFT 31 |
#define | ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) |
#define | ENET_MIBC_MIB_CLEAR_SHIFT (29U) |
#define | ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
#define | ENET_MIBC_MIB_IDLE_MASK (0x40000000U) |
#define | ENET_MIBC_MIB_IDLE_SHIFT (30U) |
#define | ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
#define | ENET_MIBC_MIB_DIS_MASK (0x80000000U) |
#define | ENET_MIBC_MIB_DIS_SHIFT (31U) |
#define | ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
#define | ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) |
#define | ENET_MIBC_MIB_CLEAR_SHIFT (29U) |
#define | ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
#define | ENET_MIBC_MIB_IDLE_MASK (0x40000000U) |
#define | ENET_MIBC_MIB_IDLE_SHIFT (30U) |
#define | ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
#define | ENET_MIBC_MIB_DIS_MASK (0x80000000U) |
#define | ENET_MIBC_MIB_DIS_SHIFT (31U) |
#define | ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
#define | ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) |
#define | ENET_MIBC_MIB_CLEAR_SHIFT (29U) |
#define | ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
#define | ENET_MIBC_MIB_IDLE_MASK (0x40000000U) |
#define | ENET_MIBC_MIB_IDLE_SHIFT (30U) |
#define | ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
#define | ENET_MIBC_MIB_DIS_MASK (0x80000000U) |
#define | ENET_MIBC_MIB_DIS_SHIFT (31U) |
#define | ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
#define | ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) |
#define | ENET_MIBC_MIB_CLEAR_SHIFT (29U) |
#define | ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
#define | ENET_MIBC_MIB_IDLE_MASK (0x40000000U) |
#define | ENET_MIBC_MIB_IDLE_SHIFT (30U) |
#define | ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
#define | ENET_MIBC_MIB_DIS_MASK (0x80000000U) |
#define | ENET_MIBC_MIB_DIS_SHIFT (31U) |
#define | ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
RCR - Receive Control Register | |
#define | ENET_RCR_LOOP_MASK (0x1U) |
#define | ENET_RCR_LOOP_SHIFT (0U) |
#define | ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
#define | ENET_RCR_DRT_MASK (0x2U) |
#define | ENET_RCR_DRT_SHIFT (1U) |
#define | ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
#define | ENET_RCR_MII_MODE_MASK (0x4U) |
#define | ENET_RCR_MII_MODE_SHIFT (2U) |
#define | ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
#define | ENET_RCR_PROM_MASK (0x8U) |
#define | ENET_RCR_PROM_SHIFT (3U) |
#define | ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
#define | ENET_RCR_BC_REJ_MASK (0x10U) |
#define | ENET_RCR_BC_REJ_SHIFT (4U) |
#define | ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) |
#define | ENET_RCR_FCE_MASK (0x20U) |
#define | ENET_RCR_FCE_SHIFT (5U) |
#define | ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) |
#define | ENET_RCR_RMII_MODE_MASK (0x100U) |
#define | ENET_RCR_RMII_MODE_SHIFT (8U) |
#define | ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
#define | ENET_RCR_RMII_10T_MASK (0x200U) |
#define | ENET_RCR_RMII_10T_SHIFT (9U) |
#define | ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
#define | ENET_RCR_PADEN_MASK (0x1000U) |
#define | ENET_RCR_PADEN_SHIFT (12U) |
#define | ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
#define | ENET_RCR_PAUFWD_MASK (0x2000U) |
#define | ENET_RCR_PAUFWD_SHIFT (13U) |
#define | ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
#define | ENET_RCR_CRCFWD_MASK (0x4000U) |
#define | ENET_RCR_CRCFWD_SHIFT (14U) |
#define | ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
#define | ENET_RCR_CFEN_MASK (0x8000U) |
#define | ENET_RCR_CFEN_SHIFT (15U) |
#define | ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
#define | ENET_RCR_MAX_FL_MASK (0x3FFF0000U) |
#define | ENET_RCR_MAX_FL_SHIFT (16U) |
#define | ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) |
#define | ENET_RCR_NLC_MASK (0x40000000U) |
#define | ENET_RCR_NLC_SHIFT (30U) |
#define | ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
#define | ENET_RCR_GRS_MASK (0x80000000U) |
#define | ENET_RCR_GRS_SHIFT (31U) |
#define | ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) |
#define | ENET_RCR_LOOP_MASK 0x1u |
#define | ENET_RCR_LOOP_SHIFT 0 |
#define | ENET_RCR_DRT_MASK 0x2u |
#define | ENET_RCR_DRT_SHIFT 1 |
#define | ENET_RCR_MII_MODE_MASK 0x4u |
#define | ENET_RCR_MII_MODE_SHIFT 2 |
#define | ENET_RCR_PROM_MASK 0x8u |
#define | ENET_RCR_PROM_SHIFT 3 |
#define | ENET_RCR_BC_REJ_MASK 0x10u |
#define | ENET_RCR_BC_REJ_SHIFT 4 |
#define | ENET_RCR_FCE_MASK 0x20u |
#define | ENET_RCR_FCE_SHIFT 5 |
#define | ENET_RCR_RMII_MODE_MASK 0x100u |
#define | ENET_RCR_RMII_MODE_SHIFT 8 |
#define | ENET_RCR_RMII_10T_MASK 0x200u |
#define | ENET_RCR_RMII_10T_SHIFT 9 |
#define | ENET_RCR_PADEN_MASK 0x1000u |
#define | ENET_RCR_PADEN_SHIFT 12 |
#define | ENET_RCR_PAUFWD_MASK 0x2000u |
#define | ENET_RCR_PAUFWD_SHIFT 13 |
#define | ENET_RCR_CRCFWD_MASK 0x4000u |
#define | ENET_RCR_CRCFWD_SHIFT 14 |
#define | ENET_RCR_CFEN_MASK 0x8000u |
#define | ENET_RCR_CFEN_SHIFT 15 |
#define | ENET_RCR_MAX_FL_MASK 0x3FFF0000u |
#define | ENET_RCR_MAX_FL_SHIFT 16 |
#define | ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK) |
#define | ENET_RCR_NLC_MASK 0x40000000u |
#define | ENET_RCR_NLC_SHIFT 30 |
#define | ENET_RCR_GRS_MASK 0x80000000u |
#define | ENET_RCR_GRS_SHIFT 31 |
#define | ENET_RCR_LOOP_MASK (0x1U) |
#define | ENET_RCR_LOOP_SHIFT (0U) |
#define | ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
#define | ENET_RCR_DRT_MASK (0x2U) |
#define | ENET_RCR_DRT_SHIFT (1U) |
#define | ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
#define | ENET_RCR_MII_MODE_MASK (0x4U) |
#define | ENET_RCR_MII_MODE_SHIFT (2U) |
#define | ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
#define | ENET_RCR_PROM_MASK (0x8U) |
#define | ENET_RCR_PROM_SHIFT (3U) |
#define | ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
#define | ENET_RCR_BC_REJ_MASK (0x10U) |
#define | ENET_RCR_BC_REJ_SHIFT (4U) |
#define | ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) |
#define | ENET_RCR_FCE_MASK (0x20U) |
#define | ENET_RCR_FCE_SHIFT (5U) |
#define | ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) |
#define | ENET_RCR_RMII_MODE_MASK (0x100U) |
#define | ENET_RCR_RMII_MODE_SHIFT (8U) |
#define | ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
#define | ENET_RCR_RMII_10T_MASK (0x200U) |
#define | ENET_RCR_RMII_10T_SHIFT (9U) |
#define | ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
#define | ENET_RCR_PADEN_MASK (0x1000U) |
#define | ENET_RCR_PADEN_SHIFT (12U) |
#define | ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
#define | ENET_RCR_PAUFWD_MASK (0x2000U) |
#define | ENET_RCR_PAUFWD_SHIFT (13U) |
#define | ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
#define | ENET_RCR_CRCFWD_MASK (0x4000U) |
#define | ENET_RCR_CRCFWD_SHIFT (14U) |
#define | ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
#define | ENET_RCR_CFEN_MASK (0x8000U) |
#define | ENET_RCR_CFEN_SHIFT (15U) |
#define | ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
#define | ENET_RCR_MAX_FL_MASK (0x3FFF0000U) |
#define | ENET_RCR_MAX_FL_SHIFT (16U) |
#define | ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) |
#define | ENET_RCR_NLC_MASK (0x40000000U) |
#define | ENET_RCR_NLC_SHIFT (30U) |
#define | ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
#define | ENET_RCR_GRS_MASK (0x80000000U) |
#define | ENET_RCR_GRS_SHIFT (31U) |
#define | ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) |
#define | ENET_RCR_LOOP_MASK (0x1U) |
#define | ENET_RCR_LOOP_SHIFT (0U) |
#define | ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
#define | ENET_RCR_DRT_MASK (0x2U) |
#define | ENET_RCR_DRT_SHIFT (1U) |
#define | ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
#define | ENET_RCR_MII_MODE_MASK (0x4U) |
#define | ENET_RCR_MII_MODE_SHIFT (2U) |
#define | ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
#define | ENET_RCR_PROM_MASK (0x8U) |
#define | ENET_RCR_PROM_SHIFT (3U) |
#define | ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
#define | ENET_RCR_BC_REJ_MASK (0x10U) |
#define | ENET_RCR_BC_REJ_SHIFT (4U) |
#define | ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) |
#define | ENET_RCR_FCE_MASK (0x20U) |
#define | ENET_RCR_FCE_SHIFT (5U) |
#define | ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) |
#define | ENET_RCR_RMII_MODE_MASK (0x100U) |
#define | ENET_RCR_RMII_MODE_SHIFT (8U) |
#define | ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
#define | ENET_RCR_RMII_10T_MASK (0x200U) |
#define | ENET_RCR_RMII_10T_SHIFT (9U) |
#define | ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
#define | ENET_RCR_PADEN_MASK (0x1000U) |
#define | ENET_RCR_PADEN_SHIFT (12U) |
#define | ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
#define | ENET_RCR_PAUFWD_MASK (0x2000U) |
#define | ENET_RCR_PAUFWD_SHIFT (13U) |
#define | ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
#define | ENET_RCR_CRCFWD_MASK (0x4000U) |
#define | ENET_RCR_CRCFWD_SHIFT (14U) |
#define | ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
#define | ENET_RCR_CFEN_MASK (0x8000U) |
#define | ENET_RCR_CFEN_SHIFT (15U) |
#define | ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
#define | ENET_RCR_MAX_FL_MASK (0x3FFF0000U) |
#define | ENET_RCR_MAX_FL_SHIFT (16U) |
#define | ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) |
#define | ENET_RCR_NLC_MASK (0x40000000U) |
#define | ENET_RCR_NLC_SHIFT (30U) |
#define | ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
#define | ENET_RCR_GRS_MASK (0x80000000U) |
#define | ENET_RCR_GRS_SHIFT (31U) |
#define | ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) |
#define | ENET_RCR_LOOP_MASK (0x1U) |
#define | ENET_RCR_LOOP_SHIFT (0U) |
#define | ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
#define | ENET_RCR_DRT_MASK (0x2U) |
#define | ENET_RCR_DRT_SHIFT (1U) |
#define | ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
#define | ENET_RCR_MII_MODE_MASK (0x4U) |
#define | ENET_RCR_MII_MODE_SHIFT (2U) |
#define | ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
#define | ENET_RCR_PROM_MASK (0x8U) |
#define | ENET_RCR_PROM_SHIFT (3U) |
#define | ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
#define | ENET_RCR_BC_REJ_MASK (0x10U) |
#define | ENET_RCR_BC_REJ_SHIFT (4U) |
#define | ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) |
#define | ENET_RCR_FCE_MASK (0x20U) |
#define | ENET_RCR_FCE_SHIFT (5U) |
#define | ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) |
#define | ENET_RCR_RMII_MODE_MASK (0x100U) |
#define | ENET_RCR_RMII_MODE_SHIFT (8U) |
#define | ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
#define | ENET_RCR_RMII_10T_MASK (0x200U) |
#define | ENET_RCR_RMII_10T_SHIFT (9U) |
#define | ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
#define | ENET_RCR_PADEN_MASK (0x1000U) |
#define | ENET_RCR_PADEN_SHIFT (12U) |
#define | ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
#define | ENET_RCR_PAUFWD_MASK (0x2000U) |
#define | ENET_RCR_PAUFWD_SHIFT (13U) |
#define | ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
#define | ENET_RCR_CRCFWD_MASK (0x4000U) |
#define | ENET_RCR_CRCFWD_SHIFT (14U) |
#define | ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
#define | ENET_RCR_CFEN_MASK (0x8000U) |
#define | ENET_RCR_CFEN_SHIFT (15U) |
#define | ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
#define | ENET_RCR_MAX_FL_MASK (0x3FFF0000U) |
#define | ENET_RCR_MAX_FL_SHIFT (16U) |
#define | ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) |
#define | ENET_RCR_NLC_MASK (0x40000000U) |
#define | ENET_RCR_NLC_SHIFT (30U) |
#define | ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
#define | ENET_RCR_GRS_MASK (0x80000000U) |
#define | ENET_RCR_GRS_SHIFT (31U) |
#define | ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) |
#define | ENET_RCR_LOOP_MASK (0x1U) |
#define | ENET_RCR_LOOP_SHIFT (0U) |
#define | ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
#define | ENET_RCR_DRT_MASK (0x2U) |
#define | ENET_RCR_DRT_SHIFT (1U) |
#define | ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
#define | ENET_RCR_MII_MODE_MASK (0x4U) |
#define | ENET_RCR_MII_MODE_SHIFT (2U) |
#define | ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
#define | ENET_RCR_PROM_MASK (0x8U) |
#define | ENET_RCR_PROM_SHIFT (3U) |
#define | ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
#define | ENET_RCR_BC_REJ_MASK (0x10U) |
#define | ENET_RCR_BC_REJ_SHIFT (4U) |
#define | ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) |
#define | ENET_RCR_FCE_MASK (0x20U) |
#define | ENET_RCR_FCE_SHIFT (5U) |
#define | ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) |
#define | ENET_RCR_RMII_MODE_MASK (0x100U) |
#define | ENET_RCR_RMII_MODE_SHIFT (8U) |
#define | ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
#define | ENET_RCR_RMII_10T_MASK (0x200U) |
#define | ENET_RCR_RMII_10T_SHIFT (9U) |
#define | ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
#define | ENET_RCR_PADEN_MASK (0x1000U) |
#define | ENET_RCR_PADEN_SHIFT (12U) |
#define | ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
#define | ENET_RCR_PAUFWD_MASK (0x2000U) |
#define | ENET_RCR_PAUFWD_SHIFT (13U) |
#define | ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
#define | ENET_RCR_CRCFWD_MASK (0x4000U) |
#define | ENET_RCR_CRCFWD_SHIFT (14U) |
#define | ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
#define | ENET_RCR_CFEN_MASK (0x8000U) |
#define | ENET_RCR_CFEN_SHIFT (15U) |
#define | ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
#define | ENET_RCR_MAX_FL_MASK (0x3FFF0000U) |
#define | ENET_RCR_MAX_FL_SHIFT (16U) |
#define | ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) |
#define | ENET_RCR_NLC_MASK (0x40000000U) |
#define | ENET_RCR_NLC_SHIFT (30U) |
#define | ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
#define | ENET_RCR_GRS_MASK (0x80000000U) |
#define | ENET_RCR_GRS_SHIFT (31U) |
#define | ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) |
TCR - Transmit Control Register | |
#define | ENET_TCR_GTS_MASK (0x1U) |
#define | ENET_TCR_GTS_SHIFT (0U) |
#define | ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) |
#define | ENET_TCR_FDEN_MASK (0x4U) |
#define | ENET_TCR_FDEN_SHIFT (2U) |
#define | ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) |
#define | ENET_TCR_TFC_PAUSE_MASK (0x8U) |
#define | ENET_TCR_TFC_PAUSE_SHIFT (3U) |
#define | ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
#define | ENET_TCR_RFC_PAUSE_MASK (0x10U) |
#define | ENET_TCR_RFC_PAUSE_SHIFT (4U) |
#define | ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) |
#define | ENET_TCR_ADDSEL_MASK (0xE0U) |
#define | ENET_TCR_ADDSEL_SHIFT (5U) |
#define | ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
#define | ENET_TCR_ADDINS_MASK (0x100U) |
#define | ENET_TCR_ADDINS_SHIFT (8U) |
#define | ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
#define | ENET_TCR_CRCFWD_MASK (0x200U) |
#define | ENET_TCR_CRCFWD_SHIFT (9U) |
#define | ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
#define | ENET_TCR_GTS_MASK 0x1u |
#define | ENET_TCR_GTS_SHIFT 0 |
#define | ENET_TCR_FDEN_MASK 0x4u |
#define | ENET_TCR_FDEN_SHIFT 2 |
#define | ENET_TCR_TFC_PAUSE_MASK 0x8u |
#define | ENET_TCR_TFC_PAUSE_SHIFT 3 |
#define | ENET_TCR_RFC_PAUSE_MASK 0x10u |
#define | ENET_TCR_RFC_PAUSE_SHIFT 4 |
#define | ENET_TCR_ADDSEL_MASK 0xE0u |
#define | ENET_TCR_ADDSEL_SHIFT 5 |
#define | ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK) |
#define | ENET_TCR_ADDINS_MASK 0x100u |
#define | ENET_TCR_ADDINS_SHIFT 8 |
#define | ENET_TCR_CRCFWD_MASK 0x200u |
#define | ENET_TCR_CRCFWD_SHIFT 9 |
#define | ENET_TCR_GTS_MASK (0x1U) |
#define | ENET_TCR_GTS_SHIFT (0U) |
#define | ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) |
#define | ENET_TCR_FDEN_MASK (0x4U) |
#define | ENET_TCR_FDEN_SHIFT (2U) |
#define | ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) |
#define | ENET_TCR_TFC_PAUSE_MASK (0x8U) |
#define | ENET_TCR_TFC_PAUSE_SHIFT (3U) |
#define | ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
#define | ENET_TCR_RFC_PAUSE_MASK (0x10U) |
#define | ENET_TCR_RFC_PAUSE_SHIFT (4U) |
#define | ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) |
#define | ENET_TCR_ADDSEL_MASK (0xE0U) |
#define | ENET_TCR_ADDSEL_SHIFT (5U) |
#define | ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
#define | ENET_TCR_ADDINS_MASK (0x100U) |
#define | ENET_TCR_ADDINS_SHIFT (8U) |
#define | ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
#define | ENET_TCR_CRCFWD_MASK (0x200U) |
#define | ENET_TCR_CRCFWD_SHIFT (9U) |
#define | ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
#define | ENET_TCR_GTS_MASK (0x1U) |
#define | ENET_TCR_GTS_SHIFT (0U) |
#define | ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) |
#define | ENET_TCR_FDEN_MASK (0x4U) |
#define | ENET_TCR_FDEN_SHIFT (2U) |
#define | ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) |
#define | ENET_TCR_TFC_PAUSE_MASK (0x8U) |
#define | ENET_TCR_TFC_PAUSE_SHIFT (3U) |
#define | ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
#define | ENET_TCR_RFC_PAUSE_MASK (0x10U) |
#define | ENET_TCR_RFC_PAUSE_SHIFT (4U) |
#define | ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) |
#define | ENET_TCR_ADDSEL_MASK (0xE0U) |
#define | ENET_TCR_ADDSEL_SHIFT (5U) |
#define | ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
#define | ENET_TCR_ADDINS_MASK (0x100U) |
#define | ENET_TCR_ADDINS_SHIFT (8U) |
#define | ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
#define | ENET_TCR_CRCFWD_MASK (0x200U) |
#define | ENET_TCR_CRCFWD_SHIFT (9U) |
#define | ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
#define | ENET_TCR_GTS_MASK (0x1U) |
#define | ENET_TCR_GTS_SHIFT (0U) |
#define | ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) |
#define | ENET_TCR_FDEN_MASK (0x4U) |
#define | ENET_TCR_FDEN_SHIFT (2U) |
#define | ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) |
#define | ENET_TCR_TFC_PAUSE_MASK (0x8U) |
#define | ENET_TCR_TFC_PAUSE_SHIFT (3U) |
#define | ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
#define | ENET_TCR_RFC_PAUSE_MASK (0x10U) |
#define | ENET_TCR_RFC_PAUSE_SHIFT (4U) |
#define | ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) |
#define | ENET_TCR_ADDSEL_MASK (0xE0U) |
#define | ENET_TCR_ADDSEL_SHIFT (5U) |
#define | ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
#define | ENET_TCR_ADDINS_MASK (0x100U) |
#define | ENET_TCR_ADDINS_SHIFT (8U) |
#define | ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
#define | ENET_TCR_CRCFWD_MASK (0x200U) |
#define | ENET_TCR_CRCFWD_SHIFT (9U) |
#define | ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
#define | ENET_TCR_GTS_MASK (0x1U) |
#define | ENET_TCR_GTS_SHIFT (0U) |
#define | ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) |
#define | ENET_TCR_FDEN_MASK (0x4U) |
#define | ENET_TCR_FDEN_SHIFT (2U) |
#define | ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) |
#define | ENET_TCR_TFC_PAUSE_MASK (0x8U) |
#define | ENET_TCR_TFC_PAUSE_SHIFT (3U) |
#define | ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
#define | ENET_TCR_RFC_PAUSE_MASK (0x10U) |
#define | ENET_TCR_RFC_PAUSE_SHIFT (4U) |
#define | ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) |
#define | ENET_TCR_ADDSEL_MASK (0xE0U) |
#define | ENET_TCR_ADDSEL_SHIFT (5U) |
#define | ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
#define | ENET_TCR_ADDINS_MASK (0x100U) |
#define | ENET_TCR_ADDINS_SHIFT (8U) |
#define | ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
#define | ENET_TCR_CRCFWD_MASK (0x200U) |
#define | ENET_TCR_CRCFWD_SHIFT (9U) |
#define | ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
TFWR - Transmit FIFO Watermark Register | |
#define | ENET_TFWR_TFWR_MASK (0x3FU) |
#define | ENET_TFWR_TFWR_SHIFT (0U) |
#define | ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
#define | ENET_TFWR_STRFWD_MASK (0x100U) |
#define | ENET_TFWR_STRFWD_SHIFT (8U) |
#define | ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
#define | ENET_TFWR_TFWR_MASK 0x3Fu |
#define | ENET_TFWR_TFWR_SHIFT 0 |
#define | ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK) |
#define | ENET_TFWR_STRFWD_MASK 0x100u |
#define | ENET_TFWR_STRFWD_SHIFT 8 |
#define | ENET_TFWR_TFWR_MASK (0x3FU) |
#define | ENET_TFWR_TFWR_SHIFT (0U) |
#define | ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
#define | ENET_TFWR_STRFWD_MASK (0x100U) |
#define | ENET_TFWR_STRFWD_SHIFT (8U) |
#define | ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
#define | ENET_TFWR_TFWR_MASK (0x3FU) |
#define | ENET_TFWR_TFWR_SHIFT (0U) |
#define | ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
#define | ENET_TFWR_STRFWD_MASK (0x100U) |
#define | ENET_TFWR_STRFWD_SHIFT (8U) |
#define | ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
#define | ENET_TFWR_TFWR_MASK (0x3FU) |
#define | ENET_TFWR_TFWR_SHIFT (0U) |
#define | ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
#define | ENET_TFWR_STRFWD_MASK (0x100U) |
#define | ENET_TFWR_STRFWD_SHIFT (8U) |
#define | ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
#define | ENET_TFWR_TFWR_MASK (0x3FU) |
#define | ENET_TFWR_TFWR_SHIFT (0U) |
#define | ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
#define | ENET_TFWR_STRFWD_MASK (0x100U) |
#define | ENET_TFWR_STRFWD_SHIFT (8U) |
#define | ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
TACC - Transmit Accelerator Function Configuration | |
#define | ENET_TACC_SHIFT16_MASK (0x1U) |
#define | ENET_TACC_SHIFT16_SHIFT (0U) |
#define | ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
#define | ENET_TACC_IPCHK_MASK (0x8U) |
#define | ENET_TACC_IPCHK_SHIFT (3U) |
#define | ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
#define | ENET_TACC_PROCHK_MASK (0x10U) |
#define | ENET_TACC_PROCHK_SHIFT (4U) |
#define | ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
#define | ENET_TACC_SHIFT16_MASK 0x1u |
#define | ENET_TACC_SHIFT16_SHIFT 0 |
#define | ENET_TACC_IPCHK_MASK 0x8u |
#define | ENET_TACC_IPCHK_SHIFT 3 |
#define | ENET_TACC_PROCHK_MASK 0x10u |
#define | ENET_TACC_PROCHK_SHIFT 4 |
#define | ENET_TACC_SHIFT16_MASK (0x1U) |
#define | ENET_TACC_SHIFT16_SHIFT (0U) |
#define | ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
#define | ENET_TACC_IPCHK_MASK (0x8U) |
#define | ENET_TACC_IPCHK_SHIFT (3U) |
#define | ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
#define | ENET_TACC_PROCHK_MASK (0x10U) |
#define | ENET_TACC_PROCHK_SHIFT (4U) |
#define | ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
#define | ENET_TACC_SHIFT16_MASK (0x1U) |
#define | ENET_TACC_SHIFT16_SHIFT (0U) |
#define | ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
#define | ENET_TACC_IPCHK_MASK (0x8U) |
#define | ENET_TACC_IPCHK_SHIFT (3U) |
#define | ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
#define | ENET_TACC_PROCHK_MASK (0x10U) |
#define | ENET_TACC_PROCHK_SHIFT (4U) |
#define | ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
#define | ENET_TACC_SHIFT16_MASK (0x1U) |
#define | ENET_TACC_SHIFT16_SHIFT (0U) |
#define | ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
#define | ENET_TACC_IPCHK_MASK (0x8U) |
#define | ENET_TACC_IPCHK_SHIFT (3U) |
#define | ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
#define | ENET_TACC_PROCHK_MASK (0x10U) |
#define | ENET_TACC_PROCHK_SHIFT (4U) |
#define | ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
#define | ENET_TACC_SHIFT16_MASK (0x1U) |
#define | ENET_TACC_SHIFT16_SHIFT (0U) |
#define | ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
#define | ENET_TACC_IPCHK_MASK (0x8U) |
#define | ENET_TACC_IPCHK_SHIFT (3U) |
#define | ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
#define | ENET_TACC_PROCHK_MASK (0x10U) |
#define | ENET_TACC_PROCHK_SHIFT (4U) |
#define | ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
RACC - Receive Accelerator Function Configuration | |
#define | ENET_RACC_PADREM_MASK (0x1U) |
#define | ENET_RACC_PADREM_SHIFT (0U) |
#define | ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
#define | ENET_RACC_IPDIS_MASK (0x2U) |
#define | ENET_RACC_IPDIS_SHIFT (1U) |
#define | ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
#define | ENET_RACC_PRODIS_MASK (0x4U) |
#define | ENET_RACC_PRODIS_SHIFT (2U) |
#define | ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
#define | ENET_RACC_LINEDIS_MASK (0x40U) |
#define | ENET_RACC_LINEDIS_SHIFT (6U) |
#define | ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
#define | ENET_RACC_SHIFT16_MASK (0x80U) |
#define | ENET_RACC_SHIFT16_SHIFT (7U) |
#define | ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
#define | ENET_RACC_PADREM_MASK 0x1u |
#define | ENET_RACC_PADREM_SHIFT 0 |
#define | ENET_RACC_IPDIS_MASK 0x2u |
#define | ENET_RACC_IPDIS_SHIFT 1 |
#define | ENET_RACC_PRODIS_MASK 0x4u |
#define | ENET_RACC_PRODIS_SHIFT 2 |
#define | ENET_RACC_LINEDIS_MASK 0x40u |
#define | ENET_RACC_LINEDIS_SHIFT 6 |
#define | ENET_RACC_SHIFT16_MASK 0x80u |
#define | ENET_RACC_SHIFT16_SHIFT 7 |
#define | ENET_RACC_PADREM_MASK (0x1U) |
#define | ENET_RACC_PADREM_SHIFT (0U) |
#define | ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
#define | ENET_RACC_IPDIS_MASK (0x2U) |
#define | ENET_RACC_IPDIS_SHIFT (1U) |
#define | ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
#define | ENET_RACC_PRODIS_MASK (0x4U) |
#define | ENET_RACC_PRODIS_SHIFT (2U) |
#define | ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
#define | ENET_RACC_LINEDIS_MASK (0x40U) |
#define | ENET_RACC_LINEDIS_SHIFT (6U) |
#define | ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
#define | ENET_RACC_SHIFT16_MASK (0x80U) |
#define | ENET_RACC_SHIFT16_SHIFT (7U) |
#define | ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
#define | ENET_RACC_PADREM_MASK (0x1U) |
#define | ENET_RACC_PADREM_SHIFT (0U) |
#define | ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
#define | ENET_RACC_IPDIS_MASK (0x2U) |
#define | ENET_RACC_IPDIS_SHIFT (1U) |
#define | ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
#define | ENET_RACC_PRODIS_MASK (0x4U) |
#define | ENET_RACC_PRODIS_SHIFT (2U) |
#define | ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
#define | ENET_RACC_LINEDIS_MASK (0x40U) |
#define | ENET_RACC_LINEDIS_SHIFT (6U) |
#define | ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
#define | ENET_RACC_SHIFT16_MASK (0x80U) |
#define | ENET_RACC_SHIFT16_SHIFT (7U) |
#define | ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
#define | ENET_RACC_PADREM_MASK (0x1U) |
#define | ENET_RACC_PADREM_SHIFT (0U) |
#define | ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
#define | ENET_RACC_IPDIS_MASK (0x2U) |
#define | ENET_RACC_IPDIS_SHIFT (1U) |
#define | ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
#define | ENET_RACC_PRODIS_MASK (0x4U) |
#define | ENET_RACC_PRODIS_SHIFT (2U) |
#define | ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
#define | ENET_RACC_LINEDIS_MASK (0x40U) |
#define | ENET_RACC_LINEDIS_SHIFT (6U) |
#define | ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
#define | ENET_RACC_SHIFT16_MASK (0x80U) |
#define | ENET_RACC_SHIFT16_SHIFT (7U) |
#define | ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
#define | ENET_RACC_PADREM_MASK (0x1U) |
#define | ENET_RACC_PADREM_SHIFT (0U) |
#define | ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
#define | ENET_RACC_IPDIS_MASK (0x2U) |
#define | ENET_RACC_IPDIS_SHIFT (1U) |
#define | ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
#define | ENET_RACC_PRODIS_MASK (0x4U) |
#define | ENET_RACC_PRODIS_SHIFT (2U) |
#define | ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
#define | ENET_RACC_LINEDIS_MASK (0x40U) |
#define | ENET_RACC_LINEDIS_SHIFT (6U) |
#define | ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
#define | ENET_RACC_SHIFT16_MASK (0x80U) |
#define | ENET_RACC_SHIFT16_SHIFT (7U) |
#define | ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
ATCR - Adjustable Timer Control Register | |
#define | ENET_ATCR_EN_MASK (0x1U) |
#define | ENET_ATCR_EN_SHIFT (0U) |
#define | ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
#define | ENET_ATCR_OFFEN_MASK (0x4U) |
#define | ENET_ATCR_OFFEN_SHIFT (2U) |
#define | ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
#define | ENET_ATCR_OFFRST_MASK (0x8U) |
#define | ENET_ATCR_OFFRST_SHIFT (3U) |
#define | ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
#define | ENET_ATCR_PEREN_MASK (0x10U) |
#define | ENET_ATCR_PEREN_SHIFT (4U) |
#define | ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
#define | ENET_ATCR_PINPER_MASK (0x80U) |
#define | ENET_ATCR_PINPER_SHIFT (7U) |
#define | ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
#define | ENET_ATCR_RESTART_MASK (0x200U) |
#define | ENET_ATCR_RESTART_SHIFT (9U) |
#define | ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) |
#define | ENET_ATCR_CAPTURE_MASK (0x800U) |
#define | ENET_ATCR_CAPTURE_SHIFT (11U) |
#define | ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
#define | ENET_ATCR_SLAVE_MASK (0x2000U) |
#define | ENET_ATCR_SLAVE_SHIFT (13U) |
#define | ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
#define | ENET_ATCR_EN_MASK 0x1u |
#define | ENET_ATCR_EN_SHIFT 0 |
#define | ENET_ATCR_OFFEN_MASK 0x4u |
#define | ENET_ATCR_OFFEN_SHIFT 2 |
#define | ENET_ATCR_OFFRST_MASK 0x8u |
#define | ENET_ATCR_OFFRST_SHIFT 3 |
#define | ENET_ATCR_PEREN_MASK 0x10u |
#define | ENET_ATCR_PEREN_SHIFT 4 |
#define | ENET_ATCR_PINPER_MASK 0x80u |
#define | ENET_ATCR_PINPER_SHIFT 7 |
#define | ENET_ATCR_RESTART_MASK 0x200u |
#define | ENET_ATCR_RESTART_SHIFT 9 |
#define | ENET_ATCR_CAPTURE_MASK 0x800u |
#define | ENET_ATCR_CAPTURE_SHIFT 11 |
#define | ENET_ATCR_SLAVE_MASK 0x2000u |
#define | ENET_ATCR_SLAVE_SHIFT 13 |
#define | ENET_ATCR_EN_MASK (0x1U) |
#define | ENET_ATCR_EN_SHIFT (0U) |
#define | ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
#define | ENET_ATCR_OFFEN_MASK (0x4U) |
#define | ENET_ATCR_OFFEN_SHIFT (2U) |
#define | ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
#define | ENET_ATCR_OFFRST_MASK (0x8U) |
#define | ENET_ATCR_OFFRST_SHIFT (3U) |
#define | ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
#define | ENET_ATCR_PEREN_MASK (0x10U) |
#define | ENET_ATCR_PEREN_SHIFT (4U) |
#define | ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
#define | ENET_ATCR_PINPER_MASK (0x80U) |
#define | ENET_ATCR_PINPER_SHIFT (7U) |
#define | ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
#define | ENET_ATCR_RESTART_MASK (0x200U) |
#define | ENET_ATCR_RESTART_SHIFT (9U) |
#define | ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) |
#define | ENET_ATCR_CAPTURE_MASK (0x800U) |
#define | ENET_ATCR_CAPTURE_SHIFT (11U) |
#define | ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
#define | ENET_ATCR_SLAVE_MASK (0x2000U) |
#define | ENET_ATCR_SLAVE_SHIFT (13U) |
#define | ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
#define | ENET_ATCR_EN_MASK (0x1U) |
#define | ENET_ATCR_EN_SHIFT (0U) |
#define | ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
#define | ENET_ATCR_OFFEN_MASK (0x4U) |
#define | ENET_ATCR_OFFEN_SHIFT (2U) |
#define | ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
#define | ENET_ATCR_OFFRST_MASK (0x8U) |
#define | ENET_ATCR_OFFRST_SHIFT (3U) |
#define | ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
#define | ENET_ATCR_PEREN_MASK (0x10U) |
#define | ENET_ATCR_PEREN_SHIFT (4U) |
#define | ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
#define | ENET_ATCR_PINPER_MASK (0x80U) |
#define | ENET_ATCR_PINPER_SHIFT (7U) |
#define | ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
#define | ENET_ATCR_RESTART_MASK (0x200U) |
#define | ENET_ATCR_RESTART_SHIFT (9U) |
#define | ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) |
#define | ENET_ATCR_CAPTURE_MASK (0x800U) |
#define | ENET_ATCR_CAPTURE_SHIFT (11U) |
#define | ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
#define | ENET_ATCR_SLAVE_MASK (0x2000U) |
#define | ENET_ATCR_SLAVE_SHIFT (13U) |
#define | ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
#define | ENET_ATCR_EN_MASK (0x1U) |
#define | ENET_ATCR_EN_SHIFT (0U) |
#define | ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
#define | ENET_ATCR_OFFEN_MASK (0x4U) |
#define | ENET_ATCR_OFFEN_SHIFT (2U) |
#define | ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
#define | ENET_ATCR_OFFRST_MASK (0x8U) |
#define | ENET_ATCR_OFFRST_SHIFT (3U) |
#define | ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
#define | ENET_ATCR_PEREN_MASK (0x10U) |
#define | ENET_ATCR_PEREN_SHIFT (4U) |
#define | ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
#define | ENET_ATCR_PINPER_MASK (0x80U) |
#define | ENET_ATCR_PINPER_SHIFT (7U) |
#define | ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
#define | ENET_ATCR_RESTART_MASK (0x200U) |
#define | ENET_ATCR_RESTART_SHIFT (9U) |
#define | ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) |
#define | ENET_ATCR_CAPTURE_MASK (0x800U) |
#define | ENET_ATCR_CAPTURE_SHIFT (11U) |
#define | ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
#define | ENET_ATCR_SLAVE_MASK (0x2000U) |
#define | ENET_ATCR_SLAVE_SHIFT (13U) |
#define | ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
#define | ENET_ATCR_EN_MASK (0x1U) |
#define | ENET_ATCR_EN_SHIFT (0U) |
#define | ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
#define | ENET_ATCR_OFFEN_MASK (0x4U) |
#define | ENET_ATCR_OFFEN_SHIFT (2U) |
#define | ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
#define | ENET_ATCR_OFFRST_MASK (0x8U) |
#define | ENET_ATCR_OFFRST_SHIFT (3U) |
#define | ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
#define | ENET_ATCR_PEREN_MASK (0x10U) |
#define | ENET_ATCR_PEREN_SHIFT (4U) |
#define | ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
#define | ENET_ATCR_PINPER_MASK (0x80U) |
#define | ENET_ATCR_PINPER_SHIFT (7U) |
#define | ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
#define | ENET_ATCR_RESTART_MASK (0x200U) |
#define | ENET_ATCR_RESTART_SHIFT (9U) |
#define | ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) |
#define | ENET_ATCR_CAPTURE_MASK (0x800U) |
#define | ENET_ATCR_CAPTURE_SHIFT (11U) |
#define | ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
#define | ENET_ATCR_SLAVE_MASK (0x2000U) |
#define | ENET_ATCR_SLAVE_SHIFT (13U) |
#define | ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
TGSR - Timer Global Status Register | |
#define | ENET_TGSR_TF0_MASK (0x1U) |
#define | ENET_TGSR_TF0_SHIFT (0U) |
#define | ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
#define | ENET_TGSR_TF1_MASK (0x2U) |
#define | ENET_TGSR_TF1_SHIFT (1U) |
#define | ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
#define | ENET_TGSR_TF2_MASK (0x4U) |
#define | ENET_TGSR_TF2_SHIFT (2U) |
#define | ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
#define | ENET_TGSR_TF3_MASK (0x8U) |
#define | ENET_TGSR_TF3_SHIFT (3U) |
#define | ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
#define | ENET_TGSR_TF0_MASK 0x1u |
#define | ENET_TGSR_TF0_SHIFT 0 |
#define | ENET_TGSR_TF1_MASK 0x2u |
#define | ENET_TGSR_TF1_SHIFT 1 |
#define | ENET_TGSR_TF2_MASK 0x4u |
#define | ENET_TGSR_TF2_SHIFT 2 |
#define | ENET_TGSR_TF3_MASK 0x8u |
#define | ENET_TGSR_TF3_SHIFT 3 |
#define | ENET_TGSR_TF0_MASK (0x1U) |
#define | ENET_TGSR_TF0_SHIFT (0U) |
#define | ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
#define | ENET_TGSR_TF1_MASK (0x2U) |
#define | ENET_TGSR_TF1_SHIFT (1U) |
#define | ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
#define | ENET_TGSR_TF2_MASK (0x4U) |
#define | ENET_TGSR_TF2_SHIFT (2U) |
#define | ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
#define | ENET_TGSR_TF3_MASK (0x8U) |
#define | ENET_TGSR_TF3_SHIFT (3U) |
#define | ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
#define | ENET_TGSR_TF0_MASK (0x1U) |
#define | ENET_TGSR_TF0_SHIFT (0U) |
#define | ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
#define | ENET_TGSR_TF1_MASK (0x2U) |
#define | ENET_TGSR_TF1_SHIFT (1U) |
#define | ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
#define | ENET_TGSR_TF2_MASK (0x4U) |
#define | ENET_TGSR_TF2_SHIFT (2U) |
#define | ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
#define | ENET_TGSR_TF3_MASK (0x8U) |
#define | ENET_TGSR_TF3_SHIFT (3U) |
#define | ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
#define | ENET_TGSR_TF0_MASK (0x1U) |
#define | ENET_TGSR_TF0_SHIFT (0U) |
#define | ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
#define | ENET_TGSR_TF1_MASK (0x2U) |
#define | ENET_TGSR_TF1_SHIFT (1U) |
#define | ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
#define | ENET_TGSR_TF2_MASK (0x4U) |
#define | ENET_TGSR_TF2_SHIFT (2U) |
#define | ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
#define | ENET_TGSR_TF3_MASK (0x8U) |
#define | ENET_TGSR_TF3_SHIFT (3U) |
#define | ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
#define | ENET_TGSR_TF0_MASK (0x1U) |
#define | ENET_TGSR_TF0_SHIFT (0U) |
#define | ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
#define | ENET_TGSR_TF1_MASK (0x2U) |
#define | ENET_TGSR_TF1_SHIFT (1U) |
#define | ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
#define | ENET_TGSR_TF2_MASK (0x4U) |
#define | ENET_TGSR_TF2_SHIFT (2U) |
#define | ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
#define | ENET_TGSR_TF3_MASK (0x8U) |
#define | ENET_TGSR_TF3_SHIFT (3U) |
#define | ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
TCSR - Timer Control Status Register | |
#define | ENET_TCSR_TDRE_MASK (0x1U) |
#define | ENET_TCSR_TDRE_SHIFT (0U) |
#define | ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
#define | ENET_TCSR_TMODE_MASK (0x3CU) |
#define | ENET_TCSR_TMODE_SHIFT (2U) |
#define | ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
#define | ENET_TCSR_TIE_MASK (0x40U) |
#define | ENET_TCSR_TIE_SHIFT (6U) |
#define | ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
#define | ENET_TCSR_TF_MASK (0x80U) |
#define | ENET_TCSR_TF_SHIFT (7U) |
#define | ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
#define | ENET_TCSR_TDRE_MASK 0x1u |
#define | ENET_TCSR_TDRE_SHIFT 0 |
#define | ENET_TCSR_TMODE_MASK 0x3Cu |
#define | ENET_TCSR_TMODE_SHIFT 2 |
#define | ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK) |
#define | ENET_TCSR_TIE_MASK 0x40u |
#define | ENET_TCSR_TIE_SHIFT 6 |
#define | ENET_TCSR_TF_MASK 0x80u |
#define | ENET_TCSR_TF_SHIFT 7 |
#define | ENET_TCSR_TDRE_MASK (0x1U) |
#define | ENET_TCSR_TDRE_SHIFT (0U) |
#define | ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
#define | ENET_TCSR_TMODE_MASK (0x3CU) |
#define | ENET_TCSR_TMODE_SHIFT (2U) |
#define | ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
#define | ENET_TCSR_TIE_MASK (0x40U) |
#define | ENET_TCSR_TIE_SHIFT (6U) |
#define | ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
#define | ENET_TCSR_TF_MASK (0x80U) |
#define | ENET_TCSR_TF_SHIFT (7U) |
#define | ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
#define | ENET_TCSR_TDRE_MASK (0x1U) |
#define | ENET_TCSR_TDRE_SHIFT (0U) |
#define | ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
#define | ENET_TCSR_TMODE_MASK (0x3CU) |
#define | ENET_TCSR_TMODE_SHIFT (2U) |
#define | ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
#define | ENET_TCSR_TIE_MASK (0x40U) |
#define | ENET_TCSR_TIE_SHIFT (6U) |
#define | ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
#define | ENET_TCSR_TF_MASK (0x80U) |
#define | ENET_TCSR_TF_SHIFT (7U) |
#define | ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
#define | ENET_TCSR_TDRE_MASK (0x1U) |
#define | ENET_TCSR_TDRE_SHIFT (0U) |
#define | ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
#define | ENET_TCSR_TMODE_MASK (0x3CU) |
#define | ENET_TCSR_TMODE_SHIFT (2U) |
#define | ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
#define | ENET_TCSR_TIE_MASK (0x40U) |
#define | ENET_TCSR_TIE_SHIFT (6U) |
#define | ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
#define | ENET_TCSR_TF_MASK (0x80U) |
#define | ENET_TCSR_TF_SHIFT (7U) |
#define | ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
#define | ENET_TCSR_TDRE_MASK (0x1U) |
#define | ENET_TCSR_TDRE_SHIFT (0U) |
#define | ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
#define | ENET_TCSR_TMODE_MASK (0x3CU) |
#define | ENET_TCSR_TMODE_SHIFT (2U) |
#define | ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
#define | ENET_TCSR_TIE_MASK (0x40U) |
#define | ENET_TCSR_TIE_SHIFT (6U) |
#define | ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
#define | ENET_TCSR_TF_MASK (0x80U) |
#define | ENET_TCSR_TF_SHIFT (7U) |
#define | ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
TCSR - Timer Control Status Register | |
#define | ENET_TCSR_COUNT (4U) |
TCCR - Timer Compare Capture Register | |
#define | ENET_TCCR_COUNT (4U) |
#define ENET_ATCR_CAPTURE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.
#define ENET_ATCR_CAPTURE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.
#define ENET_ATCR_CAPTURE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.
#define ENET_ATCR_CAPTURE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.
#define ENET_ATCR_CAPTURE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) |
CAPTURE - Capture Timer Value 0b0..No effect. 0b1..The current time is captured and can be read from the ATVR register.
#define ENET_ATCR_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.
#define ENET_ATCR_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.
#define ENET_ATCR_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.
#define ENET_ATCR_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.
#define ENET_ATCR_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) |
EN - Enable Timer 0b0..The timer stops at the current value. 0b1..The timer starts incrementing.
#define ENET_ATCR_OFFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.
#define ENET_ATCR_OFFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.
#define ENET_ATCR_OFFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.
#define ENET_ATCR_OFFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.
#define ENET_ATCR_OFFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) |
OFFEN - Enable One-Shot Offset Event 0b0..Disable. 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field.
#define ENET_ATCR_OFFRST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
#define ENET_ATCR_OFFRST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
#define ENET_ATCR_OFFRST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
#define ENET_ATCR_OFFRST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
#define ENET_ATCR_OFFRST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) |
OFFRST - Reset Timer On Offset Event 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
#define ENET_ATCR_PEREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.
#define ENET_ATCR_PEREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.
#define ENET_ATCR_PEREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.
#define ENET_ATCR_PEREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.
#define ENET_ATCR_PEREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) |
PEREN - Enable Periodical Event 0b0..Disable. 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details.
#define ENET_ATCR_PINPER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
PINPER 0b0..Disable. 0b1..Enable.
#define ENET_ATCR_PINPER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
PINPER 0b0..Disable. 0b1..Enable.
#define ENET_ATCR_PINPER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
PINPER 0b0..Disable. 0b1..Enable.
#define ENET_ATCR_PINPER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
PINPER 0b0..Disable. 0b1..Enable.
#define ENET_ATCR_PINPER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) |
PINPER 0b0..Disable. 0b1..Enable.
#define ENET_ATCR_SLAVE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
#define ENET_ATCR_SLAVE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
#define ENET_ATCR_SLAVE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
#define ENET_ATCR_SLAVE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
#define ENET_ATCR_SLAVE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) |
SLAVE - Enable Timer Slave Mode 0b0..The timer is active and all configuration fields in this register are relevant. 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
#define ENET_BASE (0x400C0000u) |
Peripheral ENET base address
#define ENET_BASE_ADDRS { ENET_BASE } |
Array initializer of ENET peripheral base addresses
#define ENET_BASE_PTRS { ENET } |
Array initializer of ENET peripheral base pointers
#define ENET_ECR_DBGEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
#define ENET_ECR_DBGEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
#define ENET_ECR_DBGEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
#define ENET_ECR_DBGEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
#define ENET_ECR_DBGEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) |
DBGEN - Debug Enable 0b0..MAC continues operation in debug mode. 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
#define ENET_ECR_DBSWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
#define ENET_ECR_DBSWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
#define ENET_ECR_DBSWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
#define ENET_ECR_DBSWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
#define ENET_ECR_DBSWP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) |
DBSWP - Descriptor Byte Swapping Enable 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
#define ENET_ECR_EN1588 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.
#define ENET_ECR_EN1588 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.
#define ENET_ECR_EN1588 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.
#define ENET_ECR_EN1588 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.
#define ENET_ECR_EN1588 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) |
EN1588 - EN1588 Enable 0b0..Legacy FEC buffer descriptors and functions enabled. 0b1..Enhanced frame time-stamping functions enabled.
#define ENET_ECR_ETHEREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.
#define ENET_ECR_ETHEREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.
#define ENET_ECR_ETHEREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.
#define ENET_ECR_ETHEREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.
#define ENET_ECR_ETHEREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) |
ETHEREN - Ethernet Enable 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. 0b1..MAC is enabled, and reception and transmission are possible.
#define ENET_ECR_MAGICEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
#define ENET_ECR_MAGICEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
#define ENET_ECR_MAGICEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
#define ENET_ECR_MAGICEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
#define ENET_ECR_MAGICEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) |
MAGICEN - Magic Packet Detection Enable 0b0..Magic detection logic disabled. 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
#define ENET_ECR_SLEEP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.
#define ENET_ECR_SLEEP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.
#define ENET_ECR_SLEEP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.
#define ENET_ECR_SLEEP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.
#define ENET_ECR_SLEEP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) |
SLEEP - Sleep Mode Enable 0b0..Normal operating mode. 0b1..Sleep mode.
#define ENET_EIMR_BABR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_BABR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_BABR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_BABR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_BABR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) |
BABR - BABR Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_BABT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_BABT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_BABT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_BABT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_BABT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) |
BABT - BABT Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_GRA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_GRA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_GRA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_GRA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_GRA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) |
GRA - GRA Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_TXB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_TXB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_TXB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_TXB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_TXB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) |
TXB - TXB Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_TXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_TXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_TXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_TXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_EIMR_TXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) |
TXF - TXF Interrupt Mask 0b0..The corresponding interrupt source is masked. 0b1..The corresponding interrupt source is not masked.
#define ENET_MIBC_MIB_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.
#define ENET_MIBC_MIB_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.
#define ENET_MIBC_MIB_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.
#define ENET_MIBC_MIB_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.
#define ENET_MIBC_MIB_CLEAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) |
MIB_CLEAR - MIB Clear 0b0..See note above. 0b1..All statistics counters are reset to 0.
#define ENET_MIBC_MIB_DIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
#define ENET_MIBC_MIB_DIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
#define ENET_MIBC_MIB_DIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
#define ENET_MIBC_MIB_DIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
#define ENET_MIBC_MIB_DIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) |
MIB_DIS - Disable MIB Logic 0b0..MIB logic is enabled. 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
#define ENET_MIBC_MIB_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.
#define ENET_MIBC_MIB_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.
#define ENET_MIBC_MIB_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.
#define ENET_MIBC_MIB_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.
#define ENET_MIBC_MIB_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) |
MIB_IDLE - MIB Idle 0b0..The MIB block is updating MIB counters. 0b1..The MIB block is not currently updating any MIB counters.
#define ENET_MMFR_OP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) |
OP - Operation Code 0b00..Write frame operation, but not MII compliant. 0b01..Write frame operation for a valid MII management frame. 0b10..Read frame operation for a valid MII management frame. 0b11..Read frame operation, but not MII compliant.
#define ENET_MMFR_OP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK) |
OP - Operation Code 0b00..Write frame operation, but not MII compliant. 0b01..Write frame operation for a valid MII management frame. 0b10..Read frame operation for a valid MII management frame. 0b11..Read frame operation, but not MII compliant.
#define ENET_MMFR_OP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) |
OP - Operation Code 0b00..Write frame operation, but not MII compliant. 0b01..Write frame operation for a valid MII management frame. 0b10..Read frame operation for a valid MII management frame. 0b11..Read frame operation, but not MII compliant.
#define ENET_MSCR_DIS_PRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.
#define ENET_MSCR_DIS_PRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.
#define ENET_MSCR_DIS_PRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.
#define ENET_MSCR_DIS_PRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.
#define ENET_MSCR_DIS_PRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) |
DIS_PRE - Disable Preamble 0b0..Preamble enabled. 0b1..Preamble (32 ones) is not prepended to the MII management frame.
#define ENET_MSCR_HOLDTIME | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles
#define ENET_MSCR_HOLDTIME | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK) |
HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles
#define ENET_MSCR_HOLDTIME | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles
#define ENET_MSCR_HOLDTIME | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles
#define ENET_MSCR_HOLDTIME | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles
#define ENET_MSCR_HOLDTIME | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) |
HOLDTIME - Hold time On MDIO Output 0b000..1 internal module clock cycle 0b001..2 internal module clock cycles 0b010..3 internal module clock cycles 0b111..8 internal module clock cycles
#define ENET_RACC_IPDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#define ENET_RACC_IPDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#define ENET_RACC_IPDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#define ENET_RACC_IPDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#define ENET_RACC_IPDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) |
IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum 0b0..Frames with wrong IPv4 header checksum are not discarded. 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#define ENET_RACC_LINEDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
#define ENET_RACC_LINEDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
#define ENET_RACC_LINEDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
#define ENET_RACC_LINEDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
#define ENET_RACC_LINEDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) |
LINEDIS - Enable Discard Of Frames With MAC Layer Errors 0b0..Frames with errors are not discarded. 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
#define ENET_RACC_PADREM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
#define ENET_RACC_PADREM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
#define ENET_RACC_PADREM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
#define ENET_RACC_PADREM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
#define ENET_RACC_PADREM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) |
PADREM - Enable Padding Removal For Short IP Frames 0b0..Padding not removed. 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
#define ENET_RACC_PRODIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#define ENET_RACC_PRODIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#define ENET_RACC_PRODIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#define ENET_RACC_PRODIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#define ENET_RACC_PRODIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) |
PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum 0b0..Frames with wrong checksum are not discarded. 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared).
#define ENET_RACC_SHIFT16 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
#define ENET_RACC_SHIFT16 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
#define ENET_RACC_SHIFT16 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
#define ENET_RACC_SHIFT16 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
#define ENET_RACC_SHIFT16 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) |
SHIFT16 - RX FIFO Shift-16 0b0..Disabled. 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
#define ENET_RCR_CFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
#define ENET_RCR_CFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
#define ENET_RCR_CFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
#define ENET_RCR_CFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
#define ENET_RCR_CFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) |
CFEN - MAC Control Frame Enable 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
#define ENET_RCR_CRCFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.
#define ENET_RCR_CRCFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.
#define ENET_RCR_CRCFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.
#define ENET_RCR_CRCFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.
#define ENET_RCR_CRCFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) |
CRCFWD - Terminate/Forward Received CRC 0b0..The CRC field of received frames is transmitted to the user application. 0b1..The CRC field is stripped from the frame.
#define ENET_RCR_DRT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. Normally used for half-duplex mode.
DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
#define ENET_RCR_DRT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. Normally used for half-duplex mode.
DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
#define ENET_RCR_DRT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. Normally used for half-duplex mode.
DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
#define ENET_RCR_DRT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit. Used for full-duplex or to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. Normally used for half-duplex mode.
DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
#define ENET_RCR_DRT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) |
DRT - Disable Receive On Transmit 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
#define ENET_RCR_LOOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
#define ENET_RCR_LOOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
#define ENET_RCR_LOOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
#define ENET_RCR_LOOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
#define ENET_RCR_LOOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) |
LOOP - Internal Loopback 0b0..Loopback disabled. 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
#define ENET_RCR_MII_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
#define ENET_RCR_MII_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
#define ENET_RCR_MII_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
#define ENET_RCR_MII_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
#define ENET_RCR_MII_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) |
MII_MODE - Media Independent Interface Mode 0b0..Reserved. 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
#define ENET_RCR_NLC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.
#define ENET_RCR_NLC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.
#define ENET_RCR_NLC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.
#define ENET_RCR_NLC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.
#define ENET_RCR_NLC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) |
NLC - Payload Length Check Disable 0b0..The payload length check is disabled. 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLC] field.
#define ENET_RCR_PADEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.
#define ENET_RCR_PADEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.
#define ENET_RCR_PADEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.
#define ENET_RCR_PADEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.
#define ENET_RCR_PADEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) |
PADEN - Enable Frame Padding Remove On Receive 0b0..No padding is removed on receive by the MAC. 0b1..Padding is removed from received frames.
#define ENET_RCR_PAUFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.
#define ENET_RCR_PAUFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.
#define ENET_RCR_PAUFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.
#define ENET_RCR_PAUFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.
#define ENET_RCR_PAUFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) |
PAUFWD - Terminate/Forward Pause Frames 0b0..Pause frames are terminated and discarded in the MAC. 0b1..Pause frames are forwarded to the user application.
#define ENET_RCR_PROM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.
#define ENET_RCR_PROM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.
#define ENET_RCR_PROM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.
#define ENET_RCR_PROM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.
#define ENET_RCR_PROM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) |
PROM - Promiscuous Mode 0b0..Disabled. 0b1..Enabled.
#define ENET_RCR_RMII_10T | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
RMII_10T 0b0..100 Mbps operation. 0b1..10 Mbps operation.
RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.
#define ENET_RCR_RMII_10T | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
RMII_10T 0b0..100 Mbps operation. 0b1..10 Mbps operation.
RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.
#define ENET_RCR_RMII_10T | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
RMII_10T 0b0..100 Mbps operation. 0b1..10 Mbps operation.
RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.
#define ENET_RCR_RMII_10T | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
RMII_10T 0b0..100 Mbps operation. 0b1..10 Mbps operation.
RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.
#define ENET_RCR_RMII_10T | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) |
RMII_10T 0b0..100-Mbit/s operation. 0b1..10-Mbit/s operation.
#define ENET_RCR_RMII_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.
#define ENET_RCR_RMII_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.
#define ENET_RCR_RMII_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.
#define ENET_RCR_RMII_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.
#define ENET_RCR_RMII_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) |
RMII_MODE - RMII Mode Enable 0b0..MAC configured for MII mode. 0b1..MAC configured for RMII operation.
#define ENET_TACC_IPCHK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.
#define ENET_TACC_IPCHK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.
#define ENET_TACC_IPCHK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.
#define ENET_TACC_IPCHK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.
#define ENET_TACC_IPCHK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) |
IPCHK 0b0..Checksum is not inserted. 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified.
#define ENET_TACC_PROCHK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.
#define ENET_TACC_PROCHK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.
#define ENET_TACC_PROCHK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.
#define ENET_TACC_PROCHK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.
#define ENET_TACC_PROCHK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) |
PROCHK 0b0..Checksum not inserted. 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified.
#define ENET_TACC_SHIFT16 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.
#define ENET_TACC_SHIFT16 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.
#define ENET_TACC_SHIFT16 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.
#define ENET_TACC_SHIFT16 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.
#define ENET_TACC_SHIFT16 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) |
SHIFT16 - TX FIFO Shift-16 0b0..Disabled. 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header.
#define ENET_TCR_ADDINS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
#define ENET_TCR_ADDINS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
#define ENET_TCR_ADDINS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
#define ENET_TCR_ADDINS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
#define ENET_TCR_ADDINS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) |
ADDINS - Set MAC Address On Transmit 0b0..The source MAC address is not modified by the MAC. 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
#define ENET_TCR_ADDSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.
#define ENET_TCR_ADDSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK) |
ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.
#define ENET_TCR_ADDSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.
#define ENET_TCR_ADDSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.
#define ENET_TCR_ADDSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.
#define ENET_TCR_ADDSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) |
ADDSEL - Source MAC Address Select On Transmit 0b000..Node MAC address programmed on PADDR1/2 registers. 0b100..Reserved. 0b101..Reserved. 0b110..Reserved.
#define ENET_TCR_CRCFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
#define ENET_TCR_CRCFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
#define ENET_TCR_CRCFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
#define ENET_TCR_CRCFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
#define ENET_TCR_CRCFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) |
CRCFWD - Forward Frame From Application With CRC 0b0..TxBD[TC] controls whether the frame has a CRC from the application. 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
#define ENET_TCR_TFC_PAUSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.
#define ENET_TCR_TFC_PAUSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.
#define ENET_TCR_TFC_PAUSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.
#define ENET_TCR_TFC_PAUSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.
#define ENET_TCR_TFC_PAUSE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) |
TFC_PAUSE - Transmit Frame Control Pause 0b0..No PAUSE frame transmitted. 0b1..The MAC stops transmission of data frames after the current transmission is complete.
#define ENET_TCSR_TDRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled
#define ENET_TCSR_TDRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled
#define ENET_TCSR_TDRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled
#define ENET_TCSR_TDRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled
#define ENET_TCSR_TDRE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) |
TDRE - Timer DMA Request Enable 0b0..DMA request is disabled 0b1..DMA request is enabled
#define ENET_TCSR_TF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred 0b1..Input Capture or Output Compare has occurred
TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.
#define ENET_TCSR_TF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred 0b1..Input Capture or Output Compare has occurred
TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.
#define ENET_TCSR_TF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.
#define ENET_TCSR_TF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.
#define ENET_TCSR_TF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) |
TF - Timer Flag 0b0..Input Capture or Output Compare has not occurred. 0b1..Input Capture or Output Compare has occurred.
#define ENET_TCSR_TIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define ENET_TCSR_TIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define ENET_TCSR_TIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define ENET_TCSR_TIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define ENET_TCSR_TIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) |
TIE - Timer Interrupt Enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define ENET_TCSR_TMODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge 0b0010..Timer Channel is configured for Input Capture on falling edge 0b0011..Timer Channel is configured for Input Capture on both edges 0b0100..Timer Channel is configured for Output Compare - software only 0b0101..Timer Channel is configured for Output Compare - toggle output on compare 0b0110..Timer Channel is configured for Output Compare - clear output on compare 0b0111..Timer Channel is configured for Output Compare - set output on compare 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow 0b1100..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle
TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
#define ENET_TCSR_TMODE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK) |
TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge 0b0010..Timer Channel is configured for Input Capture on falling edge 0b0011..Timer Channel is configured for Input Capture on both edges 0b0100..Timer Channel is configured for Output Compare - software only 0b0101..Timer Channel is configured for Output Compare - toggle output on compare 0b0110..Timer Channel is configured for Output Compare - clear output on compare 0b0111..Timer Channel is configured for Output Compare - set output on compare 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow 0b1100..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle
TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
#define ENET_TCSR_TMODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge 0b0010..Timer Channel is configured for Input Capture on falling edge 0b0011..Timer Channel is configured for Input Capture on both edges 0b0100..Timer Channel is configured for Output Compare - software only 0b0101..Timer Channel is configured for Output Compare - toggle output on compare 0b0110..Timer Channel is configured for Output Compare - clear output on compare 0b0111..Timer Channel is configured for Output Compare - set output on compare 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow 0b1100..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588 clock cycle 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588 clock cycle
TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
#define ENET_TCSR_TMODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
#define ENET_TCSR_TMODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
#define ENET_TCSR_TMODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) |
TMODE - Timer Mode 0b0000..Timer Channel is disabled. 0b0001..Timer Channel is configured for Input Capture on rising edge. 0b0010..Timer Channel is configured for Input Capture on falling edge. 0b0011..Timer Channel is configured for Input Capture on both edges. 0b0100..Timer Channel is configured for Output Compare - software only. 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. 0b0110..Timer Channel is configured for Output Compare - clear output on compare. 0b0111..Timer Channel is configured for Output Compare - set output on compare. 0b1000..Reserved 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. 0b110x..Reserved 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle. 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
#define ENET_TFWR_STRFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.
#define ENET_TFWR_STRFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.
#define ENET_TFWR_STRFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.
#define ENET_TFWR_STRFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.
#define ENET_TFWR_STRFWD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) |
STRFWD - Store And Forward Enable 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. 0b1..Enabled.
#define ENET_TFWR_TFWR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b111110..3968 bytes written. 0b111111..4032 bytes written.
TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.
#define ENET_TFWR_TFWR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK) |
TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b111110..3968 bytes written. 0b111111..4032 bytes written.
TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.
#define ENET_TFWR_TFWR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b111110..3968 bytes written. 0b111111..4032 bytes written.
TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.
#define ENET_TFWR_TFWR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.
#define ENET_TFWR_TFWR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.
#define ENET_TFWR_TFWR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) |
TFWR - Transmit FIFO Write 0b000000..64 bytes written. 0b000001..64 bytes written. 0b000010..128 bytes written. 0b000011..192 bytes written. 0b011111..1984 bytes written.
#define ENET_TGSR_TF0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set
#define ENET_TGSR_TF0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set
#define ENET_TGSR_TF0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set
#define ENET_TGSR_TF0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set
#define ENET_TGSR_TF0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) |
TF0 - Copy Of Timer Flag For Channel 0 0b0..Timer Flag for Channel 0 is clear 0b1..Timer Flag for Channel 0 is set
#define ENET_TGSR_TF1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set
#define ENET_TGSR_TF1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set
#define ENET_TGSR_TF1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set
#define ENET_TGSR_TF1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set
#define ENET_TGSR_TF1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) |
TF1 - Copy Of Timer Flag For Channel 1 0b0..Timer Flag for Channel 1 is clear 0b1..Timer Flag for Channel 1 is set
#define ENET_TGSR_TF2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set
#define ENET_TGSR_TF2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set
#define ENET_TGSR_TF2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set
#define ENET_TGSR_TF2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set
#define ENET_TGSR_TF2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) |
TF2 - Copy Of Timer Flag For Channel 2 0b0..Timer Flag for Channel 2 is clear 0b1..Timer Flag for Channel 2 is set
#define ENET_TGSR_TF3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set
#define ENET_TGSR_TF3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set
#define ENET_TGSR_TF3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set
#define ENET_TGSR_TF3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set
#define ENET_TGSR_TF3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) |
TF3 - Copy Of Timer Flag For Channel 3 0b0..Timer Flag for Channel 3 is clear 0b1..Timer Flag for Channel 3 is set
#define ENET_Transmit_IRQS { ENET_Transmit_IRQn } |
Interrupt vectors for the ENET peripheral type