FB Register Masks

Macros
#define	FB_BASE   (0x4000C000u)
#define	FB   ((FB_Type *)FB_BASE)
#define	FB_BASE_ADDRS   { FB_BASE }
#define	FB_BASE_PTRS   { FB }
#define	FB_CSCR_EXALE_MASK   0x400000u
#define	FB_CSCR_EXALE_SHIFT   22
#define	FB_CSAR_COUNT   (6U)
#define	FB_CSMR_COUNT   (6U)
#define	FB_CSCR_COUNT   (6U)
#define	FB_CSAR_COUNT   (6U)
#define	FB_CSMR_COUNT   (6U)
#define	FB_CSCR_COUNT   (6U)
#define	FB_CSAR_COUNT   (6U)
#define	FB_CSMR_COUNT   (6U)
#define	FB_CSCR_COUNT   (6U)
#define	FB_CSAR_COUNT   (6U)
#define	FB_CSMR_COUNT   (6U)
#define	FB_CSCR_COUNT   (6U)

CSAR - Chip Select Address Register
#define	FB_CSAR_BA_MASK   (0xFFFF0000U)
#define	FB_CSAR_BA_SHIFT   (16U)
#define	FB_CSAR_BA(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
#define	FB_CSAR_BA_MASK   0xFFFF0000u
#define	FB_CSAR_BA_SHIFT   16
#define	FB_CSAR_BA(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
#define	FB_CSAR_BA_MASK   (0xFFFF0000U)
#define	FB_CSAR_BA_SHIFT   (16U)
#define	FB_CSAR_BA(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
#define	FB_CSAR_BA_MASK   (0xFFFF0000U)
#define	FB_CSAR_BA_SHIFT   (16U)
#define	FB_CSAR_BA(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
#define	FB_CSAR_BA_MASK   (0xFFFF0000U)
#define	FB_CSAR_BA_SHIFT   (16U)
#define	FB_CSAR_BA(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
#define	FB_CSAR_BA_MASK   (0xFFFF0000U)
#define	FB_CSAR_BA_SHIFT   (16U)
#define	FB_CSAR_BA(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)

CSAR - Chip Select Address Register
#define	FB_CSAR_COUNT   (6U)

CSMR - Chip Select Mask Register
#define	FB_CSMR_V_MASK   (0x1U)
#define	FB_CSMR_V_SHIFT   (0U)
#define	FB_CSMR_V(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
#define	FB_CSMR_WP_MASK   (0x100U)
#define	FB_CSMR_WP_SHIFT   (8U)
#define	FB_CSMR_WP(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
#define	FB_CSMR_BAM_MASK   (0xFFFF0000U)
#define	FB_CSMR_BAM_SHIFT   (16U)
#define	FB_CSMR_BAM(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
#define	FB_CSMR_V_MASK   0x1u
#define	FB_CSMR_V_SHIFT   0
#define	FB_CSMR_WP_MASK   0x100u
#define	FB_CSMR_WP_SHIFT   8
#define	FB_CSMR_BAM_MASK   0xFFFF0000u
#define	FB_CSMR_BAM_SHIFT   16
#define	FB_CSMR_BAM(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
#define	FB_CSMR_V_MASK   (0x1U)
#define	FB_CSMR_V_SHIFT   (0U)
#define	FB_CSMR_V(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
#define	FB_CSMR_WP_MASK   (0x100U)
#define	FB_CSMR_WP_SHIFT   (8U)
#define	FB_CSMR_WP(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
#define	FB_CSMR_BAM_MASK   (0xFFFF0000U)
#define	FB_CSMR_BAM_SHIFT   (16U)
#define	FB_CSMR_BAM(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
#define	FB_CSMR_V_MASK   (0x1U)
#define	FB_CSMR_V_SHIFT   (0U)
#define	FB_CSMR_V(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
#define	FB_CSMR_WP_MASK   (0x100U)
#define	FB_CSMR_WP_SHIFT   (8U)
#define	FB_CSMR_WP(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
#define	FB_CSMR_BAM_MASK   (0xFFFF0000U)
#define	FB_CSMR_BAM_SHIFT   (16U)
#define	FB_CSMR_BAM(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
#define	FB_CSMR_V_MASK   (0x1U)
#define	FB_CSMR_V_SHIFT   (0U)
#define	FB_CSMR_V(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
#define	FB_CSMR_WP_MASK   (0x100U)
#define	FB_CSMR_WP_SHIFT   (8U)
#define	FB_CSMR_WP(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
#define	FB_CSMR_BAM_MASK   (0xFFFF0000U)
#define	FB_CSMR_BAM_SHIFT   (16U)
#define	FB_CSMR_BAM(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
#define	FB_CSMR_V_MASK   (0x1U)
#define	FB_CSMR_V_SHIFT   (0U)
#define	FB_CSMR_V(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
#define	FB_CSMR_WP_MASK   (0x100U)
#define	FB_CSMR_WP_SHIFT   (8U)
#define	FB_CSMR_WP(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
#define	FB_CSMR_BAM_MASK   (0xFFFF0000U)
#define	FB_CSMR_BAM_SHIFT   (16U)
#define	FB_CSMR_BAM(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)

CSMR - Chip Select Mask Register
#define	FB_CSMR_COUNT   (6U)

CSCR - Chip Select Control Register
#define	FB_CSCR_BSTW_MASK   (0x8U)
#define	FB_CSCR_BSTW_SHIFT   (3U)
#define	FB_CSCR_BSTW(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
#define	FB_CSCR_BSTR_MASK   (0x10U)
#define	FB_CSCR_BSTR_SHIFT   (4U)
#define	FB_CSCR_BSTR(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
#define	FB_CSCR_BEM_MASK   (0x20U)
#define	FB_CSCR_BEM_SHIFT   (5U)
#define	FB_CSCR_BEM(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
#define	FB_CSCR_PS_MASK   (0xC0U)
#define	FB_CSCR_PS_SHIFT   (6U)
#define	FB_CSCR_PS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
#define	FB_CSCR_AA_MASK   (0x100U)
#define	FB_CSCR_AA_SHIFT   (8U)
#define	FB_CSCR_AA(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
#define	FB_CSCR_BLS_MASK   (0x200U)
#define	FB_CSCR_BLS_SHIFT   (9U)
#define	FB_CSCR_BLS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
#define	FB_CSCR_WS_MASK   (0xFC00U)
#define	FB_CSCR_WS_SHIFT   (10U)
#define	FB_CSCR_WS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
#define	FB_CSCR_WRAH_MASK   (0x30000U)
#define	FB_CSCR_WRAH_SHIFT   (16U)
#define	FB_CSCR_WRAH(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
#define	FB_CSCR_RDAH_MASK   (0xC0000U)
#define	FB_CSCR_RDAH_SHIFT   (18U)
#define	FB_CSCR_RDAH(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
#define	FB_CSCR_ASET_MASK   (0x300000U)
#define	FB_CSCR_ASET_SHIFT   (20U)
#define	FB_CSCR_ASET(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
#define	FB_CSCR_EXTS_MASK   (0x400000U)
#define	FB_CSCR_EXTS_SHIFT   (22U)
#define	FB_CSCR_EXTS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
#define	FB_CSCR_SWSEN_MASK   (0x800000U)
#define	FB_CSCR_SWSEN_SHIFT   (23U)
#define	FB_CSCR_SWSEN(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
#define	FB_CSCR_SWS_MASK   (0xFC000000U)
#define	FB_CSCR_SWS_SHIFT   (26U)
#define	FB_CSCR_SWS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
#define	FB_CSCR_BSTW_MASK   0x8u
#define	FB_CSCR_BSTW_SHIFT   3
#define	FB_CSCR_BSTR_MASK   0x10u
#define	FB_CSCR_BSTR_SHIFT   4
#define	FB_CSCR_BEM_MASK   0x20u
#define	FB_CSCR_BEM_SHIFT   5
#define	FB_CSCR_PS_MASK   0xC0u
#define	FB_CSCR_PS_SHIFT   6
#define	FB_CSCR_PS(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
#define	FB_CSCR_AA_MASK   0x100u
#define	FB_CSCR_AA_SHIFT   8
#define	FB_CSCR_BLS_MASK   0x200u
#define	FB_CSCR_BLS_SHIFT   9
#define	FB_CSCR_WS_MASK   0xFC00u
#define	FB_CSCR_WS_SHIFT   10
#define	FB_CSCR_WS(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
#define	FB_CSCR_WRAH_MASK   0x30000u
#define	FB_CSCR_WRAH_SHIFT   16
#define	FB_CSCR_WRAH(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
#define	FB_CSCR_RDAH_MASK   0xC0000u
#define	FB_CSCR_RDAH_SHIFT   18
#define	FB_CSCR_RDAH(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
#define	FB_CSCR_ASET_MASK   0x300000u
#define	FB_CSCR_ASET_SHIFT   20
#define	FB_CSCR_ASET(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
#define	FB_CSCR_SWSEN_MASK   0x800000u
#define	FB_CSCR_SWSEN_SHIFT   23
#define	FB_CSCR_SWS_MASK   0xFC000000u
#define	FB_CSCR_SWS_SHIFT   26
#define	FB_CSCR_SWS(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
#define	FB_CSCR_BSTW_MASK   (0x8U)
#define	FB_CSCR_BSTW_SHIFT   (3U)
#define	FB_CSCR_BSTW(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
#define	FB_CSCR_BSTR_MASK   (0x10U)
#define	FB_CSCR_BSTR_SHIFT   (4U)
#define	FB_CSCR_BSTR(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
#define	FB_CSCR_BEM_MASK   (0x20U)
#define	FB_CSCR_BEM_SHIFT   (5U)
#define	FB_CSCR_BEM(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
#define	FB_CSCR_PS_MASK   (0xC0U)
#define	FB_CSCR_PS_SHIFT   (6U)
#define	FB_CSCR_PS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
#define	FB_CSCR_AA_MASK   (0x100U)
#define	FB_CSCR_AA_SHIFT   (8U)
#define	FB_CSCR_AA(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
#define	FB_CSCR_BLS_MASK   (0x200U)
#define	FB_CSCR_BLS_SHIFT   (9U)
#define	FB_CSCR_BLS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
#define	FB_CSCR_WS_MASK   (0xFC00U)
#define	FB_CSCR_WS_SHIFT   (10U)
#define	FB_CSCR_WS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
#define	FB_CSCR_WRAH_MASK   (0x30000U)
#define	FB_CSCR_WRAH_SHIFT   (16U)
#define	FB_CSCR_WRAH(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
#define	FB_CSCR_RDAH_MASK   (0xC0000U)
#define	FB_CSCR_RDAH_SHIFT   (18U)
#define	FB_CSCR_RDAH(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
#define	FB_CSCR_ASET_MASK   (0x300000U)
#define	FB_CSCR_ASET_SHIFT   (20U)
#define	FB_CSCR_ASET(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
#define	FB_CSCR_EXTS_MASK   (0x400000U)
#define	FB_CSCR_EXTS_SHIFT   (22U)
#define	FB_CSCR_EXTS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
#define	FB_CSCR_SWSEN_MASK   (0x800000U)
#define	FB_CSCR_SWSEN_SHIFT   (23U)
#define	FB_CSCR_SWSEN(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
#define	FB_CSCR_SWS_MASK   (0xFC000000U)
#define	FB_CSCR_SWS_SHIFT   (26U)
#define	FB_CSCR_SWS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
#define	FB_CSCR_BSTW_MASK   (0x8U)
#define	FB_CSCR_BSTW_SHIFT   (3U)
#define	FB_CSCR_BSTW(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
#define	FB_CSCR_BSTR_MASK   (0x10U)
#define	FB_CSCR_BSTR_SHIFT   (4U)
#define	FB_CSCR_BSTR(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
#define	FB_CSCR_BEM_MASK   (0x20U)
#define	FB_CSCR_BEM_SHIFT   (5U)
#define	FB_CSCR_BEM(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
#define	FB_CSCR_PS_MASK   (0xC0U)
#define	FB_CSCR_PS_SHIFT   (6U)
#define	FB_CSCR_PS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
#define	FB_CSCR_AA_MASK   (0x100U)
#define	FB_CSCR_AA_SHIFT   (8U)
#define	FB_CSCR_AA(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
#define	FB_CSCR_BLS_MASK   (0x200U)
#define	FB_CSCR_BLS_SHIFT   (9U)
#define	FB_CSCR_BLS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
#define	FB_CSCR_WS_MASK   (0xFC00U)
#define	FB_CSCR_WS_SHIFT   (10U)
#define	FB_CSCR_WS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
#define	FB_CSCR_WRAH_MASK   (0x30000U)
#define	FB_CSCR_WRAH_SHIFT   (16U)
#define	FB_CSCR_WRAH(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
#define	FB_CSCR_RDAH_MASK   (0xC0000U)
#define	FB_CSCR_RDAH_SHIFT   (18U)
#define	FB_CSCR_RDAH(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
#define	FB_CSCR_ASET_MASK   (0x300000U)
#define	FB_CSCR_ASET_SHIFT   (20U)
#define	FB_CSCR_ASET(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
#define	FB_CSCR_EXTS_MASK   (0x400000U)
#define	FB_CSCR_EXTS_SHIFT   (22U)
#define	FB_CSCR_EXTS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
#define	FB_CSCR_SWSEN_MASK   (0x800000U)
#define	FB_CSCR_SWSEN_SHIFT   (23U)
#define	FB_CSCR_SWSEN(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
#define	FB_CSCR_SWS_MASK   (0xFC000000U)
#define	FB_CSCR_SWS_SHIFT   (26U)
#define	FB_CSCR_SWS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
#define	FB_CSCR_BSTW_MASK   (0x8U)
#define	FB_CSCR_BSTW_SHIFT   (3U)
#define	FB_CSCR_BSTW(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
#define	FB_CSCR_BSTR_MASK   (0x10U)
#define	FB_CSCR_BSTR_SHIFT   (4U)
#define	FB_CSCR_BSTR(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
#define	FB_CSCR_BEM_MASK   (0x20U)
#define	FB_CSCR_BEM_SHIFT   (5U)
#define	FB_CSCR_BEM(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
#define	FB_CSCR_PS_MASK   (0xC0U)
#define	FB_CSCR_PS_SHIFT   (6U)
#define	FB_CSCR_PS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
#define	FB_CSCR_AA_MASK   (0x100U)
#define	FB_CSCR_AA_SHIFT   (8U)
#define	FB_CSCR_AA(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
#define	FB_CSCR_BLS_MASK   (0x200U)
#define	FB_CSCR_BLS_SHIFT   (9U)
#define	FB_CSCR_BLS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
#define	FB_CSCR_WS_MASK   (0xFC00U)
#define	FB_CSCR_WS_SHIFT   (10U)
#define	FB_CSCR_WS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
#define	FB_CSCR_WRAH_MASK   (0x30000U)
#define	FB_CSCR_WRAH_SHIFT   (16U)
#define	FB_CSCR_WRAH(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
#define	FB_CSCR_RDAH_MASK   (0xC0000U)
#define	FB_CSCR_RDAH_SHIFT   (18U)
#define	FB_CSCR_RDAH(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
#define	FB_CSCR_ASET_MASK   (0x300000U)
#define	FB_CSCR_ASET_SHIFT   (20U)
#define	FB_CSCR_ASET(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
#define	FB_CSCR_EXTS_MASK   (0x400000U)
#define	FB_CSCR_EXTS_SHIFT   (22U)
#define	FB_CSCR_EXTS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
#define	FB_CSCR_SWSEN_MASK   (0x800000U)
#define	FB_CSCR_SWSEN_SHIFT   (23U)
#define	FB_CSCR_SWSEN(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
#define	FB_CSCR_SWS_MASK   (0xFC000000U)
#define	FB_CSCR_SWS_SHIFT   (26U)
#define	FB_CSCR_SWS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
#define	FB_CSCR_BSTW_MASK   (0x8U)
#define	FB_CSCR_BSTW_SHIFT   (3U)
#define	FB_CSCR_BSTW(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
#define	FB_CSCR_BSTR_MASK   (0x10U)
#define	FB_CSCR_BSTR_SHIFT   (4U)
#define	FB_CSCR_BSTR(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
#define	FB_CSCR_BEM_MASK   (0x20U)
#define	FB_CSCR_BEM_SHIFT   (5U)
#define	FB_CSCR_BEM(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
#define	FB_CSCR_PS_MASK   (0xC0U)
#define	FB_CSCR_PS_SHIFT   (6U)
#define	FB_CSCR_PS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
#define	FB_CSCR_AA_MASK   (0x100U)
#define	FB_CSCR_AA_SHIFT   (8U)
#define	FB_CSCR_AA(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
#define	FB_CSCR_BLS_MASK   (0x200U)
#define	FB_CSCR_BLS_SHIFT   (9U)
#define	FB_CSCR_BLS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
#define	FB_CSCR_WS_MASK   (0xFC00U)
#define	FB_CSCR_WS_SHIFT   (10U)
#define	FB_CSCR_WS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
#define	FB_CSCR_WRAH_MASK   (0x30000U)
#define	FB_CSCR_WRAH_SHIFT   (16U)
#define	FB_CSCR_WRAH(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
#define	FB_CSCR_RDAH_MASK   (0xC0000U)
#define	FB_CSCR_RDAH_SHIFT   (18U)
#define	FB_CSCR_RDAH(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
#define	FB_CSCR_ASET_MASK   (0x300000U)
#define	FB_CSCR_ASET_SHIFT   (20U)
#define	FB_CSCR_ASET(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
#define	FB_CSCR_EXTS_MASK   (0x400000U)
#define	FB_CSCR_EXTS_SHIFT   (22U)
#define	FB_CSCR_EXTS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
#define	FB_CSCR_SWSEN_MASK   (0x800000U)
#define	FB_CSCR_SWSEN_SHIFT   (23U)
#define	FB_CSCR_SWSEN(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
#define	FB_CSCR_SWS_MASK   (0xFC000000U)
#define	FB_CSCR_SWS_SHIFT   (26U)
#define	FB_CSCR_SWS(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)

CSCR - Chip Select Control Register
#define	FB_CSCR_COUNT   (6U)

CSPMCR - Chip Select port Multiplexing Control Register
#define	FB_CSPMCR_GROUP5_MASK   (0xF000U)
#define	FB_CSPMCR_GROUP5_SHIFT   (12U)
#define	FB_CSPMCR_GROUP5(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
#define	FB_CSPMCR_GROUP4_MASK   (0xF0000U)
#define	FB_CSPMCR_GROUP4_SHIFT   (16U)
#define	FB_CSPMCR_GROUP4(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
#define	FB_CSPMCR_GROUP3_MASK   (0xF00000U)
#define	FB_CSPMCR_GROUP3_SHIFT   (20U)
#define	FB_CSPMCR_GROUP3(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
#define	FB_CSPMCR_GROUP2_MASK   (0xF000000U)
#define	FB_CSPMCR_GROUP2_SHIFT   (24U)
#define	FB_CSPMCR_GROUP2(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
#define	FB_CSPMCR_GROUP1_MASK   (0xF0000000U)
#define	FB_CSPMCR_GROUP1_SHIFT   (28U)
#define	FB_CSPMCR_GROUP1(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
#define	FB_CSPMCR_GROUP5_MASK   0xF000u
#define	FB_CSPMCR_GROUP5_SHIFT   12
#define	FB_CSPMCR_GROUP5(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
#define	FB_CSPMCR_GROUP4_MASK   0xF0000u
#define	FB_CSPMCR_GROUP4_SHIFT   16
#define	FB_CSPMCR_GROUP4(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
#define	FB_CSPMCR_GROUP3_MASK   0xF00000u
#define	FB_CSPMCR_GROUP3_SHIFT   20
#define	FB_CSPMCR_GROUP3(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
#define	FB_CSPMCR_GROUP2_MASK   0xF000000u
#define	FB_CSPMCR_GROUP2_SHIFT   24
#define	FB_CSPMCR_GROUP2(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
#define	FB_CSPMCR_GROUP1_MASK   0xF0000000u
#define	FB_CSPMCR_GROUP1_SHIFT   28
#define	FB_CSPMCR_GROUP1(x)   (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
#define	FB_CSPMCR_GROUP5_MASK   (0xF000U)
#define	FB_CSPMCR_GROUP5_SHIFT   (12U)
#define	FB_CSPMCR_GROUP5(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
#define	FB_CSPMCR_GROUP4_MASK   (0xF0000U)
#define	FB_CSPMCR_GROUP4_SHIFT   (16U)
#define	FB_CSPMCR_GROUP4(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
#define	FB_CSPMCR_GROUP3_MASK   (0xF00000U)
#define	FB_CSPMCR_GROUP3_SHIFT   (20U)
#define	FB_CSPMCR_GROUP3(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
#define	FB_CSPMCR_GROUP2_MASK   (0xF000000U)
#define	FB_CSPMCR_GROUP2_SHIFT   (24U)
#define	FB_CSPMCR_GROUP2(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
#define	FB_CSPMCR_GROUP1_MASK   (0xF0000000U)
#define	FB_CSPMCR_GROUP1_SHIFT   (28U)
#define	FB_CSPMCR_GROUP1(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
#define	FB_CSPMCR_GROUP5_MASK   (0xF000U)
#define	FB_CSPMCR_GROUP5_SHIFT   (12U)
#define	FB_CSPMCR_GROUP5(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
#define	FB_CSPMCR_GROUP4_MASK   (0xF0000U)
#define	FB_CSPMCR_GROUP4_SHIFT   (16U)
#define	FB_CSPMCR_GROUP4(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
#define	FB_CSPMCR_GROUP3_MASK   (0xF00000U)
#define	FB_CSPMCR_GROUP3_SHIFT   (20U)
#define	FB_CSPMCR_GROUP3(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
#define	FB_CSPMCR_GROUP2_MASK   (0xF000000U)
#define	FB_CSPMCR_GROUP2_SHIFT   (24U)
#define	FB_CSPMCR_GROUP2(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
#define	FB_CSPMCR_GROUP1_MASK   (0xF0000000U)
#define	FB_CSPMCR_GROUP1_SHIFT   (28U)
#define	FB_CSPMCR_GROUP1(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
#define	FB_CSPMCR_GROUP5_MASK   (0xF000U)
#define	FB_CSPMCR_GROUP5_SHIFT   (12U)
#define	FB_CSPMCR_GROUP5(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
#define	FB_CSPMCR_GROUP4_MASK   (0xF0000U)
#define	FB_CSPMCR_GROUP4_SHIFT   (16U)
#define	FB_CSPMCR_GROUP4(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
#define	FB_CSPMCR_GROUP3_MASK   (0xF00000U)
#define	FB_CSPMCR_GROUP3_SHIFT   (20U)
#define	FB_CSPMCR_GROUP3(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
#define	FB_CSPMCR_GROUP2_MASK   (0xF000000U)
#define	FB_CSPMCR_GROUP2_SHIFT   (24U)
#define	FB_CSPMCR_GROUP2(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
#define	FB_CSPMCR_GROUP1_MASK   (0xF0000000U)
#define	FB_CSPMCR_GROUP1_SHIFT   (28U)
#define	FB_CSPMCR_GROUP1(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
#define	FB_CSPMCR_GROUP5_MASK   (0xF000U)
#define	FB_CSPMCR_GROUP5_SHIFT   (12U)
#define	FB_CSPMCR_GROUP5(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
#define	FB_CSPMCR_GROUP4_MASK   (0xF0000U)
#define	FB_CSPMCR_GROUP4_SHIFT   (16U)
#define	FB_CSPMCR_GROUP4(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
#define	FB_CSPMCR_GROUP3_MASK   (0xF00000U)
#define	FB_CSPMCR_GROUP3_SHIFT   (20U)
#define	FB_CSPMCR_GROUP3(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
#define	FB_CSPMCR_GROUP2_MASK   (0xF000000U)
#define	FB_CSPMCR_GROUP2_SHIFT   (24U)
#define	FB_CSPMCR_GROUP2(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
#define	FB_CSPMCR_GROUP1_MASK   (0xF0000000U)
#define	FB_CSPMCR_GROUP1_SHIFT   (28U)
#define	FB_CSPMCR_GROUP1(x)   (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)

Macro Definition Documentation

FB

#define FB   ((FB_Type *)FB_BASE)

Peripheral FB base pointer

FB_BASE

#define FB_BASE   (0x4000C000u)

Peripheral FB base address

FB_BASE_ADDRS

#define FB_BASE_ADDRS   { FB_BASE }

Array initializer of FB peripheral base addresses

FB_BASE_PTRS

#define FB_BASE_PTRS   { FB }

Array initializer of FB peripheral base pointers

FB_CSCR_AA [1/5]

#define FB_CSCR_AA

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)

AA - Auto-Acknowledge Enable 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.

FB_CSCR_AA [2/5]

#define FB_CSCR_AA

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)

AA - Auto-Acknowledge Enable 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.

FB_CSCR_AA [3/5]

#define FB_CSCR_AA

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)

AA - Auto-Acknowledge Enable 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.

FB_CSCR_AA [4/5]

#define FB_CSCR_AA

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)

AA - Auto-Acknowledge Enable 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.

FB_CSCR_AA [5/5]

#define FB_CSCR_AA

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)

AA - Auto-Acknowledge Enable 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.

FB_CSCR_ASET [1/6]

#define FB_CSCR_ASET

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)

ASET - Address Setup 0b00..Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). 0b01..Assert FB_CSn on the second rising clock edge after the address is asserted. 0b10..Assert FB_CSn on the third rising clock edge after the address is asserted. 0b11..Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).

FB_CSCR_ASET [2/6]

#define FB_CSCR_ASET

(

x

)

(((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)

ASET - Address Setup 0b00..Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). 0b01..Assert FB_CSn on the second rising clock edge after the address is asserted. 0b10..Assert FB_CSn on the third rising clock edge after the address is asserted. 0b11..Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).

FB_CSCR_ASET [3/6]

#define FB_CSCR_ASET

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)

ASET - Address Setup 0b00..Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). 0b01..Assert FB_CSn on the second rising clock edge after the address is asserted. 0b10..Assert FB_CSn on the third rising clock edge after the address is asserted. 0b11..Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).

FB_CSCR_ASET [4/6]

#define FB_CSCR_ASET

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)

ASET - Address Setup 0b00..Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). 0b01..Assert FB_CSn on the second rising clock edge after the address is asserted. 0b10..Assert FB_CSn on the third rising clock edge after the address is asserted. 0b11..Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).

FB_CSCR_ASET [5/6]

#define FB_CSCR_ASET

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)

ASET - Address Setup 0b00..Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). 0b01..Assert FB_CSn on the second rising clock edge after the address is asserted. 0b10..Assert FB_CSn on the third rising clock edge after the address is asserted. 0b11..Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).

FB_CSCR_ASET [6/6]

#define FB_CSCR_ASET

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)

ASET - Address Setup 0b00..Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ). 0b01..Assert FB_CSn on the second rising clock edge after the address is asserted. 0b10..Assert FB_CSn on the third rising clock edge after the address is asserted. 0b11..Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).

FB_CSCR_BEM [1/5]

#define FB_CSCR_BEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)

BEM - Byte-Enable Mode 0b0..FB_BE is asserted for data write only. 0b1..FB_BE is asserted for data read and write accesses.

FB_CSCR_BEM [2/5]

#define FB_CSCR_BEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)

BEM - Byte-Enable Mode 0b0..FB_BE is asserted for data write only. 0b1..FB_BE is asserted for data read and write accesses.

FB_CSCR_BEM [3/5]

#define FB_CSCR_BEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)

BEM - Byte-Enable Mode 0b0..FB_BE is asserted for data write only. 0b1..FB_BE is asserted for data read and write accesses.

FB_CSCR_BEM [4/5]

#define FB_CSCR_BEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)

BEM - Byte-Enable Mode 0b0..FB_BE is asserted for data write only. 0b1..FB_BE is asserted for data read and write accesses.

FB_CSCR_BEM [5/5]

#define FB_CSCR_BEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)

BEM - Byte-Enable Mode 0b0..FB_BE is asserted for data write only. 0b1..FB_BE is asserted for data read and write accesses.

FB_CSCR_BLS [1/5]

#define FB_CSCR_BLS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)

BLS - Byte-Lane Shift 0b0..Not shifted. Data is left-aligned on FB_AD. 0b1..Shifted. Data is right-aligned on FB_AD.

FB_CSCR_BLS [2/5]

#define FB_CSCR_BLS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)

BLS - Byte-Lane Shift 0b0..Not shifted. Data is left-aligned on FB_AD. 0b1..Shifted. Data is right-aligned on FB_AD.

FB_CSCR_BLS [3/5]

#define FB_CSCR_BLS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)

BLS - Byte-Lane Shift 0b0..Not shifted. Data is left-aligned on FB_AD. 0b1..Shifted. Data is right-aligned on FB_AD.

FB_CSCR_BLS [4/5]

#define FB_CSCR_BLS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)

BLS - Byte-Lane Shift 0b0..Not shifted. Data is left-aligned on FB_AD. 0b1..Shifted. Data is right-aligned on FB_AD.

FB_CSCR_BLS [5/5]

#define FB_CSCR_BLS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)

BLS - Byte-Lane Shift 0b0..Not shifted. Data is left-aligned on FB_AD. 0b1..Shifted. Data is right-aligned on FB_AD.

FB_CSCR_BSTR [1/5]

#define FB_CSCR_BSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)

BSTR - Burst-Read Enable 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.

FB_CSCR_BSTR [2/5]

#define FB_CSCR_BSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)

BSTR - Burst-Read Enable 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.

FB_CSCR_BSTR [3/5]

#define FB_CSCR_BSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)

BSTR - Burst-Read Enable 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.

FB_CSCR_BSTR [4/5]

#define FB_CSCR_BSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)

BSTR - Burst-Read Enable 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.

FB_CSCR_BSTR [5/5]

#define FB_CSCR_BSTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)

BSTR - Burst-Read Enable 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.

FB_CSCR_BSTW [1/5]

#define FB_CSCR_BSTW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)

BSTW - Burst-Write Enable 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.

FB_CSCR_BSTW [2/5]

#define FB_CSCR_BSTW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)

BSTW - Burst-Write Enable 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.

FB_CSCR_BSTW [3/5]

#define FB_CSCR_BSTW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)

BSTW - Burst-Write Enable 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.

FB_CSCR_BSTW [4/5]

#define FB_CSCR_BSTW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)

BSTW - Burst-Write Enable 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.

FB_CSCR_BSTW [5/5]

#define FB_CSCR_BSTW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)

BSTW - Burst-Write Enable 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.

FB_CSCR_EXTS [1/5]

#define FB_CSCR_EXTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)

EXTS 0b0..Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. 0b1..Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.

FB_CSCR_EXTS [2/5]

#define FB_CSCR_EXTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)

EXTS 0b0..Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. 0b1..Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.

FB_CSCR_EXTS [3/5]

#define FB_CSCR_EXTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)

EXTS 0b0..Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. 0b1..Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.

FB_CSCR_EXTS [4/5]

#define FB_CSCR_EXTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)

EXTS 0b0..Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. 0b1..Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.

FB_CSCR_EXTS [5/5]

#define FB_CSCR_EXTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)

EXTS 0b0..Disabled. FB_TS /FB_ALE asserts for one bus clock cycle. 0b1..Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.

FB_CSCR_PS [1/6]

#define FB_CSCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)

PS - Port Size 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.

FB_CSCR_PS [2/6]

#define FB_CSCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)

PS - Port Size 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.

FB_CSCR_PS [3/6]

#define FB_CSCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)

PS - Port Size 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.

FB_CSCR_PS [4/6]

#define FB_CSCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)

PS - Port Size 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.

FB_CSCR_PS [5/6]

#define FB_CSCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)

PS - Port Size 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.

FB_CSCR_PS [6/6]

#define FB_CSCR_PS

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)

PS - Port Size 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b. 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.

FB_CSCR_RDAH [1/6]

#define FB_CSCR_RDAH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)

RDAH - Read Address Hold or Deselect 0b00..When AA is 0b, 1 cycle. When AA is 1b, 0 cycles. 0b01..When AA is 0b, 2 cycles. When AA is 1b, 1 cycle. 0b10..When AA is 0b, 3 cycles. When AA is 1b, 2 cycles. 0b11..When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.

RDAH - Read Address Hold or Deselect 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.

FB_CSCR_RDAH [2/6]

#define FB_CSCR_RDAH

(

x

)

(((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)

RDAH - Read Address Hold or Deselect 0b00..When AA is 0b, 1 cycle. When AA is 1b, 0 cycles. 0b01..When AA is 0b, 2 cycles. When AA is 1b, 1 cycle. 0b10..When AA is 0b, 3 cycles. When AA is 1b, 2 cycles. 0b11..When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.

RDAH - Read Address Hold or Deselect 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.

FB_CSCR_RDAH [3/6]

#define FB_CSCR_RDAH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)

RDAH - Read Address Hold or Deselect 0b00..When AA is 0b, 1 cycle. When AA is 1b, 0 cycles. 0b01..When AA is 0b, 2 cycles. When AA is 1b, 1 cycle. 0b10..When AA is 0b, 3 cycles. When AA is 1b, 2 cycles. 0b11..When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.

RDAH - Read Address Hold or Deselect 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.

FB_CSCR_RDAH [4/6]

#define FB_CSCR_RDAH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)

RDAH - Read Address Hold or Deselect 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.

FB_CSCR_RDAH [5/6]

#define FB_CSCR_RDAH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)

RDAH - Read Address Hold or Deselect 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.

FB_CSCR_RDAH [6/6]

#define FB_CSCR_RDAH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)

RDAH - Read Address Hold or Deselect 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.

FB_CSCR_SWSEN [1/5]

#define FB_CSCR_SWSEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)

SWSEN - Secondary Wait State Enable 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.

FB_CSCR_SWSEN [2/5]

#define FB_CSCR_SWSEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)

SWSEN - Secondary Wait State Enable 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.

FB_CSCR_SWSEN [3/5]

#define FB_CSCR_SWSEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)

SWSEN - Secondary Wait State Enable 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.

FB_CSCR_SWSEN [4/5]

#define FB_CSCR_SWSEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)

SWSEN - Secondary Wait State Enable 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.

FB_CSCR_SWSEN [5/5]

#define FB_CSCR_SWSEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)

SWSEN - Secondary Wait State Enable 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.

FB_CSCR_WRAH [1/6]

#define FB_CSCR_WRAH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)

WRAH - Write Address Hold or Deselect 0b00..1 cycle (default for all but FB_CS0 ) 0b01..2 cycles 0b10..3 cycles 0b11..4 cycles (default for FB_CS0 )

FB_CSCR_WRAH [2/6]

#define FB_CSCR_WRAH

(

x

)

(((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)

WRAH - Write Address Hold or Deselect 0b00..1 cycle (default for all but FB_CS0 ) 0b01..2 cycles 0b10..3 cycles 0b11..4 cycles (default for FB_CS0 )

FB_CSCR_WRAH [3/6]

#define FB_CSCR_WRAH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)

WRAH - Write Address Hold or Deselect 0b00..1 cycle (default for all but FB_CS0 ) 0b01..2 cycles 0b10..3 cycles 0b11..4 cycles (default for FB_CS0 )

FB_CSCR_WRAH [4/6]

#define FB_CSCR_WRAH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)

WRAH - Write Address Hold or Deselect 0b00..1 cycle (default for all but FB_CS0 ) 0b01..2 cycles 0b10..3 cycles 0b11..4 cycles (default for FB_CS0 )

FB_CSCR_WRAH [5/6]

#define FB_CSCR_WRAH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)

WRAH - Write Address Hold or Deselect 0b00..1 cycle (default for all but FB_CS0 ) 0b01..2 cycles 0b10..3 cycles 0b11..4 cycles (default for FB_CS0 )

FB_CSCR_WRAH [6/6]

#define FB_CSCR_WRAH

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)

WRAH - Write Address Hold or Deselect 0b00..1 cycle (default for all but FB_CS0 ) 0b01..2 cycles 0b10..3 cycles 0b11..4 cycles (default for FB_CS0 )

FB_CSMR_BAM [1/6]

#define FB_CSMR_BAM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)

BAM - Base Address Mask 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode. 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.

FB_CSMR_BAM [2/6]

#define FB_CSMR_BAM

(

x

)

(((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)

BAM - Base Address Mask 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode. 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.

FB_CSMR_BAM [3/6]

#define FB_CSMR_BAM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)

BAM - Base Address Mask 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode. 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.

FB_CSMR_BAM [4/6]

#define FB_CSMR_BAM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)

BAM - Base Address Mask 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode. 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.

FB_CSMR_BAM [5/6]

#define FB_CSMR_BAM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)

BAM - Base Address Mask 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode. 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.

FB_CSMR_BAM [6/6]

#define FB_CSMR_BAM

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)

BAM - Base Address Mask 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode. 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.

FB_CSMR_V [1/5]

#define FB_CSMR_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)

V - Valid 0b0..Chip-select is invalid. 0b1..Chip-select is valid.

FB_CSMR_V [2/5]

#define FB_CSMR_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)

V - Valid 0b0..Chip-select is invalid. 0b1..Chip-select is valid.

FB_CSMR_V [3/5]

#define FB_CSMR_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)

V - Valid 0b0..Chip-select is invalid. 0b1..Chip-select is valid.

FB_CSMR_V [4/5]

#define FB_CSMR_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)

V - Valid 0b0..Chip-select is invalid. 0b1..Chip-select is valid.

FB_CSMR_V [5/5]

#define FB_CSMR_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)

V - Valid 0b0..Chip-select is invalid. 0b1..Chip-select is valid.

FB_CSMR_WP [1/5]

#define FB_CSMR_WP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)

WP - Write Protect 0b0..Write accesses are allowed. 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.

FB_CSMR_WP [2/5]

#define FB_CSMR_WP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)

WP - Write Protect 0b0..Write accesses are allowed. 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.

FB_CSMR_WP [3/5]

#define FB_CSMR_WP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)

WP - Write Protect 0b0..Write accesses are allowed. 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.

FB_CSMR_WP [4/5]

#define FB_CSMR_WP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)

WP - Write Protect 0b0..Write accesses are allowed. 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.

FB_CSMR_WP [5/5]

#define FB_CSMR_WP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)

WP - Write Protect 0b0..Write accesses are allowed. 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.

FB_CSPMCR_GROUP1 [1/6]

#define FB_CSPMCR_GROUP1

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)

GROUP1 - FlexBus Signal Group 1 Multiplex control 0b0000..FB_ALE 0b0001..FB_CS1 0b0010..FB_TS

FB_CSPMCR_GROUP1 [2/6]

#define FB_CSPMCR_GROUP1

(

x

)

(((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)

GROUP1 - FlexBus Signal Group 1 Multiplex control 0b0000..FB_ALE 0b0001..FB_CS1 0b0010..FB_TS

FB_CSPMCR_GROUP1 [3/6]

#define FB_CSPMCR_GROUP1

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)

GROUP1 - FlexBus Signal Group 1 Multiplex control 0b0000..FB_ALE 0b0001..FB_CS1 0b0010..FB_TS

FB_CSPMCR_GROUP1 [4/6]

#define FB_CSPMCR_GROUP1

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)

GROUP1 - FlexBus Signal Group 1 Multiplex control 0b0000..FB_ALE 0b0001..FB_CS1 0b0010..FB_TS

FB_CSPMCR_GROUP1 [5/6]

#define FB_CSPMCR_GROUP1

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)

GROUP1 - FlexBus Signal Group 1 Multiplex control 0b0000..FB_ALE 0b0001..FB_CS1 0b0010..FB_TS

FB_CSPMCR_GROUP1 [6/6]

#define FB_CSPMCR_GROUP1

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)

GROUP1 - FlexBus Signal Group 1 Multiplex control 0b0000..FB_ALE 0b0001..FB_CS1 0b0010..FB_TS

FB_CSPMCR_GROUP2 [1/6]

#define FB_CSPMCR_GROUP2

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)

GROUP2 - FlexBus Signal Group 2 Multiplex control 0b0000..FB_CS4 0b0001..FB_TSIZ0 0b0010..FB_BE_31_24

FB_CSPMCR_GROUP2 [2/6]

#define FB_CSPMCR_GROUP2

(

x

)

(((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)

GROUP2 - FlexBus Signal Group 2 Multiplex control 0b0000..FB_CS4 0b0001..FB_TSIZ0 0b0010..FB_BE_31_24

FB_CSPMCR_GROUP2 [3/6]

#define FB_CSPMCR_GROUP2

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)

GROUP2 - FlexBus Signal Group 2 Multiplex control 0b0000..FB_CS4 0b0001..FB_TSIZ0 0b0010..FB_BE_31_24

FB_CSPMCR_GROUP2 [4/6]

#define FB_CSPMCR_GROUP2

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)

GROUP2 - FlexBus Signal Group 2 Multiplex control 0b0000..FB_CS4 0b0001..FB_TSIZ0 0b0010..FB_BE_31_24

FB_CSPMCR_GROUP2 [5/6]

#define FB_CSPMCR_GROUP2

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)

GROUP2 - FlexBus Signal Group 2 Multiplex control 0b0000..FB_CS4 0b0001..FB_TSIZ0 0b0010..FB_BE_31_24

FB_CSPMCR_GROUP2 [6/6]

#define FB_CSPMCR_GROUP2

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)

GROUP2 - FlexBus Signal Group 2 Multiplex control 0b0000..FB_CS4 0b0001..FB_TSIZ0 0b0010..FB_BE_31_24

FB_CSPMCR_GROUP3 [1/6]

#define FB_CSPMCR_GROUP3

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)

GROUP3 - FlexBus Signal Group 3 Multiplex control 0b0000..FB_CS5 0b0001..FB_TSIZ1 0b0010..FB_BE_23_16

FB_CSPMCR_GROUP3 [2/6]

#define FB_CSPMCR_GROUP3

(

x

)

(((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)

GROUP3 - FlexBus Signal Group 3 Multiplex control 0b0000..FB_CS5 0b0001..FB_TSIZ1 0b0010..FB_BE_23_16

FB_CSPMCR_GROUP3 [3/6]

#define FB_CSPMCR_GROUP3

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)

GROUP3 - FlexBus Signal Group 3 Multiplex control 0b0000..FB_CS5 0b0001..FB_TSIZ1 0b0010..FB_BE_23_16

FB_CSPMCR_GROUP3 [4/6]

#define FB_CSPMCR_GROUP3

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)

GROUP3 - FlexBus Signal Group 3 Multiplex control 0b0000..FB_CS5 0b0001..FB_TSIZ1 0b0010..FB_BE_23_16

FB_CSPMCR_GROUP3 [5/6]

#define FB_CSPMCR_GROUP3

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)

GROUP3 - FlexBus Signal Group 3 Multiplex control 0b0000..FB_CS5 0b0001..FB_TSIZ1 0b0010..FB_BE_23_16

FB_CSPMCR_GROUP3 [6/6]

#define FB_CSPMCR_GROUP3

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)

GROUP3 - FlexBus Signal Group 3 Multiplex control 0b0000..FB_CS5 0b0001..FB_TSIZ1 0b0010..FB_BE_23_16

FB_CSPMCR_GROUP4 [1/6]

#define FB_CSPMCR_GROUP4

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)

GROUP4 - FlexBus Signal Group 4 Multiplex control 0b0000..FB_TBST 0b0001..FB_CS2 0b0010..FB_BE_15_8

FB_CSPMCR_GROUP4 [2/6]

#define FB_CSPMCR_GROUP4

(

x

)

(((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)

GROUP4 - FlexBus Signal Group 4 Multiplex control 0b0000..FB_TBST 0b0001..FB_CS2 0b0010..FB_BE_15_8

FB_CSPMCR_GROUP4 [3/6]

#define FB_CSPMCR_GROUP4

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)

GROUP4 - FlexBus Signal Group 4 Multiplex control 0b0000..FB_TBST 0b0001..FB_CS2 0b0010..FB_BE_15_8

FB_CSPMCR_GROUP4 [4/6]

#define FB_CSPMCR_GROUP4

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)

GROUP4 - FlexBus Signal Group 4 Multiplex control 0b0000..FB_TBST 0b0001..FB_CS2 0b0010..FB_BE_15_8

FB_CSPMCR_GROUP4 [5/6]

#define FB_CSPMCR_GROUP4

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)

GROUP4 - FlexBus Signal Group 4 Multiplex control 0b0000..FB_TBST 0b0001..FB_CS2 0b0010..FB_BE_15_8

FB_CSPMCR_GROUP4 [6/6]

#define FB_CSPMCR_GROUP4

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)

GROUP4 - FlexBus Signal Group 4 Multiplex control 0b0000..FB_TBST 0b0001..FB_CS2 0b0010..FB_BE_15_8

FB_CSPMCR_GROUP5 [1/6]

#define FB_CSPMCR_GROUP5

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)

GROUP5 - FlexBus Signal Group 5 Multiplex control 0b0000..FB_TA 0b0001..FB_CS3 . You must also write 1b to CSCR[AA]. 0b0010..FB_BE_7_0 . You must also write 1b to CSCR[AA].

FB_CSPMCR_GROUP5 [2/6]

#define FB_CSPMCR_GROUP5

(

x

)

(((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)

GROUP5 - FlexBus Signal Group 5 Multiplex control 0b0000..FB_TA 0b0001..FB_CS3 . You must also write 1b to CSCR[AA]. 0b0010..FB_BE_7_0 . You must also write 1b to CSCR[AA].

FB_CSPMCR_GROUP5 [3/6]

#define FB_CSPMCR_GROUP5

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)

GROUP5 - FlexBus Signal Group 5 Multiplex control 0b0000..FB_TA 0b0001..FB_CS3 . You must also write 1b to CSCR[AA]. 0b0010..FB_BE_7_0 . You must also write 1b to CSCR[AA].

FB_CSPMCR_GROUP5 [4/6]

#define FB_CSPMCR_GROUP5

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)

GROUP5 - FlexBus Signal Group 5 Multiplex control 0b0000..FB_TA 0b0001..FB_CS3 . You must also write 1b to CSCR[AA]. 0b0010..FB_BE_7_0 . You must also write 1b to CSCR[AA].

FB_CSPMCR_GROUP5 [5/6]

#define FB_CSPMCR_GROUP5

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)

GROUP5 - FlexBus Signal Group 5 Multiplex control 0b0000..FB_TA 0b0001..FB_CS3 . You must also write 1b to CSCR[AA]. 0b0010..FB_BE_7_0 . You must also write 1b to CSCR[AA].

FB_CSPMCR_GROUP5 [6/6]

#define FB_CSPMCR_GROUP5

(

x

)

(((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)

GROUP5 - FlexBus Signal Group 5 Multiplex control 0b0000..FB_TA 0b0001..FB_CS3 . You must also write 1b to CSCR[AA]. 0b0010..FB_BE_7_0 . You must also write 1b to CSCR[AA].