FMC Register Masks

Macros
#define	FMC_BASE   (0x4001F000u)
#define	FMC   ((FMC_Type *)FMC_BASE)
#define	FMC_BASE_ADDRS   { FMC_BASE }
#define	FMC_BASE_PTRS   { FMC }
#define	FMC_TAGVD_valid_MASK   0x1u
#define	FMC_TAGVD_valid_SHIFT   0
#define	FMC_TAGVD_tag_MASK   0x7FFC0u
#define	FMC_TAGVD_tag_SHIFT   6
#define	FMC_TAGVD_tag(x)   (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
#define	FMC_TAGVDW0S_COUNT   (4U)
#define	FMC_TAGVDW1S_COUNT   (4U)
#define	FMC_TAGVDW2S_COUNT   (4U)
#define	FMC_TAGVDW3S_COUNT   (4U)
#define	FMC_DATA_U_COUNT   (4U)
#define	FMC_DATA_U_COUNT2   (4U)
#define	FMC_DATA_L_COUNT   (4U)
#define	FMC_DATA_L_COUNT2   (4U)
#define	FMC_TAGVDW0S_COUNT   (4U)
#define	FMC_TAGVDW1S_COUNT   (4U)
#define	FMC_TAGVDW2S_COUNT   (4U)
#define	FMC_TAGVDW3S_COUNT   (4U)
#define	FMC_DATA_UM_COUNT   (4U)
#define	FMC_DATA_UM_COUNT2   (4U)
#define	FMC_DATA_MU_COUNT   (4U)
#define	FMC_DATA_MU_COUNT2   (4U)
#define	FMC_DATA_ML_COUNT   (4U)
#define	FMC_DATA_ML_COUNT2   (4U)
#define	FMC_DATA_LM_COUNT   (4U)
#define	FMC_DATA_LM_COUNT2   (4U)
#define	FMC_TAGVDW0S_COUNT   (4U)
#define	FMC_TAGVDW1S_COUNT   (4U)
#define	FMC_TAGVDW2S_COUNT   (4U)
#define	FMC_TAGVDW3S_COUNT   (4U)
#define	FMC_DATA_UM_COUNT   (4U)
#define	FMC_DATA_UM_COUNT2   (4U)
#define	FMC_DATA_MU_COUNT   (4U)
#define	FMC_DATA_MU_COUNT2   (4U)
#define	FMC_DATA_ML_COUNT   (4U)
#define	FMC_DATA_ML_COUNT2   (4U)
#define	FMC_DATA_LM_COUNT   (4U)
#define	FMC_DATA_LM_COUNT2   (4U)

PFAPR - Flash Access Protection Register
#define	FMC_PFAPR_M0AP_MASK   (0x3U)
#define	FMC_PFAPR_M0AP_SHIFT   (0U)
#define	FMC_PFAPR_M0AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
#define	FMC_PFAPR_M1AP_MASK   (0xCU)
#define	FMC_PFAPR_M1AP_SHIFT   (2U)
#define	FMC_PFAPR_M1AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
#define	FMC_PFAPR_M2AP_MASK   (0x30U)
#define	FMC_PFAPR_M2AP_SHIFT   (4U)
#define	FMC_PFAPR_M2AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
#define	FMC_PFAPR_M3AP_MASK   (0xC0U)
#define	FMC_PFAPR_M3AP_SHIFT   (6U)
#define	FMC_PFAPR_M3AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
#define	FMC_PFAPR_M0PFD_MASK   (0x10000U)
#define	FMC_PFAPR_M0PFD_SHIFT   (16U)
#define	FMC_PFAPR_M0PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
#define	FMC_PFAPR_M1PFD_MASK   (0x20000U)
#define	FMC_PFAPR_M1PFD_SHIFT   (17U)
#define	FMC_PFAPR_M1PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
#define	FMC_PFAPR_M2PFD_MASK   (0x40000U)
#define	FMC_PFAPR_M2PFD_SHIFT   (18U)
#define	FMC_PFAPR_M2PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
#define	FMC_PFAPR_M3PFD_MASK   (0x80000U)
#define	FMC_PFAPR_M3PFD_SHIFT   (19U)
#define	FMC_PFAPR_M3PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
#define	FMC_PFAPR_M0AP_MASK   0x3u
#define	FMC_PFAPR_M0AP_SHIFT   0
#define	FMC_PFAPR_M0AP(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
#define	FMC_PFAPR_M1AP_MASK   0xCu
#define	FMC_PFAPR_M1AP_SHIFT   2
#define	FMC_PFAPR_M1AP(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
#define	FMC_PFAPR_M2AP_MASK   0x30u
#define	FMC_PFAPR_M2AP_SHIFT   4
#define	FMC_PFAPR_M2AP(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
#define	FMC_PFAPR_M3AP_MASK   0xC0u
#define	FMC_PFAPR_M3AP_SHIFT   6
#define	FMC_PFAPR_M3AP(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
#define	FMC_PFAPR_M0PFD_MASK   0x10000u
#define	FMC_PFAPR_M0PFD_SHIFT   16
#define	FMC_PFAPR_M1PFD_MASK   0x20000u
#define	FMC_PFAPR_M1PFD_SHIFT   17
#define	FMC_PFAPR_M2PFD_MASK   0x40000u
#define	FMC_PFAPR_M2PFD_SHIFT   18
#define	FMC_PFAPR_M3PFD_MASK   0x80000u
#define	FMC_PFAPR_M3PFD_SHIFT   19
#define	FMC_PFAPR_M0AP_MASK   (0x3U)
#define	FMC_PFAPR_M0AP_SHIFT   (0U)
#define	FMC_PFAPR_M0AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
#define	FMC_PFAPR_M1AP_MASK   (0xCU)
#define	FMC_PFAPR_M1AP_SHIFT   (2U)
#define	FMC_PFAPR_M1AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
#define	FMC_PFAPR_M2AP_MASK   (0x30U)
#define	FMC_PFAPR_M2AP_SHIFT   (4U)
#define	FMC_PFAPR_M2AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
#define	FMC_PFAPR_M3AP_MASK   (0xC0U)
#define	FMC_PFAPR_M3AP_SHIFT   (6U)
#define	FMC_PFAPR_M3AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
#define	FMC_PFAPR_M0PFD_MASK   (0x10000U)
#define	FMC_PFAPR_M0PFD_SHIFT   (16U)
#define	FMC_PFAPR_M0PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
#define	FMC_PFAPR_M1PFD_MASK   (0x20000U)
#define	FMC_PFAPR_M1PFD_SHIFT   (17U)
#define	FMC_PFAPR_M1PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
#define	FMC_PFAPR_M2PFD_MASK   (0x40000U)
#define	FMC_PFAPR_M2PFD_SHIFT   (18U)
#define	FMC_PFAPR_M2PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
#define	FMC_PFAPR_M3PFD_MASK   (0x80000U)
#define	FMC_PFAPR_M3PFD_SHIFT   (19U)
#define	FMC_PFAPR_M3PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
#define	FMC_PFAPR_M0AP_MASK   (0x3U)
#define	FMC_PFAPR_M0AP_SHIFT   (0U)
#define	FMC_PFAPR_M0AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
#define	FMC_PFAPR_M1AP_MASK   (0xCU)
#define	FMC_PFAPR_M1AP_SHIFT   (2U)
#define	FMC_PFAPR_M1AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
#define	FMC_PFAPR_M2AP_MASK   (0x30U)
#define	FMC_PFAPR_M2AP_SHIFT   (4U)
#define	FMC_PFAPR_M2AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
#define	FMC_PFAPR_M3AP_MASK   (0xC0U)
#define	FMC_PFAPR_M3AP_SHIFT   (6U)
#define	FMC_PFAPR_M3AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
#define	FMC_PFAPR_M0PFD_MASK   (0x10000U)
#define	FMC_PFAPR_M0PFD_SHIFT   (16U)
#define	FMC_PFAPR_M0PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
#define	FMC_PFAPR_M1PFD_MASK   (0x20000U)
#define	FMC_PFAPR_M1PFD_SHIFT   (17U)
#define	FMC_PFAPR_M1PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
#define	FMC_PFAPR_M2PFD_MASK   (0x40000U)
#define	FMC_PFAPR_M2PFD_SHIFT   (18U)
#define	FMC_PFAPR_M2PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
#define	FMC_PFAPR_M3PFD_MASK   (0x80000U)
#define	FMC_PFAPR_M3PFD_SHIFT   (19U)
#define	FMC_PFAPR_M3PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
#define	FMC_PFAPR_M0AP_MASK   (0x3U)
#define	FMC_PFAPR_M0AP_SHIFT   (0U)
#define	FMC_PFAPR_M0AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
#define	FMC_PFAPR_M1AP_MASK   (0xCU)
#define	FMC_PFAPR_M1AP_SHIFT   (2U)
#define	FMC_PFAPR_M1AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
#define	FMC_PFAPR_M2AP_MASK   (0x30U)
#define	FMC_PFAPR_M2AP_SHIFT   (4U)
#define	FMC_PFAPR_M2AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
#define	FMC_PFAPR_M3AP_MASK   (0xC0U)
#define	FMC_PFAPR_M3AP_SHIFT   (6U)
#define	FMC_PFAPR_M3AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
#define	FMC_PFAPR_M0PFD_MASK   (0x10000U)
#define	FMC_PFAPR_M0PFD_SHIFT   (16U)
#define	FMC_PFAPR_M0PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
#define	FMC_PFAPR_M1PFD_MASK   (0x20000U)
#define	FMC_PFAPR_M1PFD_SHIFT   (17U)
#define	FMC_PFAPR_M1PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
#define	FMC_PFAPR_M2PFD_MASK   (0x40000U)
#define	FMC_PFAPR_M2PFD_SHIFT   (18U)
#define	FMC_PFAPR_M2PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
#define	FMC_PFAPR_M3PFD_MASK   (0x80000U)
#define	FMC_PFAPR_M3PFD_SHIFT   (19U)
#define	FMC_PFAPR_M3PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
#define	FMC_PFAPR_M0AP_MASK   (0x3U)
#define	FMC_PFAPR_M0AP_SHIFT   (0U)
#define	FMC_PFAPR_M0AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
#define	FMC_PFAPR_M1AP_MASK   (0xCU)
#define	FMC_PFAPR_M1AP_SHIFT   (2U)
#define	FMC_PFAPR_M1AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
#define	FMC_PFAPR_M2AP_MASK   (0x30U)
#define	FMC_PFAPR_M2AP_SHIFT   (4U)
#define	FMC_PFAPR_M2AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
#define	FMC_PFAPR_M3AP_MASK   (0xC0U)
#define	FMC_PFAPR_M3AP_SHIFT   (6U)
#define	FMC_PFAPR_M3AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
#define	FMC_PFAPR_M0PFD_MASK   (0x10000U)
#define	FMC_PFAPR_M0PFD_SHIFT   (16U)
#define	FMC_PFAPR_M0PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
#define	FMC_PFAPR_M1PFD_MASK   (0x20000U)
#define	FMC_PFAPR_M1PFD_SHIFT   (17U)
#define	FMC_PFAPR_M1PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
#define	FMC_PFAPR_M2PFD_MASK   (0x40000U)
#define	FMC_PFAPR_M2PFD_SHIFT   (18U)
#define	FMC_PFAPR_M2PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
#define	FMC_PFAPR_M3PFD_MASK   (0x80000U)
#define	FMC_PFAPR_M3PFD_SHIFT   (19U)
#define	FMC_PFAPR_M3PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)

PFAPR - Flash Access Protection Register
#define	FMC_PFAPR_M4AP_MASK   (0x300U)
#define	FMC_PFAPR_M4AP_SHIFT   (8U)
#define	FMC_PFAPR_M4AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
#define	FMC_PFAPR_M5AP_MASK   (0xC00U)
#define	FMC_PFAPR_M5AP_SHIFT   (10U)
#define	FMC_PFAPR_M5AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
#define	FMC_PFAPR_M6AP_MASK   (0x3000U)
#define	FMC_PFAPR_M6AP_SHIFT   (12U)
#define	FMC_PFAPR_M6AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
#define	FMC_PFAPR_M7AP_MASK   (0xC000U)
#define	FMC_PFAPR_M7AP_SHIFT   (14U)
#define	FMC_PFAPR_M7AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
#define	FMC_PFAPR_M4PFD_MASK   (0x100000U)
#define	FMC_PFAPR_M4PFD_SHIFT   (20U)
#define	FMC_PFAPR_M4PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
#define	FMC_PFAPR_M5PFD_MASK   (0x200000U)
#define	FMC_PFAPR_M5PFD_SHIFT   (21U)
#define	FMC_PFAPR_M5PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
#define	FMC_PFAPR_M6PFD_MASK   (0x400000U)
#define	FMC_PFAPR_M6PFD_SHIFT   (22U)
#define	FMC_PFAPR_M6PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
#define	FMC_PFAPR_M7PFD_MASK   (0x800000U)
#define	FMC_PFAPR_M7PFD_SHIFT   (23U)
#define	FMC_PFAPR_M7PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
#define	FMC_PFAPR_M4AP_MASK   0x300u
#define	FMC_PFAPR_M4AP_SHIFT   8
#define	FMC_PFAPR_M4AP(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
#define	FMC_PFAPR_M5AP_MASK   0xC00u
#define	FMC_PFAPR_M5AP_SHIFT   10
#define	FMC_PFAPR_M5AP(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
#define	FMC_PFAPR_M6AP_MASK   0x3000u
#define	FMC_PFAPR_M6AP_SHIFT   12
#define	FMC_PFAPR_M6AP(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
#define	FMC_PFAPR_M7AP_MASK   0xC000u
#define	FMC_PFAPR_M7AP_SHIFT   14
#define	FMC_PFAPR_M7AP(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
#define	FMC_PFAPR_M4PFD_MASK   0x100000u
#define	FMC_PFAPR_M4PFD_SHIFT   20
#define	FMC_PFAPR_M5PFD_MASK   0x200000u
#define	FMC_PFAPR_M5PFD_SHIFT   21
#define	FMC_PFAPR_M6PFD_MASK   0x400000u
#define	FMC_PFAPR_M6PFD_SHIFT   22
#define	FMC_PFAPR_M7PFD_MASK   0x800000u
#define	FMC_PFAPR_M7PFD_SHIFT   23
#define	FMC_PFAPR_M4AP_MASK   (0x300U)
#define	FMC_PFAPR_M4AP_SHIFT   (8U)
#define	FMC_PFAPR_M4AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
#define	FMC_PFAPR_M5AP_MASK   (0xC00U)
#define	FMC_PFAPR_M5AP_SHIFT   (10U)
#define	FMC_PFAPR_M5AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
#define	FMC_PFAPR_M6AP_MASK   (0x3000U)
#define	FMC_PFAPR_M6AP_SHIFT   (12U)
#define	FMC_PFAPR_M6AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
#define	FMC_PFAPR_M7AP_MASK   (0xC000U)
#define	FMC_PFAPR_M7AP_SHIFT   (14U)
#define	FMC_PFAPR_M7AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
#define	FMC_PFAPR_M4PFD_MASK   (0x100000U)
#define	FMC_PFAPR_M4PFD_SHIFT   (20U)
#define	FMC_PFAPR_M4PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
#define	FMC_PFAPR_M5PFD_MASK   (0x200000U)
#define	FMC_PFAPR_M5PFD_SHIFT   (21U)
#define	FMC_PFAPR_M5PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
#define	FMC_PFAPR_M6PFD_MASK   (0x400000U)
#define	FMC_PFAPR_M6PFD_SHIFT   (22U)
#define	FMC_PFAPR_M6PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
#define	FMC_PFAPR_M7PFD_MASK   (0x800000U)
#define	FMC_PFAPR_M7PFD_SHIFT   (23U)
#define	FMC_PFAPR_M7PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
#define	FMC_PFAPR_M4AP_MASK   (0x300U)
#define	FMC_PFAPR_M4AP_SHIFT   (8U)
#define	FMC_PFAPR_M4AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
#define	FMC_PFAPR_M5AP_MASK   (0xC00U)
#define	FMC_PFAPR_M5AP_SHIFT   (10U)
#define	FMC_PFAPR_M5AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
#define	FMC_PFAPR_M6AP_MASK   (0x3000U)
#define	FMC_PFAPR_M6AP_SHIFT   (12U)
#define	FMC_PFAPR_M6AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
#define	FMC_PFAPR_M7AP_MASK   (0xC000U)
#define	FMC_PFAPR_M7AP_SHIFT   (14U)
#define	FMC_PFAPR_M7AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
#define	FMC_PFAPR_M4PFD_MASK   (0x100000U)
#define	FMC_PFAPR_M4PFD_SHIFT   (20U)
#define	FMC_PFAPR_M4PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
#define	FMC_PFAPR_M5PFD_MASK   (0x200000U)
#define	FMC_PFAPR_M5PFD_SHIFT   (21U)
#define	FMC_PFAPR_M5PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
#define	FMC_PFAPR_M6PFD_MASK   (0x400000U)
#define	FMC_PFAPR_M6PFD_SHIFT   (22U)
#define	FMC_PFAPR_M6PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
#define	FMC_PFAPR_M7PFD_MASK   (0x800000U)
#define	FMC_PFAPR_M7PFD_SHIFT   (23U)
#define	FMC_PFAPR_M7PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
#define	FMC_PFAPR_M4AP_MASK   (0x300U)
#define	FMC_PFAPR_M4AP_SHIFT   (8U)
#define	FMC_PFAPR_M4AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
#define	FMC_PFAPR_M5AP_MASK   (0xC00U)
#define	FMC_PFAPR_M5AP_SHIFT   (10U)
#define	FMC_PFAPR_M5AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
#define	FMC_PFAPR_M6AP_MASK   (0x3000U)
#define	FMC_PFAPR_M6AP_SHIFT   (12U)
#define	FMC_PFAPR_M6AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
#define	FMC_PFAPR_M7AP_MASK   (0xC000U)
#define	FMC_PFAPR_M7AP_SHIFT   (14U)
#define	FMC_PFAPR_M7AP(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
#define	FMC_PFAPR_M4PFD_MASK   (0x100000U)
#define	FMC_PFAPR_M4PFD_SHIFT   (20U)
#define	FMC_PFAPR_M4PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
#define	FMC_PFAPR_M5PFD_MASK   (0x200000U)
#define	FMC_PFAPR_M5PFD_SHIFT   (21U)
#define	FMC_PFAPR_M5PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
#define	FMC_PFAPR_M6PFD_MASK   (0x400000U)
#define	FMC_PFAPR_M6PFD_SHIFT   (22U)
#define	FMC_PFAPR_M6PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
#define	FMC_PFAPR_M7PFD_MASK   (0x800000U)
#define	FMC_PFAPR_M7PFD_SHIFT   (23U)
#define	FMC_PFAPR_M7PFD(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)

PFB0CR - Flash Bank 0 Control Register
#define	FMC_PFB0CR_B0SEBE_MASK   (0x1U)
#define	FMC_PFB0CR_B0SEBE_SHIFT   (0U)
#define	FMC_PFB0CR_B0SEBE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
#define	FMC_PFB0CR_B0ICE_MASK   (0x8U)
#define	FMC_PFB0CR_B0ICE_SHIFT   (3U)
#define	FMC_PFB0CR_B0ICE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
#define	FMC_PFB0CR_B0DCE_MASK   (0x10U)
#define	FMC_PFB0CR_B0DCE_SHIFT   (4U)
#define	FMC_PFB0CR_B0DCE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
#define	FMC_PFB0CR_CRC_MASK   (0xE0U)
#define	FMC_PFB0CR_CRC_SHIFT   (5U)
#define	FMC_PFB0CR_CRC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
#define	FMC_PFB0CR_S_B_INV_MASK   (0x80000U)
#define	FMC_PFB0CR_S_B_INV_SHIFT   (19U)
#define	FMC_PFB0CR_S_B_INV(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
#define	FMC_PFB0CR_CINV_WAY_MASK   (0xF00000U)
#define	FMC_PFB0CR_CINV_WAY_SHIFT   (20U)
#define	FMC_PFB0CR_CINV_WAY(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
#define	FMC_PFB0CR_CLCK_WAY_MASK   (0xF000000U)
#define	FMC_PFB0CR_CLCK_WAY_SHIFT   (24U)
#define	FMC_PFB0CR_CLCK_WAY(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
#define	FMC_PFB0CR_B0SEBE_MASK   0x1u
#define	FMC_PFB0CR_B0SEBE_SHIFT   0
#define	FMC_PFB0CR_B0ICE_MASK   0x8u
#define	FMC_PFB0CR_B0ICE_SHIFT   3
#define	FMC_PFB0CR_B0DCE_MASK   0x10u
#define	FMC_PFB0CR_B0DCE_SHIFT   4
#define	FMC_PFB0CR_CRC_MASK   0xE0u
#define	FMC_PFB0CR_CRC_SHIFT   5
#define	FMC_PFB0CR_CRC(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
#define	FMC_PFB0CR_S_B_INV_MASK   0x80000u
#define	FMC_PFB0CR_S_B_INV_SHIFT   19
#define	FMC_PFB0CR_CINV_WAY_MASK   0xF00000u
#define	FMC_PFB0CR_CINV_WAY_SHIFT   20
#define	FMC_PFB0CR_CINV_WAY(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
#define	FMC_PFB0CR_CLCK_WAY_MASK   0xF000000u
#define	FMC_PFB0CR_CLCK_WAY_SHIFT   24
#define	FMC_PFB0CR_CLCK_WAY(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
#define	FMC_PFB0CR_B0SEBE_MASK   (0x1U)
#define	FMC_PFB0CR_B0SEBE_SHIFT   (0U)
#define	FMC_PFB0CR_B0SEBE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
#define	FMC_PFB0CR_B0ICE_MASK   (0x8U)
#define	FMC_PFB0CR_B0ICE_SHIFT   (3U)
#define	FMC_PFB0CR_B0ICE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
#define	FMC_PFB0CR_B0DCE_MASK   (0x10U)
#define	FMC_PFB0CR_B0DCE_SHIFT   (4U)
#define	FMC_PFB0CR_B0DCE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
#define	FMC_PFB0CR_CRC_MASK   (0xE0U)
#define	FMC_PFB0CR_CRC_SHIFT   (5U)
#define	FMC_PFB0CR_CRC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
#define	FMC_PFB0CR_S_B_INV_MASK   (0x80000U)
#define	FMC_PFB0CR_S_B_INV_SHIFT   (19U)
#define	FMC_PFB0CR_S_B_INV(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
#define	FMC_PFB0CR_CINV_WAY_MASK   (0xF00000U)
#define	FMC_PFB0CR_CINV_WAY_SHIFT   (20U)
#define	FMC_PFB0CR_CINV_WAY(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
#define	FMC_PFB0CR_CLCK_WAY_MASK   (0xF000000U)
#define	FMC_PFB0CR_CLCK_WAY_SHIFT   (24U)
#define	FMC_PFB0CR_CLCK_WAY(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)

PFB0CR - Flash Bank 0 Control Register
#define	FMC_PFB0CR_B0IPE_MASK   (0x2U)
#define	FMC_PFB0CR_B0IPE_SHIFT   (1U)
#define	FMC_PFB0CR_B0IPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
#define	FMC_PFB0CR_B0DPE_MASK   (0x4U)
#define	FMC_PFB0CR_B0DPE_SHIFT   (2U)
#define	FMC_PFB0CR_B0DPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
#define	FMC_PFB0CR_B0MW_MASK   (0x60000U)
#define	FMC_PFB0CR_B0MW_SHIFT   (17U)
#define	FMC_PFB0CR_B0MW(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
#define	FMC_PFB0CR_B0RWSC_MASK   (0xF0000000U)
#define	FMC_PFB0CR_B0RWSC_SHIFT   (28U)
#define	FMC_PFB0CR_B0RWSC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
#define	FMC_PFB0CR_B0IPE_MASK   0x2u
#define	FMC_PFB0CR_B0IPE_SHIFT   1
#define	FMC_PFB0CR_B0DPE_MASK   0x4u
#define	FMC_PFB0CR_B0DPE_SHIFT   2
#define	FMC_PFB0CR_B0MW_MASK   0x60000u
#define	FMC_PFB0CR_B0MW_SHIFT   17
#define	FMC_PFB0CR_B0MW(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
#define	FMC_PFB0CR_B0RWSC_MASK   0xF0000000u
#define	FMC_PFB0CR_B0RWSC_SHIFT   28
#define	FMC_PFB0CR_B0RWSC(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
#define	FMC_PFB0CR_B0IPE_MASK   (0x2U)
#define	FMC_PFB0CR_B0IPE_SHIFT   (1U)
#define	FMC_PFB0CR_B0IPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
#define	FMC_PFB0CR_B0DPE_MASK   (0x4U)
#define	FMC_PFB0CR_B0DPE_SHIFT   (2U)
#define	FMC_PFB0CR_B0DPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
#define	FMC_PFB0CR_B0MW_MASK   (0x60000U)
#define	FMC_PFB0CR_B0MW_SHIFT   (17U)
#define	FMC_PFB0CR_B0MW(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
#define	FMC_PFB0CR_B0RWSC_MASK   (0xF0000000U)
#define	FMC_PFB0CR_B0RWSC_SHIFT   (28U)
#define	FMC_PFB0CR_B0RWSC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
#define	FMC_PFB0CR_B0IPE_MASK   (0x2U)
#define	FMC_PFB0CR_B0IPE_SHIFT   (1U)
#define	FMC_PFB0CR_B0IPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
#define	FMC_PFB0CR_B0DPE_MASK   (0x4U)
#define	FMC_PFB0CR_B0DPE_SHIFT   (2U)
#define	FMC_PFB0CR_B0DPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
#define	FMC_PFB0CR_B0MW_MASK   (0x60000U)
#define	FMC_PFB0CR_B0MW_SHIFT   (17U)
#define	FMC_PFB0CR_B0MW(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
#define	FMC_PFB0CR_S_INV_MASK   (0x80000U)
#define	FMC_PFB0CR_S_INV_SHIFT   (19U)
#define	FMC_PFB0CR_S_INV(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_INV_SHIFT)) & FMC_PFB0CR_S_INV_MASK)
#define	FMC_PFB0CR_B0RWSC_MASK   (0xF0000000U)
#define	FMC_PFB0CR_B0RWSC_SHIFT   (28U)
#define	FMC_PFB0CR_B0RWSC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)

PFB1CR - Flash Bank 1 Control Register
#define	FMC_PFB1CR_B1SEBE_MASK   (0x1U)
#define	FMC_PFB1CR_B1SEBE_SHIFT   (0U)
#define	FMC_PFB1CR_B1SEBE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
#define	FMC_PFB1CR_B1IPE_MASK   (0x2U)
#define	FMC_PFB1CR_B1IPE_SHIFT   (1U)
#define	FMC_PFB1CR_B1IPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
#define	FMC_PFB1CR_B1DPE_MASK   (0x4U)
#define	FMC_PFB1CR_B1DPE_SHIFT   (2U)
#define	FMC_PFB1CR_B1DPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
#define	FMC_PFB1CR_B1ICE_MASK   (0x8U)
#define	FMC_PFB1CR_B1ICE_SHIFT   (3U)
#define	FMC_PFB1CR_B1ICE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
#define	FMC_PFB1CR_B1DCE_MASK   (0x10U)
#define	FMC_PFB1CR_B1DCE_SHIFT   (4U)
#define	FMC_PFB1CR_B1DCE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
#define	FMC_PFB1CR_B1MW_MASK   (0x60000U)
#define	FMC_PFB1CR_B1MW_SHIFT   (17U)
#define	FMC_PFB1CR_B1MW(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
#define	FMC_PFB1CR_B1RWSC_MASK   (0xF0000000U)
#define	FMC_PFB1CR_B1RWSC_SHIFT   (28U)
#define	FMC_PFB1CR_B1RWSC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
#define	FMC_PFB1CR_B1SEBE_MASK   0x1u
#define	FMC_PFB1CR_B1SEBE_SHIFT   0
#define	FMC_PFB1CR_B1IPE_MASK   0x2u
#define	FMC_PFB1CR_B1IPE_SHIFT   1
#define	FMC_PFB1CR_B1DPE_MASK   0x4u
#define	FMC_PFB1CR_B1DPE_SHIFT   2
#define	FMC_PFB1CR_B1ICE_MASK   0x8u
#define	FMC_PFB1CR_B1ICE_SHIFT   3
#define	FMC_PFB1CR_B1DCE_MASK   0x10u
#define	FMC_PFB1CR_B1DCE_SHIFT   4
#define	FMC_PFB1CR_B1MW_MASK   0x60000u
#define	FMC_PFB1CR_B1MW_SHIFT   17
#define	FMC_PFB1CR_B1MW(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
#define	FMC_PFB1CR_B1RWSC_MASK   0xF0000000u
#define	FMC_PFB1CR_B1RWSC_SHIFT   28
#define	FMC_PFB1CR_B1RWSC(x)   (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
#define	FMC_PFB1CR_B1SEBE_MASK   (0x1U)
#define	FMC_PFB1CR_B1SEBE_SHIFT   (0U)
#define	FMC_PFB1CR_B1SEBE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
#define	FMC_PFB1CR_B1IPE_MASK   (0x2U)
#define	FMC_PFB1CR_B1IPE_SHIFT   (1U)
#define	FMC_PFB1CR_B1IPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
#define	FMC_PFB1CR_B1DPE_MASK   (0x4U)
#define	FMC_PFB1CR_B1DPE_SHIFT   (2U)
#define	FMC_PFB1CR_B1DPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
#define	FMC_PFB1CR_B1ICE_MASK   (0x8U)
#define	FMC_PFB1CR_B1ICE_SHIFT   (3U)
#define	FMC_PFB1CR_B1ICE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
#define	FMC_PFB1CR_B1DCE_MASK   (0x10U)
#define	FMC_PFB1CR_B1DCE_SHIFT   (4U)
#define	FMC_PFB1CR_B1DCE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
#define	FMC_PFB1CR_B1MW_MASK   (0x60000U)
#define	FMC_PFB1CR_B1MW_SHIFT   (17U)
#define	FMC_PFB1CR_B1MW(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
#define	FMC_PFB1CR_B1RWSC_MASK   (0xF0000000U)
#define	FMC_PFB1CR_B1RWSC_SHIFT   (28U)
#define	FMC_PFB1CR_B1RWSC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)

TAGVD - Cache Tag Storage
#define	FMC_TAGVD_valid_MASK   (0x1U)
#define	FMC_TAGVD_valid_SHIFT   (0U)
#define	FMC_TAGVD_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_valid_SHIFT)) & FMC_TAGVD_valid_MASK)
#define	FMC_TAGVD_tag_MASK   (0x7FFC0U)
#define	FMC_TAGVD_tag_SHIFT   (6U)
#define	FMC_TAGVD_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVD_tag_SHIFT)) & FMC_TAGVD_tag_MASK)
#define	FMC_TAGVD_COUNT   (4U)
#define	FMC_TAGVD_COUNT2   (8U)

DATA_U - Cache Data Storage (upper word)
#define	FMC_DATA_U_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_U_data_SHIFT   (0U)
#define	FMC_DATA_U_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
#define	FMC_DATA_U_data_MASK   0xFFFFFFFFu
#define	FMC_DATA_U_data_SHIFT   0
#define	FMC_DATA_U_data(x)   (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
#define	FMC_DATA_U_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_U_data_SHIFT   (0U)
#define	FMC_DATA_U_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)

DATA_U - Cache Data Storage (upper word)
#define	FMC_DATA_U_COUNT   (4U)
#define	FMC_DATA_U_COUNT2   (8U)

DATA_L - Cache Data Storage (lower word)
#define	FMC_DATA_L_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_L_data_SHIFT   (0U)
#define	FMC_DATA_L_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
#define	FMC_DATA_L_data_MASK   0xFFFFFFFFu
#define	FMC_DATA_L_data_SHIFT   0
#define	FMC_DATA_L_data(x)   (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
#define	FMC_DATA_L_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_L_data_SHIFT   (0U)
#define	FMC_DATA_L_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)

DATA_L - Cache Data Storage (lower word)
#define	FMC_DATA_L_COUNT   (4U)
#define	FMC_DATA_L_COUNT2   (8U)

TAGVDW0S - Cache Tag Storage
#define	FMC_TAGVDW0S_valid_MASK   (0x1U)
#define	FMC_TAGVDW0S_valid_SHIFT   (0U)
#define	FMC_TAGVDW0S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
#define	FMC_TAGVDW0S_tag_MASK   (0x7FFE0U)
#define	FMC_TAGVDW0S_tag_SHIFT   (5U)
#define	FMC_TAGVDW0S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
#define	FMC_TAGVDW0S_valid_MASK   (0x1U)
#define	FMC_TAGVDW0S_valid_SHIFT   (0U)
#define	FMC_TAGVDW0S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
#define	FMC_TAGVDW0S_tag_MASK   (0x3FFFC0U)
#define	FMC_TAGVDW0S_tag_SHIFT   (6U)
#define	FMC_TAGVDW0S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
#define	FMC_TAGVDW0S_valid_MASK   (0x1U)
#define	FMC_TAGVDW0S_valid_SHIFT   (0U)
#define	FMC_TAGVDW0S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
#define	FMC_TAGVDW0S_tag_MASK   (0x3FFFC0U)
#define	FMC_TAGVDW0S_tag_SHIFT   (6U)
#define	FMC_TAGVDW0S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)

TAGVDW1S - Cache Tag Storage
#define	FMC_TAGVDW1S_valid_MASK   (0x1U)
#define	FMC_TAGVDW1S_valid_SHIFT   (0U)
#define	FMC_TAGVDW1S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
#define	FMC_TAGVDW1S_tag_MASK   (0x7FFE0U)
#define	FMC_TAGVDW1S_tag_SHIFT   (5U)
#define	FMC_TAGVDW1S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
#define	FMC_TAGVDW1S_valid_MASK   (0x1U)
#define	FMC_TAGVDW1S_valid_SHIFT   (0U)
#define	FMC_TAGVDW1S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
#define	FMC_TAGVDW1S_tag_MASK   (0x3FFFC0U)
#define	FMC_TAGVDW1S_tag_SHIFT   (6U)
#define	FMC_TAGVDW1S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
#define	FMC_TAGVDW1S_valid_MASK   (0x1U)
#define	FMC_TAGVDW1S_valid_SHIFT   (0U)
#define	FMC_TAGVDW1S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
#define	FMC_TAGVDW1S_tag_MASK   (0x3FFFC0U)
#define	FMC_TAGVDW1S_tag_SHIFT   (6U)
#define	FMC_TAGVDW1S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)

TAGVDW2S - Cache Tag Storage
#define	FMC_TAGVDW2S_valid_MASK   (0x1U)
#define	FMC_TAGVDW2S_valid_SHIFT   (0U)
#define	FMC_TAGVDW2S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
#define	FMC_TAGVDW2S_tag_MASK   (0x7FFE0U)
#define	FMC_TAGVDW2S_tag_SHIFT   (5U)
#define	FMC_TAGVDW2S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
#define	FMC_TAGVDW2S_valid_MASK   (0x1U)
#define	FMC_TAGVDW2S_valid_SHIFT   (0U)
#define	FMC_TAGVDW2S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
#define	FMC_TAGVDW2S_tag_MASK   (0x3FFFC0U)
#define	FMC_TAGVDW2S_tag_SHIFT   (6U)
#define	FMC_TAGVDW2S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
#define	FMC_TAGVDW2S_valid_MASK   (0x1U)
#define	FMC_TAGVDW2S_valid_SHIFT   (0U)
#define	FMC_TAGVDW2S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
#define	FMC_TAGVDW2S_tag_MASK   (0x3FFFC0U)
#define	FMC_TAGVDW2S_tag_SHIFT   (6U)
#define	FMC_TAGVDW2S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)

TAGVDW3S - Cache Tag Storage
#define	FMC_TAGVDW3S_valid_MASK   (0x1U)
#define	FMC_TAGVDW3S_valid_SHIFT   (0U)
#define	FMC_TAGVDW3S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
#define	FMC_TAGVDW3S_tag_MASK   (0x7FFE0U)
#define	FMC_TAGVDW3S_tag_SHIFT   (5U)
#define	FMC_TAGVDW3S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
#define	FMC_TAGVDW3S_valid_MASK   (0x1U)
#define	FMC_TAGVDW3S_valid_SHIFT   (0U)
#define	FMC_TAGVDW3S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
#define	FMC_TAGVDW3S_tag_MASK   (0x3FFFC0U)
#define	FMC_TAGVDW3S_tag_SHIFT   (6U)
#define	FMC_TAGVDW3S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
#define	FMC_TAGVDW3S_valid_MASK   (0x1U)
#define	FMC_TAGVDW3S_valid_SHIFT   (0U)
#define	FMC_TAGVDW3S_valid(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
#define	FMC_TAGVDW3S_tag_MASK   (0x3FFFC0U)
#define	FMC_TAGVDW3S_tag_SHIFT   (6U)
#define	FMC_TAGVDW3S_tag(x)   (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)

PFB01CR - Flash Bank 0-1 Control Register
#define	FMC_PFB01CR_RFU_MASK   (0x1U)
#define	FMC_PFB01CR_RFU_SHIFT   (0U)
#define	FMC_PFB01CR_RFU(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_RFU_SHIFT)) & FMC_PFB01CR_RFU_MASK)
#define	FMC_PFB01CR_B0IPE_MASK   (0x2U)
#define	FMC_PFB01CR_B0IPE_SHIFT   (1U)
#define	FMC_PFB01CR_B0IPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)
#define	FMC_PFB01CR_B0DPE_MASK   (0x4U)
#define	FMC_PFB01CR_B0DPE_SHIFT   (2U)
#define	FMC_PFB01CR_B0DPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)
#define	FMC_PFB01CR_B0ICE_MASK   (0x8U)
#define	FMC_PFB01CR_B0ICE_SHIFT   (3U)
#define	FMC_PFB01CR_B0ICE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)
#define	FMC_PFB01CR_B0DCE_MASK   (0x10U)
#define	FMC_PFB01CR_B0DCE_SHIFT   (4U)
#define	FMC_PFB01CR_B0DCE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)
#define	FMC_PFB01CR_CRC_MASK   (0xE0U)
#define	FMC_PFB01CR_CRC_SHIFT   (5U)
#define	FMC_PFB01CR_CRC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)
#define	FMC_PFB01CR_B0MW_MASK   (0x60000U)
#define	FMC_PFB01CR_B0MW_SHIFT   (17U)
#define	FMC_PFB01CR_B0MW(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)
#define	FMC_PFB01CR_S_B_INV_MASK   (0x80000U)
#define	FMC_PFB01CR_S_B_INV_SHIFT   (19U)
#define	FMC_PFB01CR_S_B_INV(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)
#define	FMC_PFB01CR_CINV_WAY_MASK   (0xF00000U)
#define	FMC_PFB01CR_CINV_WAY_SHIFT   (20U)
#define	FMC_PFB01CR_CINV_WAY(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)
#define	FMC_PFB01CR_CLCK_WAY_MASK   (0xF000000U)
#define	FMC_PFB01CR_CLCK_WAY_SHIFT   (24U)
#define	FMC_PFB01CR_CLCK_WAY(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)
#define	FMC_PFB01CR_B0RWSC_MASK   (0xF0000000U)
#define	FMC_PFB01CR_B0RWSC_SHIFT   (28U)
#define	FMC_PFB01CR_B0RWSC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0RWSC_SHIFT)) & FMC_PFB01CR_B0RWSC_MASK)
#define	FMC_PFB01CR_RFU_MASK   (0x1U)
#define	FMC_PFB01CR_RFU_SHIFT   (0U)
#define	FMC_PFB01CR_RFU(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_RFU_SHIFT)) & FMC_PFB01CR_RFU_MASK)
#define	FMC_PFB01CR_B0IPE_MASK   (0x2U)
#define	FMC_PFB01CR_B0IPE_SHIFT   (1U)
#define	FMC_PFB01CR_B0IPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)
#define	FMC_PFB01CR_B0DPE_MASK   (0x4U)
#define	FMC_PFB01CR_B0DPE_SHIFT   (2U)
#define	FMC_PFB01CR_B0DPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)
#define	FMC_PFB01CR_B0ICE_MASK   (0x8U)
#define	FMC_PFB01CR_B0ICE_SHIFT   (3U)
#define	FMC_PFB01CR_B0ICE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)
#define	FMC_PFB01CR_B0DCE_MASK   (0x10U)
#define	FMC_PFB01CR_B0DCE_SHIFT   (4U)
#define	FMC_PFB01CR_B0DCE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)
#define	FMC_PFB01CR_CRC_MASK   (0xE0U)
#define	FMC_PFB01CR_CRC_SHIFT   (5U)
#define	FMC_PFB01CR_CRC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)
#define	FMC_PFB01CR_B0MW_MASK   (0x60000U)
#define	FMC_PFB01CR_B0MW_SHIFT   (17U)
#define	FMC_PFB01CR_B0MW(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)
#define	FMC_PFB01CR_S_B_INV_MASK   (0x80000U)
#define	FMC_PFB01CR_S_B_INV_SHIFT   (19U)
#define	FMC_PFB01CR_S_B_INV(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)
#define	FMC_PFB01CR_CINV_WAY_MASK   (0xF00000U)
#define	FMC_PFB01CR_CINV_WAY_SHIFT   (20U)
#define	FMC_PFB01CR_CINV_WAY(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)
#define	FMC_PFB01CR_CLCK_WAY_MASK   (0xF000000U)
#define	FMC_PFB01CR_CLCK_WAY_SHIFT   (24U)
#define	FMC_PFB01CR_CLCK_WAY(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)
#define	FMC_PFB01CR_B0RWSC_MASK   (0xF0000000U)
#define	FMC_PFB01CR_B0RWSC_SHIFT   (28U)
#define	FMC_PFB01CR_B0RWSC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0RWSC_SHIFT)) & FMC_PFB01CR_B0RWSC_MASK)

PFB23CR - Flash Bank 2-3 Control Register
#define	FMC_PFB23CR_RFU_MASK   (0x1U)
#define	FMC_PFB23CR_RFU_SHIFT   (0U)
#define	FMC_PFB23CR_RFU(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_RFU_SHIFT)) & FMC_PFB23CR_RFU_MASK)
#define	FMC_PFB23CR_B1IPE_MASK   (0x2U)
#define	FMC_PFB23CR_B1IPE_SHIFT   (1U)
#define	FMC_PFB23CR_B1IPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)
#define	FMC_PFB23CR_B1DPE_MASK   (0x4U)
#define	FMC_PFB23CR_B1DPE_SHIFT   (2U)
#define	FMC_PFB23CR_B1DPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)
#define	FMC_PFB23CR_B1ICE_MASK   (0x8U)
#define	FMC_PFB23CR_B1ICE_SHIFT   (3U)
#define	FMC_PFB23CR_B1ICE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)
#define	FMC_PFB23CR_B1DCE_MASK   (0x10U)
#define	FMC_PFB23CR_B1DCE_SHIFT   (4U)
#define	FMC_PFB23CR_B1DCE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)
#define	FMC_PFB23CR_B1MW_MASK   (0x60000U)
#define	FMC_PFB23CR_B1MW_SHIFT   (17U)
#define	FMC_PFB23CR_B1MW(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)
#define	FMC_PFB23CR_B1RWSC_MASK   (0xF0000000U)
#define	FMC_PFB23CR_B1RWSC_SHIFT   (28U)
#define	FMC_PFB23CR_B1RWSC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1RWSC_SHIFT)) & FMC_PFB23CR_B1RWSC_MASK)
#define	FMC_PFB23CR_RFU_MASK   (0x1U)
#define	FMC_PFB23CR_RFU_SHIFT   (0U)
#define	FMC_PFB23CR_RFU(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_RFU_SHIFT)) & FMC_PFB23CR_RFU_MASK)
#define	FMC_PFB23CR_B1IPE_MASK   (0x2U)
#define	FMC_PFB23CR_B1IPE_SHIFT   (1U)
#define	FMC_PFB23CR_B1IPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)
#define	FMC_PFB23CR_B1DPE_MASK   (0x4U)
#define	FMC_PFB23CR_B1DPE_SHIFT   (2U)
#define	FMC_PFB23CR_B1DPE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)
#define	FMC_PFB23CR_B1ICE_MASK   (0x8U)
#define	FMC_PFB23CR_B1ICE_SHIFT   (3U)
#define	FMC_PFB23CR_B1ICE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)
#define	FMC_PFB23CR_B1DCE_MASK   (0x10U)
#define	FMC_PFB23CR_B1DCE_SHIFT   (4U)
#define	FMC_PFB23CR_B1DCE(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)
#define	FMC_PFB23CR_B1MW_MASK   (0x60000U)
#define	FMC_PFB23CR_B1MW_SHIFT   (17U)
#define	FMC_PFB23CR_B1MW(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)
#define	FMC_PFB23CR_B1RWSC_MASK   (0xF0000000U)
#define	FMC_PFB23CR_B1RWSC_SHIFT   (28U)
#define	FMC_PFB23CR_B1RWSC(x)   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1RWSC_SHIFT)) & FMC_PFB23CR_B1RWSC_MASK)

DATA_UM - Cache Data Storage (uppermost word)
#define	FMC_DATA_UM_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_UM_data_SHIFT   (0U)
#define	FMC_DATA_UM_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
#define	FMC_DATA_UM_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_UM_data_SHIFT   (0U)
#define	FMC_DATA_UM_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)

DATA_MU - Cache Data Storage (mid-upper word)
#define	FMC_DATA_MU_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_MU_data_SHIFT   (0U)
#define	FMC_DATA_MU_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
#define	FMC_DATA_MU_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_MU_data_SHIFT   (0U)
#define	FMC_DATA_MU_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)

DATA_ML - Cache Data Storage (mid-lower word)
#define	FMC_DATA_ML_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_ML_data_SHIFT   (0U)
#define	FMC_DATA_ML_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
#define	FMC_DATA_ML_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_ML_data_SHIFT   (0U)
#define	FMC_DATA_ML_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)

DATA_LM - Cache Data Storage (lowermost word)
#define	FMC_DATA_LM_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_LM_data_SHIFT   (0U)
#define	FMC_DATA_LM_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
#define	FMC_DATA_LM_data_MASK   (0xFFFFFFFFU)
#define	FMC_DATA_LM_data_SHIFT   (0U)
#define	FMC_DATA_LM_data(x)   (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)

Macro Definition Documentation

FMC

#define FMC   ((FMC_Type *)FMC_BASE)

Peripheral FMC base pointer

FMC_BASE

#define FMC_BASE   (0x4001F000u)

Peripheral FMC base address

FMC_BASE_ADDRS

#define FMC_BASE_ADDRS   { FMC_BASE }

Array initializer of FMC peripheral base addresses

FMC_BASE_PTRS

#define FMC_BASE_PTRS   { FMC }

Array initializer of FMC peripheral base pointers

FMC_PFAPR_M0AP [1/6]

#define FMC_PFAPR_M0AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)

M0AP - Master 0 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M0AP [2/6]

#define FMC_PFAPR_M0AP

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)

M0AP - Master 0 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M0AP [3/6]

#define FMC_PFAPR_M0AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)

M0AP - Master 0 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M0AP [4/6]

#define FMC_PFAPR_M0AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)

M0AP - Master 0 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M0AP [5/6]

#define FMC_PFAPR_M0AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)

M0AP - Master 0 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M0AP [6/6]

#define FMC_PFAPR_M0AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)

M0AP - Master 0 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M0PFD [1/5]

#define FMC_PFAPR_M0PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)

M0PFD - Master 0 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M0PFD [2/5]

#define FMC_PFAPR_M0PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)

M0PFD - Master 0 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M0PFD [3/5]

#define FMC_PFAPR_M0PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)

M0PFD - Master 0 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M0PFD [4/5]

#define FMC_PFAPR_M0PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)

M0PFD - Master 0 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M0PFD [5/5]

#define FMC_PFAPR_M0PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)

M0PFD - Master 0 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M1AP [1/6]

#define FMC_PFAPR_M1AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)

M1AP - Master 1 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M1AP [2/6]

#define FMC_PFAPR_M1AP

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)

M1AP - Master 1 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M1AP [3/6]

#define FMC_PFAPR_M1AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)

M1AP - Master 1 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M1AP [4/6]

#define FMC_PFAPR_M1AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)

M1AP - Master 1 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M1AP [5/6]

#define FMC_PFAPR_M1AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)

M1AP - Master 1 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M1AP [6/6]

#define FMC_PFAPR_M1AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)

M1AP - Master 1 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M1PFD [1/5]

#define FMC_PFAPR_M1PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)

M1PFD - Master 1 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M1PFD [2/5]

#define FMC_PFAPR_M1PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)

M1PFD - Master 1 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M1PFD [3/5]

#define FMC_PFAPR_M1PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)

M1PFD - Master 1 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M1PFD [4/5]

#define FMC_PFAPR_M1PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)

M1PFD - Master 1 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M1PFD [5/5]

#define FMC_PFAPR_M1PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)

M1PFD - Master 1 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M2AP [1/6]

#define FMC_PFAPR_M2AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)

M2AP - Master 2 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M2AP [2/6]

#define FMC_PFAPR_M2AP

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)

M2AP - Master 2 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M2AP [3/6]

#define FMC_PFAPR_M2AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)

M2AP - Master 2 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M2AP [4/6]

#define FMC_PFAPR_M2AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)

M2AP - Master 2 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M2AP [5/6]

#define FMC_PFAPR_M2AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)

M2AP - Master 2 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M2AP [6/6]

#define FMC_PFAPR_M2AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)

M2AP - Master 2 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M2PFD [1/5]

#define FMC_PFAPR_M2PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)

M2PFD - Master 2 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M2PFD [2/5]

#define FMC_PFAPR_M2PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)

M2PFD - Master 2 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M2PFD [3/5]

#define FMC_PFAPR_M2PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)

M2PFD - Master 2 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M2PFD [4/5]

#define FMC_PFAPR_M2PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)

M2PFD - Master 2 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M2PFD [5/5]

#define FMC_PFAPR_M2PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)

M2PFD - Master 2 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M3AP [1/6]

#define FMC_PFAPR_M3AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)

M3AP - Master 3 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M3AP [2/6]

#define FMC_PFAPR_M3AP

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)

M3AP - Master 3 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M3AP [3/6]

#define FMC_PFAPR_M3AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)

M3AP - Master 3 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M3AP [4/6]

#define FMC_PFAPR_M3AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)

M3AP - Master 3 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M3AP [5/6]

#define FMC_PFAPR_M3AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)

M3AP - Master 3 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M3AP [6/6]

#define FMC_PFAPR_M3AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)

M3AP - Master 3 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M3PFD [1/5]

#define FMC_PFAPR_M3PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)

M3PFD - Master 3 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M3PFD [2/5]

#define FMC_PFAPR_M3PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)

M3PFD - Master 3 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M3PFD [3/5]

#define FMC_PFAPR_M3PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)

M3PFD - Master 3 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M3PFD [4/5]

#define FMC_PFAPR_M3PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)

M3PFD - Master 3 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M3PFD [5/5]

#define FMC_PFAPR_M3PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)

M3PFD - Master 3 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M4AP [1/5]

#define FMC_PFAPR_M4AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)

M4AP - Master 4 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M4AP [2/5]

#define FMC_PFAPR_M4AP

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)

M4AP - Master 4 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M4AP [3/5]

#define FMC_PFAPR_M4AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)

M4AP - Master 4 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M4AP [4/5]

#define FMC_PFAPR_M4AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)

M4AP - Master 4 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M4AP [5/5]

#define FMC_PFAPR_M4AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)

M4AP - Master 4 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M4PFD [1/4]

#define FMC_PFAPR_M4PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)

M4PFD - Master 4 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M4PFD [2/4]

#define FMC_PFAPR_M4PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)

M4PFD - Master 4 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M4PFD [3/4]

#define FMC_PFAPR_M4PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)

M4PFD - Master 4 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M4PFD [4/4]

#define FMC_PFAPR_M4PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)

M4PFD - Master 4 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M5AP [1/5]

#define FMC_PFAPR_M5AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)

M5AP - Master 5 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M5AP [2/5]

#define FMC_PFAPR_M5AP

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)

M5AP - Master 5 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M5AP [3/5]

#define FMC_PFAPR_M5AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)

M5AP - Master 5 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M5AP [4/5]

#define FMC_PFAPR_M5AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)

M5AP - Master 5 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M5AP [5/5]

#define FMC_PFAPR_M5AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)

M5AP - Master 5 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M5PFD [1/4]

#define FMC_PFAPR_M5PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)

M5PFD - Master 5 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M5PFD [2/4]

#define FMC_PFAPR_M5PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)

M5PFD - Master 5 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M5PFD [3/4]

#define FMC_PFAPR_M5PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)

M5PFD - Master 5 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M5PFD [4/4]

#define FMC_PFAPR_M5PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)

M5PFD - Master 5 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M6AP [1/5]

#define FMC_PFAPR_M6AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)

M6AP - Master 6 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M6AP [2/5]

#define FMC_PFAPR_M6AP

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)

M6AP - Master 6 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M6AP [3/5]

#define FMC_PFAPR_M6AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)

M6AP - Master 6 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M6AP [4/5]

#define FMC_PFAPR_M6AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)

M6AP - Master 6 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M6AP [5/5]

#define FMC_PFAPR_M6AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)

M6AP - Master 6 Access Protection 0b00..No access may be performed by this master 0b01..Only read accesses may be performed by this master 0b10..Only write accesses may be performed by this master 0b11..Both read and write accesses may be performed by this master

FMC_PFAPR_M6PFD [1/4]

#define FMC_PFAPR_M6PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)

M6PFD - Master 6 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M6PFD [2/4]

#define FMC_PFAPR_M6PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)

M6PFD - Master 6 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M6PFD [3/4]

#define FMC_PFAPR_M6PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)

M6PFD - Master 6 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M6PFD [4/4]

#define FMC_PFAPR_M6PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)

M6PFD - Master 6 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M7AP [1/5]

#define FMC_PFAPR_M7AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)

M7AP - Master 7 Access Protection 0b00..No access may be performed by this master. 0b01..Only read accesses may be performed by this master. 0b10..Only write accesses may be performed by this master. 0b11..Both read and write accesses may be performed by this master.

FMC_PFAPR_M7AP [2/5]

#define FMC_PFAPR_M7AP

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)

M7AP - Master 7 Access Protection 0b00..No access may be performed by this master. 0b01..Only read accesses may be performed by this master. 0b10..Only write accesses may be performed by this master. 0b11..Both read and write accesses may be performed by this master.

FMC_PFAPR_M7AP [3/5]

#define FMC_PFAPR_M7AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)

M7AP - Master 7 Access Protection 0b00..No access may be performed by this master. 0b01..Only read accesses may be performed by this master. 0b10..Only write accesses may be performed by this master. 0b11..Both read and write accesses may be performed by this master.

FMC_PFAPR_M7AP [4/5]

#define FMC_PFAPR_M7AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)

M7AP - Master 7 Access Protection 0b00..No access may be performed by this master. 0b01..Only read accesses may be performed by this master. 0b10..Only write accesses may be performed by this master. 0b11..Both read and write accesses may be performed by this master.

FMC_PFAPR_M7AP [5/5]

#define FMC_PFAPR_M7AP

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)

M7AP - Master 7 Access Protection 0b00..No access may be performed by this master. 0b01..Only read accesses may be performed by this master. 0b10..Only write accesses may be performed by this master. 0b11..Both read and write accesses may be performed by this master.

FMC_PFAPR_M7PFD [1/4]

#define FMC_PFAPR_M7PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)

M7PFD - Master 7 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M7PFD [2/4]

#define FMC_PFAPR_M7PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)

M7PFD - Master 7 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M7PFD [3/4]

#define FMC_PFAPR_M7PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)

M7PFD - Master 7 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFAPR_M7PFD [4/4]

#define FMC_PFAPR_M7PFD

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)

M7PFD - Master 7 Prefetch Disable 0b0..Prefetching for this master is enabled. 0b1..Prefetching for this master is disabled.

FMC_PFB01CR_B0DCE [1/2]

#define FMC_PFB01CR_B0DCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)

B0DCE - Bank 0 Data Cache Enable 0b0..Do not cache data references. 0b1..Cache data references.

FMC_PFB01CR_B0DCE [2/2]

#define FMC_PFB01CR_B0DCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)

B0DCE - Bank 0 Data Cache Enable 0b0..Do not cache data references. 0b1..Cache data references.

FMC_PFB01CR_B0DPE [1/2]

#define FMC_PFB01CR_B0DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)

B0DPE - Bank 0 Data Prefetch Enable 0b0..Do not prefetch in response to data references. 0b1..Enable prefetches in response to data references.

FMC_PFB01CR_B0DPE [2/2]

#define FMC_PFB01CR_B0DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)

B0DPE - Bank 0 Data Prefetch Enable 0b0..Do not prefetch in response to data references. 0b1..Enable prefetches in response to data references.

FMC_PFB01CR_B0ICE [1/2]

#define FMC_PFB01CR_B0ICE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)

B0ICE - Bank 0 Instruction Cache Enable 0b0..Do not cache instruction fetches. 0b1..Cache instruction fetches.

FMC_PFB01CR_B0ICE [2/2]

#define FMC_PFB01CR_B0ICE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)

B0ICE - Bank 0 Instruction Cache Enable 0b0..Do not cache instruction fetches. 0b1..Cache instruction fetches.

FMC_PFB01CR_B0IPE [1/2]

#define FMC_PFB01CR_B0IPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)

B0IPE - Bank 0 Instruction Prefetch Enable 0b0..Do not prefetch in response to instruction fetches. 0b1..Enable prefetches in response to instruction fetches.

FMC_PFB01CR_B0IPE [2/2]

#define FMC_PFB01CR_B0IPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)

B0IPE - Bank 0 Instruction Prefetch Enable 0b0..Do not prefetch in response to instruction fetches. 0b1..Enable prefetches in response to instruction fetches.

FMC_PFB01CR_B0MW [1/2]

#define FMC_PFB01CR_B0MW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)

B0MW - Bank 0 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..Reserved

FMC_PFB01CR_B0MW [2/2]

#define FMC_PFB01CR_B0MW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)

B0MW - Bank 0 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..Reserved

FMC_PFB01CR_CINV_WAY [1/2]

#define FMC_PFB01CR_CINV_WAY

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)

CINV_WAY - Cache Invalidate Way x 0b0000..No cache way invalidation for the corresponding cache 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected

FMC_PFB01CR_CINV_WAY [2/2]

#define FMC_PFB01CR_CINV_WAY

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)

CINV_WAY - Cache Invalidate Way x 0b0000..No cache way invalidation for the corresponding cache 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected

FMC_PFB01CR_CLCK_WAY [1/2]

#define FMC_PFB01CR_CLCK_WAY

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)

CLCK_WAY - Cache Lock Way x 0b0000..Cache way is unlocked and may be displaced 0b0001..Cache way is locked and its contents are not displaced

FMC_PFB01CR_CLCK_WAY [2/2]

#define FMC_PFB01CR_CLCK_WAY

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)

CLCK_WAY - Cache Lock Way x 0b0000..Cache way is unlocked and may be displaced 0b0001..Cache way is locked and its contents are not displaced

FMC_PFB01CR_CRC [1/2]

#define FMC_PFB01CR_CRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)

CRC - Cache Replacement Control 0b000..LRU replacement algorithm per set across all four ways 0b001..Reserved 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data 0b1xx..Reserved

FMC_PFB01CR_CRC [2/2]

#define FMC_PFB01CR_CRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)

CRC - Cache Replacement Control 0b000..LRU replacement algorithm per set across all four ways 0b001..Reserved 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data 0b1xx..Reserved

FMC_PFB01CR_S_B_INV [1/2]

#define FMC_PFB01CR_S_B_INV

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)

S_B_INV - Invalidate Prefetch Speculation Buffer 0b0..Speculation buffer is not affected 0b1..Invalidate (clear) speculation buffer

FMC_PFB01CR_S_B_INV [2/2]

#define FMC_PFB01CR_S_B_INV

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)

S_B_INV - Invalidate Prefetch Speculation Buffer 0b0..Speculation buffer is not affected 0b1..Invalidate (clear) speculation buffer

FMC_PFB0CR_B0DCE [1/2]

#define FMC_PFB0CR_B0DCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)

B0DCE - Bank 0 Data Cache Enable 0b0..Do not cache data references. 0b1..Cache data references.

FMC_PFB0CR_B0DCE [2/2]

#define FMC_PFB0CR_B0DCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)

B0DCE - Bank 0 Data Cache Enable 0b0..Do not cache data references. 0b1..Cache data references.

FMC_PFB0CR_B0DPE [1/3]

#define FMC_PFB0CR_B0DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)

B0DPE - Bank 0 Data Prefetch Enable 0b0..Do not prefetch in response to data references. 0b1..Enable prefetches in response to data references.

FMC_PFB0CR_B0DPE [2/3]

#define FMC_PFB0CR_B0DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)

B0DPE - Bank 0 Data Prefetch Enable 0b0..Do not prefetch in response to data references. 0b1..Enable prefetches in response to data references.

FMC_PFB0CR_B0DPE [3/3]

#define FMC_PFB0CR_B0DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)

B0DPE - Bank 0 Data Prefetch Enable 0b0..Do not prefetch in response to data references. 0b1..Enable prefetches in response to data references.

FMC_PFB0CR_B0ICE [1/2]

#define FMC_PFB0CR_B0ICE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)

B0ICE - Bank 0 Instruction Cache Enable 0b0..Do not cache instruction fetches. 0b1..Cache instruction fetches.

FMC_PFB0CR_B0ICE [2/2]

#define FMC_PFB0CR_B0ICE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)

B0ICE - Bank 0 Instruction Cache Enable 0b0..Do not cache instruction fetches. 0b1..Cache instruction fetches.

FMC_PFB0CR_B0IPE [1/3]

#define FMC_PFB0CR_B0IPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)

B0IPE - Bank 0 Instruction Prefetch Enable 0b0..Do not prefetch in response to instruction fetches. 0b1..Enable prefetches in response to instruction fetches.

FMC_PFB0CR_B0IPE [2/3]

#define FMC_PFB0CR_B0IPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)

B0IPE - Bank 0 Instruction Prefetch Enable 0b0..Do not prefetch in response to instruction fetches. 0b1..Enable prefetches in response to instruction fetches.

FMC_PFB0CR_B0IPE [3/3]

#define FMC_PFB0CR_B0IPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)

B0IPE - Bank 0 Instruction Prefetch Enable 0b0..Do not prefetch in response to instruction fetches. 0b1..Enable prefetches in response to instruction fetches.

FMC_PFB0CR_B0MW [1/4]

#define FMC_PFB0CR_B0MW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)

B0MW - Bank 0 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..Reserved

B0MW - Bank 0 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..256 bits

FMC_PFB0CR_B0MW [2/4]

#define FMC_PFB0CR_B0MW

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)

B0MW - Bank 0 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..Reserved

B0MW - Bank 0 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..256 bits

FMC_PFB0CR_B0MW [3/4]

#define FMC_PFB0CR_B0MW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)

B0MW - Bank 0 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..Reserved

B0MW - Bank 0 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..256 bits

FMC_PFB0CR_B0MW [4/4]

#define FMC_PFB0CR_B0MW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)

B0MW - Bank 0 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..256 bits

FMC_PFB0CR_B0SEBE [1/2]

#define FMC_PFB0CR_B0SEBE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)

B0SEBE - Bank 0 Single Entry Buffer Enable 0b0..Single entry buffer is disabled. 0b1..Single entry buffer is enabled.

FMC_PFB0CR_B0SEBE [2/2]

#define FMC_PFB0CR_B0SEBE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)

B0SEBE - Bank 0 Single Entry Buffer Enable 0b0..Single entry buffer is disabled. 0b1..Single entry buffer is enabled.

FMC_PFB0CR_CINV_WAY [1/3]

#define FMC_PFB0CR_CINV_WAY

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)

CINV_WAY - Cache Invalidate Way x 0b0000..No cache way invalidation for the corresponding cache 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected

FMC_PFB0CR_CINV_WAY [2/3]

#define FMC_PFB0CR_CINV_WAY

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)

CINV_WAY - Cache Invalidate Way x 0b0000..No cache way invalidation for the corresponding cache 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected

FMC_PFB0CR_CINV_WAY [3/3]

#define FMC_PFB0CR_CINV_WAY

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)

CINV_WAY - Cache Invalidate Way x 0b0000..No cache way invalidation for the corresponding cache 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected

FMC_PFB0CR_CLCK_WAY [1/3]

#define FMC_PFB0CR_CLCK_WAY

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)

CLCK_WAY - Cache Lock Way x 0b0000..Cache way is unlocked and may be displaced 0b0001..Cache way is locked and its contents are not displaced

FMC_PFB0CR_CLCK_WAY [2/3]

#define FMC_PFB0CR_CLCK_WAY

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)

CLCK_WAY - Cache Lock Way x 0b0000..Cache way is unlocked and may be displaced 0b0001..Cache way is locked and its contents are not displaced

FMC_PFB0CR_CLCK_WAY [3/3]

#define FMC_PFB0CR_CLCK_WAY

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)

CLCK_WAY - Cache Lock Way x 0b0000..Cache way is unlocked and may be displaced 0b0001..Cache way is locked and its contents are not displaced

FMC_PFB0CR_CRC [1/3]

#define FMC_PFB0CR_CRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)

CRC - Cache Replacement Control 0b000..LRU replacement algorithm per set across all four ways 0b001..Reserved 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data 0b1xx..Reserved

FMC_PFB0CR_CRC [2/3]

#define FMC_PFB0CR_CRC

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)

CRC - Cache Replacement Control 0b000..LRU replacement algorithm per set across all four ways 0b001..Reserved 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data 0b1xx..Reserved

FMC_PFB0CR_CRC [3/3]

#define FMC_PFB0CR_CRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)

CRC - Cache Replacement Control 0b000..LRU replacement algorithm per set across all four ways 0b001..Reserved 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data 0b1xx..Reserved

FMC_PFB0CR_S_B_INV [1/2]

#define FMC_PFB0CR_S_B_INV

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)

S_B_INV - Invalidate Prefetch Speculation Buffer 0b0..Speculation buffer and single entry buffer are not affected. 0b1..Invalidate (clear) speculation buffer and single entry buffer.

FMC_PFB0CR_S_B_INV [2/2]

#define FMC_PFB0CR_S_B_INV

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)

S_B_INV - Invalidate Prefetch Speculation Buffer 0b0..Speculation buffer and single entry buffer are not affected. 0b1..Invalidate (clear) speculation buffer and single entry buffer.

FMC_PFB0CR_S_INV

#define FMC_PFB0CR_S_INV

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_INV_SHIFT)) & FMC_PFB0CR_S_INV_MASK)

S_INV - Invalidate Prefetch Speculation Buffer 0b0..Speculation buffer is not affected. 0b1..Invalidate (clear) the speculation buffer.

FMC_PFB1CR_B1DCE [1/2]

#define FMC_PFB1CR_B1DCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)

B1DCE - Bank 1 Data Cache Enable 0b0..Do not cache data references. 0b1..Cache data references.

FMC_PFB1CR_B1DCE [2/2]

#define FMC_PFB1CR_B1DCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)

B1DCE - Bank 1 Data Cache Enable 0b0..Do not cache data references. 0b1..Cache data references.

FMC_PFB1CR_B1DPE [1/2]

#define FMC_PFB1CR_B1DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)

B1DPE - Bank 1 Data Prefetch Enable 0b0..Do not prefetch in response to data references. 0b1..Enable prefetches in response to data references.

FMC_PFB1CR_B1DPE [2/2]

#define FMC_PFB1CR_B1DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)

B1DPE - Bank 1 Data Prefetch Enable 0b0..Do not prefetch in response to data references. 0b1..Enable prefetches in response to data references.

FMC_PFB1CR_B1ICE [1/2]

#define FMC_PFB1CR_B1ICE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)

B1ICE - Bank 1 Instruction Cache Enable 0b0..Do not cache instruction fetches. 0b1..Cache instruction fetches.

FMC_PFB1CR_B1ICE [2/2]

#define FMC_PFB1CR_B1ICE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)

B1ICE - Bank 1 Instruction Cache Enable 0b0..Do not cache instruction fetches. 0b1..Cache instruction fetches.

FMC_PFB1CR_B1IPE [1/2]

#define FMC_PFB1CR_B1IPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)

B1IPE - Bank 1 Instruction Prefetch Enable 0b0..Do not prefetch in response to instruction fetches. 0b1..Enable prefetches in response to instruction fetches.

FMC_PFB1CR_B1IPE [2/2]

#define FMC_PFB1CR_B1IPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)

B1IPE - Bank 1 Instruction Prefetch Enable 0b0..Do not prefetch in response to instruction fetches. 0b1..Enable prefetches in response to instruction fetches.

FMC_PFB1CR_B1MW [1/3]

#define FMC_PFB1CR_B1MW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)

B1MW - Bank 1 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..Reserved

FMC_PFB1CR_B1MW [2/3]

#define FMC_PFB1CR_B1MW

(

x

)

(((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)

B1MW - Bank 1 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..Reserved

FMC_PFB1CR_B1MW [3/3]

#define FMC_PFB1CR_B1MW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)

B1MW - Bank 1 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..Reserved

FMC_PFB1CR_B1SEBE [1/2]

#define FMC_PFB1CR_B1SEBE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)

B1SEBE - Bank 1 Single Entry Buffer Enable 0b0..Single entry buffer is disabled. 0b1..Single entry buffer is enabled.

FMC_PFB1CR_B1SEBE [2/2]

#define FMC_PFB1CR_B1SEBE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)

B1SEBE - Bank 1 Single Entry Buffer Enable 0b0..Single entry buffer is disabled. 0b1..Single entry buffer is enabled.

FMC_PFB23CR_B1DCE [1/2]

#define FMC_PFB23CR_B1DCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)

B1DCE - Bank 1 Data Cache Enable 0b0..Do not cache data references. 0b1..Cache data references.

FMC_PFB23CR_B1DCE [2/2]

#define FMC_PFB23CR_B1DCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)

B1DCE - Bank 1 Data Cache Enable 0b0..Do not cache data references. 0b1..Cache data references.

FMC_PFB23CR_B1DPE [1/2]

#define FMC_PFB23CR_B1DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)

B1DPE - Bank 1 Data Prefetch Enable 0b0..Do not prefetch in response to data references. 0b1..Enable prefetches in response to data references.

FMC_PFB23CR_B1DPE [2/2]

#define FMC_PFB23CR_B1DPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)

B1DPE - Bank 1 Data Prefetch Enable 0b0..Do not prefetch in response to data references. 0b1..Enable prefetches in response to data references.

FMC_PFB23CR_B1ICE [1/2]

#define FMC_PFB23CR_B1ICE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)

B1ICE - Bank 1 Instruction Cache Enable 0b0..Do not cache instruction fetches. 0b1..Cache instruction fetches.

FMC_PFB23CR_B1ICE [2/2]

#define FMC_PFB23CR_B1ICE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)

B1ICE - Bank 1 Instruction Cache Enable 0b0..Do not cache instruction fetches. 0b1..Cache instruction fetches.

FMC_PFB23CR_B1IPE [1/2]

#define FMC_PFB23CR_B1IPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)

B1IPE - Bank 1 Instruction Prefetch Enable 0b0..Do not prefetch in response to instruction fetches. 0b1..Enable prefetches in response to instruction fetches.

FMC_PFB23CR_B1IPE [2/2]

#define FMC_PFB23CR_B1IPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)

B1IPE - Bank 1 Instruction Prefetch Enable 0b0..Do not prefetch in response to instruction fetches. 0b1..Enable prefetches in response to instruction fetches.

FMC_PFB23CR_B1MW [1/2]

#define FMC_PFB23CR_B1MW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)

B1MW - Bank 1 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..Reserved

FMC_PFB23CR_B1MW [2/2]

#define FMC_PFB23CR_B1MW

(

x

)

(((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)

B1MW - Bank 1 Memory Width 0b00..32 bits 0b01..64 bits 0b10..128 bits 0b11..Reserved