mikroSDK Reference Manual
stm32f1xx_hal_rcc.h
Go to the documentation of this file.
1
20/* Define to prevent recursive inclusion -------------------------------------*/
21#ifndef __STM32F1xx_HAL_RCC_H
22#define __STM32F1xx_HAL_RCC_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28/* Includes ------------------------------------------------------------------*/
29#include "stm32f1xx_hal_def.h"
30
31
40/* Exported types ------------------------------------------------------------*/
41
49typedef struct
50{
51 uint32_t PLLState;
54 uint32_t PLLSource;
57 uint32_t PLLMUL;
59} RCC_PLLInitTypeDef;
60
64typedef struct
65{
66 uint32_t ClockType;
69 uint32_t SYSCLKSource;
72 uint32_t AHBCLKDivider;
75 uint32_t APB1CLKDivider;
78 uint32_t APB2CLKDivider;
80} RCC_ClkInitTypeDef;
81
86/* Exported constants --------------------------------------------------------*/
95#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U
96#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC
105#define RCC_OSCILLATORTYPE_NONE 0x00000000U
106#define RCC_OSCILLATORTYPE_HSE 0x00000001U
107#define RCC_OSCILLATORTYPE_HSI 0x00000002U
108#define RCC_OSCILLATORTYPE_LSE 0x00000004U
109#define RCC_OSCILLATORTYPE_LSI 0x00000008U
117#define RCC_HSE_OFF 0x00000000U
118#define RCC_HSE_ON RCC_CR_HSEON
119#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
127#define RCC_LSE_OFF 0x00000000U
128#define RCC_LSE_ON RCC_BDCR_LSEON
129#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
138#define RCC_HSI_OFF 0x00000000U
139#define RCC_HSI_ON RCC_CR_HSION
141#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
142
150#define RCC_LSI_OFF 0x00000000U
151#define RCC_LSI_ON RCC_CSR_LSION
160#define RCC_PLL_NONE 0x00000000U
161#define RCC_PLL_OFF 0x00000001U
162#define RCC_PLL_ON 0x00000002U
171#define RCC_CLOCKTYPE_SYSCLK 0x00000001U
172#define RCC_CLOCKTYPE_HCLK 0x00000002U
173#define RCC_CLOCKTYPE_PCLK1 0x00000004U
174#define RCC_CLOCKTYPE_PCLK2 0x00000008U
183#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
184#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
185#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
194#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
195#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
196#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
205#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
206#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
207#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
208#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
209#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
210#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
211#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
212#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
213#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
222#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
223#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
224#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
225#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
226#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
235#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
236#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
237#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
238#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE
247#define RCC_MCO1 0x00000000U
248#define RCC_MCO RCC_MCO1
257#define RCC_MCODIV_1 0x00000000U
258
266#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)
267#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)
268#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)
269#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)
270#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)
271#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)
285/* Flags in the CR register */
286#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos))
287#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos))
288#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos))
290/* Flags in the CSR register */
291#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos))
292#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos))
293#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos))
294#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos))
295#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos))
296#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos))
297#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos))
299/* Flags in the BDCR register */
300#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos))
310/* Exported macro ------------------------------------------------------------*/
311
323#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
324 __IO uint32_t tmpreg; \
325 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
326 /* Delay after an RCC peripheral clock enabling */\
327 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
328 UNUSED(tmpreg); \
329 } while(0U)
330
331#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
332 __IO uint32_t tmpreg; \
333 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
334 /* Delay after an RCC peripheral clock enabling */\
335 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
336 UNUSED(tmpreg); \
337 } while(0U)
338
339#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
340 __IO uint32_t tmpreg; \
341 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
342 /* Delay after an RCC peripheral clock enabling */\
343 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
344 UNUSED(tmpreg); \
345 } while(0U)
346
347#define __HAL_RCC_CRC_CLK_ENABLE() do { \
348 __IO uint32_t tmpreg; \
349 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
350 /* Delay after an RCC peripheral clock enabling */\
351 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
352 UNUSED(tmpreg); \
353 } while(0U)
354
355#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
356#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
357#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
358#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
359
372#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
373#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
374#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
375#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
376#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
377#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
378#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
379#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
380
392#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
393 __IO uint32_t tmpreg; \
394 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
395 /* Delay after an RCC peripheral clock enabling */\
396 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
397 UNUSED(tmpreg); \
398 } while(0U)
399
400#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
401 __IO uint32_t tmpreg; \
402 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
403 /* Delay after an RCC peripheral clock enabling */\
404 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
405 UNUSED(tmpreg); \
406 } while(0U)
407
408#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
409 __IO uint32_t tmpreg; \
410 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
411 /* Delay after an RCC peripheral clock enabling */\
412 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
413 UNUSED(tmpreg); \
414 } while(0U)
415
416#define __HAL_RCC_USART2_CLK_ENABLE() do { \
417 __IO uint32_t tmpreg; \
418 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
419 /* Delay after an RCC peripheral clock enabling */\
420 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
421 UNUSED(tmpreg); \
422 } while(0U)
423
424#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
425 __IO uint32_t tmpreg; \
426 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
427 /* Delay after an RCC peripheral clock enabling */\
428 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
429 UNUSED(tmpreg); \
430 } while(0U)
431
432#define __HAL_RCC_BKP_CLK_ENABLE() do { \
433 __IO uint32_t tmpreg; \
434 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
435 /* Delay after an RCC peripheral clock enabling */\
436 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
437 UNUSED(tmpreg); \
438 } while(0U)
439
440#define __HAL_RCC_PWR_CLK_ENABLE() do { \
441 __IO uint32_t tmpreg; \
442 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
443 /* Delay after an RCC peripheral clock enabling */\
444 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
445 UNUSED(tmpreg); \
446 } while(0U)
447
448#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
449#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
450#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
451#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
452#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
453
454#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
455#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
456
469#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
470#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
471#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
472#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
473#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
474#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
475#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
476#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
477#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
478#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
479#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
480#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
481#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
482#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
483
495#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
496 __IO uint32_t tmpreg; \
497 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
498 /* Delay after an RCC peripheral clock enabling */\
499 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
500 UNUSED(tmpreg); \
501 } while(0U)
502
503#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
504 __IO uint32_t tmpreg; \
505 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
506 /* Delay after an RCC peripheral clock enabling */\
507 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
508 UNUSED(tmpreg); \
509 } while(0U)
510
511#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
512 __IO uint32_t tmpreg; \
513 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
514 /* Delay after an RCC peripheral clock enabling */\
515 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
516 UNUSED(tmpreg); \
517 } while(0U)
518
519#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
520 __IO uint32_t tmpreg; \
521 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
522 /* Delay after an RCC peripheral clock enabling */\
523 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
524 UNUSED(tmpreg); \
525 } while(0U)
526
527#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
528 __IO uint32_t tmpreg; \
529 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
530 /* Delay after an RCC peripheral clock enabling */\
531 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
532 UNUSED(tmpreg); \
533 } while(0U)
534
535#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
536 __IO uint32_t tmpreg; \
537 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
538 /* Delay after an RCC peripheral clock enabling */\
539 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
540 UNUSED(tmpreg); \
541 } while(0U)
542
543#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
544 __IO uint32_t tmpreg; \
545 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
546 /* Delay after an RCC peripheral clock enabling */\
547 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
548 UNUSED(tmpreg); \
549 } while(0U)
550
551#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
552 __IO uint32_t tmpreg; \
553 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
554 /* Delay after an RCC peripheral clock enabling */\
555 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
556 UNUSED(tmpreg); \
557 } while(0U)
558
559#define __HAL_RCC_USART1_CLK_ENABLE() do { \
560 __IO uint32_t tmpreg; \
561 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
562 /* Delay after an RCC peripheral clock enabling */\
563 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
564 UNUSED(tmpreg); \
565 } while(0U)
566
567#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
568#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
569#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
570#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
571#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
572#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
573
574#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
575#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
576#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
577
590#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
591#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
592#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
593#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
594#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
595#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
596#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
597#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
598#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
599#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
600#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
601#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
602#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
603#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
604#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
605#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
606#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
607#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
608
617#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
618#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
619#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
620#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
621#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
622#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
623
624#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
625#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
626
627#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
628#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
629#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
630#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
631#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
632#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
633
634#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
635#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
636
645#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
646#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
647#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
648#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
649#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
650#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
651#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
652
653#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
654#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
655#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
656
657#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
658#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
659#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
660#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
661#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
662#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
663#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
664
665#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
666#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
667#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
668
687#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
688#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
689
697#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
698 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
699
713#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
714
720#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
721
752#define __HAL_RCC_HSE_CONFIG(__STATE__) \
753 do{ \
754 if ((__STATE__) == RCC_HSE_ON) \
755 { \
756 SET_BIT(RCC->CR, RCC_CR_HSEON); \
757 } \
758 else if ((__STATE__) == RCC_HSE_OFF) \
759 { \
760 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
761 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
762 } \
763 else if ((__STATE__) == RCC_HSE_BYPASS) \
764 { \
765 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
766 SET_BIT(RCC->CR, RCC_CR_HSEON); \
767 } \
768 else \
769 { \
770 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
771 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
772 } \
773 }while(0U)
774
800#define __HAL_RCC_LSE_CONFIG(__STATE__) \
801 do{ \
802 if ((__STATE__) == RCC_LSE_ON) \
803 { \
804 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
805 } \
806 else if ((__STATE__) == RCC_LSE_OFF) \
807 { \
808 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
809 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
810 } \
811 else if ((__STATE__) == RCC_LSE_BYPASS) \
812 { \
813 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
814 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
815 } \
816 else \
817 { \
818 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
819 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
820 } \
821 }while(0U)
822
837#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
838
842#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
843
874#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
875 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
876
883#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
884
901#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
902 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
903
911#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
912
921#if defined(RCC_CFGR_MCO_3)
938#else
951#endif
952
953#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
954 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
955
956
987#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
988
996#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
997
1001#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
1002
1006#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
1007
1012#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
1013
1016#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
1017
1043#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1044
1061#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1062
1080#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1081
1100#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1101
1106#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
1107
1131#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
1132 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
1133 RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
1134
1143/* Include RCC HAL Extension module */
1144#include "stm32f1xx_hal_rcc_ex.h"
1145
1146/* Exported functions --------------------------------------------------------*/
1155/* Initialization and de-initialization functions ******************************/
1156HAL_StatusTypeDef HAL_RCC_DeInit(void);
1157HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1158HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1159
1168/* Peripheral Control functions ************************************************/
1169void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1170void HAL_RCC_EnableCSS(void);
1171void HAL_RCC_DisableCSS(void);
1172uint32_t HAL_RCC_GetSysClockFreq(void);
1173uint32_t HAL_RCC_GetHCLKFreq(void);
1174uint32_t HAL_RCC_GetPCLK1Freq(void);
1175uint32_t HAL_RCC_GetPCLK2Freq(void);
1176void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1177void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1178
1179/* CSS NMI IRQ handler */
1180void HAL_RCC_NMI_IRQHandler(void);
1181
1182/* User Callbacks in non blocking mode (IT mode) */
1183void HAL_RCC_CSSCallback(void);
1184
1201/* Disable Backup domain write protection state change timeout */
1202#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
1203/* LSE state change timeout */
1204#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1205#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
1206#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1207#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
1208#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
1209#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
1210
1218#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1219#define RCC_CR_OFFSET 0x00U
1220#define RCC_CFGR_OFFSET 0x04U
1221#define RCC_CIR_OFFSET 0x08U
1222#define RCC_BDCR_OFFSET 0x20U
1223#define RCC_CSR_OFFSET 0x24U
1224
1233#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
1234#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
1235#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
1236#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
1237#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
1238
1239/* --- CR Register ---*/
1240/* Alias word address of HSION bit */
1241#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
1242#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
1243/* Alias word address of HSEON bit */
1244#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
1245#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
1246/* Alias word address of CSSON bit */
1247#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
1248#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
1249/* Alias word address of PLLON bit */
1250#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
1251#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
1252
1253/* --- CSR Register ---*/
1254/* Alias word address of LSION bit */
1255#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
1256#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
1257
1258/* Alias word address of RMVF bit */
1259#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
1260#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
1261
1262/* --- BDCR Registers ---*/
1263/* Alias word address of LSEON bit */
1264#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
1265#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
1266
1267/* Alias word address of LSEON bit */
1268#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
1269#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
1270
1271/* Alias word address of RTCEN bit */
1272#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
1273#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
1274
1275/* Alias word address of BDRST bit */
1276#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
1277#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
1278
1283/* CR register byte 2 (Bits[23:16]) base address */
1284#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
1285
1286/* CIR register byte 1 (Bits[15:8]) base address */
1287#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
1288
1289/* CIR register byte 2 (Bits[23:16]) base address */
1290#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
1291
1292/* Defines used for Flags */
1293#define CR_REG_INDEX ((uint8_t)1)
1294#define BDCR_REG_INDEX ((uint8_t)2)
1295#define CSR_REG_INDEX ((uint8_t)3)
1296
1297#define RCC_FLAG_MASK ((uint8_t)0x1F)
1298
1309#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
1310#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
1311#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
1312#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
1317#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
1318 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
1319#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
1320 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
1321 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
1322 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
1323 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
1324#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
1325 ((__HSE__) == RCC_HSE_BYPASS))
1326#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
1327 ((__LSE__) == RCC_LSE_BYPASS))
1328#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
1329#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
1330#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
1331#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
1332 ((__PLL__) == RCC_PLL_ON))
1333
1334#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
1335 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
1336 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
1337 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
1338#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
1339 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
1340 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
1341#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
1342 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
1343 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
1344#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
1345 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
1346 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
1347 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
1348 ((__HCLK__) == RCC_SYSCLK_DIV512))
1349#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
1350 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
1351 ((__PCLK__) == RCC_HCLK_DIV16))
1352#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
1353#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
1354#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
1355 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
1356 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
1357 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
1358
1371#ifdef __cplusplus
1372}
1373#endif
1374
1375#endif /* __STM32F1xx_HAL_RCC_H */
1376
1377/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1378
stm32f1xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f1xx_hal_def.h:40
stm32f1xx_hal_rcc_ex.h
Header file of RCC HAL Extension module.
RCC_ClkInitTypeDef
RCC System, AHB and APB busses clock configuration structure definition.
Definition stm32f1xx_hal_rcc.h:65
RCC_ClkInitTypeDef::APB1CLKDivider
uint32_t APB1CLKDivider
Definition stm32f1xx_hal_rcc.h:75
RCC_ClkInitTypeDef::SYSCLKSource
uint32_t SYSCLKSource
Definition stm32f1xx_hal_rcc.h:69
RCC_ClkInitTypeDef::ClockType
uint32_t ClockType
Definition stm32f1xx_hal_rcc.h:66
RCC_ClkInitTypeDef::APB2CLKDivider
uint32_t APB2CLKDivider
Definition stm32f1xx_hal_rcc.h:78
RCC_ClkInitTypeDef::AHBCLKDivider
uint32_t AHBCLKDivider
Definition stm32f1xx_hal_rcc.h:72
RCC_OscInitTypeDef
RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition.
Definition stm32f1xx_hal_rcc_ex.h:229
RCC_PLLInitTypeDef
RCC PLL configuration structure definition.
Definition stm32f1xx_hal_rcc.h:50
RCC_PLLInitTypeDef::PLLMUL
uint32_t PLLMUL
Definition stm32f1xx_hal_rcc.h:57
RCC_PLLInitTypeDef::PLLState
uint32_t PLLState
Definition stm32f1xx_hal_rcc.h:51
RCC_PLLInitTypeDef::PLLSource
uint32_t PLLSource
Definition stm32f1xx_hal_rcc.h:54