FTM Peripheral Access Layer

Topics
	FTM Register Masks
	GPIO Peripheral Access Layer

Data Structures
struct	FTM_Type

Macros
#define	FTM0_BASE   (0x40038000u)
#define	FTM0   ((FTM_Type *)FTM0_BASE)
#define	FTM1_BASE   (0x40039000u)
#define	FTM1   ((FTM_Type *)FTM1_BASE)
#define	FTM2_BASE   (0x400B8000u)
#define	FTM2   ((FTM_Type *)FTM2_BASE)
#define	FTM0_BASE   (0x40038000u)
#define	FTM0   ((FTM_Type *)FTM0_BASE)
#define	FTM1_BASE   (0x40039000u)
#define	FTM1   ((FTM_Type *)FTM1_BASE)
#define	FTM2_BASE   (0x4003A000u)
#define	FTM2   ((FTM_Type *)FTM2_BASE)
#define	FTM3_BASE   (0x400B9000u)
#define	FTM3   ((FTM_Type *)FTM3_BASE)
#define	FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
#define	FTM_BASE_PTRS   { FTM0, FTM1, FTM2, FTM3 }
#define	FTM_IRQS   { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
#define	FTM0_BASE   (0x40038000u)
#define	FTM0   ((FTM_Type *)FTM0_BASE)
#define	FTM1_BASE   (0x40039000u)
#define	FTM1   ((FTM_Type *)FTM1_BASE)
#define	FTM2_BASE   (0x4003A000u)
#define	FTM2   ((FTM_Type *)FTM2_BASE)
#define	FTM3_BASE   (0x400B9000u)
#define	FTM3   ((FTM_Type *)FTM3_BASE)
#define	FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
#define	FTM_BASE_PTRS   { FTM0, FTM1, FTM2, FTM3 }
#define	FTM_IRQS   { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
#define	FTM0_BASE   (0x40038000u)
#define	FTM0   ((FTM_Type *)FTM0_BASE)
#define	FTM1_BASE   (0x40039000u)
#define	FTM1   ((FTM_Type *)FTM1_BASE)
#define	FTM2_BASE   (0x4003A000u)
#define	FTM2   ((FTM_Type *)FTM2_BASE)
#define	FTM3_BASE   (0x400B9000u)
#define	FTM3   ((FTM_Type *)FTM3_BASE)
#define	FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
#define	FTM_BASE_PTRS   { FTM0, FTM1, FTM2, FTM3 }
#define	FTM_IRQS   { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
#define	FTM0_BASE   (0x40038000u)
#define	FTM0   ((FTM_Type *)FTM0_BASE)
#define	FTM1_BASE   (0x40039000u)
#define	FTM1   ((FTM_Type *)FTM1_BASE)
#define	FTM2_BASE   (0x4003A000u)
#define	FTM2   ((FTM_Type *)FTM2_BASE)
#define	FTM3_BASE   (0x40026000u)
#define	FTM3   ((FTM_Type *)FTM3_BASE)
#define	FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
#define	FTM_BASE_PTRS   { FTM0, FTM1, FTM2, FTM3 }
#define	FTM_IRQS   { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }

Macro Definition Documentation

FTM0 [1/5]

#define FTM0   ((FTM_Type *)FTM0_BASE)

Peripheral FTM0 base pointer

FTM0 [2/5]

#define FTM0   ((FTM_Type *)FTM0_BASE)

Peripheral FTM0 base pointer

FTM0 [3/5]

#define FTM0   ((FTM_Type *)FTM0_BASE)

Peripheral FTM0 base pointer

FTM0 [4/5]

#define FTM0   ((FTM_Type *)FTM0_BASE)

Peripheral FTM0 base pointer

FTM0 [5/5]

#define FTM0   ((FTM_Type *)FTM0_BASE)

Peripheral FTM0 base pointer

FTM0_BASE [1/5]

#define FTM0_BASE   (0x40038000u)

Peripheral FTM0 base address

FTM0_BASE [2/5]

#define FTM0_BASE   (0x40038000u)

Peripheral FTM0 base address

FTM0_BASE [3/5]

#define FTM0_BASE   (0x40038000u)

Peripheral FTM0 base address

FTM0_BASE [4/5]

#define FTM0_BASE   (0x40038000u)

Peripheral FTM0 base address

FTM0_BASE [5/5]

#define FTM0_BASE   (0x40038000u)

Peripheral FTM0 base address

FTM1 [1/5]

#define FTM1   ((FTM_Type *)FTM1_BASE)

Peripheral FTM1 base pointer

FTM1 [2/5]

#define FTM1   ((FTM_Type *)FTM1_BASE)

Peripheral FTM1 base pointer

FTM1 [3/5]

#define FTM1   ((FTM_Type *)FTM1_BASE)

Peripheral FTM1 base pointer

FTM1 [4/5]

#define FTM1   ((FTM_Type *)FTM1_BASE)

Peripheral FTM1 base pointer

FTM1 [5/5]

#define FTM1   ((FTM_Type *)FTM1_BASE)

Peripheral FTM1 base pointer

FTM1_BASE [1/5]

#define FTM1_BASE   (0x40039000u)

Peripheral FTM1 base address

FTM1_BASE [2/5]

#define FTM1_BASE   (0x40039000u)

Peripheral FTM1 base address

FTM1_BASE [3/5]

#define FTM1_BASE   (0x40039000u)

Peripheral FTM1 base address

FTM1_BASE [4/5]

#define FTM1_BASE   (0x40039000u)

Peripheral FTM1 base address

FTM1_BASE [5/5]

#define FTM1_BASE   (0x40039000u)

Peripheral FTM1 base address

FTM2 [1/5]

#define FTM2   ((FTM_Type *)FTM2_BASE)

Peripheral FTM2 base pointer

FTM2 [2/5]

#define FTM2   ((FTM_Type *)FTM2_BASE)

Peripheral FTM2 base pointer

FTM2 [3/5]

#define FTM2   ((FTM_Type *)FTM2_BASE)

Peripheral FTM2 base pointer

FTM2 [4/5]

#define FTM2   ((FTM_Type *)FTM2_BASE)

Peripheral FTM2 base pointer

FTM2 [5/5]

#define FTM2   ((FTM_Type *)FTM2_BASE)

Peripheral FTM2 base pointer

FTM2_BASE [1/5]

#define FTM2_BASE   (0x400B8000u)

Peripheral FTM2 base address

FTM2_BASE [2/5]

#define FTM2_BASE   (0x4003A000u)

Peripheral FTM2 base address

FTM2_BASE [3/5]

#define FTM2_BASE   (0x4003A000u)

Peripheral FTM2 base address

FTM2_BASE [4/5]

#define FTM2_BASE   (0x4003A000u)

Peripheral FTM2 base address

FTM2_BASE [5/5]

#define FTM2_BASE   (0x4003A000u)

Peripheral FTM2 base address

FTM3 [1/4]

#define FTM3   ((FTM_Type *)FTM3_BASE)

Peripheral FTM3 base pointer

FTM3 [2/4]

#define FTM3   ((FTM_Type *)FTM3_BASE)

Peripheral FTM3 base pointer

FTM3 [3/4]

#define FTM3   ((FTM_Type *)FTM3_BASE)

Peripheral FTM3 base pointer

FTM3 [4/4]

#define FTM3   ((FTM_Type *)FTM3_BASE)

Peripheral FTM3 base pointer

FTM3_BASE [1/4]

#define FTM3_BASE   (0x400B9000u)

Peripheral FTM3 base address

FTM3_BASE [2/4]

#define FTM3_BASE   (0x400B9000u)

Peripheral FTM3 base address

FTM3_BASE [3/4]

#define FTM3_BASE   (0x400B9000u)

Peripheral FTM3 base address

FTM3_BASE [4/4]

#define FTM3_BASE   (0x40026000u)

Peripheral FTM3 base address

FTM_BASE_ADDRS [1/4]

#define FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }

Array initializer of FTM peripheral base addresses

FTM_BASE_ADDRS [2/4]

#define FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }

Array initializer of FTM peripheral base addresses

FTM_BASE_ADDRS [3/4]

#define FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }

Array initializer of FTM peripheral base addresses

FTM_BASE_ADDRS [4/4]

#define FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }

Array initializer of FTM peripheral base addresses

FTM_BASE_PTRS [1/4]

#define FTM_BASE_PTRS   { FTM0, FTM1, FTM2, FTM3 }

Array initializer of FTM peripheral base pointers

FTM_BASE_PTRS [2/4]

#define FTM_BASE_PTRS   { FTM0, FTM1, FTM2, FTM3 }

Array initializer of FTM peripheral base pointers

FTM_BASE_PTRS [3/4]

#define FTM_BASE_PTRS   { FTM0, FTM1, FTM2, FTM3 }

Array initializer of FTM peripheral base pointers

FTM_BASE_PTRS [4/4]

#define FTM_BASE_PTRS   { FTM0, FTM1, FTM2, FTM3 }

Array initializer of FTM peripheral base pointers

FTM_IRQS [1/4]

#define FTM_IRQS   { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }

Interrupt vectors for the FTM peripheral type

FTM_IRQS [2/4]

#define FTM_IRQS   { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }

Interrupt vectors for the FTM peripheral type

FTM_IRQS [3/4]

#define FTM_IRQS   { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }

Interrupt vectors for the FTM peripheral type

FTM_IRQS [4/4]

#define FTM_IRQS   { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }

Interrupt vectors for the FTM peripheral type