mikroSDK Reference Manual
Macros
FTM Register Masks
Mapping Information » Device Peripheral Access Layer » ADC Peripheral Access Layer » AIPS Peripheral Access Layer » AXBS Peripheral Access Layer » CAN Peripheral Access Layer » CAU Peripheral Access Layer » CMP Peripheral Access Layer » CMT Peripheral Access Layer » CRC Peripheral Access Layer » DAC Peripheral Access Layer » DMA Peripheral Access Layer » DMAMUX Peripheral Access Layer » ENET Peripheral Access Layer » EWM Peripheral Access Layer » FB Peripheral Access Layer » FMC Peripheral Access Layer » FTFL Peripheral Access Layer » FTM Peripheral Access Layer

Macros

#define FTM0_BASE   (0x40038000u)
 
#define FTM0   ((FTM_Type *)FTM0_BASE)
 
#define FTM1_BASE   (0x40039000u)
 
#define FTM1   ((FTM_Type *)FTM1_BASE)
 
#define FTM2_BASE   (0x400B8000u)
 
#define FTM2   ((FTM_Type *)FTM2_BASE)
 
#define FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE }
 
#define FTM_BASE_PTRS   { FTM0, FTM1, FTM2 }
 
#define FTM_IRQS   { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }
 
#define FTM_CnSC_COUNT   (8U)
 
#define FTM_CnV_COUNT   (8U)
 
#define FTM_CnSC_COUNT   (8U)
 
#define FTM_CnV_COUNT   (8U)
 
#define FTM_CnSC_COUNT   (8U)
 
#define FTM_CnV_COUNT   (8U)
 
#define FTM_CnSC_COUNT   (8U)
 
#define FTM_CnV_COUNT   (8U)
 

SC - Status And Control

#define FTM_SC_PS_MASK   (0x7U)
 
#define FTM_SC_PS_SHIFT   (0U)
 
#define FTM_SC_PS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
 
#define FTM_SC_CLKS_MASK   (0x18U)
 
#define FTM_SC_CLKS_SHIFT   (3U)
 
#define FTM_SC_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
 
#define FTM_SC_CPWMS_MASK   (0x20U)
 
#define FTM_SC_CPWMS_SHIFT   (5U)
 
#define FTM_SC_CPWMS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
 
#define FTM_SC_TOIE_MASK   (0x40U)
 
#define FTM_SC_TOIE_SHIFT   (6U)
 
#define FTM_SC_TOIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
 
#define FTM_SC_TOF_MASK   (0x80U)
 
#define FTM_SC_TOF_SHIFT   (7U)
 
#define FTM_SC_TOF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
 
#define FTM_SC_PS_MASK   0x7u
 
#define FTM_SC_PS_SHIFT   0
 
#define FTM_SC_PS(x)   (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
 
#define FTM_SC_CLKS_MASK   0x18u
 
#define FTM_SC_CLKS_SHIFT   3
 
#define FTM_SC_CLKS(x)   (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
 
#define FTM_SC_CPWMS_MASK   0x20u
 
#define FTM_SC_CPWMS_SHIFT   5
 
#define FTM_SC_TOIE_MASK   0x40u
 
#define FTM_SC_TOIE_SHIFT   6
 
#define FTM_SC_TOF_MASK   0x80u
 
#define FTM_SC_TOF_SHIFT   7
 
#define FTM_SC_PS_MASK   (0x7U)
 
#define FTM_SC_PS_SHIFT   (0U)
 
#define FTM_SC_PS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
 
#define FTM_SC_CLKS_MASK   (0x18U)
 
#define FTM_SC_CLKS_SHIFT   (3U)
 
#define FTM_SC_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
 
#define FTM_SC_CPWMS_MASK   (0x20U)
 
#define FTM_SC_CPWMS_SHIFT   (5U)
 
#define FTM_SC_CPWMS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
 
#define FTM_SC_TOIE_MASK   (0x40U)
 
#define FTM_SC_TOIE_SHIFT   (6U)
 
#define FTM_SC_TOIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
 
#define FTM_SC_TOF_MASK   (0x80U)
 
#define FTM_SC_TOF_SHIFT   (7U)
 
#define FTM_SC_TOF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
 
#define FTM_SC_PS_MASK   (0x7U)
 
#define FTM_SC_PS_SHIFT   (0U)
 
#define FTM_SC_PS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
 
#define FTM_SC_CLKS_MASK   (0x18U)
 
#define FTM_SC_CLKS_SHIFT   (3U)
 
#define FTM_SC_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
 
#define FTM_SC_CPWMS_MASK   (0x20U)
 
#define FTM_SC_CPWMS_SHIFT   (5U)
 
#define FTM_SC_CPWMS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
 
#define FTM_SC_TOIE_MASK   (0x40U)
 
#define FTM_SC_TOIE_SHIFT   (6U)
 
#define FTM_SC_TOIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
 
#define FTM_SC_TOF_MASK   (0x80U)
 
#define FTM_SC_TOF_SHIFT   (7U)
 
#define FTM_SC_TOF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
 
#define FTM_SC_PS_MASK   (0x7U)
 
#define FTM_SC_PS_SHIFT   (0U)
 
#define FTM_SC_PS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
 
#define FTM_SC_CLKS_MASK   (0x18U)
 
#define FTM_SC_CLKS_SHIFT   (3U)
 
#define FTM_SC_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
 
#define FTM_SC_CPWMS_MASK   (0x20U)
 
#define FTM_SC_CPWMS_SHIFT   (5U)
 
#define FTM_SC_CPWMS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
 
#define FTM_SC_TOIE_MASK   (0x40U)
 
#define FTM_SC_TOIE_SHIFT   (6U)
 
#define FTM_SC_TOIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
 
#define FTM_SC_TOF_MASK   (0x80U)
 
#define FTM_SC_TOF_SHIFT   (7U)
 
#define FTM_SC_TOF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
 
#define FTM_SC_PS_MASK   (0x7U)
 
#define FTM_SC_PS_SHIFT   (0U)
 
#define FTM_SC_PS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
 
#define FTM_SC_CLKS_MASK   (0x18U)
 
#define FTM_SC_CLKS_SHIFT   (3U)
 
#define FTM_SC_CLKS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
 
#define FTM_SC_CPWMS_MASK   (0x20U)
 
#define FTM_SC_CPWMS_SHIFT   (5U)
 
#define FTM_SC_CPWMS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
 
#define FTM_SC_TOIE_MASK   (0x40U)
 
#define FTM_SC_TOIE_SHIFT   (6U)
 
#define FTM_SC_TOIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
 
#define FTM_SC_TOF_MASK   (0x80U)
 
#define FTM_SC_TOF_SHIFT   (7U)
 
#define FTM_SC_TOF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
 

CNT - Counter

#define FTM_CNT_COUNT_MASK   (0xFFFFU)
 
#define FTM_CNT_COUNT_SHIFT   (0U)
 
#define FTM_CNT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
 
#define FTM_CNT_COUNT_MASK   0xFFFFu
 
#define FTM_CNT_COUNT_SHIFT   0
 
#define FTM_CNT_COUNT(x)   (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
 
#define FTM_CNT_COUNT_MASK   (0xFFFFU)
 
#define FTM_CNT_COUNT_SHIFT   (0U)
 
#define FTM_CNT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
 
#define FTM_CNT_COUNT_MASK   (0xFFFFU)
 
#define FTM_CNT_COUNT_SHIFT   (0U)
 
#define FTM_CNT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
 
#define FTM_CNT_COUNT_MASK   (0xFFFFU)
 
#define FTM_CNT_COUNT_SHIFT   (0U)
 
#define FTM_CNT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
 
#define FTM_CNT_COUNT_MASK   (0xFFFFU)
 
#define FTM_CNT_COUNT_SHIFT   (0U)
 
#define FTM_CNT_COUNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
 

MOD - Modulo

#define FTM_MOD_MOD_MASK   (0xFFFFU)
 
#define FTM_MOD_MOD_SHIFT   (0U)
 
#define FTM_MOD_MOD(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
 
#define FTM_MOD_MOD_MASK   0xFFFFu
 
#define FTM_MOD_MOD_SHIFT   0
 
#define FTM_MOD_MOD(x)   (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
 
#define FTM_MOD_MOD_MASK   (0xFFFFU)
 
#define FTM_MOD_MOD_SHIFT   (0U)
 
#define FTM_MOD_MOD(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
 
#define FTM_MOD_MOD_MASK   (0xFFFFU)
 
#define FTM_MOD_MOD_SHIFT   (0U)
 
#define FTM_MOD_MOD(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
 
#define FTM_MOD_MOD_MASK   (0xFFFFU)
 
#define FTM_MOD_MOD_SHIFT   (0U)
 
#define FTM_MOD_MOD(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
 
#define FTM_MOD_MOD_MASK   (0xFFFFU)
 
#define FTM_MOD_MOD_SHIFT   (0U)
 
#define FTM_MOD_MOD(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
 

CnSC - Channel (n) Status And Control

#define FTM_CnSC_DMA_MASK   (0x1U)
 
#define FTM_CnSC_DMA_SHIFT   (0U)
 
#define FTM_CnSC_DMA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
 
#define FTM_CnSC_ELSA_MASK   (0x4U)
 
#define FTM_CnSC_ELSA_SHIFT   (2U)
 
#define FTM_CnSC_ELSA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
 
#define FTM_CnSC_ELSB_MASK   (0x8U)
 
#define FTM_CnSC_ELSB_SHIFT   (3U)
 
#define FTM_CnSC_ELSB(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
 
#define FTM_CnSC_MSA_MASK   (0x10U)
 
#define FTM_CnSC_MSA_SHIFT   (4U)
 
#define FTM_CnSC_MSA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
 
#define FTM_CnSC_MSB_MASK   (0x20U)
 
#define FTM_CnSC_MSB_SHIFT   (5U)
 
#define FTM_CnSC_MSB(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
 
#define FTM_CnSC_CHIE_MASK   (0x40U)
 
#define FTM_CnSC_CHIE_SHIFT   (6U)
 
#define FTM_CnSC_CHIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
 
#define FTM_CnSC_CHF_MASK   (0x80U)
 
#define FTM_CnSC_CHF_SHIFT   (7U)
 
#define FTM_CnSC_CHF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
 
#define FTM_CnSC_DMA_MASK   0x1u
 
#define FTM_CnSC_DMA_SHIFT   0
 
#define FTM_CnSC_ELSA_MASK   0x4u
 
#define FTM_CnSC_ELSA_SHIFT   2
 
#define FTM_CnSC_ELSB_MASK   0x8u
 
#define FTM_CnSC_ELSB_SHIFT   3
 
#define FTM_CnSC_MSA_MASK   0x10u
 
#define FTM_CnSC_MSA_SHIFT   4
 
#define FTM_CnSC_MSB_MASK   0x20u
 
#define FTM_CnSC_MSB_SHIFT   5
 
#define FTM_CnSC_CHIE_MASK   0x40u
 
#define FTM_CnSC_CHIE_SHIFT   6
 
#define FTM_CnSC_CHF_MASK   0x80u
 
#define FTM_CnSC_CHF_SHIFT   7
 
#define FTM_CnSC_DMA_MASK   (0x1U)
 
#define FTM_CnSC_DMA_SHIFT   (0U)
 
#define FTM_CnSC_DMA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
 
#define FTM_CnSC_ELSA_MASK   (0x4U)
 
#define FTM_CnSC_ELSA_SHIFT   (2U)
 
#define FTM_CnSC_ELSA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
 
#define FTM_CnSC_ELSB_MASK   (0x8U)
 
#define FTM_CnSC_ELSB_SHIFT   (3U)
 
#define FTM_CnSC_ELSB(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
 
#define FTM_CnSC_MSA_MASK   (0x10U)
 
#define FTM_CnSC_MSA_SHIFT   (4U)
 
#define FTM_CnSC_MSA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
 
#define FTM_CnSC_MSB_MASK   (0x20U)
 
#define FTM_CnSC_MSB_SHIFT   (5U)
 
#define FTM_CnSC_MSB(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
 
#define FTM_CnSC_CHIE_MASK   (0x40U)
 
#define FTM_CnSC_CHIE_SHIFT   (6U)
 
#define FTM_CnSC_CHIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
 
#define FTM_CnSC_CHF_MASK   (0x80U)
 
#define FTM_CnSC_CHF_SHIFT   (7U)
 
#define FTM_CnSC_CHF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
 
#define FTM_CnSC_DMA_MASK   (0x1U)
 
#define FTM_CnSC_DMA_SHIFT   (0U)
 
#define FTM_CnSC_DMA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
 
#define FTM_CnSC_ELSA_MASK   (0x4U)
 
#define FTM_CnSC_ELSA_SHIFT   (2U)
 
#define FTM_CnSC_ELSA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
 
#define FTM_CnSC_ELSB_MASK   (0x8U)
 
#define FTM_CnSC_ELSB_SHIFT   (3U)
 
#define FTM_CnSC_ELSB(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
 
#define FTM_CnSC_MSA_MASK   (0x10U)
 
#define FTM_CnSC_MSA_SHIFT   (4U)
 
#define FTM_CnSC_MSA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
 
#define FTM_CnSC_MSB_MASK   (0x20U)
 
#define FTM_CnSC_MSB_SHIFT   (5U)
 
#define FTM_CnSC_MSB(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
 
#define FTM_CnSC_CHIE_MASK   (0x40U)
 
#define FTM_CnSC_CHIE_SHIFT   (6U)
 
#define FTM_CnSC_CHIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
 
#define FTM_CnSC_CHF_MASK   (0x80U)
 
#define FTM_CnSC_CHF_SHIFT   (7U)
 
#define FTM_CnSC_CHF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
 
#define FTM_CnSC_DMA_MASK   (0x1U)
 
#define FTM_CnSC_DMA_SHIFT   (0U)
 
#define FTM_CnSC_DMA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
 
#define FTM_CnSC_ELSA_MASK   (0x4U)
 
#define FTM_CnSC_ELSA_SHIFT   (2U)
 
#define FTM_CnSC_ELSA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
 
#define FTM_CnSC_ELSB_MASK   (0x8U)
 
#define FTM_CnSC_ELSB_SHIFT   (3U)
 
#define FTM_CnSC_ELSB(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
 
#define FTM_CnSC_MSA_MASK   (0x10U)
 
#define FTM_CnSC_MSA_SHIFT   (4U)
 
#define FTM_CnSC_MSA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
 
#define FTM_CnSC_MSB_MASK   (0x20U)
 
#define FTM_CnSC_MSB_SHIFT   (5U)
 
#define FTM_CnSC_MSB(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
 
#define FTM_CnSC_CHIE_MASK   (0x40U)
 
#define FTM_CnSC_CHIE_SHIFT   (6U)
 
#define FTM_CnSC_CHIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
 
#define FTM_CnSC_CHF_MASK   (0x80U)
 
#define FTM_CnSC_CHF_SHIFT   (7U)
 
#define FTM_CnSC_CHF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
 
#define FTM_CnSC_DMA_MASK   (0x1U)
 
#define FTM_CnSC_DMA_SHIFT   (0U)
 
#define FTM_CnSC_DMA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
 
#define FTM_CnSC_ICRST_MASK   (0x2U)
 
#define FTM_CnSC_ICRST_SHIFT   (1U)
 
#define FTM_CnSC_ICRST(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
 
#define FTM_CnSC_ELSA_MASK   (0x4U)
 
#define FTM_CnSC_ELSA_SHIFT   (2U)
 
#define FTM_CnSC_ELSA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
 
#define FTM_CnSC_ELSB_MASK   (0x8U)
 
#define FTM_CnSC_ELSB_SHIFT   (3U)
 
#define FTM_CnSC_ELSB(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
 
#define FTM_CnSC_MSA_MASK   (0x10U)
 
#define FTM_CnSC_MSA_SHIFT   (4U)
 
#define FTM_CnSC_MSA(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
 
#define FTM_CnSC_MSB_MASK   (0x20U)
 
#define FTM_CnSC_MSB_SHIFT   (5U)
 
#define FTM_CnSC_MSB(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
 
#define FTM_CnSC_CHIE_MASK   (0x40U)
 
#define FTM_CnSC_CHIE_SHIFT   (6U)
 
#define FTM_CnSC_CHIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
 
#define FTM_CnSC_CHF_MASK   (0x80U)
 
#define FTM_CnSC_CHF_SHIFT   (7U)
 
#define FTM_CnSC_CHF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
 

CnSC - Channel (n) Status And Control

#define FTM_CnSC_COUNT   (8U)
 

CnV - Channel (n) Value

#define FTM_CnV_VAL_MASK   (0xFFFFU)
 
#define FTM_CnV_VAL_SHIFT   (0U)
 
#define FTM_CnV_VAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
 
#define FTM_CnV_VAL_MASK   0xFFFFu
 
#define FTM_CnV_VAL_SHIFT   0
 
#define FTM_CnV_VAL(x)   (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
 
#define FTM_CnV_VAL_MASK   (0xFFFFU)
 
#define FTM_CnV_VAL_SHIFT   (0U)
 
#define FTM_CnV_VAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
 
#define FTM_CnV_VAL_MASK   (0xFFFFU)
 
#define FTM_CnV_VAL_SHIFT   (0U)
 
#define FTM_CnV_VAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
 
#define FTM_CnV_VAL_MASK   (0xFFFFU)
 
#define FTM_CnV_VAL_SHIFT   (0U)
 
#define FTM_CnV_VAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
 
#define FTM_CnV_VAL_MASK   (0xFFFFU)
 
#define FTM_CnV_VAL_SHIFT   (0U)
 
#define FTM_CnV_VAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
 

CnV - Channel (n) Value

#define FTM_CnV_COUNT   (8U)
 

CNTIN - Counter Initial Value

#define FTM_CNTIN_INIT_MASK   (0xFFFFU)
 
#define FTM_CNTIN_INIT_SHIFT   (0U)
 
#define FTM_CNTIN_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
 
#define FTM_CNTIN_INIT_MASK   0xFFFFu
 
#define FTM_CNTIN_INIT_SHIFT   0
 
#define FTM_CNTIN_INIT(x)   (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
 
#define FTM_CNTIN_INIT_MASK   (0xFFFFU)
 
#define FTM_CNTIN_INIT_SHIFT   (0U)
 
#define FTM_CNTIN_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
 
#define FTM_CNTIN_INIT_MASK   (0xFFFFU)
 
#define FTM_CNTIN_INIT_SHIFT   (0U)
 
#define FTM_CNTIN_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
 
#define FTM_CNTIN_INIT_MASK   (0xFFFFU)
 
#define FTM_CNTIN_INIT_SHIFT   (0U)
 
#define FTM_CNTIN_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
 
#define FTM_CNTIN_INIT_MASK   (0xFFFFU)
 
#define FTM_CNTIN_INIT_SHIFT   (0U)
 
#define FTM_CNTIN_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
 

STATUS - Capture And Compare Status

#define FTM_STATUS_CH0F_MASK   (0x1U)
 
#define FTM_STATUS_CH0F_SHIFT   (0U)
 
#define FTM_STATUS_CH0F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
 
#define FTM_STATUS_CH1F_MASK   (0x2U)
 
#define FTM_STATUS_CH1F_SHIFT   (1U)
 
#define FTM_STATUS_CH1F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
 
#define FTM_STATUS_CH2F_MASK   (0x4U)
 
#define FTM_STATUS_CH2F_SHIFT   (2U)
 
#define FTM_STATUS_CH2F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
 
#define FTM_STATUS_CH3F_MASK   (0x8U)
 
#define FTM_STATUS_CH3F_SHIFT   (3U)
 
#define FTM_STATUS_CH3F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
 
#define FTM_STATUS_CH4F_MASK   (0x10U)
 
#define FTM_STATUS_CH4F_SHIFT   (4U)
 
#define FTM_STATUS_CH4F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
 
#define FTM_STATUS_CH5F_MASK   (0x20U)
 
#define FTM_STATUS_CH5F_SHIFT   (5U)
 
#define FTM_STATUS_CH5F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
 
#define FTM_STATUS_CH6F_MASK   (0x40U)
 
#define FTM_STATUS_CH6F_SHIFT   (6U)
 
#define FTM_STATUS_CH6F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
 
#define FTM_STATUS_CH7F_MASK   (0x80U)
 
#define FTM_STATUS_CH7F_SHIFT   (7U)
 
#define FTM_STATUS_CH7F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
 
#define FTM_STATUS_CH0F_MASK   0x1u
 
#define FTM_STATUS_CH0F_SHIFT   0
 
#define FTM_STATUS_CH1F_MASK   0x2u
 
#define FTM_STATUS_CH1F_SHIFT   1
 
#define FTM_STATUS_CH2F_MASK   0x4u
 
#define FTM_STATUS_CH2F_SHIFT   2
 
#define FTM_STATUS_CH3F_MASK   0x8u
 
#define FTM_STATUS_CH3F_SHIFT   3
 
#define FTM_STATUS_CH4F_MASK   0x10u
 
#define FTM_STATUS_CH4F_SHIFT   4
 
#define FTM_STATUS_CH5F_MASK   0x20u
 
#define FTM_STATUS_CH5F_SHIFT   5
 
#define FTM_STATUS_CH6F_MASK   0x40u
 
#define FTM_STATUS_CH6F_SHIFT   6
 
#define FTM_STATUS_CH7F_MASK   0x80u
 
#define FTM_STATUS_CH7F_SHIFT   7
 
#define FTM_STATUS_CH0F_MASK   (0x1U)
 
#define FTM_STATUS_CH0F_SHIFT   (0U)
 
#define FTM_STATUS_CH0F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
 
#define FTM_STATUS_CH1F_MASK   (0x2U)
 
#define FTM_STATUS_CH1F_SHIFT   (1U)
 
#define FTM_STATUS_CH1F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
 
#define FTM_STATUS_CH2F_MASK   (0x4U)
 
#define FTM_STATUS_CH2F_SHIFT   (2U)
 
#define FTM_STATUS_CH2F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
 
#define FTM_STATUS_CH3F_MASK   (0x8U)
 
#define FTM_STATUS_CH3F_SHIFT   (3U)
 
#define FTM_STATUS_CH3F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
 
#define FTM_STATUS_CH4F_MASK   (0x10U)
 
#define FTM_STATUS_CH4F_SHIFT   (4U)
 
#define FTM_STATUS_CH4F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
 
#define FTM_STATUS_CH5F_MASK   (0x20U)
 
#define FTM_STATUS_CH5F_SHIFT   (5U)
 
#define FTM_STATUS_CH5F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
 
#define FTM_STATUS_CH6F_MASK   (0x40U)
 
#define FTM_STATUS_CH6F_SHIFT   (6U)
 
#define FTM_STATUS_CH6F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
 
#define FTM_STATUS_CH7F_MASK   (0x80U)
 
#define FTM_STATUS_CH7F_SHIFT   (7U)
 
#define FTM_STATUS_CH7F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
 
#define FTM_STATUS_CH0F_MASK   (0x1U)
 
#define FTM_STATUS_CH0F_SHIFT   (0U)
 
#define FTM_STATUS_CH0F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
 
#define FTM_STATUS_CH1F_MASK   (0x2U)
 
#define FTM_STATUS_CH1F_SHIFT   (1U)
 
#define FTM_STATUS_CH1F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
 
#define FTM_STATUS_CH2F_MASK   (0x4U)
 
#define FTM_STATUS_CH2F_SHIFT   (2U)
 
#define FTM_STATUS_CH2F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
 
#define FTM_STATUS_CH3F_MASK   (0x8U)
 
#define FTM_STATUS_CH3F_SHIFT   (3U)
 
#define FTM_STATUS_CH3F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
 
#define FTM_STATUS_CH4F_MASK   (0x10U)
 
#define FTM_STATUS_CH4F_SHIFT   (4U)
 
#define FTM_STATUS_CH4F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
 
#define FTM_STATUS_CH5F_MASK   (0x20U)
 
#define FTM_STATUS_CH5F_SHIFT   (5U)
 
#define FTM_STATUS_CH5F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
 
#define FTM_STATUS_CH6F_MASK   (0x40U)
 
#define FTM_STATUS_CH6F_SHIFT   (6U)
 
#define FTM_STATUS_CH6F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
 
#define FTM_STATUS_CH7F_MASK   (0x80U)
 
#define FTM_STATUS_CH7F_SHIFT   (7U)
 
#define FTM_STATUS_CH7F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
 
#define FTM_STATUS_CH0F_MASK   (0x1U)
 
#define FTM_STATUS_CH0F_SHIFT   (0U)
 
#define FTM_STATUS_CH0F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
 
#define FTM_STATUS_CH1F_MASK   (0x2U)
 
#define FTM_STATUS_CH1F_SHIFT   (1U)
 
#define FTM_STATUS_CH1F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
 
#define FTM_STATUS_CH2F_MASK   (0x4U)
 
#define FTM_STATUS_CH2F_SHIFT   (2U)
 
#define FTM_STATUS_CH2F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
 
#define FTM_STATUS_CH3F_MASK   (0x8U)
 
#define FTM_STATUS_CH3F_SHIFT   (3U)
 
#define FTM_STATUS_CH3F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
 
#define FTM_STATUS_CH4F_MASK   (0x10U)
 
#define FTM_STATUS_CH4F_SHIFT   (4U)
 
#define FTM_STATUS_CH4F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
 
#define FTM_STATUS_CH5F_MASK   (0x20U)
 
#define FTM_STATUS_CH5F_SHIFT   (5U)
 
#define FTM_STATUS_CH5F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
 
#define FTM_STATUS_CH6F_MASK   (0x40U)
 
#define FTM_STATUS_CH6F_SHIFT   (6U)
 
#define FTM_STATUS_CH6F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
 
#define FTM_STATUS_CH7F_MASK   (0x80U)
 
#define FTM_STATUS_CH7F_SHIFT   (7U)
 
#define FTM_STATUS_CH7F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
 
#define FTM_STATUS_CH0F_MASK   (0x1U)
 
#define FTM_STATUS_CH0F_SHIFT   (0U)
 
#define FTM_STATUS_CH0F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
 
#define FTM_STATUS_CH1F_MASK   (0x2U)
 
#define FTM_STATUS_CH1F_SHIFT   (1U)
 
#define FTM_STATUS_CH1F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
 
#define FTM_STATUS_CH2F_MASK   (0x4U)
 
#define FTM_STATUS_CH2F_SHIFT   (2U)
 
#define FTM_STATUS_CH2F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
 
#define FTM_STATUS_CH3F_MASK   (0x8U)
 
#define FTM_STATUS_CH3F_SHIFT   (3U)
 
#define FTM_STATUS_CH3F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
 
#define FTM_STATUS_CH4F_MASK   (0x10U)
 
#define FTM_STATUS_CH4F_SHIFT   (4U)
 
#define FTM_STATUS_CH4F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
 
#define FTM_STATUS_CH5F_MASK   (0x20U)
 
#define FTM_STATUS_CH5F_SHIFT   (5U)
 
#define FTM_STATUS_CH5F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
 
#define FTM_STATUS_CH6F_MASK   (0x40U)
 
#define FTM_STATUS_CH6F_SHIFT   (6U)
 
#define FTM_STATUS_CH6F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
 
#define FTM_STATUS_CH7F_MASK   (0x80U)
 
#define FTM_STATUS_CH7F_SHIFT   (7U)
 
#define FTM_STATUS_CH7F(x)   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
 

MODE - Features Mode Selection

#define FTM_MODE_FTMEN_MASK   (0x1U)
 
#define FTM_MODE_FTMEN_SHIFT   (0U)
 
#define FTM_MODE_FTMEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
 
#define FTM_MODE_INIT_MASK   (0x2U)
 
#define FTM_MODE_INIT_SHIFT   (1U)
 
#define FTM_MODE_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
 
#define FTM_MODE_WPDIS_MASK   (0x4U)
 
#define FTM_MODE_WPDIS_SHIFT   (2U)
 
#define FTM_MODE_WPDIS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
 
#define FTM_MODE_PWMSYNC_MASK   (0x8U)
 
#define FTM_MODE_PWMSYNC_SHIFT   (3U)
 
#define FTM_MODE_PWMSYNC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
 
#define FTM_MODE_CAPTEST_MASK   (0x10U)
 
#define FTM_MODE_CAPTEST_SHIFT   (4U)
 
#define FTM_MODE_CAPTEST(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
 
#define FTM_MODE_FAULTM_MASK   (0x60U)
 
#define FTM_MODE_FAULTM_SHIFT   (5U)
 
#define FTM_MODE_FAULTM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
 
#define FTM_MODE_FAULTIE_MASK   (0x80U)
 
#define FTM_MODE_FAULTIE_SHIFT   (7U)
 
#define FTM_MODE_FAULTIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
 
#define FTM_MODE_FTMEN_MASK   0x1u
 
#define FTM_MODE_FTMEN_SHIFT   0
 
#define FTM_MODE_INIT_MASK   0x2u
 
#define FTM_MODE_INIT_SHIFT   1
 
#define FTM_MODE_WPDIS_MASK   0x4u
 
#define FTM_MODE_WPDIS_SHIFT   2
 
#define FTM_MODE_PWMSYNC_MASK   0x8u
 
#define FTM_MODE_PWMSYNC_SHIFT   3
 
#define FTM_MODE_CAPTEST_MASK   0x10u
 
#define FTM_MODE_CAPTEST_SHIFT   4
 
#define FTM_MODE_FAULTM_MASK   0x60u
 
#define FTM_MODE_FAULTM_SHIFT   5
 
#define FTM_MODE_FAULTM(x)   (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
 
#define FTM_MODE_FAULTIE_MASK   0x80u
 
#define FTM_MODE_FAULTIE_SHIFT   7
 
#define FTM_MODE_FTMEN_MASK   (0x1U)
 
#define FTM_MODE_FTMEN_SHIFT   (0U)
 
#define FTM_MODE_FTMEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
 
#define FTM_MODE_INIT_MASK   (0x2U)
 
#define FTM_MODE_INIT_SHIFT   (1U)
 
#define FTM_MODE_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
 
#define FTM_MODE_WPDIS_MASK   (0x4U)
 
#define FTM_MODE_WPDIS_SHIFT   (2U)
 
#define FTM_MODE_WPDIS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
 
#define FTM_MODE_PWMSYNC_MASK   (0x8U)
 
#define FTM_MODE_PWMSYNC_SHIFT   (3U)
 
#define FTM_MODE_PWMSYNC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
 
#define FTM_MODE_CAPTEST_MASK   (0x10U)
 
#define FTM_MODE_CAPTEST_SHIFT   (4U)
 
#define FTM_MODE_CAPTEST(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
 
#define FTM_MODE_FAULTM_MASK   (0x60U)
 
#define FTM_MODE_FAULTM_SHIFT   (5U)
 
#define FTM_MODE_FAULTM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
 
#define FTM_MODE_FAULTIE_MASK   (0x80U)
 
#define FTM_MODE_FAULTIE_SHIFT   (7U)
 
#define FTM_MODE_FAULTIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
 
#define FTM_MODE_FTMEN_MASK   (0x1U)
 
#define FTM_MODE_FTMEN_SHIFT   (0U)
 
#define FTM_MODE_FTMEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
 
#define FTM_MODE_INIT_MASK   (0x2U)
 
#define FTM_MODE_INIT_SHIFT   (1U)
 
#define FTM_MODE_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
 
#define FTM_MODE_WPDIS_MASK   (0x4U)
 
#define FTM_MODE_WPDIS_SHIFT   (2U)
 
#define FTM_MODE_WPDIS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
 
#define FTM_MODE_PWMSYNC_MASK   (0x8U)
 
#define FTM_MODE_PWMSYNC_SHIFT   (3U)
 
#define FTM_MODE_PWMSYNC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
 
#define FTM_MODE_CAPTEST_MASK   (0x10U)
 
#define FTM_MODE_CAPTEST_SHIFT   (4U)
 
#define FTM_MODE_CAPTEST(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
 
#define FTM_MODE_FAULTM_MASK   (0x60U)
 
#define FTM_MODE_FAULTM_SHIFT   (5U)
 
#define FTM_MODE_FAULTM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
 
#define FTM_MODE_FAULTIE_MASK   (0x80U)
 
#define FTM_MODE_FAULTIE_SHIFT   (7U)
 
#define FTM_MODE_FAULTIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
 
#define FTM_MODE_FTMEN_MASK   (0x1U)
 
#define FTM_MODE_FTMEN_SHIFT   (0U)
 
#define FTM_MODE_FTMEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
 
#define FTM_MODE_INIT_MASK   (0x2U)
 
#define FTM_MODE_INIT_SHIFT   (1U)
 
#define FTM_MODE_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
 
#define FTM_MODE_WPDIS_MASK   (0x4U)
 
#define FTM_MODE_WPDIS_SHIFT   (2U)
 
#define FTM_MODE_WPDIS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
 
#define FTM_MODE_PWMSYNC_MASK   (0x8U)
 
#define FTM_MODE_PWMSYNC_SHIFT   (3U)
 
#define FTM_MODE_PWMSYNC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
 
#define FTM_MODE_CAPTEST_MASK   (0x10U)
 
#define FTM_MODE_CAPTEST_SHIFT   (4U)
 
#define FTM_MODE_CAPTEST(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
 
#define FTM_MODE_FAULTM_MASK   (0x60U)
 
#define FTM_MODE_FAULTM_SHIFT   (5U)
 
#define FTM_MODE_FAULTM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
 
#define FTM_MODE_FAULTIE_MASK   (0x80U)
 
#define FTM_MODE_FAULTIE_SHIFT   (7U)
 
#define FTM_MODE_FAULTIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
 
#define FTM_MODE_FTMEN_MASK   (0x1U)
 
#define FTM_MODE_FTMEN_SHIFT   (0U)
 
#define FTM_MODE_FTMEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
 
#define FTM_MODE_INIT_MASK   (0x2U)
 
#define FTM_MODE_INIT_SHIFT   (1U)
 
#define FTM_MODE_INIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
 
#define FTM_MODE_WPDIS_MASK   (0x4U)
 
#define FTM_MODE_WPDIS_SHIFT   (2U)
 
#define FTM_MODE_WPDIS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
 
#define FTM_MODE_PWMSYNC_MASK   (0x8U)
 
#define FTM_MODE_PWMSYNC_SHIFT   (3U)
 
#define FTM_MODE_PWMSYNC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
 
#define FTM_MODE_CAPTEST_MASK   (0x10U)
 
#define FTM_MODE_CAPTEST_SHIFT   (4U)
 
#define FTM_MODE_CAPTEST(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
 
#define FTM_MODE_FAULTM_MASK   (0x60U)
 
#define FTM_MODE_FAULTM_SHIFT   (5U)
 
#define FTM_MODE_FAULTM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
 
#define FTM_MODE_FAULTIE_MASK   (0x80U)
 
#define FTM_MODE_FAULTIE_SHIFT   (7U)
 
#define FTM_MODE_FAULTIE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
 

SYNC - Synchronization

#define FTM_SYNC_CNTMIN_MASK   (0x1U)
 
#define FTM_SYNC_CNTMIN_SHIFT   (0U)
 
#define FTM_SYNC_CNTMIN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
 
#define FTM_SYNC_CNTMAX_MASK   (0x2U)
 
#define FTM_SYNC_CNTMAX_SHIFT   (1U)
 
#define FTM_SYNC_CNTMAX(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
 
#define FTM_SYNC_REINIT_MASK   (0x4U)
 
#define FTM_SYNC_REINIT_SHIFT   (2U)
 
#define FTM_SYNC_REINIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
 
#define FTM_SYNC_SYNCHOM_MASK   (0x8U)
 
#define FTM_SYNC_SYNCHOM_SHIFT   (3U)
 
#define FTM_SYNC_SYNCHOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
 
#define FTM_SYNC_TRIG0_MASK   (0x10U)
 
#define FTM_SYNC_TRIG0_SHIFT   (4U)
 
#define FTM_SYNC_TRIG0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
 
#define FTM_SYNC_TRIG1_MASK   (0x20U)
 
#define FTM_SYNC_TRIG1_SHIFT   (5U)
 
#define FTM_SYNC_TRIG1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
 
#define FTM_SYNC_TRIG2_MASK   (0x40U)
 
#define FTM_SYNC_TRIG2_SHIFT   (6U)
 
#define FTM_SYNC_TRIG2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
 
#define FTM_SYNC_SWSYNC_MASK   (0x80U)
 
#define FTM_SYNC_SWSYNC_SHIFT   (7U)
 
#define FTM_SYNC_SWSYNC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
 
#define FTM_SYNC_CNTMIN_MASK   0x1u
 
#define FTM_SYNC_CNTMIN_SHIFT   0
 
#define FTM_SYNC_CNTMAX_MASK   0x2u
 
#define FTM_SYNC_CNTMAX_SHIFT   1
 
#define FTM_SYNC_REINIT_MASK   0x4u
 
#define FTM_SYNC_REINIT_SHIFT   2
 
#define FTM_SYNC_SYNCHOM_MASK   0x8u
 
#define FTM_SYNC_SYNCHOM_SHIFT   3
 
#define FTM_SYNC_TRIG0_MASK   0x10u
 
#define FTM_SYNC_TRIG0_SHIFT   4
 
#define FTM_SYNC_TRIG1_MASK   0x20u
 
#define FTM_SYNC_TRIG1_SHIFT   5
 
#define FTM_SYNC_TRIG2_MASK   0x40u
 
#define FTM_SYNC_TRIG2_SHIFT   6
 
#define FTM_SYNC_SWSYNC_MASK   0x80u
 
#define FTM_SYNC_SWSYNC_SHIFT   7
 
#define FTM_SYNC_CNTMIN_MASK   (0x1U)
 
#define FTM_SYNC_CNTMIN_SHIFT   (0U)
 
#define FTM_SYNC_CNTMIN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
 
#define FTM_SYNC_CNTMAX_MASK   (0x2U)
 
#define FTM_SYNC_CNTMAX_SHIFT   (1U)
 
#define FTM_SYNC_CNTMAX(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
 
#define FTM_SYNC_REINIT_MASK   (0x4U)
 
#define FTM_SYNC_REINIT_SHIFT   (2U)
 
#define FTM_SYNC_REINIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
 
#define FTM_SYNC_SYNCHOM_MASK   (0x8U)
 
#define FTM_SYNC_SYNCHOM_SHIFT   (3U)
 
#define FTM_SYNC_SYNCHOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
 
#define FTM_SYNC_TRIG0_MASK   (0x10U)
 
#define FTM_SYNC_TRIG0_SHIFT   (4U)
 
#define FTM_SYNC_TRIG0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
 
#define FTM_SYNC_TRIG1_MASK   (0x20U)
 
#define FTM_SYNC_TRIG1_SHIFT   (5U)
 
#define FTM_SYNC_TRIG1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
 
#define FTM_SYNC_TRIG2_MASK   (0x40U)
 
#define FTM_SYNC_TRIG2_SHIFT   (6U)
 
#define FTM_SYNC_TRIG2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
 
#define FTM_SYNC_SWSYNC_MASK   (0x80U)
 
#define FTM_SYNC_SWSYNC_SHIFT   (7U)
 
#define FTM_SYNC_SWSYNC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
 
#define FTM_SYNC_CNTMIN_MASK   (0x1U)
 
#define FTM_SYNC_CNTMIN_SHIFT   (0U)
 
#define FTM_SYNC_CNTMIN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
 
#define FTM_SYNC_CNTMAX_MASK   (0x2U)
 
#define FTM_SYNC_CNTMAX_SHIFT   (1U)
 
#define FTM_SYNC_CNTMAX(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
 
#define FTM_SYNC_REINIT_MASK   (0x4U)
 
#define FTM_SYNC_REINIT_SHIFT   (2U)
 
#define FTM_SYNC_REINIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
 
#define FTM_SYNC_SYNCHOM_MASK   (0x8U)
 
#define FTM_SYNC_SYNCHOM_SHIFT   (3U)
 
#define FTM_SYNC_SYNCHOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
 
#define FTM_SYNC_TRIG0_MASK   (0x10U)
 
#define FTM_SYNC_TRIG0_SHIFT   (4U)
 
#define FTM_SYNC_TRIG0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
 
#define FTM_SYNC_TRIG1_MASK   (0x20U)
 
#define FTM_SYNC_TRIG1_SHIFT   (5U)
 
#define FTM_SYNC_TRIG1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
 
#define FTM_SYNC_TRIG2_MASK   (0x40U)
 
#define FTM_SYNC_TRIG2_SHIFT   (6U)
 
#define FTM_SYNC_TRIG2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
 
#define FTM_SYNC_SWSYNC_MASK   (0x80U)
 
#define FTM_SYNC_SWSYNC_SHIFT   (7U)
 
#define FTM_SYNC_SWSYNC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
 
#define FTM_SYNC_CNTMIN_MASK   (0x1U)
 
#define FTM_SYNC_CNTMIN_SHIFT   (0U)
 
#define FTM_SYNC_CNTMIN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
 
#define FTM_SYNC_CNTMAX_MASK   (0x2U)
 
#define FTM_SYNC_CNTMAX_SHIFT   (1U)
 
#define FTM_SYNC_CNTMAX(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
 
#define FTM_SYNC_REINIT_MASK   (0x4U)
 
#define FTM_SYNC_REINIT_SHIFT   (2U)
 
#define FTM_SYNC_REINIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
 
#define FTM_SYNC_SYNCHOM_MASK   (0x8U)
 
#define FTM_SYNC_SYNCHOM_SHIFT   (3U)
 
#define FTM_SYNC_SYNCHOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
 
#define FTM_SYNC_TRIG0_MASK   (0x10U)
 
#define FTM_SYNC_TRIG0_SHIFT   (4U)
 
#define FTM_SYNC_TRIG0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
 
#define FTM_SYNC_TRIG1_MASK   (0x20U)
 
#define FTM_SYNC_TRIG1_SHIFT   (5U)
 
#define FTM_SYNC_TRIG1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
 
#define FTM_SYNC_TRIG2_MASK   (0x40U)
 
#define FTM_SYNC_TRIG2_SHIFT   (6U)
 
#define FTM_SYNC_TRIG2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
 
#define FTM_SYNC_SWSYNC_MASK   (0x80U)
 
#define FTM_SYNC_SWSYNC_SHIFT   (7U)
 
#define FTM_SYNC_SWSYNC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
 
#define FTM_SYNC_CNTMIN_MASK   (0x1U)
 
#define FTM_SYNC_CNTMIN_SHIFT   (0U)
 
#define FTM_SYNC_CNTMIN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
 
#define FTM_SYNC_CNTMAX_MASK   (0x2U)
 
#define FTM_SYNC_CNTMAX_SHIFT   (1U)
 
#define FTM_SYNC_CNTMAX(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
 
#define FTM_SYNC_REINIT_MASK   (0x4U)
 
#define FTM_SYNC_REINIT_SHIFT   (2U)
 
#define FTM_SYNC_REINIT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
 
#define FTM_SYNC_SYNCHOM_MASK   (0x8U)
 
#define FTM_SYNC_SYNCHOM_SHIFT   (3U)
 
#define FTM_SYNC_SYNCHOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
 
#define FTM_SYNC_TRIG0_MASK   (0x10U)
 
#define FTM_SYNC_TRIG0_SHIFT   (4U)
 
#define FTM_SYNC_TRIG0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
 
#define FTM_SYNC_TRIG1_MASK   (0x20U)
 
#define FTM_SYNC_TRIG1_SHIFT   (5U)
 
#define FTM_SYNC_TRIG1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
 
#define FTM_SYNC_TRIG2_MASK   (0x40U)
 
#define FTM_SYNC_TRIG2_SHIFT   (6U)
 
#define FTM_SYNC_TRIG2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
 
#define FTM_SYNC_SWSYNC_MASK   (0x80U)
 
#define FTM_SYNC_SWSYNC_SHIFT   (7U)
 
#define FTM_SYNC_SWSYNC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
 

OUTINIT - Initial State For Channels Output

#define FTM_OUTINIT_CH0OI_MASK   (0x1U)
 
#define FTM_OUTINIT_CH0OI_SHIFT   (0U)
 
#define FTM_OUTINIT_CH0OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
 
#define FTM_OUTINIT_CH1OI_MASK   (0x2U)
 
#define FTM_OUTINIT_CH1OI_SHIFT   (1U)
 
#define FTM_OUTINIT_CH1OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
 
#define FTM_OUTINIT_CH2OI_MASK   (0x4U)
 
#define FTM_OUTINIT_CH2OI_SHIFT   (2U)
 
#define FTM_OUTINIT_CH2OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
 
#define FTM_OUTINIT_CH3OI_MASK   (0x8U)
 
#define FTM_OUTINIT_CH3OI_SHIFT   (3U)
 
#define FTM_OUTINIT_CH3OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
 
#define FTM_OUTINIT_CH4OI_MASK   (0x10U)
 
#define FTM_OUTINIT_CH4OI_SHIFT   (4U)
 
#define FTM_OUTINIT_CH4OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
 
#define FTM_OUTINIT_CH5OI_MASK   (0x20U)
 
#define FTM_OUTINIT_CH5OI_SHIFT   (5U)
 
#define FTM_OUTINIT_CH5OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
 
#define FTM_OUTINIT_CH6OI_MASK   (0x40U)
 
#define FTM_OUTINIT_CH6OI_SHIFT   (6U)
 
#define FTM_OUTINIT_CH6OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
 
#define FTM_OUTINIT_CH7OI_MASK   (0x80U)
 
#define FTM_OUTINIT_CH7OI_SHIFT   (7U)
 
#define FTM_OUTINIT_CH7OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
 
#define FTM_OUTINIT_CH0OI_MASK   0x1u
 
#define FTM_OUTINIT_CH0OI_SHIFT   0
 
#define FTM_OUTINIT_CH1OI_MASK   0x2u
 
#define FTM_OUTINIT_CH1OI_SHIFT   1
 
#define FTM_OUTINIT_CH2OI_MASK   0x4u
 
#define FTM_OUTINIT_CH2OI_SHIFT   2
 
#define FTM_OUTINIT_CH3OI_MASK   0x8u
 
#define FTM_OUTINIT_CH3OI_SHIFT   3
 
#define FTM_OUTINIT_CH4OI_MASK   0x10u
 
#define FTM_OUTINIT_CH4OI_SHIFT   4
 
#define FTM_OUTINIT_CH5OI_MASK   0x20u
 
#define FTM_OUTINIT_CH5OI_SHIFT   5
 
#define FTM_OUTINIT_CH6OI_MASK   0x40u
 
#define FTM_OUTINIT_CH6OI_SHIFT   6
 
#define FTM_OUTINIT_CH7OI_MASK   0x80u
 
#define FTM_OUTINIT_CH7OI_SHIFT   7
 
#define FTM_OUTINIT_CH0OI_MASK   (0x1U)
 
#define FTM_OUTINIT_CH0OI_SHIFT   (0U)
 
#define FTM_OUTINIT_CH0OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
 
#define FTM_OUTINIT_CH1OI_MASK   (0x2U)
 
#define FTM_OUTINIT_CH1OI_SHIFT   (1U)
 
#define FTM_OUTINIT_CH1OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
 
#define FTM_OUTINIT_CH2OI_MASK   (0x4U)
 
#define FTM_OUTINIT_CH2OI_SHIFT   (2U)
 
#define FTM_OUTINIT_CH2OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
 
#define FTM_OUTINIT_CH3OI_MASK   (0x8U)
 
#define FTM_OUTINIT_CH3OI_SHIFT   (3U)
 
#define FTM_OUTINIT_CH3OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
 
#define FTM_OUTINIT_CH4OI_MASK   (0x10U)
 
#define FTM_OUTINIT_CH4OI_SHIFT   (4U)
 
#define FTM_OUTINIT_CH4OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
 
#define FTM_OUTINIT_CH5OI_MASK   (0x20U)
 
#define FTM_OUTINIT_CH5OI_SHIFT   (5U)
 
#define FTM_OUTINIT_CH5OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
 
#define FTM_OUTINIT_CH6OI_MASK   (0x40U)
 
#define FTM_OUTINIT_CH6OI_SHIFT   (6U)
 
#define FTM_OUTINIT_CH6OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
 
#define FTM_OUTINIT_CH7OI_MASK   (0x80U)
 
#define FTM_OUTINIT_CH7OI_SHIFT   (7U)
 
#define FTM_OUTINIT_CH7OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
 
#define FTM_OUTINIT_CH0OI_MASK   (0x1U)
 
#define FTM_OUTINIT_CH0OI_SHIFT   (0U)
 
#define FTM_OUTINIT_CH0OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
 
#define FTM_OUTINIT_CH1OI_MASK   (0x2U)
 
#define FTM_OUTINIT_CH1OI_SHIFT   (1U)
 
#define FTM_OUTINIT_CH1OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
 
#define FTM_OUTINIT_CH2OI_MASK   (0x4U)
 
#define FTM_OUTINIT_CH2OI_SHIFT   (2U)
 
#define FTM_OUTINIT_CH2OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
 
#define FTM_OUTINIT_CH3OI_MASK   (0x8U)
 
#define FTM_OUTINIT_CH3OI_SHIFT   (3U)
 
#define FTM_OUTINIT_CH3OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
 
#define FTM_OUTINIT_CH4OI_MASK   (0x10U)
 
#define FTM_OUTINIT_CH4OI_SHIFT   (4U)
 
#define FTM_OUTINIT_CH4OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
 
#define FTM_OUTINIT_CH5OI_MASK   (0x20U)
 
#define FTM_OUTINIT_CH5OI_SHIFT   (5U)
 
#define FTM_OUTINIT_CH5OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
 
#define FTM_OUTINIT_CH6OI_MASK   (0x40U)
 
#define FTM_OUTINIT_CH6OI_SHIFT   (6U)
 
#define FTM_OUTINIT_CH6OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
 
#define FTM_OUTINIT_CH7OI_MASK   (0x80U)
 
#define FTM_OUTINIT_CH7OI_SHIFT   (7U)
 
#define FTM_OUTINIT_CH7OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
 
#define FTM_OUTINIT_CH0OI_MASK   (0x1U)
 
#define FTM_OUTINIT_CH0OI_SHIFT   (0U)
 
#define FTM_OUTINIT_CH0OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
 
#define FTM_OUTINIT_CH1OI_MASK   (0x2U)
 
#define FTM_OUTINIT_CH1OI_SHIFT   (1U)
 
#define FTM_OUTINIT_CH1OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
 
#define FTM_OUTINIT_CH2OI_MASK   (0x4U)
 
#define FTM_OUTINIT_CH2OI_SHIFT   (2U)
 
#define FTM_OUTINIT_CH2OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
 
#define FTM_OUTINIT_CH3OI_MASK   (0x8U)
 
#define FTM_OUTINIT_CH3OI_SHIFT   (3U)
 
#define FTM_OUTINIT_CH3OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
 
#define FTM_OUTINIT_CH4OI_MASK   (0x10U)
 
#define FTM_OUTINIT_CH4OI_SHIFT   (4U)
 
#define FTM_OUTINIT_CH4OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
 
#define FTM_OUTINIT_CH5OI_MASK   (0x20U)
 
#define FTM_OUTINIT_CH5OI_SHIFT   (5U)
 
#define FTM_OUTINIT_CH5OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
 
#define FTM_OUTINIT_CH6OI_MASK   (0x40U)
 
#define FTM_OUTINIT_CH6OI_SHIFT   (6U)
 
#define FTM_OUTINIT_CH6OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
 
#define FTM_OUTINIT_CH7OI_MASK   (0x80U)
 
#define FTM_OUTINIT_CH7OI_SHIFT   (7U)
 
#define FTM_OUTINIT_CH7OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
 
#define FTM_OUTINIT_CH0OI_MASK   (0x1U)
 
#define FTM_OUTINIT_CH0OI_SHIFT   (0U)
 
#define FTM_OUTINIT_CH0OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
 
#define FTM_OUTINIT_CH1OI_MASK   (0x2U)
 
#define FTM_OUTINIT_CH1OI_SHIFT   (1U)
 
#define FTM_OUTINIT_CH1OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
 
#define FTM_OUTINIT_CH2OI_MASK   (0x4U)
 
#define FTM_OUTINIT_CH2OI_SHIFT   (2U)
 
#define FTM_OUTINIT_CH2OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
 
#define FTM_OUTINIT_CH3OI_MASK   (0x8U)
 
#define FTM_OUTINIT_CH3OI_SHIFT   (3U)
 
#define FTM_OUTINIT_CH3OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
 
#define FTM_OUTINIT_CH4OI_MASK   (0x10U)
 
#define FTM_OUTINIT_CH4OI_SHIFT   (4U)
 
#define FTM_OUTINIT_CH4OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
 
#define FTM_OUTINIT_CH5OI_MASK   (0x20U)
 
#define FTM_OUTINIT_CH5OI_SHIFT   (5U)
 
#define FTM_OUTINIT_CH5OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
 
#define FTM_OUTINIT_CH6OI_MASK   (0x40U)
 
#define FTM_OUTINIT_CH6OI_SHIFT   (6U)
 
#define FTM_OUTINIT_CH6OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
 
#define FTM_OUTINIT_CH7OI_MASK   (0x80U)
 
#define FTM_OUTINIT_CH7OI_SHIFT   (7U)
 
#define FTM_OUTINIT_CH7OI(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
 

OUTMASK - Output Mask

#define FTM_OUTMASK_CH0OM_MASK   (0x1U)
 
#define FTM_OUTMASK_CH0OM_SHIFT   (0U)
 
#define FTM_OUTMASK_CH0OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
 
#define FTM_OUTMASK_CH1OM_MASK   (0x2U)
 
#define FTM_OUTMASK_CH1OM_SHIFT   (1U)
 
#define FTM_OUTMASK_CH1OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
 
#define FTM_OUTMASK_CH2OM_MASK   (0x4U)
 
#define FTM_OUTMASK_CH2OM_SHIFT   (2U)
 
#define FTM_OUTMASK_CH2OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
 
#define FTM_OUTMASK_CH3OM_MASK   (0x8U)
 
#define FTM_OUTMASK_CH3OM_SHIFT   (3U)
 
#define FTM_OUTMASK_CH3OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
 
#define FTM_OUTMASK_CH4OM_MASK   (0x10U)
 
#define FTM_OUTMASK_CH4OM_SHIFT   (4U)
 
#define FTM_OUTMASK_CH4OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
 
#define FTM_OUTMASK_CH5OM_MASK   (0x20U)
 
#define FTM_OUTMASK_CH5OM_SHIFT   (5U)
 
#define FTM_OUTMASK_CH5OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
 
#define FTM_OUTMASK_CH6OM_MASK   (0x40U)
 
#define FTM_OUTMASK_CH6OM_SHIFT   (6U)
 
#define FTM_OUTMASK_CH6OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
 
#define FTM_OUTMASK_CH7OM_MASK   (0x80U)
 
#define FTM_OUTMASK_CH7OM_SHIFT   (7U)
 
#define FTM_OUTMASK_CH7OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
 
#define FTM_OUTMASK_CH0OM_MASK   0x1u
 
#define FTM_OUTMASK_CH0OM_SHIFT   0
 
#define FTM_OUTMASK_CH1OM_MASK   0x2u
 
#define FTM_OUTMASK_CH1OM_SHIFT   1
 
#define FTM_OUTMASK_CH2OM_MASK   0x4u
 
#define FTM_OUTMASK_CH2OM_SHIFT   2
 
#define FTM_OUTMASK_CH3OM_MASK   0x8u
 
#define FTM_OUTMASK_CH3OM_SHIFT   3
 
#define FTM_OUTMASK_CH4OM_MASK   0x10u
 
#define FTM_OUTMASK_CH4OM_SHIFT   4
 
#define FTM_OUTMASK_CH5OM_MASK   0x20u
 
#define FTM_OUTMASK_CH5OM_SHIFT   5
 
#define FTM_OUTMASK_CH6OM_MASK   0x40u
 
#define FTM_OUTMASK_CH6OM_SHIFT   6
 
#define FTM_OUTMASK_CH7OM_MASK   0x80u
 
#define FTM_OUTMASK_CH7OM_SHIFT   7
 
#define FTM_OUTMASK_CH0OM_MASK   (0x1U)
 
#define FTM_OUTMASK_CH0OM_SHIFT   (0U)
 
#define FTM_OUTMASK_CH0OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
 
#define FTM_OUTMASK_CH1OM_MASK   (0x2U)
 
#define FTM_OUTMASK_CH1OM_SHIFT   (1U)
 
#define FTM_OUTMASK_CH1OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
 
#define FTM_OUTMASK_CH2OM_MASK   (0x4U)
 
#define FTM_OUTMASK_CH2OM_SHIFT   (2U)
 
#define FTM_OUTMASK_CH2OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
 
#define FTM_OUTMASK_CH3OM_MASK   (0x8U)
 
#define FTM_OUTMASK_CH3OM_SHIFT   (3U)
 
#define FTM_OUTMASK_CH3OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
 
#define FTM_OUTMASK_CH4OM_MASK   (0x10U)
 
#define FTM_OUTMASK_CH4OM_SHIFT   (4U)
 
#define FTM_OUTMASK_CH4OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
 
#define FTM_OUTMASK_CH5OM_MASK   (0x20U)
 
#define FTM_OUTMASK_CH5OM_SHIFT   (5U)
 
#define FTM_OUTMASK_CH5OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
 
#define FTM_OUTMASK_CH6OM_MASK   (0x40U)
 
#define FTM_OUTMASK_CH6OM_SHIFT   (6U)
 
#define FTM_OUTMASK_CH6OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
 
#define FTM_OUTMASK_CH7OM_MASK   (0x80U)
 
#define FTM_OUTMASK_CH7OM_SHIFT   (7U)
 
#define FTM_OUTMASK_CH7OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
 
#define FTM_OUTMASK_CH0OM_MASK   (0x1U)
 
#define FTM_OUTMASK_CH0OM_SHIFT   (0U)
 
#define FTM_OUTMASK_CH0OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
 
#define FTM_OUTMASK_CH1OM_MASK   (0x2U)
 
#define FTM_OUTMASK_CH1OM_SHIFT   (1U)
 
#define FTM_OUTMASK_CH1OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
 
#define FTM_OUTMASK_CH2OM_MASK   (0x4U)
 
#define FTM_OUTMASK_CH2OM_SHIFT   (2U)
 
#define FTM_OUTMASK_CH2OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
 
#define FTM_OUTMASK_CH3OM_MASK   (0x8U)
 
#define FTM_OUTMASK_CH3OM_SHIFT   (3U)
 
#define FTM_OUTMASK_CH3OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
 
#define FTM_OUTMASK_CH4OM_MASK   (0x10U)
 
#define FTM_OUTMASK_CH4OM_SHIFT   (4U)
 
#define FTM_OUTMASK_CH4OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
 
#define FTM_OUTMASK_CH5OM_MASK   (0x20U)
 
#define FTM_OUTMASK_CH5OM_SHIFT   (5U)
 
#define FTM_OUTMASK_CH5OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
 
#define FTM_OUTMASK_CH6OM_MASK   (0x40U)
 
#define FTM_OUTMASK_CH6OM_SHIFT   (6U)
 
#define FTM_OUTMASK_CH6OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
 
#define FTM_OUTMASK_CH7OM_MASK   (0x80U)
 
#define FTM_OUTMASK_CH7OM_SHIFT   (7U)
 
#define FTM_OUTMASK_CH7OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
 
#define FTM_OUTMASK_CH0OM_MASK   (0x1U)
 
#define FTM_OUTMASK_CH0OM_SHIFT   (0U)
 
#define FTM_OUTMASK_CH0OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
 
#define FTM_OUTMASK_CH1OM_MASK   (0x2U)
 
#define FTM_OUTMASK_CH1OM_SHIFT   (1U)
 
#define FTM_OUTMASK_CH1OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
 
#define FTM_OUTMASK_CH2OM_MASK   (0x4U)
 
#define FTM_OUTMASK_CH2OM_SHIFT   (2U)
 
#define FTM_OUTMASK_CH2OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
 
#define FTM_OUTMASK_CH3OM_MASK   (0x8U)
 
#define FTM_OUTMASK_CH3OM_SHIFT   (3U)
 
#define FTM_OUTMASK_CH3OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
 
#define FTM_OUTMASK_CH4OM_MASK   (0x10U)
 
#define FTM_OUTMASK_CH4OM_SHIFT   (4U)
 
#define FTM_OUTMASK_CH4OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
 
#define FTM_OUTMASK_CH5OM_MASK   (0x20U)
 
#define FTM_OUTMASK_CH5OM_SHIFT   (5U)
 
#define FTM_OUTMASK_CH5OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
 
#define FTM_OUTMASK_CH6OM_MASK   (0x40U)
 
#define FTM_OUTMASK_CH6OM_SHIFT   (6U)
 
#define FTM_OUTMASK_CH6OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
 
#define FTM_OUTMASK_CH7OM_MASK   (0x80U)
 
#define FTM_OUTMASK_CH7OM_SHIFT   (7U)
 
#define FTM_OUTMASK_CH7OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
 
#define FTM_OUTMASK_CH0OM_MASK   (0x1U)
 
#define FTM_OUTMASK_CH0OM_SHIFT   (0U)
 
#define FTM_OUTMASK_CH0OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
 
#define FTM_OUTMASK_CH1OM_MASK   (0x2U)
 
#define FTM_OUTMASK_CH1OM_SHIFT   (1U)
 
#define FTM_OUTMASK_CH1OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
 
#define FTM_OUTMASK_CH2OM_MASK   (0x4U)
 
#define FTM_OUTMASK_CH2OM_SHIFT   (2U)
 
#define FTM_OUTMASK_CH2OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
 
#define FTM_OUTMASK_CH3OM_MASK   (0x8U)
 
#define FTM_OUTMASK_CH3OM_SHIFT   (3U)
 
#define FTM_OUTMASK_CH3OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
 
#define FTM_OUTMASK_CH4OM_MASK   (0x10U)
 
#define FTM_OUTMASK_CH4OM_SHIFT   (4U)
 
#define FTM_OUTMASK_CH4OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
 
#define FTM_OUTMASK_CH5OM_MASK   (0x20U)
 
#define FTM_OUTMASK_CH5OM_SHIFT   (5U)
 
#define FTM_OUTMASK_CH5OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
 
#define FTM_OUTMASK_CH6OM_MASK   (0x40U)
 
#define FTM_OUTMASK_CH6OM_SHIFT   (6U)
 
#define FTM_OUTMASK_CH6OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
 
#define FTM_OUTMASK_CH7OM_MASK   (0x80U)
 
#define FTM_OUTMASK_CH7OM_SHIFT   (7U)
 
#define FTM_OUTMASK_CH7OM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
 

COMBINE - Function For Linked Channels

#define FTM_COMBINE_COMBINE0_MASK   (0x1U)
 
#define FTM_COMBINE_COMBINE0_SHIFT   (0U)
 
#define FTM_COMBINE_COMBINE0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
 
#define FTM_COMBINE_COMP0_MASK   (0x2U)
 
#define FTM_COMBINE_COMP0_SHIFT   (1U)
 
#define FTM_COMBINE_COMP0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
 
#define FTM_COMBINE_DECAPEN0_MASK   (0x4U)
 
#define FTM_COMBINE_DECAPEN0_SHIFT   (2U)
 
#define FTM_COMBINE_DECAPEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
 
#define FTM_COMBINE_DECAP0_MASK   (0x8U)
 
#define FTM_COMBINE_DECAP0_SHIFT   (3U)
 
#define FTM_COMBINE_DECAP0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
 
#define FTM_COMBINE_DTEN0_MASK   (0x10U)
 
#define FTM_COMBINE_DTEN0_SHIFT   (4U)
 
#define FTM_COMBINE_DTEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
 
#define FTM_COMBINE_SYNCEN0_MASK   (0x20U)
 
#define FTM_COMBINE_SYNCEN0_SHIFT   (5U)
 
#define FTM_COMBINE_SYNCEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
 
#define FTM_COMBINE_FAULTEN0_MASK   (0x40U)
 
#define FTM_COMBINE_FAULTEN0_SHIFT   (6U)
 
#define FTM_COMBINE_FAULTEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
 
#define FTM_COMBINE_COMBINE1_MASK   (0x100U)
 
#define FTM_COMBINE_COMBINE1_SHIFT   (8U)
 
#define FTM_COMBINE_COMBINE1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
 
#define FTM_COMBINE_COMP1_MASK   (0x200U)
 
#define FTM_COMBINE_COMP1_SHIFT   (9U)
 
#define FTM_COMBINE_COMP1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
 
#define FTM_COMBINE_DECAPEN1_MASK   (0x400U)
 
#define FTM_COMBINE_DECAPEN1_SHIFT   (10U)
 
#define FTM_COMBINE_DECAPEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
 
#define FTM_COMBINE_DECAP1_MASK   (0x800U)
 
#define FTM_COMBINE_DECAP1_SHIFT   (11U)
 
#define FTM_COMBINE_DECAP1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
 
#define FTM_COMBINE_DTEN1_MASK   (0x1000U)
 
#define FTM_COMBINE_DTEN1_SHIFT   (12U)
 
#define FTM_COMBINE_DTEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
 
#define FTM_COMBINE_SYNCEN1_MASK   (0x2000U)
 
#define FTM_COMBINE_SYNCEN1_SHIFT   (13U)
 
#define FTM_COMBINE_SYNCEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
 
#define FTM_COMBINE_FAULTEN1_MASK   (0x4000U)
 
#define FTM_COMBINE_FAULTEN1_SHIFT   (14U)
 
#define FTM_COMBINE_FAULTEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
 
#define FTM_COMBINE_COMBINE2_MASK   (0x10000U)
 
#define FTM_COMBINE_COMBINE2_SHIFT   (16U)
 
#define FTM_COMBINE_COMBINE2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
 
#define FTM_COMBINE_COMP2_MASK   (0x20000U)
 
#define FTM_COMBINE_COMP2_SHIFT   (17U)
 
#define FTM_COMBINE_COMP2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
 
#define FTM_COMBINE_DECAPEN2_MASK   (0x40000U)
 
#define FTM_COMBINE_DECAPEN2_SHIFT   (18U)
 
#define FTM_COMBINE_DECAPEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
 
#define FTM_COMBINE_DECAP2_MASK   (0x80000U)
 
#define FTM_COMBINE_DECAP2_SHIFT   (19U)
 
#define FTM_COMBINE_DECAP2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
 
#define FTM_COMBINE_DTEN2_MASK   (0x100000U)
 
#define FTM_COMBINE_DTEN2_SHIFT   (20U)
 
#define FTM_COMBINE_DTEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
 
#define FTM_COMBINE_SYNCEN2_MASK   (0x200000U)
 
#define FTM_COMBINE_SYNCEN2_SHIFT   (21U)
 
#define FTM_COMBINE_SYNCEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
 
#define FTM_COMBINE_FAULTEN2_MASK   (0x400000U)
 
#define FTM_COMBINE_FAULTEN2_SHIFT   (22U)
 
#define FTM_COMBINE_FAULTEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
 
#define FTM_COMBINE_COMBINE3_MASK   (0x1000000U)
 
#define FTM_COMBINE_COMBINE3_SHIFT   (24U)
 
#define FTM_COMBINE_COMBINE3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
 
#define FTM_COMBINE_COMP3_MASK   (0x2000000U)
 
#define FTM_COMBINE_COMP3_SHIFT   (25U)
 
#define FTM_COMBINE_COMP3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
 
#define FTM_COMBINE_DECAPEN3_MASK   (0x4000000U)
 
#define FTM_COMBINE_DECAPEN3_SHIFT   (26U)
 
#define FTM_COMBINE_DECAPEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
 
#define FTM_COMBINE_DECAP3_MASK   (0x8000000U)
 
#define FTM_COMBINE_DECAP3_SHIFT   (27U)
 
#define FTM_COMBINE_DECAP3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
 
#define FTM_COMBINE_DTEN3_MASK   (0x10000000U)
 
#define FTM_COMBINE_DTEN3_SHIFT   (28U)
 
#define FTM_COMBINE_DTEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
 
#define FTM_COMBINE_SYNCEN3_MASK   (0x20000000U)
 
#define FTM_COMBINE_SYNCEN3_SHIFT   (29U)
 
#define FTM_COMBINE_SYNCEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
 
#define FTM_COMBINE_FAULTEN3_MASK   (0x40000000U)
 
#define FTM_COMBINE_FAULTEN3_SHIFT   (30U)
 
#define FTM_COMBINE_FAULTEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
 
#define FTM_COMBINE_COMBINE0_MASK   0x1u
 
#define FTM_COMBINE_COMBINE0_SHIFT   0
 
#define FTM_COMBINE_COMP0_MASK   0x2u
 
#define FTM_COMBINE_COMP0_SHIFT   1
 
#define FTM_COMBINE_DECAPEN0_MASK   0x4u
 
#define FTM_COMBINE_DECAPEN0_SHIFT   2
 
#define FTM_COMBINE_DECAP0_MASK   0x8u
 
#define FTM_COMBINE_DECAP0_SHIFT   3
 
#define FTM_COMBINE_DTEN0_MASK   0x10u
 
#define FTM_COMBINE_DTEN0_SHIFT   4
 
#define FTM_COMBINE_SYNCEN0_MASK   0x20u
 
#define FTM_COMBINE_SYNCEN0_SHIFT   5
 
#define FTM_COMBINE_FAULTEN0_MASK   0x40u
 
#define FTM_COMBINE_FAULTEN0_SHIFT   6
 
#define FTM_COMBINE_COMBINE1_MASK   0x100u
 
#define FTM_COMBINE_COMBINE1_SHIFT   8
 
#define FTM_COMBINE_COMP1_MASK   0x200u
 
#define FTM_COMBINE_COMP1_SHIFT   9
 
#define FTM_COMBINE_DECAPEN1_MASK   0x400u
 
#define FTM_COMBINE_DECAPEN1_SHIFT   10
 
#define FTM_COMBINE_DECAP1_MASK   0x800u
 
#define FTM_COMBINE_DECAP1_SHIFT   11
 
#define FTM_COMBINE_DTEN1_MASK   0x1000u
 
#define FTM_COMBINE_DTEN1_SHIFT   12
 
#define FTM_COMBINE_SYNCEN1_MASK   0x2000u
 
#define FTM_COMBINE_SYNCEN1_SHIFT   13
 
#define FTM_COMBINE_FAULTEN1_MASK   0x4000u
 
#define FTM_COMBINE_FAULTEN1_SHIFT   14
 
#define FTM_COMBINE_COMBINE2_MASK   0x10000u
 
#define FTM_COMBINE_COMBINE2_SHIFT   16
 
#define FTM_COMBINE_COMP2_MASK   0x20000u
 
#define FTM_COMBINE_COMP2_SHIFT   17
 
#define FTM_COMBINE_DECAPEN2_MASK   0x40000u
 
#define FTM_COMBINE_DECAPEN2_SHIFT   18
 
#define FTM_COMBINE_DECAP2_MASK   0x80000u
 
#define FTM_COMBINE_DECAP2_SHIFT   19
 
#define FTM_COMBINE_DTEN2_MASK   0x100000u
 
#define FTM_COMBINE_DTEN2_SHIFT   20
 
#define FTM_COMBINE_SYNCEN2_MASK   0x200000u
 
#define FTM_COMBINE_SYNCEN2_SHIFT   21
 
#define FTM_COMBINE_FAULTEN2_MASK   0x400000u
 
#define FTM_COMBINE_FAULTEN2_SHIFT   22
 
#define FTM_COMBINE_COMBINE3_MASK   0x1000000u
 
#define FTM_COMBINE_COMBINE3_SHIFT   24
 
#define FTM_COMBINE_COMP3_MASK   0x2000000u
 
#define FTM_COMBINE_COMP3_SHIFT   25
 
#define FTM_COMBINE_DECAPEN3_MASK   0x4000000u
 
#define FTM_COMBINE_DECAPEN3_SHIFT   26
 
#define FTM_COMBINE_DECAP3_MASK   0x8000000u
 
#define FTM_COMBINE_DECAP3_SHIFT   27
 
#define FTM_COMBINE_DTEN3_MASK   0x10000000u
 
#define FTM_COMBINE_DTEN3_SHIFT   28
 
#define FTM_COMBINE_SYNCEN3_MASK   0x20000000u
 
#define FTM_COMBINE_SYNCEN3_SHIFT   29
 
#define FTM_COMBINE_FAULTEN3_MASK   0x40000000u
 
#define FTM_COMBINE_FAULTEN3_SHIFT   30
 
#define FTM_COMBINE_COMBINE0_MASK   (0x1U)
 
#define FTM_COMBINE_COMBINE0_SHIFT   (0U)
 
#define FTM_COMBINE_COMBINE0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
 
#define FTM_COMBINE_COMP0_MASK   (0x2U)
 
#define FTM_COMBINE_COMP0_SHIFT   (1U)
 
#define FTM_COMBINE_COMP0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
 
#define FTM_COMBINE_DECAPEN0_MASK   (0x4U)
 
#define FTM_COMBINE_DECAPEN0_SHIFT   (2U)
 
#define FTM_COMBINE_DECAPEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
 
#define FTM_COMBINE_DECAP0_MASK   (0x8U)
 
#define FTM_COMBINE_DECAP0_SHIFT   (3U)
 
#define FTM_COMBINE_DECAP0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
 
#define FTM_COMBINE_DTEN0_MASK   (0x10U)
 
#define FTM_COMBINE_DTEN0_SHIFT   (4U)
 
#define FTM_COMBINE_DTEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
 
#define FTM_COMBINE_SYNCEN0_MASK   (0x20U)
 
#define FTM_COMBINE_SYNCEN0_SHIFT   (5U)
 
#define FTM_COMBINE_SYNCEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
 
#define FTM_COMBINE_FAULTEN0_MASK   (0x40U)
 
#define FTM_COMBINE_FAULTEN0_SHIFT   (6U)
 
#define FTM_COMBINE_FAULTEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
 
#define FTM_COMBINE_COMBINE1_MASK   (0x100U)
 
#define FTM_COMBINE_COMBINE1_SHIFT   (8U)
 
#define FTM_COMBINE_COMBINE1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
 
#define FTM_COMBINE_COMP1_MASK   (0x200U)
 
#define FTM_COMBINE_COMP1_SHIFT   (9U)
 
#define FTM_COMBINE_COMP1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
 
#define FTM_COMBINE_DECAPEN1_MASK   (0x400U)
 
#define FTM_COMBINE_DECAPEN1_SHIFT   (10U)
 
#define FTM_COMBINE_DECAPEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
 
#define FTM_COMBINE_DECAP1_MASK   (0x800U)
 
#define FTM_COMBINE_DECAP1_SHIFT   (11U)
 
#define FTM_COMBINE_DECAP1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
 
#define FTM_COMBINE_DTEN1_MASK   (0x1000U)
 
#define FTM_COMBINE_DTEN1_SHIFT   (12U)
 
#define FTM_COMBINE_DTEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
 
#define FTM_COMBINE_SYNCEN1_MASK   (0x2000U)
 
#define FTM_COMBINE_SYNCEN1_SHIFT   (13U)
 
#define FTM_COMBINE_SYNCEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
 
#define FTM_COMBINE_FAULTEN1_MASK   (0x4000U)
 
#define FTM_COMBINE_FAULTEN1_SHIFT   (14U)
 
#define FTM_COMBINE_FAULTEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
 
#define FTM_COMBINE_COMBINE2_MASK   (0x10000U)
 
#define FTM_COMBINE_COMBINE2_SHIFT   (16U)
 
#define FTM_COMBINE_COMBINE2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
 
#define FTM_COMBINE_COMP2_MASK   (0x20000U)
 
#define FTM_COMBINE_COMP2_SHIFT   (17U)
 
#define FTM_COMBINE_COMP2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
 
#define FTM_COMBINE_DECAPEN2_MASK   (0x40000U)
 
#define FTM_COMBINE_DECAPEN2_SHIFT   (18U)
 
#define FTM_COMBINE_DECAPEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
 
#define FTM_COMBINE_DECAP2_MASK   (0x80000U)
 
#define FTM_COMBINE_DECAP2_SHIFT   (19U)
 
#define FTM_COMBINE_DECAP2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
 
#define FTM_COMBINE_DTEN2_MASK   (0x100000U)
 
#define FTM_COMBINE_DTEN2_SHIFT   (20U)
 
#define FTM_COMBINE_DTEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
 
#define FTM_COMBINE_SYNCEN2_MASK   (0x200000U)
 
#define FTM_COMBINE_SYNCEN2_SHIFT   (21U)
 
#define FTM_COMBINE_SYNCEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
 
#define FTM_COMBINE_FAULTEN2_MASK   (0x400000U)
 
#define FTM_COMBINE_FAULTEN2_SHIFT   (22U)
 
#define FTM_COMBINE_FAULTEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
 
#define FTM_COMBINE_COMBINE3_MASK   (0x1000000U)
 
#define FTM_COMBINE_COMBINE3_SHIFT   (24U)
 
#define FTM_COMBINE_COMBINE3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
 
#define FTM_COMBINE_COMP3_MASK   (0x2000000U)
 
#define FTM_COMBINE_COMP3_SHIFT   (25U)
 
#define FTM_COMBINE_COMP3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
 
#define FTM_COMBINE_DECAPEN3_MASK   (0x4000000U)
 
#define FTM_COMBINE_DECAPEN3_SHIFT   (26U)
 
#define FTM_COMBINE_DECAPEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
 
#define FTM_COMBINE_DECAP3_MASK   (0x8000000U)
 
#define FTM_COMBINE_DECAP3_SHIFT   (27U)
 
#define FTM_COMBINE_DECAP3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
 
#define FTM_COMBINE_DTEN3_MASK   (0x10000000U)
 
#define FTM_COMBINE_DTEN3_SHIFT   (28U)
 
#define FTM_COMBINE_DTEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
 
#define FTM_COMBINE_SYNCEN3_MASK   (0x20000000U)
 
#define FTM_COMBINE_SYNCEN3_SHIFT   (29U)
 
#define FTM_COMBINE_SYNCEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
 
#define FTM_COMBINE_FAULTEN3_MASK   (0x40000000U)
 
#define FTM_COMBINE_FAULTEN3_SHIFT   (30U)
 
#define FTM_COMBINE_FAULTEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
 
#define FTM_COMBINE_COMBINE0_MASK   (0x1U)
 
#define FTM_COMBINE_COMBINE0_SHIFT   (0U)
 
#define FTM_COMBINE_COMBINE0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
 
#define FTM_COMBINE_COMP0_MASK   (0x2U)
 
#define FTM_COMBINE_COMP0_SHIFT   (1U)
 
#define FTM_COMBINE_COMP0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
 
#define FTM_COMBINE_DECAPEN0_MASK   (0x4U)
 
#define FTM_COMBINE_DECAPEN0_SHIFT   (2U)
 
#define FTM_COMBINE_DECAPEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
 
#define FTM_COMBINE_DECAP0_MASK   (0x8U)
 
#define FTM_COMBINE_DECAP0_SHIFT   (3U)
 
#define FTM_COMBINE_DECAP0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
 
#define FTM_COMBINE_DTEN0_MASK   (0x10U)
 
#define FTM_COMBINE_DTEN0_SHIFT   (4U)
 
#define FTM_COMBINE_DTEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
 
#define FTM_COMBINE_SYNCEN0_MASK   (0x20U)
 
#define FTM_COMBINE_SYNCEN0_SHIFT   (5U)
 
#define FTM_COMBINE_SYNCEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
 
#define FTM_COMBINE_FAULTEN0_MASK   (0x40U)
 
#define FTM_COMBINE_FAULTEN0_SHIFT   (6U)
 
#define FTM_COMBINE_FAULTEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
 
#define FTM_COMBINE_COMBINE1_MASK   (0x100U)
 
#define FTM_COMBINE_COMBINE1_SHIFT   (8U)
 
#define FTM_COMBINE_COMBINE1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
 
#define FTM_COMBINE_COMP1_MASK   (0x200U)
 
#define FTM_COMBINE_COMP1_SHIFT   (9U)
 
#define FTM_COMBINE_COMP1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
 
#define FTM_COMBINE_DECAPEN1_MASK   (0x400U)
 
#define FTM_COMBINE_DECAPEN1_SHIFT   (10U)
 
#define FTM_COMBINE_DECAPEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
 
#define FTM_COMBINE_DECAP1_MASK   (0x800U)
 
#define FTM_COMBINE_DECAP1_SHIFT   (11U)
 
#define FTM_COMBINE_DECAP1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
 
#define FTM_COMBINE_DTEN1_MASK   (0x1000U)
 
#define FTM_COMBINE_DTEN1_SHIFT   (12U)
 
#define FTM_COMBINE_DTEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
 
#define FTM_COMBINE_SYNCEN1_MASK   (0x2000U)
 
#define FTM_COMBINE_SYNCEN1_SHIFT   (13U)
 
#define FTM_COMBINE_SYNCEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
 
#define FTM_COMBINE_FAULTEN1_MASK   (0x4000U)
 
#define FTM_COMBINE_FAULTEN1_SHIFT   (14U)
 
#define FTM_COMBINE_FAULTEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
 
#define FTM_COMBINE_COMBINE2_MASK   (0x10000U)
 
#define FTM_COMBINE_COMBINE2_SHIFT   (16U)
 
#define FTM_COMBINE_COMBINE2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
 
#define FTM_COMBINE_COMP2_MASK   (0x20000U)
 
#define FTM_COMBINE_COMP2_SHIFT   (17U)
 
#define FTM_COMBINE_COMP2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
 
#define FTM_COMBINE_DECAPEN2_MASK   (0x40000U)
 
#define FTM_COMBINE_DECAPEN2_SHIFT   (18U)
 
#define FTM_COMBINE_DECAPEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
 
#define FTM_COMBINE_DECAP2_MASK   (0x80000U)
 
#define FTM_COMBINE_DECAP2_SHIFT   (19U)
 
#define FTM_COMBINE_DECAP2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
 
#define FTM_COMBINE_DTEN2_MASK   (0x100000U)
 
#define FTM_COMBINE_DTEN2_SHIFT   (20U)
 
#define FTM_COMBINE_DTEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
 
#define FTM_COMBINE_SYNCEN2_MASK   (0x200000U)
 
#define FTM_COMBINE_SYNCEN2_SHIFT   (21U)
 
#define FTM_COMBINE_SYNCEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
 
#define FTM_COMBINE_FAULTEN2_MASK   (0x400000U)
 
#define FTM_COMBINE_FAULTEN2_SHIFT   (22U)
 
#define FTM_COMBINE_FAULTEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
 
#define FTM_COMBINE_COMBINE3_MASK   (0x1000000U)
 
#define FTM_COMBINE_COMBINE3_SHIFT   (24U)
 
#define FTM_COMBINE_COMBINE3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
 
#define FTM_COMBINE_COMP3_MASK   (0x2000000U)
 
#define FTM_COMBINE_COMP3_SHIFT   (25U)
 
#define FTM_COMBINE_COMP3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
 
#define FTM_COMBINE_DECAPEN3_MASK   (0x4000000U)
 
#define FTM_COMBINE_DECAPEN3_SHIFT   (26U)
 
#define FTM_COMBINE_DECAPEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
 
#define FTM_COMBINE_DECAP3_MASK   (0x8000000U)
 
#define FTM_COMBINE_DECAP3_SHIFT   (27U)
 
#define FTM_COMBINE_DECAP3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
 
#define FTM_COMBINE_DTEN3_MASK   (0x10000000U)
 
#define FTM_COMBINE_DTEN3_SHIFT   (28U)
 
#define FTM_COMBINE_DTEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
 
#define FTM_COMBINE_SYNCEN3_MASK   (0x20000000U)
 
#define FTM_COMBINE_SYNCEN3_SHIFT   (29U)
 
#define FTM_COMBINE_SYNCEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
 
#define FTM_COMBINE_FAULTEN3_MASK   (0x40000000U)
 
#define FTM_COMBINE_FAULTEN3_SHIFT   (30U)
 
#define FTM_COMBINE_FAULTEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
 
#define FTM_COMBINE_COMBINE0_MASK   (0x1U)
 
#define FTM_COMBINE_COMBINE0_SHIFT   (0U)
 
#define FTM_COMBINE_COMBINE0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
 
#define FTM_COMBINE_COMP0_MASK   (0x2U)
 
#define FTM_COMBINE_COMP0_SHIFT   (1U)
 
#define FTM_COMBINE_COMP0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
 
#define FTM_COMBINE_DECAPEN0_MASK   (0x4U)
 
#define FTM_COMBINE_DECAPEN0_SHIFT   (2U)
 
#define FTM_COMBINE_DECAPEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
 
#define FTM_COMBINE_DECAP0_MASK   (0x8U)
 
#define FTM_COMBINE_DECAP0_SHIFT   (3U)
 
#define FTM_COMBINE_DECAP0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
 
#define FTM_COMBINE_DTEN0_MASK   (0x10U)
 
#define FTM_COMBINE_DTEN0_SHIFT   (4U)
 
#define FTM_COMBINE_DTEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
 
#define FTM_COMBINE_SYNCEN0_MASK   (0x20U)
 
#define FTM_COMBINE_SYNCEN0_SHIFT   (5U)
 
#define FTM_COMBINE_SYNCEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
 
#define FTM_COMBINE_FAULTEN0_MASK   (0x40U)
 
#define FTM_COMBINE_FAULTEN0_SHIFT   (6U)
 
#define FTM_COMBINE_FAULTEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
 
#define FTM_COMBINE_COMBINE1_MASK   (0x100U)
 
#define FTM_COMBINE_COMBINE1_SHIFT   (8U)
 
#define FTM_COMBINE_COMBINE1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
 
#define FTM_COMBINE_COMP1_MASK   (0x200U)
 
#define FTM_COMBINE_COMP1_SHIFT   (9U)
 
#define FTM_COMBINE_COMP1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
 
#define FTM_COMBINE_DECAPEN1_MASK   (0x400U)
 
#define FTM_COMBINE_DECAPEN1_SHIFT   (10U)
 
#define FTM_COMBINE_DECAPEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
 
#define FTM_COMBINE_DECAP1_MASK   (0x800U)
 
#define FTM_COMBINE_DECAP1_SHIFT   (11U)
 
#define FTM_COMBINE_DECAP1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
 
#define FTM_COMBINE_DTEN1_MASK   (0x1000U)
 
#define FTM_COMBINE_DTEN1_SHIFT   (12U)
 
#define FTM_COMBINE_DTEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
 
#define FTM_COMBINE_SYNCEN1_MASK   (0x2000U)
 
#define FTM_COMBINE_SYNCEN1_SHIFT   (13U)
 
#define FTM_COMBINE_SYNCEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
 
#define FTM_COMBINE_FAULTEN1_MASK   (0x4000U)
 
#define FTM_COMBINE_FAULTEN1_SHIFT   (14U)
 
#define FTM_COMBINE_FAULTEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
 
#define FTM_COMBINE_COMBINE2_MASK   (0x10000U)
 
#define FTM_COMBINE_COMBINE2_SHIFT   (16U)
 
#define FTM_COMBINE_COMBINE2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
 
#define FTM_COMBINE_COMP2_MASK   (0x20000U)
 
#define FTM_COMBINE_COMP2_SHIFT   (17U)
 
#define FTM_COMBINE_COMP2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
 
#define FTM_COMBINE_DECAPEN2_MASK   (0x40000U)
 
#define FTM_COMBINE_DECAPEN2_SHIFT   (18U)
 
#define FTM_COMBINE_DECAPEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
 
#define FTM_COMBINE_DECAP2_MASK   (0x80000U)
 
#define FTM_COMBINE_DECAP2_SHIFT   (19U)
 
#define FTM_COMBINE_DECAP2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
 
#define FTM_COMBINE_DTEN2_MASK   (0x100000U)
 
#define FTM_COMBINE_DTEN2_SHIFT   (20U)
 
#define FTM_COMBINE_DTEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
 
#define FTM_COMBINE_SYNCEN2_MASK   (0x200000U)
 
#define FTM_COMBINE_SYNCEN2_SHIFT   (21U)
 
#define FTM_COMBINE_SYNCEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
 
#define FTM_COMBINE_FAULTEN2_MASK   (0x400000U)
 
#define FTM_COMBINE_FAULTEN2_SHIFT   (22U)
 
#define FTM_COMBINE_FAULTEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
 
#define FTM_COMBINE_COMBINE3_MASK   (0x1000000U)
 
#define FTM_COMBINE_COMBINE3_SHIFT   (24U)
 
#define FTM_COMBINE_COMBINE3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
 
#define FTM_COMBINE_COMP3_MASK   (0x2000000U)
 
#define FTM_COMBINE_COMP3_SHIFT   (25U)
 
#define FTM_COMBINE_COMP3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
 
#define FTM_COMBINE_DECAPEN3_MASK   (0x4000000U)
 
#define FTM_COMBINE_DECAPEN3_SHIFT   (26U)
 
#define FTM_COMBINE_DECAPEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
 
#define FTM_COMBINE_DECAP3_MASK   (0x8000000U)
 
#define FTM_COMBINE_DECAP3_SHIFT   (27U)
 
#define FTM_COMBINE_DECAP3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
 
#define FTM_COMBINE_DTEN3_MASK   (0x10000000U)
 
#define FTM_COMBINE_DTEN3_SHIFT   (28U)
 
#define FTM_COMBINE_DTEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
 
#define FTM_COMBINE_SYNCEN3_MASK   (0x20000000U)
 
#define FTM_COMBINE_SYNCEN3_SHIFT   (29U)
 
#define FTM_COMBINE_SYNCEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
 
#define FTM_COMBINE_FAULTEN3_MASK   (0x40000000U)
 
#define FTM_COMBINE_FAULTEN3_SHIFT   (30U)
 
#define FTM_COMBINE_FAULTEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
 
#define FTM_COMBINE_COMBINE0_MASK   (0x1U)
 
#define FTM_COMBINE_COMBINE0_SHIFT   (0U)
 
#define FTM_COMBINE_COMBINE0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
 
#define FTM_COMBINE_COMP0_MASK   (0x2U)
 
#define FTM_COMBINE_COMP0_SHIFT   (1U)
 
#define FTM_COMBINE_COMP0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
 
#define FTM_COMBINE_DECAPEN0_MASK   (0x4U)
 
#define FTM_COMBINE_DECAPEN0_SHIFT   (2U)
 
#define FTM_COMBINE_DECAPEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
 
#define FTM_COMBINE_DECAP0_MASK   (0x8U)
 
#define FTM_COMBINE_DECAP0_SHIFT   (3U)
 
#define FTM_COMBINE_DECAP0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
 
#define FTM_COMBINE_DTEN0_MASK   (0x10U)
 
#define FTM_COMBINE_DTEN0_SHIFT   (4U)
 
#define FTM_COMBINE_DTEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
 
#define FTM_COMBINE_SYNCEN0_MASK   (0x20U)
 
#define FTM_COMBINE_SYNCEN0_SHIFT   (5U)
 
#define FTM_COMBINE_SYNCEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
 
#define FTM_COMBINE_FAULTEN0_MASK   (0x40U)
 
#define FTM_COMBINE_FAULTEN0_SHIFT   (6U)
 
#define FTM_COMBINE_FAULTEN0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
 
#define FTM_COMBINE_COMBINE1_MASK   (0x100U)
 
#define FTM_COMBINE_COMBINE1_SHIFT   (8U)
 
#define FTM_COMBINE_COMBINE1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
 
#define FTM_COMBINE_COMP1_MASK   (0x200U)
 
#define FTM_COMBINE_COMP1_SHIFT   (9U)
 
#define FTM_COMBINE_COMP1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
 
#define FTM_COMBINE_DECAPEN1_MASK   (0x400U)
 
#define FTM_COMBINE_DECAPEN1_SHIFT   (10U)
 
#define FTM_COMBINE_DECAPEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
 
#define FTM_COMBINE_DECAP1_MASK   (0x800U)
 
#define FTM_COMBINE_DECAP1_SHIFT   (11U)
 
#define FTM_COMBINE_DECAP1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
 
#define FTM_COMBINE_DTEN1_MASK   (0x1000U)
 
#define FTM_COMBINE_DTEN1_SHIFT   (12U)
 
#define FTM_COMBINE_DTEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
 
#define FTM_COMBINE_SYNCEN1_MASK   (0x2000U)
 
#define FTM_COMBINE_SYNCEN1_SHIFT   (13U)
 
#define FTM_COMBINE_SYNCEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
 
#define FTM_COMBINE_FAULTEN1_MASK   (0x4000U)
 
#define FTM_COMBINE_FAULTEN1_SHIFT   (14U)
 
#define FTM_COMBINE_FAULTEN1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
 
#define FTM_COMBINE_COMBINE2_MASK   (0x10000U)
 
#define FTM_COMBINE_COMBINE2_SHIFT   (16U)
 
#define FTM_COMBINE_COMBINE2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
 
#define FTM_COMBINE_COMP2_MASK   (0x20000U)
 
#define FTM_COMBINE_COMP2_SHIFT   (17U)
 
#define FTM_COMBINE_COMP2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
 
#define FTM_COMBINE_DECAPEN2_MASK   (0x40000U)
 
#define FTM_COMBINE_DECAPEN2_SHIFT   (18U)
 
#define FTM_COMBINE_DECAPEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
 
#define FTM_COMBINE_DECAP2_MASK   (0x80000U)
 
#define FTM_COMBINE_DECAP2_SHIFT   (19U)
 
#define FTM_COMBINE_DECAP2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
 
#define FTM_COMBINE_DTEN2_MASK   (0x100000U)
 
#define FTM_COMBINE_DTEN2_SHIFT   (20U)
 
#define FTM_COMBINE_DTEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
 
#define FTM_COMBINE_SYNCEN2_MASK   (0x200000U)
 
#define FTM_COMBINE_SYNCEN2_SHIFT   (21U)
 
#define FTM_COMBINE_SYNCEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
 
#define FTM_COMBINE_FAULTEN2_MASK   (0x400000U)
 
#define FTM_COMBINE_FAULTEN2_SHIFT   (22U)
 
#define FTM_COMBINE_FAULTEN2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
 
#define FTM_COMBINE_COMBINE3_MASK   (0x1000000U)
 
#define FTM_COMBINE_COMBINE3_SHIFT   (24U)
 
#define FTM_COMBINE_COMBINE3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
 
#define FTM_COMBINE_COMP3_MASK   (0x2000000U)
 
#define FTM_COMBINE_COMP3_SHIFT   (25U)
 
#define FTM_COMBINE_COMP3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
 
#define FTM_COMBINE_DECAPEN3_MASK   (0x4000000U)
 
#define FTM_COMBINE_DECAPEN3_SHIFT   (26U)
 
#define FTM_COMBINE_DECAPEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
 
#define FTM_COMBINE_DECAP3_MASK   (0x8000000U)
 
#define FTM_COMBINE_DECAP3_SHIFT   (27U)
 
#define FTM_COMBINE_DECAP3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
 
#define FTM_COMBINE_DTEN3_MASK   (0x10000000U)
 
#define FTM_COMBINE_DTEN3_SHIFT   (28U)
 
#define FTM_COMBINE_DTEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
 
#define FTM_COMBINE_SYNCEN3_MASK   (0x20000000U)
 
#define FTM_COMBINE_SYNCEN3_SHIFT   (29U)
 
#define FTM_COMBINE_SYNCEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
 
#define FTM_COMBINE_FAULTEN3_MASK   (0x40000000U)
 
#define FTM_COMBINE_FAULTEN3_SHIFT   (30U)
 
#define FTM_COMBINE_FAULTEN3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
 

DEADTIME - Deadtime Insertion Control

#define FTM_DEADTIME_DTVAL_MASK   (0x3FU)
 
#define FTM_DEADTIME_DTVAL_SHIFT   (0U)
 
#define FTM_DEADTIME_DTVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
 
#define FTM_DEADTIME_DTPS_MASK   (0xC0U)
 
#define FTM_DEADTIME_DTPS_SHIFT   (6U)
 
#define FTM_DEADTIME_DTPS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
 
#define FTM_DEADTIME_DTVAL_MASK   0x3Fu
 
#define FTM_DEADTIME_DTVAL_SHIFT   0
 
#define FTM_DEADTIME_DTVAL(x)   (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
 
#define FTM_DEADTIME_DTPS_MASK   0xC0u
 
#define FTM_DEADTIME_DTPS_SHIFT   6
 
#define FTM_DEADTIME_DTPS(x)   (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
 
#define FTM_DEADTIME_DTVAL_MASK   (0x3FU)
 
#define FTM_DEADTIME_DTVAL_SHIFT   (0U)
 
#define FTM_DEADTIME_DTVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
 
#define FTM_DEADTIME_DTPS_MASK   (0xC0U)
 
#define FTM_DEADTIME_DTPS_SHIFT   (6U)
 
#define FTM_DEADTIME_DTPS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
 
#define FTM_DEADTIME_DTVAL_MASK   (0x3FU)
 
#define FTM_DEADTIME_DTVAL_SHIFT   (0U)
 
#define FTM_DEADTIME_DTVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
 
#define FTM_DEADTIME_DTPS_MASK   (0xC0U)
 
#define FTM_DEADTIME_DTPS_SHIFT   (6U)
 
#define FTM_DEADTIME_DTPS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
 
#define FTM_DEADTIME_DTVAL_MASK   (0x3FU)
 
#define FTM_DEADTIME_DTVAL_SHIFT   (0U)
 
#define FTM_DEADTIME_DTVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
 
#define FTM_DEADTIME_DTPS_MASK   (0xC0U)
 
#define FTM_DEADTIME_DTPS_SHIFT   (6U)
 
#define FTM_DEADTIME_DTPS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
 
#define FTM_DEADTIME_DTVAL_MASK   (0x3FU)
 
#define FTM_DEADTIME_DTVAL_SHIFT   (0U)
 
#define FTM_DEADTIME_DTVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
 
#define FTM_DEADTIME_DTPS_MASK   (0xC0U)
 
#define FTM_DEADTIME_DTPS_SHIFT   (6U)
 
#define FTM_DEADTIME_DTPS(x)   (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
 

EXTTRIG - FTM External Trigger

#define FTM_EXTTRIG_CH2TRIG_MASK   (0x1U)
 
#define FTM_EXTTRIG_CH2TRIG_SHIFT   (0U)
 
#define FTM_EXTTRIG_CH2TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
 
#define FTM_EXTTRIG_CH3TRIG_MASK   (0x2U)
 
#define FTM_EXTTRIG_CH3TRIG_SHIFT   (1U)
 
#define FTM_EXTTRIG_CH3TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
 
#define FTM_EXTTRIG_CH4TRIG_MASK   (0x4U)
 
#define FTM_EXTTRIG_CH4TRIG_SHIFT   (2U)
 
#define FTM_EXTTRIG_CH4TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
 
#define FTM_EXTTRIG_CH5TRIG_MASK   (0x8U)
 
#define FTM_EXTTRIG_CH5TRIG_SHIFT   (3U)
 
#define FTM_EXTTRIG_CH5TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
 
#define FTM_EXTTRIG_CH0TRIG_MASK   (0x10U)
 
#define FTM_EXTTRIG_CH0TRIG_SHIFT   (4U)
 
#define FTM_EXTTRIG_CH0TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
 
#define FTM_EXTTRIG_CH1TRIG_MASK   (0x20U)
 
#define FTM_EXTTRIG_CH1TRIG_SHIFT   (5U)
 
#define FTM_EXTTRIG_CH1TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
 
#define FTM_EXTTRIG_INITTRIGEN_MASK   (0x40U)
 
#define FTM_EXTTRIG_INITTRIGEN_SHIFT   (6U)
 
#define FTM_EXTTRIG_INITTRIGEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
 
#define FTM_EXTTRIG_TRIGF_MASK   (0x80U)
 
#define FTM_EXTTRIG_TRIGF_SHIFT   (7U)
 
#define FTM_EXTTRIG_TRIGF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
 
#define FTM_EXTTRIG_CH2TRIG_MASK   0x1u
 
#define FTM_EXTTRIG_CH2TRIG_SHIFT   0
 
#define FTM_EXTTRIG_CH3TRIG_MASK   0x2u
 
#define FTM_EXTTRIG_CH3TRIG_SHIFT   1
 
#define FTM_EXTTRIG_CH4TRIG_MASK   0x4u
 
#define FTM_EXTTRIG_CH4TRIG_SHIFT   2
 
#define FTM_EXTTRIG_CH5TRIG_MASK   0x8u
 
#define FTM_EXTTRIG_CH5TRIG_SHIFT   3
 
#define FTM_EXTTRIG_CH0TRIG_MASK   0x10u
 
#define FTM_EXTTRIG_CH0TRIG_SHIFT   4
 
#define FTM_EXTTRIG_CH1TRIG_MASK   0x20u
 
#define FTM_EXTTRIG_CH1TRIG_SHIFT   5
 
#define FTM_EXTTRIG_INITTRIGEN_MASK   0x40u
 
#define FTM_EXTTRIG_INITTRIGEN_SHIFT   6
 
#define FTM_EXTTRIG_TRIGF_MASK   0x80u
 
#define FTM_EXTTRIG_TRIGF_SHIFT   7
 
#define FTM_EXTTRIG_CH2TRIG_MASK   (0x1U)
 
#define FTM_EXTTRIG_CH2TRIG_SHIFT   (0U)
 
#define FTM_EXTTRIG_CH2TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
 
#define FTM_EXTTRIG_CH3TRIG_MASK   (0x2U)
 
#define FTM_EXTTRIG_CH3TRIG_SHIFT   (1U)
 
#define FTM_EXTTRIG_CH3TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
 
#define FTM_EXTTRIG_CH4TRIG_MASK   (0x4U)
 
#define FTM_EXTTRIG_CH4TRIG_SHIFT   (2U)
 
#define FTM_EXTTRIG_CH4TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
 
#define FTM_EXTTRIG_CH5TRIG_MASK   (0x8U)
 
#define FTM_EXTTRIG_CH5TRIG_SHIFT   (3U)
 
#define FTM_EXTTRIG_CH5TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
 
#define FTM_EXTTRIG_CH0TRIG_MASK   (0x10U)
 
#define FTM_EXTTRIG_CH0TRIG_SHIFT   (4U)
 
#define FTM_EXTTRIG_CH0TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
 
#define FTM_EXTTRIG_CH1TRIG_MASK   (0x20U)
 
#define FTM_EXTTRIG_CH1TRIG_SHIFT   (5U)
 
#define FTM_EXTTRIG_CH1TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
 
#define FTM_EXTTRIG_INITTRIGEN_MASK   (0x40U)
 
#define FTM_EXTTRIG_INITTRIGEN_SHIFT   (6U)
 
#define FTM_EXTTRIG_INITTRIGEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
 
#define FTM_EXTTRIG_TRIGF_MASK   (0x80U)
 
#define FTM_EXTTRIG_TRIGF_SHIFT   (7U)
 
#define FTM_EXTTRIG_TRIGF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
 
#define FTM_EXTTRIG_CH2TRIG_MASK   (0x1U)
 
#define FTM_EXTTRIG_CH2TRIG_SHIFT   (0U)
 
#define FTM_EXTTRIG_CH2TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
 
#define FTM_EXTTRIG_CH3TRIG_MASK   (0x2U)
 
#define FTM_EXTTRIG_CH3TRIG_SHIFT   (1U)
 
#define FTM_EXTTRIG_CH3TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
 
#define FTM_EXTTRIG_CH4TRIG_MASK   (0x4U)
 
#define FTM_EXTTRIG_CH4TRIG_SHIFT   (2U)
 
#define FTM_EXTTRIG_CH4TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
 
#define FTM_EXTTRIG_CH5TRIG_MASK   (0x8U)
 
#define FTM_EXTTRIG_CH5TRIG_SHIFT   (3U)
 
#define FTM_EXTTRIG_CH5TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
 
#define FTM_EXTTRIG_CH0TRIG_MASK   (0x10U)
 
#define FTM_EXTTRIG_CH0TRIG_SHIFT   (4U)
 
#define FTM_EXTTRIG_CH0TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
 
#define FTM_EXTTRIG_CH1TRIG_MASK   (0x20U)
 
#define FTM_EXTTRIG_CH1TRIG_SHIFT   (5U)
 
#define FTM_EXTTRIG_CH1TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
 
#define FTM_EXTTRIG_INITTRIGEN_MASK   (0x40U)
 
#define FTM_EXTTRIG_INITTRIGEN_SHIFT   (6U)
 
#define FTM_EXTTRIG_INITTRIGEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
 
#define FTM_EXTTRIG_TRIGF_MASK   (0x80U)
 
#define FTM_EXTTRIG_TRIGF_SHIFT   (7U)
 
#define FTM_EXTTRIG_TRIGF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
 
#define FTM_EXTTRIG_CH2TRIG_MASK   (0x1U)
 
#define FTM_EXTTRIG_CH2TRIG_SHIFT   (0U)
 
#define FTM_EXTTRIG_CH2TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
 
#define FTM_EXTTRIG_CH3TRIG_MASK   (0x2U)
 
#define FTM_EXTTRIG_CH3TRIG_SHIFT   (1U)
 
#define FTM_EXTTRIG_CH3TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
 
#define FTM_EXTTRIG_CH4TRIG_MASK   (0x4U)
 
#define FTM_EXTTRIG_CH4TRIG_SHIFT   (2U)
 
#define FTM_EXTTRIG_CH4TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
 
#define FTM_EXTTRIG_CH5TRIG_MASK   (0x8U)
 
#define FTM_EXTTRIG_CH5TRIG_SHIFT   (3U)
 
#define FTM_EXTTRIG_CH5TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
 
#define FTM_EXTTRIG_CH0TRIG_MASK   (0x10U)
 
#define FTM_EXTTRIG_CH0TRIG_SHIFT   (4U)
 
#define FTM_EXTTRIG_CH0TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
 
#define FTM_EXTTRIG_CH1TRIG_MASK   (0x20U)
 
#define FTM_EXTTRIG_CH1TRIG_SHIFT   (5U)
 
#define FTM_EXTTRIG_CH1TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
 
#define FTM_EXTTRIG_INITTRIGEN_MASK   (0x40U)
 
#define FTM_EXTTRIG_INITTRIGEN_SHIFT   (6U)
 
#define FTM_EXTTRIG_INITTRIGEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
 
#define FTM_EXTTRIG_TRIGF_MASK   (0x80U)
 
#define FTM_EXTTRIG_TRIGF_SHIFT   (7U)
 
#define FTM_EXTTRIG_TRIGF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
 
#define FTM_EXTTRIG_CH2TRIG_MASK   (0x1U)
 
#define FTM_EXTTRIG_CH2TRIG_SHIFT   (0U)
 
#define FTM_EXTTRIG_CH2TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
 
#define FTM_EXTTRIG_CH3TRIG_MASK   (0x2U)
 
#define FTM_EXTTRIG_CH3TRIG_SHIFT   (1U)
 
#define FTM_EXTTRIG_CH3TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
 
#define FTM_EXTTRIG_CH4TRIG_MASK   (0x4U)
 
#define FTM_EXTTRIG_CH4TRIG_SHIFT   (2U)
 
#define FTM_EXTTRIG_CH4TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
 
#define FTM_EXTTRIG_CH5TRIG_MASK   (0x8U)
 
#define FTM_EXTTRIG_CH5TRIG_SHIFT   (3U)
 
#define FTM_EXTTRIG_CH5TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
 
#define FTM_EXTTRIG_CH0TRIG_MASK   (0x10U)
 
#define FTM_EXTTRIG_CH0TRIG_SHIFT   (4U)
 
#define FTM_EXTTRIG_CH0TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
 
#define FTM_EXTTRIG_CH1TRIG_MASK   (0x20U)
 
#define FTM_EXTTRIG_CH1TRIG_SHIFT   (5U)
 
#define FTM_EXTTRIG_CH1TRIG(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
 
#define FTM_EXTTRIG_INITTRIGEN_MASK   (0x40U)
 
#define FTM_EXTTRIG_INITTRIGEN_SHIFT   (6U)
 
#define FTM_EXTTRIG_INITTRIGEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
 
#define FTM_EXTTRIG_TRIGF_MASK   (0x80U)
 
#define FTM_EXTTRIG_TRIGF_SHIFT   (7U)
 
#define FTM_EXTTRIG_TRIGF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
 

POL - Channels Polarity

#define FTM_POL_POL0_MASK   (0x1U)
 
#define FTM_POL_POL0_SHIFT   (0U)
 
#define FTM_POL_POL0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
 
#define FTM_POL_POL1_MASK   (0x2U)
 
#define FTM_POL_POL1_SHIFT   (1U)
 
#define FTM_POL_POL1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
 
#define FTM_POL_POL2_MASK   (0x4U)
 
#define FTM_POL_POL2_SHIFT   (2U)
 
#define FTM_POL_POL2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
 
#define FTM_POL_POL3_MASK   (0x8U)
 
#define FTM_POL_POL3_SHIFT   (3U)
 
#define FTM_POL_POL3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
 
#define FTM_POL_POL4_MASK   (0x10U)
 
#define FTM_POL_POL4_SHIFT   (4U)
 
#define FTM_POL_POL4(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
 
#define FTM_POL_POL5_MASK   (0x20U)
 
#define FTM_POL_POL5_SHIFT   (5U)
 
#define FTM_POL_POL5(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
 
#define FTM_POL_POL6_MASK   (0x40U)
 
#define FTM_POL_POL6_SHIFT   (6U)
 
#define FTM_POL_POL6(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
 
#define FTM_POL_POL7_MASK   (0x80U)
 
#define FTM_POL_POL7_SHIFT   (7U)
 
#define FTM_POL_POL7(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
 
#define FTM_POL_POL0_MASK   0x1u
 
#define FTM_POL_POL0_SHIFT   0
 
#define FTM_POL_POL1_MASK   0x2u
 
#define FTM_POL_POL1_SHIFT   1
 
#define FTM_POL_POL2_MASK   0x4u
 
#define FTM_POL_POL2_SHIFT   2
 
#define FTM_POL_POL3_MASK   0x8u
 
#define FTM_POL_POL3_SHIFT   3
 
#define FTM_POL_POL4_MASK   0x10u
 
#define FTM_POL_POL4_SHIFT   4
 
#define FTM_POL_POL5_MASK   0x20u
 
#define FTM_POL_POL5_SHIFT   5
 
#define FTM_POL_POL6_MASK   0x40u
 
#define FTM_POL_POL6_SHIFT   6
 
#define FTM_POL_POL7_MASK   0x80u
 
#define FTM_POL_POL7_SHIFT   7
 
#define FTM_POL_POL0_MASK   (0x1U)
 
#define FTM_POL_POL0_SHIFT   (0U)
 
#define FTM_POL_POL0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
 
#define FTM_POL_POL1_MASK   (0x2U)
 
#define FTM_POL_POL1_SHIFT   (1U)
 
#define FTM_POL_POL1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
 
#define FTM_POL_POL2_MASK   (0x4U)
 
#define FTM_POL_POL2_SHIFT   (2U)
 
#define FTM_POL_POL2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
 
#define FTM_POL_POL3_MASK   (0x8U)
 
#define FTM_POL_POL3_SHIFT   (3U)
 
#define FTM_POL_POL3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
 
#define FTM_POL_POL4_MASK   (0x10U)
 
#define FTM_POL_POL4_SHIFT   (4U)
 
#define FTM_POL_POL4(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
 
#define FTM_POL_POL5_MASK   (0x20U)
 
#define FTM_POL_POL5_SHIFT   (5U)
 
#define FTM_POL_POL5(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
 
#define FTM_POL_POL6_MASK   (0x40U)
 
#define FTM_POL_POL6_SHIFT   (6U)
 
#define FTM_POL_POL6(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
 
#define FTM_POL_POL7_MASK   (0x80U)
 
#define FTM_POL_POL7_SHIFT   (7U)
 
#define FTM_POL_POL7(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
 
#define FTM_POL_POL0_MASK   (0x1U)
 
#define FTM_POL_POL0_SHIFT   (0U)
 
#define FTM_POL_POL0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
 
#define FTM_POL_POL1_MASK   (0x2U)
 
#define FTM_POL_POL1_SHIFT   (1U)
 
#define FTM_POL_POL1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
 
#define FTM_POL_POL2_MASK   (0x4U)
 
#define FTM_POL_POL2_SHIFT   (2U)
 
#define FTM_POL_POL2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
 
#define FTM_POL_POL3_MASK   (0x8U)
 
#define FTM_POL_POL3_SHIFT   (3U)
 
#define FTM_POL_POL3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
 
#define FTM_POL_POL4_MASK   (0x10U)
 
#define FTM_POL_POL4_SHIFT   (4U)
 
#define FTM_POL_POL4(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
 
#define FTM_POL_POL5_MASK   (0x20U)
 
#define FTM_POL_POL5_SHIFT   (5U)
 
#define FTM_POL_POL5(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
 
#define FTM_POL_POL6_MASK   (0x40U)
 
#define FTM_POL_POL6_SHIFT   (6U)
 
#define FTM_POL_POL6(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
 
#define FTM_POL_POL7_MASK   (0x80U)
 
#define FTM_POL_POL7_SHIFT   (7U)
 
#define FTM_POL_POL7(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
 
#define FTM_POL_POL0_MASK   (0x1U)
 
#define FTM_POL_POL0_SHIFT   (0U)
 
#define FTM_POL_POL0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
 
#define FTM_POL_POL1_MASK   (0x2U)
 
#define FTM_POL_POL1_SHIFT   (1U)
 
#define FTM_POL_POL1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
 
#define FTM_POL_POL2_MASK   (0x4U)
 
#define FTM_POL_POL2_SHIFT   (2U)
 
#define FTM_POL_POL2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
 
#define FTM_POL_POL3_MASK   (0x8U)
 
#define FTM_POL_POL3_SHIFT   (3U)
 
#define FTM_POL_POL3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
 
#define FTM_POL_POL4_MASK   (0x10U)
 
#define FTM_POL_POL4_SHIFT   (4U)
 
#define FTM_POL_POL4(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
 
#define FTM_POL_POL5_MASK   (0x20U)
 
#define FTM_POL_POL5_SHIFT   (5U)
 
#define FTM_POL_POL5(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
 
#define FTM_POL_POL6_MASK   (0x40U)
 
#define FTM_POL_POL6_SHIFT   (6U)
 
#define FTM_POL_POL6(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
 
#define FTM_POL_POL7_MASK   (0x80U)
 
#define FTM_POL_POL7_SHIFT   (7U)
 
#define FTM_POL_POL7(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
 
#define FTM_POL_POL0_MASK   (0x1U)
 
#define FTM_POL_POL0_SHIFT   (0U)
 
#define FTM_POL_POL0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
 
#define FTM_POL_POL1_MASK   (0x2U)
 
#define FTM_POL_POL1_SHIFT   (1U)
 
#define FTM_POL_POL1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
 
#define FTM_POL_POL2_MASK   (0x4U)
 
#define FTM_POL_POL2_SHIFT   (2U)
 
#define FTM_POL_POL2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
 
#define FTM_POL_POL3_MASK   (0x8U)
 
#define FTM_POL_POL3_SHIFT   (3U)
 
#define FTM_POL_POL3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
 
#define FTM_POL_POL4_MASK   (0x10U)
 
#define FTM_POL_POL4_SHIFT   (4U)
 
#define FTM_POL_POL4(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
 
#define FTM_POL_POL5_MASK   (0x20U)
 
#define FTM_POL_POL5_SHIFT   (5U)
 
#define FTM_POL_POL5(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
 
#define FTM_POL_POL6_MASK   (0x40U)
 
#define FTM_POL_POL6_SHIFT   (6U)
 
#define FTM_POL_POL6(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
 
#define FTM_POL_POL7_MASK   (0x80U)
 
#define FTM_POL_POL7_SHIFT   (7U)
 
#define FTM_POL_POL7(x)   (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
 

FMS - Fault Mode Status

#define FTM_FMS_FAULTF0_MASK   (0x1U)
 
#define FTM_FMS_FAULTF0_SHIFT   (0U)
 
#define FTM_FMS_FAULTF0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
 
#define FTM_FMS_FAULTF1_MASK   (0x2U)
 
#define FTM_FMS_FAULTF1_SHIFT   (1U)
 
#define FTM_FMS_FAULTF1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
 
#define FTM_FMS_FAULTF2_MASK   (0x4U)
 
#define FTM_FMS_FAULTF2_SHIFT   (2U)
 
#define FTM_FMS_FAULTF2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
 
#define FTM_FMS_FAULTF3_MASK   (0x8U)
 
#define FTM_FMS_FAULTF3_SHIFT   (3U)
 
#define FTM_FMS_FAULTF3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
 
#define FTM_FMS_FAULTIN_MASK   (0x20U)
 
#define FTM_FMS_FAULTIN_SHIFT   (5U)
 
#define FTM_FMS_FAULTIN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
 
#define FTM_FMS_WPEN_MASK   (0x40U)
 
#define FTM_FMS_WPEN_SHIFT   (6U)
 
#define FTM_FMS_WPEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
 
#define FTM_FMS_FAULTF_MASK   (0x80U)
 
#define FTM_FMS_FAULTF_SHIFT   (7U)
 
#define FTM_FMS_FAULTF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
 
#define FTM_FMS_FAULTF0_MASK   0x1u
 
#define FTM_FMS_FAULTF0_SHIFT   0
 
#define FTM_FMS_FAULTF1_MASK   0x2u
 
#define FTM_FMS_FAULTF1_SHIFT   1
 
#define FTM_FMS_FAULTF2_MASK   0x4u
 
#define FTM_FMS_FAULTF2_SHIFT   2
 
#define FTM_FMS_FAULTF3_MASK   0x8u
 
#define FTM_FMS_FAULTF3_SHIFT   3
 
#define FTM_FMS_FAULTIN_MASK   0x20u
 
#define FTM_FMS_FAULTIN_SHIFT   5
 
#define FTM_FMS_WPEN_MASK   0x40u
 
#define FTM_FMS_WPEN_SHIFT   6
 
#define FTM_FMS_FAULTF_MASK   0x80u
 
#define FTM_FMS_FAULTF_SHIFT   7
 
#define FTM_FMS_FAULTF0_MASK   (0x1U)
 
#define FTM_FMS_FAULTF0_SHIFT   (0U)
 
#define FTM_FMS_FAULTF0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
 
#define FTM_FMS_FAULTF1_MASK   (0x2U)
 
#define FTM_FMS_FAULTF1_SHIFT   (1U)
 
#define FTM_FMS_FAULTF1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
 
#define FTM_FMS_FAULTF2_MASK   (0x4U)
 
#define FTM_FMS_FAULTF2_SHIFT   (2U)
 
#define FTM_FMS_FAULTF2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
 
#define FTM_FMS_FAULTF3_MASK   (0x8U)
 
#define FTM_FMS_FAULTF3_SHIFT   (3U)
 
#define FTM_FMS_FAULTF3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
 
#define FTM_FMS_FAULTIN_MASK   (0x20U)
 
#define FTM_FMS_FAULTIN_SHIFT   (5U)
 
#define FTM_FMS_FAULTIN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
 
#define FTM_FMS_WPEN_MASK   (0x40U)
 
#define FTM_FMS_WPEN_SHIFT   (6U)
 
#define FTM_FMS_WPEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
 
#define FTM_FMS_FAULTF_MASK   (0x80U)
 
#define FTM_FMS_FAULTF_SHIFT   (7U)
 
#define FTM_FMS_FAULTF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
 
#define FTM_FMS_FAULTF0_MASK   (0x1U)
 
#define FTM_FMS_FAULTF0_SHIFT   (0U)
 
#define FTM_FMS_FAULTF0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
 
#define FTM_FMS_FAULTF1_MASK   (0x2U)
 
#define FTM_FMS_FAULTF1_SHIFT   (1U)
 
#define FTM_FMS_FAULTF1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
 
#define FTM_FMS_FAULTF2_MASK   (0x4U)
 
#define FTM_FMS_FAULTF2_SHIFT   (2U)
 
#define FTM_FMS_FAULTF2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
 
#define FTM_FMS_FAULTF3_MASK   (0x8U)
 
#define FTM_FMS_FAULTF3_SHIFT   (3U)
 
#define FTM_FMS_FAULTF3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
 
#define FTM_FMS_FAULTIN_MASK   (0x20U)
 
#define FTM_FMS_FAULTIN_SHIFT   (5U)
 
#define FTM_FMS_FAULTIN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
 
#define FTM_FMS_WPEN_MASK   (0x40U)
 
#define FTM_FMS_WPEN_SHIFT   (6U)
 
#define FTM_FMS_WPEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
 
#define FTM_FMS_FAULTF_MASK   (0x80U)
 
#define FTM_FMS_FAULTF_SHIFT   (7U)
 
#define FTM_FMS_FAULTF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
 
#define FTM_FMS_FAULTF0_MASK   (0x1U)
 
#define FTM_FMS_FAULTF0_SHIFT   (0U)
 
#define FTM_FMS_FAULTF0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
 
#define FTM_FMS_FAULTF1_MASK   (0x2U)
 
#define FTM_FMS_FAULTF1_SHIFT   (1U)
 
#define FTM_FMS_FAULTF1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
 
#define FTM_FMS_FAULTF2_MASK   (0x4U)
 
#define FTM_FMS_FAULTF2_SHIFT   (2U)
 
#define FTM_FMS_FAULTF2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
 
#define FTM_FMS_FAULTF3_MASK   (0x8U)
 
#define FTM_FMS_FAULTF3_SHIFT   (3U)
 
#define FTM_FMS_FAULTF3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
 
#define FTM_FMS_FAULTIN_MASK   (0x20U)
 
#define FTM_FMS_FAULTIN_SHIFT   (5U)
 
#define FTM_FMS_FAULTIN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
 
#define FTM_FMS_WPEN_MASK   (0x40U)
 
#define FTM_FMS_WPEN_SHIFT   (6U)
 
#define FTM_FMS_WPEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
 
#define FTM_FMS_FAULTF_MASK   (0x80U)
 
#define FTM_FMS_FAULTF_SHIFT   (7U)
 
#define FTM_FMS_FAULTF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
 
#define FTM_FMS_FAULTF0_MASK   (0x1U)
 
#define FTM_FMS_FAULTF0_SHIFT   (0U)
 
#define FTM_FMS_FAULTF0(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
 
#define FTM_FMS_FAULTF1_MASK   (0x2U)
 
#define FTM_FMS_FAULTF1_SHIFT   (1U)
 
#define FTM_FMS_FAULTF1(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
 
#define FTM_FMS_FAULTF2_MASK   (0x4U)
 
#define FTM_FMS_FAULTF2_SHIFT   (2U)
 
#define FTM_FMS_FAULTF2(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
 
#define FTM_FMS_FAULTF3_MASK   (0x8U)
 
#define FTM_FMS_FAULTF3_SHIFT   (3U)
 
#define FTM_FMS_FAULTF3(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
 
#define FTM_FMS_FAULTIN_MASK   (0x20U)
 
#define FTM_FMS_FAULTIN_SHIFT   (5U)
 
#define FTM_FMS_FAULTIN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
 
#define FTM_FMS_WPEN_MASK   (0x40U)
 
#define FTM_FMS_WPEN_SHIFT   (6U)
 
#define FTM_FMS_WPEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
 
#define FTM_FMS_FAULTF_MASK   (0x80U)
 
#define FTM_FMS_FAULTF_SHIFT   (7U)
 
#define FTM_FMS_FAULTF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
 

FILTER - Input Capture Filter Control

#define FTM_FILTER_CH0FVAL_MASK   (0xFU)
 
#define FTM_FILTER_CH0FVAL_SHIFT   (0U)
 
#define FTM_FILTER_CH0FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
 
#define FTM_FILTER_CH1FVAL_MASK   (0xF0U)
 
#define FTM_FILTER_CH1FVAL_SHIFT   (4U)
 
#define FTM_FILTER_CH1FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
 
#define FTM_FILTER_CH2FVAL_MASK   (0xF00U)
 
#define FTM_FILTER_CH2FVAL_SHIFT   (8U)
 
#define FTM_FILTER_CH2FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
 
#define FTM_FILTER_CH3FVAL_MASK   (0xF000U)
 
#define FTM_FILTER_CH3FVAL_SHIFT   (12U)
 
#define FTM_FILTER_CH3FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
 
#define FTM_FILTER_CH0FVAL_MASK   0xFu
 
#define FTM_FILTER_CH0FVAL_SHIFT   0
 
#define FTM_FILTER_CH0FVAL(x)   (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
 
#define FTM_FILTER_CH1FVAL_MASK   0xF0u
 
#define FTM_FILTER_CH1FVAL_SHIFT   4
 
#define FTM_FILTER_CH1FVAL(x)   (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
 
#define FTM_FILTER_CH2FVAL_MASK   0xF00u
 
#define FTM_FILTER_CH2FVAL_SHIFT   8
 
#define FTM_FILTER_CH2FVAL(x)   (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
 
#define FTM_FILTER_CH3FVAL_MASK   0xF000u
 
#define FTM_FILTER_CH3FVAL_SHIFT   12
 
#define FTM_FILTER_CH3FVAL(x)   (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
 
#define FTM_FILTER_CH0FVAL_MASK   (0xFU)
 
#define FTM_FILTER_CH0FVAL_SHIFT   (0U)
 
#define FTM_FILTER_CH0FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
 
#define FTM_FILTER_CH1FVAL_MASK   (0xF0U)
 
#define FTM_FILTER_CH1FVAL_SHIFT   (4U)
 
#define FTM_FILTER_CH1FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
 
#define FTM_FILTER_CH2FVAL_MASK   (0xF00U)
 
#define FTM_FILTER_CH2FVAL_SHIFT   (8U)
 
#define FTM_FILTER_CH2FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
 
#define FTM_FILTER_CH3FVAL_MASK   (0xF000U)
 
#define FTM_FILTER_CH3FVAL_SHIFT   (12U)
 
#define FTM_FILTER_CH3FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
 
#define FTM_FILTER_CH0FVAL_MASK   (0xFU)
 
#define FTM_FILTER_CH0FVAL_SHIFT   (0U)
 
#define FTM_FILTER_CH0FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
 
#define FTM_FILTER_CH1FVAL_MASK   (0xF0U)
 
#define FTM_FILTER_CH1FVAL_SHIFT   (4U)
 
#define FTM_FILTER_CH1FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
 
#define FTM_FILTER_CH2FVAL_MASK   (0xF00U)
 
#define FTM_FILTER_CH2FVAL_SHIFT   (8U)
 
#define FTM_FILTER_CH2FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
 
#define FTM_FILTER_CH3FVAL_MASK   (0xF000U)
 
#define FTM_FILTER_CH3FVAL_SHIFT   (12U)
 
#define FTM_FILTER_CH3FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
 
#define FTM_FILTER_CH0FVAL_MASK   (0xFU)
 
#define FTM_FILTER_CH0FVAL_SHIFT   (0U)
 
#define FTM_FILTER_CH0FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
 
#define FTM_FILTER_CH1FVAL_MASK   (0xF0U)
 
#define FTM_FILTER_CH1FVAL_SHIFT   (4U)
 
#define FTM_FILTER_CH1FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
 
#define FTM_FILTER_CH2FVAL_MASK   (0xF00U)
 
#define FTM_FILTER_CH2FVAL_SHIFT   (8U)
 
#define FTM_FILTER_CH2FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
 
#define FTM_FILTER_CH3FVAL_MASK   (0xF000U)
 
#define FTM_FILTER_CH3FVAL_SHIFT   (12U)
 
#define FTM_FILTER_CH3FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
 
#define FTM_FILTER_CH0FVAL_MASK   (0xFU)
 
#define FTM_FILTER_CH0FVAL_SHIFT   (0U)
 
#define FTM_FILTER_CH0FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
 
#define FTM_FILTER_CH1FVAL_MASK   (0xF0U)
 
#define FTM_FILTER_CH1FVAL_SHIFT   (4U)
 
#define FTM_FILTER_CH1FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
 
#define FTM_FILTER_CH2FVAL_MASK   (0xF00U)
 
#define FTM_FILTER_CH2FVAL_SHIFT   (8U)
 
#define FTM_FILTER_CH2FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
 
#define FTM_FILTER_CH3FVAL_MASK   (0xF000U)
 
#define FTM_FILTER_CH3FVAL_SHIFT   (12U)
 
#define FTM_FILTER_CH3FVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
 

FLTCTRL - Fault Control

#define FTM_FLTCTRL_FAULT0EN_MASK   (0x1U)
 
#define FTM_FLTCTRL_FAULT0EN_SHIFT   (0U)
 
#define FTM_FLTCTRL_FAULT0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
 
#define FTM_FLTCTRL_FAULT1EN_MASK   (0x2U)
 
#define FTM_FLTCTRL_FAULT1EN_SHIFT   (1U)
 
#define FTM_FLTCTRL_FAULT1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
 
#define FTM_FLTCTRL_FAULT2EN_MASK   (0x4U)
 
#define FTM_FLTCTRL_FAULT2EN_SHIFT   (2U)
 
#define FTM_FLTCTRL_FAULT2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
 
#define FTM_FLTCTRL_FAULT3EN_MASK   (0x8U)
 
#define FTM_FLTCTRL_FAULT3EN_SHIFT   (3U)
 
#define FTM_FLTCTRL_FAULT3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
 
#define FTM_FLTCTRL_FFLTR0EN_MASK   (0x10U)
 
#define FTM_FLTCTRL_FFLTR0EN_SHIFT   (4U)
 
#define FTM_FLTCTRL_FFLTR0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
 
#define FTM_FLTCTRL_FFLTR1EN_MASK   (0x20U)
 
#define FTM_FLTCTRL_FFLTR1EN_SHIFT   (5U)
 
#define FTM_FLTCTRL_FFLTR1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
 
#define FTM_FLTCTRL_FFLTR2EN_MASK   (0x40U)
 
#define FTM_FLTCTRL_FFLTR2EN_SHIFT   (6U)
 
#define FTM_FLTCTRL_FFLTR2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
 
#define FTM_FLTCTRL_FFLTR3EN_MASK   (0x80U)
 
#define FTM_FLTCTRL_FFLTR3EN_SHIFT   (7U)
 
#define FTM_FLTCTRL_FFLTR3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
 
#define FTM_FLTCTRL_FFVAL_MASK   (0xF00U)
 
#define FTM_FLTCTRL_FFVAL_SHIFT   (8U)
 
#define FTM_FLTCTRL_FFVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
 
#define FTM_FLTCTRL_FAULT0EN_MASK   0x1u
 
#define FTM_FLTCTRL_FAULT0EN_SHIFT   0
 
#define FTM_FLTCTRL_FAULT1EN_MASK   0x2u
 
#define FTM_FLTCTRL_FAULT1EN_SHIFT   1
 
#define FTM_FLTCTRL_FAULT2EN_MASK   0x4u
 
#define FTM_FLTCTRL_FAULT2EN_SHIFT   2
 
#define FTM_FLTCTRL_FAULT3EN_MASK   0x8u
 
#define FTM_FLTCTRL_FAULT3EN_SHIFT   3
 
#define FTM_FLTCTRL_FFLTR0EN_MASK   0x10u
 
#define FTM_FLTCTRL_FFLTR0EN_SHIFT   4
 
#define FTM_FLTCTRL_FFLTR1EN_MASK   0x20u
 
#define FTM_FLTCTRL_FFLTR1EN_SHIFT   5
 
#define FTM_FLTCTRL_FFLTR2EN_MASK   0x40u
 
#define FTM_FLTCTRL_FFLTR2EN_SHIFT   6
 
#define FTM_FLTCTRL_FFLTR3EN_MASK   0x80u
 
#define FTM_FLTCTRL_FFLTR3EN_SHIFT   7
 
#define FTM_FLTCTRL_FFVAL_MASK   0xF00u
 
#define FTM_FLTCTRL_FFVAL_SHIFT   8
 
#define FTM_FLTCTRL_FFVAL(x)   (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
 
#define FTM_FLTCTRL_FAULT0EN_MASK   (0x1U)
 
#define FTM_FLTCTRL_FAULT0EN_SHIFT   (0U)
 
#define FTM_FLTCTRL_FAULT0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
 
#define FTM_FLTCTRL_FAULT1EN_MASK   (0x2U)
 
#define FTM_FLTCTRL_FAULT1EN_SHIFT   (1U)
 
#define FTM_FLTCTRL_FAULT1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
 
#define FTM_FLTCTRL_FAULT2EN_MASK   (0x4U)
 
#define FTM_FLTCTRL_FAULT2EN_SHIFT   (2U)
 
#define FTM_FLTCTRL_FAULT2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
 
#define FTM_FLTCTRL_FAULT3EN_MASK   (0x8U)
 
#define FTM_FLTCTRL_FAULT3EN_SHIFT   (3U)
 
#define FTM_FLTCTRL_FAULT3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
 
#define FTM_FLTCTRL_FFLTR0EN_MASK   (0x10U)
 
#define FTM_FLTCTRL_FFLTR0EN_SHIFT   (4U)
 
#define FTM_FLTCTRL_FFLTR0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
 
#define FTM_FLTCTRL_FFLTR1EN_MASK   (0x20U)
 
#define FTM_FLTCTRL_FFLTR1EN_SHIFT   (5U)
 
#define FTM_FLTCTRL_FFLTR1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
 
#define FTM_FLTCTRL_FFLTR2EN_MASK   (0x40U)
 
#define FTM_FLTCTRL_FFLTR2EN_SHIFT   (6U)
 
#define FTM_FLTCTRL_FFLTR2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
 
#define FTM_FLTCTRL_FFLTR3EN_MASK   (0x80U)
 
#define FTM_FLTCTRL_FFLTR3EN_SHIFT   (7U)
 
#define FTM_FLTCTRL_FFLTR3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
 
#define FTM_FLTCTRL_FFVAL_MASK   (0xF00U)
 
#define FTM_FLTCTRL_FFVAL_SHIFT   (8U)
 
#define FTM_FLTCTRL_FFVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
 
#define FTM_FLTCTRL_FAULT0EN_MASK   (0x1U)
 
#define FTM_FLTCTRL_FAULT0EN_SHIFT   (0U)
 
#define FTM_FLTCTRL_FAULT0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
 
#define FTM_FLTCTRL_FAULT1EN_MASK   (0x2U)
 
#define FTM_FLTCTRL_FAULT1EN_SHIFT   (1U)
 
#define FTM_FLTCTRL_FAULT1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
 
#define FTM_FLTCTRL_FAULT2EN_MASK   (0x4U)
 
#define FTM_FLTCTRL_FAULT2EN_SHIFT   (2U)
 
#define FTM_FLTCTRL_FAULT2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
 
#define FTM_FLTCTRL_FAULT3EN_MASK   (0x8U)
 
#define FTM_FLTCTRL_FAULT3EN_SHIFT   (3U)
 
#define FTM_FLTCTRL_FAULT3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
 
#define FTM_FLTCTRL_FFLTR0EN_MASK   (0x10U)
 
#define FTM_FLTCTRL_FFLTR0EN_SHIFT   (4U)
 
#define FTM_FLTCTRL_FFLTR0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
 
#define FTM_FLTCTRL_FFLTR1EN_MASK   (0x20U)
 
#define FTM_FLTCTRL_FFLTR1EN_SHIFT   (5U)
 
#define FTM_FLTCTRL_FFLTR1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
 
#define FTM_FLTCTRL_FFLTR2EN_MASK   (0x40U)
 
#define FTM_FLTCTRL_FFLTR2EN_SHIFT   (6U)
 
#define FTM_FLTCTRL_FFLTR2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
 
#define FTM_FLTCTRL_FFLTR3EN_MASK   (0x80U)
 
#define FTM_FLTCTRL_FFLTR3EN_SHIFT   (7U)
 
#define FTM_FLTCTRL_FFLTR3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
 
#define FTM_FLTCTRL_FFVAL_MASK   (0xF00U)
 
#define FTM_FLTCTRL_FFVAL_SHIFT   (8U)
 
#define FTM_FLTCTRL_FFVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
 
#define FTM_FLTCTRL_FAULT0EN_MASK   (0x1U)
 
#define FTM_FLTCTRL_FAULT0EN_SHIFT   (0U)
 
#define FTM_FLTCTRL_FAULT0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
 
#define FTM_FLTCTRL_FAULT1EN_MASK   (0x2U)
 
#define FTM_FLTCTRL_FAULT1EN_SHIFT   (1U)
 
#define FTM_FLTCTRL_FAULT1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
 
#define FTM_FLTCTRL_FAULT2EN_MASK   (0x4U)
 
#define FTM_FLTCTRL_FAULT2EN_SHIFT   (2U)
 
#define FTM_FLTCTRL_FAULT2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
 
#define FTM_FLTCTRL_FAULT3EN_MASK   (0x8U)
 
#define FTM_FLTCTRL_FAULT3EN_SHIFT   (3U)
 
#define FTM_FLTCTRL_FAULT3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
 
#define FTM_FLTCTRL_FFLTR0EN_MASK   (0x10U)
 
#define FTM_FLTCTRL_FFLTR0EN_SHIFT   (4U)
 
#define FTM_FLTCTRL_FFLTR0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
 
#define FTM_FLTCTRL_FFLTR1EN_MASK   (0x20U)
 
#define FTM_FLTCTRL_FFLTR1EN_SHIFT   (5U)
 
#define FTM_FLTCTRL_FFLTR1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
 
#define FTM_FLTCTRL_FFLTR2EN_MASK   (0x40U)
 
#define FTM_FLTCTRL_FFLTR2EN_SHIFT   (6U)
 
#define FTM_FLTCTRL_FFLTR2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
 
#define FTM_FLTCTRL_FFLTR3EN_MASK   (0x80U)
 
#define FTM_FLTCTRL_FFLTR3EN_SHIFT   (7U)
 
#define FTM_FLTCTRL_FFLTR3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
 
#define FTM_FLTCTRL_FFVAL_MASK   (0xF00U)
 
#define FTM_FLTCTRL_FFVAL_SHIFT   (8U)
 
#define FTM_FLTCTRL_FFVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
 
#define FTM_FLTCTRL_FAULT0EN_MASK   (0x1U)
 
#define FTM_FLTCTRL_FAULT0EN_SHIFT   (0U)
 
#define FTM_FLTCTRL_FAULT0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
 
#define FTM_FLTCTRL_FAULT1EN_MASK   (0x2U)
 
#define FTM_FLTCTRL_FAULT1EN_SHIFT   (1U)
 
#define FTM_FLTCTRL_FAULT1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
 
#define FTM_FLTCTRL_FAULT2EN_MASK   (0x4U)
 
#define FTM_FLTCTRL_FAULT2EN_SHIFT   (2U)
 
#define FTM_FLTCTRL_FAULT2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
 
#define FTM_FLTCTRL_FAULT3EN_MASK   (0x8U)
 
#define FTM_FLTCTRL_FAULT3EN_SHIFT   (3U)
 
#define FTM_FLTCTRL_FAULT3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
 
#define FTM_FLTCTRL_FFLTR0EN_MASK   (0x10U)
 
#define FTM_FLTCTRL_FFLTR0EN_SHIFT   (4U)
 
#define FTM_FLTCTRL_FFLTR0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
 
#define FTM_FLTCTRL_FFLTR1EN_MASK   (0x20U)
 
#define FTM_FLTCTRL_FFLTR1EN_SHIFT   (5U)
 
#define FTM_FLTCTRL_FFLTR1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
 
#define FTM_FLTCTRL_FFLTR2EN_MASK   (0x40U)
 
#define FTM_FLTCTRL_FFLTR2EN_SHIFT   (6U)
 
#define FTM_FLTCTRL_FFLTR2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
 
#define FTM_FLTCTRL_FFLTR3EN_MASK   (0x80U)
 
#define FTM_FLTCTRL_FFLTR3EN_SHIFT   (7U)
 
#define FTM_FLTCTRL_FFLTR3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
 
#define FTM_FLTCTRL_FFVAL_MASK   (0xF00U)
 
#define FTM_FLTCTRL_FFVAL_SHIFT   (8U)
 
#define FTM_FLTCTRL_FFVAL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
 

QDCTRL - Quadrature Decoder Control And Status

#define FTM_QDCTRL_QUADEN_MASK   (0x1U)
 
#define FTM_QDCTRL_QUADEN_SHIFT   (0U)
 
#define FTM_QDCTRL_QUADEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
 
#define FTM_QDCTRL_TOFDIR_MASK   (0x2U)
 
#define FTM_QDCTRL_TOFDIR_SHIFT   (1U)
 
#define FTM_QDCTRL_TOFDIR(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
 
#define FTM_QDCTRL_QUADIR_MASK   (0x4U)
 
#define FTM_QDCTRL_QUADIR_SHIFT   (2U)
 
#define FTM_QDCTRL_QUADIR(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
 
#define FTM_QDCTRL_QUADMODE_MASK   (0x8U)
 
#define FTM_QDCTRL_QUADMODE_SHIFT   (3U)
 
#define FTM_QDCTRL_QUADMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
 
#define FTM_QDCTRL_PHBPOL_MASK   (0x10U)
 
#define FTM_QDCTRL_PHBPOL_SHIFT   (4U)
 
#define FTM_QDCTRL_PHBPOL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
 
#define FTM_QDCTRL_PHAPOL_MASK   (0x20U)
 
#define FTM_QDCTRL_PHAPOL_SHIFT   (5U)
 
#define FTM_QDCTRL_PHAPOL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
 
#define FTM_QDCTRL_PHBFLTREN_MASK   (0x40U)
 
#define FTM_QDCTRL_PHBFLTREN_SHIFT   (6U)
 
#define FTM_QDCTRL_PHBFLTREN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
 
#define FTM_QDCTRL_PHAFLTREN_MASK   (0x80U)
 
#define FTM_QDCTRL_PHAFLTREN_SHIFT   (7U)
 
#define FTM_QDCTRL_PHAFLTREN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
 
#define FTM_QDCTRL_QUADEN_MASK   0x1u
 
#define FTM_QDCTRL_QUADEN_SHIFT   0
 
#define FTM_QDCTRL_TOFDIR_MASK   0x2u
 
#define FTM_QDCTRL_TOFDIR_SHIFT   1
 
#define FTM_QDCTRL_QUADIR_MASK   0x4u
 
#define FTM_QDCTRL_QUADIR_SHIFT   2
 
#define FTM_QDCTRL_QUADMODE_MASK   0x8u
 
#define FTM_QDCTRL_QUADMODE_SHIFT   3
 
#define FTM_QDCTRL_PHBPOL_MASK   0x10u
 
#define FTM_QDCTRL_PHBPOL_SHIFT   4
 
#define FTM_QDCTRL_PHAPOL_MASK   0x20u
 
#define FTM_QDCTRL_PHAPOL_SHIFT   5
 
#define FTM_QDCTRL_PHBFLTREN_MASK   0x40u
 
#define FTM_QDCTRL_PHBFLTREN_SHIFT   6
 
#define FTM_QDCTRL_PHAFLTREN_MASK   0x80u
 
#define FTM_QDCTRL_PHAFLTREN_SHIFT   7
 
#define FTM_QDCTRL_QUADEN_MASK   (0x1U)
 
#define FTM_QDCTRL_QUADEN_SHIFT   (0U)
 
#define FTM_QDCTRL_QUADEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
 
#define FTM_QDCTRL_TOFDIR_MASK   (0x2U)
 
#define FTM_QDCTRL_TOFDIR_SHIFT   (1U)
 
#define FTM_QDCTRL_TOFDIR(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
 
#define FTM_QDCTRL_QUADIR_MASK   (0x4U)
 
#define FTM_QDCTRL_QUADIR_SHIFT   (2U)
 
#define FTM_QDCTRL_QUADIR(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
 
#define FTM_QDCTRL_QUADMODE_MASK   (0x8U)
 
#define FTM_QDCTRL_QUADMODE_SHIFT   (3U)
 
#define FTM_QDCTRL_QUADMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
 
#define FTM_QDCTRL_PHBPOL_MASK   (0x10U)
 
#define FTM_QDCTRL_PHBPOL_SHIFT   (4U)
 
#define FTM_QDCTRL_PHBPOL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
 
#define FTM_QDCTRL_PHAPOL_MASK   (0x20U)
 
#define FTM_QDCTRL_PHAPOL_SHIFT   (5U)
 
#define FTM_QDCTRL_PHAPOL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
 
#define FTM_QDCTRL_PHBFLTREN_MASK   (0x40U)
 
#define FTM_QDCTRL_PHBFLTREN_SHIFT   (6U)
 
#define FTM_QDCTRL_PHBFLTREN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
 
#define FTM_QDCTRL_PHAFLTREN_MASK   (0x80U)
 
#define FTM_QDCTRL_PHAFLTREN_SHIFT   (7U)
 
#define FTM_QDCTRL_PHAFLTREN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
 
#define FTM_QDCTRL_QUADEN_MASK   (0x1U)
 
#define FTM_QDCTRL_QUADEN_SHIFT   (0U)
 
#define FTM_QDCTRL_QUADEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
 
#define FTM_QDCTRL_TOFDIR_MASK   (0x2U)
 
#define FTM_QDCTRL_TOFDIR_SHIFT   (1U)
 
#define FTM_QDCTRL_TOFDIR(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
 
#define FTM_QDCTRL_QUADIR_MASK   (0x4U)
 
#define FTM_QDCTRL_QUADIR_SHIFT   (2U)
 
#define FTM_QDCTRL_QUADIR(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
 
#define FTM_QDCTRL_QUADMODE_MASK   (0x8U)
 
#define FTM_QDCTRL_QUADMODE_SHIFT   (3U)
 
#define FTM_QDCTRL_QUADMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
 
#define FTM_QDCTRL_PHBPOL_MASK   (0x10U)
 
#define FTM_QDCTRL_PHBPOL_SHIFT   (4U)
 
#define FTM_QDCTRL_PHBPOL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
 
#define FTM_QDCTRL_PHAPOL_MASK   (0x20U)
 
#define FTM_QDCTRL_PHAPOL_SHIFT   (5U)
 
#define FTM_QDCTRL_PHAPOL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
 
#define FTM_QDCTRL_PHBFLTREN_MASK   (0x40U)
 
#define FTM_QDCTRL_PHBFLTREN_SHIFT   (6U)
 
#define FTM_QDCTRL_PHBFLTREN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
 
#define FTM_QDCTRL_PHAFLTREN_MASK   (0x80U)
 
#define FTM_QDCTRL_PHAFLTREN_SHIFT   (7U)
 
#define FTM_QDCTRL_PHAFLTREN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
 
#define FTM_QDCTRL_QUADEN_MASK   (0x1U)
 
#define FTM_QDCTRL_QUADEN_SHIFT   (0U)
 
#define FTM_QDCTRL_QUADEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
 
#define FTM_QDCTRL_TOFDIR_MASK   (0x2U)
 
#define FTM_QDCTRL_TOFDIR_SHIFT   (1U)
 
#define FTM_QDCTRL_TOFDIR(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
 
#define FTM_QDCTRL_QUADIR_MASK   (0x4U)
 
#define FTM_QDCTRL_QUADIR_SHIFT   (2U)
 
#define FTM_QDCTRL_QUADIR(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
 
#define FTM_QDCTRL_QUADMODE_MASK   (0x8U)
 
#define FTM_QDCTRL_QUADMODE_SHIFT   (3U)
 
#define FTM_QDCTRL_QUADMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
 
#define FTM_QDCTRL_PHBPOL_MASK   (0x10U)
 
#define FTM_QDCTRL_PHBPOL_SHIFT   (4U)
 
#define FTM_QDCTRL_PHBPOL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
 
#define FTM_QDCTRL_PHAPOL_MASK   (0x20U)
 
#define FTM_QDCTRL_PHAPOL_SHIFT   (5U)
 
#define FTM_QDCTRL_PHAPOL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
 
#define FTM_QDCTRL_PHBFLTREN_MASK   (0x40U)
 
#define FTM_QDCTRL_PHBFLTREN_SHIFT   (6U)
 
#define FTM_QDCTRL_PHBFLTREN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
 
#define FTM_QDCTRL_PHAFLTREN_MASK   (0x80U)
 
#define FTM_QDCTRL_PHAFLTREN_SHIFT   (7U)
 
#define FTM_QDCTRL_PHAFLTREN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
 
#define FTM_QDCTRL_QUADEN_MASK   (0x1U)
 
#define FTM_QDCTRL_QUADEN_SHIFT   (0U)
 
#define FTM_QDCTRL_QUADEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
 
#define FTM_QDCTRL_TOFDIR_MASK   (0x2U)
 
#define FTM_QDCTRL_TOFDIR_SHIFT   (1U)
 
#define FTM_QDCTRL_TOFDIR(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
 
#define FTM_QDCTRL_QUADIR_MASK   (0x4U)
 
#define FTM_QDCTRL_QUADIR_SHIFT   (2U)
 
#define FTM_QDCTRL_QUADIR(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
 
#define FTM_QDCTRL_QUADMODE_MASK   (0x8U)
 
#define FTM_QDCTRL_QUADMODE_SHIFT   (3U)
 
#define FTM_QDCTRL_QUADMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
 
#define FTM_QDCTRL_PHBPOL_MASK   (0x10U)
 
#define FTM_QDCTRL_PHBPOL_SHIFT   (4U)
 
#define FTM_QDCTRL_PHBPOL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
 
#define FTM_QDCTRL_PHAPOL_MASK   (0x20U)
 
#define FTM_QDCTRL_PHAPOL_SHIFT   (5U)
 
#define FTM_QDCTRL_PHAPOL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
 
#define FTM_QDCTRL_PHBFLTREN_MASK   (0x40U)
 
#define FTM_QDCTRL_PHBFLTREN_SHIFT   (6U)
 
#define FTM_QDCTRL_PHBFLTREN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
 
#define FTM_QDCTRL_PHAFLTREN_MASK   (0x80U)
 
#define FTM_QDCTRL_PHAFLTREN_SHIFT   (7U)
 
#define FTM_QDCTRL_PHAFLTREN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
 

CONF - Configuration

#define FTM_CONF_NUMTOF_MASK   (0x1FU)
 
#define FTM_CONF_NUMTOF_SHIFT   (0U)
 
#define FTM_CONF_NUMTOF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
 
#define FTM_CONF_BDMMODE_MASK   (0xC0U)
 
#define FTM_CONF_BDMMODE_SHIFT   (6U)
 
#define FTM_CONF_BDMMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
 
#define FTM_CONF_GTBEEN_MASK   (0x200U)
 
#define FTM_CONF_GTBEEN_SHIFT   (9U)
 
#define FTM_CONF_GTBEEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
 
#define FTM_CONF_GTBEOUT_MASK   (0x400U)
 
#define FTM_CONF_GTBEOUT_SHIFT   (10U)
 
#define FTM_CONF_GTBEOUT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
 
#define FTM_CONF_NUMTOF_MASK   0x1Fu
 
#define FTM_CONF_NUMTOF_SHIFT   0
 
#define FTM_CONF_NUMTOF(x)   (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
 
#define FTM_CONF_BDMMODE_MASK   0xC0u
 
#define FTM_CONF_BDMMODE_SHIFT   6
 
#define FTM_CONF_BDMMODE(x)   (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
 
#define FTM_CONF_GTBEEN_MASK   0x200u
 
#define FTM_CONF_GTBEEN_SHIFT   9
 
#define FTM_CONF_GTBEOUT_MASK   0x400u
 
#define FTM_CONF_GTBEOUT_SHIFT   10
 
#define FTM_CONF_NUMTOF_MASK   (0x1FU)
 
#define FTM_CONF_NUMTOF_SHIFT   (0U)
 
#define FTM_CONF_NUMTOF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
 
#define FTM_CONF_BDMMODE_MASK   (0xC0U)
 
#define FTM_CONF_BDMMODE_SHIFT   (6U)
 
#define FTM_CONF_BDMMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
 
#define FTM_CONF_GTBEEN_MASK   (0x200U)
 
#define FTM_CONF_GTBEEN_SHIFT   (9U)
 
#define FTM_CONF_GTBEEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
 
#define FTM_CONF_GTBEOUT_MASK   (0x400U)
 
#define FTM_CONF_GTBEOUT_SHIFT   (10U)
 
#define FTM_CONF_GTBEOUT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
 
#define FTM_CONF_NUMTOF_MASK   (0x1FU)
 
#define FTM_CONF_NUMTOF_SHIFT   (0U)
 
#define FTM_CONF_NUMTOF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
 
#define FTM_CONF_BDMMODE_MASK   (0xC0U)
 
#define FTM_CONF_BDMMODE_SHIFT   (6U)
 
#define FTM_CONF_BDMMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
 
#define FTM_CONF_GTBEEN_MASK   (0x200U)
 
#define FTM_CONF_GTBEEN_SHIFT   (9U)
 
#define FTM_CONF_GTBEEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
 
#define FTM_CONF_GTBEOUT_MASK   (0x400U)
 
#define FTM_CONF_GTBEOUT_SHIFT   (10U)
 
#define FTM_CONF_GTBEOUT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
 
#define FTM_CONF_NUMTOF_MASK   (0x1FU)
 
#define FTM_CONF_NUMTOF_SHIFT   (0U)
 
#define FTM_CONF_NUMTOF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
 
#define FTM_CONF_BDMMODE_MASK   (0xC0U)
 
#define FTM_CONF_BDMMODE_SHIFT   (6U)
 
#define FTM_CONF_BDMMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
 
#define FTM_CONF_GTBEEN_MASK   (0x200U)
 
#define FTM_CONF_GTBEEN_SHIFT   (9U)
 
#define FTM_CONF_GTBEEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
 
#define FTM_CONF_GTBEOUT_MASK   (0x400U)
 
#define FTM_CONF_GTBEOUT_SHIFT   (10U)
 
#define FTM_CONF_GTBEOUT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
 
#define FTM_CONF_NUMTOF_MASK   (0x1FU)
 
#define FTM_CONF_NUMTOF_SHIFT   (0U)
 
#define FTM_CONF_NUMTOF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
 
#define FTM_CONF_BDMMODE_MASK   (0xC0U)
 
#define FTM_CONF_BDMMODE_SHIFT   (6U)
 
#define FTM_CONF_BDMMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
 
#define FTM_CONF_GTBEEN_MASK   (0x200U)
 
#define FTM_CONF_GTBEEN_SHIFT   (9U)
 
#define FTM_CONF_GTBEEN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
 
#define FTM_CONF_GTBEOUT_MASK   (0x400U)
 
#define FTM_CONF_GTBEOUT_SHIFT   (10U)
 
#define FTM_CONF_GTBEOUT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
 

FLTPOL - FTM Fault Input Polarity

#define FTM_FLTPOL_FLT0POL_MASK   (0x1U)
 
#define FTM_FLTPOL_FLT0POL_SHIFT   (0U)
 
#define FTM_FLTPOL_FLT0POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
 
#define FTM_FLTPOL_FLT1POL_MASK   (0x2U)
 
#define FTM_FLTPOL_FLT1POL_SHIFT   (1U)
 
#define FTM_FLTPOL_FLT1POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
 
#define FTM_FLTPOL_FLT2POL_MASK   (0x4U)
 
#define FTM_FLTPOL_FLT2POL_SHIFT   (2U)
 
#define FTM_FLTPOL_FLT2POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
 
#define FTM_FLTPOL_FLT3POL_MASK   (0x8U)
 
#define FTM_FLTPOL_FLT3POL_SHIFT   (3U)
 
#define FTM_FLTPOL_FLT3POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
 
#define FTM_FLTPOL_FLT0POL_MASK   0x1u
 
#define FTM_FLTPOL_FLT0POL_SHIFT   0
 
#define FTM_FLTPOL_FLT1POL_MASK   0x2u
 
#define FTM_FLTPOL_FLT1POL_SHIFT   1
 
#define FTM_FLTPOL_FLT2POL_MASK   0x4u
 
#define FTM_FLTPOL_FLT2POL_SHIFT   2
 
#define FTM_FLTPOL_FLT3POL_MASK   0x8u
 
#define FTM_FLTPOL_FLT3POL_SHIFT   3
 
#define FTM_FLTPOL_FLT0POL_MASK   (0x1U)
 
#define FTM_FLTPOL_FLT0POL_SHIFT   (0U)
 
#define FTM_FLTPOL_FLT0POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
 
#define FTM_FLTPOL_FLT1POL_MASK   (0x2U)
 
#define FTM_FLTPOL_FLT1POL_SHIFT   (1U)
 
#define FTM_FLTPOL_FLT1POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
 
#define FTM_FLTPOL_FLT2POL_MASK   (0x4U)
 
#define FTM_FLTPOL_FLT2POL_SHIFT   (2U)
 
#define FTM_FLTPOL_FLT2POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
 
#define FTM_FLTPOL_FLT3POL_MASK   (0x8U)
 
#define FTM_FLTPOL_FLT3POL_SHIFT   (3U)
 
#define FTM_FLTPOL_FLT3POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
 
#define FTM_FLTPOL_FLT0POL_MASK   (0x1U)
 
#define FTM_FLTPOL_FLT0POL_SHIFT   (0U)
 
#define FTM_FLTPOL_FLT0POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
 
#define FTM_FLTPOL_FLT1POL_MASK   (0x2U)
 
#define FTM_FLTPOL_FLT1POL_SHIFT   (1U)
 
#define FTM_FLTPOL_FLT1POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
 
#define FTM_FLTPOL_FLT2POL_MASK   (0x4U)
 
#define FTM_FLTPOL_FLT2POL_SHIFT   (2U)
 
#define FTM_FLTPOL_FLT2POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
 
#define FTM_FLTPOL_FLT3POL_MASK   (0x8U)
 
#define FTM_FLTPOL_FLT3POL_SHIFT   (3U)
 
#define FTM_FLTPOL_FLT3POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
 
#define FTM_FLTPOL_FLT0POL_MASK   (0x1U)
 
#define FTM_FLTPOL_FLT0POL_SHIFT   (0U)
 
#define FTM_FLTPOL_FLT0POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
 
#define FTM_FLTPOL_FLT1POL_MASK   (0x2U)
 
#define FTM_FLTPOL_FLT1POL_SHIFT   (1U)
 
#define FTM_FLTPOL_FLT1POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
 
#define FTM_FLTPOL_FLT2POL_MASK   (0x4U)
 
#define FTM_FLTPOL_FLT2POL_SHIFT   (2U)
 
#define FTM_FLTPOL_FLT2POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
 
#define FTM_FLTPOL_FLT3POL_MASK   (0x8U)
 
#define FTM_FLTPOL_FLT3POL_SHIFT   (3U)
 
#define FTM_FLTPOL_FLT3POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
 
#define FTM_FLTPOL_FLT0POL_MASK   (0x1U)
 
#define FTM_FLTPOL_FLT0POL_SHIFT   (0U)
 
#define FTM_FLTPOL_FLT0POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
 
#define FTM_FLTPOL_FLT1POL_MASK   (0x2U)
 
#define FTM_FLTPOL_FLT1POL_SHIFT   (1U)
 
#define FTM_FLTPOL_FLT1POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
 
#define FTM_FLTPOL_FLT2POL_MASK   (0x4U)
 
#define FTM_FLTPOL_FLT2POL_SHIFT   (2U)
 
#define FTM_FLTPOL_FLT2POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
 
#define FTM_FLTPOL_FLT3POL_MASK   (0x8U)
 
#define FTM_FLTPOL_FLT3POL_SHIFT   (3U)
 
#define FTM_FLTPOL_FLT3POL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
 

SYNCONF - Synchronization Configuration

#define FTM_SYNCONF_HWTRIGMODE_MASK   (0x1U)
 
#define FTM_SYNCONF_HWTRIGMODE_SHIFT   (0U)
 
#define FTM_SYNCONF_HWTRIGMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
 
#define FTM_SYNCONF_CNTINC_MASK   (0x4U)
 
#define FTM_SYNCONF_CNTINC_SHIFT   (2U)
 
#define FTM_SYNCONF_CNTINC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
 
#define FTM_SYNCONF_INVC_MASK   (0x10U)
 
#define FTM_SYNCONF_INVC_SHIFT   (4U)
 
#define FTM_SYNCONF_INVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
 
#define FTM_SYNCONF_SWOC_MASK   (0x20U)
 
#define FTM_SYNCONF_SWOC_SHIFT   (5U)
 
#define FTM_SYNCONF_SWOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
 
#define FTM_SYNCONF_SYNCMODE_MASK   (0x80U)
 
#define FTM_SYNCONF_SYNCMODE_SHIFT   (7U)
 
#define FTM_SYNCONF_SYNCMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
 
#define FTM_SYNCONF_SWRSTCNT_MASK   (0x100U)
 
#define FTM_SYNCONF_SWRSTCNT_SHIFT   (8U)
 
#define FTM_SYNCONF_SWRSTCNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
 
#define FTM_SYNCONF_SWWRBUF_MASK   (0x200U)
 
#define FTM_SYNCONF_SWWRBUF_SHIFT   (9U)
 
#define FTM_SYNCONF_SWWRBUF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
 
#define FTM_SYNCONF_SWOM_MASK   (0x400U)
 
#define FTM_SYNCONF_SWOM_SHIFT   (10U)
 
#define FTM_SYNCONF_SWOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
 
#define FTM_SYNCONF_SWINVC_MASK   (0x800U)
 
#define FTM_SYNCONF_SWINVC_SHIFT   (11U)
 
#define FTM_SYNCONF_SWINVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
 
#define FTM_SYNCONF_SWSOC_MASK   (0x1000U)
 
#define FTM_SYNCONF_SWSOC_SHIFT   (12U)
 
#define FTM_SYNCONF_SWSOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
 
#define FTM_SYNCONF_HWRSTCNT_MASK   (0x10000U)
 
#define FTM_SYNCONF_HWRSTCNT_SHIFT   (16U)
 
#define FTM_SYNCONF_HWRSTCNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
 
#define FTM_SYNCONF_HWWRBUF_MASK   (0x20000U)
 
#define FTM_SYNCONF_HWWRBUF_SHIFT   (17U)
 
#define FTM_SYNCONF_HWWRBUF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
 
#define FTM_SYNCONF_HWOM_MASK   (0x40000U)
 
#define FTM_SYNCONF_HWOM_SHIFT   (18U)
 
#define FTM_SYNCONF_HWOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
 
#define FTM_SYNCONF_HWINVC_MASK   (0x80000U)
 
#define FTM_SYNCONF_HWINVC_SHIFT   (19U)
 
#define FTM_SYNCONF_HWINVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
 
#define FTM_SYNCONF_HWSOC_MASK   (0x100000U)
 
#define FTM_SYNCONF_HWSOC_SHIFT   (20U)
 
#define FTM_SYNCONF_HWSOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
 
#define FTM_SYNCONF_HWTRIGMODE_MASK   0x1u
 
#define FTM_SYNCONF_HWTRIGMODE_SHIFT   0
 
#define FTM_SYNCONF_CNTINC_MASK   0x4u
 
#define FTM_SYNCONF_CNTINC_SHIFT   2
 
#define FTM_SYNCONF_INVC_MASK   0x10u
 
#define FTM_SYNCONF_INVC_SHIFT   4
 
#define FTM_SYNCONF_SWOC_MASK   0x20u
 
#define FTM_SYNCONF_SWOC_SHIFT   5
 
#define FTM_SYNCONF_SYNCMODE_MASK   0x80u
 
#define FTM_SYNCONF_SYNCMODE_SHIFT   7
 
#define FTM_SYNCONF_SWRSTCNT_MASK   0x100u
 
#define FTM_SYNCONF_SWRSTCNT_SHIFT   8
 
#define FTM_SYNCONF_SWWRBUF_MASK   0x200u
 
#define FTM_SYNCONF_SWWRBUF_SHIFT   9
 
#define FTM_SYNCONF_SWOM_MASK   0x400u
 
#define FTM_SYNCONF_SWOM_SHIFT   10
 
#define FTM_SYNCONF_SWINVC_MASK   0x800u
 
#define FTM_SYNCONF_SWINVC_SHIFT   11
 
#define FTM_SYNCONF_SWSOC_MASK   0x1000u
 
#define FTM_SYNCONF_SWSOC_SHIFT   12
 
#define FTM_SYNCONF_HWRSTCNT_MASK   0x10000u
 
#define FTM_SYNCONF_HWRSTCNT_SHIFT   16
 
#define FTM_SYNCONF_HWWRBUF_MASK   0x20000u
 
#define FTM_SYNCONF_HWWRBUF_SHIFT   17
 
#define FTM_SYNCONF_HWOM_MASK   0x40000u
 
#define FTM_SYNCONF_HWOM_SHIFT   18
 
#define FTM_SYNCONF_HWINVC_MASK   0x80000u
 
#define FTM_SYNCONF_HWINVC_SHIFT   19
 
#define FTM_SYNCONF_HWSOC_MASK   0x100000u
 
#define FTM_SYNCONF_HWSOC_SHIFT   20
 
#define FTM_SYNCONF_HWTRIGMODE_MASK   (0x1U)
 
#define FTM_SYNCONF_HWTRIGMODE_SHIFT   (0U)
 
#define FTM_SYNCONF_HWTRIGMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
 
#define FTM_SYNCONF_CNTINC_MASK   (0x4U)
 
#define FTM_SYNCONF_CNTINC_SHIFT   (2U)
 
#define FTM_SYNCONF_CNTINC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
 
#define FTM_SYNCONF_INVC_MASK   (0x10U)
 
#define FTM_SYNCONF_INVC_SHIFT   (4U)
 
#define FTM_SYNCONF_INVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
 
#define FTM_SYNCONF_SWOC_MASK   (0x20U)
 
#define FTM_SYNCONF_SWOC_SHIFT   (5U)
 
#define FTM_SYNCONF_SWOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
 
#define FTM_SYNCONF_SYNCMODE_MASK   (0x80U)
 
#define FTM_SYNCONF_SYNCMODE_SHIFT   (7U)
 
#define FTM_SYNCONF_SYNCMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
 
#define FTM_SYNCONF_SWRSTCNT_MASK   (0x100U)
 
#define FTM_SYNCONF_SWRSTCNT_SHIFT   (8U)
 
#define FTM_SYNCONF_SWRSTCNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
 
#define FTM_SYNCONF_SWWRBUF_MASK   (0x200U)
 
#define FTM_SYNCONF_SWWRBUF_SHIFT   (9U)
 
#define FTM_SYNCONF_SWWRBUF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
 
#define FTM_SYNCONF_SWOM_MASK   (0x400U)
 
#define FTM_SYNCONF_SWOM_SHIFT   (10U)
 
#define FTM_SYNCONF_SWOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
 
#define FTM_SYNCONF_SWINVC_MASK   (0x800U)
 
#define FTM_SYNCONF_SWINVC_SHIFT   (11U)
 
#define FTM_SYNCONF_SWINVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
 
#define FTM_SYNCONF_SWSOC_MASK   (0x1000U)
 
#define FTM_SYNCONF_SWSOC_SHIFT   (12U)
 
#define FTM_SYNCONF_SWSOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
 
#define FTM_SYNCONF_HWRSTCNT_MASK   (0x10000U)
 
#define FTM_SYNCONF_HWRSTCNT_SHIFT   (16U)
 
#define FTM_SYNCONF_HWRSTCNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
 
#define FTM_SYNCONF_HWWRBUF_MASK   (0x20000U)
 
#define FTM_SYNCONF_HWWRBUF_SHIFT   (17U)
 
#define FTM_SYNCONF_HWWRBUF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
 
#define FTM_SYNCONF_HWOM_MASK   (0x40000U)
 
#define FTM_SYNCONF_HWOM_SHIFT   (18U)
 
#define FTM_SYNCONF_HWOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
 
#define FTM_SYNCONF_HWINVC_MASK   (0x80000U)
 
#define FTM_SYNCONF_HWINVC_SHIFT   (19U)
 
#define FTM_SYNCONF_HWINVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
 
#define FTM_SYNCONF_HWSOC_MASK   (0x100000U)
 
#define FTM_SYNCONF_HWSOC_SHIFT   (20U)
 
#define FTM_SYNCONF_HWSOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
 
#define FTM_SYNCONF_HWTRIGMODE_MASK   (0x1U)
 
#define FTM_SYNCONF_HWTRIGMODE_SHIFT   (0U)
 
#define FTM_SYNCONF_HWTRIGMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
 
#define FTM_SYNCONF_CNTINC_MASK   (0x4U)
 
#define FTM_SYNCONF_CNTINC_SHIFT   (2U)
 
#define FTM_SYNCONF_CNTINC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
 
#define FTM_SYNCONF_INVC_MASK   (0x10U)
 
#define FTM_SYNCONF_INVC_SHIFT   (4U)
 
#define FTM_SYNCONF_INVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
 
#define FTM_SYNCONF_SWOC_MASK   (0x20U)
 
#define FTM_SYNCONF_SWOC_SHIFT   (5U)
 
#define FTM_SYNCONF_SWOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
 
#define FTM_SYNCONF_SYNCMODE_MASK   (0x80U)
 
#define FTM_SYNCONF_SYNCMODE_SHIFT   (7U)
 
#define FTM_SYNCONF_SYNCMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
 
#define FTM_SYNCONF_SWRSTCNT_MASK   (0x100U)
 
#define FTM_SYNCONF_SWRSTCNT_SHIFT   (8U)
 
#define FTM_SYNCONF_SWRSTCNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
 
#define FTM_SYNCONF_SWWRBUF_MASK   (0x200U)
 
#define FTM_SYNCONF_SWWRBUF_SHIFT   (9U)
 
#define FTM_SYNCONF_SWWRBUF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
 
#define FTM_SYNCONF_SWOM_MASK   (0x400U)
 
#define FTM_SYNCONF_SWOM_SHIFT   (10U)
 
#define FTM_SYNCONF_SWOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
 
#define FTM_SYNCONF_SWINVC_MASK   (0x800U)
 
#define FTM_SYNCONF_SWINVC_SHIFT   (11U)
 
#define FTM_SYNCONF_SWINVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
 
#define FTM_SYNCONF_SWSOC_MASK   (0x1000U)
 
#define FTM_SYNCONF_SWSOC_SHIFT   (12U)
 
#define FTM_SYNCONF_SWSOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
 
#define FTM_SYNCONF_HWRSTCNT_MASK   (0x10000U)
 
#define FTM_SYNCONF_HWRSTCNT_SHIFT   (16U)
 
#define FTM_SYNCONF_HWRSTCNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
 
#define FTM_SYNCONF_HWWRBUF_MASK   (0x20000U)
 
#define FTM_SYNCONF_HWWRBUF_SHIFT   (17U)
 
#define FTM_SYNCONF_HWWRBUF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
 
#define FTM_SYNCONF_HWOM_MASK   (0x40000U)
 
#define FTM_SYNCONF_HWOM_SHIFT   (18U)
 
#define FTM_SYNCONF_HWOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
 
#define FTM_SYNCONF_HWINVC_MASK   (0x80000U)
 
#define FTM_SYNCONF_HWINVC_SHIFT   (19U)
 
#define FTM_SYNCONF_HWINVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
 
#define FTM_SYNCONF_HWSOC_MASK   (0x100000U)
 
#define FTM_SYNCONF_HWSOC_SHIFT   (20U)
 
#define FTM_SYNCONF_HWSOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
 
#define FTM_SYNCONF_HWTRIGMODE_MASK   (0x1U)
 
#define FTM_SYNCONF_HWTRIGMODE_SHIFT   (0U)
 
#define FTM_SYNCONF_HWTRIGMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
 
#define FTM_SYNCONF_CNTINC_MASK   (0x4U)
 
#define FTM_SYNCONF_CNTINC_SHIFT   (2U)
 
#define FTM_SYNCONF_CNTINC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
 
#define FTM_SYNCONF_INVC_MASK   (0x10U)
 
#define FTM_SYNCONF_INVC_SHIFT   (4U)
 
#define FTM_SYNCONF_INVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
 
#define FTM_SYNCONF_SWOC_MASK   (0x20U)
 
#define FTM_SYNCONF_SWOC_SHIFT   (5U)
 
#define FTM_SYNCONF_SWOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
 
#define FTM_SYNCONF_SYNCMODE_MASK   (0x80U)
 
#define FTM_SYNCONF_SYNCMODE_SHIFT   (7U)
 
#define FTM_SYNCONF_SYNCMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
 
#define FTM_SYNCONF_SWRSTCNT_MASK   (0x100U)
 
#define FTM_SYNCONF_SWRSTCNT_SHIFT   (8U)
 
#define FTM_SYNCONF_SWRSTCNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
 
#define FTM_SYNCONF_SWWRBUF_MASK   (0x200U)
 
#define FTM_SYNCONF_SWWRBUF_SHIFT   (9U)
 
#define FTM_SYNCONF_SWWRBUF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
 
#define FTM_SYNCONF_SWOM_MASK   (0x400U)
 
#define FTM_SYNCONF_SWOM_SHIFT   (10U)
 
#define FTM_SYNCONF_SWOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
 
#define FTM_SYNCONF_SWINVC_MASK   (0x800U)
 
#define FTM_SYNCONF_SWINVC_SHIFT   (11U)
 
#define FTM_SYNCONF_SWINVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
 
#define FTM_SYNCONF_SWSOC_MASK   (0x1000U)
 
#define FTM_SYNCONF_SWSOC_SHIFT   (12U)
 
#define FTM_SYNCONF_SWSOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
 
#define FTM_SYNCONF_HWRSTCNT_MASK   (0x10000U)
 
#define FTM_SYNCONF_HWRSTCNT_SHIFT   (16U)
 
#define FTM_SYNCONF_HWRSTCNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
 
#define FTM_SYNCONF_HWWRBUF_MASK   (0x20000U)
 
#define FTM_SYNCONF_HWWRBUF_SHIFT   (17U)
 
#define FTM_SYNCONF_HWWRBUF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
 
#define FTM_SYNCONF_HWOM_MASK   (0x40000U)
 
#define FTM_SYNCONF_HWOM_SHIFT   (18U)
 
#define FTM_SYNCONF_HWOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
 
#define FTM_SYNCONF_HWINVC_MASK   (0x80000U)
 
#define FTM_SYNCONF_HWINVC_SHIFT   (19U)
 
#define FTM_SYNCONF_HWINVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
 
#define FTM_SYNCONF_HWSOC_MASK   (0x100000U)
 
#define FTM_SYNCONF_HWSOC_SHIFT   (20U)
 
#define FTM_SYNCONF_HWSOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
 
#define FTM_SYNCONF_HWTRIGMODE_MASK   (0x1U)
 
#define FTM_SYNCONF_HWTRIGMODE_SHIFT   (0U)
 
#define FTM_SYNCONF_HWTRIGMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
 
#define FTM_SYNCONF_CNTINC_MASK   (0x4U)
 
#define FTM_SYNCONF_CNTINC_SHIFT   (2U)
 
#define FTM_SYNCONF_CNTINC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
 
#define FTM_SYNCONF_INVC_MASK   (0x10U)
 
#define FTM_SYNCONF_INVC_SHIFT   (4U)
 
#define FTM_SYNCONF_INVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
 
#define FTM_SYNCONF_SWOC_MASK   (0x20U)
 
#define FTM_SYNCONF_SWOC_SHIFT   (5U)
 
#define FTM_SYNCONF_SWOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
 
#define FTM_SYNCONF_SYNCMODE_MASK   (0x80U)
 
#define FTM_SYNCONF_SYNCMODE_SHIFT   (7U)
 
#define FTM_SYNCONF_SYNCMODE(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
 
#define FTM_SYNCONF_SWRSTCNT_MASK   (0x100U)
 
#define FTM_SYNCONF_SWRSTCNT_SHIFT   (8U)
 
#define FTM_SYNCONF_SWRSTCNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
 
#define FTM_SYNCONF_SWWRBUF_MASK   (0x200U)
 
#define FTM_SYNCONF_SWWRBUF_SHIFT   (9U)
 
#define FTM_SYNCONF_SWWRBUF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
 
#define FTM_SYNCONF_SWOM_MASK   (0x400U)
 
#define FTM_SYNCONF_SWOM_SHIFT   (10U)
 
#define FTM_SYNCONF_SWOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
 
#define FTM_SYNCONF_SWINVC_MASK   (0x800U)
 
#define FTM_SYNCONF_SWINVC_SHIFT   (11U)
 
#define FTM_SYNCONF_SWINVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
 
#define FTM_SYNCONF_SWSOC_MASK   (0x1000U)
 
#define FTM_SYNCONF_SWSOC_SHIFT   (12U)
 
#define FTM_SYNCONF_SWSOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
 
#define FTM_SYNCONF_HWRSTCNT_MASK   (0x10000U)
 
#define FTM_SYNCONF_HWRSTCNT_SHIFT   (16U)
 
#define FTM_SYNCONF_HWRSTCNT(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
 
#define FTM_SYNCONF_HWWRBUF_MASK   (0x20000U)
 
#define FTM_SYNCONF_HWWRBUF_SHIFT   (17U)
 
#define FTM_SYNCONF_HWWRBUF(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
 
#define FTM_SYNCONF_HWOM_MASK   (0x40000U)
 
#define FTM_SYNCONF_HWOM_SHIFT   (18U)
 
#define FTM_SYNCONF_HWOM(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
 
#define FTM_SYNCONF_HWINVC_MASK   (0x80000U)
 
#define FTM_SYNCONF_HWINVC_SHIFT   (19U)
 
#define FTM_SYNCONF_HWINVC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
 
#define FTM_SYNCONF_HWSOC_MASK   (0x100000U)
 
#define FTM_SYNCONF_HWSOC_SHIFT   (20U)
 
#define FTM_SYNCONF_HWSOC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
 

INVCTRL - FTM Inverting Control

#define FTM_INVCTRL_INV0EN_MASK   (0x1U)
 
#define FTM_INVCTRL_INV0EN_SHIFT   (0U)
 
#define FTM_INVCTRL_INV0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
 
#define FTM_INVCTRL_INV1EN_MASK   (0x2U)
 
#define FTM_INVCTRL_INV1EN_SHIFT   (1U)
 
#define FTM_INVCTRL_INV1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
 
#define FTM_INVCTRL_INV2EN_MASK   (0x4U)
 
#define FTM_INVCTRL_INV2EN_SHIFT   (2U)
 
#define FTM_INVCTRL_INV2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
 
#define FTM_INVCTRL_INV3EN_MASK   (0x8U)
 
#define FTM_INVCTRL_INV3EN_SHIFT   (3U)
 
#define FTM_INVCTRL_INV3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
 
#define FTM_INVCTRL_INV0EN_MASK   0x1u
 
#define FTM_INVCTRL_INV0EN_SHIFT   0
 
#define FTM_INVCTRL_INV1EN_MASK   0x2u
 
#define FTM_INVCTRL_INV1EN_SHIFT   1
 
#define FTM_INVCTRL_INV2EN_MASK   0x4u
 
#define FTM_INVCTRL_INV2EN_SHIFT   2
 
#define FTM_INVCTRL_INV3EN_MASK   0x8u
 
#define FTM_INVCTRL_INV3EN_SHIFT   3
 
#define FTM_INVCTRL_INV0EN_MASK   (0x1U)
 
#define FTM_INVCTRL_INV0EN_SHIFT   (0U)
 
#define FTM_INVCTRL_INV0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
 
#define FTM_INVCTRL_INV1EN_MASK   (0x2U)
 
#define FTM_INVCTRL_INV1EN_SHIFT   (1U)
 
#define FTM_INVCTRL_INV1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
 
#define FTM_INVCTRL_INV2EN_MASK   (0x4U)
 
#define FTM_INVCTRL_INV2EN_SHIFT   (2U)
 
#define FTM_INVCTRL_INV2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
 
#define FTM_INVCTRL_INV3EN_MASK   (0x8U)
 
#define FTM_INVCTRL_INV3EN_SHIFT   (3U)
 
#define FTM_INVCTRL_INV3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
 
#define FTM_INVCTRL_INV0EN_MASK   (0x1U)
 
#define FTM_INVCTRL_INV0EN_SHIFT   (0U)
 
#define FTM_INVCTRL_INV0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
 
#define FTM_INVCTRL_INV1EN_MASK   (0x2U)
 
#define FTM_INVCTRL_INV1EN_SHIFT   (1U)
 
#define FTM_INVCTRL_INV1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
 
#define FTM_INVCTRL_INV2EN_MASK   (0x4U)
 
#define FTM_INVCTRL_INV2EN_SHIFT   (2U)
 
#define FTM_INVCTRL_INV2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
 
#define FTM_INVCTRL_INV3EN_MASK   (0x8U)
 
#define FTM_INVCTRL_INV3EN_SHIFT   (3U)
 
#define FTM_INVCTRL_INV3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
 
#define FTM_INVCTRL_INV0EN_MASK   (0x1U)
 
#define FTM_INVCTRL_INV0EN_SHIFT   (0U)
 
#define FTM_INVCTRL_INV0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
 
#define FTM_INVCTRL_INV1EN_MASK   (0x2U)
 
#define FTM_INVCTRL_INV1EN_SHIFT   (1U)
 
#define FTM_INVCTRL_INV1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
 
#define FTM_INVCTRL_INV2EN_MASK   (0x4U)
 
#define FTM_INVCTRL_INV2EN_SHIFT   (2U)
 
#define FTM_INVCTRL_INV2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
 
#define FTM_INVCTRL_INV3EN_MASK   (0x8U)
 
#define FTM_INVCTRL_INV3EN_SHIFT   (3U)
 
#define FTM_INVCTRL_INV3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
 
#define FTM_INVCTRL_INV0EN_MASK   (0x1U)
 
#define FTM_INVCTRL_INV0EN_SHIFT   (0U)
 
#define FTM_INVCTRL_INV0EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
 
#define FTM_INVCTRL_INV1EN_MASK   (0x2U)
 
#define FTM_INVCTRL_INV1EN_SHIFT   (1U)
 
#define FTM_INVCTRL_INV1EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
 
#define FTM_INVCTRL_INV2EN_MASK   (0x4U)
 
#define FTM_INVCTRL_INV2EN_SHIFT   (2U)
 
#define FTM_INVCTRL_INV2EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
 
#define FTM_INVCTRL_INV3EN_MASK   (0x8U)
 
#define FTM_INVCTRL_INV3EN_SHIFT   (3U)
 
#define FTM_INVCTRL_INV3EN(x)   (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
 

SWOCTRL - FTM Software Output Control

#define FTM_SWOCTRL_CH0OC_MASK   (0x1U)
 
#define FTM_SWOCTRL_CH0OC_SHIFT   (0U)
 
#define FTM_SWOCTRL_CH0OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
 
#define FTM_SWOCTRL_CH1OC_MASK   (0x2U)
 
#define FTM_SWOCTRL_CH1OC_SHIFT   (1U)
 
#define FTM_SWOCTRL_CH1OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
 
#define FTM_SWOCTRL_CH2OC_MASK   (0x4U)
 
#define FTM_SWOCTRL_CH2OC_SHIFT   (2U)
 
#define FTM_SWOCTRL_CH2OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
 
#define FTM_SWOCTRL_CH3OC_MASK   (0x8U)
 
#define FTM_SWOCTRL_CH3OC_SHIFT   (3U)
 
#define FTM_SWOCTRL_CH3OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
 
#define FTM_SWOCTRL_CH4OC_MASK   (0x10U)
 
#define FTM_SWOCTRL_CH4OC_SHIFT   (4U)
 
#define FTM_SWOCTRL_CH4OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
 
#define FTM_SWOCTRL_CH5OC_MASK   (0x20U)
 
#define FTM_SWOCTRL_CH5OC_SHIFT   (5U)
 
#define FTM_SWOCTRL_CH5OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
 
#define FTM_SWOCTRL_CH6OC_MASK   (0x40U)
 
#define FTM_SWOCTRL_CH6OC_SHIFT   (6U)
 
#define FTM_SWOCTRL_CH6OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
 
#define FTM_SWOCTRL_CH7OC_MASK   (0x80U)
 
#define FTM_SWOCTRL_CH7OC_SHIFT   (7U)
 
#define FTM_SWOCTRL_CH7OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
 
#define FTM_SWOCTRL_CH0OCV_MASK   (0x100U)
 
#define FTM_SWOCTRL_CH0OCV_SHIFT   (8U)
 
#define FTM_SWOCTRL_CH0OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
 
#define FTM_SWOCTRL_CH1OCV_MASK   (0x200U)
 
#define FTM_SWOCTRL_CH1OCV_SHIFT   (9U)
 
#define FTM_SWOCTRL_CH1OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
 
#define FTM_SWOCTRL_CH2OCV_MASK   (0x400U)
 
#define FTM_SWOCTRL_CH2OCV_SHIFT   (10U)
 
#define FTM_SWOCTRL_CH2OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
 
#define FTM_SWOCTRL_CH3OCV_MASK   (0x800U)
 
#define FTM_SWOCTRL_CH3OCV_SHIFT   (11U)
 
#define FTM_SWOCTRL_CH3OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
 
#define FTM_SWOCTRL_CH4OCV_MASK   (0x1000U)
 
#define FTM_SWOCTRL_CH4OCV_SHIFT   (12U)
 
#define FTM_SWOCTRL_CH4OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
 
#define FTM_SWOCTRL_CH5OCV_MASK   (0x2000U)
 
#define FTM_SWOCTRL_CH5OCV_SHIFT   (13U)
 
#define FTM_SWOCTRL_CH5OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
 
#define FTM_SWOCTRL_CH6OCV_MASK   (0x4000U)
 
#define FTM_SWOCTRL_CH6OCV_SHIFT   (14U)
 
#define FTM_SWOCTRL_CH6OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
 
#define FTM_SWOCTRL_CH7OCV_MASK   (0x8000U)
 
#define FTM_SWOCTRL_CH7OCV_SHIFT   (15U)
 
#define FTM_SWOCTRL_CH7OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
 
#define FTM_SWOCTRL_CH0OC_MASK   0x1u
 
#define FTM_SWOCTRL_CH0OC_SHIFT   0
 
#define FTM_SWOCTRL_CH1OC_MASK   0x2u
 
#define FTM_SWOCTRL_CH1OC_SHIFT   1
 
#define FTM_SWOCTRL_CH2OC_MASK   0x4u
 
#define FTM_SWOCTRL_CH2OC_SHIFT   2
 
#define FTM_SWOCTRL_CH3OC_MASK   0x8u
 
#define FTM_SWOCTRL_CH3OC_SHIFT   3
 
#define FTM_SWOCTRL_CH4OC_MASK   0x10u
 
#define FTM_SWOCTRL_CH4OC_SHIFT   4
 
#define FTM_SWOCTRL_CH5OC_MASK   0x20u
 
#define FTM_SWOCTRL_CH5OC_SHIFT   5
 
#define FTM_SWOCTRL_CH6OC_MASK   0x40u
 
#define FTM_SWOCTRL_CH6OC_SHIFT   6
 
#define FTM_SWOCTRL_CH7OC_MASK   0x80u
 
#define FTM_SWOCTRL_CH7OC_SHIFT   7
 
#define FTM_SWOCTRL_CH0OCV_MASK   0x100u
 
#define FTM_SWOCTRL_CH0OCV_SHIFT   8
 
#define FTM_SWOCTRL_CH1OCV_MASK   0x200u
 
#define FTM_SWOCTRL_CH1OCV_SHIFT   9
 
#define FTM_SWOCTRL_CH2OCV_MASK   0x400u
 
#define FTM_SWOCTRL_CH2OCV_SHIFT   10
 
#define FTM_SWOCTRL_CH3OCV_MASK   0x800u
 
#define FTM_SWOCTRL_CH3OCV_SHIFT   11
 
#define FTM_SWOCTRL_CH4OCV_MASK   0x1000u
 
#define FTM_SWOCTRL_CH4OCV_SHIFT   12
 
#define FTM_SWOCTRL_CH5OCV_MASK   0x2000u
 
#define FTM_SWOCTRL_CH5OCV_SHIFT   13
 
#define FTM_SWOCTRL_CH6OCV_MASK   0x4000u
 
#define FTM_SWOCTRL_CH6OCV_SHIFT   14
 
#define FTM_SWOCTRL_CH7OCV_MASK   0x8000u
 
#define FTM_SWOCTRL_CH7OCV_SHIFT   15
 
#define FTM_SWOCTRL_CH0OC_MASK   (0x1U)
 
#define FTM_SWOCTRL_CH0OC_SHIFT   (0U)
 
#define FTM_SWOCTRL_CH0OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
 
#define FTM_SWOCTRL_CH1OC_MASK   (0x2U)
 
#define FTM_SWOCTRL_CH1OC_SHIFT   (1U)
 
#define FTM_SWOCTRL_CH1OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
 
#define FTM_SWOCTRL_CH2OC_MASK   (0x4U)
 
#define FTM_SWOCTRL_CH2OC_SHIFT   (2U)
 
#define FTM_SWOCTRL_CH2OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
 
#define FTM_SWOCTRL_CH3OC_MASK   (0x8U)
 
#define FTM_SWOCTRL_CH3OC_SHIFT   (3U)
 
#define FTM_SWOCTRL_CH3OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
 
#define FTM_SWOCTRL_CH4OC_MASK   (0x10U)
 
#define FTM_SWOCTRL_CH4OC_SHIFT   (4U)
 
#define FTM_SWOCTRL_CH4OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
 
#define FTM_SWOCTRL_CH5OC_MASK   (0x20U)
 
#define FTM_SWOCTRL_CH5OC_SHIFT   (5U)
 
#define FTM_SWOCTRL_CH5OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
 
#define FTM_SWOCTRL_CH6OC_MASK   (0x40U)
 
#define FTM_SWOCTRL_CH6OC_SHIFT   (6U)
 
#define FTM_SWOCTRL_CH6OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
 
#define FTM_SWOCTRL_CH7OC_MASK   (0x80U)
 
#define FTM_SWOCTRL_CH7OC_SHIFT   (7U)
 
#define FTM_SWOCTRL_CH7OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
 
#define FTM_SWOCTRL_CH0OCV_MASK   (0x100U)
 
#define FTM_SWOCTRL_CH0OCV_SHIFT   (8U)
 
#define FTM_SWOCTRL_CH0OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
 
#define FTM_SWOCTRL_CH1OCV_MASK   (0x200U)
 
#define FTM_SWOCTRL_CH1OCV_SHIFT   (9U)
 
#define FTM_SWOCTRL_CH1OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
 
#define FTM_SWOCTRL_CH2OCV_MASK   (0x400U)
 
#define FTM_SWOCTRL_CH2OCV_SHIFT   (10U)
 
#define FTM_SWOCTRL_CH2OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
 
#define FTM_SWOCTRL_CH3OCV_MASK   (0x800U)
 
#define FTM_SWOCTRL_CH3OCV_SHIFT   (11U)
 
#define FTM_SWOCTRL_CH3OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
 
#define FTM_SWOCTRL_CH4OCV_MASK   (0x1000U)
 
#define FTM_SWOCTRL_CH4OCV_SHIFT   (12U)
 
#define FTM_SWOCTRL_CH4OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
 
#define FTM_SWOCTRL_CH5OCV_MASK   (0x2000U)
 
#define FTM_SWOCTRL_CH5OCV_SHIFT   (13U)
 
#define FTM_SWOCTRL_CH5OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
 
#define FTM_SWOCTRL_CH6OCV_MASK   (0x4000U)
 
#define FTM_SWOCTRL_CH6OCV_SHIFT   (14U)
 
#define FTM_SWOCTRL_CH6OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
 
#define FTM_SWOCTRL_CH7OCV_MASK   (0x8000U)
 
#define FTM_SWOCTRL_CH7OCV_SHIFT   (15U)
 
#define FTM_SWOCTRL_CH7OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
 
#define FTM_SWOCTRL_CH0OC_MASK   (0x1U)
 
#define FTM_SWOCTRL_CH0OC_SHIFT   (0U)
 
#define FTM_SWOCTRL_CH0OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
 
#define FTM_SWOCTRL_CH1OC_MASK   (0x2U)
 
#define FTM_SWOCTRL_CH1OC_SHIFT   (1U)
 
#define FTM_SWOCTRL_CH1OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
 
#define FTM_SWOCTRL_CH2OC_MASK   (0x4U)
 
#define FTM_SWOCTRL_CH2OC_SHIFT   (2U)
 
#define FTM_SWOCTRL_CH2OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
 
#define FTM_SWOCTRL_CH3OC_MASK   (0x8U)
 
#define FTM_SWOCTRL_CH3OC_SHIFT   (3U)
 
#define FTM_SWOCTRL_CH3OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
 
#define FTM_SWOCTRL_CH4OC_MASK   (0x10U)
 
#define FTM_SWOCTRL_CH4OC_SHIFT   (4U)
 
#define FTM_SWOCTRL_CH4OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
 
#define FTM_SWOCTRL_CH5OC_MASK   (0x20U)
 
#define FTM_SWOCTRL_CH5OC_SHIFT   (5U)
 
#define FTM_SWOCTRL_CH5OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
 
#define FTM_SWOCTRL_CH6OC_MASK   (0x40U)
 
#define FTM_SWOCTRL_CH6OC_SHIFT   (6U)
 
#define FTM_SWOCTRL_CH6OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
 
#define FTM_SWOCTRL_CH7OC_MASK   (0x80U)
 
#define FTM_SWOCTRL_CH7OC_SHIFT   (7U)
 
#define FTM_SWOCTRL_CH7OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
 
#define FTM_SWOCTRL_CH0OCV_MASK   (0x100U)
 
#define FTM_SWOCTRL_CH0OCV_SHIFT   (8U)
 
#define FTM_SWOCTRL_CH0OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
 
#define FTM_SWOCTRL_CH1OCV_MASK   (0x200U)
 
#define FTM_SWOCTRL_CH1OCV_SHIFT   (9U)
 
#define FTM_SWOCTRL_CH1OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
 
#define FTM_SWOCTRL_CH2OCV_MASK   (0x400U)
 
#define FTM_SWOCTRL_CH2OCV_SHIFT   (10U)
 
#define FTM_SWOCTRL_CH2OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
 
#define FTM_SWOCTRL_CH3OCV_MASK   (0x800U)
 
#define FTM_SWOCTRL_CH3OCV_SHIFT   (11U)
 
#define FTM_SWOCTRL_CH3OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
 
#define FTM_SWOCTRL_CH4OCV_MASK   (0x1000U)
 
#define FTM_SWOCTRL_CH4OCV_SHIFT   (12U)
 
#define FTM_SWOCTRL_CH4OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
 
#define FTM_SWOCTRL_CH5OCV_MASK   (0x2000U)
 
#define FTM_SWOCTRL_CH5OCV_SHIFT   (13U)
 
#define FTM_SWOCTRL_CH5OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
 
#define FTM_SWOCTRL_CH6OCV_MASK   (0x4000U)
 
#define FTM_SWOCTRL_CH6OCV_SHIFT   (14U)
 
#define FTM_SWOCTRL_CH6OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
 
#define FTM_SWOCTRL_CH7OCV_MASK   (0x8000U)
 
#define FTM_SWOCTRL_CH7OCV_SHIFT   (15U)
 
#define FTM_SWOCTRL_CH7OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
 
#define FTM_SWOCTRL_CH0OC_MASK   (0x1U)
 
#define FTM_SWOCTRL_CH0OC_SHIFT   (0U)
 
#define FTM_SWOCTRL_CH0OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
 
#define FTM_SWOCTRL_CH1OC_MASK   (0x2U)
 
#define FTM_SWOCTRL_CH1OC_SHIFT   (1U)
 
#define FTM_SWOCTRL_CH1OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
 
#define FTM_SWOCTRL_CH2OC_MASK   (0x4U)
 
#define FTM_SWOCTRL_CH2OC_SHIFT   (2U)
 
#define FTM_SWOCTRL_CH2OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
 
#define FTM_SWOCTRL_CH3OC_MASK   (0x8U)
 
#define FTM_SWOCTRL_CH3OC_SHIFT   (3U)
 
#define FTM_SWOCTRL_CH3OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
 
#define FTM_SWOCTRL_CH4OC_MASK   (0x10U)
 
#define FTM_SWOCTRL_CH4OC_SHIFT   (4U)
 
#define FTM_SWOCTRL_CH4OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
 
#define FTM_SWOCTRL_CH5OC_MASK   (0x20U)
 
#define FTM_SWOCTRL_CH5OC_SHIFT   (5U)
 
#define FTM_SWOCTRL_CH5OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
 
#define FTM_SWOCTRL_CH6OC_MASK   (0x40U)
 
#define FTM_SWOCTRL_CH6OC_SHIFT   (6U)
 
#define FTM_SWOCTRL_CH6OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
 
#define FTM_SWOCTRL_CH7OC_MASK   (0x80U)
 
#define FTM_SWOCTRL_CH7OC_SHIFT   (7U)
 
#define FTM_SWOCTRL_CH7OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
 
#define FTM_SWOCTRL_CH0OCV_MASK   (0x100U)
 
#define FTM_SWOCTRL_CH0OCV_SHIFT   (8U)
 
#define FTM_SWOCTRL_CH0OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
 
#define FTM_SWOCTRL_CH1OCV_MASK   (0x200U)
 
#define FTM_SWOCTRL_CH1OCV_SHIFT   (9U)
 
#define FTM_SWOCTRL_CH1OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
 
#define FTM_SWOCTRL_CH2OCV_MASK   (0x400U)
 
#define FTM_SWOCTRL_CH2OCV_SHIFT   (10U)
 
#define FTM_SWOCTRL_CH2OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
 
#define FTM_SWOCTRL_CH3OCV_MASK   (0x800U)
 
#define FTM_SWOCTRL_CH3OCV_SHIFT   (11U)
 
#define FTM_SWOCTRL_CH3OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
 
#define FTM_SWOCTRL_CH4OCV_MASK   (0x1000U)
 
#define FTM_SWOCTRL_CH4OCV_SHIFT   (12U)
 
#define FTM_SWOCTRL_CH4OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
 
#define FTM_SWOCTRL_CH5OCV_MASK   (0x2000U)
 
#define FTM_SWOCTRL_CH5OCV_SHIFT   (13U)
 
#define FTM_SWOCTRL_CH5OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
 
#define FTM_SWOCTRL_CH6OCV_MASK   (0x4000U)
 
#define FTM_SWOCTRL_CH6OCV_SHIFT   (14U)
 
#define FTM_SWOCTRL_CH6OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
 
#define FTM_SWOCTRL_CH7OCV_MASK   (0x8000U)
 
#define FTM_SWOCTRL_CH7OCV_SHIFT   (15U)
 
#define FTM_SWOCTRL_CH7OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
 
#define FTM_SWOCTRL_CH0OC_MASK   (0x1U)
 
#define FTM_SWOCTRL_CH0OC_SHIFT   (0U)
 
#define FTM_SWOCTRL_CH0OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
 
#define FTM_SWOCTRL_CH1OC_MASK   (0x2U)
 
#define FTM_SWOCTRL_CH1OC_SHIFT   (1U)
 
#define FTM_SWOCTRL_CH1OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
 
#define FTM_SWOCTRL_CH2OC_MASK   (0x4U)
 
#define FTM_SWOCTRL_CH2OC_SHIFT   (2U)
 
#define FTM_SWOCTRL_CH2OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
 
#define FTM_SWOCTRL_CH3OC_MASK   (0x8U)
 
#define FTM_SWOCTRL_CH3OC_SHIFT   (3U)
 
#define FTM_SWOCTRL_CH3OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
 
#define FTM_SWOCTRL_CH4OC_MASK   (0x10U)
 
#define FTM_SWOCTRL_CH4OC_SHIFT   (4U)
 
#define FTM_SWOCTRL_CH4OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
 
#define FTM_SWOCTRL_CH5OC_MASK   (0x20U)
 
#define FTM_SWOCTRL_CH5OC_SHIFT   (5U)
 
#define FTM_SWOCTRL_CH5OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
 
#define FTM_SWOCTRL_CH6OC_MASK   (0x40U)
 
#define FTM_SWOCTRL_CH6OC_SHIFT   (6U)
 
#define FTM_SWOCTRL_CH6OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
 
#define FTM_SWOCTRL_CH7OC_MASK   (0x80U)
 
#define FTM_SWOCTRL_CH7OC_SHIFT   (7U)
 
#define FTM_SWOCTRL_CH7OC(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
 
#define FTM_SWOCTRL_CH0OCV_MASK   (0x100U)
 
#define FTM_SWOCTRL_CH0OCV_SHIFT   (8U)
 
#define FTM_SWOCTRL_CH0OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
 
#define FTM_SWOCTRL_CH1OCV_MASK   (0x200U)
 
#define FTM_SWOCTRL_CH1OCV_SHIFT   (9U)
 
#define FTM_SWOCTRL_CH1OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
 
#define FTM_SWOCTRL_CH2OCV_MASK   (0x400U)
 
#define FTM_SWOCTRL_CH2OCV_SHIFT   (10U)
 
#define FTM_SWOCTRL_CH2OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
 
#define FTM_SWOCTRL_CH3OCV_MASK   (0x800U)
 
#define FTM_SWOCTRL_CH3OCV_SHIFT   (11U)
 
#define FTM_SWOCTRL_CH3OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
 
#define FTM_SWOCTRL_CH4OCV_MASK   (0x1000U)
 
#define FTM_SWOCTRL_CH4OCV_SHIFT   (12U)
 
#define FTM_SWOCTRL_CH4OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
 
#define FTM_SWOCTRL_CH5OCV_MASK   (0x2000U)
 
#define FTM_SWOCTRL_CH5OCV_SHIFT   (13U)
 
#define FTM_SWOCTRL_CH5OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
 
#define FTM_SWOCTRL_CH6OCV_MASK   (0x4000U)
 
#define FTM_SWOCTRL_CH6OCV_SHIFT   (14U)
 
#define FTM_SWOCTRL_CH6OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
 
#define FTM_SWOCTRL_CH7OCV_MASK   (0x8000U)
 
#define FTM_SWOCTRL_CH7OCV_SHIFT   (15U)
 
#define FTM_SWOCTRL_CH7OCV(x)   (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
 

PWMLOAD - FTM PWM Load

#define FTM_PWMLOAD_CH0SEL_MASK   (0x1U)
 
#define FTM_PWMLOAD_CH0SEL_SHIFT   (0U)
 
#define FTM_PWMLOAD_CH0SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
 
#define FTM_PWMLOAD_CH1SEL_MASK   (0x2U)
 
#define FTM_PWMLOAD_CH1SEL_SHIFT   (1U)
 
#define FTM_PWMLOAD_CH1SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
 
#define FTM_PWMLOAD_CH2SEL_MASK   (0x4U)
 
#define FTM_PWMLOAD_CH2SEL_SHIFT   (2U)
 
#define FTM_PWMLOAD_CH2SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
 
#define FTM_PWMLOAD_CH3SEL_MASK   (0x8U)
 
#define FTM_PWMLOAD_CH3SEL_SHIFT   (3U)
 
#define FTM_PWMLOAD_CH3SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
 
#define FTM_PWMLOAD_CH4SEL_MASK   (0x10U)
 
#define FTM_PWMLOAD_CH4SEL_SHIFT   (4U)
 
#define FTM_PWMLOAD_CH4SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
 
#define FTM_PWMLOAD_CH5SEL_MASK   (0x20U)
 
#define FTM_PWMLOAD_CH5SEL_SHIFT   (5U)
 
#define FTM_PWMLOAD_CH5SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
 
#define FTM_PWMLOAD_CH6SEL_MASK   (0x40U)
 
#define FTM_PWMLOAD_CH6SEL_SHIFT   (6U)
 
#define FTM_PWMLOAD_CH6SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
 
#define FTM_PWMLOAD_CH7SEL_MASK   (0x80U)
 
#define FTM_PWMLOAD_CH7SEL_SHIFT   (7U)
 
#define FTM_PWMLOAD_CH7SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
 
#define FTM_PWMLOAD_LDOK_MASK   (0x200U)
 
#define FTM_PWMLOAD_LDOK_SHIFT   (9U)
 
#define FTM_PWMLOAD_LDOK(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
 
#define FTM_PWMLOAD_CH0SEL_MASK   0x1u
 
#define FTM_PWMLOAD_CH0SEL_SHIFT   0
 
#define FTM_PWMLOAD_CH1SEL_MASK   0x2u
 
#define FTM_PWMLOAD_CH1SEL_SHIFT   1
 
#define FTM_PWMLOAD_CH2SEL_MASK   0x4u
 
#define FTM_PWMLOAD_CH2SEL_SHIFT   2
 
#define FTM_PWMLOAD_CH3SEL_MASK   0x8u
 
#define FTM_PWMLOAD_CH3SEL_SHIFT   3
 
#define FTM_PWMLOAD_CH4SEL_MASK   0x10u
 
#define FTM_PWMLOAD_CH4SEL_SHIFT   4
 
#define FTM_PWMLOAD_CH5SEL_MASK   0x20u
 
#define FTM_PWMLOAD_CH5SEL_SHIFT   5
 
#define FTM_PWMLOAD_CH6SEL_MASK   0x40u
 
#define FTM_PWMLOAD_CH6SEL_SHIFT   6
 
#define FTM_PWMLOAD_CH7SEL_MASK   0x80u
 
#define FTM_PWMLOAD_CH7SEL_SHIFT   7
 
#define FTM_PWMLOAD_LDOK_MASK   0x200u
 
#define FTM_PWMLOAD_LDOK_SHIFT   9
 
#define FTM_PWMLOAD_CH0SEL_MASK   (0x1U)
 
#define FTM_PWMLOAD_CH0SEL_SHIFT   (0U)
 
#define FTM_PWMLOAD_CH0SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
 
#define FTM_PWMLOAD_CH1SEL_MASK   (0x2U)
 
#define FTM_PWMLOAD_CH1SEL_SHIFT   (1U)
 
#define FTM_PWMLOAD_CH1SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
 
#define FTM_PWMLOAD_CH2SEL_MASK   (0x4U)
 
#define FTM_PWMLOAD_CH2SEL_SHIFT   (2U)
 
#define FTM_PWMLOAD_CH2SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
 
#define FTM_PWMLOAD_CH3SEL_MASK   (0x8U)
 
#define FTM_PWMLOAD_CH3SEL_SHIFT   (3U)
 
#define FTM_PWMLOAD_CH3SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
 
#define FTM_PWMLOAD_CH4SEL_MASK   (0x10U)
 
#define FTM_PWMLOAD_CH4SEL_SHIFT   (4U)
 
#define FTM_PWMLOAD_CH4SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
 
#define FTM_PWMLOAD_CH5SEL_MASK   (0x20U)
 
#define FTM_PWMLOAD_CH5SEL_SHIFT   (5U)
 
#define FTM_PWMLOAD_CH5SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
 
#define FTM_PWMLOAD_CH6SEL_MASK   (0x40U)
 
#define FTM_PWMLOAD_CH6SEL_SHIFT   (6U)
 
#define FTM_PWMLOAD_CH6SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
 
#define FTM_PWMLOAD_CH7SEL_MASK   (0x80U)
 
#define FTM_PWMLOAD_CH7SEL_SHIFT   (7U)
 
#define FTM_PWMLOAD_CH7SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
 
#define FTM_PWMLOAD_LDOK_MASK   (0x200U)
 
#define FTM_PWMLOAD_LDOK_SHIFT   (9U)
 
#define FTM_PWMLOAD_LDOK(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
 
#define FTM_PWMLOAD_CH0SEL_MASK   (0x1U)
 
#define FTM_PWMLOAD_CH0SEL_SHIFT   (0U)
 
#define FTM_PWMLOAD_CH0SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
 
#define FTM_PWMLOAD_CH1SEL_MASK   (0x2U)
 
#define FTM_PWMLOAD_CH1SEL_SHIFT   (1U)
 
#define FTM_PWMLOAD_CH1SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
 
#define FTM_PWMLOAD_CH2SEL_MASK   (0x4U)
 
#define FTM_PWMLOAD_CH2SEL_SHIFT   (2U)
 
#define FTM_PWMLOAD_CH2SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
 
#define FTM_PWMLOAD_CH3SEL_MASK   (0x8U)
 
#define FTM_PWMLOAD_CH3SEL_SHIFT   (3U)
 
#define FTM_PWMLOAD_CH3SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
 
#define FTM_PWMLOAD_CH4SEL_MASK   (0x10U)
 
#define FTM_PWMLOAD_CH4SEL_SHIFT   (4U)
 
#define FTM_PWMLOAD_CH4SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
 
#define FTM_PWMLOAD_CH5SEL_MASK   (0x20U)
 
#define FTM_PWMLOAD_CH5SEL_SHIFT   (5U)
 
#define FTM_PWMLOAD_CH5SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
 
#define FTM_PWMLOAD_CH6SEL_MASK   (0x40U)
 
#define FTM_PWMLOAD_CH6SEL_SHIFT   (6U)
 
#define FTM_PWMLOAD_CH6SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
 
#define FTM_PWMLOAD_CH7SEL_MASK   (0x80U)
 
#define FTM_PWMLOAD_CH7SEL_SHIFT   (7U)
 
#define FTM_PWMLOAD_CH7SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
 
#define FTM_PWMLOAD_LDOK_MASK   (0x200U)
 
#define FTM_PWMLOAD_LDOK_SHIFT   (9U)
 
#define FTM_PWMLOAD_LDOK(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
 
#define FTM_PWMLOAD_CH0SEL_MASK   (0x1U)
 
#define FTM_PWMLOAD_CH0SEL_SHIFT   (0U)
 
#define FTM_PWMLOAD_CH0SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
 
#define FTM_PWMLOAD_CH1SEL_MASK   (0x2U)
 
#define FTM_PWMLOAD_CH1SEL_SHIFT   (1U)
 
#define FTM_PWMLOAD_CH1SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
 
#define FTM_PWMLOAD_CH2SEL_MASK   (0x4U)
 
#define FTM_PWMLOAD_CH2SEL_SHIFT   (2U)
 
#define FTM_PWMLOAD_CH2SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
 
#define FTM_PWMLOAD_CH3SEL_MASK   (0x8U)
 
#define FTM_PWMLOAD_CH3SEL_SHIFT   (3U)
 
#define FTM_PWMLOAD_CH3SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
 
#define FTM_PWMLOAD_CH4SEL_MASK   (0x10U)
 
#define FTM_PWMLOAD_CH4SEL_SHIFT   (4U)
 
#define FTM_PWMLOAD_CH4SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
 
#define FTM_PWMLOAD_CH5SEL_MASK   (0x20U)
 
#define FTM_PWMLOAD_CH5SEL_SHIFT   (5U)
 
#define FTM_PWMLOAD_CH5SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
 
#define FTM_PWMLOAD_CH6SEL_MASK   (0x40U)
 
#define FTM_PWMLOAD_CH6SEL_SHIFT   (6U)
 
#define FTM_PWMLOAD_CH6SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
 
#define FTM_PWMLOAD_CH7SEL_MASK   (0x80U)
 
#define FTM_PWMLOAD_CH7SEL_SHIFT   (7U)
 
#define FTM_PWMLOAD_CH7SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
 
#define FTM_PWMLOAD_LDOK_MASK   (0x200U)
 
#define FTM_PWMLOAD_LDOK_SHIFT   (9U)
 
#define FTM_PWMLOAD_LDOK(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
 
#define FTM_PWMLOAD_CH0SEL_MASK   (0x1U)
 
#define FTM_PWMLOAD_CH0SEL_SHIFT   (0U)
 
#define FTM_PWMLOAD_CH0SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
 
#define FTM_PWMLOAD_CH1SEL_MASK   (0x2U)
 
#define FTM_PWMLOAD_CH1SEL_SHIFT   (1U)
 
#define FTM_PWMLOAD_CH1SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
 
#define FTM_PWMLOAD_CH2SEL_MASK   (0x4U)
 
#define FTM_PWMLOAD_CH2SEL_SHIFT   (2U)
 
#define FTM_PWMLOAD_CH2SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
 
#define FTM_PWMLOAD_CH3SEL_MASK   (0x8U)
 
#define FTM_PWMLOAD_CH3SEL_SHIFT   (3U)
 
#define FTM_PWMLOAD_CH3SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
 
#define FTM_PWMLOAD_CH4SEL_MASK   (0x10U)
 
#define FTM_PWMLOAD_CH4SEL_SHIFT   (4U)
 
#define FTM_PWMLOAD_CH4SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
 
#define FTM_PWMLOAD_CH5SEL_MASK   (0x20U)
 
#define FTM_PWMLOAD_CH5SEL_SHIFT   (5U)
 
#define FTM_PWMLOAD_CH5SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
 
#define FTM_PWMLOAD_CH6SEL_MASK   (0x40U)
 
#define FTM_PWMLOAD_CH6SEL_SHIFT   (6U)
 
#define FTM_PWMLOAD_CH6SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
 
#define FTM_PWMLOAD_CH7SEL_MASK   (0x80U)
 
#define FTM_PWMLOAD_CH7SEL_SHIFT   (7U)
 
#define FTM_PWMLOAD_CH7SEL(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
 
#define FTM_PWMLOAD_LDOK_MASK   (0x200U)
 
#define FTM_PWMLOAD_LDOK_SHIFT   (9U)
 
#define FTM_PWMLOAD_LDOK(x)   (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
 

Macro Definition Documentation

◆ FTM0

#define FTM0   ((FTM_Type *)FTM0_BASE)

Peripheral FTM0 base pointer

◆ FTM0_BASE

#define FTM0_BASE   (0x40038000u)

Peripheral FTM0 base address

◆ FTM1

#define FTM1   ((FTM_Type *)FTM1_BASE)

Peripheral FTM1 base pointer

◆ FTM1_BASE

#define FTM1_BASE   (0x40039000u)

Peripheral FTM1 base address

◆ FTM2

#define FTM2   ((FTM_Type *)FTM2_BASE)

Peripheral FTM2 base pointer

◆ FTM2_BASE

#define FTM2_BASE   (0x400B8000u)

Peripheral FTM2 base address

◆ FTM_BASE_ADDRS

#define FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE }

Array initializer of FTM peripheral base addresses

◆ FTM_BASE_PTRS

#define FTM_BASE_PTRS   { FTM0, FTM1, FTM2 }

Array initializer of FTM peripheral base pointers

◆ FTM_CnSC_CHF [1/5]

#define FTM_CnSC_CHF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)

CHF - Channel Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_CnSC_CHF [2/5]

#define FTM_CnSC_CHF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)

CHF - Channel Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_CnSC_CHF [3/5]

#define FTM_CnSC_CHF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)

CHF - Channel Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_CnSC_CHF [4/5]

#define FTM_CnSC_CHF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)

CHF - Channel Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_CnSC_CHF [5/5]

#define FTM_CnSC_CHF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)

CHF - Channel Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_CnSC_CHIE [1/5]

#define FTM_CnSC_CHIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)

CHIE - Channel Interrupt Enable 0b0..Disable channel interrupts. Use software polling. 0b1..Enable channel interrupts.

◆ FTM_CnSC_CHIE [2/5]

#define FTM_CnSC_CHIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)

CHIE - Channel Interrupt Enable 0b0..Disable channel interrupts. Use software polling. 0b1..Enable channel interrupts.

◆ FTM_CnSC_CHIE [3/5]

#define FTM_CnSC_CHIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)

CHIE - Channel Interrupt Enable 0b0..Disable channel interrupts. Use software polling. 0b1..Enable channel interrupts.

◆ FTM_CnSC_CHIE [4/5]

#define FTM_CnSC_CHIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)

CHIE - Channel Interrupt Enable 0b0..Disable channel interrupts. Use software polling. 0b1..Enable channel interrupts.

◆ FTM_CnSC_CHIE [5/5]

#define FTM_CnSC_CHIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)

CHIE - Channel Interrupt Enable 0b0..Disable channel interrupts. Use software polling. 0b1..Enable channel interrupts.

◆ FTM_CnSC_DMA [1/5]

#define FTM_CnSC_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)

DMA - DMA Enable 0b0..Disable DMA transfers. 0b1..Enable DMA transfers.

◆ FTM_CnSC_DMA [2/5]

#define FTM_CnSC_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)

DMA - DMA Enable 0b0..Disable DMA transfers. 0b1..Enable DMA transfers.

◆ FTM_CnSC_DMA [3/5]

#define FTM_CnSC_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)

DMA - DMA Enable 0b0..Disable DMA transfers. 0b1..Enable DMA transfers.

◆ FTM_CnSC_DMA [4/5]

#define FTM_CnSC_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)

DMA - DMA Enable 0b0..Disable DMA transfers. 0b1..Enable DMA transfers.

◆ FTM_CnSC_DMA [5/5]

#define FTM_CnSC_DMA ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)

DMA - DMA Enable 0b0..Disable DMA transfers. 0b1..Enable DMA transfers.

◆ FTM_CnSC_ICRST

#define FTM_CnSC_ICRST ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)

ICRST - FTM counter reset by the selected input capture event. 0b0..FTM counter is not reset when the selected channel (n) input event is detected. 0b1..FTM counter is reset when the selected channel (n) input event is detected.

◆ FTM_COMBINE_COMBINE0 [1/5]

#define FTM_COMBINE_COMBINE0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)

COMBINE0 - Combine Channels For n = 0 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE0 [2/5]

#define FTM_COMBINE_COMBINE0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)

COMBINE0 - Combine Channels For n = 0 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE0 [3/5]

#define FTM_COMBINE_COMBINE0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)

COMBINE0 - Combine Channels For n = 0 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE0 [4/5]

#define FTM_COMBINE_COMBINE0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)

COMBINE0 - Combine Channels For n = 0 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE0 [5/5]

#define FTM_COMBINE_COMBINE0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)

COMBINE0 - Combine Channels For n = 0 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE1 [1/5]

#define FTM_COMBINE_COMBINE1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)

COMBINE1 - Combine Channels For n = 2 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE1 [2/5]

#define FTM_COMBINE_COMBINE1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)

COMBINE1 - Combine Channels For n = 2 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE1 [3/5]

#define FTM_COMBINE_COMBINE1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)

COMBINE1 - Combine Channels For n = 2 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE1 [4/5]

#define FTM_COMBINE_COMBINE1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)

COMBINE1 - Combine Channels For n = 2 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE1 [5/5]

#define FTM_COMBINE_COMBINE1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)

COMBINE1 - Combine Channels For n = 2 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE2 [1/5]

#define FTM_COMBINE_COMBINE2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)

COMBINE2 - Combine Channels For n = 4 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE2 [2/5]

#define FTM_COMBINE_COMBINE2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)

COMBINE2 - Combine Channels For n = 4 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE2 [3/5]

#define FTM_COMBINE_COMBINE2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)

COMBINE2 - Combine Channels For n = 4 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE2 [4/5]

#define FTM_COMBINE_COMBINE2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)

COMBINE2 - Combine Channels For n = 4 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE2 [5/5]

#define FTM_COMBINE_COMBINE2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)

COMBINE2 - Combine Channels For n = 4 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE3 [1/5]

#define FTM_COMBINE_COMBINE3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)

COMBINE3 - Combine Channels For n = 6 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE3 [2/5]

#define FTM_COMBINE_COMBINE3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)

COMBINE3 - Combine Channels For n = 6 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE3 [3/5]

#define FTM_COMBINE_COMBINE3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)

COMBINE3 - Combine Channels For n = 6 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE3 [4/5]

#define FTM_COMBINE_COMBINE3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)

COMBINE3 - Combine Channels For n = 6 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMBINE3 [5/5]

#define FTM_COMBINE_COMBINE3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)

COMBINE3 - Combine Channels For n = 6 0b0..Channels (n) and (n+1) are independent. 0b1..Channels (n) and (n+1) are combined.

◆ FTM_COMBINE_COMP0 [1/5]

#define FTM_COMBINE_COMP0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)

COMP0 - Complement Of Channel (n) For n = 0 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP0 [2/5]

#define FTM_COMBINE_COMP0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)

COMP0 - Complement Of Channel (n) For n = 0 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP0 [3/5]

#define FTM_COMBINE_COMP0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)

COMP0 - Complement Of Channel (n) For n = 0 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP0 [4/5]

#define FTM_COMBINE_COMP0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)

COMP0 - Complement Of Channel (n) For n = 0 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP0 [5/5]

#define FTM_COMBINE_COMP0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)

COMP0 - Complement Of Channel (n) For n = 0 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP1 [1/5]

#define FTM_COMBINE_COMP1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)

COMP1 - Complement Of Channel (n) For n = 2 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP1 [2/5]

#define FTM_COMBINE_COMP1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)

COMP1 - Complement Of Channel (n) For n = 2 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP1 [3/5]

#define FTM_COMBINE_COMP1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)

COMP1 - Complement Of Channel (n) For n = 2 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP1 [4/5]

#define FTM_COMBINE_COMP1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)

COMP1 - Complement Of Channel (n) For n = 2 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP1 [5/5]

#define FTM_COMBINE_COMP1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)

COMP1 - Complement Of Channel (n) For n = 2 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP2 [1/5]

#define FTM_COMBINE_COMP2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)

COMP2 - Complement Of Channel (n) For n = 4 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP2 [2/5]

#define FTM_COMBINE_COMP2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)

COMP2 - Complement Of Channel (n) For n = 4 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP2 [3/5]

#define FTM_COMBINE_COMP2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)

COMP2 - Complement Of Channel (n) For n = 4 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP2 [4/5]

#define FTM_COMBINE_COMP2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)

COMP2 - Complement Of Channel (n) For n = 4 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP2 [5/5]

#define FTM_COMBINE_COMP2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)

COMP2 - Complement Of Channel (n) For n = 4 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP3 [1/5]

#define FTM_COMBINE_COMP3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)

COMP3 - Complement Of Channel (n) for n = 6 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP3 [2/5]

#define FTM_COMBINE_COMP3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)

COMP3 - Complement Of Channel (n) for n = 6 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP3 [3/5]

#define FTM_COMBINE_COMP3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)

COMP3 - Complement Of Channel (n) for n = 6 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP3 [4/5]

#define FTM_COMBINE_COMP3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)

COMP3 - Complement Of Channel (n) for n = 6 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_COMP3 [5/5]

#define FTM_COMBINE_COMP3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)

COMP3 - Complement Of Channel (n) for n = 6 0b0..The channel (n+1) output is the same as the channel (n) output. 0b1..The channel (n+1) output is the complement of the channel (n) output.

◆ FTM_COMBINE_DECAP0 [1/5]

#define FTM_COMBINE_DECAP0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)

DECAP0 - Dual Edge Capture Mode Captures For n = 0 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP0 [2/5]

#define FTM_COMBINE_DECAP0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)

DECAP0 - Dual Edge Capture Mode Captures For n = 0 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP0 [3/5]

#define FTM_COMBINE_DECAP0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)

DECAP0 - Dual Edge Capture Mode Captures For n = 0 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP0 [4/5]

#define FTM_COMBINE_DECAP0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)

DECAP0 - Dual Edge Capture Mode Captures For n = 0 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP0 [5/5]

#define FTM_COMBINE_DECAP0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)

DECAP0 - Dual Edge Capture Mode Captures For n = 0 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP1 [1/5]

#define FTM_COMBINE_DECAP1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)

DECAP1 - Dual Edge Capture Mode Captures For n = 2 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP1 [2/5]

#define FTM_COMBINE_DECAP1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)

DECAP1 - Dual Edge Capture Mode Captures For n = 2 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP1 [3/5]

#define FTM_COMBINE_DECAP1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)

DECAP1 - Dual Edge Capture Mode Captures For n = 2 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP1 [4/5]

#define FTM_COMBINE_DECAP1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)

DECAP1 - Dual Edge Capture Mode Captures For n = 2 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP1 [5/5]

#define FTM_COMBINE_DECAP1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)

DECAP1 - Dual Edge Capture Mode Captures For n = 2 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP2 [1/5]

#define FTM_COMBINE_DECAP2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)

DECAP2 - Dual Edge Capture Mode Captures For n = 4 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP2 [2/5]

#define FTM_COMBINE_DECAP2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)

DECAP2 - Dual Edge Capture Mode Captures For n = 4 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP2 [3/5]

#define FTM_COMBINE_DECAP2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)

DECAP2 - Dual Edge Capture Mode Captures For n = 4 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP2 [4/5]

#define FTM_COMBINE_DECAP2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)

DECAP2 - Dual Edge Capture Mode Captures For n = 4 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP2 [5/5]

#define FTM_COMBINE_DECAP2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)

DECAP2 - Dual Edge Capture Mode Captures For n = 4 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP3 [1/5]

#define FTM_COMBINE_DECAP3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)

DECAP3 - Dual Edge Capture Mode Captures For n = 6 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP3 [2/5]

#define FTM_COMBINE_DECAP3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)

DECAP3 - Dual Edge Capture Mode Captures For n = 6 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP3 [3/5]

#define FTM_COMBINE_DECAP3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)

DECAP3 - Dual Edge Capture Mode Captures For n = 6 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP3 [4/5]

#define FTM_COMBINE_DECAP3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)

DECAP3 - Dual Edge Capture Mode Captures For n = 6 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAP3 [5/5]

#define FTM_COMBINE_DECAP3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)

DECAP3 - Dual Edge Capture Mode Captures For n = 6 0b0..The dual edge captures are inactive. 0b1..The dual edge captures are active.

◆ FTM_COMBINE_DECAPEN0 [1/5]

#define FTM_COMBINE_DECAPEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)

DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN0 [2/5]

#define FTM_COMBINE_DECAPEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)

DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN0 [3/5]

#define FTM_COMBINE_DECAPEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)

DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN0 [4/5]

#define FTM_COMBINE_DECAPEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)

DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN0 [5/5]

#define FTM_COMBINE_DECAPEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)

DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN1 [1/5]

#define FTM_COMBINE_DECAPEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)

DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN1 [2/5]

#define FTM_COMBINE_DECAPEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)

DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN1 [3/5]

#define FTM_COMBINE_DECAPEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)

DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN1 [4/5]

#define FTM_COMBINE_DECAPEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)

DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN1 [5/5]

#define FTM_COMBINE_DECAPEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)

DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN2 [1/5]

#define FTM_COMBINE_DECAPEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)

DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN2 [2/5]

#define FTM_COMBINE_DECAPEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)

DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN2 [3/5]

#define FTM_COMBINE_DECAPEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)

DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN2 [4/5]

#define FTM_COMBINE_DECAPEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)

DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN2 [5/5]

#define FTM_COMBINE_DECAPEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)

DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN3 [1/5]

#define FTM_COMBINE_DECAPEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)

DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN3 [2/5]

#define FTM_COMBINE_DECAPEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)

DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN3 [3/5]

#define FTM_COMBINE_DECAPEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)

DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN3 [4/5]

#define FTM_COMBINE_DECAPEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)

DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DECAPEN3 [5/5]

#define FTM_COMBINE_DECAPEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)

DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 0b1..The Dual Edge Capture mode in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN0 [1/5]

#define FTM_COMBINE_DTEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)

DTEN0 - Deadtime Enable For n = 0 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN0 [2/5]

#define FTM_COMBINE_DTEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)

DTEN0 - Deadtime Enable For n = 0 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN0 [3/5]

#define FTM_COMBINE_DTEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)

DTEN0 - Deadtime Enable For n = 0 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN0 [4/5]

#define FTM_COMBINE_DTEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)

DTEN0 - Deadtime Enable For n = 0 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN0 [5/5]

#define FTM_COMBINE_DTEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)

DTEN0 - Deadtime Enable For n = 0 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN1 [1/5]

#define FTM_COMBINE_DTEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)

DTEN1 - Deadtime Enable For n = 2 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN1 [2/5]

#define FTM_COMBINE_DTEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)

DTEN1 - Deadtime Enable For n = 2 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN1 [3/5]

#define FTM_COMBINE_DTEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)

DTEN1 - Deadtime Enable For n = 2 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN1 [4/5]

#define FTM_COMBINE_DTEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)

DTEN1 - Deadtime Enable For n = 2 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN1 [5/5]

#define FTM_COMBINE_DTEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)

DTEN1 - Deadtime Enable For n = 2 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN2 [1/5]

#define FTM_COMBINE_DTEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)

DTEN2 - Deadtime Enable For n = 4 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN2 [2/5]

#define FTM_COMBINE_DTEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)

DTEN2 - Deadtime Enable For n = 4 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN2 [3/5]

#define FTM_COMBINE_DTEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)

DTEN2 - Deadtime Enable For n = 4 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN2 [4/5]

#define FTM_COMBINE_DTEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)

DTEN2 - Deadtime Enable For n = 4 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN2 [5/5]

#define FTM_COMBINE_DTEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)

DTEN2 - Deadtime Enable For n = 4 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN3 [1/5]

#define FTM_COMBINE_DTEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)

DTEN3 - Deadtime Enable For n = 6 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN3 [2/5]

#define FTM_COMBINE_DTEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)

DTEN3 - Deadtime Enable For n = 6 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN3 [3/5]

#define FTM_COMBINE_DTEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)

DTEN3 - Deadtime Enable For n = 6 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN3 [4/5]

#define FTM_COMBINE_DTEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)

DTEN3 - Deadtime Enable For n = 6 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_DTEN3 [5/5]

#define FTM_COMBINE_DTEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)

DTEN3 - Deadtime Enable For n = 6 0b0..The deadtime insertion in this pair of channels is disabled. 0b1..The deadtime insertion in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN0 [1/5]

#define FTM_COMBINE_FAULTEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)

FAULTEN0 - Fault Control Enable For n = 0 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN0 [2/5]

#define FTM_COMBINE_FAULTEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)

FAULTEN0 - Fault Control Enable For n = 0 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN0 [3/5]

#define FTM_COMBINE_FAULTEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)

FAULTEN0 - Fault Control Enable For n = 0 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN0 [4/5]

#define FTM_COMBINE_FAULTEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)

FAULTEN0 - Fault Control Enable For n = 0 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN0 [5/5]

#define FTM_COMBINE_FAULTEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)

FAULTEN0 - Fault Control Enable For n = 0 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN1 [1/5]

#define FTM_COMBINE_FAULTEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)

FAULTEN1 - Fault Control Enable For n = 2 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN1 [2/5]

#define FTM_COMBINE_FAULTEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)

FAULTEN1 - Fault Control Enable For n = 2 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN1 [3/5]

#define FTM_COMBINE_FAULTEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)

FAULTEN1 - Fault Control Enable For n = 2 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN1 [4/5]

#define FTM_COMBINE_FAULTEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)

FAULTEN1 - Fault Control Enable For n = 2 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN1 [5/5]

#define FTM_COMBINE_FAULTEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)

FAULTEN1 - Fault Control Enable For n = 2 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN2 [1/5]

#define FTM_COMBINE_FAULTEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)

FAULTEN2 - Fault Control Enable For n = 4 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN2 [2/5]

#define FTM_COMBINE_FAULTEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)

FAULTEN2 - Fault Control Enable For n = 4 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN2 [3/5]

#define FTM_COMBINE_FAULTEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)

FAULTEN2 - Fault Control Enable For n = 4 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN2 [4/5]

#define FTM_COMBINE_FAULTEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)

FAULTEN2 - Fault Control Enable For n = 4 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN2 [5/5]

#define FTM_COMBINE_FAULTEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)

FAULTEN2 - Fault Control Enable For n = 4 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN3 [1/5]

#define FTM_COMBINE_FAULTEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)

FAULTEN3 - Fault Control Enable For n = 6 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN3 [2/5]

#define FTM_COMBINE_FAULTEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)

FAULTEN3 - Fault Control Enable For n = 6 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN3 [3/5]

#define FTM_COMBINE_FAULTEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)

FAULTEN3 - Fault Control Enable For n = 6 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN3 [4/5]

#define FTM_COMBINE_FAULTEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)

FAULTEN3 - Fault Control Enable For n = 6 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_FAULTEN3 [5/5]

#define FTM_COMBINE_FAULTEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)

FAULTEN3 - Fault Control Enable For n = 6 0b0..The fault control in this pair of channels is disabled. 0b1..The fault control in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN0 [1/5]

#define FTM_COMBINE_SYNCEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)

SYNCEN0 - Synchronization Enable For n = 0 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN0 [2/5]

#define FTM_COMBINE_SYNCEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)

SYNCEN0 - Synchronization Enable For n = 0 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN0 [3/5]

#define FTM_COMBINE_SYNCEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)

SYNCEN0 - Synchronization Enable For n = 0 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN0 [4/5]

#define FTM_COMBINE_SYNCEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)

SYNCEN0 - Synchronization Enable For n = 0 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN0 [5/5]

#define FTM_COMBINE_SYNCEN0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)

SYNCEN0 - Synchronization Enable For n = 0 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN1 [1/5]

#define FTM_COMBINE_SYNCEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)

SYNCEN1 - Synchronization Enable For n = 2 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN1 [2/5]

#define FTM_COMBINE_SYNCEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)

SYNCEN1 - Synchronization Enable For n = 2 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN1 [3/5]

#define FTM_COMBINE_SYNCEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)

SYNCEN1 - Synchronization Enable For n = 2 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN1 [4/5]

#define FTM_COMBINE_SYNCEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)

SYNCEN1 - Synchronization Enable For n = 2 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN1 [5/5]

#define FTM_COMBINE_SYNCEN1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)

SYNCEN1 - Synchronization Enable For n = 2 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN2 [1/5]

#define FTM_COMBINE_SYNCEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)

SYNCEN2 - Synchronization Enable For n = 4 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN2 [2/5]

#define FTM_COMBINE_SYNCEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)

SYNCEN2 - Synchronization Enable For n = 4 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN2 [3/5]

#define FTM_COMBINE_SYNCEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)

SYNCEN2 - Synchronization Enable For n = 4 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN2 [4/5]

#define FTM_COMBINE_SYNCEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)

SYNCEN2 - Synchronization Enable For n = 4 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN2 [5/5]

#define FTM_COMBINE_SYNCEN2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)

SYNCEN2 - Synchronization Enable For n = 4 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN3 [1/5]

#define FTM_COMBINE_SYNCEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)

SYNCEN3 - Synchronization Enable For n = 6 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN3 [2/5]

#define FTM_COMBINE_SYNCEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)

SYNCEN3 - Synchronization Enable For n = 6 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN3 [3/5]

#define FTM_COMBINE_SYNCEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)

SYNCEN3 - Synchronization Enable For n = 6 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN3 [4/5]

#define FTM_COMBINE_SYNCEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)

SYNCEN3 - Synchronization Enable For n = 6 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_COMBINE_SYNCEN3 [5/5]

#define FTM_COMBINE_SYNCEN3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)

SYNCEN3 - Synchronization Enable For n = 6 0b0..The PWM synchronization in this pair of channels is disabled. 0b1..The PWM synchronization in this pair of channels is enabled.

◆ FTM_CONF_GTBEEN [1/5]

#define FTM_CONF_GTBEEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)

GTBEEN - Global Time Base Enable 0b0..Use of an external global time base is disabled. 0b1..Use of an external global time base is enabled.

◆ FTM_CONF_GTBEEN [2/5]

#define FTM_CONF_GTBEEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)

GTBEEN - Global Time Base Enable 0b0..Use of an external global time base is disabled. 0b1..Use of an external global time base is enabled.

◆ FTM_CONF_GTBEEN [3/5]

#define FTM_CONF_GTBEEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)

GTBEEN - Global Time Base Enable 0b0..Use of an external global time base is disabled. 0b1..Use of an external global time base is enabled.

◆ FTM_CONF_GTBEEN [4/5]

#define FTM_CONF_GTBEEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)

GTBEEN - Global Time Base Enable 0b0..Use of an external global time base is disabled. 0b1..Use of an external global time base is enabled.

◆ FTM_CONF_GTBEEN [5/5]

#define FTM_CONF_GTBEEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)

GTBEEN - Global Time Base Enable 0b0..Use of an external global time base is disabled. 0b1..Use of an external global time base is enabled.

◆ FTM_CONF_GTBEOUT [1/5]

#define FTM_CONF_GTBEOUT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)

GTBEOUT - Global Time Base Output 0b0..A global time base signal generation is disabled. 0b1..A global time base signal generation is enabled.

◆ FTM_CONF_GTBEOUT [2/5]

#define FTM_CONF_GTBEOUT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)

GTBEOUT - Global Time Base Output 0b0..A global time base signal generation is disabled. 0b1..A global time base signal generation is enabled.

◆ FTM_CONF_GTBEOUT [3/5]

#define FTM_CONF_GTBEOUT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)

GTBEOUT - Global Time Base Output 0b0..A global time base signal generation is disabled. 0b1..A global time base signal generation is enabled.

◆ FTM_CONF_GTBEOUT [4/5]

#define FTM_CONF_GTBEOUT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)

GTBEOUT - Global Time Base Output 0b0..A global time base signal generation is disabled. 0b1..A global time base signal generation is enabled.

◆ FTM_CONF_GTBEOUT [5/5]

#define FTM_CONF_GTBEOUT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)

GTBEOUT - Global Time Base Output 0b0..A global time base signal generation is disabled. 0b1..A global time base signal generation is enabled.

◆ FTM_DEADTIME_DTPS [1/6]

#define FTM_DEADTIME_DTPS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)

DTPS - Deadtime Prescaler Value 0b0x..Divide the system clock by 1. 0b10..Divide the system clock by 4. 0b11..Divide the system clock by 16.

◆ FTM_DEADTIME_DTPS [2/6]

#define FTM_DEADTIME_DTPS ( x)    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)

DTPS - Deadtime Prescaler Value 0b0x..Divide the system clock by 1. 0b10..Divide the system clock by 4. 0b11..Divide the system clock by 16.

◆ FTM_DEADTIME_DTPS [3/6]

#define FTM_DEADTIME_DTPS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)

DTPS - Deadtime Prescaler Value 0b0x..Divide the system clock by 1. 0b10..Divide the system clock by 4. 0b11..Divide the system clock by 16.

◆ FTM_DEADTIME_DTPS [4/6]

#define FTM_DEADTIME_DTPS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)

DTPS - Deadtime Prescaler Value 0b0x..Divide the system clock by 1. 0b10..Divide the system clock by 4. 0b11..Divide the system clock by 16.

◆ FTM_DEADTIME_DTPS [5/6]

#define FTM_DEADTIME_DTPS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)

DTPS - Deadtime Prescaler Value 0b0x..Divide the system clock by 1. 0b10..Divide the system clock by 4. 0b11..Divide the system clock by 16.

◆ FTM_DEADTIME_DTPS [6/6]

#define FTM_DEADTIME_DTPS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)

DTPS - Deadtime Prescaler Value 0b0x..Divide the system clock by 1. 0b10..Divide the system clock by 4. 0b11..Divide the system clock by 16.

◆ FTM_EXTTRIG_CH0TRIG [1/5]

#define FTM_EXTTRIG_CH0TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)

CH0TRIG - Channel 0 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH0TRIG [2/5]

#define FTM_EXTTRIG_CH0TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)

CH0TRIG - Channel 0 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH0TRIG [3/5]

#define FTM_EXTTRIG_CH0TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)

CH0TRIG - Channel 0 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH0TRIG [4/5]

#define FTM_EXTTRIG_CH0TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)

CH0TRIG - Channel 0 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH0TRIG [5/5]

#define FTM_EXTTRIG_CH0TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)

CH0TRIG - Channel 0 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH1TRIG [1/5]

#define FTM_EXTTRIG_CH1TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)

CH1TRIG - Channel 1 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH1TRIG [2/5]

#define FTM_EXTTRIG_CH1TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)

CH1TRIG - Channel 1 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH1TRIG [3/5]

#define FTM_EXTTRIG_CH1TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)

CH1TRIG - Channel 1 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH1TRIG [4/5]

#define FTM_EXTTRIG_CH1TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)

CH1TRIG - Channel 1 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH1TRIG [5/5]

#define FTM_EXTTRIG_CH1TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)

CH1TRIG - Channel 1 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH2TRIG [1/5]

#define FTM_EXTTRIG_CH2TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)

CH2TRIG - Channel 2 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH2TRIG [2/5]

#define FTM_EXTTRIG_CH2TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)

CH2TRIG - Channel 2 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH2TRIG [3/5]

#define FTM_EXTTRIG_CH2TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)

CH2TRIG - Channel 2 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH2TRIG [4/5]

#define FTM_EXTTRIG_CH2TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)

CH2TRIG - Channel 2 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH2TRIG [5/5]

#define FTM_EXTTRIG_CH2TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)

CH2TRIG - Channel 2 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH3TRIG [1/5]

#define FTM_EXTTRIG_CH3TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)

CH3TRIG - Channel 3 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH3TRIG [2/5]

#define FTM_EXTTRIG_CH3TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)

CH3TRIG - Channel 3 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH3TRIG [3/5]

#define FTM_EXTTRIG_CH3TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)

CH3TRIG - Channel 3 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH3TRIG [4/5]

#define FTM_EXTTRIG_CH3TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)

CH3TRIG - Channel 3 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH3TRIG [5/5]

#define FTM_EXTTRIG_CH3TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)

CH3TRIG - Channel 3 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH4TRIG [1/5]

#define FTM_EXTTRIG_CH4TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)

CH4TRIG - Channel 4 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH4TRIG [2/5]

#define FTM_EXTTRIG_CH4TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)

CH4TRIG - Channel 4 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH4TRIG [3/5]

#define FTM_EXTTRIG_CH4TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)

CH4TRIG - Channel 4 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH4TRIG [4/5]

#define FTM_EXTTRIG_CH4TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)

CH4TRIG - Channel 4 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH4TRIG [5/5]

#define FTM_EXTTRIG_CH4TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)

CH4TRIG - Channel 4 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH5TRIG [1/5]

#define FTM_EXTTRIG_CH5TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)

CH5TRIG - Channel 5 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH5TRIG [2/5]

#define FTM_EXTTRIG_CH5TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)

CH5TRIG - Channel 5 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH5TRIG [3/5]

#define FTM_EXTTRIG_CH5TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)

CH5TRIG - Channel 5 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH5TRIG [4/5]

#define FTM_EXTTRIG_CH5TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)

CH5TRIG - Channel 5 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_CH5TRIG [5/5]

#define FTM_EXTTRIG_CH5TRIG ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)

CH5TRIG - Channel 5 Trigger Enable 0b0..The generation of the channel trigger is disabled. 0b1..The generation of the channel trigger is enabled.

◆ FTM_EXTTRIG_INITTRIGEN [1/5]

#define FTM_EXTTRIG_INITTRIGEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)

INITTRIGEN - Initialization Trigger Enable 0b0..The generation of initialization trigger is disabled. 0b1..The generation of initialization trigger is enabled.

◆ FTM_EXTTRIG_INITTRIGEN [2/5]

#define FTM_EXTTRIG_INITTRIGEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)

INITTRIGEN - Initialization Trigger Enable 0b0..The generation of initialization trigger is disabled. 0b1..The generation of initialization trigger is enabled.

◆ FTM_EXTTRIG_INITTRIGEN [3/5]

#define FTM_EXTTRIG_INITTRIGEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)

INITTRIGEN - Initialization Trigger Enable 0b0..The generation of initialization trigger is disabled. 0b1..The generation of initialization trigger is enabled.

◆ FTM_EXTTRIG_INITTRIGEN [4/5]

#define FTM_EXTTRIG_INITTRIGEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)

INITTRIGEN - Initialization Trigger Enable 0b0..The generation of initialization trigger is disabled. 0b1..The generation of initialization trigger is enabled.

◆ FTM_EXTTRIG_INITTRIGEN [5/5]

#define FTM_EXTTRIG_INITTRIGEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)

INITTRIGEN - Initialization Trigger Enable 0b0..The generation of initialization trigger is disabled. 0b1..The generation of initialization trigger is enabled.

◆ FTM_EXTTRIG_TRIGF [1/5]

#define FTM_EXTTRIG_TRIGF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)

TRIGF - Channel Trigger Flag 0b0..No channel trigger was generated. 0b1..A channel trigger was generated.

◆ FTM_EXTTRIG_TRIGF [2/5]

#define FTM_EXTTRIG_TRIGF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)

TRIGF - Channel Trigger Flag 0b0..No channel trigger was generated. 0b1..A channel trigger was generated.

◆ FTM_EXTTRIG_TRIGF [3/5]

#define FTM_EXTTRIG_TRIGF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)

TRIGF - Channel Trigger Flag 0b0..No channel trigger was generated. 0b1..A channel trigger was generated.

◆ FTM_EXTTRIG_TRIGF [4/5]

#define FTM_EXTTRIG_TRIGF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)

TRIGF - Channel Trigger Flag 0b0..No channel trigger was generated. 0b1..A channel trigger was generated.

◆ FTM_EXTTRIG_TRIGF [5/5]

#define FTM_EXTTRIG_TRIGF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)

TRIGF - Channel Trigger Flag 0b0..No channel trigger was generated. 0b1..A channel trigger was generated.

◆ FTM_FLTCTRL_FAULT0EN [1/5]

#define FTM_FLTCTRL_FAULT0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)

FAULT0EN - Fault Input 0 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT0EN [2/5]

#define FTM_FLTCTRL_FAULT0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)

FAULT0EN - Fault Input 0 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT0EN [3/5]

#define FTM_FLTCTRL_FAULT0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)

FAULT0EN - Fault Input 0 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT0EN [4/5]

#define FTM_FLTCTRL_FAULT0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)

FAULT0EN - Fault Input 0 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT0EN [5/5]

#define FTM_FLTCTRL_FAULT0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)

FAULT0EN - Fault Input 0 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT1EN [1/5]

#define FTM_FLTCTRL_FAULT1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)

FAULT1EN - Fault Input 1 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT1EN [2/5]

#define FTM_FLTCTRL_FAULT1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)

FAULT1EN - Fault Input 1 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT1EN [3/5]

#define FTM_FLTCTRL_FAULT1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)

FAULT1EN - Fault Input 1 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT1EN [4/5]

#define FTM_FLTCTRL_FAULT1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)

FAULT1EN - Fault Input 1 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT1EN [5/5]

#define FTM_FLTCTRL_FAULT1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)

FAULT1EN - Fault Input 1 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT2EN [1/5]

#define FTM_FLTCTRL_FAULT2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)

FAULT2EN - Fault Input 2 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT2EN [2/5]

#define FTM_FLTCTRL_FAULT2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)

FAULT2EN - Fault Input 2 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT2EN [3/5]

#define FTM_FLTCTRL_FAULT2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)

FAULT2EN - Fault Input 2 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT2EN [4/5]

#define FTM_FLTCTRL_FAULT2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)

FAULT2EN - Fault Input 2 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT2EN [5/5]

#define FTM_FLTCTRL_FAULT2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)

FAULT2EN - Fault Input 2 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT3EN [1/5]

#define FTM_FLTCTRL_FAULT3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)

FAULT3EN - Fault Input 3 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT3EN [2/5]

#define FTM_FLTCTRL_FAULT3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)

FAULT3EN - Fault Input 3 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT3EN [3/5]

#define FTM_FLTCTRL_FAULT3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)

FAULT3EN - Fault Input 3 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT3EN [4/5]

#define FTM_FLTCTRL_FAULT3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)

FAULT3EN - Fault Input 3 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FAULT3EN [5/5]

#define FTM_FLTCTRL_FAULT3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)

FAULT3EN - Fault Input 3 Enable 0b0..Fault input is disabled. 0b1..Fault input is enabled.

◆ FTM_FLTCTRL_FFLTR0EN [1/5]

#define FTM_FLTCTRL_FFLTR0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)

FFLTR0EN - Fault Input 0 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR0EN [2/5]

#define FTM_FLTCTRL_FFLTR0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)

FFLTR0EN - Fault Input 0 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR0EN [3/5]

#define FTM_FLTCTRL_FFLTR0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)

FFLTR0EN - Fault Input 0 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR0EN [4/5]

#define FTM_FLTCTRL_FFLTR0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)

FFLTR0EN - Fault Input 0 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR0EN [5/5]

#define FTM_FLTCTRL_FFLTR0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)

FFLTR0EN - Fault Input 0 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR1EN [1/5]

#define FTM_FLTCTRL_FFLTR1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)

FFLTR1EN - Fault Input 1 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR1EN [2/5]

#define FTM_FLTCTRL_FFLTR1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)

FFLTR1EN - Fault Input 1 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR1EN [3/5]

#define FTM_FLTCTRL_FFLTR1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)

FFLTR1EN - Fault Input 1 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR1EN [4/5]

#define FTM_FLTCTRL_FFLTR1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)

FFLTR1EN - Fault Input 1 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR1EN [5/5]

#define FTM_FLTCTRL_FFLTR1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)

FFLTR1EN - Fault Input 1 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR2EN [1/5]

#define FTM_FLTCTRL_FFLTR2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)

FFLTR2EN - Fault Input 2 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR2EN [2/5]

#define FTM_FLTCTRL_FFLTR2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)

FFLTR2EN - Fault Input 2 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR2EN [3/5]

#define FTM_FLTCTRL_FFLTR2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)

FFLTR2EN - Fault Input 2 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR2EN [4/5]

#define FTM_FLTCTRL_FFLTR2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)

FFLTR2EN - Fault Input 2 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR2EN [5/5]

#define FTM_FLTCTRL_FFLTR2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)

FFLTR2EN - Fault Input 2 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR3EN [1/5]

#define FTM_FLTCTRL_FFLTR3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)

FFLTR3EN - Fault Input 3 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR3EN [2/5]

#define FTM_FLTCTRL_FFLTR3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)

FFLTR3EN - Fault Input 3 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR3EN [3/5]

#define FTM_FLTCTRL_FFLTR3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)

FFLTR3EN - Fault Input 3 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR3EN [4/5]

#define FTM_FLTCTRL_FFLTR3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)

FFLTR3EN - Fault Input 3 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTCTRL_FFLTR3EN [5/5]

#define FTM_FLTCTRL_FFLTR3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)

FFLTR3EN - Fault Input 3 Filter Enable 0b0..Fault input filter is disabled. 0b1..Fault input filter is enabled.

◆ FTM_FLTPOL_FLT0POL [1/5]

#define FTM_FLTPOL_FLT0POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)

FLT0POL - Fault Input 0 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT0POL [2/5]

#define FTM_FLTPOL_FLT0POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)

FLT0POL - Fault Input 0 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT0POL [3/5]

#define FTM_FLTPOL_FLT0POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)

FLT0POL - Fault Input 0 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT0POL [4/5]

#define FTM_FLTPOL_FLT0POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)

FLT0POL - Fault Input 0 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT0POL [5/5]

#define FTM_FLTPOL_FLT0POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)

FLT0POL - Fault Input 0 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT1POL [1/5]

#define FTM_FLTPOL_FLT1POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)

FLT1POL - Fault Input 1 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT1POL [2/5]

#define FTM_FLTPOL_FLT1POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)

FLT1POL - Fault Input 1 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT1POL [3/5]

#define FTM_FLTPOL_FLT1POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)

FLT1POL - Fault Input 1 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT1POL [4/5]

#define FTM_FLTPOL_FLT1POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)

FLT1POL - Fault Input 1 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT1POL [5/5]

#define FTM_FLTPOL_FLT1POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)

FLT1POL - Fault Input 1 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT2POL [1/5]

#define FTM_FLTPOL_FLT2POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)

FLT2POL - Fault Input 2 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT2POL [2/5]

#define FTM_FLTPOL_FLT2POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)

FLT2POL - Fault Input 2 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT2POL [3/5]

#define FTM_FLTPOL_FLT2POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)

FLT2POL - Fault Input 2 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT2POL [4/5]

#define FTM_FLTPOL_FLT2POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)

FLT2POL - Fault Input 2 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT2POL [5/5]

#define FTM_FLTPOL_FLT2POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)

FLT2POL - Fault Input 2 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT3POL [1/5]

#define FTM_FLTPOL_FLT3POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)

FLT3POL - Fault Input 3 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT3POL [2/5]

#define FTM_FLTPOL_FLT3POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)

FLT3POL - Fault Input 3 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT3POL [3/5]

#define FTM_FLTPOL_FLT3POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)

FLT3POL - Fault Input 3 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT3POL [4/5]

#define FTM_FLTPOL_FLT3POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)

FLT3POL - Fault Input 3 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FLTPOL_FLT3POL [5/5]

#define FTM_FLTPOL_FLT3POL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)

FLT3POL - Fault Input 3 Polarity 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.

◆ FTM_FMS_FAULTF [1/5]

#define FTM_FMS_FAULTF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)

FAULTF - Fault Detection Flag 0b0..No fault condition was detected. 0b1..A fault condition was detected.

◆ FTM_FMS_FAULTF [2/5]

#define FTM_FMS_FAULTF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)

FAULTF - Fault Detection Flag 0b0..No fault condition was detected. 0b1..A fault condition was detected.

◆ FTM_FMS_FAULTF [3/5]

#define FTM_FMS_FAULTF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)

FAULTF - Fault Detection Flag 0b0..No fault condition was detected. 0b1..A fault condition was detected.

◆ FTM_FMS_FAULTF [4/5]

#define FTM_FMS_FAULTF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)

FAULTF - Fault Detection Flag 0b0..No fault condition was detected. 0b1..A fault condition was detected.

◆ FTM_FMS_FAULTF [5/5]

#define FTM_FMS_FAULTF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)

FAULTF - Fault Detection Flag 0b0..No fault condition was detected. 0b1..A fault condition was detected.

◆ FTM_FMS_FAULTF0 [1/5]

#define FTM_FMS_FAULTF0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)

FAULTF0 - Fault Detection Flag 0 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF0 [2/5]

#define FTM_FMS_FAULTF0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)

FAULTF0 - Fault Detection Flag 0 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF0 [3/5]

#define FTM_FMS_FAULTF0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)

FAULTF0 - Fault Detection Flag 0 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF0 [4/5]

#define FTM_FMS_FAULTF0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)

FAULTF0 - Fault Detection Flag 0 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF0 [5/5]

#define FTM_FMS_FAULTF0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)

FAULTF0 - Fault Detection Flag 0 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF1 [1/5]

#define FTM_FMS_FAULTF1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)

FAULTF1 - Fault Detection Flag 1 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF1 [2/5]

#define FTM_FMS_FAULTF1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)

FAULTF1 - Fault Detection Flag 1 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF1 [3/5]

#define FTM_FMS_FAULTF1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)

FAULTF1 - Fault Detection Flag 1 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF1 [4/5]

#define FTM_FMS_FAULTF1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)

FAULTF1 - Fault Detection Flag 1 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF1 [5/5]

#define FTM_FMS_FAULTF1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)

FAULTF1 - Fault Detection Flag 1 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF2 [1/5]

#define FTM_FMS_FAULTF2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)

FAULTF2 - Fault Detection Flag 2 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF2 [2/5]

#define FTM_FMS_FAULTF2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)

FAULTF2 - Fault Detection Flag 2 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF2 [3/5]

#define FTM_FMS_FAULTF2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)

FAULTF2 - Fault Detection Flag 2 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF2 [4/5]

#define FTM_FMS_FAULTF2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)

FAULTF2 - Fault Detection Flag 2 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF2 [5/5]

#define FTM_FMS_FAULTF2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)

FAULTF2 - Fault Detection Flag 2 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF3 [1/5]

#define FTM_FMS_FAULTF3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)

FAULTF3 - Fault Detection Flag 3 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF3 [2/5]

#define FTM_FMS_FAULTF3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)

FAULTF3 - Fault Detection Flag 3 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF3 [3/5]

#define FTM_FMS_FAULTF3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)

FAULTF3 - Fault Detection Flag 3 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF3 [4/5]

#define FTM_FMS_FAULTF3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)

FAULTF3 - Fault Detection Flag 3 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTF3 [5/5]

#define FTM_FMS_FAULTF3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)

FAULTF3 - Fault Detection Flag 3 0b0..No fault condition was detected at the fault input. 0b1..A fault condition was detected at the fault input.

◆ FTM_FMS_FAULTIN [1/5]

#define FTM_FMS_FAULTIN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)

FAULTIN - Fault Inputs 0b0..The logic OR of the enabled fault inputs is 0. 0b1..The logic OR of the enabled fault inputs is 1.

◆ FTM_FMS_FAULTIN [2/5]

#define FTM_FMS_FAULTIN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)

FAULTIN - Fault Inputs 0b0..The logic OR of the enabled fault inputs is 0. 0b1..The logic OR of the enabled fault inputs is 1.

◆ FTM_FMS_FAULTIN [3/5]

#define FTM_FMS_FAULTIN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)

FAULTIN - Fault Inputs 0b0..The logic OR of the enabled fault inputs is 0. 0b1..The logic OR of the enabled fault inputs is 1.

◆ FTM_FMS_FAULTIN [4/5]

#define FTM_FMS_FAULTIN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)

FAULTIN - Fault Inputs 0b0..The logic OR of the enabled fault inputs is 0. 0b1..The logic OR of the enabled fault inputs is 1.

◆ FTM_FMS_FAULTIN [5/5]

#define FTM_FMS_FAULTIN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)

FAULTIN - Fault Inputs 0b0..The logic OR of the enabled fault inputs is 0. 0b1..The logic OR of the enabled fault inputs is 1.

◆ FTM_FMS_WPEN [1/5]

#define FTM_FMS_WPEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)

WPEN - Write Protection Enable 0b0..Write protection is disabled. Write protected bits can be written. 0b1..Write protection is enabled. Write protected bits cannot be written.

◆ FTM_FMS_WPEN [2/5]

#define FTM_FMS_WPEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)

WPEN - Write Protection Enable 0b0..Write protection is disabled. Write protected bits can be written. 0b1..Write protection is enabled. Write protected bits cannot be written.

◆ FTM_FMS_WPEN [3/5]

#define FTM_FMS_WPEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)

WPEN - Write Protection Enable 0b0..Write protection is disabled. Write protected bits can be written. 0b1..Write protection is enabled. Write protected bits cannot be written.

◆ FTM_FMS_WPEN [4/5]

#define FTM_FMS_WPEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)

WPEN - Write Protection Enable 0b0..Write protection is disabled. Write protected bits can be written. 0b1..Write protection is enabled. Write protected bits cannot be written.

◆ FTM_FMS_WPEN [5/5]

#define FTM_FMS_WPEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)

WPEN - Write Protection Enable 0b0..Write protection is disabled. Write protected bits can be written. 0b1..Write protection is enabled. Write protected bits cannot be written.

◆ FTM_INVCTRL_INV0EN [1/5]

#define FTM_INVCTRL_INV0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)

INV0EN - Pair Channels 0 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV0EN [2/5]

#define FTM_INVCTRL_INV0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)

INV0EN - Pair Channels 0 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV0EN [3/5]

#define FTM_INVCTRL_INV0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)

INV0EN - Pair Channels 0 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV0EN [4/5]

#define FTM_INVCTRL_INV0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)

INV0EN - Pair Channels 0 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV0EN [5/5]

#define FTM_INVCTRL_INV0EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)

INV0EN - Pair Channels 0 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV1EN [1/5]

#define FTM_INVCTRL_INV1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)

INV1EN - Pair Channels 1 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV1EN [2/5]

#define FTM_INVCTRL_INV1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)

INV1EN - Pair Channels 1 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV1EN [3/5]

#define FTM_INVCTRL_INV1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)

INV1EN - Pair Channels 1 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV1EN [4/5]

#define FTM_INVCTRL_INV1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)

INV1EN - Pair Channels 1 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV1EN [5/5]

#define FTM_INVCTRL_INV1EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)

INV1EN - Pair Channels 1 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV2EN [1/5]

#define FTM_INVCTRL_INV2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)

INV2EN - Pair Channels 2 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV2EN [2/5]

#define FTM_INVCTRL_INV2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)

INV2EN - Pair Channels 2 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV2EN [3/5]

#define FTM_INVCTRL_INV2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)

INV2EN - Pair Channels 2 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV2EN [4/5]

#define FTM_INVCTRL_INV2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)

INV2EN - Pair Channels 2 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV2EN [5/5]

#define FTM_INVCTRL_INV2EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)

INV2EN - Pair Channels 2 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV3EN [1/5]

#define FTM_INVCTRL_INV3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)

INV3EN - Pair Channels 3 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV3EN [2/5]

#define FTM_INVCTRL_INV3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)

INV3EN - Pair Channels 3 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV3EN [3/5]

#define FTM_INVCTRL_INV3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)

INV3EN - Pair Channels 3 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV3EN [4/5]

#define FTM_INVCTRL_INV3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)

INV3EN - Pair Channels 3 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_INVCTRL_INV3EN [5/5]

#define FTM_INVCTRL_INV3EN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)

INV3EN - Pair Channels 3 Inverting Enable 0b0..Inverting is disabled. 0b1..Inverting is enabled.

◆ FTM_IRQS

#define FTM_IRQS   { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }

Interrupt vectors for the FTM peripheral type

◆ FTM_MODE_CAPTEST [1/5]

#define FTM_MODE_CAPTEST ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)

CAPTEST - Capture Test Mode Enable 0b0..Capture test mode is disabled. 0b1..Capture test mode is enabled.

◆ FTM_MODE_CAPTEST [2/5]

#define FTM_MODE_CAPTEST ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)

CAPTEST - Capture Test Mode Enable 0b0..Capture test mode is disabled. 0b1..Capture test mode is enabled.

◆ FTM_MODE_CAPTEST [3/5]

#define FTM_MODE_CAPTEST ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)

CAPTEST - Capture Test Mode Enable 0b0..Capture test mode is disabled. 0b1..Capture test mode is enabled.

◆ FTM_MODE_CAPTEST [4/5]

#define FTM_MODE_CAPTEST ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)

CAPTEST - Capture Test Mode Enable 0b0..Capture test mode is disabled. 0b1..Capture test mode is enabled.

◆ FTM_MODE_CAPTEST [5/5]

#define FTM_MODE_CAPTEST ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)

CAPTEST - Capture Test Mode Enable 0b0..Capture test mode is disabled. 0b1..Capture test mode is enabled.

◆ FTM_MODE_FAULTIE [1/5]

#define FTM_MODE_FAULTIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)

FAULTIE - Fault Interrupt Enable 0b0..Fault control interrupt is disabled. 0b1..Fault control interrupt is enabled.

◆ FTM_MODE_FAULTIE [2/5]

#define FTM_MODE_FAULTIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)

FAULTIE - Fault Interrupt Enable 0b0..Fault control interrupt is disabled. 0b1..Fault control interrupt is enabled.

◆ FTM_MODE_FAULTIE [3/5]

#define FTM_MODE_FAULTIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)

FAULTIE - Fault Interrupt Enable 0b0..Fault control interrupt is disabled. 0b1..Fault control interrupt is enabled.

◆ FTM_MODE_FAULTIE [4/5]

#define FTM_MODE_FAULTIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)

FAULTIE - Fault Interrupt Enable 0b0..Fault control interrupt is disabled. 0b1..Fault control interrupt is enabled.

◆ FTM_MODE_FAULTIE [5/5]

#define FTM_MODE_FAULTIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)

FAULTIE - Fault Interrupt Enable 0b0..Fault control interrupt is disabled. 0b1..Fault control interrupt is enabled.

◆ FTM_MODE_FAULTM [1/6]

#define FTM_MODE_FAULTM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)

FAULTM - Fault Control Mode 0b00..Fault control is disabled for all channels. 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.

◆ FTM_MODE_FAULTM [2/6]

#define FTM_MODE_FAULTM ( x)    (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)

FAULTM - Fault Control Mode 0b00..Fault control is disabled for all channels. 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.

◆ FTM_MODE_FAULTM [3/6]

#define FTM_MODE_FAULTM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)

FAULTM - Fault Control Mode 0b00..Fault control is disabled for all channels. 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.

◆ FTM_MODE_FAULTM [4/6]

#define FTM_MODE_FAULTM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)

FAULTM - Fault Control Mode 0b00..Fault control is disabled for all channels. 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.

◆ FTM_MODE_FAULTM [5/6]

#define FTM_MODE_FAULTM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)

FAULTM - Fault Control Mode 0b00..Fault control is disabled for all channels. 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.

◆ FTM_MODE_FAULTM [6/6]

#define FTM_MODE_FAULTM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)

FAULTM - Fault Control Mode 0b00..Fault control is disabled for all channels. 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.

◆ FTM_MODE_FTMEN [1/5]

#define FTM_MODE_FTMEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)

FTMEN - FTM Enable 0b0..Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. 0b1..All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.

FTMEN - FTM Enable 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. 0b1..Free running counter and synchronization are different from TPM behavior.

◆ FTM_MODE_FTMEN [2/5]

#define FTM_MODE_FTMEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)

FTMEN - FTM Enable 0b0..Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. 0b1..All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.

FTMEN - FTM Enable 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. 0b1..Free running counter and synchronization are different from TPM behavior.

◆ FTM_MODE_FTMEN [3/5]

#define FTM_MODE_FTMEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)

FTMEN - FTM Enable 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. 0b1..Free running counter and synchronization are different from TPM behavior.

◆ FTM_MODE_FTMEN [4/5]

#define FTM_MODE_FTMEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)

FTMEN - FTM Enable 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. 0b1..Free running counter and synchronization are different from TPM behavior.

◆ FTM_MODE_FTMEN [5/5]

#define FTM_MODE_FTMEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)

FTMEN - FTM Enable 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. 0b1..Free running counter and synchronization are different from TPM behavior.

◆ FTM_MODE_PWMSYNC [1/5]

#define FTM_MODE_PWMSYNC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)

PWMSYNC - PWM Synchronization Mode 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.

◆ FTM_MODE_PWMSYNC [2/5]

#define FTM_MODE_PWMSYNC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)

PWMSYNC - PWM Synchronization Mode 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.

◆ FTM_MODE_PWMSYNC [3/5]

#define FTM_MODE_PWMSYNC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)

PWMSYNC - PWM Synchronization Mode 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.

◆ FTM_MODE_PWMSYNC [4/5]

#define FTM_MODE_PWMSYNC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)

PWMSYNC - PWM Synchronization Mode 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.

◆ FTM_MODE_PWMSYNC [5/5]

#define FTM_MODE_PWMSYNC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)

PWMSYNC - PWM Synchronization Mode 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.

◆ FTM_MODE_WPDIS [1/5]

#define FTM_MODE_WPDIS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)

WPDIS - Write Protection Disable 0b0..Write protection is enabled. 0b1..Write protection is disabled.

◆ FTM_MODE_WPDIS [2/5]

#define FTM_MODE_WPDIS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)

WPDIS - Write Protection Disable 0b0..Write protection is enabled. 0b1..Write protection is disabled.

◆ FTM_MODE_WPDIS [3/5]

#define FTM_MODE_WPDIS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)

WPDIS - Write Protection Disable 0b0..Write protection is enabled. 0b1..Write protection is disabled.

◆ FTM_MODE_WPDIS [4/5]

#define FTM_MODE_WPDIS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)

WPDIS - Write Protection Disable 0b0..Write protection is enabled. 0b1..Write protection is disabled.

◆ FTM_MODE_WPDIS [5/5]

#define FTM_MODE_WPDIS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)

WPDIS - Write Protection Disable 0b0..Write protection is enabled. 0b1..Write protection is disabled.

◆ FTM_OUTINIT_CH0OI [1/5]

#define FTM_OUTINIT_CH0OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)

CH0OI - Channel 0 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH0OI [2/5]

#define FTM_OUTINIT_CH0OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)

CH0OI - Channel 0 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH0OI [3/5]

#define FTM_OUTINIT_CH0OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)

CH0OI - Channel 0 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH0OI [4/5]

#define FTM_OUTINIT_CH0OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)

CH0OI - Channel 0 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH0OI [5/5]

#define FTM_OUTINIT_CH0OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)

CH0OI - Channel 0 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH1OI [1/5]

#define FTM_OUTINIT_CH1OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)

CH1OI - Channel 1 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH1OI [2/5]

#define FTM_OUTINIT_CH1OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)

CH1OI - Channel 1 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH1OI [3/5]

#define FTM_OUTINIT_CH1OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)

CH1OI - Channel 1 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH1OI [4/5]

#define FTM_OUTINIT_CH1OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)

CH1OI - Channel 1 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH1OI [5/5]

#define FTM_OUTINIT_CH1OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)

CH1OI - Channel 1 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH2OI [1/5]

#define FTM_OUTINIT_CH2OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)

CH2OI - Channel 2 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH2OI [2/5]

#define FTM_OUTINIT_CH2OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)

CH2OI - Channel 2 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH2OI [3/5]

#define FTM_OUTINIT_CH2OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)

CH2OI - Channel 2 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH2OI [4/5]

#define FTM_OUTINIT_CH2OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)

CH2OI - Channel 2 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH2OI [5/5]

#define FTM_OUTINIT_CH2OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)

CH2OI - Channel 2 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH3OI [1/5]

#define FTM_OUTINIT_CH3OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)

CH3OI - Channel 3 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH3OI [2/5]

#define FTM_OUTINIT_CH3OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)

CH3OI - Channel 3 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH3OI [3/5]

#define FTM_OUTINIT_CH3OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)

CH3OI - Channel 3 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH3OI [4/5]

#define FTM_OUTINIT_CH3OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)

CH3OI - Channel 3 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH3OI [5/5]

#define FTM_OUTINIT_CH3OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)

CH3OI - Channel 3 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH4OI [1/5]

#define FTM_OUTINIT_CH4OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)

CH4OI - Channel 4 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH4OI [2/5]

#define FTM_OUTINIT_CH4OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)

CH4OI - Channel 4 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH4OI [3/5]

#define FTM_OUTINIT_CH4OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)

CH4OI - Channel 4 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH4OI [4/5]

#define FTM_OUTINIT_CH4OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)

CH4OI - Channel 4 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH4OI [5/5]

#define FTM_OUTINIT_CH4OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)

CH4OI - Channel 4 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH5OI [1/5]

#define FTM_OUTINIT_CH5OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)

CH5OI - Channel 5 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH5OI [2/5]

#define FTM_OUTINIT_CH5OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)

CH5OI - Channel 5 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH5OI [3/5]

#define FTM_OUTINIT_CH5OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)

CH5OI - Channel 5 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH5OI [4/5]

#define FTM_OUTINIT_CH5OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)

CH5OI - Channel 5 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH5OI [5/5]

#define FTM_OUTINIT_CH5OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)

CH5OI - Channel 5 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH6OI [1/5]

#define FTM_OUTINIT_CH6OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)

CH6OI - Channel 6 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH6OI [2/5]

#define FTM_OUTINIT_CH6OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)

CH6OI - Channel 6 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH6OI [3/5]

#define FTM_OUTINIT_CH6OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)

CH6OI - Channel 6 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH6OI [4/5]

#define FTM_OUTINIT_CH6OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)

CH6OI - Channel 6 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH6OI [5/5]

#define FTM_OUTINIT_CH6OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)

CH6OI - Channel 6 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH7OI [1/5]

#define FTM_OUTINIT_CH7OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)

CH7OI - Channel 7 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH7OI [2/5]

#define FTM_OUTINIT_CH7OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)

CH7OI - Channel 7 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH7OI [3/5]

#define FTM_OUTINIT_CH7OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)

CH7OI - Channel 7 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH7OI [4/5]

#define FTM_OUTINIT_CH7OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)

CH7OI - Channel 7 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTINIT_CH7OI [5/5]

#define FTM_OUTINIT_CH7OI ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)

CH7OI - Channel 7 Output Initialization Value 0b0..The initialization value is 0. 0b1..The initialization value is 1.

◆ FTM_OUTMASK_CH0OM [1/5]

#define FTM_OUTMASK_CH0OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)

CH0OM - Channel 0 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH0OM [2/5]

#define FTM_OUTMASK_CH0OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)

CH0OM - Channel 0 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH0OM [3/5]

#define FTM_OUTMASK_CH0OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)

CH0OM - Channel 0 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH0OM [4/5]

#define FTM_OUTMASK_CH0OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)

CH0OM - Channel 0 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH0OM [5/5]

#define FTM_OUTMASK_CH0OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)

CH0OM - Channel 0 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH1OM [1/5]

#define FTM_OUTMASK_CH1OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)

CH1OM - Channel 1 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH1OM [2/5]

#define FTM_OUTMASK_CH1OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)

CH1OM - Channel 1 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH1OM [3/5]

#define FTM_OUTMASK_CH1OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)

CH1OM - Channel 1 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH1OM [4/5]

#define FTM_OUTMASK_CH1OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)

CH1OM - Channel 1 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH1OM [5/5]

#define FTM_OUTMASK_CH1OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)

CH1OM - Channel 1 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH2OM [1/5]

#define FTM_OUTMASK_CH2OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)

CH2OM - Channel 2 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH2OM [2/5]

#define FTM_OUTMASK_CH2OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)

CH2OM - Channel 2 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH2OM [3/5]

#define FTM_OUTMASK_CH2OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)

CH2OM - Channel 2 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH2OM [4/5]

#define FTM_OUTMASK_CH2OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)

CH2OM - Channel 2 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH2OM [5/5]

#define FTM_OUTMASK_CH2OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)

CH2OM - Channel 2 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH3OM [1/5]

#define FTM_OUTMASK_CH3OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)

CH3OM - Channel 3 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH3OM [2/5]

#define FTM_OUTMASK_CH3OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)

CH3OM - Channel 3 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH3OM [3/5]

#define FTM_OUTMASK_CH3OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)

CH3OM - Channel 3 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH3OM [4/5]

#define FTM_OUTMASK_CH3OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)

CH3OM - Channel 3 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH3OM [5/5]

#define FTM_OUTMASK_CH3OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)

CH3OM - Channel 3 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH4OM [1/5]

#define FTM_OUTMASK_CH4OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)

CH4OM - Channel 4 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH4OM [2/5]

#define FTM_OUTMASK_CH4OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)

CH4OM - Channel 4 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH4OM [3/5]

#define FTM_OUTMASK_CH4OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)

CH4OM - Channel 4 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH4OM [4/5]

#define FTM_OUTMASK_CH4OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)

CH4OM - Channel 4 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH4OM [5/5]

#define FTM_OUTMASK_CH4OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)

CH4OM - Channel 4 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH5OM [1/5]

#define FTM_OUTMASK_CH5OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)

CH5OM - Channel 5 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH5OM [2/5]

#define FTM_OUTMASK_CH5OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)

CH5OM - Channel 5 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH5OM [3/5]

#define FTM_OUTMASK_CH5OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)

CH5OM - Channel 5 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH5OM [4/5]

#define FTM_OUTMASK_CH5OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)

CH5OM - Channel 5 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH5OM [5/5]

#define FTM_OUTMASK_CH5OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)

CH5OM - Channel 5 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH6OM [1/5]

#define FTM_OUTMASK_CH6OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)

CH6OM - Channel 6 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH6OM [2/5]

#define FTM_OUTMASK_CH6OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)

CH6OM - Channel 6 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH6OM [3/5]

#define FTM_OUTMASK_CH6OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)

CH6OM - Channel 6 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH6OM [4/5]

#define FTM_OUTMASK_CH6OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)

CH6OM - Channel 6 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH6OM [5/5]

#define FTM_OUTMASK_CH6OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)

CH6OM - Channel 6 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH7OM [1/5]

#define FTM_OUTMASK_CH7OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)

CH7OM - Channel 7 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH7OM [2/5]

#define FTM_OUTMASK_CH7OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)

CH7OM - Channel 7 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH7OM [3/5]

#define FTM_OUTMASK_CH7OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)

CH7OM - Channel 7 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH7OM [4/5]

#define FTM_OUTMASK_CH7OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)

CH7OM - Channel 7 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_OUTMASK_CH7OM [5/5]

#define FTM_OUTMASK_CH7OM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)

CH7OM - Channel 7 Output Mask 0b0..Channel output is not masked. It continues to operate normally. 0b1..Channel output is masked. It is forced to its inactive state.

◆ FTM_POL_POL0 [1/5]

#define FTM_POL_POL0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)

POL0 - Channel 0 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL0 [2/5]

#define FTM_POL_POL0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)

POL0 - Channel 0 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL0 [3/5]

#define FTM_POL_POL0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)

POL0 - Channel 0 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL0 [4/5]

#define FTM_POL_POL0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)

POL0 - Channel 0 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL0 [5/5]

#define FTM_POL_POL0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)

POL0 - Channel 0 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL1 [1/5]

#define FTM_POL_POL1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)

POL1 - Channel 1 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL1 [2/5]

#define FTM_POL_POL1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)

POL1 - Channel 1 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL1 [3/5]

#define FTM_POL_POL1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)

POL1 - Channel 1 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL1 [4/5]

#define FTM_POL_POL1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)

POL1 - Channel 1 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL1 [5/5]

#define FTM_POL_POL1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)

POL1 - Channel 1 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL2 [1/5]

#define FTM_POL_POL2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)

POL2 - Channel 2 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL2 [2/5]

#define FTM_POL_POL2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)

POL2 - Channel 2 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL2 [3/5]

#define FTM_POL_POL2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)

POL2 - Channel 2 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL2 [4/5]

#define FTM_POL_POL2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)

POL2 - Channel 2 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL2 [5/5]

#define FTM_POL_POL2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)

POL2 - Channel 2 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL3 [1/5]

#define FTM_POL_POL3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)

POL3 - Channel 3 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL3 [2/5]

#define FTM_POL_POL3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)

POL3 - Channel 3 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL3 [3/5]

#define FTM_POL_POL3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)

POL3 - Channel 3 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL3 [4/5]

#define FTM_POL_POL3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)

POL3 - Channel 3 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL3 [5/5]

#define FTM_POL_POL3 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)

POL3 - Channel 3 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL4 [1/5]

#define FTM_POL_POL4 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)

POL4 - Channel 4 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL4 [2/5]

#define FTM_POL_POL4 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)

POL4 - Channel 4 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL4 [3/5]

#define FTM_POL_POL4 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)

POL4 - Channel 4 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL4 [4/5]

#define FTM_POL_POL4 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)

POL4 - Channel 4 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL4 [5/5]

#define FTM_POL_POL4 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)

POL4 - Channel 4 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL5 [1/5]

#define FTM_POL_POL5 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)

POL5 - Channel 5 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL5 [2/5]

#define FTM_POL_POL5 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)

POL5 - Channel 5 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL5 [3/5]

#define FTM_POL_POL5 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)

POL5 - Channel 5 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL5 [4/5]

#define FTM_POL_POL5 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)

POL5 - Channel 5 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL5 [5/5]

#define FTM_POL_POL5 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)

POL5 - Channel 5 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL6 [1/5]

#define FTM_POL_POL6 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)

POL6 - Channel 6 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL6 [2/5]

#define FTM_POL_POL6 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)

POL6 - Channel 6 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL6 [3/5]

#define FTM_POL_POL6 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)

POL6 - Channel 6 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL6 [4/5]

#define FTM_POL_POL6 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)

POL6 - Channel 6 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL6 [5/5]

#define FTM_POL_POL6 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)

POL6 - Channel 6 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL7 [1/5]

#define FTM_POL_POL7 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)

POL7 - Channel 7 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL7 [2/5]

#define FTM_POL_POL7 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)

POL7 - Channel 7 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL7 [3/5]

#define FTM_POL_POL7 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)

POL7 - Channel 7 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL7 [4/5]

#define FTM_POL_POL7 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)

POL7 - Channel 7 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_POL_POL7 [5/5]

#define FTM_POL_POL7 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)

POL7 - Channel 7 Polarity 0b0..The channel polarity is active high. 0b1..The channel polarity is active low.

◆ FTM_PWMLOAD_CH0SEL [1/5]

#define FTM_PWMLOAD_CH0SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)

CH0SEL - Channel 0 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH0SEL [2/5]

#define FTM_PWMLOAD_CH0SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)

CH0SEL - Channel 0 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH0SEL [3/5]

#define FTM_PWMLOAD_CH0SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)

CH0SEL - Channel 0 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH0SEL [4/5]

#define FTM_PWMLOAD_CH0SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)

CH0SEL - Channel 0 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH0SEL [5/5]

#define FTM_PWMLOAD_CH0SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)

CH0SEL - Channel 0 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH1SEL [1/5]

#define FTM_PWMLOAD_CH1SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)

CH1SEL - Channel 1 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH1SEL [2/5]

#define FTM_PWMLOAD_CH1SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)

CH1SEL - Channel 1 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH1SEL [3/5]

#define FTM_PWMLOAD_CH1SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)

CH1SEL - Channel 1 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH1SEL [4/5]

#define FTM_PWMLOAD_CH1SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)

CH1SEL - Channel 1 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH1SEL [5/5]

#define FTM_PWMLOAD_CH1SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)

CH1SEL - Channel 1 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH2SEL [1/5]

#define FTM_PWMLOAD_CH2SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)

CH2SEL - Channel 2 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH2SEL [2/5]

#define FTM_PWMLOAD_CH2SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)

CH2SEL - Channel 2 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH2SEL [3/5]

#define FTM_PWMLOAD_CH2SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)

CH2SEL - Channel 2 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH2SEL [4/5]

#define FTM_PWMLOAD_CH2SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)

CH2SEL - Channel 2 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH2SEL [5/5]

#define FTM_PWMLOAD_CH2SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)

CH2SEL - Channel 2 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH3SEL [1/5]

#define FTM_PWMLOAD_CH3SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)

CH3SEL - Channel 3 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH3SEL [2/5]

#define FTM_PWMLOAD_CH3SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)

CH3SEL - Channel 3 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH3SEL [3/5]

#define FTM_PWMLOAD_CH3SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)

CH3SEL - Channel 3 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH3SEL [4/5]

#define FTM_PWMLOAD_CH3SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)

CH3SEL - Channel 3 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH3SEL [5/5]

#define FTM_PWMLOAD_CH3SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)

CH3SEL - Channel 3 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH4SEL [1/5]

#define FTM_PWMLOAD_CH4SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)

CH4SEL - Channel 4 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH4SEL [2/5]

#define FTM_PWMLOAD_CH4SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)

CH4SEL - Channel 4 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH4SEL [3/5]

#define FTM_PWMLOAD_CH4SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)

CH4SEL - Channel 4 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH4SEL [4/5]

#define FTM_PWMLOAD_CH4SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)

CH4SEL - Channel 4 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH4SEL [5/5]

#define FTM_PWMLOAD_CH4SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)

CH4SEL - Channel 4 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH5SEL [1/5]

#define FTM_PWMLOAD_CH5SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)

CH5SEL - Channel 5 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH5SEL [2/5]

#define FTM_PWMLOAD_CH5SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)

CH5SEL - Channel 5 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH5SEL [3/5]

#define FTM_PWMLOAD_CH5SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)

CH5SEL - Channel 5 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH5SEL [4/5]

#define FTM_PWMLOAD_CH5SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)

CH5SEL - Channel 5 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH5SEL [5/5]

#define FTM_PWMLOAD_CH5SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)

CH5SEL - Channel 5 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH6SEL [1/5]

#define FTM_PWMLOAD_CH6SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)

CH6SEL - Channel 6 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH6SEL [2/5]

#define FTM_PWMLOAD_CH6SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)

CH6SEL - Channel 6 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH6SEL [3/5]

#define FTM_PWMLOAD_CH6SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)

CH6SEL - Channel 6 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH6SEL [4/5]

#define FTM_PWMLOAD_CH6SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)

CH6SEL - Channel 6 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH6SEL [5/5]

#define FTM_PWMLOAD_CH6SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)

CH6SEL - Channel 6 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH7SEL [1/5]

#define FTM_PWMLOAD_CH7SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)

CH7SEL - Channel 7 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH7SEL [2/5]

#define FTM_PWMLOAD_CH7SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)

CH7SEL - Channel 7 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH7SEL [3/5]

#define FTM_PWMLOAD_CH7SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)

CH7SEL - Channel 7 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH7SEL [4/5]

#define FTM_PWMLOAD_CH7SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)

CH7SEL - Channel 7 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_CH7SEL [5/5]

#define FTM_PWMLOAD_CH7SEL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)

CH7SEL - Channel 7 Select 0b0..Do not include the channel in the matching process. 0b1..Include the channel in the matching process.

◆ FTM_PWMLOAD_LDOK [1/5]

#define FTM_PWMLOAD_LDOK ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)

LDOK - Load Enable 0b0..Loading updated values is disabled. 0b1..Loading updated values is enabled.

◆ FTM_PWMLOAD_LDOK [2/5]

#define FTM_PWMLOAD_LDOK ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)

LDOK - Load Enable 0b0..Loading updated values is disabled. 0b1..Loading updated values is enabled.

◆ FTM_PWMLOAD_LDOK [3/5]

#define FTM_PWMLOAD_LDOK ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)

LDOK - Load Enable 0b0..Loading updated values is disabled. 0b1..Loading updated values is enabled.

◆ FTM_PWMLOAD_LDOK [4/5]

#define FTM_PWMLOAD_LDOK ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)

LDOK - Load Enable 0b0..Loading updated values is disabled. 0b1..Loading updated values is enabled.

◆ FTM_PWMLOAD_LDOK [5/5]

#define FTM_PWMLOAD_LDOK ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)

LDOK - Load Enable 0b0..Loading updated values is disabled. 0b1..Loading updated values is enabled.

◆ FTM_QDCTRL_PHAFLTREN [1/5]

#define FTM_QDCTRL_PHAFLTREN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)

PHAFLTREN - Phase A Input Filter Enable 0b0..Phase A input filter is disabled. 0b1..Phase A input filter is enabled.

◆ FTM_QDCTRL_PHAFLTREN [2/5]

#define FTM_QDCTRL_PHAFLTREN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)

PHAFLTREN - Phase A Input Filter Enable 0b0..Phase A input filter is disabled. 0b1..Phase A input filter is enabled.

◆ FTM_QDCTRL_PHAFLTREN [3/5]

#define FTM_QDCTRL_PHAFLTREN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)

PHAFLTREN - Phase A Input Filter Enable 0b0..Phase A input filter is disabled. 0b1..Phase A input filter is enabled.

◆ FTM_QDCTRL_PHAFLTREN [4/5]

#define FTM_QDCTRL_PHAFLTREN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)

PHAFLTREN - Phase A Input Filter Enable 0b0..Phase A input filter is disabled. 0b1..Phase A input filter is enabled.

◆ FTM_QDCTRL_PHAFLTREN [5/5]

#define FTM_QDCTRL_PHAFLTREN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)

PHAFLTREN - Phase A Input Filter Enable 0b0..Phase A input filter is disabled. 0b1..Phase A input filter is enabled.

◆ FTM_QDCTRL_PHAPOL [1/5]

#define FTM_QDCTRL_PHAPOL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)

PHAPOL - Phase A Input Polarity 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.

◆ FTM_QDCTRL_PHAPOL [2/5]

#define FTM_QDCTRL_PHAPOL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)

PHAPOL - Phase A Input Polarity 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.

◆ FTM_QDCTRL_PHAPOL [3/5]

#define FTM_QDCTRL_PHAPOL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)

PHAPOL - Phase A Input Polarity 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.

◆ FTM_QDCTRL_PHAPOL [4/5]

#define FTM_QDCTRL_PHAPOL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)

PHAPOL - Phase A Input Polarity 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.

◆ FTM_QDCTRL_PHAPOL [5/5]

#define FTM_QDCTRL_PHAPOL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)

PHAPOL - Phase A Input Polarity 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.

◆ FTM_QDCTRL_PHBFLTREN [1/5]

#define FTM_QDCTRL_PHBFLTREN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)

PHBFLTREN - Phase B Input Filter Enable 0b0..Phase B input filter is disabled. 0b1..Phase B input filter is enabled.

◆ FTM_QDCTRL_PHBFLTREN [2/5]

#define FTM_QDCTRL_PHBFLTREN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)

PHBFLTREN - Phase B Input Filter Enable 0b0..Phase B input filter is disabled. 0b1..Phase B input filter is enabled.

◆ FTM_QDCTRL_PHBFLTREN [3/5]

#define FTM_QDCTRL_PHBFLTREN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)

PHBFLTREN - Phase B Input Filter Enable 0b0..Phase B input filter is disabled. 0b1..Phase B input filter is enabled.

◆ FTM_QDCTRL_PHBFLTREN [4/5]

#define FTM_QDCTRL_PHBFLTREN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)

PHBFLTREN - Phase B Input Filter Enable 0b0..Phase B input filter is disabled. 0b1..Phase B input filter is enabled.

◆ FTM_QDCTRL_PHBFLTREN [5/5]

#define FTM_QDCTRL_PHBFLTREN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)

PHBFLTREN - Phase B Input Filter Enable 0b0..Phase B input filter is disabled. 0b1..Phase B input filter is enabled.

◆ FTM_QDCTRL_PHBPOL [1/5]

#define FTM_QDCTRL_PHBPOL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)

PHBPOL - Phase B Input Polarity 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.

◆ FTM_QDCTRL_PHBPOL [2/5]

#define FTM_QDCTRL_PHBPOL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)

PHBPOL - Phase B Input Polarity 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.

◆ FTM_QDCTRL_PHBPOL [3/5]

#define FTM_QDCTRL_PHBPOL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)

PHBPOL - Phase B Input Polarity 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.

◆ FTM_QDCTRL_PHBPOL [4/5]

#define FTM_QDCTRL_PHBPOL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)

PHBPOL - Phase B Input Polarity 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.

◆ FTM_QDCTRL_PHBPOL [5/5]

#define FTM_QDCTRL_PHBPOL ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)

PHBPOL - Phase B Input Polarity 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.

◆ FTM_QDCTRL_QUADEN [1/5]

#define FTM_QDCTRL_QUADEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)

QUADEN - Quadrature Decoder Mode Enable 0b0..Quadrature Decoder mode is disabled. 0b1..Quadrature Decoder mode is enabled.

◆ FTM_QDCTRL_QUADEN [2/5]

#define FTM_QDCTRL_QUADEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)

QUADEN - Quadrature Decoder Mode Enable 0b0..Quadrature Decoder mode is disabled. 0b1..Quadrature Decoder mode is enabled.

◆ FTM_QDCTRL_QUADEN [3/5]

#define FTM_QDCTRL_QUADEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)

QUADEN - Quadrature Decoder Mode Enable 0b0..Quadrature Decoder mode is disabled. 0b1..Quadrature Decoder mode is enabled.

◆ FTM_QDCTRL_QUADEN [4/5]

#define FTM_QDCTRL_QUADEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)

QUADEN - Quadrature Decoder Mode Enable 0b0..Quadrature Decoder mode is disabled. 0b1..Quadrature Decoder mode is enabled.

◆ FTM_QDCTRL_QUADEN [5/5]

#define FTM_QDCTRL_QUADEN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)

QUADEN - Quadrature Decoder Mode Enable 0b0..Quadrature Decoder mode is disabled. 0b1..Quadrature Decoder mode is enabled.

◆ FTM_QDCTRL_QUADIR [1/5]

#define FTM_QDCTRL_QUADIR ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)

QUADIR - FTM Counter Direction In Quadrature Decoder Mode 0b0..Counting direction is decreasing (FTM counter decrement). 0b1..Counting direction is increasing (FTM counter increment).

◆ FTM_QDCTRL_QUADIR [2/5]

#define FTM_QDCTRL_QUADIR ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)

QUADIR - FTM Counter Direction In Quadrature Decoder Mode 0b0..Counting direction is decreasing (FTM counter decrement). 0b1..Counting direction is increasing (FTM counter increment).

◆ FTM_QDCTRL_QUADIR [3/5]

#define FTM_QDCTRL_QUADIR ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)

QUADIR - FTM Counter Direction In Quadrature Decoder Mode 0b0..Counting direction is decreasing (FTM counter decrement). 0b1..Counting direction is increasing (FTM counter increment).

◆ FTM_QDCTRL_QUADIR [4/5]

#define FTM_QDCTRL_QUADIR ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)

QUADIR - FTM Counter Direction In Quadrature Decoder Mode 0b0..Counting direction is decreasing (FTM counter decrement). 0b1..Counting direction is increasing (FTM counter increment).

◆ FTM_QDCTRL_QUADIR [5/5]

#define FTM_QDCTRL_QUADIR ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)

QUADIR - FTM Counter Direction In Quadrature Decoder Mode 0b0..Counting direction is decreasing (FTM counter decrement). 0b1..Counting direction is increasing (FTM counter increment).

◆ FTM_QDCTRL_QUADMODE [1/5]

#define FTM_QDCTRL_QUADMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)

QUADMODE - Quadrature Decoder Mode 0b0..Phase A and phase B encoding mode. 0b1..Count and direction encoding mode.

◆ FTM_QDCTRL_QUADMODE [2/5]

#define FTM_QDCTRL_QUADMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)

QUADMODE - Quadrature Decoder Mode 0b0..Phase A and phase B encoding mode. 0b1..Count and direction encoding mode.

◆ FTM_QDCTRL_QUADMODE [3/5]

#define FTM_QDCTRL_QUADMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)

QUADMODE - Quadrature Decoder Mode 0b0..Phase A and phase B encoding mode. 0b1..Count and direction encoding mode.

◆ FTM_QDCTRL_QUADMODE [4/5]

#define FTM_QDCTRL_QUADMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)

QUADMODE - Quadrature Decoder Mode 0b0..Phase A and phase B encoding mode. 0b1..Count and direction encoding mode.

◆ FTM_QDCTRL_QUADMODE [5/5]

#define FTM_QDCTRL_QUADMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)

QUADMODE - Quadrature Decoder Mode 0b0..Phase A and phase B encoding mode. 0b1..Count and direction encoding mode.

◆ FTM_QDCTRL_TOFDIR [1/5]

#define FTM_QDCTRL_TOFDIR ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)

TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).

◆ FTM_QDCTRL_TOFDIR [2/5]

#define FTM_QDCTRL_TOFDIR ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)

TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).

◆ FTM_QDCTRL_TOFDIR [3/5]

#define FTM_QDCTRL_TOFDIR ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)

TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).

◆ FTM_QDCTRL_TOFDIR [4/5]

#define FTM_QDCTRL_TOFDIR ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)

TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).

◆ FTM_QDCTRL_TOFDIR [5/5]

#define FTM_QDCTRL_TOFDIR ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)

TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).

◆ FTM_SC_CLKS [1/6]

#define FTM_SC_CLKS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)

CLKS - Clock Source Selection 0b00..No clock selected. This in effect disables the FTM counter. 0b01..System clock 0b10..Fixed frequency clock 0b11..External clock

◆ FTM_SC_CLKS [2/6]

#define FTM_SC_CLKS ( x)    (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)

CLKS - Clock Source Selection 0b00..No clock selected. This in effect disables the FTM counter. 0b01..System clock 0b10..Fixed frequency clock 0b11..External clock

◆ FTM_SC_CLKS [3/6]

#define FTM_SC_CLKS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)

CLKS - Clock Source Selection 0b00..No clock selected. This in effect disables the FTM counter. 0b01..System clock 0b10..Fixed frequency clock 0b11..External clock

◆ FTM_SC_CLKS [4/6]

#define FTM_SC_CLKS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)

CLKS - Clock Source Selection 0b00..No clock selected. This in effect disables the FTM counter. 0b01..System clock 0b10..Fixed frequency clock 0b11..External clock

◆ FTM_SC_CLKS [5/6]

#define FTM_SC_CLKS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)

CLKS - Clock Source Selection 0b00..No clock selected. This in effect disables the FTM counter. 0b01..System clock 0b10..Fixed frequency clock 0b11..External clock

◆ FTM_SC_CLKS [6/6]

#define FTM_SC_CLKS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)

CLKS - Clock Source Selection 0b00..No clock selected. This in effect disables the FTM counter. 0b01..System clock 0b10..Fixed frequency clock 0b11..External clock

◆ FTM_SC_CPWMS [1/5]

#define FTM_SC_CPWMS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)

CPWMS - Center-Aligned PWM Select 0b0..FTM counter operates in Up Counting mode. 0b1..FTM counter operates in Up-Down Counting mode.

◆ FTM_SC_CPWMS [2/5]

#define FTM_SC_CPWMS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)

CPWMS - Center-Aligned PWM Select 0b0..FTM counter operates in Up Counting mode. 0b1..FTM counter operates in Up-Down Counting mode.

◆ FTM_SC_CPWMS [3/5]

#define FTM_SC_CPWMS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)

CPWMS - Center-Aligned PWM Select 0b0..FTM counter operates in Up Counting mode. 0b1..FTM counter operates in Up-Down Counting mode.

◆ FTM_SC_CPWMS [4/5]

#define FTM_SC_CPWMS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)

CPWMS - Center-Aligned PWM Select 0b0..FTM counter operates in Up Counting mode. 0b1..FTM counter operates in Up-Down Counting mode.

◆ FTM_SC_CPWMS [5/5]

#define FTM_SC_CPWMS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)

CPWMS - Center-Aligned PWM Select 0b0..FTM counter operates in Up Counting mode. 0b1..FTM counter operates in Up-Down Counting mode.

◆ FTM_SC_PS [1/6]

#define FTM_SC_PS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)

PS - Prescale Factor Selection 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ FTM_SC_PS [2/6]

#define FTM_SC_PS ( x)    (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)

PS - Prescale Factor Selection 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ FTM_SC_PS [3/6]

#define FTM_SC_PS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)

PS - Prescale Factor Selection 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ FTM_SC_PS [4/6]

#define FTM_SC_PS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)

PS - Prescale Factor Selection 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ FTM_SC_PS [5/6]

#define FTM_SC_PS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)

PS - Prescale Factor Selection 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ FTM_SC_PS [6/6]

#define FTM_SC_PS ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)

PS - Prescale Factor Selection 0b000..Divide by 1 0b001..Divide by 2 0b010..Divide by 4 0b011..Divide by 8 0b100..Divide by 16 0b101..Divide by 32 0b110..Divide by 64 0b111..Divide by 128

◆ FTM_SC_TOF [1/5]

#define FTM_SC_TOF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)

TOF - Timer Overflow Flag 0b0..FTM counter has not overflowed. 0b1..FTM counter has overflowed.

◆ FTM_SC_TOF [2/5]

#define FTM_SC_TOF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)

TOF - Timer Overflow Flag 0b0..FTM counter has not overflowed. 0b1..FTM counter has overflowed.

◆ FTM_SC_TOF [3/5]

#define FTM_SC_TOF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)

TOF - Timer Overflow Flag 0b0..FTM counter has not overflowed. 0b1..FTM counter has overflowed.

◆ FTM_SC_TOF [4/5]

#define FTM_SC_TOF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)

TOF - Timer Overflow Flag 0b0..FTM counter has not overflowed. 0b1..FTM counter has overflowed.

◆ FTM_SC_TOF [5/5]

#define FTM_SC_TOF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)

TOF - Timer Overflow Flag 0b0..FTM counter has not overflowed. 0b1..FTM counter has overflowed.

◆ FTM_SC_TOIE [1/5]

#define FTM_SC_TOIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)

TOIE - Timer Overflow Interrupt Enable 0b0..Disable TOF interrupts. Use software polling. 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.

◆ FTM_SC_TOIE [2/5]

#define FTM_SC_TOIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)

TOIE - Timer Overflow Interrupt Enable 0b0..Disable TOF interrupts. Use software polling. 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.

◆ FTM_SC_TOIE [3/5]

#define FTM_SC_TOIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)

TOIE - Timer Overflow Interrupt Enable 0b0..Disable TOF interrupts. Use software polling. 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.

◆ FTM_SC_TOIE [4/5]

#define FTM_SC_TOIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)

TOIE - Timer Overflow Interrupt Enable 0b0..Disable TOF interrupts. Use software polling. 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.

◆ FTM_SC_TOIE [5/5]

#define FTM_SC_TOIE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)

TOIE - Timer Overflow Interrupt Enable 0b0..Disable TOF interrupts. Use software polling. 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.

◆ FTM_STATUS_CH0F [1/5]

#define FTM_STATUS_CH0F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)

CH0F - Channel 0 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH0F [2/5]

#define FTM_STATUS_CH0F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)

CH0F - Channel 0 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH0F [3/5]

#define FTM_STATUS_CH0F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)

CH0F - Channel 0 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH0F [4/5]

#define FTM_STATUS_CH0F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)

CH0F - Channel 0 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH0F [5/5]

#define FTM_STATUS_CH0F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)

CH0F - Channel 0 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH1F [1/5]

#define FTM_STATUS_CH1F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)

CH1F - Channel 1 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH1F [2/5]

#define FTM_STATUS_CH1F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)

CH1F - Channel 1 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH1F [3/5]

#define FTM_STATUS_CH1F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)

CH1F - Channel 1 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH1F [4/5]

#define FTM_STATUS_CH1F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)

CH1F - Channel 1 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH1F [5/5]

#define FTM_STATUS_CH1F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)

CH1F - Channel 1 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH2F [1/5]

#define FTM_STATUS_CH2F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)

CH2F - Channel 2 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH2F [2/5]

#define FTM_STATUS_CH2F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)

CH2F - Channel 2 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH2F [3/5]

#define FTM_STATUS_CH2F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)

CH2F - Channel 2 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH2F [4/5]

#define FTM_STATUS_CH2F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)

CH2F - Channel 2 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH2F [5/5]

#define FTM_STATUS_CH2F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)

CH2F - Channel 2 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH3F [1/5]

#define FTM_STATUS_CH3F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)

CH3F - Channel 3 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH3F [2/5]

#define FTM_STATUS_CH3F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)

CH3F - Channel 3 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH3F [3/5]

#define FTM_STATUS_CH3F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)

CH3F - Channel 3 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH3F [4/5]

#define FTM_STATUS_CH3F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)

CH3F - Channel 3 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH3F [5/5]

#define FTM_STATUS_CH3F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)

CH3F - Channel 3 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH4F [1/5]

#define FTM_STATUS_CH4F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)

CH4F - Channel 4 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH4F [2/5]

#define FTM_STATUS_CH4F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)

CH4F - Channel 4 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH4F [3/5]

#define FTM_STATUS_CH4F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)

CH4F - Channel 4 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH4F [4/5]

#define FTM_STATUS_CH4F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)

CH4F - Channel 4 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH4F [5/5]

#define FTM_STATUS_CH4F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)

CH4F - Channel 4 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH5F [1/5]

#define FTM_STATUS_CH5F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)

CH5F - Channel 5 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH5F [2/5]

#define FTM_STATUS_CH5F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)

CH5F - Channel 5 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH5F [3/5]

#define FTM_STATUS_CH5F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)

CH5F - Channel 5 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH5F [4/5]

#define FTM_STATUS_CH5F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)

CH5F - Channel 5 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH5F [5/5]

#define FTM_STATUS_CH5F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)

CH5F - Channel 5 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH6F [1/5]

#define FTM_STATUS_CH6F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)

CH6F - Channel 6 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH6F [2/5]

#define FTM_STATUS_CH6F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)

CH6F - Channel 6 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH6F [3/5]

#define FTM_STATUS_CH6F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)

CH6F - Channel 6 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH6F [4/5]

#define FTM_STATUS_CH6F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)

CH6F - Channel 6 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH6F [5/5]

#define FTM_STATUS_CH6F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)

CH6F - Channel 6 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH7F [1/5]

#define FTM_STATUS_CH7F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)

CH7F - Channel 7 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH7F [2/5]

#define FTM_STATUS_CH7F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)

CH7F - Channel 7 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH7F [3/5]

#define FTM_STATUS_CH7F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)

CH7F - Channel 7 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH7F [4/5]

#define FTM_STATUS_CH7F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)

CH7F - Channel 7 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_STATUS_CH7F [5/5]

#define FTM_STATUS_CH7F ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)

CH7F - Channel 7 Flag 0b0..No channel event has occurred. 0b1..A channel event has occurred.

◆ FTM_SWOCTRL_CH0OC [1/5]

#define FTM_SWOCTRL_CH0OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)

CH0OC - Channel 0 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH0OC [2/5]

#define FTM_SWOCTRL_CH0OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)

CH0OC - Channel 0 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH0OC [3/5]

#define FTM_SWOCTRL_CH0OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)

CH0OC - Channel 0 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH0OC [4/5]

#define FTM_SWOCTRL_CH0OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)

CH0OC - Channel 0 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH0OC [5/5]

#define FTM_SWOCTRL_CH0OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)

CH0OC - Channel 0 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH0OCV [1/5]

#define FTM_SWOCTRL_CH0OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)

CH0OCV - Channel 0 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH0OCV [2/5]

#define FTM_SWOCTRL_CH0OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)

CH0OCV - Channel 0 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH0OCV [3/5]

#define FTM_SWOCTRL_CH0OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)

CH0OCV - Channel 0 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH0OCV [4/5]

#define FTM_SWOCTRL_CH0OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)

CH0OCV - Channel 0 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH0OCV [5/5]

#define FTM_SWOCTRL_CH0OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)

CH0OCV - Channel 0 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH1OC [1/5]

#define FTM_SWOCTRL_CH1OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)

CH1OC - Channel 1 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH1OC [2/5]

#define FTM_SWOCTRL_CH1OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)

CH1OC - Channel 1 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH1OC [3/5]

#define FTM_SWOCTRL_CH1OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)

CH1OC - Channel 1 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH1OC [4/5]

#define FTM_SWOCTRL_CH1OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)

CH1OC - Channel 1 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH1OC [5/5]

#define FTM_SWOCTRL_CH1OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)

CH1OC - Channel 1 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH1OCV [1/5]

#define FTM_SWOCTRL_CH1OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)

CH1OCV - Channel 1 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH1OCV [2/5]

#define FTM_SWOCTRL_CH1OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)

CH1OCV - Channel 1 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH1OCV [3/5]

#define FTM_SWOCTRL_CH1OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)

CH1OCV - Channel 1 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH1OCV [4/5]

#define FTM_SWOCTRL_CH1OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)

CH1OCV - Channel 1 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH1OCV [5/5]

#define FTM_SWOCTRL_CH1OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)

CH1OCV - Channel 1 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH2OC [1/5]

#define FTM_SWOCTRL_CH2OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)

CH2OC - Channel 2 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH2OC [2/5]

#define FTM_SWOCTRL_CH2OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)

CH2OC - Channel 2 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH2OC [3/5]

#define FTM_SWOCTRL_CH2OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)

CH2OC - Channel 2 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH2OC [4/5]

#define FTM_SWOCTRL_CH2OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)

CH2OC - Channel 2 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH2OC [5/5]

#define FTM_SWOCTRL_CH2OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)

CH2OC - Channel 2 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH2OCV [1/5]

#define FTM_SWOCTRL_CH2OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)

CH2OCV - Channel 2 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH2OCV [2/5]

#define FTM_SWOCTRL_CH2OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)

CH2OCV - Channel 2 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH2OCV [3/5]

#define FTM_SWOCTRL_CH2OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)

CH2OCV - Channel 2 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH2OCV [4/5]

#define FTM_SWOCTRL_CH2OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)

CH2OCV - Channel 2 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH2OCV [5/5]

#define FTM_SWOCTRL_CH2OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)

CH2OCV - Channel 2 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH3OC [1/5]

#define FTM_SWOCTRL_CH3OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)

CH3OC - Channel 3 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH3OC [2/5]

#define FTM_SWOCTRL_CH3OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)

CH3OC - Channel 3 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH3OC [3/5]

#define FTM_SWOCTRL_CH3OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)

CH3OC - Channel 3 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH3OC [4/5]

#define FTM_SWOCTRL_CH3OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)

CH3OC - Channel 3 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH3OC [5/5]

#define FTM_SWOCTRL_CH3OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)

CH3OC - Channel 3 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH3OCV [1/5]

#define FTM_SWOCTRL_CH3OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)

CH3OCV - Channel 3 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH3OCV [2/5]

#define FTM_SWOCTRL_CH3OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)

CH3OCV - Channel 3 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH3OCV [3/5]

#define FTM_SWOCTRL_CH3OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)

CH3OCV - Channel 3 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH3OCV [4/5]

#define FTM_SWOCTRL_CH3OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)

CH3OCV - Channel 3 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH3OCV [5/5]

#define FTM_SWOCTRL_CH3OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)

CH3OCV - Channel 3 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH4OC [1/5]

#define FTM_SWOCTRL_CH4OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)

CH4OC - Channel 4 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH4OC [2/5]

#define FTM_SWOCTRL_CH4OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)

CH4OC - Channel 4 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH4OC [3/5]

#define FTM_SWOCTRL_CH4OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)

CH4OC - Channel 4 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH4OC [4/5]

#define FTM_SWOCTRL_CH4OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)

CH4OC - Channel 4 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH4OC [5/5]

#define FTM_SWOCTRL_CH4OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)

CH4OC - Channel 4 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH4OCV [1/5]

#define FTM_SWOCTRL_CH4OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)

CH4OCV - Channel 4 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH4OCV [2/5]

#define FTM_SWOCTRL_CH4OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)

CH4OCV - Channel 4 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH4OCV [3/5]

#define FTM_SWOCTRL_CH4OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)

CH4OCV - Channel 4 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH4OCV [4/5]

#define FTM_SWOCTRL_CH4OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)

CH4OCV - Channel 4 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH4OCV [5/5]

#define FTM_SWOCTRL_CH4OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)

CH4OCV - Channel 4 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH5OC [1/5]

#define FTM_SWOCTRL_CH5OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)

CH5OC - Channel 5 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH5OC [2/5]

#define FTM_SWOCTRL_CH5OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)

CH5OC - Channel 5 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH5OC [3/5]

#define FTM_SWOCTRL_CH5OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)

CH5OC - Channel 5 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH5OC [4/5]

#define FTM_SWOCTRL_CH5OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)

CH5OC - Channel 5 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH5OC [5/5]

#define FTM_SWOCTRL_CH5OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)

CH5OC - Channel 5 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH5OCV [1/5]

#define FTM_SWOCTRL_CH5OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)

CH5OCV - Channel 5 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH5OCV [2/5]

#define FTM_SWOCTRL_CH5OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)

CH5OCV - Channel 5 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH5OCV [3/5]

#define FTM_SWOCTRL_CH5OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)

CH5OCV - Channel 5 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH5OCV [4/5]

#define FTM_SWOCTRL_CH5OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)

CH5OCV - Channel 5 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH5OCV [5/5]

#define FTM_SWOCTRL_CH5OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)

CH5OCV - Channel 5 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH6OC [1/5]

#define FTM_SWOCTRL_CH6OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)

CH6OC - Channel 6 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH6OC [2/5]

#define FTM_SWOCTRL_CH6OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)

CH6OC - Channel 6 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH6OC [3/5]

#define FTM_SWOCTRL_CH6OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)

CH6OC - Channel 6 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH6OC [4/5]

#define FTM_SWOCTRL_CH6OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)

CH6OC - Channel 6 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH6OC [5/5]

#define FTM_SWOCTRL_CH6OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)

CH6OC - Channel 6 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH6OCV [1/5]

#define FTM_SWOCTRL_CH6OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)

CH6OCV - Channel 6 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH6OCV [2/5]

#define FTM_SWOCTRL_CH6OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)

CH6OCV - Channel 6 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH6OCV [3/5]

#define FTM_SWOCTRL_CH6OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)

CH6OCV - Channel 6 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH6OCV [4/5]

#define FTM_SWOCTRL_CH6OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)

CH6OCV - Channel 6 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH6OCV [5/5]

#define FTM_SWOCTRL_CH6OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)

CH6OCV - Channel 6 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH7OC [1/5]

#define FTM_SWOCTRL_CH7OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)

CH7OC - Channel 7 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH7OC [2/5]

#define FTM_SWOCTRL_CH7OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)

CH7OC - Channel 7 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH7OC [3/5]

#define FTM_SWOCTRL_CH7OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)

CH7OC - Channel 7 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH7OC [4/5]

#define FTM_SWOCTRL_CH7OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)

CH7OC - Channel 7 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH7OC [5/5]

#define FTM_SWOCTRL_CH7OC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)

CH7OC - Channel 7 Software Output Control Enable 0b0..The channel output is not affected by software output control. 0b1..The channel output is affected by software output control.

◆ FTM_SWOCTRL_CH7OCV [1/5]

#define FTM_SWOCTRL_CH7OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)

CH7OCV - Channel 7 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH7OCV [2/5]

#define FTM_SWOCTRL_CH7OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)

CH7OCV - Channel 7 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH7OCV [3/5]

#define FTM_SWOCTRL_CH7OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)

CH7OCV - Channel 7 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH7OCV [4/5]

#define FTM_SWOCTRL_CH7OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)

CH7OCV - Channel 7 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SWOCTRL_CH7OCV [5/5]

#define FTM_SWOCTRL_CH7OCV ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)

CH7OCV - Channel 7 Software Output Control Value 0b0..The software output control forces 0 to the channel output. 0b1..The software output control forces 1 to the channel output.

◆ FTM_SYNC_CNTMAX [1/5]

#define FTM_SYNC_CNTMAX ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)

CNTMAX - Maximum Loading Point Enable 0b0..The maximum loading point is disabled. 0b1..The maximum loading point is enabled.

◆ FTM_SYNC_CNTMAX [2/5]

#define FTM_SYNC_CNTMAX ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)

CNTMAX - Maximum Loading Point Enable 0b0..The maximum loading point is disabled. 0b1..The maximum loading point is enabled.

◆ FTM_SYNC_CNTMAX [3/5]

#define FTM_SYNC_CNTMAX ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)

CNTMAX - Maximum Loading Point Enable 0b0..The maximum loading point is disabled. 0b1..The maximum loading point is enabled.

◆ FTM_SYNC_CNTMAX [4/5]

#define FTM_SYNC_CNTMAX ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)

CNTMAX - Maximum Loading Point Enable 0b0..The maximum loading point is disabled. 0b1..The maximum loading point is enabled.

◆ FTM_SYNC_CNTMAX [5/5]

#define FTM_SYNC_CNTMAX ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)

CNTMAX - Maximum Loading Point Enable 0b0..The maximum loading point is disabled. 0b1..The maximum loading point is enabled.

◆ FTM_SYNC_CNTMIN [1/5]

#define FTM_SYNC_CNTMIN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)

CNTMIN - Minimum Loading Point Enable 0b0..The minimum loading point is disabled. 0b1..The minimum loading point is enabled.

◆ FTM_SYNC_CNTMIN [2/5]

#define FTM_SYNC_CNTMIN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)

CNTMIN - Minimum Loading Point Enable 0b0..The minimum loading point is disabled. 0b1..The minimum loading point is enabled.

◆ FTM_SYNC_CNTMIN [3/5]

#define FTM_SYNC_CNTMIN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)

CNTMIN - Minimum Loading Point Enable 0b0..The minimum loading point is disabled. 0b1..The minimum loading point is enabled.

◆ FTM_SYNC_CNTMIN [4/5]

#define FTM_SYNC_CNTMIN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)

CNTMIN - Minimum Loading Point Enable 0b0..The minimum loading point is disabled. 0b1..The minimum loading point is enabled.

◆ FTM_SYNC_CNTMIN [5/5]

#define FTM_SYNC_CNTMIN ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)

CNTMIN - Minimum Loading Point Enable 0b0..The minimum loading point is disabled. 0b1..The minimum loading point is enabled.

◆ FTM_SYNC_REINIT [1/5]

#define FTM_SYNC_REINIT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)

REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 0b0..FTM counter continues to count normally. 0b1..FTM counter is updated with its initial value when the selected trigger is detected.

◆ FTM_SYNC_REINIT [2/5]

#define FTM_SYNC_REINIT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)

REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 0b0..FTM counter continues to count normally. 0b1..FTM counter is updated with its initial value when the selected trigger is detected.

◆ FTM_SYNC_REINIT [3/5]

#define FTM_SYNC_REINIT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)

REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 0b0..FTM counter continues to count normally. 0b1..FTM counter is updated with its initial value when the selected trigger is detected.

◆ FTM_SYNC_REINIT [4/5]

#define FTM_SYNC_REINIT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)

REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 0b0..FTM counter continues to count normally. 0b1..FTM counter is updated with its initial value when the selected trigger is detected.

◆ FTM_SYNC_REINIT [5/5]

#define FTM_SYNC_REINIT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)

REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 0b0..FTM counter continues to count normally. 0b1..FTM counter is updated with its initial value when the selected trigger is detected.

◆ FTM_SYNC_SWSYNC [1/5]

#define FTM_SYNC_SWSYNC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)

SWSYNC - PWM Synchronization Software Trigger 0b0..Software trigger is not selected. 0b1..Software trigger is selected.

◆ FTM_SYNC_SWSYNC [2/5]

#define FTM_SYNC_SWSYNC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)

SWSYNC - PWM Synchronization Software Trigger 0b0..Software trigger is not selected. 0b1..Software trigger is selected.

◆ FTM_SYNC_SWSYNC [3/5]

#define FTM_SYNC_SWSYNC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)

SWSYNC - PWM Synchronization Software Trigger 0b0..Software trigger is not selected. 0b1..Software trigger is selected.

◆ FTM_SYNC_SWSYNC [4/5]

#define FTM_SYNC_SWSYNC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)

SWSYNC - PWM Synchronization Software Trigger 0b0..Software trigger is not selected. 0b1..Software trigger is selected.

◆ FTM_SYNC_SWSYNC [5/5]

#define FTM_SYNC_SWSYNC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)

SWSYNC - PWM Synchronization Software Trigger 0b0..Software trigger is not selected. 0b1..Software trigger is selected.

◆ FTM_SYNC_SYNCHOM [1/5]

#define FTM_SYNC_SYNCHOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)

SYNCHOM - Output Mask Synchronization 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.

◆ FTM_SYNC_SYNCHOM [2/5]

#define FTM_SYNC_SYNCHOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)

SYNCHOM - Output Mask Synchronization 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.

◆ FTM_SYNC_SYNCHOM [3/5]

#define FTM_SYNC_SYNCHOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)

SYNCHOM - Output Mask Synchronization 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.

◆ FTM_SYNC_SYNCHOM [4/5]

#define FTM_SYNC_SYNCHOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)

SYNCHOM - Output Mask Synchronization 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.

◆ FTM_SYNC_SYNCHOM [5/5]

#define FTM_SYNC_SYNCHOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)

SYNCHOM - Output Mask Synchronization 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.

◆ FTM_SYNC_TRIG0 [1/5]

#define FTM_SYNC_TRIG0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)

TRIG0 - PWM Synchronization Hardware Trigger 0 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG0 [2/5]

#define FTM_SYNC_TRIG0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)

TRIG0 - PWM Synchronization Hardware Trigger 0 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG0 [3/5]

#define FTM_SYNC_TRIG0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)

TRIG0 - PWM Synchronization Hardware Trigger 0 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG0 [4/5]

#define FTM_SYNC_TRIG0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)

TRIG0 - PWM Synchronization Hardware Trigger 0 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG0 [5/5]

#define FTM_SYNC_TRIG0 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)

TRIG0 - PWM Synchronization Hardware Trigger 0 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG1 [1/5]

#define FTM_SYNC_TRIG1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)

TRIG1 - PWM Synchronization Hardware Trigger 1 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG1 [2/5]

#define FTM_SYNC_TRIG1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)

TRIG1 - PWM Synchronization Hardware Trigger 1 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG1 [3/5]

#define FTM_SYNC_TRIG1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)

TRIG1 - PWM Synchronization Hardware Trigger 1 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG1 [4/5]

#define FTM_SYNC_TRIG1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)

TRIG1 - PWM Synchronization Hardware Trigger 1 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG1 [5/5]

#define FTM_SYNC_TRIG1 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)

TRIG1 - PWM Synchronization Hardware Trigger 1 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG2 [1/5]

#define FTM_SYNC_TRIG2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)

TRIG2 - PWM Synchronization Hardware Trigger 2 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG2 [2/5]

#define FTM_SYNC_TRIG2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)

TRIG2 - PWM Synchronization Hardware Trigger 2 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG2 [3/5]

#define FTM_SYNC_TRIG2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)

TRIG2 - PWM Synchronization Hardware Trigger 2 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG2 [4/5]

#define FTM_SYNC_TRIG2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)

TRIG2 - PWM Synchronization Hardware Trigger 2 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNC_TRIG2 [5/5]

#define FTM_SYNC_TRIG2 ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)

TRIG2 - PWM Synchronization Hardware Trigger 2 0b0..Trigger is disabled. 0b1..Trigger is enabled.

◆ FTM_SYNCONF_CNTINC [1/5]

#define FTM_SYNCONF_CNTINC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)

CNTINC - CNTIN Register Synchronization 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock. 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_CNTINC [2/5]

#define FTM_SYNCONF_CNTINC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)

CNTINC - CNTIN Register Synchronization 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock. 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_CNTINC [3/5]

#define FTM_SYNCONF_CNTINC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)

CNTINC - CNTIN Register Synchronization 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock. 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_CNTINC [4/5]

#define FTM_SYNCONF_CNTINC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)

CNTINC - CNTIN Register Synchronization 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock. 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_CNTINC [5/5]

#define FTM_SYNCONF_CNTINC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)

CNTINC - CNTIN Register Synchronization 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock. 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_HWINVC [1/5]

#define FTM_SYNCONF_HWINVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)

HWINVC 0b0..A hardware trigger does not activate the INVCTRL register synchronization. 0b1..A hardware trigger activates the INVCTRL register synchronization.

◆ FTM_SYNCONF_HWINVC [2/5]

#define FTM_SYNCONF_HWINVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)

HWINVC 0b0..A hardware trigger does not activate the INVCTRL register synchronization. 0b1..A hardware trigger activates the INVCTRL register synchronization.

◆ FTM_SYNCONF_HWINVC [3/5]

#define FTM_SYNCONF_HWINVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)

HWINVC 0b0..A hardware trigger does not activate the INVCTRL register synchronization. 0b1..A hardware trigger activates the INVCTRL register synchronization.

◆ FTM_SYNCONF_HWINVC [4/5]

#define FTM_SYNCONF_HWINVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)

HWINVC 0b0..A hardware trigger does not activate the INVCTRL register synchronization. 0b1..A hardware trigger activates the INVCTRL register synchronization.

◆ FTM_SYNCONF_HWINVC [5/5]

#define FTM_SYNCONF_HWINVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)

HWINVC 0b0..A hardware trigger does not activate the INVCTRL register synchronization. 0b1..A hardware trigger activates the INVCTRL register synchronization.

◆ FTM_SYNCONF_HWOM [1/5]

#define FTM_SYNCONF_HWOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)

HWOM 0b0..A hardware trigger does not activate the OUTMASK register synchronization. 0b1..A hardware trigger activates the OUTMASK register synchronization.

◆ FTM_SYNCONF_HWOM [2/5]

#define FTM_SYNCONF_HWOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)

HWOM 0b0..A hardware trigger does not activate the OUTMASK register synchronization. 0b1..A hardware trigger activates the OUTMASK register synchronization.

◆ FTM_SYNCONF_HWOM [3/5]

#define FTM_SYNCONF_HWOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)

HWOM 0b0..A hardware trigger does not activate the OUTMASK register synchronization. 0b1..A hardware trigger activates the OUTMASK register synchronization.

◆ FTM_SYNCONF_HWOM [4/5]

#define FTM_SYNCONF_HWOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)

HWOM 0b0..A hardware trigger does not activate the OUTMASK register synchronization. 0b1..A hardware trigger activates the OUTMASK register synchronization.

◆ FTM_SYNCONF_HWOM [5/5]

#define FTM_SYNCONF_HWOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)

HWOM 0b0..A hardware trigger does not activate the OUTMASK register synchronization. 0b1..A hardware trigger activates the OUTMASK register synchronization.

◆ FTM_SYNCONF_HWRSTCNT [1/5]

#define FTM_SYNCONF_HWRSTCNT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)

HWRSTCNT 0b0..A hardware trigger does not activate the FTM counter synchronization. 0b1..A hardware trigger activates the FTM counter synchronization.

◆ FTM_SYNCONF_HWRSTCNT [2/5]

#define FTM_SYNCONF_HWRSTCNT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)

HWRSTCNT 0b0..A hardware trigger does not activate the FTM counter synchronization. 0b1..A hardware trigger activates the FTM counter synchronization.

◆ FTM_SYNCONF_HWRSTCNT [3/5]

#define FTM_SYNCONF_HWRSTCNT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)

HWRSTCNT 0b0..A hardware trigger does not activate the FTM counter synchronization. 0b1..A hardware trigger activates the FTM counter synchronization.

◆ FTM_SYNCONF_HWRSTCNT [4/5]

#define FTM_SYNCONF_HWRSTCNT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)

HWRSTCNT 0b0..A hardware trigger does not activate the FTM counter synchronization. 0b1..A hardware trigger activates the FTM counter synchronization.

◆ FTM_SYNCONF_HWRSTCNT [5/5]

#define FTM_SYNCONF_HWRSTCNT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)

HWRSTCNT 0b0..A hardware trigger does not activate the FTM counter synchronization. 0b1..A hardware trigger activates the FTM counter synchronization.

◆ FTM_SYNCONF_HWSOC [1/5]

#define FTM_SYNCONF_HWSOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)

HWSOC 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. 0b1..A hardware trigger activates the SWOCTRL register synchronization.

◆ FTM_SYNCONF_HWSOC [2/5]

#define FTM_SYNCONF_HWSOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)

HWSOC 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. 0b1..A hardware trigger activates the SWOCTRL register synchronization.

◆ FTM_SYNCONF_HWSOC [3/5]

#define FTM_SYNCONF_HWSOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)

HWSOC 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. 0b1..A hardware trigger activates the SWOCTRL register synchronization.

◆ FTM_SYNCONF_HWSOC [4/5]

#define FTM_SYNCONF_HWSOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)

HWSOC 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. 0b1..A hardware trigger activates the SWOCTRL register synchronization.

◆ FTM_SYNCONF_HWSOC [5/5]

#define FTM_SYNCONF_HWSOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)

HWSOC 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. 0b1..A hardware trigger activates the SWOCTRL register synchronization.

◆ FTM_SYNCONF_HWTRIGMODE [1/5]

#define FTM_SYNCONF_HWTRIGMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)

HWTRIGMODE - Hardware Trigger Mode 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.

◆ FTM_SYNCONF_HWTRIGMODE [2/5]

#define FTM_SYNCONF_HWTRIGMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)

HWTRIGMODE - Hardware Trigger Mode 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.

◆ FTM_SYNCONF_HWTRIGMODE [3/5]

#define FTM_SYNCONF_HWTRIGMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)

HWTRIGMODE - Hardware Trigger Mode 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.

◆ FTM_SYNCONF_HWTRIGMODE [4/5]

#define FTM_SYNCONF_HWTRIGMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)

HWTRIGMODE - Hardware Trigger Mode 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.

◆ FTM_SYNCONF_HWTRIGMODE [5/5]

#define FTM_SYNCONF_HWTRIGMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)

HWTRIGMODE - Hardware Trigger Mode 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.

◆ FTM_SYNCONF_HWWRBUF [1/5]

#define FTM_SYNCONF_HWWRBUF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)

HWWRBUF 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.

◆ FTM_SYNCONF_HWWRBUF [2/5]

#define FTM_SYNCONF_HWWRBUF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)

HWWRBUF 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.

◆ FTM_SYNCONF_HWWRBUF [3/5]

#define FTM_SYNCONF_HWWRBUF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)

HWWRBUF 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.

◆ FTM_SYNCONF_HWWRBUF [4/5]

#define FTM_SYNCONF_HWWRBUF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)

HWWRBUF 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.

◆ FTM_SYNCONF_HWWRBUF [5/5]

#define FTM_SYNCONF_HWWRBUF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)

HWWRBUF 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.

◆ FTM_SYNCONF_INVC [1/5]

#define FTM_SYNCONF_INVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)

INVC - INVCTRL Register Synchronization 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock. 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_INVC [2/5]

#define FTM_SYNCONF_INVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)

INVC - INVCTRL Register Synchronization 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock. 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_INVC [3/5]

#define FTM_SYNCONF_INVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)

INVC - INVCTRL Register Synchronization 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock. 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_INVC [4/5]

#define FTM_SYNCONF_INVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)

INVC - INVCTRL Register Synchronization 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock. 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_INVC [5/5]

#define FTM_SYNCONF_INVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)

INVC - INVCTRL Register Synchronization 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock. 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_SWINVC [1/5]

#define FTM_SYNCONF_SWINVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)

SWINVC 0b0..The software trigger does not activate the INVCTRL register synchronization. 0b1..The software trigger activates the INVCTRL register synchronization.

◆ FTM_SYNCONF_SWINVC [2/5]

#define FTM_SYNCONF_SWINVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)

SWINVC 0b0..The software trigger does not activate the INVCTRL register synchronization. 0b1..The software trigger activates the INVCTRL register synchronization.

◆ FTM_SYNCONF_SWINVC [3/5]

#define FTM_SYNCONF_SWINVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)

SWINVC 0b0..The software trigger does not activate the INVCTRL register synchronization. 0b1..The software trigger activates the INVCTRL register synchronization.

◆ FTM_SYNCONF_SWINVC [4/5]

#define FTM_SYNCONF_SWINVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)

SWINVC 0b0..The software trigger does not activate the INVCTRL register synchronization. 0b1..The software trigger activates the INVCTRL register synchronization.

◆ FTM_SYNCONF_SWINVC [5/5]

#define FTM_SYNCONF_SWINVC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)

SWINVC 0b0..The software trigger does not activate the INVCTRL register synchronization. 0b1..The software trigger activates the INVCTRL register synchronization.

◆ FTM_SYNCONF_SWOC [1/5]

#define FTM_SYNCONF_SWOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)

SWOC - SWOCTRL Register Synchronization 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock. 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_SWOC [2/5]

#define FTM_SYNCONF_SWOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)

SWOC - SWOCTRL Register Synchronization 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock. 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_SWOC [3/5]

#define FTM_SYNCONF_SWOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)

SWOC - SWOCTRL Register Synchronization 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock. 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_SWOC [4/5]

#define FTM_SYNCONF_SWOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)

SWOC - SWOCTRL Register Synchronization 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock. 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_SWOC [5/5]

#define FTM_SYNCONF_SWOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)

SWOC - SWOCTRL Register Synchronization 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock. 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.

◆ FTM_SYNCONF_SWOM [1/5]

#define FTM_SYNCONF_SWOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)

SWOM 0b0..The software trigger does not activate the OUTMASK register synchronization. 0b1..The software trigger activates the OUTMASK register synchronization.

◆ FTM_SYNCONF_SWOM [2/5]

#define FTM_SYNCONF_SWOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)

SWOM 0b0..The software trigger does not activate the OUTMASK register synchronization. 0b1..The software trigger activates the OUTMASK register synchronization.

◆ FTM_SYNCONF_SWOM [3/5]

#define FTM_SYNCONF_SWOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)

SWOM 0b0..The software trigger does not activate the OUTMASK register synchronization. 0b1..The software trigger activates the OUTMASK register synchronization.

◆ FTM_SYNCONF_SWOM [4/5]

#define FTM_SYNCONF_SWOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)

SWOM 0b0..The software trigger does not activate the OUTMASK register synchronization. 0b1..The software trigger activates the OUTMASK register synchronization.

◆ FTM_SYNCONF_SWOM [5/5]

#define FTM_SYNCONF_SWOM ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)

SWOM 0b0..The software trigger does not activate the OUTMASK register synchronization. 0b1..The software trigger activates the OUTMASK register synchronization.

◆ FTM_SYNCONF_SWRSTCNT [1/5]

#define FTM_SYNCONF_SWRSTCNT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)

SWRSTCNT 0b0..The software trigger does not activate the FTM counter synchronization. 0b1..The software trigger activates the FTM counter synchronization.

◆ FTM_SYNCONF_SWRSTCNT [2/5]

#define FTM_SYNCONF_SWRSTCNT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)

SWRSTCNT 0b0..The software trigger does not activate the FTM counter synchronization. 0b1..The software trigger activates the FTM counter synchronization.

◆ FTM_SYNCONF_SWRSTCNT [3/5]

#define FTM_SYNCONF_SWRSTCNT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)

SWRSTCNT 0b0..The software trigger does not activate the FTM counter synchronization. 0b1..The software trigger activates the FTM counter synchronization.

◆ FTM_SYNCONF_SWRSTCNT [4/5]

#define FTM_SYNCONF_SWRSTCNT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)

SWRSTCNT 0b0..The software trigger does not activate the FTM counter synchronization. 0b1..The software trigger activates the FTM counter synchronization.

◆ FTM_SYNCONF_SWRSTCNT [5/5]

#define FTM_SYNCONF_SWRSTCNT ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)

SWRSTCNT 0b0..The software trigger does not activate the FTM counter synchronization. 0b1..The software trigger activates the FTM counter synchronization.

◆ FTM_SYNCONF_SWSOC [1/5]

#define FTM_SYNCONF_SWSOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)

SWSOC 0b0..The software trigger does not activate the SWOCTRL register synchronization. 0b1..The software trigger activates the SWOCTRL register synchronization.

◆ FTM_SYNCONF_SWSOC [2/5]

#define FTM_SYNCONF_SWSOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)

SWSOC 0b0..The software trigger does not activate the SWOCTRL register synchronization. 0b1..The software trigger activates the SWOCTRL register synchronization.

◆ FTM_SYNCONF_SWSOC [3/5]

#define FTM_SYNCONF_SWSOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)

SWSOC 0b0..The software trigger does not activate the SWOCTRL register synchronization. 0b1..The software trigger activates the SWOCTRL register synchronization.

◆ FTM_SYNCONF_SWSOC [4/5]

#define FTM_SYNCONF_SWSOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)

SWSOC 0b0..The software trigger does not activate the SWOCTRL register synchronization. 0b1..The software trigger activates the SWOCTRL register synchronization.

◆ FTM_SYNCONF_SWSOC [5/5]

#define FTM_SYNCONF_SWSOC ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)

SWSOC 0b0..The software trigger does not activate the SWOCTRL register synchronization. 0b1..The software trigger activates the SWOCTRL register synchronization.

◆ FTM_SYNCONF_SWWRBUF [1/5]

#define FTM_SYNCONF_SWWRBUF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)

SWWRBUF 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization. 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.

◆ FTM_SYNCONF_SWWRBUF [2/5]

#define FTM_SYNCONF_SWWRBUF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)

SWWRBUF 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization. 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.

◆ FTM_SYNCONF_SWWRBUF [3/5]

#define FTM_SYNCONF_SWWRBUF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)

SWWRBUF 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization. 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.

◆ FTM_SYNCONF_SWWRBUF [4/5]

#define FTM_SYNCONF_SWWRBUF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)

SWWRBUF 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization. 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.

◆ FTM_SYNCONF_SWWRBUF [5/5]

#define FTM_SYNCONF_SWWRBUF ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)

SWWRBUF 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization. 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.

◆ FTM_SYNCONF_SYNCMODE [1/5]

#define FTM_SYNCONF_SYNCMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)

SYNCMODE - Synchronization Mode 0b0..Legacy PWM synchronization is selected. 0b1..Enhanced PWM synchronization is selected.

◆ FTM_SYNCONF_SYNCMODE [2/5]

#define FTM_SYNCONF_SYNCMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)

SYNCMODE - Synchronization Mode 0b0..Legacy PWM synchronization is selected. 0b1..Enhanced PWM synchronization is selected.

◆ FTM_SYNCONF_SYNCMODE [3/5]

#define FTM_SYNCONF_SYNCMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)

SYNCMODE - Synchronization Mode 0b0..Legacy PWM synchronization is selected. 0b1..Enhanced PWM synchronization is selected.

◆ FTM_SYNCONF_SYNCMODE [4/5]

#define FTM_SYNCONF_SYNCMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)

SYNCMODE - Synchronization Mode 0b0..Legacy PWM synchronization is selected. 0b1..Enhanced PWM synchronization is selected.

◆ FTM_SYNCONF_SYNCMODE [5/5]

#define FTM_SYNCONF_SYNCMODE ( x)    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)

SYNCMODE - Synchronization Mode 0b0..Legacy PWM synchronization is selected. 0b1..Enhanced PWM synchronization is selected.